TLF12501 [INFINEON]
current sensing, current & temperture reporting, over-current protection & flag, over-temperature protection & shutdown, high-side short detection & flag, bootstrap under-voltage protection, VDRV under-voltage lockout, 3.3V tri-state PWM-input, auto-sleep- & deep-sleep-mode;
| 型号： | TLF12501 |
| 厂家： | 
Infineon |
| 描述： | current sensing, current & temperture reporting, over-current protection & flag, over-temperature protection & shutdown, high-side short detection & flag, bootstrap under-voltage protection, VDRV under-voltage lockout, 3.3V tri-state PWM-input, auto-sleep- & deep-sleep-mode |
| 文件： | 总22页 (文件大小：950K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLF12501 Automotive 60A OptiMOSTM Power Stage
1
Description
•
Qualified for automotive applications requiring AEC-Q100 Rev H Grade 1 Compliance
•
High frequency, low profile DC-DC converters
The TLF12501 integrated power-stage contains a low quiescent current synchronous buck gate-driver IC which is
co-packed with control and synchronous MOSFETs. The package is optimized for PCB layout, heat transfer,
driver/MOSFET control timing, and minimal switch node ringing when layout guidelines are followed. The paired
gate driver and MOSFET combination enables higher efficiency at lower output voltages required by cutting edge
CPU, GPU and DDR memory designs.
The internal MOSFET sensing achieves superior current sense accuracy vs. best-in-class controller based Inductor
DCR sense methods.
Protection includes IC temperature reporting and over temperature protection feature (OTP with thermal
shutdown), cycle-by-cycle over-current protection (OCP), control MOSFET short detection (HSS - High side short
detection), VDRV and bootstrap under-voltage protection. The TLF12501 also features "refreshing" of bootstrap
capacitor to prevent the bootstrap capacitor from over-discharging.
Operation of up to 2 MHz switching frequency enables high performance transient response, allowing
miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading
efficiency.
Features
•
•
•
•
•
•
•
•
•
•
•
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•
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Integrated driver, control MOSFET Q1 and synchronous MOSFET Q2
On-chip MOSFET Current sensing and reporting at 5uA/A.
Input voltage (VIN) range of 4.25 V to 16 V
VCC and VDRV supply of 4.25 V to 5.5 V
Output voltage range from 0.225 V up to 5.5 V at VIN = 12 V
Output current capability of 60 A
Operation up to 2 MHz
VDRV under-voltage lockout (UVLO)
Bootstrap under-voltage protection
8mV / °C temperature analog output
Over-temperature protection and thermal shutdown
Cycle-by-cycle over current Protection (OCP) and flag
Control MOSFET short (HSS) detection and flag
Auto-replenishment on bootstrap capacitor
Compatible with 3.3 V tri-state PWM Input
Auto SLEEP mode after 20 µs of PWM Tri-state (1.6 mA typ)
DEEP SLEEP mode for power saving via EN= low (32 µA typ)
Small 5 mm x 6 mm x 0.9 mm PQFN package
Lead free RoHS compliant package
Compliant to automotive AEC-Q100 Rev H Grade 1 requirements
Datasheet
Please read the Important Notice and Warnings at the end of this document
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Table 1
Product Identification
Temp Range
Part Number
TLF12501
Package
Marking
PQFN 5 mm x 6 mm
TLF12501
-40 to 125C
Figure 1
Picture of the Product
1.1
Pinout
`
Figure 2
Pinout, Numbering and Name of Pins (transparent top view)
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TLF12501 Automotive 60A Smart Power Stage
2
Pinout, Numbering and Name of Pins ꢀtransparent top viewꢁ
Table 2
I/O Signals
Pin No. Name
Pin Type Buffer Type Function
1
IMONREF
I/O
Analog
This pin provides a common-mode voltage reference for
the IMON information. This pin may be tied to a fixed
voltage such as bias rails of a PWM controller or left
floating.
11-18,
23, 38
SW
O
Analog
Switching node of synchronous buck converter.
30
31
PHASE
BOOT
I
I
Analog
Analog
Switching node. For Bootstrap capacitor connection only.
Bootstrap capacitor connection. Connect an X7R ceramic
capacitor with value between 0.22 µF to 0.56 µF from
BOOT to PHASE pin. Recommended value is 0.47µF. The
bootstrap capacitor provides the charge to turn on the
control MOSFET. For VIN > 13.2 V, a 2-Ω bootstrap resistor
in series with the capacitor is required to help reduce SW
ringing and EMI.
32
33
PWM
EN
I/O
I
+3.3 V logic ꢀ.ꢀ V 5802c 5eve5 PWM 27put. PWM 27putꢁ ꢂH201ꢃ tur7s
c87tr85 MOSFET 87ꢄ ꢂTr2-stateꢃ tur7s both MOSFETs off;
ꢂL8wꢃ tur7s t1e sy7c1r878us MOSFET 87.
+3.3 V logic Pulling EN high enables the driver; pulling EN low disables
the driver and enters ultra-low quiescent current mode.
Floating this pin is not recommended, however a pull-
down is embedded to keep the driver off if the pin is
floating. Pin is VCC tolerant.
34
36
TMON /
FAULT
O
O
Analog
The voltage at this pin is defined by the equation
8mV * (Celsius Temperature) + 0.6 V. This pin will be
pulled up to 3.3 V under severe over-temperature, over-
current, HSS or bootstrap under-voltage condition.
IMON
Analog
Sensed current output signal referenced to the IMONREF
pin through external resistor. V (IMON – IMONREF) voltage
across that resistor represents current information.
Table 3
Pin No.
3
Power Supply
Name Pin Type Buffer Type Function
VCC
POWER
–
–
–
Bias voltage for control logic. Connect a 1 µF cap between
VCC and AGND. VCC should be connected to +5 V power
supply.
4
VDRV POWER
The supply of gate driver. Connect a 1 µF cap between
VDRV and PGND. VDRV should be connected to +5 V power
supply.
24-29
VIN
POWER
4.25 V to 16 V high current input voltage connection.
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Table 4
Pin No.
2
Ground Pins
Name Pin Type Buffer Type Function
AGND GND
PGND GND
PGND GND
PGND GND
–
–
–
–
Signal ground. All interface signals are referenced to this
pin.
5-10, 37
19-22
35
Power ground. It is also the power ground of the
synchronous MOSFET.
Power ground. It is also the power ground of the
synchronous MOSFET.
Power ground. It is also the power ground of the
synchronous MOSFET.
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3
Block Diagram
Figure 3 Simplied Block Diagram
Datasheet
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TLF12501 Automotive 60A Smart Power Stage
4
Electrical Specification
4.1
Absolute Maximum Ratings
Note: TA = 25 °C
Stresses above those listed in Table 5 ꢂAbs85ute Max26u6 Rat270sꢃ 6ay cause per6a7e7t da6a0e t8 t1e device.
These are absolute stress ratings only and operation of the device is not implied or recommended at these or any
other conditions in excess of those given in the operational sections of this specification. Exposure over values of
the recommended ratings for extended periods may adversely affect the operation and reliability of the device.
Table 5
Absolute Maximum Ratings
Symbol
Parameter
Values
Unit Note / Test
Condition
Min.
0.1
Typ. Max.
fSW
Frequency of the PWM input
Maximum average load current
Input Voltage
–
–
–
–
–
2
MHz
A
IOUT
VIN
–
60
25
6.5
6.5
-0.30
-0.3
-0.3
V
V
V
Pin VIN
VCC
VDRV
Logic supply voltage
Pin VCC
Pin VDRV
High and low-side driver
voltage
Switch node voltage
VSW (DC)
-1
–
–
–
–
–
–
25
V
V
V
Pin SW
VSW (AC)
-8 for 10ns
32 for 2ns
25
PHASE voltage
VPHASE (DC)
VPHASE (AC)
-1
Pin PHASE
-8 for 10ns
-1
32 for 2ns
25
VVIN-PHASE(DC)
VIN-PHASE Voltage
VVIN-PHASE(AC)
Below -5V
for 5ns
32 for 1ns
BOOT voltage
VBOOT (DC)
-0.3
–
29
V
Pin BOOT
VBOOT (AC)
--
–
30 for 10ns
VBOOT-PHASE
-0.3
6.5V (DC),
7.5V for 3ns
6.5
–
VEN
EN voltage
-0.3
-0.3
-0.3
–
–
–
V
V
V
Pin EN
VPWM
VTMON
PWM voltage
TMON voltage
3.6
3.6
Pin PWM
Pin TMON /
FAULT
VIMON
VIMONREF
TJmax
IMON voltage
-0.3
-0.3
-40
-55
–
–
–
–
3.6
V
Pin IMON
IMONREF voltage
Junction temperature
Storage temperature
3.6
V
Pin IMONREF
150
150
C
C
TSTG
–
Note: All rated voltages are relative to voltages on the AGND and PGND pins unless otherwise specified.
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4.2
Thermal Characteristics
Table 6
Thermal Characteristics
Symbol
Parameter
Values
Unit
Note / Test Condition
Min.
Typ. Max.
K/W
θJC_PCB
Thermal resistance-Junction to
PCB
–
1.5
–
θJC_Top
Thermal resistance-Junction to
top of package
–
–
17.8
28.4
–
–
–
Note
Thermal resistance to ambient θJA
–
Note: Thermal Resistance (θJA) is measured with the component mounted on a high effective thermal conductivity test board in free air.
4.3
Recommended Operating Conditions
Table 7
Recommended Operating Conditions
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
4.25
4.25
4.25
100
–
Typ.
Max.
16
VIN
Input voltage
–
–
–
–
–
–
–
–
V
–
VDRV
VCC
MOSFET driver voltage
Logic supply voltage
Frequency of the PWM
EN voltage
5.5
–
5.5
–
fSW
2000
5.5
kHz
V
-
VEN
Pin EN
Pin PWM
PWM voltage
VPWM
VIMON_CM
TjOP
–
3.6
V
Current Sense reference voltage
Junction temperature
1.1
-40
1.9
V
+125
°C
4.4
Electrical Characteristics
Note: VDRV = VCC = 5 V, TJ = 25 °C, VIMONREF = 1.2V
Table 8
Voltage Supply, Biasing Current
Parameter
Symbol
Values
Typ. Max.
Unit
Note / Test Condition
Min.
3.9
UVLO VDRV rising
UVLO VDRV falling
VUVLO_R
VUVLO_F
VUVBOOT_R
4.05
3.85
3.85
4.2
4.0
4.0
V
3.7
3.7
Bootstrap Under-voltage
rising threshold
Bootstrap Under-voltage
falling threshold
VUVBOOT_F 3.65
3.82
4.0
EN = H, fSW = 600 kHz, D=15%
EN = L
Driver current
Supply Current
VIN Current
IVDRV
–
29
2.5
8
-
mA
1.4
3.5
18
–
4.2
9.5
42
5
µA
mA
µA
µA
EN = H, fSW = 600 kHz, D=15%
EN = L
IVcc
30
–
No switching
IVIN
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TLF12501 Automotive 60A Smart Power Stage
Table 9
Current Sense
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ. Max.
IMON IMON Voltage
range
VIMON
0.8
–
2.35
V
V
DC + AC components
IMON/IMONREF
reference voltage
range
VIMON_CM
1.1
–
–
1.9
Reference Voltage connected
externally for the current sense
signal
Current sense
gain
Acs
5
1
–
µA/A
IMON Gain
resistor range
Resistor to be connected
between IMON and IMONREF. For
5mV/A, recommended 1kΩ RIMON
RIMON
-
-
kΩ
Leakage Current
IOUT = 0A, VIMON=1.2V
PWM in tri-state
ILeak
-2
-3
0
0
2
3
µA
µA
Zero current
offset
Ioffset
Corresponds to 3 mV at 5 mV/A.
(RIMON = 1 kΩꢅ, device in
regulation
Note 1
Accuracy at
TJ = -5 to 125°C
-3.0
-0.5
–
–
3.0
0.5
%
A
for 25A < IOUT < IOCP_TH
for -25A < IOUT < 25A Note 1
VCC = VDRV = 5 V ±
10 %
Table 10
Temperature Sense and Fault Communication
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ. Max.
TMON Temperature
ATMPGAIN
7.84
8.0
8.16
mV/°C
mV
ꢆꢇ°C ≤ TJ ≤ ꢈꢆꢇ°C, Note 1
/
Sense Slope
FAULT
Temperature
Sense Offset
Voltage
VTMPOFFSE
T
784
800
816
TJ = 25°C, 0.6 V + 8 mV/°C * TJ
TMON / FAULT
Source Current
ITMONSRC
ITMONSNK
400
26
500 650
µA
µA
TMON / FAULT pulled low
TMON / FAULT pulled high
TMON / FAULT
Sink Current
32
3.3
–
40
ITMON/FAULT = 5 mA and under Over-
Temperature, Over-Current, bootstrap
under-voltage or HSS Fault
Fault mode
Active High
VTFLTHIGH
2.6
–
3.6
0.35
–
V
V
TMON / FAULT
LowNote 1
VTFLTLOW
No Fault, VDRV < VUVLO1_R
TMON / FAULT
pull down
resistance
RPULLDN_T
MON
–
150
kΩ
No Fault, VDRV < VUVLO1_R
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TLF12501 Automotive 60A Smart Power Stage
Table 11
Other Logic Functions, Inputs/Outputs And Thresholds
Parameter
Symbol
Values
Unit
Note / Test Condition
Min. Typ. Max.
EN
Enable Power-on
Delay
PWM=0. Measured from EN rising
edge to VSW> 1 V.
tEN_ondelay
tEN_offdelay
RPULLDN_EN
VEN_H
–
–
27
-
35
1
μs
μs
kΩ
V
Enable Power-off
Delay
PWM=0. Measured from EN falling
edge to VSW < 0.9* VIN.
Internal Pull
down Resistance
–
280
–
–
When EN is floating
Input High
Voltage
2.0
–
–
Input Low
Voltage
–
VEN_L
0.8
–
V
PWM
PWM Input High
Threshold
PWM Low or Tri-state to High
PWM High or Tri-state to Low
VIH
2.4
–
–
V
PWM Input Low
Threshold
VIL
–
0.8
–
V
PWM Hysteresis
Active to Tri-state or Tri-state to
Active
IPWM_HYS
–
40
mV
PWM Input Tri-
State Floating
Voltage
PWM Input Floating
VPWM_TRI
1.4
1.2
–
1.6
–
1.8
2.0
–
V
V
Tri-state Window VPWM_S
PWM Input
Equivalent Pull-
up Resistance
VPWM = 0 V
RPWM_PU
20
kΩ
PWM Input
VPWM = 3.3 V
Equivalent Pull-
RPWM_PD
–
50
–
kΩ
down Resistance
Bootstrap
Diode
Forward Voltage VFWD
-
-
620
-
-
mV
mV
kΩ
I(BOOT) = 5mA
SW
Bleeding
Resistor
SW Floating
Voltage
VSW_FLOAT
RSW_PULL_DOWN
VPWM = 1.6 V or Tri-state, VCC =
VDRV = 5V
200
SW Pull Down
Resistance
0.85 1.125 1.5
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Table 12
Protection
Parameter
Values
Unit Note / Test Condition
Symbol
Min. Typ. Max.
OTP
Over Temp Rising
Threshold
TMON/FAULT pulled up high Note
TRISE
TFALL
–
–
155
143
560
150
90
–
–
°C
1
Over Temp Falling
Threshold
Note 1
°C TMON/FAULT released
HSS
High-side MOSFET VHSS_TH
FAULT Short Threshold
VSW – VPGND
–
–
mV
TMON/FAULT Delay THSS_DEL
After VHSS_TH is detected and
ns
–
–
TMON/FAULT is pulled high
OCP
Over-Current
Threshold
IOCP_TH
80
10
100
–
A
Cycl PWM High-Low Cycles to
Over-Current Delay TOCP_DEL
–
e
TMON/FAULT is pulled high
Table 13
Timing Characteristics
Symbol
Parameter
Values
Min. Typ. Max.
Unit Note / Test Condition
PWM High Propagation Delay
PWM Low Propagation Delay
Measured from PWM rising edge
to VSW starts to rise
tPWM_HI_DELAY
tPWM_LO_DELAY
tTRI_HI_DELAY
–
–
48
45
53
56
75
17
–
–
ns
Measured from PWM falling
edge to VSW starts to fall
ns
Tri-State to High Propagation
Delay
PWM Tri-state to High transition
to VSW > 1 V
–
–
ns
Tri-State Hold Off Time
PWM Low to Tri-state transition
40
76
to SW starts to fall Note 1
ns
tTriHold
PWM High to Tri-state transition
to SW starts to fall Note 1
Minimum Recognized PWM
Pulse Width Note 1
tMinPWM
–
–
–
–
ns
Minimum output pulse width
Positive load current.PWM
tOnSWmin
18
ns pulses shorter than tOnSWmin will
Note 1
be extended to tOnSWmin
.
Notes
1. Guaranteed by design but not tested in production
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TLF12501 Automotive 60A Smart Power Stage
5
Typical operating conditions
Single Phase Circuit of Figure 18, VIN = 12 V, VOUT = ꢉ.ꢊ V, ƒSW = 500KHz, L = 100 nH, VCC = VDRV = 5 V, TAMBIENT = 25
°C, RIMON =1kΩ ꢉ.ꢈ%, no heat sink, no air flow, 8-5ayer PCB b8ard 8f ꢀ.ꢋꢃ ꢌLꢅ x ꢆ.ꢍꢃ ꢌWꢅ, no PWM controller loss, no
inductor loss, unless specified otherwise.
Figure 4
Power stage Efficiency
Figure 5
Power stage Loss
Figure 6
VCC / VDRV current vs Frequency
Figure 7
Thermal derating
Figure 8
Datasheet
Current sense gain variation vs Frequency
Figure 9 Current sense output
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TLF12501 Automotive 60A Smart Power Stage
Single Phase Circuit of Figure 18, VIN = 12 V, VOUT = 0.ꢊ V, ƒSW = 500KHz, L = 100 nH, VCC = VDRV = 5 V, TAMBIENT = 25
°C, RIMON = 1kΩ ꢉ.ꢈ%, no heat sink, no air flow, 8-5ayer PCB b8ard 8f ꢀ.ꢋꢃꢌLꢅ x ꢆ.ꢍꢃꢌWꢅ, no PWM controller loss, no
inductor loss, unless specified otherwise.
Figure 10 Current sense gain vs Reference Voltage
Figure 11 Current sense gain variation vs VCC/VDRV
Figure 12 Current sense gain variation vs Vout
Figure 13 Current sense gain variation vs Temperature
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TLF12501 Automotive 60A Smart Power Stage
6
Theory of Operation
6.1
Description
The TLF12501 contains an improved high speed MOSFET driver optimized to drive a pair of co-packaged high-side
and low-side Optimos MOSFETs at frequency up to 2 MHz. DC-DC controllers using traditional current sense
methods like DCR sensing and Rdson sensing typically have limitations. DCR current sensing is sensitive to
temperature changes of the inductor and needs temperature compensation either implemented externally using
a thermo-couple or inside the power stage. Rdson current sensing, on the other hand, is not dependent on the
inductor but there is a temperature co-efficient associated with the MOSFET rdson. Besides, it is difficult to
implement rdson current sensing for high-side MOSFET which is therefore replaced by emulated current while the
low-side current is sensed across the MOSFET. With the advanced current-mirror sensing in TLF12501, all these
limitations are eliminated while achieving superior accuracy. Current on both high-side as well as low-side
MOSFET is mirrored on a sense MOSFET which is a part of the main MOSFET device, and hence comes with an
inherent temperature compensation without the need for an additional circuitry. Real current-sensing on both
MOSFET ensures that the system is always monitoring the real output current and can immediately react to any
critical events like load step or over-current fault.
The TLF12501 reports accurate temperature with the gain of 8 mV / °C, which helps the system to actively monitor
the temperature in real time. Temperature outputs from multiple power stages can be connected together to
report the highest temperature to Infineon’s d202ta5 PWM c87tr855er.
The TLF12501 PWM input is compatible with industry standard 3.3V PWM input with tri-state.
The TLF12501 can enable Body-Braking mode by responding to PWM tri-state signals sent from the controller,
quickly disabling both MOSFETs in the power stage in order to enhance transient performance or provide a high
impedance output.
The TLF12501 supports diode emulation mode through the PWM tri-state s207a5. C87tr855ed by I7f27e87’s d202ta5
PWM controller, the PWM tri-state signal will force the low-side FET to be off when the inductor current is about to
go negative. The light-load efficiency then can be increased by preventing conduction loss caused by negative
inductor current.
The TLF12501 also supports deep-sleep power saving mode. When in deep-sleep mode, the driver will disable
most of the function circuitry to greatly reduce power consumption.
The TLF12501 features a full-range of protection, including VCC/VDRV Under-Voltage-Lockout (UVLO), thermal
shutdown against an internal over-temperature condition, phase fault detection of a shorted high-side MOSFET,
and cycle-by-cycle over-current protection due to an overload condition or saturated output inductor.
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TLF12501 Automotive 60A Smart Power Stage
The TLF12501 also features internal protection circuitry to automatically replenish the voltage across the
bootstrap capacitor. It avoids the gradual depletion of capacitor energy when the power stage sits in tri-state for
a long period of time.
6.2
Sleep Modes
When EN is pulled low, the power stage enters deep-sleep mode. The gate driver circuitry will be turned off
immediately and most of the logic circuitry will be shut down to reduce the bias current to less than 32 µA. The
IMON output will be shorted to IMONREF in deep sleep mode.
When EN toggles from low to high, the power stage will be active and able to accept PWM signals after a delay of
17 µs.
6.3
Current Sensing and Reporting
The TLF12501 features a very accurate current mirror architecture on both high-side as well as low-side MOSFET,
thus reporting the real time current information. The current information is reported using the IMON pin. The
reported current is in the form of current output with the gain of 5µA /A from the IMON pin. In order to convert this
into voltage, a 1kΩ, 0.1% resistor is recommended at the IMON pin and placed close to the PWM controller. A
differential voltage signal from this resistor is connected to the controller as the reported current information.
Note that for accurate current reporting, it is important that the other end of the resistor cannot be left floating.
The converted voltage signal at the controller side has an effective gain of 5mV/A i.e. for every 1 A load, the
controller will read 5mV from the power stage. The current-output differential signal from the power stage
provides excellent noise immunity to the reported current information.
6.4
Advanced Fault reporting
TLF12501 uses TMON / FAULT pin for reporting all types of faults detected. Since typical multiphase applications
connect the TMON / FAULT signal from all the phases in a particular loop into a wired OR connection, the system
cannot distinguish the faulty phase and the type of fault occurred. This is resolved by using advanced fault
reporting in TLF12501 which uses a combination of TMON / FAULT and IMON signals to identify the fault. Since the
IMON is separately connected from each phase to the controller, it provides phase-specific information in the
event of a fault. Appropriate IMON response to each fault is explained in the corresponding fault sub-sections
further. A summary of fault reporting is given in the Table 14 at the end of Section 6.
6.5
VDRV Under-voltage Lock-out ꢀUVLOꢁ
TLF12501 features a VDRV under-voltage lock-out fault circuitry that monitors the VDRV voltage actively. As shown
in Table 15, this is a non-catastrophic fault and the TMON/FAULT pin is pulled low with a weak pull down as long
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TLF12501 Automotive 60A Smart Power Stage
as the VDRV voltage is below the UVLO threshold. If the power stage has not started up, the power stage PWM pin
is also pulled down to 0V with a weak pull down. This can be monitored by the PWM controller as a signal from
the power stage indicating that it is not ready yet for power up. As soon as VDRV voltage is above the UVLO
threshold, the PWM pin is at tri state instead of 0V, this indicating the controller that it is OK to send the PWM
signals.
Once the powerstage is in normal operation, if then it encounters a VDRV UVLO condition, the power stage stops
switching, and both TMON and IMON pins are pulled down to 0V. If there are multiple phases connected in the
same loop, the TMON pin voltage, being connected to other power stage TMON pins, will continue reporting the
highest power stage temperature. But the controller can still detect IMON pin voltage to be 0V (IMON –IMONREF =
-IMONREF, as seen by the controller), and thus identify this faulty phase. Since TMON pin is not pulled high, but
continues reporting the temperature, this can be distinguished from a BOOT UVLO condition as shown in Table
14.
6.6
Temperature Reporting and Over-temperature protection
An internal temperature-sense circuit monitors the temperature of the TLF12501. The sensed temperature is
reported at the TMON/FAULT pin with a linear voltage slope of 8mV/°C and a 0.6V offset at 0°C, as shown in
equation (1).
VTMON/FAULT (V)=0.6V +0.008V / C x T (C)
………………………………………….……… ꢌꢈꢅ
j
The TMON/FAULT pin also serves as a FAULT pin that is pulled to 3.3V in case of any catastrophic faults and is
pulled down to 0V in case of any non-catastrophic faults. When there is no fault, it continues reporting temperature
as long as the VCC supply is connected to a voltage in the recommended operating range. For a junction
temperature below -25ᵒC, the TMON voltage is clamped to 0.4V to avoid false triggering of VDRV under-voltage.
Once the temperature rises above the OTP rising threshold (155 °C), the TMON/FAULT output will be pulled high
immediately, the driver will stop switching and stop responding to the PWM signal input from the controller. Both
high-side and low-side MOSFET are turned off. The TMON/FAULT will remain high until temperature falls below
the falling threshold (143 °C). As soon as TMON is pulled high during OTP, the IMON is internally shorted to
IMONREF, thus identifying the faulty phase and occurrence of OTP to the system.
6.7
Over-current Protection and Flag
This feature protects the power stage from self-destruction from repetitive high current events such as saturated
inductors due to poor component selection or by incorrectly optimized control loops. These high current events
could eventually lead to a shorted high-side MOSFET failure.
Datasheet
15
Rev2.11
2021-10-05
Restricted
TLF12501 Automotive 60A Smart Power Stage
With cycle-by-cycle self-preservation, the current is monitored every cycle. If the over-current threshold (default
90 A) has been exceeded, the PWM high pulse will be truncated so that the inductor current is allowed to relax.
When TLF12501 detects 10 consecutive PWM cycle over-current events, the TMON/FAULT pin is flagged high to
27d2cate t1e c87tr855er 8f t1e fau5t. T1e TMON/FAULT f5a00ed ꢂ1201ꢃ a5870 w2t1 IMON 27f8r6at287 cr8ss270 t1e
over-current threshold helps the controller identify the faulty phase that caused OC. Note the PWM pu5se ꢂ87-
t26eꢃ s18u5d be at 5east ꢇꢉ7s f8r accurate fu7ct287270 8ver-current protection.
6.8
Bootstrap Capacitor Under-Voltage
TLF12501 features a bootstrap capacitor under-voltage circuitry that detects a missing bootstrap capacitor before
powering up or a damaged bootstrap capacitor during normal operation. Once bootstrap capacitor under-voltage
is determined, the TMON/FAULT pin will be pulled high to report a catastrophic fault to the PWM controller. At the
same time, IMON pin is pulled to 0V or GND voltage, thus effectively indicating a negative IMONREF voltage
differential between IMON and IMONREF pins at the controller.
Table 14
Advanced Fault Reporting
Datasheet
16
Rev2.11
2021-10-05
Restricted
TLF12501 Automotive 60A Smart Power Stage
Fault
Severity
Level
Type of Fault
Power stage PWM
Response
Power
stage IMON
Response
Powerstage TMON Recommended
Response
Controller
Identification
Criteria
VDRV UVLO
(power-up)
Weak pull down to 0V = IMONREF Weak pull down to
TMON < 2V,
PWM < 0.8V
0V
(PWM pin voltage can
be driven by
controller, no
switching on
powerstage)
(or VTMON from other
power stages in
same loop)
VDRV UVLO
Weak pull down to 0V
= 0V
Weak pull down to
0V
TMON < 2V,
IMON < 0.4V
(normal operation) (PWM pin voltage can
be driven by
controller, no
switching on
powerstage)
(or VTMON from other
power stages in
same loop)
OTP
OCP
Power stage stops
switching until OTP
clears
=IMONREF
= 3.3V
= 3.3V
TMON > 2.6V,
IMON=IMONREF,
1V < IMON < 2V
Power stage continues Continues
TMON > 2.6V,
IMON-IMONREF
> CTRL_OCP,
IMON < 2.6V
responding to PWM
signal from controller.
Truncates high side
pulse until powerstage
is in OCP.
reporting
current
(10 events without 3
consecutive good
cycles)
HSS (1st event)
Power stage continues
responding to PWM
signal from controller.
= 3.3V
= 3.3V
= 3.3V
TMON > 2.6V,
IMON > 2.6V
(latched)
BOOT UVLO (10
events without 3
consecutive good
cycles)
Power stage continues
responding to PWM
signal from controller.
= 0V
TMON > 2.6V,
IMON < 0.4V
(latched)
Datasheet
17
Rev2.11
2021-10-05
Restricted
TLF12501 Automotive 60A Smart Power Stage
7
Application Diagram
12V
CVIN1
L1
Cboot1
PHASE
TMON/FLT
PWM
V_CPU_L1
SW
PWM1
ISEN1
L
VSEN1
VRTN2
TLF12501
O
A
D
IMON
IMONREF
EN
1K
PGND
3.3V
VCC
1uF
CVCC1
CVDRV1
Multiphase
PWM
Controller
+5V
VRDY1
12V
VRDY2
CVIN2
L2
Cboot2
PHASE
RVIN1_1
VIN_1
VINSEN1
TMON/FLT
PWM
13K
SW
PWM2
ISEN2
1K
10nF
RVIN1_2
TLF12501
IMON
1K
1K
1K
IMONREF
EN
PGND
CVCC2
CVDRV2
SM_DAT
I2C Bus
SM_CLK
.
.
.
.
.
.
+5V
SM_ALERT#
12V
CVIN6
Cboot6
PHASE
SV_ALERT#
SV_DAT
VCCIO
CPU Serial
Bus
TMON/FLT
PWM
TSEN1
PWM6
ISEN6
L6
SV_CLK
SW
1K
TLF12501
IMON
VRHOT_ICRIT#
IMONREF
EN
PGND
VR_EN1
VR_EN2
From
System
CVCC6
CVDRV6
+5V
PWR_IN_ALERT#
12V
CVIN1_L2
L_L2
Cboot1_L2
PHASE
TMON/FLT
PWM
TSEN2
SW
V_CPU_L2
PWM1_L2
L
TLF12501
PROG
O
A
D
IMON
ISEN1_L2
IMONREF
EN
PGND
CVCC1_L2 CVDRV1_L2
CFILT
VSEN2
VRTN2
1uF
+5V
GND
Figure 14 6+1 - Phase Voltage Regulator - Typical Application (simplified schematic)
Datasheet
18
Rev2.11
2021-10-05
Restricted
TLF12501 Automotive 60A Smart Power Stage
8
Mechanical Dimensions ꢀTop View and Side Viewꢁ PQFN
Figure 15 Mechanical Dimensions of Package (Top View and Side View) in mm
Datasheet
19
Rev2.11
2021-10-05
Restricted
TLF12501 Automotive 60A Smart Power Stage
9
Mechanical Dimensions of Package in mm
Figure 16 Mechanical Dimensions of Package (Bottom View) in mm
Datasheet
20
Rev2.11
2021-10-05
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Edition <yyyy-mm-dd>
Published by
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contact your nearest Infineon Technologies office
(www.infineon.com).
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81726 München, Germany
With respect to any examples, hints or any typical
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regarding the application of the product, Infineon
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warranties and liabilities of any kind, including
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c87cer7270 cust86er’s pr8ducts a7d a7y use 8f t1e
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resp87s2b252ty 8f cust86er’s tec172ca5 depart6e7ts
to evaluate the suitability of the product for the
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respect to such application.
OptimosꢀPowerstage
TLF12501
RevisionꢀHistory
TLF12501
Revision:ꢀ2021-11-16,ꢀRev.ꢀ2.11
Previous Revision
Revision Date
Subjects (major changes since last revision)
2.0
Release of final version
2021-10-06
2021-11-16
2.11
Updated Absolute maximum ratings table and description section
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22
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