TLE9564QX [INFINEON]

The device is designed for various motor control automotive applications. To support these applications, the device provides the main functions, such as a 5 V lowdropout voltage regulator , one LIN transceiver, three half-bridges for BDLC motor control, one current sense amplifier and one 32 bit serial peripheral interface (SPI). The device includes diagnostic and supervision features, such as drain-source monitoring and open-load detection, short circuit protection, configurable time-out and window watchdog, fail-safe output, as well as overtemperature protection.;
TLE9564QX
型号: TLE9564QX
厂家: Infineon    Infineon
描述:

The device is designed for various motor control automotive applications. To support these applications, the device provides the main functions, such as a 5 V lowdropout voltage regulator , one LIN transceiver, three half-bridges for BDLC motor control, one current sense amplifier and one 32 bit serial peripheral interface (SPI). The device includes diagnostic and supervision features, such as drain-source monitoring and open-load detection, short circuit protection, configurable time-out and window watchdog, fail-safe output, as well as overtemperature protection.

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TLE9564QX  
BLDC Motor System IC  
1
Overview  
Features  
Low-drop voltage regulator 5 V, 250 mA for main supply  
Three half-bridge gate drivers for external N-channel MOSFETs  
Adaptive MOSFET gate control:  
Regulation of the MOSFET switching time  
Reduced switching losses in PWM mode  
High efficient constant gate charge  
Control of reverse battery protection MOSFET  
One low-side capable current sense amplifier (CSA) with configurable gain for protection and diagnosis  
LIN Transceivers LIN2.2/SAE J2602 with programmable TXD time-out feature and LIN flash mode  
Configurable wake-up sources  
Three high-side outputs 7 typ.  
Six PWM inputs  
High-side and low-side PWM capable  
Active free-wheeling  
Up to 25 kHz PWM frequency  
32 bit serial peripheral interface (SPI) with cyclic redundancy check (CRC)  
Very low quiescent current consumption in Stop Mode and Sleep Mode  
Periodic cyclic sense and cyclic wake in Normal Mode, Stop Mode and Sleep Mode  
Reset and interrupt output  
Drain-source monitoring and open-load detection  
Configurable time-out and window watchdog  
Overtemperature and short circuit protection features  
Leadless power package with support of optical lead tip inspection  
Green Product (RoHS compliant)  
Datasheet  
www.infineon.com  
Rev. 1.0  
2021-01-21  
1
TLE9564QX  
BLDC Motor System IC  
Overview  
Potential applications  
Auxiliary pumps (fuel, water, etc.)  
Blower motor  
Engine cooling fan  
Sunroof module  
Transfer case  
Product validation  
Qualified for automotive applications. Product validation according to AEC-Q100.  
Description  
The TLE9564QX is a multifunctional system IC with integrated power supply, communication interfaces,  
multiple half-bridges and support features in an exposed pad PG-VQFN-48 power package. The device is  
designed for various motor control automotive applications.  
To support these applications, the BLDC Motor System IC provides the main functions, such as a 5 V low-  
dropout voltage regulator, one LIN transceiver, three half-bridges for BDLC motor control, one current sense  
amplifier and one 32 bit serial peripheral interface (SPI).  
The device includes diagnostic and supervision features, such as drain-source monitoring and open-load  
detection, short circuit protection, configurable time-out and window watchdog, as well as overtemperature  
protection.  
Type  
Package  
Marking  
TLE9564QX  
PG-VQFN-48  
TLE9564QX  
Datasheet  
2
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Table of Contents  
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Hints for not functional pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
3.1  
3.2  
3.3  
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
4.1  
4.2  
4.3  
4.4  
5
5.1  
5.2  
5.3  
System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Short State Machine Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Block Description of State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
State Machine Modes Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Software Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Transition Between States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Transition into Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Init Mode -> Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Normal Mode -> Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Normal Mode -> Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Stop Mode -> Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Sleep Mode -> Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Restart Mode -> Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Fail-Safe Mode -> Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Reaction on Detected Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Stay in Current State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Transition into Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Transition into Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Configuration and Operation of Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Cyclic Sense in Low-power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Internal Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
VS Supply Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
5.4  
5.4.1  
5.4.2  
5.4.3  
5.4.4  
5.4.5  
5.4.6  
5.4.7  
5.5  
5.5.1  
5.5.2  
5.5.3  
5.5.4  
5.5.5  
5.5.6  
5.5.7  
5.5.8  
5.6  
5.6.1  
5.6.2  
5.6.3  
5.7  
5.7.1  
5.7.1.1  
5.7.1.2  
5.7.2  
5.7.3  
5.8  
6
Voltage Regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
6.1  
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Datasheet  
3
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
6.2  
6.3  
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
7
7.1  
7.2  
7.2.1  
7.2.2  
7.2.3  
7.2.4  
7.2.5  
7.3  
High-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Under Voltage Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Over Voltage Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Over Current Detection and Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
PWM, Timer and SYNC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
8
8.1  
8.1.1  
8.2  
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
LIN Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
LIN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
LIN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
LIN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
LIN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Under-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Slope Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Flash Programming via LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
8.2.1  
8.2.2  
8.2.3  
8.2.4  
8.2.5  
8.2.6  
8.2.7  
8.2.8  
8.2.9  
8.3  
9
9.1  
9.2  
9.2.1  
9.2.2  
9.2.3  
9.2.4  
9.3  
High-Voltage Wake Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
High-Voltage Wake Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
Wake configuration for Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
Wake configuration for Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
10  
10.1  
10.2  
Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66  
11  
11.1  
11.2  
11.2.1  
11.2.2  
11.2.3  
11.3  
11.3.1  
11.3.2  
11.3.3  
Gate Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67  
MOSFET control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67  
Static activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
Static activation of a high-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
Static activation of a low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
Turn-off of the high-side and low-side MOSFETs of a half-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
PWM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
Determination of the active and freewheeling MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
Configurations in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
PWM operation with 3 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
Datasheet  
4
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
11.3.3.1  
11.3.3.2  
11.3.3.3  
11.3.3.4  
11.3.3.5  
11.3.4  
11.3.5  
11.3.6  
11.4  
11.5  
11.6  
11.7  
11.8  
Control signals with active free-wheeling (AFWx = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
Control signals with passive free-wheeling (AFWx = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82  
Time modulation of pre-charge and pre-discharge times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86  
Operation at high and low duty cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
Measurements of the switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
PWM operation with 6 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90  
Status bits for regulation of turn-on and turn-off delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95  
Gate driver current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97  
Passive discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102  
Slam mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103  
Parking braking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103  
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104  
Frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105  
Electrical characteristics gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106  
11.9  
12  
12.1  
Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114  
Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114  
Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114  
Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115  
Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116  
Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117  
Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118  
Watchdog Setting Check Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118  
Watchdog during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119  
Watchdog Start in Stop Mode due to Bus Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119  
VSINT Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120  
VSINT Under- and Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121  
VSINT Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121  
VSINT Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121  
VS Under- and Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122  
VS Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122  
VS Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122  
VS Under- Overvoltage for high-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123  
VS Undervoltage for high-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123  
VS Overvoltage for high-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123  
VCC1 Over-/ Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124  
VCC1 Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124  
VCC1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125  
VCC1 Short Circuit Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125  
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126  
Individual Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126  
Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126  
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126  
Bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128  
Bridge driver supervision with activated charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128  
Drain-source voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128  
Cross-current protection and drain-source overvoltage blank time . . . . . . . . . . . . . . . . . . . . . . 129  
OFF-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130  
12.1.1  
12.1.2  
12.2  
12.2.1  
12.2.2  
12.2.3  
12.2.4  
12.2.5  
12.3  
12.4  
12.4.1  
12.4.2  
12.5  
12.5.1  
12.5.2  
12.6  
12.6.1  
12.6.2  
12.7  
12.7.1  
12.7.2  
12.8  
12.9  
12.9.1  
12.9.2  
12.9.3  
12.10  
12.10.1  
12.10.1.1  
12.10.1.2  
12.10.1.3  
Datasheet  
5
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
12.10.1.4  
12.10.1.5  
12.10.2  
12.10.3  
12.11  
12.11.1  
12.11.2  
12.11.3  
12.11.4  
12.12  
Charge pump undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131  
Switching parameters of MOSFETs in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131  
Low-side drain-source voltage monitoring during braking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131  
VS or VSINT Overvoltage braking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132  
Current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132  
Unidirectional and bidirectional operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132  
Gain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133  
Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133  
CSO output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136  
13  
13.1  
13.2  
13.3  
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144  
SPI Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144  
Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145  
SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147  
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148  
SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150  
Register Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151  
SPI control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153  
Device Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155  
Control registers bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174  
SPI status information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195  
Device Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196  
Status registers bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206  
Family and product information register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219  
13.3.1  
13.4  
13.4.1  
13.5  
13.5.1  
13.5.2  
13.6  
13.6.1  
13.6.2  
13.6.3  
13.7  
14  
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221  
Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221  
ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224  
ESD according to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224  
ESD according to SAE J2962 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224  
Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225  
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225  
14.1  
14.2  
14.2.1  
14.2.2  
14.3  
14.4  
15  
16  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227  
Datasheet  
6
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Block Diagram  
2
Block Diagram  
VSINT  
VS  
VCC1  
VCC1  
CP  
VS  
VCC1  
MUX(VSINT,VS)  
CP  
Charge pump  
SDI  
Control Logic  
CPC1N  
SDO  
SPI  
CPC1P  
CPC2N  
CPC2P  
CLK  
CSN  
state machine  
watchdog  
VCC1  
CP  
VS  
Reset  
RSTN  
GH1  
SH1  
GH2  
SH2  
Interrupt  
INTN/TEST  
Interrupt  
Generation  
VS  
GH3  
SH3  
HSS output  
HSS output  
HSS output  
HS1  
HS2  
HS3  
Gate  
Drivers  
Reset  
Generation  
GL1  
GL2  
GL3  
CSA logic  
MUX(VSINT,VS)  
MUX(VSINT,VS)  
SL  
PWM1/CRC  
PWM2  
Wake-up input  
WK4/SYNC  
Wake Logic  
Fail Safe  
PWM3  
PWM  
inputs  
PWM4  
PWM5  
PWM6  
CP/VCC1  
CSA  
CSAP  
CSAN  
CSO  
VS  
TXDLIN  
RXDLIN  
LIN  
LIN transceiver  
GND  
(Transceiver GND, Pin 16)  
(Analog/dig. GND, Pin 6)  
MUX(VSINT,VS): multiplexed VSINT & VS  
GND  
Figure 1  
Block Diagram  
Datasheet  
7
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Pin Configuration  
3
Pin Configuration  
3.1  
Pin Assignment  
N.U. 37  
N.U. 38  
24 SH2  
23 GH2  
22 PWM2  
21 GL1  
20 GL2  
19 SL  
PWM4 39  
GL3 40  
N.U. 41  
WK4/SYNC 42  
HS1 43  
TLE9564  
18 CSN  
17 LIN  
PG-VQFN-48  
HS2 44  
HS3 45  
PWM5 46  
PWM6 47  
VSINT 48  
16 GND  
15 N.U.  
14 N.U.  
13 N.U.  
Figure 2  
Pin Configuration  
3.2  
Pin Definitions and Functions  
Pin  
1
Symbol  
Function  
VCC1  
Voltage Regulator. Output voltage 1  
2
RSTN  
Reset Output. Active LOW, internally passive pull-up with open-drain output  
3
INTN/TEST  
Interrupt Output. Active LOW output, push-pull structure  
TEST. Connect to GND (via pull-down) to activate Software Development Mode  
4
5
6
7
SDO  
SDI  
SPI Data Output to Microcontroller (=MISO). Push-pull structure  
SPI Data Input from Microcontroller (=MOSI). Internal pull-down  
Ground. Analog/digital ground  
GND  
CSAP  
Not Inverting input of Current Sense Amplifier.  
Datasheet  
8
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Pin Configuration  
Pin  
8
Symbol  
CSAN  
CSO  
Function  
Inverting input of Current Sense Amplifier.  
Current Sense Amplifier Output.  
SPI Clock Input. Internal passive pull-down  
Transmit LIN. Internal passive pull-up  
Receive LIN. Push-pull structure  
Not used.  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
CLK  
TXDLIN  
RXDLIN  
N.U.  
N.U.  
Not used.  
N.U.  
Not used.  
GND  
Ground. Transceiver ground (, LIN)  
LIN Bus.  
LIN  
CSN  
SPI Chip Select Not input. Internal passive pull-up  
Source Low Side.  
SL  
GL2  
Gate Low Side 2.  
GL1  
Gate Low Side 1.  
PWM2  
GH2  
PWM input 2. Internal passive pull-up  
Gate High Side 2.  
SH2  
Source High Side 2.  
SH1  
Source High Side 1.  
GH1  
Gate High Side 1.  
PWM1/CRC  
PWM input 1. Internal passive pull-down  
CRC. Connect to GND (via pull-down) to activate CRC functionality  
28  
29  
30  
31  
32  
CPC2N  
CPC2P  
CPC1P  
CPC1N  
VS  
Negative connection to Charge Pump Capacitor 2.  
Positive connection to Charge Pump Capacitor 2.  
Positive connection to Charge Pump Capacitor 1.  
Negative connection to Charge Pump Capacitor 1.  
Supply voltage for HSx, LIN, Bridge Drivers and Charge pump. Connected to  
the battery voltage after reverse protection.  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
CP  
Charge Pump output voltage.  
PWM input 3. Internal passive pull-down  
Gate High Side 3.  
PWM3  
GH3  
SH3  
Source High Side 3.  
Not used.  
N.U.  
N.U.  
Not used.  
PWM4  
GL3  
PWM input 4. Internal passive pull-down  
Gate Low Side 3.  
N.U.  
Not used.  
WK4/SYNC  
HS1  
Wake-up input 4/Sync.  
High Side output 1.  
High Side output 2.  
HS2  
Datasheet  
9
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Pin Configuration  
Pin  
45  
46  
47  
48  
Symbol  
HS3  
Function  
High Side output 3.  
PWM5  
PWM6  
VSINT  
PWM input 5. Internal passive pull-down  
PWM input 6. Internal passive pull-down  
Voltage regulator and main supply voltage. Connected to the battery voltage  
after reverse protection  
Cooling GND  
Tab  
Cooling Tab - Exposed Die Pad; For cooling purposes only, do not use as an  
electrical ground1)  
1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the device via the  
PCB. The exposed die pad is not connected to any active part of the IC. However, it should be connected to GND for  
the best EMC performance.  
Note:  
The GND pin as well as the Cooling Tab must be connected to one common GND potential.  
3.3  
Hints for not functional pins  
It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that  
they are disabled via SPI. Unused pins should be handled as follows:  
N.U.: not used; internally bonded for testing purpose; leave open.  
RSVD: must be connected to GND.  
Datasheet  
10  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
General Product Characteristics  
4
General Product Characteristics  
4.1  
Absolute Maximum Ratings  
Table 1  
Absolute Maximum Ratings1)  
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or  
Test Condition  
Number  
Min.  
Typ. Max.  
Voltages  
Supply Voltage VS  
Supply Voltage VS  
Supply Voltage VSINT  
Supply Voltage VSINT  
Voltage Regulator 1  
VS, max  
-0.3  
28  
V
V
V
V
V
V
P_4.1.1  
P_4.1.2  
P_4.1.3  
P_4.1.4  
P_4.1.7  
VS, max  
-0.3  
40  
Load Dump  
VSINT, max  
VSINT, max  
VCC1, max  
VCP, max  
-0.3  
28  
-0.3  
40  
Load Dump  
-0.3  
5.5  
VS + 17  
Charge Pump Output Pin  
(CP)  
VS - 0.8  
ICP > - 200 µA if CP P_4.1.8  
is disabled  
CPC1P, CPC2P  
CPC1N, CPC2N  
VCPCxP, max  
- 0.3  
VS + 17  
VS + 0.3  
40  
V
V
V
P_4.1.38  
P_4.1.39  
VCPCxN, max - 0.3  
Bridge Driver Gate High Side VGHx, max  
(GHx)  
-8.0  
-8.0  
-0.3  
P_4.1.11  
P_4.1.12  
P_4.1.13  
Bridge Driver Gate Low Side VGLx, max  
(GLx)  
24  
16  
V
V
Voltage difference between VGS  
GHx-SHx and between GLx-  
SLx  
Bridge Driver Source High  
(SHx)  
VSHx, max  
VSL, max  
VCSx, max  
VCSx, max  
VCSA,Diff  
-8.0  
-8.0  
-8.0  
-0.3  
-8.0  
40  
V
V
V
V
V
P_4.1.14  
P_4.1.15  
P_4.1.16  
P_4.1.17  
P_4.1.18  
Bridge Driver Source Low  
Side SL  
6.0  
+8.0  
Current Sense Amplifier  
inputs (CSAP, CSAN)  
Current Sense Amplifier  
Output CSO  
VCC1  
+ 0.3  
Differential input voltage  
range CSAPx - CSANx  
8.0  
Wake Input WKx  
High Side HSx  
VWKx, max  
VHSx, max  
-0.3  
-0.3  
40  
V
V
P_4.1.19  
P_4.1.20  
VS, max  
+
0.3  
LIN bus  
VLIN, max  
-27  
40  
V
P_4.1.21  
Datasheet  
11  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
General Product Characteristics  
Table 1  
Absolute Maximum Ratings1) (cont’d)  
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or  
Test Condition  
Number  
Min.  
Typ. Max.  
PWM1/CRC, PWM2, PWM3, VPWM1-2-3-4-5- -0.3  
40  
V
P_4.1.25  
PWM4, PWM 5, PWM6 Input  
6, max  
Pins  
Logic Input Pins (SDI, CLK, ) VI, max  
-0.3  
VCC1  
V
P_4.1.28  
+ 0.3  
CSN  
VCSN  
-0.3  
-0.3  
40  
V
V
P_4.1.29  
P_4.1.30  
Logic Output Pins (SDO,  
RSTN, INTN, , RXDLIN)  
VO, max  
VCC1  
+ 0.3  
Temperatures  
Junction Temperature  
Storage Temperature  
ESD Susceptibility  
ESD Resistivity  
Tj  
-40  
-55  
150  
150  
°C  
°C  
P_4.1.32  
P_4.1.33  
Tstg  
VESD,11  
-2  
2
kV  
kV  
V
HBM2)  
HBM2)3)  
CDM4)  
CDM4)  
P_4.1.34  
P_4.1.35  
P_4.1.36  
P_4.1.37  
ESD Resistivity to GND, LIN VESD,12  
-8  
8
ESD Resistivity to GND  
VESD,21  
VESD,22  
-500  
-750  
500  
750  
ESD Resistivity Pin 1,  
12,13,24,25,36,37,48 (corner  
pins) to GND  
V
1) Not subject to production test, specified by design.  
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 k, 100 pF).  
3) For ESD “GUN” Resistivity (according to IEC61000-4-2 “gun test” (150 pF, 330 )), is shown in Application Information  
and test report will be provided from IBEE.  
4) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1.  
Notes  
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the  
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are  
not designed for continuous repetitive operation.  
Datasheet  
12  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
General Product Characteristics  
4.2  
Functional Range  
Table 2  
Functional Range1)  
Parameter  
Symbol  
Values  
Unit Note or  
Test Condition  
Number  
Min.  
VPOR,f  
6.0  
Typ.  
Max.  
28  
2)  
Supply Voltage  
VSINT,func  
VS,func  
VS_LIN,func  
Tj  
V
P_4.2.1  
P_4.2.2  
P_4.2.3  
P_4.2.6  
Bridge Supply Voltage  
LIN Bus Voltage  
28  
V
3)  
6
18  
V
Junction Temperature  
-40  
150  
°C  
1) Not subject to production test, specified by design.  
2) Including Power-On Reset, Over- and Undervoltage Protection.  
3) Parameter specification according to ISO 17987-4: rev 2016.  
Note:  
Within the functional range the IC operates as described in the circuit description. The electrical  
characteristics are specified within the conditions given in the related electrical characteristics  
table.  
Device Behavior Outside of Specified Functional Range  
28 V < VSINT,func < 40 V: Device will still be functional including the state machine; the specified electrical  
characteristics might not be ensured anymore. The VCC1 is working properly, however, a thermal shutdown  
might occur due to high power dissipation. HSx switches might be turned OFF depending on HSx_OV  
configurations. The specified SPI communication speed is ensured; the absolute maximum ratings are not  
violated, however the device is not intended for continuous operation of VSINT > 28 V and a thermal  
shutdown might occur due to high power dissipation. The device operation at high junction temperatures  
for long periods might reduce the operating life time.  
Note: 18 V < VS <28 V: The LIN transceiver is still functional. However, the communication might fail due to  
out-of-LIN-spec operation.  
Note: VS,UV < VS < 6 V: The LIN transceiver is still functional. However, the communication might fail due to  
out-of-LIN-spec operation.  
V
POR,f < VSINT < 5.5 V (given the fact that the device was powered up correctly before with VSINT > 5.5 V):  
Device will still be functional; the specified electrical characteristics might not be ensured anymore:  
The voltage regulator will enter the low-drop operation mode.  
A reset could be triggered depending on the Vrthx settings.  
The LIN transmitter will be disabled if VS,UV is reached. .  
HSx switch behavior will depend on the respective configuration:  
HS_UV_SD_DIS = ‘0’ (default): HSx will be turned OFF for VS < VS,UVD and will stay OFF.  
HS_UV_SD_DIS = ‘1’: HSx stays on as long as possible. An unwanted overcurrent shut down may occur.  
OC shut down bit set and the respective HSx switch will stay OFF.  
The specified SPI communication speed is ensured.  
Note:  
VS,UV < VS < 6.0 V: the charge pump might be deactivated due to a charge pump undervoltage  
detection, resulting in a turn-off of the external MOSFETs.  
Datasheet  
13  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
General Product Characteristics  
4.3  
Thermal Resistance  
Table 3  
Thermal Resistance1)  
Symbol  
Parameter  
Values  
Typ.  
7.2  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Junction to Soldering Point Rth(JSP)  
Junction to Ambient Rth(JA)  
K/W Exposed Pad  
P_4.3.1  
P_4.3.2  
2)  
27  
K/W  
1) Not subject to production test, specified by design.  
2) Specified Rth(JA) value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for a power  
dissipation of 1.5 W; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 with 2 inner copper layers  
(2 x 70 µm Cu, 2 x 35 µm C); where applicable a thermal via array under the exposed pad contacted the first inner  
copper layer and 300 mm2 cooling areas on the top layer and bottom layers (70 µm).  
4.4  
Current Consumption  
Table 4  
Current Consumption  
Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Normal Mode  
1)  
Normal Mode current  
consumption  
INormal  
4.5  
5.5  
mA  
V
= 5.5 V to 28 V; P_4.4.1  
SINT  
Tj = -40°C to +150°C;  
LIN=CP=off  
Stop Mode  
Stop Mode current  
consumption  
(low active peak threshold)  
IStop_1,25  
50  
65  
80  
µA  
1)2) CSA=LIN=off;  
WKx=HSx=CP=off:  
Cyclic Wak./Sen.=off  
Watchdog = off;  
P_4.4.2  
P_4.4.3  
no load on VCC1  
;
I_PEAK_TH = 0B  
1)2)3) Tj = 85°C;  
CSA=LIN=off;  
WKx=HSx=CP=off:  
Cyclic Wak./Sen.=off  
Watchdog = off;  
Stop Mode current  
consumption  
(low active peak threshold)  
IStop_1,85  
55  
70  
µA  
µA  
no load on VCC1  
;
I_PEAK_TH = 0B  
Stop Mode current  
consumption  
(high active peak threshold)  
IStop_2,25  
95  
1)2) CSA=LIN=off;  
WKx=HSx=CP=off:  
Cyclic Wak./Sen.=off  
Watchdog = off;  
P_4.4.4  
no load on VCC1  
;
I_PEAK_TH = 1B  
Datasheet  
14  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
General Product Characteristics  
Table 4  
Current Consumption (cont’d)  
Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
75  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Stop Mode current  
consumption  
IStop_2,85  
105  
µA  
1)2)3) Tj = 85°C;  
P_4.4.5  
CSA=LIN=off;  
(high active peak threshold)  
Cyclic Wak./Sen.=off;  
Watchdog = off;  
no load on VCC1  
;
I_PEAK_TH = 1B  
Sleep Mode  
Sleep Mode current  
consumption  
ISleep,25  
18  
28  
30  
40  
µA  
µA  
1) CSA=LIN=off;  
WKx=HSx=CP=off:  
Cyclic Wak./Sen.= off  
1)3) Tj = 85°C;  
CSA=LIN=off;  
P_4.4.6  
P_4.4.7  
Sleep Mode current  
consumption  
ISleep,85  
WKx=HSx=CP=off:  
Cyclic Wak./Sen.=off  
Feature Incremental Current Consumption  
Current consumption for LIN ILIN,rec  
1.0  
1.5  
0.1  
1.2  
1.7  
0.2  
mA 3)4) Normal/Stop  
Mode;  
P_4.4.8  
P_4.4.9  
module, recessive state  
LIN Normal Mode;  
Tj = -40°C to +150°C;  
VTXDLIN = VCC1  
;
no RL on LIN  
mA 3)4) Normal/Stop  
Mode;  
Current consumption for LIN ILIN,dom  
module, dominant state  
LIN Normal Mode;  
Tj = -40°C to +150°C;  
V
TXDLIN = GND;  
no RL on LIN  
Current consumption for LIN ILIN,Rec_onlyN  
module, Receive Only Mode,  
Normal Mode  
mA 3)4) Normal Mode;  
LIN Receive Only  
Mode;  
P_4.4.10  
P_4.4.11  
V
TXDLIN = VCC1  
no RL on LIN  
4) Stop/Sleep Mode;  
LIN wake capable;  
Current consumption for LIN ILIN,wake,25  
wake capability  
0.2  
2
2
3
µA  
µA  
Current consumption for LIN ILIN,wake,85  
wake capability  
3)4) Stop/Sleep Mode; P_4.4.12  
Tj = 85°C;  
LIN wake capable;  
Current consumption for  
each WK input  
IWK,wake,25  
0.2  
2
µA  
1)5)6)7) Sleep Mode; WK P_4.4.22  
wake capable;  
no activity on WK pin;  
Datasheet  
15  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
General Product Characteristics  
Table 4  
Current Consumption (cont’d)  
Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
0.5  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Current consumption for  
each WK input  
IWK,wake,85  
3
µA  
1)3)5)6)7) Sleep Mode; Tj P_4.4.23  
= 85°C;  
WK wake capable;  
no activity on WK pin;  
3)5)8)10)9)  
Current consumption for  
first High-Side in Stop Mode  
IStop,HS,25  
250  
250  
375  
375  
µA  
µA  
Stop Mode;  
HS with 100% duty  
cycle (no load);  
P_4.4.24  
Current consumption for  
first High-Side in Stop Mode  
IStop,HS,85  
3)5)8)10)9) Stop Mode; Tj P_4.4.25  
= 85°C;  
HS with 100% duty  
cycle (no load);  
Current consumption for  
cyclic sense function  
IStop,CS25  
IStop,CS85  
20  
24  
26  
32  
µA  
µA  
5)8)10)11) Stop Mode; WD P_4.4.26  
= off;  
3)5)8)10)11) Stop Mode; Tj P_4.4.27  
Current consumption for  
cyclic sense function  
= 85°C;  
WD = off;  
Current consumption for  
watchdog active in Stop  
Mode  
IStop,WD25  
IStop,WD85  
ICSA1  
18  
19  
23  
25  
4
µA  
µA  
3)12) Stop Mode;  
Watchdog running;  
P_4.4.28  
P_4.4.29  
Current consumption for  
watchdog active in Stop  
Mode  
3)12) Stop Mode;  
Tj = 85°C;  
Watchdog running;  
Current Sense Amplifier  
mA 12) CSA_OFF = 0B; VCSP P_4.4.31  
= VCSAP = VCSAN = 0 V;  
CSO_CAP = 0B;  
CCSO = 330 pF  
Current Sense Amplifier  
ICSA2  
10  
mA 12) CSA_OFF = 0B; VCSP P_4.4.36  
= VCSAP = VCSAN = 0 V;  
CSO_CAP = 1B;  
CCSO = 2.2 nF  
Current consumption in  
parking braking mode  
(LSx ON)  
Iparking  
10  
7
14  
10  
40  
µA  
µA  
3)12) Stop Mode or  
Sleep Mode; Tj < 85°C;  
PARK_BRK_EN = 1B  
3)12) Stop Mode or  
Sleep Mode; Tj < 85°C;  
OV_BRK_EN = 1B  
P_4.4.32  
P_4.4.34  
P_4.4.35  
Current consumption Over IOV,LS_OFF  
voltage braking mode  
(LSx OFF)  
Current consumption in VS ICP,BD  
for Charge Pump and Bridge  
Driver  
30  
mA Normal Mode;  
Tj = -40°C to +150°C;  
CPEN = 1; All HB OFF  
1) Measured at VSINT  
.
Datasheet  
16  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
General Product Characteristics  
2) If the load current on VCC1 will exceed the configured VCC1 active peak threshold, the current consumption will increase  
by typ. 2.9 mA to ensure optimum dynamic load behavior. See also Chapter 6.  
3) Not subject to production test, specified by design.  
4) Additional current will be drawn from VS.  
5) Current consumption adders of features defined for Stop Mode also apply for Sleep Mode and vice versa. Wake input  
signals are stable (i.e. not toggling), cyclic wake/sense & watchdog are OFF (unless otherwise specified).  
6) No pull-up or pull-down configuration selected.  
7) The specified WKx current consumption adder for wake capability applies regardless how many WK inputs are  
activated.  
8) Additional current will be drawn from VS and VSINT  
.
9) Typical adder of additional high-side switch activation 200 µA.  
10) HSx used for cyclic sense, Timerx with 20ms period, 0.1 ms on-time, no load.  
In general the current consumption adder for cyclic sense in Stop Mode can be calculated with below equation:  
I
Stop,CS_typ = 18 µA + (IStop,HS,25 x ton/TPer)  
where the 18 uA is the base current consumption of the digital cyclic sense/wake functionality.  
11) Also applies to cyclic wake but without adder from HS biasing contribution.  
12) Additional current will be drawn from VSINT  
.
Notes  
1. There is no additional current consumption contribution in Normal Mode due to PWM generators or Timers.  
2. The quiescent current consumption in Stop Mode and Sleep Mode will increase for VSINT < 9 V.  
Datasheet  
17  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
5
System Features  
This chapter describes the system features and behavior of the TLE9564QX:  
State machine  
Device configuration  
State machine modes and mode transitions  
Wake-up features such as cyclic sense and cyclic wake  
5.1  
Short State Machine Description  
The BLDC Motor System IC offers six operating modes:  
Init Mode: Power-up of the device and after a soft reset.  
Normal Mode: The main operating mode of the device.  
Stop Mode: The first-level power saving mode with the main voltage regulator VCC1 enabled.  
Sleep Mode: The second-level power saving mode with VCC1 disabled.  
Restart Mode: An intermediate mode after a wake event from Sleep Mode or Fail-Safe Mode or after a  
failure (e.g. WD failure, VCC1 under voltage reset) to bring the microcontroller into a defined state via a  
reset.  
Fail-Safe Mode: A safe-state mode after critical failures (e.g. Temperature shutdown) to bring the system  
into a safe state and to ensure a proper restart of the system.  
A special mode, called Software Development Mode, is available during software development or debugging  
of the system. All above mentioned operating modes can be accessed in this mode. However, the watchdog is  
still running, but no reset to the microcontroller is applied. Watchdog failures are indicated over INTN pin  
instead.  
However, the watchdog reset signaling can be reactivated again in Software Development Mode. The  
Watchdog will start always with the Long Open Windows (t_low).  
The BLDC Motor System IC is controlled via a 32-bit SPI interface (refer to Chapter 13 for detailed  
information). The configuration as well as the diagnosis is handled via the SPI.  
The device offers various supervision features to support functional safety requirements. Refer to Chapter 12  
for more information.  
Datasheet  
18  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
5.2  
Device Configuration  
Two features on the BLDC Motor System IC can be configured by hardware:  
The selection of the normal device operation or the Software Development Mode.  
Enabling/disabling the CRC on the SPI interface.  
The configurations are done monitoring the follow pins:  
INTN/TEST  
PWM1/CRC  
The hardware configuration can be done typically at device power-up, where the device is in Init Mode or (only  
in case of CRC setting) in Restart Mode.  
Software development Mode configuration detail  
After the RSTN is released, the INTN/TEST pin is internally pulled HIGH with a weak pull-up resistor. Therefore  
the default configuration is the device in normal operation.  
In order to configure the Software Development Mode, the following conditions have to be fulfilled:  
Init Mode from power-up  
VCC1>Vrtx  
POR=1  
RSTN = HIGH  
The Software Development Mode is configured using the following scheme:  
Only one external pull-down on INTN/TEST pin followed by an arbitrary SPI command, the device latches  
the Software Development Mode.  
External pull-up or no pull-down on INTN/TEST pin enable the device in normal operation.  
To enter Software Development Mode, a pull-down resistor to GND might be used.  
Soft. Dev.  
Mode OFF for tSDM_F to avoid supply glitches  
The INTN/TEST is externally pulled-down  
INTN/TEST  
Soft. Dev.  
Mode ON  
tSDM_F  
Intn_filt  
RSTN  
LATCHED (first SPI frame)  
Entry in Software Development Mode  
(not latched )  
Mode  
Successful latched Software Development Mode  
Normal Mode  
Init Mode  
Time/us  
Intn_filt: internal filtered INTN/TEST signal  
Figure 3  
Software Development Mode Selection Timing  
Intn_filt is a filtered signal from INTN/TEST, with the filter time tSMD_F (P_11.2.7). Intn_filt starts (at the rising  
edge if RSNT) wit the value 1.  
Datasheet  
19  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
Note:  
If during monitoring the INTN/TEST pin for Software Development Mode entry, the device changes  
the mode without SPI command, the device will not enter/stay in Software Development Mode.  
CRC configuration detail  
The CRC is configured using the following scheme:  
Pull-down on PWM1/CRC enable the CRC.  
No external components on PWM1/CRC disables the CRC.  
In order to configure the CRC, the follow conditions have to be full filled:  
Init Mode (from power-up) or Restart Mode  
VCC1>Vrtx  
POR=1  
RSTN = LOW  
The configuration selection is done during the reset delay time tRD1 with a continuous filter time of tCFG_F and  
the configuration (depending on the voltage level at PWM1/CRC) is latched at the rising edge of RSTN.  
VS_INT  
VPOR,r  
t
VCC1  
VRT1,r  
t
RSTN  
tCFG_F  
Continuous Filtering with  
t
tRD1  
Configuration selection monitoring period  
Figure 4  
CRC configuration Selection Timing Diagram at the device power-up.  
In case of mismatch between CRC setting between the device and µC (CRC_STAT), the device can accept two  
recovery SPI commands (static patterns).  
The pattern 67AA AA0EH (addr + rw_bit = 67 ; data = AAAA ; CRC = 0E ) enables the CRC.  
The pattern E7AA AAC3H (addr + rw_bit = E7 ; data = AAAA ; CRC = C3) disables the CRC.  
The patterns shall be send only in Normal Mode.  
For additional details about the CRC setting and configuration, refer also to Chapter 13.3.1.  
Datasheet  
20  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
5.3  
Block Description of State Machine  
The state machine describes the different states of operation, the device may get into. The following figure  
shows the state machine flow diagram.  
First battery connection  
Soft Reset  
* The Software Development Mode is a super set of  
state machine where the WD reset is not signaled,  
LIN behavior differs in Init Mode. Otherwise, there are  
no differences in behavior.  
Config.: settings can be changed in  
this device mode;  
CSA  
Init Mode  
*
OFF  
(Long open window)  
Fixed: settings stay as defined in  
Normal Mode  
(1) After Fail-Safe Mode entry, the device will stay for at  
least typ. 1s in this mode (with RSTN low) after a TSD2  
event and min. typ. 100ms after other Fail-Safe Events.  
Only then the device can leave the mode via a wake-up  
event. Wake events are stored during this time.  
VCC1  
ON  
LIN(2)  
OFF  
CP(3)  
OFF  
HSx  
OFF  
Cyc.  
Sense  
OFF  
BD(3)  
OFF  
Cyc.  
Wake  
OFF  
WD  
fixed  
(2) For Software Development Mode LIN is ON in  
Init Mode and stays ON when going from there to  
Normal Mode.  
Any SPI  
command  
(3) HB Passive off due to gate-source resistors.  
CSA  
config.  
Normal Mode  
VCC1  
ON  
CP  
HSx  
BD  
WD trigger  
config. config. config.  
Cyc.  
Cyc.  
LIN  
WD  
Sense  
Wake  
config. config.  
config. config.  
ꢀꢁReset is released  
ꢀꢁWD starts with long open window  
Automatic  
SPI cmd  
SPI cmd  
SPI cmd  
CSA  
OFF  
CSA  
OFF  
Sleep Mode  
Stop Mode  
VCC1  
OFF  
CP(3)  
OFF  
HSx  
fixed  
BD(3)  
OFF  
VCC1  
ON  
CP(3)  
OFF  
HSx  
fixed  
BD(3)  
OFF  
LIN  
Cyc.  
Sense  
fixed  
Cyc.  
Wake  
fixed  
Cyc.  
Sense  
fixed  
Cyc.  
Wake  
fixed  
VCC1 over voltage  
(depend from VCC1_OV_MOD setting)  
LIN  
fixed  
WD  
OFF  
WD  
fixed  
Wake cap./  
OFF  
Wake up event  
LS short circuit during  
VS_OV event  
CSA  
OFF  
Restart Mode  
(RO pin is asserted)  
Sleep Mode entry without any  
wake source enabled  
CP(3)  
OFF  
HSx  
OFF  
BD(3)  
OFF  
VCC1  
ON/  
ramping  
Watchdog Failure  
After 4x consecutive VCC1  
After 4x consecutive  
Watchdog failure  
Cyc.  
Sense  
OFF  
Cyc.  
Wake  
OFF  
under voltage events  
VCC1 Under voltage  
LIN  
WD  
OFF  
(if VS_INT > VS_INT_UV)  
woken/OFF  
VCC1 over voltage  
(depend from VCC1_OV_MOD setting)  
CSA  
OFF  
Fail-Safe Mode (1)  
TSD2 event  
VCC1  
OFF  
CP(3)  
OFF  
HSx  
BD(3)  
CAN, LIN, WK, wake-up event  
OR  
Release of overtemperature TSD2  
after a time depending on TSD2_DEL  
OFF  
OFF  
Cyc.  
Sense  
OFF  
Cyc.  
Wake  
OFF  
VCC1 Short to GND  
LIN  
WD  
OFF  
Wake cap.  
Figure 5  
State Diagram showing the operating modes  
Description:  
ON /OFF:= Indicate if the module is enabled or disabled either via SPI or from the device itself  
config:= Settings can be changed in this mode  
fixed:= Settings stay as defined in Normal Mode or Init Mode  
active/inactive:= Indicate if the device activates/deactivates one specific feature  
Wake capable:= Transceiver that is capable to detect one wake-up events  
woken:= Transceiver that has detected one wake-up event  
Datasheet  
21  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
5.4  
State Machine Modes Description  
5.4.1  
Init Mode  
The device starts up in Init Mode after crossing the power-on reset VPOR,r threshold (see also Chapter 12.3) and  
the watchdog will start with a long open window (tLW) after RSTN is released (High level).  
In Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence.  
Init Mode  
(Long open window)  
CSA  
OFF  
VCC1  
ON  
CP  
OFF  
HSx  
OFF  
BD  
OFF  
Cyc.  
Sense  
OFF  
Cyc.  
Wake  
OFF  
LIN  
OFF  
WD  
fixed  
Figure 6  
Table 5  
Init Mode  
Init Mode Settings  
Part/Function  
VCC1  
Value  
ON  
Description  
The VCC1 is ON  
Watchdog is fixed and set with a long open window (tLW  
All HSx are OFF  
)
WD  
fixed  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
HSx  
Bridge Drivers is OFF  
BD  
Charge Pump is OFF  
CP  
Current Sense Amplifier is OFF  
LIN transceiver is OFF 1)  
Cycle Sense is OFF  
CSA  
LIN  
Cyc Sense  
Cycle Wake is OFF  
Cyc Wake  
1) Exception: The LIN transceiver is ON during Software Development Mode  
5.4.2  
Normal Mode  
The Normal Mode is the standard operating mode for the device. The VCC1 is active and all features are  
configurable. Supervision and monitoring features are enabled.  
Datasheet  
22  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
CSA  
config.  
Normal Mode  
VCC1  
ON  
CP  
config.  
HSx  
config.  
BD  
config.  
Cyc.  
Cyc.  
Wake  
config.  
LIN  
config.  
WD  
config.  
Sense  
config.  
Figure 7  
Table 6  
Normal Mode  
Normal Mode Settings  
Part/Function  
Value  
ON  
Description  
VCC1 is active  
VCC1  
WD  
Watchdog may be configured by SPI  
config  
config  
The High Side Switches may be configured and switched ON or OFF by  
SPI  
HSx  
The Bridge Drivers and Charge Pump may be configured and switched  
ON or OFF by SPI  
Current Sense Amplifier may be configurable and switched ON or OFF by  
SPI  
BD/CP  
CSA  
config  
config  
LIN may be configurable and switched ON or OFF by SPI  
LIN  
config  
config  
Cyclic sense may be configured with the HSx, WKx inputs and Timer1 or  
Timer2 or SYNC (WK4)  
Cyc. Sense  
Cyclic wake can be configured with the Timer1 or Timer 2  
Cyc. Wake  
config  
5.4.3  
Stop Mode  
The Stop Mode is the first level technique to reduce the overall current consumption by setting the voltage  
regulator VCC1 into a low-power mode.  
Note:  
All settings have to be done before entering Stop Mode.  
In Stop Mode any kind of SPI WRITE commands are ignored and the SPI_FAIL bit is set, except for changing to  
Normal Mode, triggering a device Soft Reset, refreshing the watchdog as well as for reading and clearing the  
SPI status registers.  
Note:  
A wake-up event on , LIN, WKx, Low-Side short circuit detection in parking braking mode or  
overvoltage brake detection, could generate an interrupt on pin INTN (based on INTN masking  
configuration; refer to Chapter 10) however, no change of the device mode will occur.  
Datasheet  
23  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
CSA  
OFF  
Stop Mode  
VCC1  
ON  
CP  
OFF  
HSx  
fixed  
BD  
OFF  
Cyc.  
Sense  
fixed  
Cyc.  
Wake  
fixed  
WD  
fixed  
LIN  
fixed  
Figure 8  
Table 7  
Stop Mode  
Stop Mode Settings  
Part/Function  
VCC1  
Value  
ON  
Description  
VCC1 is ON  
Watchdog is fixed as configured in Normal Mode  
HSx are fixed as configured in Normal Mode  
The Bridge Drivers and Charge Pump are OFF  
Current Sense Amplifier is OFF  
WD  
fixed  
fixed  
OFF  
HSx  
BD/CP  
CSA  
OFF  
LIN fixed as configured in Normal Mode  
LIN  
fixed  
fixed  
fixed  
Cyclic sense fixed as configured in Normal Mode  
Cyclic wake is fixed as configured in Normal Mode  
Cyc. Sense  
Cyc. Wake  
Note:  
In Stop Mode, it is possible to activate the Low-Side of Bridge Drivers (e.g. in case of parking braking  
mode or overvoltage brake detection). Refer to Chapter 12.10 for additional details.  
5.4.4  
Sleep Mode  
The Sleep Mode is the second level technique to reduce the overall current consumption to a minimum  
needed to react on wake-up events or for the device to perform autonomous actions (e.g. cyclic sense).  
Note:  
All settings have to be done before entering Sleep Mode.  
CSA  
OFF  
Sleep Mode  
VCC1  
OFF  
CP  
OFF  
HSx  
fixed  
BD  
OFF  
Cyc.  
Sense  
fixed  
Cyc.  
Wake  
fixed  
LIN  
Wake cap.  
OFF  
WD  
OFF  
/
Figure 9  
Sleep Mode  
Datasheet  
24  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
Table 8  
Part/Function  
VCC1  
Sleep Mode Settings  
Value  
OFF  
Description  
VCC1 is OFF  
Watchdog is OFF  
WD  
OFF  
HSx are fixed as configured in Normal Mode  
The Bridge Drivers and Charge Pump are OFF  
Current Sense Amplifier is OFF  
LIN fixed as configured (Wake Capable or OFF)  
HSx  
fixed  
OFF  
BD/CP  
CSA  
OFF  
LIN  
Wake Cap/  
OFF  
Cyclic sense fixed as configured in Normal Mode  
Cyclic wake is fixed  
Cyc. Sense  
Cyc. Wake  
fixed  
fixed  
Note:  
In Sleep Mode, it is possible to activate the Low-Side’s of Bridge Drivers (e.g. in case of parking  
braking mode or overvoltage braking). Refer to Chapter 12.10 for additional details.  
5.4.5  
Restart Mode  
The Restart Mode is a transition state where the RSNT pin is asserted.  
CSA  
OFF  
Restart Mode  
(RO pin is asserted)  
VCC1  
ON/  
CP  
OFF  
HSx  
OFF  
BD  
OFF  
ramping  
Cyc.  
Sense  
OFF  
Cyc.  
Wake  
OFF  
LIN  
woken/  
OFF  
WD  
OFF  
Figure 10 Restart Mode  
Table 9  
Restart Mode Settings  
Part/Function  
VCC1  
Value  
Description  
VCC1 is ON or ramping up  
ON/  
ramping  
WD will be disabled if it was activated before  
HSx will be disabled if it was activated before  
The Bridge Drivers and Charge Pump are OFF  
Current Sense Amplifier is OFF  
WD  
OFF  
OFF  
OFF  
OFF  
HSx  
BD/CP  
CSA  
LIN  
LIN may woken (in case of wake-up event on the Bus) or wake capable  
or OFF  
Woken/  
wake  
capable/  
OFF  
Datasheet  
25  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
Table 9  
Restart Mode Settings (cont’d)  
Part/Function  
Cyc. Sense  
Cyc. Wake  
Value  
OFF  
Description  
Cyclic sense will be disabled if it was activated before  
Cyclic wake will be disabled if it was activated before  
OFF  
5.4.6  
Fail-Safe Mode  
The purpose of this mode is to bring the system in a safe status after a failure condition by turning OFF the  
VCC1 supply and powering off the microcontroller. After a wake event the system is then able to restart again.  
CSA  
Fail-Safe Mode  
OFF  
VCC1  
OFF  
CP  
OFF  
HSx  
OFF  
BD  
OFF  
Cyc.  
Sense  
OFF  
Cyc.  
Wake  
OFF  
WD  
OFF  
LIN  
Wake cap.  
Figure 11 Fail-Safe Mode  
Table 10 Fail-Safe Mode Settings  
Part/Function  
VCC1  
Value  
OFF  
Description  
VCC1 is switched OFF  
WD is switched OFF  
HSx are switched OFF  
WD  
OFF  
HSx  
OFF  
The Bridge Drivers and Charge Pump are OFF  
Current Sense Amplifier is OFF  
LIN is forced to be Wake capable  
Cyclic sense is switched OFF  
BD/CP  
CSA  
OFF  
OFF  
LIN  
Wake Cap  
OFF  
Cyc. Sense  
Cyc. Wake  
Cyclic wake is switched OFF  
OFF  
Note  
In Fail-Safe Mode, the default wake sources , LIN and WKx (if configured as wake inputs) are activated  
automatically and all wake event bits will be cleared.  
The Fail-Safe Mode will be maintained until a wake event on the default wake sources occurs. To avoid any  
fast toggling behavior a filter time of typ. 100ms (tFS,min) is implemented. Wake events during this time will  
be stored and will automatically lead to entering Restart Mode after the filter time.  
In case of an VCC1 overtemperature shutdown (TSD2) the Restart Mode will be reached automatically after  
a filter time of typ. 1s (tTSD2) without the need of a wake event once the device temperature has fallen below  
the TSD2 threshold.  
The parking braking mode is automatically disabled in Fail-Safe Mode.  
Datasheet  
26  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
5.4.7  
Software Development Mode  
The Software Development Mode is a dedicated device configuration especially useful for software  
development.  
Compared to the default device user mode operation, this mode is a super set of the state machine. The device  
will start also in Init Mode and it is possible to use all the modes and functions with following differences:  
Restart Mode or Fail-Safe Mode (depending on the configuration) is not reached due to watchdog failure  
but the other reasons to enter these modes are still valid.  
, LIN default value in Init Mode and entering Normal Mode from Init Mode is ON instead of OFF.  
Table 11 Normal Mode Settings (Software Development Mode active)  
Part/Function  
Default  
State  
Description  
VCC1 is active  
VCC1  
WD  
ON  
ON  
WD is on, but will not trigger transition to Fail-Safe Mode or Restart  
Mode  
The High Side Switches may be configured and switched ON or OFF by  
SPI  
The Bridge Drivers and Charge Pump may be configured and switched  
ON or OFF by SPI  
HSx  
OFF  
OFF  
BD/CP  
LIN may be configurable and switched ON or OFF by SPI  
Can be configured  
LIN  
ON  
Cyc. Sense  
Cyc. Wake  
OFF  
OFF  
Can be configured  
Software Development Mode entry  
For timing and configuration details, refer to Chapter 5.2.  
Note  
After Init Mode, the pull-up is released as the INTN/TEST pin acts as output then to drive the INTN signal.  
If the device enters Fail-Safe Mode due to VCC1 short circuit to GND during the Init Mode, the Software  
Development Mode will not be entered and can only be reached at the next power-up of the device after  
the VCC1 short circuit is removed.  
The absolute maximum ratings of the pin INTN must be observed. To increase the robustness of this pin  
during debugging or programming a series resistor between INTN and the connector can be added.  
Watchdog in Software Development Mode  
The Watchdog is enabled in Software Development Mode as default state. One INTN event is generated due  
to wrong watchdog trigger.  
It is possible to deactivate the integrated Watchdog module using the WD_SDM_DISABLE bit. After disabling  
the Watchdog, no INTN events are generated and the WD_FAIL bit will also not be set anymore in case of a  
trigger failure. It is also possible only to mask / unmask the INTN event of the WD in Software Development  
Mode by using the bit WD_SDM. In case of unmasking, a WD trigger fail will only lead to WD_FAIL bit set.  
5.5  
Transition Between States  
This chapter describes the transition between the modes triggered by power-up, SPI commands or wake-up  
events.  
Datasheet  
27  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
5.5.1  
Transition into Init Mode  
The device goes into Init Mode in case of a power-up or after sending a soft-reset in Normal or Stop Mode.  
Prerequisites:  
Power OFF  
Device in Normal Mode or Stop Mode with follow conditions:  
VSINT > VPOR,r  
RSTN High  
Triggering Events:  
A Soft Reset command (MODE = ‘11’). All SPI registers will be changed to their respective Soft Reset values.  
Note  
In case of Soft Reset command, a hardware RSTN event can be generated depending on the configuration.  
An external Reset will be generated in case of SOFT_RESET_RO = 0B . In case of SOFT_RESET_RO = 1B, no  
RSTN hardware event is generated in case of Soft Reset.  
At power-up, the SPI bit VCC1_UV will not be set as long as VCC1 is below the VRT,x threshold and if VSINT  
is below the VSINT,UV threshold. The RSTN pin will be kept LOW as long as VCC1 is below the selected  
VRT1,r threshold. The reset delay counter will start after VRT1,r threshold is reached. After the first  
threshold crossing of VCC1 > VRT1,R and RSTN transition from low to high, all subsequent undervoltage  
events will lead to Restart Mode.  
Wake events are ignored during Init Mode and will be lost.  
The bit VSINT_UV will only be updated in Init Mode once RSTN resumes a high level.  
5.5.2  
Init Mode -> Normal Mode  
This transition moves the device in the mode where all configurations are accessable via SPI command.  
Prerequisites:  
VSINT > VPOR,r  
Init Mode  
RSTN High  
Triggering Events:  
Any valid SPI command (from SPI protocol point of view) will bring the device to Normal Mode (i.e. any  
register can be written, cleared and read) during the long open window where the watchdog has to be  
triggered (refer also Chapter 13.2). The CRC is not taken into account for this transition.  
For example:  
A SPI Sleep Mode command will still bring the device into Normal Mode. However, as this is an invalid  
state transition, the SPI bit SPI_FAIL is set.  
Any invalid SPI command (from content point of view) will still bring the device into Normal Mode. The  
SPI bit SPI_FAIL is set.  
Note  
It is recommended to use the first SPI command to trigger and to configure the watchdog.  
5.5.3  
Normal Mode -> Stop Mode  
This transition is intended as first measure to reduce the current consumption. All the device features needed  
in Stop Mode shall be configured in Normal Mode.  
Datasheet  
28  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
Prerequisites:  
VCC1>Vrtx  
Device in Normal Mode  
Triggering Events:  
State transition is only initiated by specific SPI command.  
Note  
An interrupt is triggered on the pin INTN when Stop Mode is entered and not all wake source signalization  
flags were cleared.  
If high-side switches are kept enabled during Stop Mode, then the device current consumption will  
increase.  
It is not possible to switch directly from Stop Mode to Sleep Mode. Doing so will also set the SPI_FAIL flag  
and will bring the device into Restart Mode.  
5.5.4  
Normal Mode -> Sleep Mode  
This transition is intended to reduce as much as possible the current consumption keeping active only wake-  
up sources. All wake-up sources configurations shall be done in Normal Mode.  
Prerequisites:  
VCC1>Vrtx  
Device in Normal Mode  
All wake source signalization flags were cleared (including the LSxDSOV_BRK bit)  
At least one wake-up source activated  
Triggering Events:  
State transition is only initiated by specific SPI command.  
Note  
If the HSx outputs are kept enabled during Sleep Mode, then the device current consumption will increase  
(see Chapter 4.4).  
The Cyclic Sense function will not work properly anymore in case of a failure event (e.g. overcurrent, over  
temperature, reset) because the configured HSx and Timers will be disabled.  
If VCC1_UV or VCC1_OV (with Config to go to Restart Mode) occurs at the border of the Sleep Mode entry:  
The device will go immeditaley into Restart Mode.  
If TSD2 or VCC1_OV (with Config to go to Fail-Safe Mode) occurs at the border of the Sleep Mode entry: The  
device will enter immediately Fail-Safe Mode.  
As soon as the Sleep Mode command is sent, the Reset will go low.  
It is not possible to switch all wake sources off in Sleep Mode. Doing so will set the SPI_FAIL flag and will  
bring the device into Restart Mode.  
5.5.5  
Stop Mode -> Normal Mode  
This transition is intented to set the device in Normal Mode where all the device integrated features are  
availbale and configurable.  
Prerequisites:  
VCC1>Vrtx  
Datasheet  
29  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
Device in Stop Mode  
Triggering Events:  
State transition is only initiated by SPI command.  
Note  
None  
5.5.6  
Sleep Mode -> Restart Mode  
This transition is the consequence of a detection of wake-up event by the device. This transition is used to  
ramp up VCC1 after a wake in a defined way.  
Prerequisites:  
Device in Sleep Mode  
At least one wake-up source active  
Triggering Events:  
A wake-up event on , LIN, WKx, Cyclic Sense, Cyclic Wake.  
Bridge driver low-side short circuit detected during overvoltage braking or in parking braking mode.  
Note  
It is not possible to switch off all wake sources in Sleep Mode. Doing so will set the SPI_FAIL flag and will  
bring the device into Restart Mode.  
RSTN is pulled low during Restart Mode.  
The Restart Mode entry is signalled in the SPI register DEV_STAT.  
The wake-up events are flaged in WK_STAT register or DSOV register.  
5.5.7  
Restart Mode -> Normal Mode  
From Restart Mode, the device goes automatically to Normal Mode.  
Prerequisites:  
Device in Sleep Mode or Fail-Safe Mode  
Triggering Events:  
Automatic  
Reset is released  
Note  
The watchdog timer will start with a long open window starting from the moment of the rising edge of  
RSTN and the watchdog period setting in the register WD_CTRL will be changed to the respective default  
value.  
5.5.8  
Fail-Safe Mode -> Restart Mode  
This transition is similar to device from Sleep Mode to Restart Mode and consequence of a detection of wake-  
up event by the device. This transition is used to ramp up VCC1 after a wake in a defined way.  
Prerequisites:  
Device in Fail-Safe Mode  
Triggering Events:  
Datasheet  
30  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
A wake-up event on , LIN, WKx, TSD2 (released over temperature TDS2 after tTSD2).  
Bridge Driver Low Side short circuit detected during VS/VSINT overvoltage braking mode or in parking  
braking mode.  
Note:  
After leaving Fail-Safe Mode, the FAILURE bit in DEV_STAT register is set.  
5.6  
Reaction on Detected Faults  
The device can react at some critical events either signalling the specific failure or changing the device mode.  
The chapter describes actions taken from the device in case of critical events in particular related the device  
mode change.  
5.6.1  
Stay in Current State  
The following failures will not trigger any device mode changes, but will indicate the failures by an INTN event  
(depending from the Interrupt Masking) and in dedicated status registers:  
Failures on LIN  
Failures in Bridge Driver and/or Charge Pump  
Failures on HSx  
5.6.2  
Transition into Restart Mode  
The Restart Mode can be entered in case of failure as shown in following figure.  
VCC1 over voltage  
(depend from VCC1_OV_MOD setting)  
CSA  
OFF  
Restart Mode  
(RO pin is asserted)  
Sleep Mode entry without any  
wake source enabled  
VCC1  
ON/  
CP  
OFF  
HSx  
OFF  
BD  
OFF  
Watchdog Failure  
ramping  
Cyc.  
Sense  
OFF  
Cyc.  
Wake  
OFF  
VCC1 Under voltage  
LIN  
WD  
OFF  
woken/OFF  
Figure 12 Move into Restart Mode  
Prerequisites  
In case of wake-up event from Sleep Mode or Fail Safe Mode  
In case of Normal Mode  
In case of Stop Mode  
Trigger Events  
VCC1 Undervoltage in case of Normal Mode or Stop Mode.  
Watchdog trigger failure in case of Normal Mode or Stop Mode.  
VCC1 Overvoltage (based on VCC1_OV_MOD) in case of Normal Mode or Stop Mode.  
Datasheet  
31  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
Sleep Mode entry without any wake-up sources enabled in Normal Mode or Stop Mode.  
Note  
None  
Datasheet  
32  
Rev.1.0  
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TLE9564QX  
BLDC Motor System IC  
System Features  
5.6.3  
Transition into Fail-Safe Mode  
The Fail-Safe Mode can be entered in case of critical event as shown in the following figure.  
After 4x consecutive VCC1  
After 4x consecutive  
under voltage events  
Watchdog failure  
(if VS_INT > VS_INT_UV)  
VCC1 over voltage  
(depend from VCC1_OV_MOD setting)  
CSA  
OFF  
Fail-Safe Mode  
TSD2 event  
VCC1  
OFF  
CP  
OFF  
HSx  
OFF  
BD  
OFF  
Cyc.  
Sense  
OFF  
Cyc.  
Wake  
OFF  
VCC1 Short to GND  
LIN  
WD  
OFF  
Wake cap.  
Figure 13 Move into Fail-Safe Mode  
Prerequisites:  
Critical events on VCC1  
Watchdog trigger failures  
Trigger Events:  
Device thermal shutdown (TSD2) (see also Chapter 12.9.3).  
VCC1 is shorted to GND (see also Chapter 12.8).  
VCC1 over voltage (based on VCC1_OV_MOD).  
4 consecutive Watchdog trigger failure.  
4 consecutive VCC1 under voltage events.  
5.7  
Wake Features  
Following wake sources are implemented in the device:  
Static Sense: WKx inputs are permanently active as wake sources.  
Cyclic Sense: WKx inputs only active during on-time of cyclic sense period. Internal timers are activating  
HSx during on-time for sensing the WKx inputs.  
Cyclic Wake: wake controlled by internal timers, wake inputs are not used for cyclic wake.  
LIN wake: Wake-up via Bus messages (refer to Chapter 8.2.4).  
Note:  
Differences of 'cyclic sense' and 'cyclic wake':  
In both cases a timer is active. With 'cyclic sense' one of the high-side drivers is switched on  
periodically and supplies some external circuits connected to the WK inputs. For the design, this  
means that the WK input states are only sampled at the end of the selected HS on-phase which is set  
by the corresponding SPI settings for GPIO HS and the timer. 'Cyclic wake' means that the timer is a  
wake source and thus generates periodic interrupts as long as it is enabled.  
Datasheet  
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Rev.1.0  
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TLE9564QX  
BLDC Motor System IC  
System Features  
5.7.1  
Cyclic Sense  
The cyclic sense feature is intended to reduce the quiescent current of the device and the application.  
In the cyclic sense configuration, one high-side driver is switched on periodically controlled by TIMER_CTRL  
or WK4/SYNC pin. One high-side driver supplies external circuitries e.g. switches and/or resistor arrays, which  
are connected to one wake input WKx (see Figure 14). Any edge change of the WKx input signal during the on-  
time of the cyclic sense period causes a wake event. Depending on the device mode, either the INTN is pulled  
low (Normal Mode and Stop Mode) or the device is woken enabling the VCC1 (after Sleep Mode).  
HSx  
HSx  
HS_CTRL  
10k  
10k  
WKx  
WKx  
Signal  
TIMER_CTRL  
Period / On-Time  
Switching  
Circuitry  
INTN  
STATE MACHINE  
to uC  
Figure 14 Cyclic Sense Working Principle  
5.7.1.1 Configuration and Operation of Cyclic Sense  
The correct sequence to configure the cyclic sense is shown in Figure 15. All the configurations have to be  
performed before the on-time is set in the TIMER_CTRL registers. The settings “OFF / LOW” and “OFF / HIGH”  
define the voltage level of the respective HS driver before the start of the cyclic sense. The intention of this  
selection is to avoid an unintentional wake due to a voltage level change at the start of the cyclic sense.  
Cyclic Sense will start as soon as the respective on-time has been selected independently from the assignment  
of the HS and filter configuration. The correct configuration sequence is as follows:  
Configure the initial level.  
Mapping of a Timer to the respective HSx outputs.  
Configuring the respective filter timing and WK pins.  
Configuring the timer period and on-time.  
Datasheet  
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Rev.1.0  
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TLE9564QX  
BLDC Motor System IC  
System Features  
Cyclic Sense Configuration  
Assign TIMERx_ON to OFF/Low or  
Timer1, Timer2  
Timer1, Timer2  
OFF/High in TIMER_CTRL  
Assign Timer to selected HSx switch  
in HS_CTRL  
WKx  
Enable WKx as wake source with  
configured Timer in WK_CTRL  
Select WKx pull-up / pull-down  
configuration in WK_CTRL  
with above selected timer  
No pull-up/-down, pull-down or pull-  
up selected, automatic switching  
Select Timer Period and desired  
Period: 10, 20, 50, 100, 200ms, 1s, 2s  
On-Time: 0.1, 0.3, 1.0, 10, 20ms  
On-Time in TIMER_CTRL  
A new timer configuration will become  
active immediately, i.e. as soon as CSN  
goes high  
Cyclic Sense starts / ends by  
setting / clearing On-time  
Figure 15 Cyclic Sense: Configuration and Sequence  
Datasheet  
35  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
Cyclic Sense Configuration  
Assign WK4 as SYNC input on  
WK_CTRL  
Assign SYNC to selected HSx switch  
in HS_CTRL  
Enable WKx as wake source with  
configured SYNC in WK_CTRL  
Select WKx pull-up / pull-down  
configuration in WK_CTRL  
WKx except WK4  
with SYNC  
No pull-up/-down, pull-down or pull-  
up selected, automatic switching  
Cyclic Sense starts / ends by  
sensing SYNC rise/fall edge  
Figure 16 Cyclic Sense: Configuration and Sequence in case of SYNC usage  
Note  
All configurations of period and on-time can be selected. However, recommended on-times for cyclic  
sense are 0.1ms, 0.3ms and 1ms for quiescent current saving reasons. The SPI_FAIL will be set if the on-  
time is longer than the period.  
If the sequence is not ensured before entering Sleep Mode, then the cyclic sense function might not work  
properly, e.g. an interrupt could be missed or an unintentional interrupt could be triggered. However, if  
cyclic sense is the only wake source and it is not configured properly, then Restart Mode will be entered  
immediately because no valid wake source was set.  
During the HSx on phase in cyclic-sensing, the WKx level is sampled only once (one sample point). In case,  
a level change will appear during HSx on phase, but before the sampling, as the sampling will happen at  
the end of the on time, the level change will not be detected and has to wait for the next sensing-cycle.  
A wake event caused by cyclic-sensing will also set the corresponding bit WKx_WU.  
During Cyclic Sense, WK_LVL_STAT is updated only with the sampled voltage levels of the WKx pin in Normal  
Mode or Stop Mode.  
The functionality of the sampling and different scenarios are depicted in Figure 17 to Figure 19. The behavior  
in Stop Mode and Sleep Mode is identical except that in Normal Mode and Stop Mode INTN will be triggered to  
signal a change of WKx input level and in Sleep Mode, VCC1 will power-up instead. A wake event will be  
triggered regardless if the bit WKx_WU is already set.  
Datasheet  
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Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
HSx static ON  
Cyclic Sense  
Period  
HSx  
Filter time  
tFWK1  
Filter time  
tFWK1  
On Time  
t
1st sample taken  
as reference  
Wake detection possible  
on 2nd sample  
Figure 17 Cyclic Sense Timing  
HSx  
Filter time  
High  
Low  
Spike  
Switch  
open  
closed  
WKx  
High  
Low  
n-1  
n
n+1  
n+2  
WKn = WKn+1 = Low  
(but ignored because  
change during filter time)  
WKn = WKn+1  
WKn+2= High  
WKn+2 ≠WKn+1  
wake event  
Learning  
WKn= Low  
WKn = WKn-1  
no wake event  
Cycle  
WKn-1= Low  
INTN  
ꢂꢁno wake event  
High  
Low  
INTN &  
WK Bit Set  
Start of  
Cyclic Sense  
Figure 18 Cyclic Sense Example Timing for Stop Mode, HSx starts LOW, GND based WKx input  
Datasheet  
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Rev.1.0  
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TLE9564QX  
BLDC Motor System IC  
System Features  
HSx  
Filter time  
High  
Low  
Spike  
Switch  
open  
closed  
WKx  
High  
Low  
n-1  
n
n+1  
n+2  
WKn = WKn+1 = Low (but  
ignored because change during  
filter time), WKn = WKn+1  
ꢂꢁno wake event  
WKn+2= High  
WKn+2 ≠WKn+1  
wake event  
Learning  
Cycle  
WKn-1= Low  
WKn= Low  
WKn = WKn-1  
no wake event  
VCC1  
High  
Transition to Normal  
via Restart Mode  
Sleep Mode  
Low  
WK Bit Set  
Start of  
Cyclic Sense  
Figure 19 Cyclic Sense Example Timing for Sleep Mode, HSx starts with ON, GND based WKx input  
The cyclic sense function will be disabled in case of following conditions:  
in case Fail-Safe Mode is entered, the HSx switch will be disabled and the WKx pin will be changed to static  
sensing. An unintended wake-up event could be triggered when the WKx input is changed to static sensing.  
In Normal Mode, Stop Mode, or Sleep Mode in case of an overcurrent, or overtemperature, or under- or  
overvoltage event, the respective HS switch will be disabled.  
5.7.1.2 Cyclic Sense in Low-power Mode  
If cyclic sense is intended for Stop Mode or Sleep Mode, it is necessary to activate cyclic sense in Normal Mode  
before going to the low-power mode. A wake event due to cyclic sense will set the bit WKx_WU. In Stop Mode  
a wake event will trigger an interrupt, in Sleep Mode the wake event will send the device via Restart Mode to  
Normal Mode.  
Before returning to Sleep Mode, the wake status registers WK_STAT and DSOV must be cleared. Trying to go  
to Sleep Mode with uncleared wake flags will lead to a direct wake-up from Sleep Mode by going via Restart  
Mode to Normal Mode and triggering of RSTN.  
5.7.2  
Cyclic Wake  
For the cyclic wake feature one timer is configured as internal wake-up source and will periodically trigger an  
interrupt on INTN in Normal Mode and Stop Mode. During Sleep Mode, the timer triggers and wakes up the  
device again. The device enters via Restart Mode the Normal Mode.  
The correct sequence to configure the cyclic wake is shown in Figure 20. The sequence is as follows:  
Datasheet  
38  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
System Features  
Cyclic Wake Configuration  
Disable Timer1 and Timer2 as a wake  
To avoid unintentional interrupts  
source in TIMER_CTRL  
No interrupt will be generated,  
if the timer is not enabled as a wake source  
Select Timer1 or Timer2 as a wake  
source in TIMER_CTRL  
Periods: 10, 20, 50, 100, 200ms, 1s, 2s  
On-times: any  
(OFF/LOW & OFF/HIGH are not allowed)  
Select Timer Period and any  
On-Time in TIMER_CTRL  
Cyclic Wake starts / ends by  
setting / clearing On-time  
INTN is pulled low at every rising  
edge of On-time except first one  
Figure 20 Cyclic Wake: Configuration and Sequence  
Note:  
The on-time is only used to enable the cyclic wake function regardless of the value of the on time, i.e.  
the on time value has no meaning to the cyclic wake function as long as it is not ‘000’ or ‘110’ or ‘111’.  
As in cyclic sense, the cyclic wake function will start as soon as the on-time is configured. An interrupt is  
generated for every start of the on-time except for the very first time when the timer is started.  
5.7.3  
Internal Timers  
Two integrated timers can be used to control the below features:  
Cyclic Wake, i.e. to wake up the microcontroller periodically in Normal Mode, Stop Mode and Sleep Mode.  
Cyclic Sense, i.e. to perform cyclic sensing using the wake input WKx and the HSx by mapping the timer  
accordingly via the HS_CTRL register.  
Datasheet  
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Rev.1.0  
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TLE9564QX  
BLDC Motor System IC  
System Features  
5.8  
VS Supply Multiplexing  
VMAX SWITCH  
+
-
1
0
VSINT  
VS  
INTERNAL SUPPLY  
MUX  
Figure 21 VS Supply Multiplexing  
The internal supply voltage is multiplexed from VSINT and VS, choosing continuously the larger of both. In  
case of transient low VBAT, the buffered supply voltage takes over the internal supply, avoiding loss of power.  
Note:  
Only the internal digital logic of the device is supplied by the VMAX SWITCH. In case of a power loss  
of either VS or VSINT, the internal register values will not be lost.  
Datasheet  
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Rev.1.0  
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TLE9564QX  
BLDC Motor System IC  
Voltage Regulator 1  
6
Voltage Regulator 1  
6.1  
Block Description  
VCC1  
VSINT  
Vref  
1
Overtemperature  
Shutdown  
State  
Machine  
Bandgap  
Reference  
INH  
GND  
Figure 22 Module Block Diagram  
Functional Features  
5 V low-drop voltage regulator.  
Undervoltage monitoring with adjustable reset level and VCC1 undervoltage prewarning (refer to  
Chapter 12.7 and Chapter 12.8 for more information).  
Short circuit detection and switch off with undervoltage fail threshold, device enters Fail-Safe Mode.  
Effective capacitance must be 1 µF at nominal voltage output for stability. A 2.2 µF ceramic capacitor  
(MLCC) is recommended for best transient response.  
Output current capability up to IVCC1,lim.  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Voltage Regulator 1  
6.2  
Functional Description  
The Voltage Regulator 1 (=VCC1) is “ON” in Normal Mode and Stop Mode and is disabled in Sleep Mode and in  
Fail-Safe Mode. The regulator can provide an output current up to IVCC1,lim  
.
For low-quiescent current reasons, the output voltage tolerance is decreased in Stop Mode because only the  
less accurate low-power mode regulator will be active for small loads. If the load current on VCC1 exceeds the  
selected threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) then the high-power mode regulator will be also activated to  
support an optimum dynamic load behavior. The current consumption will then increase (approx. 2.8 mA  
additional quiescent current). The device mode stays unchanged.  
If the load current on VCC1 falls below the selected threshold (IVCC1,Ipeak1,f or IVCC1,Ipeak2,f), then the low-quiescent  
current mode is resumed again by disabling the high-power mode regulator.  
Both regulators (low-power mode and high-power mode) are active in Normal Mode.  
Two different active peak thresholds can be selected via SPI:  
I_PEAK_TH = ‘0’(default): the lower VCC1 active peak threshold 1 is selected with lowest quiescent current  
consumption in Stop Mode.  
I_PEAK_TH = ‘1’: the higher VCC1 active peak threshold 2 is selected with an increased quiescent current  
consumption in Stop Mode.  
Datasheet  
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Rev.1.0  
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TLE9564QX  
BLDC Motor System IC  
Voltage Regulator 1  
6.3  
Electrical Characteristics  
Table 12 Electrical Characteristics  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified).  
Parameter  
Symbol  
Values  
Unit Note or  
Test Condition  
Number  
Min. Typ. Max.  
Output Voltage including Line VCC1,out1  
and Load Regulation  
4.9  
5.0  
5.0  
5.1  
V
V
V
1)Normal Mode; 10 µA < P_6.3.1  
IVCC1 < 150 mA;  
Output Voltage including Line VCC1,out2  
and Load Regulation  
(Full Load Current Range)  
4.9  
5.1  
1)Normal Mode;  
P_6.3.2  
6 V < VSINT < 28 V;  
10 µA < IVCC1 < 250 mA  
2)Normal Mode; 20 mA P_6.3.3  
< IVCC1 < 80 mA;  
Output Voltage including Line VCC1,out3  
and Load Regulation  
4.95  
5.05  
(Higher Accuracy Rage)  
8 V < VSINT < 18 V;  
25°C < Tj < 150°C  
Output Voltage including Line VCC1,out4  
and Load Regulation  
4.9  
5.05 5.2  
V
Stop Mode;  
10 µA < IVCC1 < IVCC1,Ipeak  
P_6.3.4  
(low-power mode)  
Output Drop Voltage  
Output Drop Voltage  
VCC1,d1  
VCC1,d2  
200  
300  
400  
500  
mV  
mV  
mA  
IVCC1 = 50 mA,  
VSINT = 5 V  
P_6.3.9  
IVCC1 = 150 mA,  
VSINT = 5 V  
2)  
P_6.3.10  
P_6.3.17  
VCC1 Active Peak Threshold 1 IVCC1,Ipeak1,r  
(Transition threshold  
3.25 5.0  
I
rising;  
CC1  
VSINT = 13.5 V;  
between low-power and high-  
power mode regulator)  
I_PEAK_TH = ‘0’  
2)  
VCC1 Active Peak Threshold 1 IVCC1,Ipeak1,f 1.2  
(Transition threshold  
between high-power and low-  
power mode regulator)  
1.7  
mA  
mA  
mA  
mA  
I
falling;  
P_6.3.18  
P_6.3.19  
P_6.3.20  
CC1  
V
SINT = 13.5V;  
I_PEAK_TH = ‘0’  
2)  
VCC1 Active Peak Threshold 2 IVCC1,Ipeak2,r  
(Transition threshold  
between low-power and high-  
power mode regulator)  
6
5
20  
15  
500  
I
rising;  
CC1  
V
SINT = 13.5 V;  
I_PEAK_TH = ‘1’  
2)  
VCC1 Active Peak Threshold 2 IVCC1,Ipeak2,f  
(Transition threshold  
between high-power and low-  
power mode regulator)  
I
falling;  
CC1  
V
SINT = 13.5V;  
I_PEAK_TH = ‘1’  
Overcurrent Limitation  
IVCC1,lim  
260 360  
current following out of P_6.3.21  
pin, VCC1= 0V 2)  
Datasheet  
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Rev.1.0  
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TLE9564QX  
BLDC Motor System IC  
Voltage Regulator 1  
Table 12 Electrical Characteristics (cont’d)  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified).  
Parameter  
Symbol  
Values  
Unit Note or  
Test Condition  
Number  
Min. Typ. Max.  
2)  
MinimumOutputCapacitance CVCC1,min  
for stability  
13)  
µF  
P_6.3.22  
P_6.3.23  
2)  
Maximum Output  
Capacitance  
CVCC1,max  
47  
µF  
1) In Stop Mode, the specified output voltage tolerance applies when IVCC1 has exceeded the selected active peak  
threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) but with increased current consumption.  
2) Not subject to production test, specified by design.  
3) Value is meant to be an effective value at rated output voltage level.  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
High-Side Switch  
7
High-Side Switch  
7.1  
Block Description  
VS  
HSx  
HS Gate Control  
Overcurrent Detection  
Open Load (On)  
Figure 23 High-Side Module Block Diagram  
Features  
All HSx supplied by VS  
Under voltage switch off configurable via SPI.  
Dedicated over voltage switch off per each HSx in Normal Mode- configurable via SPI.  
Overvoltage switch off in Stop Mode and Sleep Mode- configurable via SPI.  
Overcurrent detection and switch off.  
Open load detection in ON-state.  
PWM capability with internal or external timers configurable via SPI.  
Switch recovery after removal of OV or UV condition configurable via SPI.  
7.2  
Functional Description  
The High-Side switches can be used for control of LEDs, as supply for the wake inputs and for other loads  
(except inductive load). The High-Side outputs can be controlled either directly via SPI by the integrated  
timers or by the integrated PWM generators or by external sync signal (using WK4/SYNC pin).  
The high-side outputs are supplied by VS pin. The topology supports improved cranking condition behavior.  
The configuration of the High-Sides (Permanent On, PWM, cyclic sense, etc.) drivers must be done in Normal  
Mode. The configuration is taken over in Stop Mode or Sleep Mode and cannot be modified. When entering  
Restart Mode or Fail-Safe Mode the HSx outputs are disabled.  
7.2.1  
Under Voltage Switch Off  
All HS drivers in on-state are switched off in case of under voltage on VS. The feature can be disabled by setting  
the SPI bit HS_UV_SD_DIS .  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
High-Side Switch  
After release of under voltage condition, the HSx switch goes back to programmed state in which it was  
configured via SPI. This behavior is only valid if the bit HS_UV_REC is set. Otherwise the switches will stay off  
and the respective SPI control bits are cleared.  
The under voltage is signaled in the bit HS_UV, no other error bits are set.  
7.2.2  
Over Voltage Switch Off  
The HS drivers in on-state are switched off in case of over voltage on VS.. In Normal Mode the HSx can be kept  
in on-state above the VS overvoltage threshold if the HSx_OV_SDN_DIS bit is set.  
In Stop Mode or Sleep Modes all HS drivers can be kept in on-state if HS_OV_SDS_DIS bit is set.  
When the HSx are configured to switch off in case of over voltage condition, after release of over voltage  
condition, the HS switch goes back to programmed state in which it was configured via SPI. This behavior is  
only valid if the respective bit HSx_OV_REC is set. Otherwise the switch will stay off and the respective SPI  
control bits are cleared. This configuration is available for each HSx.  
The over voltage is signaled in the bit HS_OV, no other error bits are set.  
7.2.3  
Over Current Detection and Switch Off  
If the load current exceeds the over current shutdown threshold for a time longer then the over current  
shutdown filter time the output is switched off.  
The over current condition and the switch off is signaled with the respective HSx_OC_OT bit in the register  
HS_OL_OC_OT_STAT. The HSx configuration is then reset to 000 by the device. To activate the High-Side  
again the HSx configuration has to be set to ON (001) or be programmed to a timer function. It is  
recommended to clear the over current bit before activation the High-Side switch, as the bits are not cleared  
automatically by the device.  
7.2.4  
Open Load Detection  
Open load detection on the High-Side outputs is done during on state of the output. If the current in the  
activated output falls below the open load detection current threshold, the open load is detected and signaled  
via the respective bit HS1_OL, HS2_OL, HS3_OL, or HS4_OL in the register HS_OL_OC_OT_STAT. The High-  
Side output stays activated.. If the open load condition disappears the Open Load bit in the SPI can be cleared.  
The bits are not cleared automatically by the device.  
7.2.5  
PWM, Timer and SYNC Function  
Each integrated HSx can be configured in different ways, in particular:  
Static OFF  
Static ON  
Timer 1  
Timer 2  
Internal generator PWM1  
Internal generator PWM2  
Internal generator PWM3  
Internal generator PWM4  
SYNC (via WK4)  
Note:  
PWMx mentioned in this chapter refer to the internal PWM generators, which are configured by the  
registers HS_CTRL and PWM_CTRL. They can be used to control the internal high-side switches HSx.  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
High-Side Switch  
Note:  
PWMx mentioned in this chapter do not refer to the PWMx pins. The PWMx pins are used for the PWM  
operation of the bridge drivers, to control the external MOSFETs.  
Static configuration (ON/OFF)  
This configuration set the HSx permanently ON or OFF. This configuration is available in Normal Mode, Stop  
Mode and Sleep Mode.  
The configuration shall be done via SPI.  
Timer configuration (TIMER1 or TIMER2)  
Two Timers are dedicated to control the ON phase of dedicated HS outputs.  
The Timers are mapped to the dedicated HS outputs. Period and the duty cycle can be independently  
configured with via SPI.  
PWM configuration (PWM1..PWM4)  
Several internal PWM generators are dedicated to generate a PWM signal on the HSx output, e.g. for brightness  
adjustment or compensation of supply voltage fluctuation. The PWM generators are mapped to the dedicated  
HS outputs, and the duty cycle can be independently configured with a 10-bit resolution via SPI (PWM_CTRL).  
Two different frequencies can be selected independently for every PWM generator in the register PWM_CTRL.  
In order to assign and configure the PWMx to specific HSX, the follow steps have to be followed:  
Configure duty cycle and frequency for respective PWM generator in PWM_CTRL.  
Assign PWM generator to respective HS switch(es) in HSx_CTRL.  
The PWM generation will start right after the HSx is assigned to the PWM generator (HS_CTRL) .  
Note:  
The min. on-time during PWM is limited by the actual on- and off-time of the respective HS switch,  
e.g. the PWM setting ‘00 0000 0001’ could not be realized.  
SYNC configuration (using WK4)  
Another possible configuration is to use the WK4 (set as SYNC pin) and mapped to one dedicated HSx output.  
The configuration of the WK4/SYNC bit is done using the WK_EN bits. If the WK_EN=10B (SYNC selected), all  
bits in WK4 bank are ignored and wake-up capability on WK4 is not available.  
Only after the WK4/SYNC configuration, the HSx can be configured for SYNC usage (HSx = 1000B).  
Datasheet  
47  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
High-Side Switch  
7.3  
Electrical Characteristics  
Table 13  
Electrical Characteristics  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Output HS1, HS2, HS3, HS4  
Static Drain-Source ON  
Resistance HSx  
RON,HS25  
RON,HS150  
Ileak,HS  
7
Ids = 60 mA,  
Tj < 25°C  
P_7.3.1  
P_7.3.2  
P_7.3.3  
Static Drain-Source ON  
Resistance HSx  
11.5  
16  
2
Ids = 60 mA,  
Tj < 150°C  
1)0 V < VHSx  
Leakage Current HSx / per  
channel  
µA  
< VS_HS  
;
Tj < 85°C  
Output Slew Rate (rising)  
Output Slew Rate (falling)  
Switch-on time HSx  
SRraise,HS  
SRfall,HS  
tON,HS  
0.8  
-2.5  
3
2.5  
-0.8  
30  
V/µs 1)20 to 80%  
VS = 6 to 18 V  
P_7.3.4  
P_7.3.5  
P_7.3.6  
RL = 220 Ω  
V/µs 1)80 to 20%  
VS = 6 to 18 V  
RL = 220 Ω  
µs  
CSN = HIGH to  
0.8 × VS;  
RL = 220 ;  
VS = 6 to 18 V  
Switch-off time HSx  
tOFF,HS  
3
30  
µs  
CSN = HIGH to  
0.2 × VS;  
P_7.3.7  
RL = 220 ;  
VS = 6 to 18 V  
Short Circuit Shutdown  
Current  
ISD,HS  
150  
12  
245  
16  
300  
22  
2
mA  
µs  
VS = 6 to 20 V  
P_7.3.8  
P_7.3.9  
P_7.3.10  
P_7.3.11  
P_7.3.12  
2)  
Short Circuit Shutdown  
Filter Time  
tSD,HS  
Open Load Detection  
Current  
IOL,HS  
0.4  
mA  
mA  
µs  
hysteresis  
included  
1)  
Open Load Detection  
hysteresis  
IOL,HS,hys  
0.45  
220  
2)  
Open Load Detection Filter tOL,HS  
160  
270  
Time  
1) Not subject to production test, specified by design.  
2) Not subject to production test, tolerance defined by internal oscillator tolerance.  
Datasheet  
48  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
8
LIN Transceiver  
8.1  
Block Description  
VS  
SPI Mode Control  
VCC1  
Driver  
TxD Input  
Temp.-  
Protection  
Current  
RTxD  
RBUS  
Output  
Stage  
TXDLIN  
Timeout  
Limit  
LIN  
To SPI Diagnostic  
Receiver  
VCC1  
Filter  
VSHS  
RXDLIN  
Wake  
Receiver  
Figure 24 Block Diagram  
8.1.1  
LIN Specifications  
The LIN network is standardized by international regulations.  
The device is compliant to:  
ISO17987-4: rev. 2016  
SAE-J2602-2  
Datasheet  
49  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
8.2  
Functional Description  
The LIN Bus is a single wire, bi-directional bus, used for in-vehicle networks. The LIN transceivers implemented  
inside the TLE9564QX are the interface between the microcontroller and the physical LIN Bus. The digital  
output data from the microcontroller are driven to the LIN bus via the TXDLIN pin on the TLE9564QX. The  
transmit data stream on the TXDLIN is converted to a LIN bus signal with optimized slew rate to minimize the  
EME level of the LIN network. The RXDLIN sends back the information from the LIN bus to the microcontroller.  
The receiver has an integrated filter network to suppress noise on the LIN Bus and to increase the EMI (Electro  
Magnetic Immunity) level of the transceiver.  
Two logical states are possible on the LIN Bus according to the LIN specification.  
Every LIN network consists of a master node and one or more slave nodes. To configure the TLE9564QX for  
master node applications, a resistor in the range of 1 kand a reverse diode must be connected between the  
LIN bus and the power supply VS.  
The different transceiver modes can be controlled via the SPI LIN bits.  
Figure 25 shows the possible transceiver mode transitions when changing the devicemode.  
Device Mode  
LIN Transceiver Mode  
Stop Mode  
Receive Only Wake Capable Normal Mode  
OFF  
OFF  
Normal Mode  
Sleep Mode  
Receive Only Wake Capable Normal Mode  
Wake Capable  
OFF  
OFF  
Woken1  
Restart Mode  
Fail-Safe Mode  
Wake Capable  
1after a wake event on LIN Bus  
Behavior after Restart Mode - not coming from Sleep Mode due to a wake up of the respective transceiver:  
If the transceivers had been configured to Normal Mode, or Receive Only Mode, then the mode will be changed to Wake  
Capable. If it was Wake Capable, then it will remain Wake Capable. If it had been OFF before Restart Mode, then it will  
remain OFF.  
Behavior in Software Development Mode:  
LIN default value in INIT MODE and entering Normal Mode from Init Mode is ON instead of OFF.  
Figure 25 LIN Mode Control Diagram  
8.2.1  
LIN OFF Mode  
The LIN OFF Mode is the default mode after power-up of the device. It is available in all device modes and is  
intended to completely stop LIN activities or when LIN communication is not needed. In LIN OFF Mode, a  
wake-up event on the bus will be ignored.  
8.2.2  
LIN Normal Mode  
The LIN Transceiver is enabled via SPI in Normal Mode. LIN Normal Mode is designed for normal data  
transmission/reception within the LIN network. The mode is available in Normal Mode and in Stop Mode.  
Datasheet  
50  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
Transmission  
The signal from the microcontroller is applied to the TXDLIN input of the device. The bus driver switches the  
LIN output stage to transfer this input signal to the LIN bus line.  
Enabling Sequence  
The LIN transceiver requires an enabling time tLIN,EN before a message can be sent on the bus. This means that  
the TXDLIN signal can only be pulled LOW after the enabling time. If this is not ensured, then the TXDLIN needs  
to be set back to high (=recessive) until the enabling time is completed.  
Only the next dominant bit will be transmitted on the bus.  
Figure 26 shows different scenarios and explanations for LIN enabling.  
VTXDLIN  
t
LIN  
Mode  
t LIN ,EN  
t LIN,EN  
t LIN,EN  
LIN  
NORMAL  
LIN OFF  
t
t
V
LIN_ BUS  
Recessive  
Dominant  
recessive TXD level  
required before start of  
transmission  
Correct sequence ,  
Bus is enabled after tLIN,  
tLIN, EN not ensured , no  
transmission on bus  
tLIN, not ensured ,  
no transmission on bus  
recessive TXD  
level required  
EN  
EN  
Figure 26 LIN Transceiver Enabling Sequence  
Reduced Electromagnetic Emission  
To reduce electromagnetic emissions (EME), the bus driver controls LIN slopes symmetrically. The  
configuration of the different slopes is described in Chapter 8.2.8.  
Reception  
Analog LIN bus signals are converted into digital signals at RXDLIN via the differential input receiver.  
8.2.3  
LIN Receive Only Mode  
In LIN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still possible. This mode  
is accessible by an SPI command and is available in Normal Mode and Stop Mode.  
8.2.4  
LIN Wake Capable Mode  
This mode can be used in Stop Mode, Sleep Mode, Restart Mode and Normal Mode by programming via SPI  
and it is used to monitor bus activities. It is automatically accessed in Fail-Safe Mode. A wake up is detected,  
if a recessive to dominant transition on the LIN bus is followed by a dominant level of longer than tWK,Bus  
followed by a dominant to recessive transition. The dominant to recessive transition will cause a wake up of  
the LIN transceiver.  
Datasheet  
51  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
A wake-up results in different behavior of the device, as described in below Table 14. As a signalization to the  
microcontroller, the RXDLIN pin is set LOW and will stay LOW until the LIN transceiver is changed to any other  
mode. After a wake-up event the transceiver can be switched to LIN Normal Mode for communication.  
Table 14  
Action due to a LIN BUS Wake-up  
Mode after Wake  
Normal Mode  
Mode  
VCC1  
INTN  
LOW  
LOW  
HIGH  
HIGH  
HIGH  
RXDLIN  
LOW  
Normal Mode  
Stop Mode  
Sleep Mode  
Restart Mode  
ON  
Stop Mode  
ON  
LOW  
Restart Mode  
Ramping Up  
ON  
LOW  
Restart Mode  
LOW  
Fail-Safe Mode  
Restart Mode  
Ramping up  
LOW  
Rearming the transceiver for wake capability  
After a BUS wake-up event, the transceiver is woken. However, the LIN transceiver mode bits will still show  
wake capable (=‘01’) so that the RXDLIN signal will be pulled low.  
There are two possibilities how the LIN transceiver’s wake capable mode is enabled again after a wake event:  
The LIN transceiver mode must be toggled, i.e. switched to LIN Normal Mode, LIN Receive Only Mode or LIN  
OFF Mode, before switching to LIN Wake Capable Mode again.  
Rearming is done automatically when the device is changed to Stop Mode, Sleep Mode or Fail-Safe Mode  
to ensure wake-up capability.  
Wake-Up in Stop Mode and Normal Mode  
In Stop Mode, if a wake-up is detected, it is signaled by the INTN output and in the WK_STAT SPI register. It is  
also signaled by RXDLIN put to LOW. The same applies for the Normal Mode. The microcontroller should set  
the device to Normal Mode, there is no automatic transition to Normal Mode.  
For functional safety reasons, the watchdog will be automatically enabled in Stop Mode after a Bus wake  
event in case it was disabled before (if bit WD_EN_ WK_BUS was configured to HIGH before).  
Wake-Up in Sleep Mode  
One wake-up event on the LIN Bus from Sleep or Fail-Safe Mode automatically transfers the device into the  
Restart Mode and from there to Normal Mode. The corresponding RXD pin in set to LOW. The microcontroller  
is able to detect the low signal on RXD and to read the wake source out of the WK_STAT register via SPI. No  
interrupt is generated when coming out of Sleep or Fail-Safe Mode. The microcontroller can now switch the  
LIN transceiver into LIN Normal Mode via SPI to start communication.  
8.2.5  
TXD Time-out Feature  
If the TXDLIN signal is dominant for the time t >tTxD_LIN _TO, the TXD time-out function deactivates the LIN  
transmitter output stage temporarily. The transceiver remains in recessive state. The TXD time-out function  
prevents the LIN bus from being blocked by a permanent LOW signal on the TXDLIN pin, caused by a failure.  
The failure is stored in the SPI flag LIN_FAIL. The LIN transmitter stage is activated again after the dominant  
time-out condition is removed. The transceiver configuration stays unchanged.  
Datasheet  
52  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
Recovery of the  
microcontroller error  
TxD Time-Out due to  
microcontroller error  
Release after TxD  
Time-out  
Normal Communication  
ttimeout  
ttorec  
Normal Communication  
TXDLIN  
t
LIN  
t
Figure 27 TXD Time-Out Function  
8.2.6  
Bus Dominant Clamping  
If the LIN bus signal is dominant for a time t > tBUS_LIN_TO in LIN Normal Mode and LIN Receive Only Mode, then  
a bus dominant clamping is detected and the SPI bit LIN_FAIL is set. The transceiver configuration stays  
unchanged.  
8.2.7  
Under-Voltage Detection  
In case the supply voltage is dropping below the VS undervoltage detection threshold (VS < VS,UV), the  
TLE9564QX disables the output and receiver stages. If the power supply reaches a higher level than the  
undervoltage detection threshold (VS> VS,UV), the TLE9564QX continues with normal operation. The  
transceiver configuration stays unchanged.  
8.2.8  
Slope Selection  
The LIN transceiver offers a LIN Low-Slope Mode for 10.4 kBaud communication and a LIN Normal-Slope Mode  
for 20 kBaud communication. The only difference is the behavior of the transmitter. In LIN Low-Slope Mode,  
the transmitter uses a lower slew rate to further reduce the EME compared to Normal-Slope Mode. This  
complies with SAE J2602 requirements.By default, the device works in LIN Normal-Slope Mode. The selection  
of LIN Low-Slope Mode is done by an SPI bit LIN_LSM and will become effective as soon as CSN goes ‘HIGH’.  
Only the LIN Slope is changed. The selection is accessible in Normal Mode only.  
8.2.9  
Flash Programming via LIN  
The device allows LIN flash programming, e.g. of another LIN Slave with a communication of up to 115 kBaud.  
This feature is enabled by de-activating the slope control mechanism via a SPI command (bit LIN_FLASH) and  
will become effective as soon as CSN goes ‘HIGH’. The SPI bit can be set in Normal Mode.  
Note:  
It is recommended to perform flash programming only at nominal supply voltage VS = 13.5 V to  
ensure stable data communication.  
Datasheet  
53  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
8.3  
Electrical Characteristics  
Table 15  
Electrical Characteristics  
VSHS = 5.5 V to 18 V, Tj = -40°C to +150°C, RL = 500 , all voltages with respect to ground, positive current flowing  
into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or Test Condition  
Number  
Min. Typ. Max.  
Receiver Output (RXD pin)  
HIGH Level Output Voltage  
VRXD,H  
VRXD,L  
0.8 ×  
VCC1  
V
V
IRXD = -2 mA;  
Bus = VS  
IRXD = 2 mA;  
Bus = 0 V  
P_9.3.1  
P_9.3.2  
V
LOW Level Output Voltage  
0.2 ×  
VCC1  
V
Transmission Input (TXD pin)  
HIGH Level Input Voltage  
VTXD,H  
0.7 ×  
VCC1  
V
V
V
Recessive State  
P_9.3.3  
P_9.3.4  
P_9.3.5  
P_9.3.6  
1)  
TXD Input Hysteresis  
VTXD,hys  
VTXD,L  
RTXD  
0.12 × –  
VCC1  
LOW Level Input Voltage  
0.3 ×  
VCC1  
Dominant State  
TXD Pull-up Resistance  
20  
40  
80  
kVTXD = 0 V  
LIN Bus Receiver (LIN Pin)  
Receiver Threshold Voltage, VBus,rd  
0.4 × 0.45 × –  
V
P_9.3.7  
Recessive to Dominant Edge  
VS  
VS  
Receiver Dominant State  
VBus,dom  
0.4 ×  
V
LIN 2.2 Param. 17  
P_9.3.8  
VS  
Receiver Threshold Voltage, VBus,dr  
0.55 × 0.60 × V  
P_9.3.9  
Dominant to Recessive Edge  
VS  
VS  
Receiver Recessive State  
Receiver Center Voltage  
Receiver Hysteresis  
VBus,rec  
VBus,c  
0.6 ×  
VS  
V
LIN 2.2 Param 18  
P_9.3.10  
P_9.3.11  
P_9.3.12  
P_9.3.13  
P_9.3.14  
0.475 0.5 × 0.525  
× VS VS × VS  
0.07 × 0.1 × 0.175  
VS VS × VS  
0.40 × 0.5 × 0.6 ×  
V
LIN 2.2 Param 19  
6 V < VS < 18 V  
VBus,hys  
V
Vbus,hys = Vbus,dr - Vbus,rd  
LIN 2.2 Param 20  
Wake-up Threshold Voltage VBus,wk  
V
VS  
VS  
VS  
2)  
Dominant Time for Bus  
Wake-up  
tWK,Bus  
30  
150  
µs  
Datasheet  
54  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
Table 15  
Electrical Characteristics (cont’d)  
VSHS = 5.5 V to 18 V, Tj = -40°C to +150°C, RL = 500 , all voltages with respect to ground, positive current flowing  
into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or Test Condition  
Number  
Min. Typ. Max.  
LIN Bus Transmitter (LIN Pin)  
1)  
Bus Serial Diode Voltage  
Drop  
Vserdiode 0.4  
0.7  
1.0  
V
V
V
= VCC1;  
P_9.3.15  
TXD  
LIN 2.2 Param 21  
Bus Recessive Output  
VBUS,ro  
0.8 ×  
VS  
VTXD = HIGH Level  
P_9.3.16  
P_9.3.20  
P_9.3.21  
Voltage  
VS  
Bus Short Circuit Current  
IBUS,sc  
40  
100  
150  
mA VBUS = 18 V;  
LIN 2.2 Param 12  
Leakage Current  
Loss of Ground  
IBUS,lk1  
-1000 -450 20  
µA VS = 12 V = GND;  
0 V < VBUS < 18 V;  
LIN 2.2 Param 15  
Leakage Current  
Loss of Battery  
IBUS,lk2  
IBUS,lk3  
IBUS,lk4  
20  
µA VS = 0 V;  
P_9.3.22  
P_9.3.23  
P_9.3.24  
P_9.3.25  
V
BUS = 18 V;  
LIN 2.2 Param 16  
mA VS = 18 V;  
Leakage Current  
Driver Off  
-1  
VBUS = 0 V;  
LIN 2.2 Param 13  
Leakage Current  
Driver Off  
20  
47  
µA VS = 8 V;  
BUS = 18 V;  
V
LIN 2.2 Param 14  
Bus Pull-up Resistance  
LIN Input Capacitance  
RBUS  
CBUS  
20  
30  
kNormal Mode  
LIN 2.2 Param 26  
1)  
20  
1
25  
6
pF  
P_9.3.26  
P_9.3.27  
Receiver propagation delay td(L),R  
bus dominant to RXD LOW  
µs VCC = 5 V;  
C
RXD = 20 pF;  
LIN 2.2 Param 31  
µs VCC = 5 V;  
Receiver propagation delay td(H),R  
1
6
P_9.3.28  
bus recessive to RXD HIGH  
CRXD = 20 pF;  
LIN 2.2 Param 31  
Receiver delay symmetry  
tsym,R  
-2  
8
2
µs tsym,R = td(L),R - td(H),R;  
LIN 2.2 Param 32  
µs 2)CSN = HIGH to first valid P_9.3.30  
P_9.3.29  
LIN Transceiver Enabling  
Time  
tLIN,EN  
tBUS_LIN  
13  
20  
20  
10  
18  
transmitted TXD dominant  
1)2)  
Bus Dominant Time Out  
ms  
ms  
µs  
P_9.3.31  
P_9.3.32  
P_9.3.33  
_TO  
1)2)  
TXD Dominant Time Out  
tTxD_LIN  
V
= 0 V  
TXD  
_TO  
1)2)  
TXD Dominant Time Out  
Recovery Time  
ttorec  
Datasheet  
55  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
Table 15  
Electrical Characteristics (cont’d)  
VSHS = 5.5 V to 18 V, Tj = -40°C to +150°C, RL = 500 , all voltages with respect to ground, positive current flowing  
into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or Test Condition  
Number  
Min. Typ. Max.  
Duty Cycle D1  
D1  
0.396  
3) THRec(max) = 0.744 × VS; P_9.3.34  
THDom(max) = 0.581 × VS;  
VS = 7.0 … 18 V;  
(For worst case at 20 kbit/s)  
LIN 2.2 Normal Slope  
tbit = 50 µs;  
D1 = tbus_rec(min)/2 tbit  
;
LIN 2.2 Param 27  
Duty Cycle D2  
(for worst case at 20 kbit/s)  
LIN 2.2 Normal Slope  
D2  
D3  
D4  
0.581  
3)THRec(min.) = 0.422 × VS; P_9.3.35  
THDom(min.) = 0.284 × VS;  
VS = 7.6 … 18 V;  
t
bit = 50 µs;  
D2 = tbus_rec(max)/2 tbit  
;
LIN 2.2 Param 28  
Duty Cycle D3  
(for worst case at 10.4 kbit/s)  
SAE J2602 Low Slope  
0.417  
3)THRec(max) = 0.778 × VS  
THDom(max) = 0.616 × VS;  
VS = 7.0 … 18 V;  
P_9.3.36  
t
bit = 96 µs;  
D3 = tbus_rec(min)/2 tbit  
;
LIN 2.2 Param 29  
Duty Cycle D4  
0.590  
3)THRec(min.) = 0.389 × VS; P_9.3.37  
THDom(min.) = 0.251 × VS;  
VS = 7.6 … 18 V;  
(for worst case at 10.4 kbit/s)  
SAE J2602 Low Slope  
tbit = 96 µs;  
D4 = tbus_rec(max)/2 tbit  
;
LIN 2.2 Param 30  
1) Not subject to production test, specified by design.  
2) Not subject to production test, tolerance defined by internal oscillator tolerance.  
3) Bus load conditions concerning LIN Specification 2.2 CLIN, RLIN = 1 nF, 1 k/ 6.8 nF, 660 / 10 nF, 500 .  
Datasheet  
56  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
VS  
TxD  
RxD  
100 nF  
RLIN  
CRxD  
WK  
LIN  
GND  
CLIN  
Figure 28 Simplified Test Circuit for Dynamic Characteristics  
Datasheet  
57  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
LIN Transceiver  
tBit  
tBit  
tBit  
TxD  
(input to  
transmitting node )  
tBus _dom (max )  
tBus_rec (min)  
Thresholds of  
receiving node 1  
THRec (max)  
THDom (max)  
VSUP  
(Transceiver supply  
of transmitting  
node )  
Thresholds of  
receiving node 2  
THRec(min)  
THDom(min)  
tBus _dom (min)  
tBus_rec(max )  
RxD  
(output of receiving  
node 1)  
td(L),R (1)  
td(H),R(1)  
RxD  
(output of receiving  
node 2)  
t(L),R(2)  
td(H),r(2)  
Duty Cycle1 = tBUS_rec(min) / (2 x t  
)
BIT  
Duty Cycle2 = tBUS_rec(max ) / (2 x tBIT  
)
Figure 29 Timing Diagram for Dynamic Characteristics  
Datasheet  
58  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
High-Voltage Wake Input  
9
High-Voltage Wake Input  
9.1  
Block Description  
Internal Supply  
IPU_WK  
WKx  
+
-
tWK  
IPD_WK  
VRef  
Logic  
Figure 30 Wake Input Block Diagram  
Features  
High-Voltage inputs with a 3 V (typ.) threshold voltage.  
Wake-up capability for power saving modes.  
Edge sensitive wake feature low to high and high to low.  
Pull-up and Pull-down current sources, configurable via SPI.  
Selectable configuration for static sense or cyclic sense.  
In Normal Mode and Stop Mode the level of the WKx pin can be read via SPI unless WK4 is configured as  
SYNC.  
Synchronization with HSx via WK4 (for cyclic sense).  
Datasheet  
59  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
High-Voltage Wake Input  
9.2  
High-Voltage Wake Function  
9.2.1  
Functional Description  
The wake inputs pin are edge-sensitive inputs with a switching threshold of typically 3 V. Both transitions, high  
to low and low to high, result in a signalization by the device. The signalization occurs either in triggering the  
interrupt in Normal Mode and Stop Mode or by a wake up of the device in Sleep Mode and Fail-Safe Mode.  
Two different wake detection modes can be selected via SPI:  
Static sense: WK inputs are always active.  
Cyclic sense: WK inputs are only active for a certain time period (see Chapter 5.7.1).  
A filter time tFWKx is implemented to avoid an unintentional wake-up due to transients or EMC disturbances  
in static sense configuration.  
The filter time (tFWKx) is triggered by a level change crossing the switching threshold and a wake signal is  
recognized if the input level will not cross again the threshold during the selected filter time.  
Figure 31 shows a typical wake-up timing and filtering of transient pulses.  
VWKx  
VWKTh,f  
VWKth,f  
t
t
VINTN  
tFWK  
tFWK  
tINTN  
No Wake Event  
Wake Event  
Figure 31 Wake-up Filter Timing for Static Sense  
The wake-up capability for the WKx pin can be enabled or disabled via SPI command.  
A wake event via the WKx pin can always be read in the register WK_STAT.  
The actual voltage level of the WKx pin (low or high) can always be read in Normal Mode, Stop Mode and Init  
Mode in the register WK_LVL_STAT. During Cyclic Sense, the register shows the sampled levels of the  
respective WKx pin.  
9.2.2  
Wake Input Configuration  
To ensure a defined and stable voltage levels at the internal comparator input it is possible to configure  
integrated current sources via the SPI register WK_CTRL.  
Datasheet  
60  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
High-Voltage Wake Input  
Table 16 Pull-Up / Pull-Down Resistor  
WKx_PUPD_ WKx_PUPD_ Current Sources Note  
1
0
0
0
no current  
source  
WK input is floating if left open (default setting)  
0
1
1
1
0
1
pull-down  
pull-up  
WK input internally pulled to GND  
WK input internally pulled to internal 5V supply  
Automatic  
switching  
If a high level is detected at the WK input the pull-up source is  
activated, if low level is detected the pull down is activated.  
Note:  
If a WK input is not used, the respective WK input must be tied to GND on board to avoid unintended  
floating state of the pin.  
One additional configuration is related the filter time of each Wake-up module. The bits WK_FILT permit to set  
the filter time in static sensing or in cyclic sensing.  
Note:  
When the device mode is changed to normal (from INIT), in case of static sense, if the WK pin is set,  
the WK_STAT register is set in this time (also the interrupt pin).  
9.2.3  
Wake configuration for Cyclic Sense  
The wake-up inputs can also be used for cyclical sensing signals during low-power modes. For this function  
the WKx input performs a cyclic sensing of the voltage level during the on-time of specific HSx.  
A transition of the voltage level will trigger a wake-up event.  
See also Chapter 5.7.1 for more details.  
9.2.4  
Wake configuration for Synchronization  
The WK4 pin can be configured as SYNC input for driving the HSx.  
Prerequisite to configure the WK4 as SYNC input is that the WK4 has to be OFF.  
The configuration of the WK4/SYNC bit is done using the WK_EN bits. if the WK_EN=10B (SYNC selected), all  
bits in WK4 bank are ignored and wake-up capability on WK4 is not available.  
Note:  
If WKx is the only wake source available and is configured with cyclic sense with  
SYNC (WKx_FILT = 100), trying to go to Sleep Mode is not possible (restart mode is entered) -  
because SYNC is driven by the microcontroller which is not supplied in Sleep Mode.  
Datasheet  
61  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
High-Voltage Wake Input  
9.3  
Electrical Characteristics  
Table 17 Electrical Characteristics  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
WK4 Input Pin Characteristics  
Wake-up/monitoring VWKx_th,f 2.5  
threshold voltage  
falling  
3
3.5  
V
V
V
without external  
serial resistor RS  
P_10.3.1  
P_10.3.2  
P_10.3.3  
Wake-up/monitoring VWKx_th,r  
threshold voltage  
rising  
3
3.5  
0.6  
4
without external  
serial resistor RS  
Threshold hysteresis  
VWKx_th,hys 0.4  
0.85  
without external  
serial resistor RS  
WK pin Pull-up Current IPU_WKx  
-20  
3
-10  
10  
-3  
µA  
µA  
VWKx = 4 V  
P_10.3.4  
P_10.3.5  
WK pin Pull-down  
Current  
IPD_WKx  
20  
VWKx = 2.5 V  
Input leakage current ILK,lx  
-2  
2
-
µA  
0 V < VWKx < 40 V;  
Pull-up / Pull-down  
disabled  
P_10.3.6  
WK4 as SYNC input pin  
LOW input voltage  
threshold  
WK4SYNC_ 0.3 ×  
-
V
P_10.3.11  
P_10.3.12  
P_10.3.13  
VCC1  
th,L  
HIGH input voltage  
threshold  
WK4SYNC_  
-
-
0.7 ×  
VCC1  
V
th,H  
Pull-down resistance RSYNC  
20  
40  
80  
kΩ  
VSYNC = 1 V  
on WK/SYNC  
Timing  
1)  
1)  
Wake-up filter time 1 tFWK1  
Wake-up filter time 2 tFWK2  
12  
50  
16  
64  
22  
80  
µs  
µs  
P_10.3.16  
P_10.3.17  
1) Not subject to production test, tolerance defined by internal oscillator tolerance.  
Datasheet  
62  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Interrupt Function  
10  
Interrupt Function  
10.1  
Block and Functional Description  
Vcc1  
Time  
out  
INTN  
Interrupt logic  
INTERRUPT BLOCK.VSD  
Figure 32 Interrupt Block Diagram  
The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is  
designed as a push/pull output stage as shown in Figure 32. An interrupt is triggered and the INTN pin is pulled  
low (active low) for tINTN in Normal Mode and Stop Mode and it is released again once tINTN is expired. The  
minimum high-time of INTN between two consecutive interrupts is tINTND. An interrupt does not cause a device  
mode change.  
Two different interrupt generation methods are implemented:  
Interrupt Mask: One dedicated register (INT_MASK) is intended to enable or disable set of interrupt  
sources. The interrupt sources follow the SPI Status Information Field.  
In details:  
SUPPLY_STAT: “OR” of all bits on SUP_STAT register except POR, VCC1_UV, VCC1_SC, VCC1_OV  
TEMP_STAT: “OR” of all bits on THERM_STAT register except TSD2  
BUS_STAT: “OR” of all bits on BUS_STAT register  
HS_STAT: “OR” of all bits on HS_OL_OC_OT_STAT register  
BD_STAT: “OR” of all bits on DSOV register  
SPI_CRC_FAIL: or between SPI_FAIL and CRC_FAIL bits on DEV_STAT register.  
Wake-up events: all wake-up events stored in the wake status SPI register WK_STAT only in case the  
corresponding input was configured as wake-up source.  
The wake-up sources are:  
via LIN  
via WK pin  
via TIMERx (cyclic wake)  
via LSx_DSOV_BRK if any of the brake-feature is enabled  
The methods are both available at the same time.  
Note:  
The errors which will cause Restart or Fail-Safe Mode (VCC1_UV, VCC1_SC, VCC1_OV, TSD2) are the  
exceptions of an INTN generation. Also the bit POR will not generate interrupts. If the above  
mentioned bits are not cleared after the device is back in Normal Mode or Stop Mode, the INTN is  
periodically generated (Register based cyclic interrupt generation).  
Datasheet  
63  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Interrupt Function  
Note:  
Note:  
Periodical interrupts are only generated by CRC fail and SPI fail from DEV_STAT register.  
During Restart Mode the SPI is blocked and the microcontroller is in reset. Therefore the INTN will not  
be in Restart Mode, which is the same behavior in Fail-Safe Mode or Sleep Mode.  
In addition to this behavior, INTN will be triggered when Stop Mode is entered and not all wake source bits  
were cleared in the WK_STAT register and also the LSx_DSOV_BRK bits in the DSOV register..  
The SPI status registers are updated at every falling edge of the INTN pulse. All interrupt events are stored in  
the respective register until the register is cleared via SPI command. A second SPI read after reading out the  
respective status register is optional but recommended to verify that the interrupt event is not present  
anymore. The interrupt behavior is shown in Figure 33.  
The INTN pin is also used during Init Mode to select the Software Development Mode entry. See Chapter 5.2  
for further information.  
In case of pending INTN event (SPI Status registers are not cleared after INTN event), additional periodical  
INTN events are generated as shown in Figure 34.  
The periodical INTN events generation can be disabled via SPI command using INTN_CYC_EN bit.  
WKx  
INTN  
tINTD  
tINTN  
Update of  
WK_STAT register  
Update of  
WK_STAT register  
optional  
no WK  
SPI  
Read & Clear  
WK_STAT  
contents  
WKx  
no WK  
SPI  
Read & Clear  
No SPI Read & Clear  
Command sent  
WK_STAT  
contents  
WKx  
no WK  
Figure 33 Interrupt Signalization Behavior  
Note:  
For two or more interrupt events at the same time, when INTN pin is low the same time, it will not  
start multiple toggling.  
Datasheet  
64  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Interrupt Function  
WKx  
INTN  
tINTN  
tINTN  
tINTN_PULSE  
tINTN_PULSE  
Update of  
WK_STAT register  
SPI  
Read & Clear  
No SPI Read & Clear  
Command sent  
No SPI Read & Clear  
Command sent  
WK_STAT  
contents  
WKx  
WKx  
Figure 34 Interrupt Signalization Behavior in case of pending INTN events  
Datasheet  
65  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Interrupt Function  
10.2  
Electrical Characteristics  
Table 18 Electrical Characteristics  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current  
defined flowing into pin; unless otherwise specified.  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Interrupt Output; Pin INTN  
1)  
INTN High Output Voltage VINTN,H 0.8 ×  
V
V
I
= -2 mA;  
P_11.2.1  
P_11.2.2  
INTN  
VCC1  
INTN = off  
1)  
INTN Low Output Voltage VINTN,L  
0.2 ×  
I
= 2mA;  
INTN  
VCC1  
INTN = on  
2)  
INTN Pulse Width  
tINTN  
80  
80  
100  
100  
120  
120  
µs  
µs  
P_11.2.3  
P_11.2.4  
INTN Pulse Minimum  
Delay Time  
tINTND  
2) between  
consecutive pulses  
Pulse in case of pending tINTN_PUL  
4
5
6
ms  
2) between  
P_11.2.5  
INTN  
consecutive pulses  
SE  
SDM Select; Pin INTN  
Config Pull-up Resistance RSDM  
30  
50  
60  
64  
100  
80  
kΩ  
VINTN = 5 V  
2)  
P_11.2.6  
P_11.2.7  
Config Select Filter Time tSDM_F  
µs  
1) Output Voltage Value also determines device configuration during Init Mode.  
2) Not subject to production test, tolerance defined by internal oscillator tolerance.  
Datasheet  
66  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11  
Gate Drivers  
The TLE9564QX integrates six floating gate drivers capable of controlling a wide range of N-channel MOSFETs.  
They are configured as three high-sides and three low-sides, building three half-bridges.  
VCP  
VS  
GHx  
Highside  
Gate-Driver  
VDSMONTH  
Current-Steering  
DACs  
SHx  
High-Speed  
Comparators  
VCP  
GLx  
Lowside  
Gate-Driver  
VDSMONTH  
Current-Steering  
DACs  
SL  
Figure 35 Half-bridge gate driver - Block diagram  
This section describes the MOSFET control in static activation and during PWM operation.  
Note:  
PWMx mentioned in this chapter refer to the PWMx pins and signal used by the bridge driver to  
control the external MOSFETs.  
Note:  
In this chapter PWMx do not refer to the internal PWM generators used to control the internal high-  
side switches HSx.  
11.1  
MOSFET control  
Depending on the configuration bits HBxMODE[1:0] (refer to HBMODE), CPEN, each high-side and low-side  
MOSFETs can be:  
Datasheet  
67  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Kept off with the passive discharge.  
Kept off actively.  
Activated (statically, no PWM, HBx_PWM_EN = 0).  
Activated in PWM mode (HBx_PWM_EN = 1).  
Refer to Table 19 for details.  
Table 19  
CPEN  
Half-bridge mode selection  
HBxMODE[1:0]1) Configuration of HSx/LSx1)  
CPEN = 0  
CPEN = 1  
CPEN = 1  
CPEN = 1  
Don’t care  
00B  
All MOSFETs are kept off by the passive discharge  
HBx MOSFETs are kept off by the passive discharge  
LSx MOSFET is ON, HSx MOSFET is actively kept OFF  
HSx MOSFET is ON, LSx MOSFET is actively kept OFF  
LSx and HSx MOSFETs are actively kept OFF with IHOLD  
01B  
10B  
CPEN = 1  
11B  
1) x = 1 … 3  
11.2  
Static activation  
In this section, we consider the static activation of the high-side and low-side MOSFET of the half-bridge x:  
HBx_PWM_EN= 0 (in ST_ICHG) and CPEN = 1.  
The low-side or high-side MOSFET of HBx is statically activated (no PWM) by setting HBxMODE[1:0] to  
respectively (0,1) or (1,0).  
The configured active cross-current protection and the Drain-Source overvoltage blank times for the Half-  
Bridge x are noted tHBxCCP ACTIVE and tHBxBLANK ACTIVE  
.
The charge and discharge currents applied to the static controlled Half-Bridge x are noted ICHGSTx  
(ST_ICHG).  
IHARDOFF is the maximum current that the gate drivers can sink (150 mA typ.). This current is used to keep a  
MOSFET off, when the opposite MOSFET of the same half-bridge is being turned on. This feature reduces the  
risk of parasitic cross-current conduction.  
ICHGSTx is the current sourced, respectively sunk, by the gate driver to turn-on the high-side x or low-side x.  
ICHGSTx is configured in the control register ST_ICHG.  
Table 20  
Static charge currents  
ICHGSTx[3:0]  
Nom. charge current  
[mA]  
Nom. discharge current  
[mA]  
Max. deviation to typ. values  
0000B  
0001B  
0010B  
0011B  
0100B  
0101B  
0.5 (ICHG0  
1.8 (ICHG4  
4.7 (ICHG8  
)
)
)
0.5 (IDCHG0  
1.8 (IDCHG4  
4.7 (IDCHG8  
)
)
)
+/- 60%  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 40 %  
+/- 40 %  
9.4 (ICHG12  
15.3 (ICHG16  
23 (ICHG20  
)
9.4 (IDCHG12)  
)
15.1 (IDCHG16  
22.5 (IDCHG20  
)
)
)
Datasheet  
68  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 20  
Static charge currents (cont’d)  
ICHGSTx[3:0]  
Nom. charge current  
[mA]  
Nom. discharge current  
[mA]  
Max. deviation to typ. values  
0110B  
0111B  
1000B  
1001B  
1010B  
1011B  
1100B  
1101B  
1110B  
1111B  
31.6 (ICHG24  
41.6 (ICHG28  
52.5 (ICHG32  
63.6 (ICHG36  
75.2 (ICHG40  
87.1 (ICHG44  
99.5 (ICHG48  
)
)
)
)
)
)
)
30.9 (IDCHG24  
40.8 (IDCHG28  
51.5 (IDCHG32  
62.4 (IDCHG36  
73.7 (IDCHG40  
85.5 (IDCHG44  
97.7 (IDCHG48  
)
)
)
)
)
)
)
+/- 40 %  
+/- 40%  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
112.2 (ICHG52  
125.3 (ICHG56  
)
)
110.8 (IDCHG52  
124.5 (IDCHG56  
138.7 (IDCHG60  
)
)
)
139 (ICHG60  
)
IHOLD is the hold current used to keep the gate of the external MOSFETs in the desired state. This parameter  
is configurable with the IHOLD control bit in GENCTRL.  
If the control bit IHOLD = 0:  
A MOSFET is kept ON with the current ICHG15  
.
A MOSFET is kept OFF with the current IDCHG15  
.
.
If the control bit IHOLD = 1:  
A MOSFET is kept ON with the current ICHG20  
.
A MOSFET is kept OFF with the current IDCHG20  
11.2.1  
Static activation of a high-side MOSFET  
Turn-on with cross-current protection  
If LSx is ON (HBxMODE[1:0] = 01B), before the activation of HSx (HBxMODE[1:0] = 10B) then the high-side  
MOSFET is turned on after a cross-current protection time (refer to Figure 36):  
After the CSN rising edge and for the duration tHBxCCP ACTIVE :  
The high-side MOSFET is kept OFF with the current -ICHGSTx.  
The gate of the low-side MOSFET is discharged with the current -ICHGSTx.  
At the end of tHBxCCP ACTIVE and for the duration tHBxBLANK ACTIVE + tFVDS  
:
The gate of the high-side MOSFET is charged with the current ICHGSTx.  
Low-side MOSFET is kept OFF with the current -IHARDOFF (hard off phase).  
At the end of tFVDS  
:
The drive current of the high-side MOSFET is reduced to IHOLD.  
The drive current of the low-side MOSFET is set to -IHOLD.  
Datasheet  
69  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
SPI Frame accepted  
Turn on HSx  
CSN  
Previous State  
HSx OFF  
LSx ON  
New State  
HSx ON  
LSx OFF  
t
VS  
tHBxCCP  
Active  
tHBxBLANK  
Active  
IGHx  
tFVDS  
ICHGSTx  
HSx  
GHx  
0
t
IGHx  
HSx internal  
drive signal  
SHx  
ICHGSTx  
LSx  
GLx  
SL  
IHOLD  
-IHOLD  
IGLx  
t
-ICHGSTx  
IGLx  
t
-ICHGSTx  
LSx internal  
drive signal  
IHOLD  
-IHOLD  
t
-ICHGSTx  
Hard off  
-IHARDOFF  
Figure 36 Turn-on of a high-side MOSFET with cross-current protection  
Note:  
The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are  
executed with a delay of up to 3 µs after the CSN rising edge.  
Datasheet  
70  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Turn-on without cross-current protection  
If LSx is OFF (HBxMODE[1:0] = 11B), before the activation of HSx (HBxMODE[1:0] = 10B), then the high-side  
MOSFET is turned on without cross-current protection (refer to Figure 37):  
right after the CSN rising edge and for a duration tHBxBLANK ACTIVE + tFVDS:  
The gate of the high-side MOSFET is charged with the current ICHGSTx.  
The low-side MOSFET is kept OFF with the current -IHARDOFF.  
At the end of tFVDS  
:
The drive current of the high-side MOSFET is reduced to IHOLD.  
The drive current of the low-side MOSFET is set to -IHOLD.  
SPI Frame accepted  
Turn on HSx  
CSN  
Previous State  
HSx OFF  
LSx OFF  
New State  
HSx ON  
LSx OFF  
t
tHBxBLANK  
Active  
IGHx  
tFVDS  
ICHGSTx  
0
t
HSx internal  
drive signal  
ICHGSTx  
VS  
IHOLD  
-IHOLD  
t
HSx  
GHx  
IGHx  
IGLx  
0
SHx  
t
LSx  
GLx  
SL  
IGLx  
LSx internal  
drive signal  
IHOLD  
-IHOLD  
t
Hard off  
-IHARDOFF  
Figure 37 Turn-on of a high-side MOSFET without cross-current protection  
Note:  
The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are  
executed with a delay of up to 3 µs after the CSN rising edge.  
Datasheet  
71  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.2.2  
Static activation of a low-side MOSFET  
The description of the static activation of a low-side x differs from the description of Chapter 11.2.1 only by  
exchanging high-side x and low-side x.  
11.2.3  
Turn-off of the high-side and low-side MOSFETs of a half-bridge  
When the TLE9564QX receives a SPI command to turn-off both the high-side and low-side MOSFETs of the half-  
bridge x (HBxMODE[1:0] = (0,0) or (1,1)):  
The gate of HSx and LSx are discharged with the current -ICHGSTx for the duration tHBxCCP ACTIVE (Figure 38).  
At the end of tHBxCCP ACTIVE, the drive current of HSx and LSx are reduced to -IHOLD.  
SPI Frame accepted  
Turn off HSx and LSx  
VS  
CSN  
HSx  
t
GHx  
IGHx  
IGHx  
SHx  
0
LSx  
t
GLx  
-ICHGSTx  
IGLx  
SL  
HSx internal  
drive signal  
tHBxCCP  
Active  
IHOLD  
-IHOLD  
t
t
-ICHGSTx  
IGLx  
LSx internal  
drive signal  
t
-IHOLD  
-ICHGSTx  
Figure 38 Turn-off of the high-side and low-side MOSFETs of a half-bridge  
Note:  
The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are  
executed with a delay of up to 3 µs after the CSN rising edge.  
Datasheet  
72  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.3  
PWM operation  
The half-bridge can be controlled in PWM using either three or six PWM inputs.  
The TLE9564QX offers the possibility to detect the active and the freewheeling (FW) MOSFET in each half-  
bridge.  
11.3.1  
Determination of the active and freewheeling MOSFET  
If EN_GEN_CHECK = 1, right before each MOSFET activation, the device detects which MOSFET of the half-  
bridge is the active MOSFET and which MOSFET is the free-wheeling (FW) MOSFET:  
If VSHx > VS - VSHH: The high-side MOSFET is the FW MOSFET and the low-side MOSFET is the active  
MOSFET.  
If VSHx < VSHL: Then the low-side MOSFET is the FW MOSFET and the high-side MOSFET is the active  
MOSFET.  
If VSHL < VSHx < VSHH: No clear distinction between the active FW MOSFET and the active MOSFET. The  
next MOSFET to be turned on is turned on as if it was the active MOSFET.  
If EN_GEN_CHECK = 0, the detection of the active and FW MOSFET is disabled. The PWM MOSFET is considered  
as the active MOSFET.  
Figure 39 shows the detection of the active and of the FW MOSFET.  
HS and LS off  
Freewheeling through  
high-side MOSFET body diode  
VSHx > VSHH  
HS and LS are off  
Freewheeling through  
low-side MOSFET body diode  
VSHx < VSHL  
HS = FW MOSFET  
LS = FW MOSFET  
LS = Active MOSFET  
HS = Active MOSFET  
VCP  
VCP  
VS  
VS  
GHx  
GHx  
Highside  
Highside  
Gate-Driver  
Gate-Driver  
SHx  
SHx  
VSHH  
VSHH  
High-Speed  
Comparators  
High-Speed  
Comparators  
VSHL  
VSHL  
VCP  
VCP  
GLx  
GLx  
Lowside  
Lowside  
Gate-Driver  
Gate-Driver  
SL  
SL  
Figure 39 Detection of the active and FW MOSFET - Principle  
11.3.2  
Configurations in PWM mode  
The following sections describe the different control schemes in PWM mode.  
Datasheet  
73  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Active gate control (AGC)  
The active gate control is configured by the control bits AGC[1:0]. The control scheme during the pre-charge  
and pre-discharge phases of:  
The active MOSFET (EN_GEN_CHECK=1).  
The PWM MOSFET (EN_GEN_CHECK=0).  
can be selected.  
The following settings are possible:  
Adaptive gate control (AGC[1:0] = (1,0) or (1,1), see GENCTRL): In this mode a pre-charge current and a pre-  
discharge current are applied to the gate of the controlled MOSFET. These currents are used to regulate  
effective the turn-on and turn-off delays to the respective target values.  
No adaptive gate control (AGC[1;0] = (0,0)): in this mode, the pre-charge and pre-discharge phases are  
deactivated.  
No adaptive gate control (AGC[1;0] = (0,1)). In this mode:  
During the pre-charge phase, the MOSFET is discharged with the configured current IPCHGINIT  
(HB_PCHG_INIT).  
During the pre-discharge phase, the MOSFET is discharged with the configured current IPDCHGINIT  
(HB_PCHG_INIT).  
Note:  
It is recommended to configure tPCHGx < tHBxBLANK Active and tPDCHGx < tHBxCCP Active (Refer to  
TPRECHG and CCP_BLK) independently from the AGC settings.  
Active free-wheeling (AFW)  
The active free-wheeling is activated for HBx if these conditions are fulfilled:  
AFWx = 1 (HBMODE)  
HBx_PWM_EN = 1 (HBMODE)  
PWM_NB = 0  
If AFWx = 1, a cross-current protection time is applied to HBx (set by CCP_BLK) during the PWM operation.  
If AFWx = 0, no cross current protection is applied to HBx during the PWM operation.  
The active free-wheeling reduces the power dissipation of the free-wheeling MOSFET. If an active MOSFET is  
OFF, the opposite MOSFET of the same half-bridge is actively turned on. Refer to Figure 43 and Figure 44.  
Datasheet  
74  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Post-charge  
A post-charge is initiated if POCHGDIS is set to 0 (GENCTRL) to reach the minimum MOSFET Rdson:  
POCHGDIS = 0: After the charge phase, the control signal for the charge current of LSx is increased by one  
current step at every bridge driver clock cycle (BDFREQ) to ICHGMAXx. Refer to Figure 40  
POCHGDIS = 1: The post-charge phase is disabled. The charge current is kept to the ICHGx  
Turn-on of:  
Turn-off of:  
PWM MOSFET if EN_GEN_CHECK = 0  
Active MOSFET if EN_GEN_CHECK =1  
PWM MOSFET if EN_GEN_CHECK = 0  
Active MOSFET if EN_GEN_CHECK =1  
Precharge  
Post-charge  
IGS  
tPCHGx  
Predischarge  
ICHGMAXx  
IPRECHGx  
tPDCHGx  
ICHGx  
0
t
- IDCHGx  
tBLANK active  
- IPREDCHGx  
tHBxCPP active  
Figure 40 PWM overview - AGC = 10B or 11B, POCHGDIS=0 (post-charge enabled)  
Turn-on of:  
Turn-off of:  
PWM MOSFET if EN_GEN_CHECK = 0  
Active MOSFET if EN_GEN_CHECK =1  
PWM MOSFET if EN_GEN_CHECK = 0  
Active MOSFET if EN_GEN_CHECK =1  
Precharge  
IGS  
tPCHGx  
Predischarge  
tPDCHGx  
IPRECHGx  
ICHGx  
0
t
- IDCHGx  
tBLANK Active  
- IPREDCHGx  
tHBxCPP Active  
Figure 41 PWM overview - AGC = 10B or 11B, POCHGDIS=1 (post-charge disabled)  
Table 21  
Abbreviation  
Suffix x  
Abbreviations for adaptive turn-on and turn-off phases in PWM configuration  
Definition  
Related to the half-bridge x.  
VGS_HSx  
IGS_HSx  
Gate-Source voltage of high-side MOSFET x.  
Gate current of high-side MOSFET x.  
IGS_HSx is positive when the current flows out of GHx.  
VGS_LSx  
IGS_LSx  
Gate-Source voltage of low-side MOSFET x.  
Gate current of low-side MOSFET x.  
IGS_LSx is positive when the current flows out of GLx.  
tPWM_SYNCH  
Synchronization delay between external and internal PWM signal.  
tHBxCCP ACTIVE Active cross-current protection time of HBx. See control register CCP_BLK.  
tHBxBLANK ACTIVE Active Drain-source overvoltage blank time of HBx. See control register and CCP_BLK.  
tHBxCCP FW  
Freewheeling cross-current protection time of HBx. See control register CCP_BLK.  
Datasheet  
75  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 21  
Abbreviations for adaptive turn-on and turn-off phases in PWM configuration (cont’d)  
Abbreviation  
tHBxBLANK FW  
Definition  
Freewheeling drain-source overvoltage blank time of HBx. See control register and  
CCP_BLK.  
PWMz  
External PWM signal applied to the input pin PWMz.  
ICHGMAXx  
Maximum drive current of the half-bridge x during the pre-charge and pre-discharge  
phases. See control register HB_ICHG_MAX.  
IPRECHGx and IPREDCHGx are limited to ICHGMAXx.  
IPRECHGx  
Pre-charge current sourced by the gate driver to the active MOSFET of the half-bridge  
x during tPCHGx (TPRECHG).  
Internal and self-adaptive parameter (if AGC[1:0] = (1,0) or (1,1), GENCTRL).  
IPRECHGx is clamped between ICHG0 (0.5 mA typ.) and ICHGMAXx.  
IPCHGINITx  
IPREDCHGx  
Initial value of IPRECHGx. Refer to HB_PCHG_INIT.  
Pre-discharge-current sunk by the gate driver mapped to the half-bridge x during  
tPDCHGx.  
Internal and self-adaptive parameter (if AGC[1:0] = (1,0) or (1,1), GENCTRL).  
IPREDCHGx is clamped between IDCHG0 (0.5 mA typ.) and ICHGMAXx.  
IPDCHGINITx  
ICHGx  
Initial value of IPREDCHGx. Refer to HB_PCHG_INIT.  
Current sourced by the gate driver to the active MOSFET of the half-bridge x during the  
charge phase. See control register HB_ICHG.  
IDCHGx  
Current sunk by the gate driver to turn-off the active MOSFET of the half-bridge x  
during the discharge phase. See control register HB_ICHG.  
ICHGFWx  
tPCHGx  
tPDCHGx  
Current sourced or sunk by the gate driver to turn on / turn off the freewheeling  
MOSFET of the half-bridge x . See control register HB_ICHG.  
Duration of the pre-charge phase of half-bridge x.  
tPCHGx is configurable by SPI. See control register TPRECHG.  
Duration of the pre-discharge phase of half-bridge x.  
tPDCHGx is configurable by SPI. See control register TPRECHG.  
tDONx  
tDOFFx  
IHOLD  
Turn-on delay of the active MOSFET of HBx.  
Turn-off delay of the active MOSFET of HBx.  
Hold current sourced or sunk by the gate driver to keep the MOSFET in the desired  
state. See IHOLD control bit in GENCTRL.  
IHARDOFF  
TFVDS  
IHARDOFF is the maximum current that the gate drivers can sink. It corresponds to the  
discharge current when IDCHGx[5:0] = 63D (150 mA typ.).  
Drain-Source overvoltage filter time. See LS_VDS.  
11.3.3  
PWM operation with 3 PWM inputs  
Each half bridge are controlled by one input if PWM_NB = 0 (see CSA) and HBx_PWM_EN (see HBMODE):  
PWM1/CRC controls HB1  
PWM3 controls HB2  
PWM5 controls HB3  
Datasheet  
76  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
CP  
CP  
VS  
HS1  
PWM1  
PWM2  
µC_PWM1  
µC_PWM3  
µC_PWM5  
LS1  
SL  
CP  
VS  
PWM3  
PWM4  
HS2  
CP  
LS2  
SL  
CP  
VS  
PWM5  
PWM6  
HS3  
CP  
SL  
LS3  
Figure 42 Half-bridge PWM control with three PWM inputs, PWM_NB = 0  
Table 22  
Half-bridge PWM settings with 3 PWM inputs  
PWM_NB HBxPWM_ HBxMODE1) AFW  
Half-bridge x settings1)  
EN1)  
0
0
Don’t care 00B  
Don’t care  
0
LSx and HSx MOSFETs are kept OFF by the passive  
discharge  
1
1
01B  
10B  
PWM signal applied to LSx  
PWM signal = 1: LSx, ON, HSx OFF  
PWM signal = 0: LSx OFF, HS x OFF  
0
1
PWM signal applied to HSx  
PWM signal= 1: HSx, ON, LSx OFF  
PWM signal = 0: HSx OFF, LS x ON  
0
Don’t care 11B  
Don’t care  
LSx and HSx MOSFETs are actively kept OFF  
1) x = 1 to 3  
11.3.3.1 Control signals with active free-wheeling (AFWx = 1)  
This section describes the MOSFET control signals with active freewheeling and HS PWM:  
The HS PWM MOSFET is the active MOSFET (Chapter 11.3.3.1.1).  
The HS PWM MOSFET is the free-wheeling MOSFET (Chapter 11.3.3.1.2).  
11.3.3.1.1  
The PWM MOSFET is the active MOSFET  
This section shows the control signals of the MOSFET when the PWM is the active MOSFET.  
Datasheet  
77  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
tPWM_SYNCH  
External  
PWM signal  
t
VSHx < VSHL right before activation of HSx  
HSx detected as active MOSFET  
Synchronized intern.  
PWM signal  
tHBxCCP  
Charge  
t
Postcharge Phase  
FW  
phase  
IGS_HSx  
tPCHGx  
ICHGMAXx  
IPRECHGx  
ICHGx  
0
t
t
HSx internal  
drive signal  
tFVDS  
tHBxBLANK Active  
ICHGMAXx  
IPRECHGx  
IHOLD  
IHOLD  
ICHGx  
ICHGx  
0
-
IHOLD  
VGS_HSx  
t
t
tRISEx  
VSHx  
VS  
VSHH  
VSHH  
VSHL  
tDONx  
VSHL  
IDS_HSDx  
IPHASE  
t
tHBxCCP  
FW  
LSx internal  
drive signal  
IHOLD  
t
-
IHOLD  
-
IHOLD  
Hard off  
-
ICHGFWx  
-
IHARDOFF  
Figure 43 Turn-on of an active MOSFET in PWM mode with active gate control, HS PWM, HS as active  
MOSFET, LS as FW MOSFET. PWM_NB =0 (one PWM input per HB), HBxMODE = 10B (HS PWM),  
AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET),  
AFWx = 1 (active freewheeling for HBx is activated)  
Datasheet  
78  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
External  
PWM signal  
t
t
Synchronized intern.  
PWM signal  
tPWM_SYNCH  
tPDCHGx  
VSHx < VSHL right before activation of LSx  
LSx detected as FW MOSFET  
HSx internal  
drive signal  
Discharge phase  
IHOLD  
0
t
- IHOLD  
- IDCHGx  
- IHOLD  
- IDCHGx  
- IPREDCHGx  
tHBxCCP Active  
Hard off  
- IHARDOFF  
VGS_HSx  
t
t
tFALLx  
VSHx  
tDOFFx  
VS  
VSHH  
VSHH  
VSHL  
VSHL  
IDS_HSDx  
IPHASE  
t
tHBx_BLANK FW  
LSx internal  
drive signal  
tFVDS  
ICHGFWx  
IHOLD  
IHOLD  
t
- IHOLD  
Figure 44 Turn-off of an active MOSFET in PWM mode with active gate control, HS PWM, HS as active  
MOSFET, LS as FW MOSFET. PWM_NB =0 (one PWM input per HB), HBxMODE = 10B (HS PWM),  
AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET),  
AFWx = 1 (active freewheeling for HBx is activated)  
Datasheet  
79  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.3.3.1.2  
The PWM MOSFET is the free-wheeling MOSFET  
This section shows the control signals of the MOSFET when the PWM is the free-wheeling MOSFET.  
External  
PWMz  
t
t
tPWM_SYNCH  
Synchronized  
intern. PWMz  
IGS_LSx  
Discharge phase  
tPDCHGx  
t
0
- IDCHGx  
- IPREDCHGx  
tHBxCCP Active for cross current  
protection  
LSx internal  
drive signal  
IHOLD  
0
t
-
IHOLD  
- IDCHGx  
- IHOLD  
- IDCHGx  
- IPREDCHGx  
Hard off  
-
IHARDOFF  
tFVDS  
VGS_LSx  
t
t
VSHx  
tDOFFx tFALLx  
VS  
VSHH  
VSHH  
VSHL  
VSHL  
Detection of the active MOSFET  
(EN_GEN_CHECK= 1). VSH > VSHH: LS  
MOSFET is the active MOSFET  
IDS_LSDx  
IPHASE  
t
IGS_HSx  
ICHGFWx  
t
tHBxBLANK FW  
HSx internal  
drive signal  
tFVDS  
ICHGFWx  
IHOLD  
IHOLD  
t
-
IHOLD  
\G  
D i
 
\fi  
\BLDC  
Figure 45 PWM rising edge - PWM mode with active gate control, HS PWM (HBxMODE = 10B) , LS as  
active MOSFET, HS as FW MOSFET. PWM_NB =0 (one PWM input per HB), AGC = 01B or 10B  
(Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active  
freewheeling for HBx is activated)  
Datasheet  
80  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
External  
PWMz  
Synchronized  
intern. PWMz  
t
t
tPWM_SYNCH  
Charge  
phase  
Postcharge Phase  
IGS_LSx  
tPCHGx  
ICHGMAXx  
IPRECHGx  
ICHGx  
0
t
tHBxBLANK Active  
tHBxCCP FW  
LSx internal  
drive signal  
tFVDS  
ICHGMAXx  
IPRECHGx  
IHOLD  
IHOLD  
ICHGx  
ICHGx  
t
0
-
IHOLD  
VGS_LSx  
t
t
tRISEx  
VSHx  
tDONx  
VS  
VSHH  
VSHH  
VSHL  
VSHL  
Detection of the active MOSFET  
(EN_GEN_CHECK= 1). VSH > VSHH: LS  
MOSFET is the active MOSFET  
IDS_LSDx  
IPHASE  
t
t
IGS_HSx  
-
ICHGFWx  
HSx internal  
drive signal  
tFVDS  
IHOLD  
t
-
IHOLD  
-
IHOLD  
-
ICHGFWx  
Hard off  
-
IHARDOFF  
Figure 46 PWM falling edge - PWM mode with active gate control, HS PWM (HBxMODE = 10B) , LS as  
active MOSFET, HS as FW MOSFET. PWM_NB =0 (one PWM input per HB), AGC = 01B or 10B  
(Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active  
freewheeling for HBx is activated)  
Datasheet  
81  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.3.3.2 Control signals with passive free-wheeling (AFWx = 0)  
This section describes the MOSFET control signals with active freewheeling and HS PWM:  
The HS PWM MOSFET is the active MOSFET (Chapter 11.3.3.2.1).  
The HS PWM MOSFET is the free-wheeling MOSFET (Chapter 11.3.3.2.2).  
11.3.3.2.1  
The PWM MOSFET is the active MOSFET  
This section shows the control signals of the MOSFET when the PWM is the active MOSFET.  
Datasheet  
82  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
External  
PWMz  
Synchronized  
intern. PWMz  
t
t
tPWM_SYNCH  
Charge  
phase  
Postcharge Phase  
IGS_HSx  
tPCHGx  
ICHGMAXx  
IPRECHGx  
ICHGx  
0
t
tHBxBLANK  
HSx internal  
drive signal  
tFVDS  
ICHGMAXx  
IPRECHGx  
IHOLD  
IHOLD  
ICHGx  
ICHGx  
t
0
-
IHOLD  
VGS_HSx  
t
t
tRISEx  
VSHx  
VS  
VSHH  
VSHH  
VSHL  
tDONx  
VSHL  
IDS_HSDx  
IPHASE  
t
IGS_LSx  
t
t
LSx internal  
drive signal  
tFVDS  
-
IHOLD  
-
IHOLD  
Hard off  
-
IHARDOFF  
Figure 47 Adaptive turn-on with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0, the  
PWM MOSFET is the active MOSFET. PWM_NB=0.  
Datasheet  
83  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
External  
PWMz  
t
t
tPWM_SYNCH  
Synchronized  
intern. PWMz  
IGS_HSx  
Discharge phase  
tPDCHGx  
t
0
- IDCHGx  
- IPREDCHGx  
tHBxCCP Active  
HSx internal  
drive signal  
IHOLD  
0
t
-
IHOLD  
- IDCHGx  
- IHOLD  
- IDCHGx  
- IPREDCHGx  
VGS_HSx  
t
t
tFALLx  
VSHx  
tDOFFx  
VS  
VSHH  
VSHH  
VSHL  
VSHL  
IDS_HSDx  
IPHASE  
t
t
IGS_LSx  
0
LSx internal  
drive signal  
t
-
IHOLD  
Figure 48 Adaptive turn-off with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0, the  
PWM MOSFET is the active MOSFET.PWM_NB=0.  
11.3.3.2.2  
The PWM MOSFET is the free-wheeling MOSFET  
This section shows the control signals of the MOSFET when the PWM is the free-wheeling MOSFET.  
Datasheet  
84  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
External  
PWMz  
t
t
tPWM_SYNCH  
Synchronized  
intern. PWMz  
IGS_LSx  
Discharge phase  
tPDCHGx  
t
0
- IDCHGx  
- IPREDCHGx  
tHBxCCP Active for cross current  
protection  
LSx internal  
drive signal  
IHOLD  
0
t
-
IHOLD  
- IDCHGx  
- IHOLD  
- IDCHGx  
- IPREDCHGx  
VGS_LSx  
t
t
VSHx  
tDOFFx tFALLx  
VS  
VSHH  
VSHH  
VSHL  
VSHL  
Detection of the active MOSFET  
IDS_LSDx  
IPHASE  
(EN_GEN_CHECK= 1). VSH > VSHH: LS  
MOSFET is the active MOSFET  
t
IGS_HSx  
t
HSx internal  
drive signal  
t
-
IHOLD  
\G t
 
D i
 
\fi  
\BLDC\  
Figure 49 PWM rising edge with adaptive control, EN_GEN_CHECK = 1 with high-side PWM, AGC[1:0] =  
(1,0) or (1,1), AFWx=0, POCHGDIS=0. The PWM MOSFET is the FW MOSFET. PWM_NB=0.  
Datasheet  
85  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Detection of the active MOSFET  
(EN_GEN_CHECK= 1). VSH > VSHH: LS  
MOSFET is the active MOSFET  
External  
PWMz  
Synchronized  
intern. PWMz  
t
t
tPWM_SYNCH  
Charge  
phase  
Postcharge Phase  
IGS_LSx  
tPCHGx  
ICHGMAXx  
IPRECHGx  
ICHGx  
0
t
tHBxBLANK Active  
LSx internal  
drive signal  
tFVDS  
ICHGMAXx  
IPRECHGx  
IHOLD  
IHOLD  
ICHGx  
ICHGx  
t
0
-
IHOLD  
VGS_LSx  
t
t
tRISEx  
VSHH  
VSHx  
VS  
VSHH  
tDONx  
VSHL  
VSHL  
IDS_LSDx  
IPHASE  
t
t
IGS_HSx  
HSx internal  
drive signal  
tFVDS  
t
-
IHOLD  
-
IHOLD  
Hard off  
-
IHARDOFF  
Figure 50 PWM falling edge with adaptive control, EN_GEN_CHECK = 1 with high-side PWM, AGC[1:0]  
= (1,0) or (1,1), AFWx=0, POCHGDIS=0. The PWM MOSFET is the FW MOSFET. PWM_NB=0.  
11.3.3.3 Time modulation of pre-charge and pre-discharge times  
If DEEP_ADAP =0:  
Datasheet  
86  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
one single precharge current is applied during tPCHGx to regulate TDON  
one single precharge current is applied during tPDCHGx to regulate TDOFF  
If DEEP_ADAP = 1 (“deep adaptation” or “time modulation”) it is possible to:  
to divide the precharge phase in two parts, during which two different precharge currents can be applied  
to divide the predischarge phase in two parts, during which two different precharge currents can be  
applied  
Figure 51 describes the principle of the time modulation applied to the precharge phase. The same principle  
is also applied for the regulation of the pre-discharge phase.  
Datasheet  
87  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
TDON adaptation  
with two current  
steps (IPCHGADT =  
1)  
Current i+2  
No  
3 consecutive sign changes of (TDON  
EFF- TDON TARGET) or No error for 3  
consecutive PWM cycles  
Current i  
Yes  
tPCHG  
tPCHG  
TDON adaptation  
with one current step  
i+1  
i
3 consecutive sign changes  
of (TDON EFF- TDON  
TARGET)  
No  
tPCHG  
tPCHG  
Yes  
i+1  
i
Precharge phase splitted in 2  
sub-phases  
50% 50%  
tPCHG  
Yes  
TDON EFF = TDON  
TARGET  
No  
Precharge splitted:  
75%-25% if TDON EFF > TDON TARGET  
25%-75% if TDON EFF < TDON TARGET  
i+1  
i
i+1  
i
or  
25%  
75%  
75%  
tPCHG  
25%  
tPCHG  
Yes  
TDON EFF = TDON  
TARGET  
No  
Precharge splitted:  
E.g 87.5%-12.5%  
1) Precharge further split either:  
- until TDON EFF = TDON TARGET  
Etc... 1)  
- Or until no further split of tPCHG is possible. Refer to 2).  
No 2)  
TDON EFF = TDON TARGET  
2) Exit time modulation:  
- tPCHG cannot be further divided due to the limitation of the resolution  
- and the regulation of TDON is still not possible  
One single current is applied during tPCHG  
Figure 51  
Principle of the time modulation of the precharge phase, DEEP_ADAP = 1, AGC = 10B or 11B  
Datasheet  
88  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.3.3.4 Operation at high and low duty cycles  
In the particular cases where the on-time is shorter than tHBxCCP FW or the off-time of the PWM signal is  
shorter than tHBxCCP Active:  
No distinction between active MOSFET and FW MOSFET is possible. Therefore PWM MOSFET (selected by  
HBxMODE[1:0]) is controlled as active MOSFET.  
The MOSFET opposite to the PWM MOSFET stays off (passive FW)  
11.3.3.5 Measurements of the switching times  
The effective switching times in PWM operation:  
of the PWM MOSFET if EN_GEN_CHECK = 0  
of the active MOSFET if EN_GEN_CHECK = 1  
are reported in the registers:  
EFF_TDON_OFF1,EFF_TDON_OFF2,EFF_TDON_OFF3.  
If the end of the rise time for a given MOSFET is not detected before tHBxBLANK Active elapses, then the  
corresponding status register reports an effective rise time equal to zero.  
If the end of the fall time for a given MOSFET is not detected before tHBxCCP Active active elapses, then the  
corresponding status register reports an effective fall time equal to zero.  
The device cannot measure the switching times tDON, tDOFF, tRISE and tFALL at very high and very low duty cycles:  
tON < tHBxCCP FW and tOFF < tHBxCCP active. In this case, the corresponding registers report effective tDON, tDOFF, tRISE  
and tFALL equal to zero.  
Datasheet  
89  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.3.4  
PWM operation with 6 PWM inputs  
Each high-side MOSFET and each low-side MOSFET is controlled by one PWM input. if PWM_NB is set to 1 (see  
CSA) and HBx_PWM_EN are set to 1 (see HBMODE). Refer to Table 23.  
CP  
VS  
PWM2  
HS1  
µC_PWM2  
CP  
PWM1  
µC_PWM1  
LS1  
SL  
CP  
VS  
VS  
PWM4  
PWM3  
µC_PWM4  
µC_PWM3  
HS2  
LS2  
CP  
SL  
CP  
PWM6  
PWM5  
HS3  
LS3  
µC_PWM6  
µC_PWM5  
CP  
SL  
Figure 52 Half-bridge PWM control with six PWM inputs, PWM_NB = 1  
Table 23  
PWM_NB  
Half-bridge PWM settings with 6 PWM inputs (PWM_NB = 1)FW and Active MOSFET  
HBx_PWM HBxMODE1)  
Half-bridge x settings1)  
_EN1)  
1
1
Don’t care 00B  
LSx and HSx MOSFETs are kept OFF by the passive  
discharge (default)  
1
1
01B  
HBx is controlled by its PWM inputs  
If EN_GEN_CHECK = 0: LSx is always considered as the  
active MOSFET  
If EN_GEN_CHECK = 1: The active and the FW MOSFETs  
are detected according to Chapter 11.3.1,  
independently from HBxMODE  
1
10B  
HBx is controlled by its PWM inputs  
If EN_GEN_CHECK = 0: HSx is always considered as the  
active MOSFET  
If EN_GEN_CHECK = 1: The active and the FW MOSFETs  
are detected according to Chapter 11.3.1  
independently from HBxMODE  
1
Don’t care 11B  
LSx and HSx MOSFETs are actively kept OFF  
1) x = 1 to 3  
Datasheet  
90  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 24  
PWM Control of HS1 and LS1, PWM_NB = 1, HB1_PWM_EN = 1  
HB1MODE[1:0]  
PWM1/CRC  
Low  
PWM2  
Low  
HS1  
OFF  
ON  
LS1  
OFF  
OFF  
ON  
01  
01  
01  
01  
10  
10  
10  
10  
Low  
High  
Low  
High  
OFF  
OFF  
OFF  
OFF  
ON  
High  
High  
Low  
OFF  
OFF  
ON  
Low  
Low  
High  
Low  
High  
OFF  
OFF  
High  
High  
OFF  
Table 25  
PWM Control of HS2 and LS2, PWM_NB = 1, HB2_PWM_EN = 1  
HB2MODE[1:0]  
PWM3  
Low  
PWM4  
Low  
HS2  
OFF  
ON  
LS2  
OFF  
OFF  
ON  
01  
01  
01  
01  
10  
10  
10  
10  
Low  
High  
Low  
High  
High  
Low  
OFF  
OFF  
OFF  
OFF  
ON  
High  
Low  
OFF  
OFF  
ON  
Low  
High  
Low  
High  
High  
OFF  
OFF  
High  
OFF  
Table 26  
PWM Control of HS3 and LS3, PWM_NB = 1, HB3_PWM_EN = 1  
HB3MODE[1:0]  
PWM5  
Low  
PWM6  
Low  
HS3  
OFF  
ON  
LS3  
OFF  
OFF  
ON  
01  
01  
01  
01  
10  
10  
10  
10  
Low  
High  
Low  
High  
High  
Low  
OFF  
OFF  
OFF  
OFF  
ON  
High  
Low  
OFF  
OFF  
ON  
Low  
High  
Low  
High  
High  
OFF  
OFF  
High  
OFF  
Figure 53 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the FW MOSFET (low-side  
MOSFET in this case) followed by the activation of the active MOSFET (high-side MOSFET in this case)1) with  
PWM_NB = 1, AGC[1:0]=01B or 10B, POCHGDIS = 0 (post-charge enabled).  
This control scheme is applicable for the following cases:  
1) If the synchronized HS PWM rising edge occurs after tHBxCCP FW and before the end of tOFF timeout FW, then the LS MOSFET is  
discharged with IHARDOFF and the HS is turned on, when the HS PWM rising edge is detected  
Datasheet  
91  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
1. EN_GEN_CHECK = 0 (detection of FW/Active MOSFET disabled); HBxMODE[1:0] = 10B (HS MOSFET is  
considered as active MOSFET by default).  
2. EN_GEN_CHECK = 1 (detection of active / FW MOSFET enabled); HS MOSFET detected as active MOSFET;  
HBxMODE[1:0] = 01B or10B.  
Note:  
If the synchronized HS PWM rising edge occurs before the end of tHBxCCP active, then the device  
prevents an activation of the HS MOSFET until tHBxCCP FW elapses. In other words, the HS PWM  
rising edge is ignored until the end of tHBxCCP FW.  
Datasheet  
92  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
External HSx PWM  
signal  
Synchronized HSx  
PWM signal  
tPWM_SYNCH  
Charge  
phase  
t
Postcharge Phase  
IGS_HSx  
tPCHGx  
ICHGMAXx  
IPRECHGx  
ICHGx  
0
t
HSx internal  
drive signal  
tFVDS  
tHBxBLANK Active  
ICHGMAXx  
IPRECHGx  
IHOLD  
IHOLD  
ICHGx  
ICHGx  
t
t
t
0
- IHOLD  
VGS_HSx  
VSHx < VSHL right before the activation of HSx  
tRISEx  
VSHx  
HSx detected as active MOSFET  
VS  
VSHH  
VSHH  
VSHL  
tDONx  
VSHL  
IDS_HSDx  
IPHASE  
t
Synchronized LSx  
PWM signal  
tHBxCCP FW  
t
tOFF Timeout  
FW  
LSx internal  
drive signal  
tFVDS  
IHOLD  
t
- IHOLD  
- IHOLD  
- ICHGFWx  
Hard off  
- IHARDOFF  
Figure 53 Turn-on of an active MOSFET in PWM mode with active gate control, HS as active MOSFET,  
LS as FW MOSFET. Two PWM inputs per half-bridge, active gate control enabled. PWM_EN =1  
Datasheet  
93  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Figure 54 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the active MOSFET (high-side  
MOSFET in this case) followed by the activation of the FW MOSFET low-side MOSFET in this case) with PWM_NB  
= 1, AGC[1:0] = 01B or 10B, POCHGDIS = 0 (post-charge enabled).  
This control scheme is applicable for the following cases:  
1. EN_GEN_CHECK = 0 (detection of FW/Active MOSFET disabled); HBxMODE[1:0] = 10B (HS MOSFET is  
considered as active MOSFET by default).  
2. EN_GEN_CHECK = 1 (detection of active / FW MOSFET enabled); HS MOSFET detected as active MOSFET;  
HBxMODE[1:0] = 01B or 10B.  
Note:  
If the synchronized LS PWM rising edge occurs before the end of tHBxCCP active, then the device  
prevents an activation of the LS MOSFET until tHBxCCP active elapses. In other words, the LS PWM  
rising edge is ignored until the end of tHBxCCP active.  
Datasheet  
94  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
External HSx PWM  
signal  
t
t
tPWM_SYNCH  
tPDCHGx  
Synchronized HSx  
PWM signal  
Discharge phase  
HSx internal  
drive signal  
tHBxCCP Active  
IHOLD  
0
t
- IHOLD  
- IHOLD  
- IHOLD  
- IDCHGx  
- IDCHGx  
- IPREDCHGx  
tOFF timeout  
Active  
Hard off  
- IHARDOFF  
VGS_HSx  
t
t
tFALLx  
VSHH  
VSHx  
VSHx < VSHL right before the activation of HSx  
HSx detected as active MOSFET  
tDOFFx  
VS  
VSHH  
VSHL  
VSHL  
IDS_HSDx  
IPHASE  
t
Synchronized LSx  
PWM signal  
t
tHBxBLANK FW  
LSx internal  
drive signal  
tFVDS  
ICHGFWx  
IHOLD  
IHOLD  
t
- IHOLD  
Figure 54 Turn-off of an active MOSFET in PWM mode with active gate control, HS as active MOSFET,  
LS as FW MOSFET. two PWM inputs per half-bridge, active gate control enabled. PWM_NB=1.  
11.3.5  
Status bits for regulation of turn-on and turn-off delay times  
The control bits TDREGx (TDREG) indicate if tDONx and tDOFFx of the half-bridge x, using the adaptive control  
scheme (AGC = 10B or 11B), are in regulation.  
Datasheet  
95  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
The half-bridge x is considered in regulation if one of the following conditions is met:  
Condition 1: The effective turn-on and turn-off delays are equal to the configured delays for at least eight  
cumulative PWM cycle (HBx tDON counter 8 and HBx tDOFF counter 8). For each PWM cycle  
if tDONxEFF1) = TDONx2), x = 1.. 3, HBx tDON counter is incremented  
if tDONxEFF1) TDONx2), x = 1.. 3, HBx tDON counter is decremented  
if tDOFFxEFF1) = TDOFFx3), x = 1.. 3, HBx tDOFF counter is incremented  
if tDOFFxEFF 1) TDOFFx3), x = 1.. 3, HBx tDOFF counter is decremented  
Condition 2: The error between the effective delays ((tDONxEFF-TDONx) and(tDOFFxEFF-TDOFFx ))  
changes its sign three times consecutively  
1) Refer to EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3  
2) Refer to TDON_HB_CTRL  
3) Refer to TDOFF_HB_CTRL  
Datasheet  
96  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.3.6  
Gate driver current  
Each gate driver is able to source and sink currents from 0.5 mA to 150 mA, with 64 steps.  
150  
140  
130  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
55  
60  
ICHG[5:0]dec  
Figure 55 Configurable discharge currents in PWM operation  
Datasheet  
97  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 27  
Charge currents and initial precharge currents  
Parameter Nom. current  
ICHGx[5:0],  
Max. deviation to nominal  
values [%]  
PCHGINITx[5:0]  
name  
[mA]  
000000B  
000001B  
000010B  
000011B  
000100B  
000101B  
000110B  
000111B  
001000B  
001001B  
001010B  
001011B  
001100B  
001101B  
001110B  
001111B  
010000B  
010001B  
010010B  
010011B  
010100B  
010101B  
010110B  
010111B  
011000B  
011001B  
011010B  
011011B  
011100B  
011101B  
011110B  
011111B  
100000B  
100001B  
100010B  
100011B  
ICHG0  
0.5  
+/- 60%  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 55%  
+/- 55%  
+/- 55%  
+/- 55%  
+/- 55%  
+/- 55%  
+/- 40%  
+/- 40%  
+/- 40 %  
+/- 40 %  
+/- 40%  
+/- 40 %  
+/- 40%  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
ICHG1  
0.7  
ICHG2  
1.0  
ICHG3  
1.4  
ICHG4  
1.8  
ICHG5  
2.4  
ICHG6  
3.0  
ICHG7  
3.8  
ICHG8  
4.7  
ICHG9  
5.8  
ICHG10  
ICHG11  
ICHG12  
ICHG13  
ICHG14  
ICHG15  
ICHG16  
ICHG17  
ICHG18  
ICHG19  
ICHG20  
ICHG21  
ICHG22  
ICHG23  
ICHG24  
ICHG25  
ICHG26  
ICHG27  
ICHG28  
ICHG29  
ICHG30  
ICHG31  
ICHG32  
ICHG33  
ICHG34  
ICHG35  
6.9  
8.1  
9.4  
10.8  
12.2  
13.7  
15.3  
17.1  
19  
21  
23  
25  
27.1  
29.3  
31.6  
34  
36.5  
39  
41.6  
44.2  
46.9  
49.7  
52.5  
55.3  
58.1  
60.8  
Datasheet  
98  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 27  
Charge currents and initial precharge currents (cont’d)  
Parameter Nom. current  
ICHGx[5:0],  
Max. deviation to nominal  
values [%]  
PCHGINITx[5:0]  
name  
ICHG36  
ICHG37  
ICHG38  
ICHG39  
ICHG40  
ICHG41  
ICHG42  
ICHG43  
ICHG44  
ICHG45  
ICHG46  
ICHG47  
ICHG48  
ICHG49  
ICHG50  
ICHG51  
ICHG52  
ICHG53  
ICHG54  
ICHG55  
ICHG56  
ICHG57  
ICHG58  
ICHG59  
ICHG60  
ICHG61  
ICHG62  
ICHG63  
[mA]  
63.6  
66.5  
69.4  
72.3  
75.2  
78.1  
81.1  
84.1  
87.1  
90.2  
93.3  
96.4  
99.5  
102.7  
105.8  
109  
100100B  
100101B  
100110B  
100111B  
101000B  
101001B  
101010B  
101011B  
101100B  
101101B  
101110B  
101111B  
110000B  
110001B  
110010B  
110011B  
110100B  
110101B  
110110B  
110111B  
111000B  
111001B  
111010B  
111011B  
111100B  
111101B  
111110B  
111111B  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
112.2  
115.4  
118.7  
122  
125.3  
128.7  
132.1  
135.5  
139  
142.5  
146  
150  
Datasheet  
99  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
150  
140  
130  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
55  
60  
IDCHG[5:0]dec  
Figure 56 Configurable discharge currents in PWM operation  
Datasheet  
100  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 28  
Discharge currents and initial predischarge currents  
IDCHG[5:0],  
PDCHGINITx[5:0]  
Parameter  
name  
Nom. current  
[mA]  
Max. deviation to nominal  
values [%]  
000000B  
000001B  
000010B  
000011B  
000100B  
000101B  
000110B  
000111B  
001000B  
001001B  
001010B  
001011B  
001100B  
001101B  
001110B  
001111B  
010000B  
010001B  
010010B  
010011B  
010100B  
010101B  
010110B  
010111B  
011000B  
011001B  
011010B  
011011B  
011100B  
011101B  
011110B  
011111B  
100000B  
100001B  
100010B  
100011B  
IDCHG0  
0.5  
+/- 60%  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 60 %  
+/- 40%  
+/- 40%  
+/- 40 %  
+/- 40 %  
+/- 40%  
+/- 40 %  
+/- 40%  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 40 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
IDCHG1  
0.7  
IDCHG2  
1.0  
IDCHG3  
1.4  
IDCHG4  
1.8  
IDCHG5  
2.4  
IDCHG6  
3.0  
IDCHG7  
3.8  
IDCHG8  
4.7  
IDCHG9  
5.8  
IDCHG10  
IDCHG11  
IDCHG12  
IDCHG13  
IDCHG14  
IDCHG15  
IDCHG16  
IDCHG17  
IDCHG18  
IDCHG19  
IDCHG20  
IDCHG21  
IDCHG22  
IDCHG23  
IDCHG24  
IDCHG25  
IDCHG26  
IDCHG27  
IDCHG28  
IDCHG29  
IDCHG30  
IDCHG31  
IDCHG32  
IDCHG33  
IDCHG34  
IDCHG35  
6.9  
8.1  
9.4  
10.7  
12.1  
13.5  
15.1  
16.8  
18.6  
20.5  
22.5  
24.5  
26.5  
28.7  
30.9  
33.2  
35.7  
38.2  
40.8  
43.4  
46.1  
48.8  
51.5  
54.2  
56.9  
59.6  
Datasheet  
101  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 28  
Discharge currents and initial predischarge currents (cont’d)  
IDCHG[5:0],  
PDCHGINITx[5:0]  
Parameter  
name  
Nom. current  
[mA]  
Max. deviation to nominal  
values [%]  
100100B  
100101B  
100110B  
100111B  
101000B  
101001B  
101010B  
101011B  
101100B  
101101B  
101110B  
101111B  
110000B  
110001B  
110010B  
110011B  
110100B  
110101B  
110110B  
110111B  
111000B  
111001B  
111010B  
111011B  
111100B  
111101B  
111110B  
111111B  
IDCHG36  
IDCHG37  
IDCHG38  
IDCHG39  
IDCHG40  
IDCHG41  
IDCHG42  
IDCHG43  
IDCHG44  
IDCHG45  
IDCHG46  
IDCHG47  
IDCHG48  
IDCHG49  
IDCHG50  
IDCHG51  
IDCHG52  
IDCHG53  
IDCHG54  
IDCHG55  
IDCHG56  
IDCHG57  
IDCHG58  
IDCHG59  
IDCHG60  
IDCHG61  
IDCHG62  
IDCHG63  
62.4  
65.2  
68  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
+/- 30 %  
70.8  
73.7  
76.6  
79.5  
82.5  
85.5  
88.5  
91.5  
94.6  
97.7  
100.9  
104.2  
107.5  
110.8  
114.2  
117.6  
121  
124.5  
128  
131.5  
135.1  
138.7  
142.3  
145.8  
150  
11.4  
Passive discharge  
Resistors (RGGND) between the gate of GHx and GND, and between GLx and GND, ensure that the external  
MOSFETs are turned off in the following conditions:  
VCC1 undervoltage  
HBxMODE = 00B in Normal Mode  
CPEN = 0 in Normal Mode  
CSA Overcurrent detection with OCEN = 1 in normal mode  
Datasheet  
102  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
VS overvoltage or VSINT overvoltage  
Charge pump undervoltage and charge pump blank time (tCPUVBLANK  
)
Charge pump overtemperature (CP_OT)  
VDS overvoltage after active discharge in Normal Mode  
In Init Mode, Stop Mode, Fail Safe Mode, Restart Mode and Sleep Mode (exceptions for low-sides in parking  
braking and VS / VSINT overvoltage braking , refer to Chapter 11.6 and Chapter 12.10.3)  
11.5  
Slam mode  
The slam mode is applicable in Normal Mode.  
If the SLAM bit is set in BRAKE register:  
1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static  
discharge current during their respective tHBxCCP Active.  
2. Then charge pump is deactivated independently from CPEN  
3. Then PWM1/CRC input pin is mapped to LS1, LS2, LS3, independently from PWM_NB, HBxMODE and  
HBx_PWM_EN  
a) If PWM1/CRC is High, then the low-side MOSFETs are turned on within tON_BRAKE  
.
b) If PWM1/CRC is Low, then the low-side MOSFETs are turned off within tOFF_BRAKE  
.
There is also the possibility to disable selectively the LSx in SLAM mode.  
11.6  
Parking braking mode  
If PARK_BRK_EN bit is set, while the device goes in Sleep Mode or in Stop Mode:  
1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static  
discharge current during their respective tHBxCCP Active.  
2. Then charge pump is deactivated independently from CPEN bit.  
3. Then the passive discharge (RGGND) of the low-sides is deactivated, the passive discharge of the high-sides  
are activated  
4. If PWM1/CRC is High, then the low-side MOSFETs are turned on within tON_BRAKE  
.
Refer to Chapter 12.10.2 for the protection of the of low-side MOSFETs against short circuits when the parking  
braking mode is activated.  
Datasheet  
103  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.7  
Charge pump  
A dual-stage charge pump supplies the gate drivers for the high-side and low-side MOSFETs. It requires three  
external capacitors connected between CPC1N and CPC1P, CPC2N and CPC2P, VS and CP.  
The buffer capacitor between VS and CP must have a capacitance equal or higher than 470 nF.  
CCP ≥ 470 nF  
CCP1  
CCP2  
VS  
CP  
Single/dual stage  
charge pump  
Precharge  
Logic  
Figure 57 Charge pump - Block diagram  
Logic or normal level MOSFETs  
The regulation of the charge pump outputs voltage can be configured depending on the type of MOSFET.  
FET_LVL = 0: Logic level MOSFETs are selected:  
VCP - VS = VCP3 (11 V typ. at VS > 8 V).  
The high-side gate-source voltage GHx - SHx is VGH4 (VS > 8 V).  
The low-side gate-source voltage GLx - SL is VGH3 (VS > 8 V).  
FET_LVL = 1: Normal level MOSFETs are selected:  
VCP - VS = VCP1(15 V typ. at VS > 8 V).  
The high-side and low-side gate-source voltage GHx - SHx or GLx - SL is VGH1 (VS > 8 V).  
CPSTGA = 0 (default, see GENCTRL), the device operates with the dual-stage charge pump.  
If CPSTGA = 1, the device switches to single-stage or dual-stage charge pump automatically:  
If VS > VCPSO DS: the TLE9564QX switches from a dual-stage to a single-stage charge pump.  
If VS < VCPSO SD: the TLE9564QX switches from single-stage to dual-stage charge pump.  
The operation with the single-stage charge pump reduces the current consumption from the VS pin.  
Datasheet  
104  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.8  
Frequency modulation  
A modulation of the charge pump frequency can be activated to reduce the peak emission.  
The modulation frequency is set by the control bit FMODE in GENCTRL:  
FMODE = 0: No modulation.  
FMODE = 1: Modulation frequency = 15.6 kHz (default).  
Datasheet  
105  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
11.9  
Electrical characteristics gate driver  
The electrical characteristics related to the gate driver are valid for VCP > VS + 8.5 V  
Table 29  
Electrical characteristics: gate drivers  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C,  
VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx  
and IGHx (unless otherwise specified).  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Comparators  
SHx High Threshold  
SHx Low Threshold  
SHx comparator delay  
MOSFET Driver Output  
VSHH  
VSHL  
tSHx  
VS - 2.6  
1.9  
VS - 1.9  
2.6  
V
P_12.11.1  
P_12.11.2  
P_12.11.3  
V
Referred to GND  
1)  
12  
30  
ns  
High Level Output Voltage VGH1  
GHx vs. SHx and GLx vs. SL  
10  
7
11.5  
12.5  
12.5  
V
V
2) VS 8 V ,  
CLoad = 10 nF,  
ICP = -12 mA,  
FET_LVL = 1  
P_12.11.4  
High Level Output Voltage VGH2  
VS = 6 V,  
P_12.11.5  
GHx vs. SHx and GLx vs. SL  
C
Load = 10 nF,  
ICP = -6 mA,  
FET_LVL = 1  
High Level Output Voltage VGH3  
GLx vs. SL  
10  
12.5  
12.5  
V
V
3) VS 6 V ,  
CLoad = 10 nF,  
FET_LVL = 0  
P_12.11.6  
P_12.11.7  
High Level Output Voltage VGH4  
8.5  
10  
2) VS 8 V ,  
GHx vs. SHx  
C
Load = 10 nF,  
ICP = -12 mA,  
FET_LVL = 0  
High Level Output Voltage VGH5  
7
12.5  
V
VS = 6 V,  
P_12.11.8  
GHx vs. SHx  
CLOAD= 10 nF,  
ICP = -6 mA,  
FET_LVL =0  
1)  
Charge current  
Charge current  
Charge current  
Charge current  
ICHG0  
ICHG8  
ICHG16  
ICHG32  
-60% 0.5  
-55% 4.7  
-40% 15.3  
-30% 52.5  
+60% mA  
+55% mA  
+40% mA  
+30% mA  
ICHG = 0D  
P_12.11.70  
P_12.11.71  
P_12.11.72  
P_12.11.73  
CLoad = 2.2 nF  
4)  
4)  
4)  
4)  
VS 8V, VGSVGS(ON)  
1)  
ICHG =8 D  
CLoad = 2.2 nF  
VS 8V, VGSVGS(ON)  
1)  
ICHG =16 D  
CLoad = 2.2 nF  
VS 8V, VGSVGS(ON)  
1)  
ICHG =32 D  
CLoad = 10 nF  
VS 8V, VGSVGS(ON)  
Datasheet  
106  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 29  
Electrical characteristics: gate drivers (cont’d)  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C,  
VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx  
and IGHx (unless otherwise specified).  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
Charge current  
ICHG48  
-30% 99.5  
-30% 150  
-60% -0.5  
-55% -4.7  
-40% -15.1  
-30% -51.5  
-30% -97.7  
-30% -150  
+30% mA  
ICHG =48 D  
P_12.11.74  
CLoad = 10 nF  
VS 8V, VGSVGS(ON)  
4)  
4)  
1)  
Charge current  
ICHG63  
+30% mA  
+60% mA  
ICHG =63 D  
P_12.11.75  
P_12.11.76  
P_12.11.77  
P_12.11.78  
P_12.11.79  
P_12.11.80  
P_12.11.81  
CLoad = 22 nF  
VS 8V, VGSVGS(ON)  
1)  
Discharge current  
Discharge current  
Discharge current  
Discharge current  
Discharge current  
Discharge current  
IDCH0  
IDCHG =0 D  
CLoad = 2.2 nF  
VS 8V,VGSVGS(OFF1)  
1)  
IDCH8  
55%  
mA  
IDCHG =8 D  
CLoad = 2.2 nF  
VS 8V,VGSVGS(OFF1)  
1)  
IDCHG16  
IDCHG32  
IDCHG48  
IDCHG63  
+40% mA  
+30% mA  
+30% mA  
+30% mA  
IDCHG =16 D  
CLoad = 2.2 nF  
VS 8V,VGSVGS(OFF1)  
1)  
IDCHG =32 D  
CLoad = 10 nF  
VS 8V,VGSVGS(OFF2)  
1)  
IDCHG = 48D  
CLoad = 10 nF  
VS 8V,VGSVGS(OFF2)  
1)  
IDCHG = 63D  
CLoad = 22 nF  
VS 8V,VGSVGS(OFF2)  
1)5)  
Charge current  
temperature drift  
ICHG0,TDrift  
ICHG8,TDrift  
-37% -12% 15%  
ICHG = 0D  
P_12.11.119  
P_12.11.120  
P_12.11.121  
P_12.11.122  
P_12.11.123  
P_12.11.124  
P_12.11.125  
1)5)  
Charge current  
temperature drift  
-17% 1%  
20%  
18%  
9%  
ICHG = 8D  
1)5)  
Charge current  
temperature drift  
ICHG16,TDrift -12% 3%  
ICHG32,TDrift -11% -1%  
ICHG48,TDrift -7.5% 0.5%  
ICHG63,TDrift -5.5% 1.5%  
ICHG = 16D  
1)5)  
Charge current  
temperature drift  
ICHG = 32D  
1)5)  
Charge current  
temperature drift  
8%  
ICHG = 48D  
1)5)  
Charge current  
temperature drift  
8.5%  
IDCHG = 63D  
1)5)  
Discharge current  
temperature drift  
IDCHG0,TDrift -29% -4.5% 20%  
IDCHG = 0D  
Datasheet  
107  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 29  
Electrical characteristics: gate drivers (cont’d)  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C,  
VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx  
and IGHx (unless otherwise specified).  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)5)  
Discharge current  
temperature drift  
IDCHG8,TDrift -8%  
IDCHG16,TDrift -4%  
IDCHG32,TDrift -4%  
IDCHG48,TDrift -4%  
8.5%  
26%  
IDCHG = 8D  
P_12.11.126  
P_12.11.127  
P_12.11.128  
P_12.11.129  
P_12.11.130  
1)5)  
1)5)  
1)5)  
1)5)  
Discharge current  
temperature drift  
9.5%  
4.5%  
3.5%  
23%  
13%  
10%  
9.5%  
IDCHG = 16D  
IDCHG = 32D  
IDCHG = 48D  
IDCHG = 63D  
Discharge current  
temperature drift  
Discharge current  
temperature drift  
Discharge current  
temperature drift  
IDCHG63,TDrift -3.5% 3.5%  
1)6)  
Charge current VS drift  
Charge current VS drift  
Charge current VS drift  
Charge current VS drift  
Charge current VS drift  
Charge current VS drift  
ICHG0,VsDrift  
ICHG8,VsDrift  
3%  
4.5%  
6%  
6%  
ICHG = 0D  
P_12.11.131  
P_12.11.132  
P_12.11.133  
P_12.11.134  
P_12.11.135  
P_12.11.136  
P_12.11.137  
P_12.11.138  
P_12.11.139  
P_12.11.140  
P_12.11.141  
P_12.11.142  
P_12.11.22  
1)6)  
4.5%  
7.5%  
7.5%  
5.8%  
4.5%  
2.8%  
ICHG = 8D  
1)6)  
ICHG16,VsDrift 4%  
ICHG32,VsDrift 2%  
5.8%  
3.8%  
ICHG = 16D  
ICHG = 32D  
ICHG = 48D  
ICHG = 63D  
IDCHG = 0D  
IDCHG = 8D  
1)6)  
1)6)  
1)6)  
1)6)  
1)6)  
ICHG48,VsDrift -0.5% 2%  
ICHG63,VsDrift -2.3% 0.3%  
Discharge current VS drift IDCHG0,VsDrift -3%  
Discharge current VS drift IDCHG8,VsDrift -3%  
-1.5% 0%  
-0.5% 2%  
1)6)  
1)6)  
1)6)  
1)6)  
Discharge current VS drift IDCHG16,VsDrift -3.3% -0.3% 2.3%  
IDCHG = 16D  
IDCHG = 32D  
IDCHG = 48D  
Discharge current VS drift IDCHG32,VsDrift -2%  
0%  
2%  
Discharge current VS drift IDCHG48,VsDrift -1.5% 0%  
Discharge current VS drift IDCHG63,VsDrift -1.5% 0.2%  
1.5%  
1.5%  
30  
IDCHG = 63D  
1)  
Passive discharge  
resistance between  
GHx/GLx and GND  
RGGND  
10  
20  
kΩ  
1)7)  
Resistor between SHx and RSHGND  
GND  
10  
20  
22  
30  
35  
kΩ  
P_12.11.23  
P_12.11.24  
Low RDSON mode  
RONCCP  
1) VS = 13.5 V  
V
CP = VS + 14 V  
ICHG = IDCHG = 63D  
Gate Drivers Dynamic Parameters  
Datasheet  
108  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 29  
Electrical characteristics: gate drivers (cont’d)  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C,  
VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx  
and IGHx (unless otherwise specified).  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Gate Driver turn-on delay tDGDRV_ON1  
400  
ns  
8) From PWM9)  
P_12.11.25  
Time  
rising edge to 20%  
of ICHGx  
x = 0 to 63,  
Load = 10 nF,  
,
C
BDFREQ = 0  
Gate Driver turn-on delay tDGDRV_ON2  
300  
ns  
8) From PWM9)  
P_12.11.93  
Time  
rising edge to 20%  
of ICHGx  
x = 0 to 63,  
Load = 10 nF,  
BDFREQ = 1  
8) From 20% of ICHGx P_12.11.26  
to ICHGx  
x = 0 to 63,  
Load = 10 nF  
,
C
Gate Driver current turn-on tGDRV_RISE(ON)  
rise time  
30  
50  
ns  
ns  
,
C
Gate Driver turn-off delay tDGDRV_OFF1  
Time  
400  
8) From PWM9)  
rising edge to 20%  
P_12.11.27  
P_12.11.94  
P_12.11.28  
of IDCHGx  
x = 0 to 63,  
Load = 10 nF,  
,
C
BDFREQ = 0  
8) From PWM9)  
rising edge to 20%  
Gate Driver turn-off delay tDGDRV_OFF2  
Time  
300  
50  
ns  
ns  
of IDCHGx  
x = 0 to 63,  
Load = 10 nF,  
,
C
BDFREQ = 1  
Gate Driver current turn-off tGDRV_RISE(OFF  
30  
8) From 20% of  
IDCHGx to IDCHGx  
x = 0 to 63,  
rise time  
,
)
C
Load = 10 nF  
External MOSFET gate-to- VGS(ON)1  
source voltage - ON  
7
V
V
V
V
1) VS 8 V,  
FET_LVL=1  
1) VS 8 V,  
FET_LVL=1  
1) VS 8 V,  
FET_LVL=0  
1) IDCHGx 24D(P_12.11.30  
P_12.11.29  
P_12.11.102  
P_12.11.103  
External MOSFET gate-to- VGS(ON)1  
source voltage - ON  
7
External MOSFET gate-to- VGS(ON)2  
source voltage - ON  
5.5  
External MOSFET gate-to- VGS(OFF)1  
1.5  
source voltage - OFF  
41 mA typ.)  
Datasheet  
109  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 29  
Electrical characteristics: gate drivers (cont’d)  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C,  
VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx  
and IGHx (unless otherwise specified).  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
External MOSFET gate-to- VGS(OFF)2  
source voltage - OFF  
5
V
1)IDCHGx > 28D(>  
41 mA typ.)  
P_12.11.101  
P_12.11.33  
P_12.11.82  
PWM synchronization  
delay  
tPWM_SYNCH0 80  
tPWM_SYNCH1 40  
200  
100  
ns  
ns  
1) BDFREQ = 0  
PWM synchronization  
delay  
1) BDFREQ= 1  
Bridge driver frequency  
Bridge driver frequency  
Pre-charge time  
tBDFREQ0  
tBDFREQ1  
tPCHG000  
16.8  
33.7  
80  
18.75 20.7  
MHz 1) BDFREQ= 0  
MHz 1) BDFREQ= 1  
P_12.11.83  
P_12.11.84  
P_12.11.34  
37.5  
107  
42.3  
140  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1) TPCHG = 000,  
BDFREQ= 0 or 1  
1) TPCHG = 001,  
BDFREQ= 0 or 1  
1) TPCHG = 010,  
BDFREQ= 0 or 1  
1) TPCHG = 011,  
BDFREQ= 0 or 1  
1) TPCHG = 100,  
BDFREQ= 0 or 1  
1) TPCHG = 101,  
BDFREQ= 0 or 1  
1) TPCHG = 110,  
BDFREQ= 0 or 1  
1) TPCHG = 111,  
BDFREQ= 0 or 1  
1) TPDCHG = 000,  
BDFREQ= 0 or 1  
1) TPDCHG = 001,  
BDFREQ= 0 or 1  
1) TPDCHG = 010,  
BDFREQ= 0 or 1  
1) TPDCHG = 011,  
BDFREQ= 0 or 1  
1) TPDCHG = 100,  
BDFREQ= 0 or 1  
1) TPDCHG = 101,  
BDFREQ= 0 or 1  
Pre-charge time  
Pre-charge time  
Pre-charge time  
Pre-charge time  
Pre-charge time  
Pre-charge time  
Pre-charge time  
Pre-discharge time  
Pre-discharge time  
Pre-discharge time  
Pre-discharge time  
Pre-discharge time  
Pre-discharge time  
Pre-discharge time  
tPCHG001  
tPCHG010  
tPCHG011  
tPCHG100  
tPCHG101  
tPCHG110  
tPCHG111  
tPDCHG000  
tPDCHG001  
tPDCHG010  
tPDCHG011  
tPDCHG100  
tPDCHG101  
tPDCHG110  
130  
170  
210  
250  
420  
600  
840  
80  
160  
214  
267  
320  
533  
747  
1067  
107  
160  
214  
267  
320  
533  
747  
190  
260  
330  
390  
630  
900  
1260  
140  
190  
260  
330  
390  
630  
900  
P_12.11.35  
P_12.11.36  
P_12.11.37  
P_12.11.85  
P_12.11.86  
P_12.11.87  
P_12.11.88  
P_12.11.38  
P_12.11.39  
P_12.11.40  
P_12.11.41  
P_12.11.89  
P_12.11.90  
P_12.11.91  
130  
170  
210  
250  
420  
600  
1) TPDCHG = 110,  
BDFREQ= 0 or 1  
Datasheet  
110  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 29  
Electrical characteristics: gate drivers (cont’d)  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C,  
VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx  
and IGHx (unless otherwise specified).  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Pre-discharge time  
Discharge timeout  
tPDCHG111  
840  
1067  
1260  
ns  
1) TPDCHG = 111,  
BDFREQ= 0 or 1  
1) PWM_NB=1B  
P_12.11.92  
P_12.11.9  
tOFF_TIMEOUT 3.2  
4
4.8  
µs  
Low-side gate driver, CP off - Slam mode, parking braking and VS overvoltage braking  
LS turn-on time, CP off  
tON_BRAKE  
tOFF_BRAKE  
VGLx_BRAKE  
5
4.5  
0.7  
9
µs  
µs  
V
CLOAD = 10 nF  
VGLx-VSL = 5 V,  
VS > 8 V or VSINT > 8 V  
P_12.11.42  
P_12.11.43  
LS turn-off time, CP off  
2
CLOAD = 10 nF  
VGLx-VSL = 1.5 V,  
VS > 8 V or VSINT > 8 V  
High output voltage  
GLx - SL  
10  
VS > 8 V or VSINT > 8 V P_12.11.48  
Charge pump  
1)  
Charge Pump Frequency  
fCP  
250  
kHz  
V
P_12.11.49  
Output Voltage VCP vs. VS VCPmin1  
8.5  
VS = 6 V, ICP = - 6 mA, P_12.11.50  
FET_LVL =1  
Output Voltage VCP vs. VS VCPmin2  
7.5  
12  
V
V
VS = 6 V, ICP = - 6 mA, P_12.11.51  
FET_LVL =0  
Regulated CP output  
voltage, VCP vs. VS  
VCP1  
15  
17  
8 V < VS < 23 V  
ICP = - 12 mA11)  
CPSTGA = 0,  
FET_LVL =1  
P_12.11.52  
P_12.11.53  
P_12.11.54  
P_12.11.55  
,
Regulated CP output  
voltage, VCP vs. VS  
VCP2  
12  
7.5  
7.5  
5
15  
11  
11  
17  
13  
13  
60  
V
18 V < VS < 23 V  
I
CP = - 12 mA11)  
,
CPSTGA = 1,  
FET_LVL =1  
Regulated CP output  
voltage, VCP vs. VS  
VCP3  
V
8 V < VS < 23 V  
I
CP = - 12 mA11)  
,
CPSTGA = 0,  
FET_LVL =0  
Regulated CP output  
voltage, VCP vs. VS  
VCP4  
V
13 V < VS < 23 V  
I
CP = - 12 mA11)  
,
CPSTGA = 0,  
FET_LVL =0  
1)10)11)18 V<VS< 23 V P_12.11.56  
(25%), ICP = 0 ,  
Turn-on time  
tON_VCP1  
µs  
CPSTGA = 1,  
FET_LVL =1  
Datasheet  
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Rev. 1.0  
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TLE9564QX  
BLDC Motor System IC  
Gate Drivers  
Table 29  
Electrical characteristics: gate drivers (cont’d)  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C,  
VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx  
and IGHx (unless otherwise specified).  
Parameter  
Symbol  
Values  
Typ.  
30  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Rise time  
tRISE_VCP1  
5
60  
µs  
µs  
µs  
1)10)11)18 V < VS < 23 P_12.11.57  
V (25%-75%)  
ICP = 0 , CPSTGA = 1,  
FET_LVL =1  
1)10)11) 13 V < VS <23 P_12.11.58  
V (25%), ICP = 0,  
CPSTGA = 1,  
FET_LVL =0  
Turn-on time  
Rise time  
tON_VCP2  
20  
5
60  
30  
17  
120  
60  
tRISE_VCP2  
1)10)11)13 V < VS < 23 P_12.11.59  
V (25%-75%)  
ICP = 0 , CPSTGA = 1,  
FET_LVL =0  
Automatic switch over dual VCPSO DS  
to single stage charge  
pump  
16  
18  
V
V
V
V
CPSTGA = 1,  
FET_LVL =1,  
VS rising  
P_12.11.60  
P_12.11.61  
P_12.11.62  
P_12.11.64  
Automatic switch over dual VCPSO DS  
to single stage charge  
pump  
11.5  
15.5  
11  
12.25 13  
CPSTGA = 1,  
FET_LVL = 0,  
VS rising  
Automatic switch over  
single to dual stage charge  
pump  
VCPSO SD  
16.5  
17.5  
CPSTGA = 1,  
FET_LVL =1,  
VS falling  
Automatic switch over  
single to dual stage charge  
pump  
VCPSO SD  
11.75 12.5  
CPSTGA = 1,  
FET_LVL = 0,  
VS falling  
Charge pump switch over VCPSO HY  
hysteresis  
0.5  
V
1) CPSTGA = 1  
VCPSO DS - VCPSO SD  
11) 8 V < VS < 28 V  
CPSTGA = 0  
P_12.11.65  
P_12.11.68  
Charge pump minimum  
output current  
ICPOC1  
-12  
mA  
FET_LVL =1  
Charge pump minimum  
output current  
ICPOC2  
-12  
mA  
11) 8 V < VS < 28 V  
CPSTGA = 0  
P_12.11.69  
FET_LVL =0  
Datasheet  
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BLDC Motor System IC  
Gate Drivers  
Table 29  
Electrical characteristics: gate drivers (cont’d)  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C,  
VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx  
and IGHx (unless otherwise specified).  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Digital PWMx Inputs  
High Level Input Voltage  
Threshold  
VPWMH  
0.7 ×  
Vcc1  
V
P_12.11.95  
P_12.11.96  
P_12.11.97  
P_12.11.98  
Low Level Input Voltage  
Threshold  
VPWML  
0.3 ×  
Vcc1  
V
1)  
PWMx Input Hysteresis  
VPWM,hys  
RPD_PWM  
0.12 ×  
Vcc1  
V
PWMx Pull-down  
Resistance  
20  
40  
80  
kΩ  
CRC Select; Pin PWM1/CRC  
12)  
1)  
Config Pull-up Resistance RCFG  
100  
10  
kΩ  
P_12.11.99  
Config Select Filter Time tCFG_F  
5
14  
µs  
P_12.11.105  
1) Not subject to production test, specified by design.  
2) Independent from CPSTGA.  
3) ICP = -12 mA for VS 8 V, ICP = 6 mA for VS = 6 V.  
4) VGS(ON) = VGS(ON)1 if FET_LVL = 1, VGS(ON) = VGS(ON)2 if FET_LVL = 0.  
5) Tj reference = 25°C  
6) Valid for VS = 8 to 19 V, VS reference = 13.5 V  
7) This resistance is the resistance between GHx and GND connected through a diode to SHx. As a consequence, the  
voltage at SHx can rise up to 0.6 V typ. before it is discharged through the resistor.  
8) Not subject to production test, specified by design.  
9) External PWM signal.  
10) Parameter dependent on the capacitance CCP  
.
11) CCPC1 = CCPC2 = 220 nF, CCP = 470 nF. Other CCP values higher than 470 nF can be used. Note that this capacitor  
influences the charge pump rise and turn-on times, and the charge , VCP ripple voltage when charging the gate of a  
MOSFET.  
12) Config Pull-up will be only active during startup-phase for checking external pull-down. After checking, the typ. 40 kΩ  
Pull-down resistance will be present.  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Supervision Functions  
12  
Supervision Functions  
12.1  
Reset Function  
VCC1  
RSTN  
Resetlogic  
Incl. filter & delay  
Figure 58 Reset Block Diagram  
12.1.1  
Reset Output Description  
The reset output pin RSTN provides a reset information to the microcontroller, for example, in the event that  
the output voltage has fallen below the undervoltage threshold VRTx. In case of a reset event, the reset output  
RSTN is pulled to low after the filter time tRF and stays low as long as the reset event is present plus a reset  
delay time tRD1 or tRD2 depending on the value in RSTN_DEL. When connecting the device to battery voltage,  
the reset signal remains low initially. When the output voltage VCC1 has reached the reset default threshold  
VRT1,r, the reset output RSTN is released to high after the reset delay time tRD1. A reset can also occur due to a  
watchdog trigger failure. The reset threshold can be adjusted via SPI, the default reset threshold is VRT1,f. The  
RSTN pin has an integrated pull-up resistor. In case reset is triggered, it will be pulled low for VCC1 1V and  
for VSINT VPOR,f (see also Chapter 12.3).  
The timings for the RSTN triggering regarding VCC1 undervoltage and watchdog trigger is shown in Figure 59.  
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Supervision Functions  
VCC1  
VRT1  
t < tRF  
The reset threshold can be  
configured via SPI in  
Normal Mode, default is VRT1  
undervoltage  
t
tCW  
tOW  
tRD1  
tRDx (config)  
tCW  
tLW  
tLW  
tCW  
tOW  
SPI  
SPI  
Init  
WD  
Trigger  
WD  
Trigger  
SPI  
Init  
t
t
tRF  
RSTN  
t
t
t
LW= long open window  
CW= closed window  
OW= open window  
Init  
Normal  
Restart  
Normal  
Reset_timing.vsd  
Figure 59 Reset Timing Diagram  
12.1.2  
Soft Reset Description  
In Normal Mode and Stop Mode, it is also possible to trigger a device internal reset via a SPI command in order  
to bring the device into a defined state in case of failures. In this case the microcontroller must send a SPI  
command and set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as this command becomes valid,  
the device is set back to Init Mode and all SPI registers are set to their default values (see SPI Chapter 13.5.1  
and Chapter 13.6.1).  
Two different soft reset configurations are possible via the SPI bit SOFT_RESET_RO:  
SOFT_RESET_RO = ‘0’: The reset output (RSTN) is triggered when the soft reset is executed (default  
setting) The configured reset delay time tRD1 or tRD2 is applied depending on the value in RSTN_DEL).  
SOFT_RESET_RO = ‘1’: The reset output (RSTN) is not triggered when the soft reset is executed.  
Note:  
The device must be in Normal Mode or Stop Mode when sending this command.  
Otherwise, the command will be ignored.  
Note:  
Allow CRC configuration after software-reset - or better check once again via SPI after software  
reset.  
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Supervision Functions  
12.2  
Watchdog Function  
The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset or move  
the device to Fail Safe Mode, if the microcontroller stops serving the watchdog due to a lock up in the software.  
Two different types of watchdog functions are implemented and can be selected via the bit WD_CFG:  
Time-Out Watchdog (default value)  
Window Watchdog  
The respective watchdog functions can be selected and programmed in Normal Mode. The configuration stays  
unchanged in Stop Mode.  
Please refer to Table 30 to match the device modes with the respective watchdog modes.  
Table 30 Watchdog Functionality by modes  
Mode  
Watchdog Mode  
Remarks  
Init Mode  
Starts with Long Open  
Window  
Watchdog starts with Long Open Window after RSTN  
is released.  
Normal Mode  
WD Programmable  
Window Watchdog, Time-Out watchdog or switched  
off for Stop Mode.  
Stop Mode  
Sleep Mode  
Watchdog is fixed or off  
Off  
Device will start with Long Open Window when  
entering Normal Mode.  
Restart Mode  
Off  
Device will start with Long Open Window when  
entering Normal Mode.  
The watchdog timing is programmed via SPI command in the register WD_CTRL. As soon as the watchdog is  
programmed, the timer starts with the new setting and the watchdog must be served. The watchdog is  
triggered by sending a valid SPI-write command to the watchdog configuration register. The watchdog trigger  
command is executed when the SPI command is interpreted.  
When coming from Init Mode, Restart Mode or in certain cases from Stop Mode, the watchdog timer is always  
started with a long open window. The long open window (tLW) allows the microcontroller to run its  
initialization sequences and then to trigger the watchdog via SPI.  
The watchdog timer period can be selected via SPI (WD_TIMER).The timer setting is valid for both watchdog  
types.  
The following watchdog timer periods are available:  
WD Setting 1: 10 ms  
WD Setting 2: 20 ms  
WD Setting 3: 50 ms  
WD Setting 4: 100 ms  
WD Setting 5: 200 ms  
WD Setting 6: 500 ms  
WD Setting 7: 1 s  
WD Setting 8: 10 s  
In case of a reset, Restart Mode or Fail-Safe Mode is entered according to the configuration and the SPI bits  
WD_FAIL are set. Once the RSTN goes high again the watchdog immediately starts with a long open window  
the device enters automatically Normal Mode.  
The Watchdog behaviour in Software Development Mode is described in Chapter 5.4.7.  
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BLDC Motor System IC  
Supervision Functions  
In case a watchdog-trigger was missed in Software Development Mode, the watchdog will start with the long-  
open-window once again.  
The WD_FAIL bits will be set after a watchdog trigger failure.  
The WD_FAIL bits are cleared automatically when following conditions apply:  
After a successful watchdog trigger.  
When the watchdog is off: in Stop Mode after successfully disabling it, in Sleep Mode, or in Fail-Safe Mode  
(except for a watchdog failure).  
12.2.1  
Time-Out Watchdog  
The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog  
trigger can be done at any time within the configured watchdog timer period.  
A correct watchdog service immediately results in starting a new watchdog timer period. Taking the  
tolerances of the internal oscillator into account leads to the safe trigger area as defined in Figure 60.  
If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RSTN low and  
the device switches to Restart Mode or Fail-Safe Mode.  
Typical timout watchdog trigger period  
tWD x 1.50  
open window  
uncertainty  
Watchdog Timer Period (WD_TIMER)  
tWD x 1.20  
tWD x 1.80  
t / [tWD_TIMER  
]
safe trigger area  
Figure 60 Time-out Watchdog Definitions  
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BLDC Motor System IC  
Supervision Functions  
12.2.2  
Window Watchdog  
Compared to the time-out watchdog the characteristic of the window watchdog is that the watchdog timer  
period is divided between a closed and an open window. The watchdog must be triggered within the open  
window.  
A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an  
open window.  
The watchdog timer period is at the same time the typical trigger time and defines the middle of the open  
window. Taking the oscillator tolerances into account leads to a safe trigger area of:  
tWD × 0.72 < safe trigger area < tWD × 1.20.  
The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking  
the tolerances of the internal oscillator into account leads to the timings as defined in Figure 61.  
A correct watchdog service immediately results in starting the next closed window.  
If the trigger signal meet the closed window or if the watchdog timer period elapses, then a watchdog reset is  
triggered (RSTN low) and the device switches to Restart Mode or Fail-Safe Mode.  
tWD x 0.6  
tWD x 0.9  
Typ. closed window  
Typ. open window  
tWD x 0.48  
tWD x 0.72  
tWD x 1.0  
tWD x 1.20  
tWD x 1.80  
closed window  
uncertainty  
open window  
uncertainty  
Watchdog Timer Period (WD_TIMER)  
t / [tWD_TIMER  
]
safe trigger area  
Figure 61 Window Watchdog Definitions  
12.2.3  
Watchdog Setting Check Sum  
A check sum bit is part of the SPI command to trigger the watchdog and to set the watchdog setting.  
The sum of the 16 data bits in the register WD_CTRL needs to have even parity (see Equation (12.1)). This is  
realized by either setting the bit CHECKSUM to 0 or 1. If the check sum is wrong, then the SPI command is  
ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set.  
The written value of the reserved bits of the WD_CTRL register is considered (even if read as ‘0’ in the SPI  
output) for checksum calculation, i.e. if a 1 is written on the reserved bit position, then a 1 will be used in the  
checksum calculation.  
(12.1)  
Bit(CHECKSUM) = Bit22 ⊕ … ⊕ Bit8  
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BLDC Motor System IC  
Supervision Functions  
12.2.4  
Watchdog during Stop Mode  
The watchdog can be disabled for Stop Mode in Normal Mode. For safety reasons, there is a special sequence  
to be followed in order to disable the watchdog as described in Figure 62. Two different SPI bits  
(WD_STM_EN_0, WD_STM_EN_1) in the registers HW_CTRL and WD_CTRL need to be set.  
Correct WD disabling  
Sequence Errors  
sequence  
Missing to set bit  
WD_STM_EN_0 with the  
next watchdog trigger after  
having set WD_STM_EN_1  
Set bit  
WD_STM_EN_1 = 1  
with next WD Trigger  
Staying in Normal Mode  
instead of going to Stop  
Mode with the next trigger  
Set bit  
WD_STM_EN_0 = 1  
Before subsequent WD Trigger  
Will enable the WD:  
Change to  
Stop Mode  
Switching back to  
Normal Mode  
Triggering the watchdog  
WD is switched off  
Figure 62 Watchdog disabling sequence in Stop Mode  
If a sequence error occurs, then the bit WD_STM_EN_1 will be cleared and the sequence has to be started  
again.  
The watchdog can be enabled by triggering the watchdog in Stop Mode or by switching back to Normal Mode  
via SPI command. In both cases the watchdog will start with a long open window and the bits WD_STM_EN_1  
and WD_STM_EN_0 are cleared. After the long open window the watchdog has to be served as configured in  
the WD_CTRL register.  
Note:  
The bit WD_STM_EN_0 will be cleared automatically when the sequence is started and it was 1  
before. WD_STM_EN_0 can also not be set if WD_STM_EN_1 isn't yet set.  
12.2.5  
Watchdog Start in Stop Mode due to Bus Wake  
In Stop Mode the Watchdog can be disabled. In addition a feature is available which will start the watchdog  
with any BUS wake (LIN) during Stop Mode. The feature is enabled by setting the bit WD_EN_ WK_BUS = 1  
(default value after POR). The bit can only be changed in Normal Mode and needs to be programmed before  
starting the watchdog disable sequence.  
A wake on the Bus will generate an interrupt and the RXDLIN is pulled to low. By these signals the  
microcontroller is informed that the watchdog is started with a long open window. After the long open  
window the watchdog has to be served as configured in the WD_CTRL register.  
To disable the watchdog again, the device needs to be switched to Normal Mode and the sequence needs to  
be sent again.  
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Supervision Functions  
12.3  
VSINT Power On Reset  
At power up of the device, the Power on Reset is detected when VSINT > VPOR,r and the SPI bit POR is set to  
indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be  
kept low and will only be released once VCC1 has crossed VRT1,r and after tRD1 has elapsed.  
In case VSINT < VPOR,f, an device internal reset will be generated and the device is switched off and will restart  
in Init Mode at the next VSINT rising. This is shown in Figure 63.  
VSINT  
VPOR,r  
VPOR,f  
t
t
VCC1  
VRT1,r  
The reset threshold can be  
configured via SPI in  
Normal Mode, default is VRT1  
VRTx,f  
RSTN  
Restart Mode is entered  
whenever the Reset is  
triggered  
t
tRD1  
Mode  
Re-  
start  
OFF  
INIT MODE  
Any MODE  
OFF  
t
SPI  
Command  
Figure 63 Ramp up / down example of Supply Voltage  
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BLDC Motor System IC  
Supervision Functions  
12.4  
VSINT Under- and Overvoltage  
12.4.1  
VSINT Undervoltage  
The VSINT under-voltage monitoring is always active in Init Mode, Restart Mode, Normal Mode. If the supply  
voltage VSINT drops below VSINT,UV for more than tVSUV_FILT, then the device does the following measures:  
The VCC1 short circuit diagnosis becomes inactive (see Chapter 12.8). However, the thermal protection of  
the device remains active. If the undervoltage threshold is exceeded (VSINT rising) then the function will  
be automatically enabled again.  
The status bit VSINT_UV is set and latched until a clear command of SUP_STAT is received.  
Note:  
VSINT under-voltage monitoring is not available in Stop Mode due to current consumption saving  
requirements except if the VCC1 load current is above the active peak threshold (I_PEAK_TH) or if  
VCC1 is below the VCC1 prewarning threshold.  
12.4.2  
VSINT Overvoltage  
The VSINT over-voltage monitoring is always active in Init Mode, Restart Mode and Normal Mode. If VSINT rises  
above VS,OVD1, VS,OVD2 for more than tVSOV_FILT then the device does the following measures:  
1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static  
discharge current during their respective tHBxCCP Active.  
2. Then the charge pump is turned off and the passive discharge is activated.  
3. The status bits VSINT_OV is set and latched until a clear command of SUP_STAT is received.  
If VS or VSINT fall below VS,OVD1 or VS,OVD2  
:
If CPEN = 0 : the charge pumps stays and the bridge driver stay off.  
If CPEN = 1 :  
If BDOV_REC = 0 : Then the charge pump is reactivated but the bridge driver stays off until VS_OV and  
VSINT_OV are cleared. The current sense amplifier is reactivated (provided that CSA_OFF = 0)  
If BDOV_REC = 1 : Then the charge pump and the current sense amplifier are reactivated and the bridge  
driver is enabled if VCP > VCPUVx, even if VS_OV or VSINT_OV is set. The state of the external MOSFETs is  
according to the control registers.  
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Supervision Functions  
12.5  
VS Under- and Overvoltage  
12.5.1  
VS Undervoltage  
The VS under-voltage monitoring is always active in Init-, Restart Mode and Normal Mode. If VS drops below  
VS,UV for more than tVSUV_FILT, then the device does the following measures:  
1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static  
discharge current during their respective tHBxCCP Active.  
2. Then the charge pump is turned off and the passive discharge is activated and the current sense amplifier  
is turned off.  
3. The status bits VS_UV is set and latched until a clear command of SUP_STAT is received.  
If VS rises above VS,UV, then the charge pump is reactivated (provided that CPEN is set) and the current sense  
amplifier is reactivated (provided CSA_OFF = 0) but the bridge driver stays off until VS_UV is cleared. The  
bridge driver will be reactivated once the VS_UV bit is cleared.  
12.5.2  
VS Overvoltage  
The VS over-voltage monitoring is always active in Init-, Restart Mode and Normal Mode or when the charge  
pump is enabled. If VS rises above VS,OVD1 or VS,OVD2 for more than tVSOV_FILT, then the device does the following  
measures:  
1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static  
discharge current during their respective tHBxCCP Active.  
2. Then the charge pump is turned off and the passive discharge is activated and current sense amplifier is  
turned off .  
3. The status bits VS_OV is set and latched until a clear command of SUP_STAT is received.  
If VS and VSINT fall below VS,OVD1 or VS,OVD2  
:
If CPEN = 0 : the charge pumps and the bridge driver stay off.  
If CPEN = 1 :  
If BDOV_REC = 0 : Then the charge pump is reactivated but the bridge driver stays off until VS_OV and  
VSINT_OV are cleared. The current sense amplifier is reactivated provided that CSA_OFF = 0  
If BDOV_REC = 1 : Then the charge pump and the current sense amplifier are reactivated and the bridge  
driver is enabled if VCP > VCPUVx, even if VS_OV or VSINT_OV is set. The state of the external MOSFETs is  
according to the control registers.  
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Supervision Functions  
12.6  
VS Under- Overvoltage for high-side  
12.6.1  
VS Undervoltage for high-side  
If the supply voltage VS passes below the undervoltage threshold (VSHS,UVD) the device does the following  
measures:  
HS1...3 are acting accordingly to the SPI setting (refer also to Chapter 7.2.1).  
LIN: Transmitter and Receiver are disabled during the VS undervoltage condition.  
SPI bit HS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present  
anymore.  
12.6.2  
VS Overvoltage for high-side  
If the supply voltage VSHS reaches the overvoltage threshold (VSHS,OVD) the device triggers the following  
measures:  
HS1...3 are acting accordingly to the SPI setting (refer also to Chapter 7.2.2).  
The status bit HS_OV is set. No other error bits are set. The bit can be cleared once the condition is not  
present anymore.  
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Supervision Functions  
12.7  
VCC1 Over-/ Undervoltage and Undervoltage Prewarning  
12.7.1  
VCC1 Undervoltage and Undervoltage Prewarning  
This function is always active when the VCC1 voltage regulator is enabled.  
A first-level voltage detection threshold is implemented as a prewarning for the microcontroller. The  
prewarning event is signaled with the bit VCC1_WARN. No other actions are taken.  
As described in Chapter 12.1 and Figure 64, a reset will be triggered (RSTN pulled low) when the VCC1 output  
voltage falls below the selected undervoltage threshold (VRTx). The device will enter Restart Mode and the bit  
VCC1_UV is set when RSTN is released again.  
The hysteresis of the VCC1 undervoltage threshold can be increased by setting the bit RSTN_HYS. In this case  
always the highest rising threshold (VRT1,R) is used for the release of the undervoltage reset. The falling reset  
threshold remains as configured.  
An additional safety mechanism is implemented to avoid repetitive VCC1 undervoltage resets due to high  
dynamic loads on VCC1:  
A counter is increased for every consecutive VCC1 undervoltage event (regardless on the selected reset  
threshold).  
The counter is active in Init Mode, Normal Mode and Stop Mode.  
For VS < VSINT,UV the counter will be stopped in Normal Mode (i.e. the VS UV comparator is always enabled  
in Normal Mode).  
A 4th consecutive VCC1 undervoltage event will lead to Fail-Safe Mode entry and to setting the bit  
VCC1_UV_FS.  
This counter is cleared:  
When Fail-Safe Mode is entered.  
When the bit VCC1_UV is cleared.  
When a Soft-Reset is triggered.  
Note:  
Note:  
After 4 consecutive VCC1_UV events, the device will enter Fail-Safe Mode and the VCC1_UV_FS bit is  
set.  
The VCC1_WARN or VCC1_UV bits are not set in Sleep Mode as VCC1 = 0 V in this case.  
VCC1  
VRTx  
t
tRF  
tRDx (config)  
RSTN  
t
Normal Mode  
Restart Mode  
Normal Mode  
Figure 64 VCC1 Undervoltage Timing Diagram  
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Note:  
It is recommended to clear the VCC1_WARN and VCC1_UV bit once it is detected by the  
microcontroller software to verify if the undervoltage still exists or not.  
12.7.2  
VCC1 Overvoltage  
For fail-safe reasons a configurable VCC1 over voltage detection feature is implemented. It is active when the  
VCC1 voltage regulator is enabled.  
In case the VCC1,OV,r threshold is crossed, the device triggers following measures depending on the  
configuration:  
The bit VCC1_OV is always set.  
Based on the configuration of VCC1_OV_MOD, different kind of event are generated from device.  
If the VCC1_OV_MOD=11B, in case of the device enters in Fail Safe Mode.  
VCC1  
VCC1,OV  
t
tOV_filt  
RSTN  
tRDx (config)  
t
Normal Mode  
Restart Mode  
Normal Mode  
Figure 65 VCC1 Over Voltage Timing Diagram  
12.8  
VCC1 Short Circuit Diagnostics  
The short circuit protection feature for VCC1 is implemented as follows:  
The short circuit detection is only enabled if VS > VSINT,UV.  
If VCC1 is not above the VRTx within tVCC1,SC after device power up or after waking from Sleep Mode or Fail-  
Safe Mode (i.e. after VCC1 is enabled) then the SPI bit VCC1_SC bit is set, VCC1 is turned off, the FO pin is  
enabled, FAILURE is set and Fail-Safe Mode is entered. The device can be activated again via a wake-up  
sources.  
The same behavior applies, if VCC1 falls below VRTx for longer than tVCC1,SC.  
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12.9  
Thermal Protection  
Three independent and different thermal protection features are implemented in the device according to the  
system impact:  
Individual thermal shutdown of specific blocks  
Temperature prewarning of VCC1 voltage regulator  
Device thermal shutdown due to VCC1 overtemperature  
12.9.1  
Individual Thermal Shutdown  
As a first-level protection measure, LIN, HSx and the charge pump are independently switched off if the  
respective block reaches the temperature threshold TjTSD1. Then the TSD1 bit is set. This bit can only be  
cleared via SPI once the overtemperature is not present anymore. Independent of the device mode the  
thermal shutdown protection is only active if the respective block is ON.  
The respective modules behave as follows:  
LIN: The transmitter is disabled and stays in LIN Normal Mode acting like LIN Receive Only Mode. The status  
bits LIN_FAIL are set to ‘01’. Once the over temperature condition is not present anymore, then the LIN  
transmitter is automatically switched on.  
HSx: If one or more HSx switches reach the TSD1 threshold, then the HSx switches are turned OFF  
(depending on configuration either individually or all at once) and the control bits for HSx are cleared  
based on HS_OT_SD_DIS setting. The status bits HSx_OT are set (see register HS_OL_OC_OT_STAT).  
Once the over temperature condition is not present anymore, then HSx has to be configured again by SPI.  
Charge pump: If the charge pump reaches TjTSD1, then CP_OT is set, CPEN is cleared and the activated  
MOSFETs are actively discharged with their respective static currents during their respective active cross  
current protection times (tHBxCCP active). When all tHBxCCP active elapsed, then the charge pump and  
the MOSFETs active discharge are disabled and the current sense amplifier is deactivated. Once the over  
temperature condition is not present anymore, then CPEN has to be configured again by SPI.  
Note:  
The diagnosis bits are not cleared automatically and have to be cleared via SPI once the  
overtemperature condition is not present anymore.  
12.9.2  
Temperature Prewarning  
As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1  
reaches the thermal prewarning temperature threshold TjPW. Then the status bit TPW is set. This bit can only  
be cleared via SPI once the overtemperature is not present anymore.  
12.9.3  
Thermal Shutdown  
As a highest level of thermal protection a temperature shutdown of the device is implemented if the main  
supply VCC1 reaches the thermal shutdown temperature threshold TjTSD2. Once a TSD2 event is detected Fail-  
Safe Mode is entered. Only when device temperature falls below the TSD2 threshold then the device remains  
in Fail-Safe Mode for tTSD2 to allow the device to cool down. After this time has expired, the device will  
automatically change via Restart Mode to Normal Mode (see also Chapter 5.4.6).  
When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in Normal  
Mode once the overtemperature is not present anymore.  
For increased robustness requirements it is possible to extend the TSD2 waiting time by 64x of tTSD2 after 16  
consecutive TSD2 events by setting the SPI bit TSD2_DEL. The counter is incremented with each TSD2 event  
even if the bit TSD2 is not cleared. Once the counter has reached the value 16, then the bit TSD2_SAFE is set  
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and the extended TSD2 waiting time is active. The extended waiting time will be kept until TSD2_SAFE is  
cleared. The TSD counter is cleared when TSD2 or TSD2_DEL is cleared.  
Note:  
In case a TSD2 overtemperature occurs while entering Sleep Mode then Fail-Safe Mode is still  
entered.  
Note:  
In case of a TSD2 event, the FAILURE bit is set to ‘1’ and the DEV_STAT field is set to ‘01’ inside the  
DEV_STAT register.  
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12.10  
Bridge driver  
This section describes the supervision functions related to the bridge driver.  
12.10.1 Bridge driver supervision with activated charge pump  
This section describes the supervision functions when the charge pump is activated.  
12.10.1.1 Drain-source voltage monitoring  
Voltage comparators monitor the activated MOSFETs to protect high-side MOSFETs and low-side MOSFETs  
against a short circuit respectively to ground and to the battery during ON-state.  
A drain-source overvoltage is detected on a low-side MOSFET if the voltage difference between VSHx and SL  
exceeds the threshold voltage configured by LS_VDS (see Table 31). Consequently, the corresponding half-  
bridge is latched off with the static discharge current.  
A drain-source overvoltage is detected on a high-side MOSFET if the voltage difference between VS and VSHx  
exceeds the threshold voltage configured by HS_VDS (see Table 32). Consequently, the corresponding half-  
bridge is latched off with the static discharge current.  
Table 31 Low-side drain-source overvoltage threshold  
LSxVDSTH[2:0]  
000B  
Drain-Source overvoltage threshold for LSx (typical)  
160 mV  
200 mV (default)  
300 mV  
400 mV  
500 mV  
600 mV  
800 mV  
2 V  
001B  
010B  
011B  
100B  
101B  
110B  
111B  
Table 32 High-side drain-source overvoltage threshold  
HSxVDSTH[2:0]  
000B  
Drain-Source overvoltage threshold for HSx (typical)  
160 mV  
200 mV (default)  
300 mV  
400 mV  
500 mV  
600 mV  
800 mV  
2 V  
001B  
010B  
011B  
100B  
101B  
110B  
111B  
Attention: 2 V threshold is dedicated for the diagnostic in off-state. It is highly recommended to select  
another drain-source overvoltage threshold once the routine of the diagnostic in off-state has  
been performed to avoid additional current consumption from VS and from the charge pump.  
The device reports a Drain-Source overvoltage error if both conditions are met:  
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After expiration of the blank time .  
If the Drain-Source voltage monitoring exceeds the configured threshold for a duration longer than the  
configured filter time (refer to Table 33 and LS_VDS TFVDS bits).  
Table 33 Drain-Source overvoltage filter time  
TFVDS[2:0]  
Drain-Source overvoltage filter time (typical)  
00B  
01B  
10B  
11B  
0.5 µs (default)  
1 µs  
2 µs  
6 µs  
If a short circuit is detected by the Drain-Source voltage monitoring:  
The impacted half-bridge is latched off with the static discharge current for the configured cross-current  
protection time.  
The corresponding bit in the status register DSOV is set.  
The DSOV bit in Global Status Register GEN_STAT is set.  
If a Drain-Source overvoltage is detected for one of the MOSFETs, then the status register DSOV must be  
cleared in order to re-enable the faulty half-bridge.  
12.10.1.2 Cross-current protection and drain-source overvoltage blank time  
All gate drivers feature a cross-current protection time and a Drain-Source overvoltage blank time.  
The cross-current protection avoids the simultaneous activation of the high-side and the low-side MOSFETs  
of the same half-bridge.  
During the blank time, the drain-source overvoltage detection is disabled, to avoid a wrong fault detection  
during the activation phase of a MOSFET.  
Note:  
The setting of the cross-current protection and of the blank times may be changed by the  
microcontroller only if all HBx_PWM_EN bits are reset.  
Note:  
Changing the Drain-Source overvoltage of a half-bridge x (HBx) in on-state (HBxMODE[1:0]=(0,1) or  
(1,0)) may result in a wrong VDS overvoltage detection on HBx. Therefore it is highly recommended  
to change this threshold when HBxMODE[1:0]=(0,0) or (1,1)  
12.10.1.2.1 Cross-current protection  
The active and freewheeling cross-current protection times of each half-bridge is configured individually with  
the control register CCP_BLK.  
The typical cross-current protection time applied to the freewheeling MOSFET of the half-bridge x is 587 ns +  
266 ns x TCCP[3:0]D, where TCCP[3:0]D is the decimal value of the control bits TCCP.  
12.10.1.2.2 Drain-source overvoltage blank time  
A configurable blank time for the Drain-Source monitoring is applied at the turn-on of the MOSFETs. During  
the blank time, a Drain-Source overvoltage error is masked.  
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For Half-Bridges in PWM mode with AFWx = 1:  
the blank time of the PWM MOSFET starts at the expiration of the cross-current protection time of the PWM  
MOSFET. Refer to Figure 66.  
the blank time of the free-wheeling MOSFET starts after expiration of the cross-current protection time at  
turn-off of the PWM MOSFET. Refer to Figure 66.  
PWM  
t
IGS_PWM  
MOSFET  
Post-charge  
tPCHGz  
ICHGMAXz  
tPDCHGz  
IPRECHGz  
ICHGz  
t
0
- IDCHGz  
tBLANK for  
PWM MOSFET  
- IPREDCHGz  
tHBxCPP for  
symmetrisation  
tHBxCPP  
tHBxCPP  
IGS Freewheeling  
MOSFET  
ICHGMAXz  
t
tBLANK for  
freewheeling MOSFET  
-
ICHGMAXz  
Figure 66 Blank time for half-bridges in PWM operation with AFW = 1  
For statically activated half-bridges, the blank time starts:  
Case1: at expiration of the cross-current protection (Figure 36), if the opposite MOSFET was previously  
activated.  
Case 2: right after the decoding of the SPI command to turn on a MOSFET, if the half-bridge was in high  
impedance (Figure 37).  
The blank times of the active and FW MOSFETs can be configured with the control register CCP_BLK.  
The typical blank is 587 ns + 266 ns x TBLK[3:0]D).  
Note:  
The blank time is implemented at every new activation of a MOSFET, including a recovery from VS  
undervoltage, VS overvoltage, VSINT overvoltage, CP UV, CP OT.  
12.10.1.3 OFF-state diagnostic  
In order to support the off-state diagnostic (HBxMODE= 11 and CPEN = 1), the gate driver of each MOSFET  
provides pull-up (IPUDiag) and a pull-down currents (IPDDiag) at the SHx pins. This function requires an activated  
charge pump.  
The pull-up current source of a given half-bridge is on when the half-bridge is active: HBxMODE= 01, 10 or 11  
and CPEN = 1.  
The pull-down current of each low-side gate driver is activated by the control bits HBx (HB_ICHG_MAX  
register).  
During the off-state diagnostic routine performed by the microcontroller, the drain-source overvoltage  
threshold of the relevant half-bridges must be set to 2V nominal. Refer to Table 31. Once the routine is  
finished, it is highly recommended to decrease the drain-source overvoltage threshold to a lower value,  
avoiding additional current consumption from the VS input.  
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The following failures can be detected:  
MOSFET short circuit to GND  
MOSFET short circuit the battery  
Open load (disconnected motor)  
The status of the output voltages VOUTx, can be read back with status bit HBxVOUT (register GEN_STAT) when  
the corresponding half-bridge is in off-state (HBxMODE[1:0] = 11).  
Note:  
HBxVOUT = 0 if the half-bridge x is not actively off (HBxMODE[1:0] = (0,0), (0,1) or (1,0) and CPEN=1)  
or when the charge pump is deactivated (CPEN=0).  
12.10.1.4 Charge pump undervoltage  
The voltage of the charge pump output (VCP) is monitored in order to ensure a correct control of the external  
MOSFETs.  
The charge pump undervoltage threshold is configurable by the control bits FET_LVL and CPUVTH.  
Table 34 Charge pump undervoltage thresholds  
FET_LVL = 0  
FET_LVL = 1  
CPUVTH = 0  
CPUVTH = 1  
V
CPUV1 (6 V typ. referred to VS)  
CPUV2 (6.5 V typ. referred to VS)  
VCPUV3 (7.5 V typ. referred to VS)  
VCPUV4 (8 V typ. referred to VS)  
V
If VCP falls below the configured charge pump undervoltage threshold while CPEN = 1:  
If one of the MOSFET is on, then all MOSFETs are actively turned off with their configured static discharge  
current during their respective tHBxCCP active.  
Then the gate drivers are turned off and CSA is turned off .  
CP_UV is set and latched.  
The CP_UV is reset and the normal operation is resumed once SUP_STAT is cleared and VCP > VCPUV.  
The charge pump undervoltage detection is blanked (tCPUVBLANK) during each new activation of the charge  
pump1).  
12.10.1.5 Switching parameters of MOSFETs in PWM mode  
The effective switching parameters of the active MOSFETs (EN_GEN_CHECK=1), respectively PWM MOSFET  
(EN_GEN_CHECK=0)can be read out with dedicated status registers:  
The turn-on and turn off delays, noted tDON and tDOFF are reported by the status register  
EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3.  
The rise and fall times, noted tRISE and tFALL, are reported by the status register TRISE_FALL1,  
TRISE_FALL2, TRISE_FALL3.  
12.10.2 Low-side drain-source voltage monitoring during braking  
The low-side MOSFETs are turned-on while the charge pump is deactivated in the following conditions:  
The slam mode is activated and PWM1/CRC is High.  
1) Including CPEN set to 1, recovery from VS under/overvoltage, VSINT overvoltage and CP_ OT  
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The parking braking mode is activated and the device is in Sleep Mode or Stop Mode.  
VS overvoltage brake is activated and (VS > VS Overvoltage braking or VSINT > VSINT Overvoltage braking)  
in all device modes if OV_BRK_EN is set.  
Under these conditions, the drain-source voltage of the low-sides are monitored and the applied drain-source  
overvoltage thresholds are according to VDSTH_BRK.  
The applied blank time, which starts at the beginning of the brake activation, is:  
t
t
BLK_BRAKE1 if TBLK_BRK = 0  
BLK_BRAKE2 if TBLK_BRK = 1  
During the blank time, a drain-source overvoltage of the low-sides is masked.  
The applied filter time is tFVDS_BRAKE  
.
If a drain-source overvoltage is detected during braking , then all low-side MOSFETs are turned off (latched)  
within tOFF_BRAKE. SLAM_LSx_DIS (BRAKE, SLAM, PARK_BRK_EN, OV_BRK_EN are unchanged. The  
corresponding status bit LSxDSOV_BRK is set in DSOV.  
The low-sides can be reactivated only if all LSxDSOV_BRK bits (DSOV) are cleared (even in slam mode with the  
respective LSx disabled by the SLAM_LSx_DIS bit).  
If any of the status bits LSxDSOV_BRK is set, then the charge pump stays off (CPEN=1 command is accepted  
but the charge pump stays disabled until all LSxDSOV_BRK are cleared).  
12.10.3 VS or VSINT Overvoltage braking  
The VS and VSINT overvoltage braking is activated if the OV_BRK_EN bit in BRAKE register is set regardless of  
the device mode.  
If VS, respectively VSINT, exceeds VOVBR,cfgx,r (x = 0 to 7), then all low-sides MOSFETs are turned-on within  
tON_BRAKE. The status bits VSOVBRAKE_ST, respectively VSINTOVBRAKE_ST, is set and latched (see DSOV  
register).  
If VS and VSINT decrease below VOVBR,cfgx,r - VHYS,cfgx (x = 0 to 7), then all low-sides MOSFETs are turned-off within  
tOFF_BRAKE after the filter time tOV_BR_FILT.  
If (VSHx - VSL) exceeds the configured threshold, then all low-sides MOSFETs are turned-off within tOFF_BRAKE  
after the filter time tFVDS_BRAKE. The threshold is:  
V
V
VDSMONTH0_BRAKE if VDSTH_BRK = 0  
VDSMONTH1_BRAKE if VDSTH_BRK = 1  
12.11  
Current sense amplifier  
The current sense amplifier (CSA) allows current measurements with external shunt resistor in low-side  
configuration. The CSA is supplied by the charge pump (CP). Therefore, if the CP is off, then the CSA is  
deactivated.  
12.11.1 Unidirectional and bidirectional operation  
The current sense amplifier (CSA) can work either as unidirectional or bi-directional operation. Refer to CSA  
register.  
Unidirectional operation CSD = 0  
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In unidirectional operation, the CSA is optimized to measure the current flowing through the external shunt  
resistor when VCSAP VCSAN.  
VCSO = VREF Unidir + (VCSAP - VCSAN + VOS) × GDIFF provided that VCSO is in the linear range1) 2)  
.
Bidirectional operation CSD = 1  
In bidirectional operation, the CSA measures the current flowing through the external shunt resistor in both  
directions: VCSAP VCSAN or VCSAP VCSAN.  
The output CSO works at half-scale range: VCSO = VREF Bidir+ (VCSAP - VCSAN + VOS) × GDIFF, provided that VCSO  
is in the linear range 2).  
12.11.2 Gain configuration  
The gain of the current sense amplifier is configurable by the configuration bits CSAG bits. Refer to Table 35.  
Table 35 Configuration of the current sense amplifier gain  
CSAG[1:0]  
00B  
Current sense amplifier gain GDIFF  
GDIFF10  
GDIFF20  
GDIFF40  
GDIFF60  
01B  
10B  
11B  
12.11.3 Overcurrent Detection  
A comparator at CSO detects overcurrent conditions. The overcurrent threshold is configurable with the OCTH  
bits. Refer to Table 36 for unidirectional operation and Table 37 for bidirectional operation.  
Table 36 Overcurrent detection thresholds in unidirectional operation (CSD = 0)  
OCTH[1:0]  
00B  
Typical Overcurrent Detection Threshold  
VCSO > VCC1/2  
01B  
VCSO > VCC1 /2+ VCC1/10  
10B  
VCSO > VCC1 /2+ 2 × VCC1/10  
VCSO > VCC1/2 /2+ 3 × VCC1/10  
11B  
1) Valid if 0.5 V VCSO VCC1 - 0.5 V.  
2) VCSO is clamped between VCC1 and GND.  
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CSO unidirectional overcurrent detection threshold  
VCSO  
VCC1  
OCTH[1:0]  
VCC1 / 2 + 3 x VCC1 / 10  
VCC1 / 2 + 2 x VCC1 / 10  
VOCTH4 Unidir  
VOCTH3 Unidir  
(1,1)  
(1,0)  
(0,1)  
(0,0)  
VCC1 / 2 + VCC1 / 10  
VCC1 / 2  
VOCTH2 Unidir  
VOCTH1 Unidir  
VREF Unidir  
Typ. VCC1/5  
0V  
Figure 67 Overcurrent detection thresholds in unidirectional operation (CSD = 0)  
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Table 37 Overcurrent detection thresholds in bidirectional operation (CSD = 1)  
OCTHx[1:0]  
Typical Overcurrent Detection Threshold  
00B  
01B  
10B  
11B  
VCSO > VCC1/2 + 2 × VCC1/20 or VCSO< VCC1/2 -2 × VCC1/20  
VCSO > VCC1/2 + 4 × VCC1/20 or VCSO< VCC1/2 - 4 × VCC1/20  
VCSO > VCC1/2+ 5 × VCC1/20 or VCSO< VCC1/2 - 5 × VCC1/20  
VCSO > VCC1/2+ 6 × VCC1/20 or VCSO< VCC1/2 - 6 × VCC1/20  
VCSO  
VCC1  
CSO bidirectional overcurrent detection threshold  
OCTH[1:0]  
VOCTH4 BidirH  
VOCTH3 BidirH  
VOCTH2 BidirH  
VCC1 / 2 + 6 x VCC1 / 20  
VCC1 / 2 + 5 x VCC1 / 20  
VCC1 / 2 + 4 x VCC1 / 20  
(1,1)  
(1,0)  
(0,1)  
VOCTH1 BidirH (0,0)  
VCC1 / 2 + 2 x VCC1 / 20  
VREF Bidir  
Typ. VCC1 /2  
VOCTH1 BidirL (0,0)  
VCC1 / 2 - 2 x VCC1 / 20  
VOCTH2 BidirL  
VOCTH3 BidirL  
VOCTH4 BidirL  
(0,1)  
V
CC1 / 2 - 4 x VCC1 / 20  
CC1 / 2 - 5 x VCC1 / 20  
V
(1,0)  
(1,1)  
VCC1 / 2 - 6 x VCC1 / 20  
0V  
Figure 68 Overcurrent detection thresholds in bidirectional operation (CSD = 1)  
It is possible to program the device behavior when an overcurrent condition is detected:  
OCEN bit = 0 (see CSA): the device only reports the overcurrent event ( bit is set), without any change of the  
gate driver states.  
OCEN bit = 1 (see CSA): the device reports the overcurrent event ( bit is set) and actively turns off all  
MOSFETs with static discharge curent:  
The MOSFETs can be reactivated by clearing OC_CSA or by resetting the OCEN bit.  
The overcurrent filter time is configurable (refer to tFOC) by the OCFILT control bits.  
FOC refers to the output of the current sense amplifier. The CSO settling time (2 µs max, tSET) and the analog  
t
propagation delay (< 1 µs) are not taken into account by the overcurrent filter time.  
12.11.4 CSO output capacitor  
The capacitor connected to CSO (CCSO) must be between 10 pF and 2.2 nF. The control bit CSO_CAP  
optimizes the current consumption for CCSO < 400 pF or 400 pF < CCSO < 2.2 nF1).  
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12.12  
Electrical Characteristics  
Table 38 Electrical Characteristics  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current  
defined flowing into pin; unless otherwise specified.  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
VCC1 Monitoring; VCC1 = 5.0V Version  
Undervoltage Prewarning VPW,f  
Threshold Voltage PW,f  
4.53  
4.60  
30  
4.70  
4.75  
50  
4.84  
4.90  
90  
V
VCC1 falling,  
SPI bit is set  
P_13.12.1  
P_13.12.2  
P_13.12.3  
Undervoltage Prewarning VPW,r  
Threshold Voltage PW,r  
V
VCC1 rising  
6)  
Undervoltage Prewarning VPW,hys  
Threshold Voltage  
mV  
hysteresis  
VCC1 UV Prewarning  
Detection Filter Time  
tVCC1,PW_F  
VRT1,f  
VRT1,r  
VRT2,f  
VRT2,r  
VRT3,f  
VRT3,r  
VRT4,f  
5
10  
14  
us  
V
V
V
V
V
V
V
V
2) rising and falling P_13.12.4  
Reset Threshold  
Voltage RT1,f  
4.45  
4.58  
3.70  
3.85  
3.24  
3.39  
2.49  
2.65  
4.6  
4.75  
4.90  
4.00  
4.15  
3.55  
3.70  
2.8  
default setting;  
VCC1 falling  
P_13.12.5  
P_13.12.6  
P_13.12.7  
P_13.12.8  
P_13.12.9  
P_13.12.10  
P_13.12.11  
P_13.12.12  
Reset Threshold  
Voltage RT1,r  
4.74  
3.85  
4.0  
default setting;  
VCC1 rising  
Reset Threshold  
Voltage RT2,f  
VCC1 falling  
Reset Threshold  
Voltage RT2,r  
VCC1 rising  
Reset Threshold  
Voltage RT3,f  
3.40  
3.54  
2.65  
2.76  
VS 4 V;  
VCC1 falling  
Reset Threshold  
Voltage RT3,r  
VS 4 V;  
VCC1 rising  
Reset Threshold  
Voltage RT4,f  
VS 4 V;  
VCC1 falling  
Reset Threshold  
Voltage RT4,r  
VRT4,r  
2.95  
VS 4 V;  
VCC1 rising  
6)  
Reset Threshold Hysteresis VRT,hys  
70  
140  
220  
5.8  
mV  
V
P_13.12.13  
P_13.12.26  
VCC1 Over Voltage  
Detection Threshold  
Voltage  
VCC1,OV,r  
VCC1,OV,f  
tVCC1,OV_F  
5.5  
5.65  
1)6) rising VCC1  
VCC1 Over Voltage  
Detection Threshold  
Voltage  
5.4  
51  
5.55  
64  
5.7  
80  
V
6) falling VCC1  
P_13.12.27  
P_13.12.31  
2)  
VCC1 OV Detection Filter  
Time  
us  
1) for 400 pF < CCSO < 2.2 nF, a seial resistor of min. 45 Ohm between the CSO pin and the CCSO capacitor is required,  
Datasheet 136  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Supervision Functions  
Table 38 Electrical Characteristics (cont’d)  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current  
defined flowing into pin; unless otherwise specified.  
Parameter  
Symbol  
Values  
Typ.  
4
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
VCC1 Short to GND Filter  
Time  
tVCC1,SC  
3.2  
4.8  
ms  
2) blanking time  
during power-up,  
short circuit  
P_13.12.32  
detection for  
VS VS,UV  
Reset Generator; Pin RSTN  
Reset Low Output Voltage VRSTN,L  
0.2  
0.4  
V
V
IRSTN = 1 mA for  
VCC1 1 V &  
VS VPOR,f  
P_13.12.33  
P_13.12.34  
Reset High Output Voltage VRSTN,H  
0.8 x  
VCC1  
+
IRSTN = -20 µA  
VCC1  
0.3 V  
Reset Pull-up Resistor  
Reset Filter Time  
RRSTN  
tRF  
10  
4
20  
10  
40  
26  
kΩ  
VRSTN = 0 V  
P_13.12.35  
P_13.12.36  
2)  
µs  
V
< VRT1x  
CC1  
to RSTN = L see  
also Chapter 12.3  
Reset Delay Time 1  
Reset Delay Time 2  
tRD1  
tRD2  
8
10  
2
12  
ms  
ms  
2) RSTN_DEL = 0  
2) RSTN_DEL = 1  
P_13.12.37  
P_13.12.64  
1.6  
2.4  
Watchdog Generator / Internal Oscillator  
2)  
Long Open Window  
tLW  
160  
0.8  
200  
1.0  
240  
1.2  
ms  
P_13.12.42  
P_13.12.43  
Internal Clock Generator  
Frequency  
fCLKSBC,1  
MHz  
Minimum Waiting time during Fail-Safe Mode  
Min. waiting time Fail-Safe tFS,min 80  
2)3)  
100  
120  
ms  
P_13.12.45  
Power-on Reset, Over / Undervoltage Protection  
VSINT Power on reset rising VPOR,r  
4.5  
3
V
V
VSINT increasing P_13.12.46  
VSINT decreasing P_13.12.47  
VSINT Power on reset  
falling  
VPOR,f  
VSINT Undervoltage  
Detection Threshold  
VSINT,UV  
5.3  
6.0  
V
Supply UV  
P_13.12.48  
threshold for VCC1  
SC detection;  
hysteresis  
included; includes  
rising and falling  
threshold  
Datasheet  
137  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Supervision Functions  
Table 38 Electrical Characteristics (cont’d)  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current  
defined flowing into pin; unless otherwise specified.  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
VSHS Overvoltage  
VSHS,OVD  
20  
22  
V
Supply OV  
P_13.12.55  
Detection Threshold  
supervision for  
HSx, LIN;  
hysteresis  
included  
6)  
VSHS Overvoltage  
Detection hysteresis  
VSHS,OVD,hys 100  
VSHS,UVD 4.8  
500  
mV  
V
P_13.12.56  
P_13.12.57  
VSHS Undervoltage  
Detection Threshold  
5.5  
Supply UV  
supervision for  
HSx, LIN;  
hysteresis  
included  
6)  
VSHS Undervoltage  
Detection hysteresis  
VSHS,UVD,hys 50  
200  
10  
350  
14  
mV  
us  
P_13.12.58  
VSHS Undervoltage  
Detection Filter Time  
tVSHS,UV  
tVSHS,OV  
5
5
2) rising and falling P_13.12.300  
2) rising and falling P_13.12.301  
VSHS Overvoltage  
10  
14  
us  
Detection Filter Time  
Charge Pump Undervoltage  
Charge Pump  
Undervoltage Referred to  
VS  
VCPUV1  
5.4  
5.9  
6.35  
7.35  
8
6.4  
V
V
V
V
FET_LVL = 0  
CPUVTH = 0  
falling threshold,  
VS 6 V  
P_13.12.59  
P_13.12.60  
P_13.12.61  
P_13.12.62  
Charge Pump  
Undervoltage Referred to  
VS  
VCPUV2  
VCPUV3  
VCPUV4  
5.85  
6.85  
7.5  
6.85  
7.85  
8.5  
FET_LVL = 0  
CPUVTH = 1  
falling threshold,  
VS 6 V  
Charge Pump  
Undervoltage Referred to  
VS  
FET_LVL = 1  
CPUVTH = 0  
falling threshold,  
VS 6 V  
Charge Pump  
Undervoltage Referred to  
VS  
FET_LVL = 1  
CPUVTH = 1  
falling threshold,  
VS 6 V  
Charge Pump  
Undervoltage Filter Time  
tCPUV  
51  
64  
80  
µs  
µs  
6)VS 6 V  
P_13.12.63  
Charge Pump  
tCPUVBLANK  
400  
500  
600  
6)VS 6 V  
P_13.12.175  
Undervoltage Blank Time  
VS monitoring  
Datasheet  
138  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Supervision Functions  
Table 38 Electrical Characteristics (cont’d)  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current  
defined flowing into pin; unless otherwise specified.  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
VS undervoltage threshold VS,UV  
4.7  
5.4  
V
hysteresis  
P_13.12.66  
P_13.12.68  
included  
VS overvoltage threshold VS,OVD1  
detection 1  
19  
22.5  
V
hysteresis  
included,  
VS_OV_SEL = 0  
VS overvoltage threshold VS,OVD2  
27.75  
31.25  
V
hysteresis  
P_13.12.65  
detection 2  
included,  
VS_OV_SEL = 1  
VS undervoltage filter time tVSUV_FILT  
VS overvoltage filter time tVSOV_FILT  
Off-state open load diagnosis  
5
5
10  
10  
14  
14  
µs  
µs  
2) rising and falling P_13.12.71  
2) rising and falling P_13.12.72  
Pull-up diagnosis current IPUDiag  
-600  
-400  
-270  
µA  
µA  
VS 6 V  
VS 6 V  
P_13.12.73  
P_13.12.74  
Pull-down diagnosis  
current  
IPDDiag  
1600  
2200  
2800  
Diagnosis current ratio  
IDiag_ratio  
4.25  
5.25  
6.25  
Ratio  
P_13.12.302  
IPDDiag / IPUDiag  
Drain-source monitoring CP activated  
Blank time  
tBLANK  
typ-  
20%  
587  
+266  
xTBLK  
typ+20 ns  
%
6) TBLK: decimal  
valueofTBLK[3:0],  
VS 6 V  
P_13.12.75  
P_13.12.76  
Cross-current protection  
time  
tCCP  
typ-  
20%  
587  
+266  
xTCCP  
typ+20 ns  
%
6) TCCP: decimal  
value of  
TCCPx[3:0],  
VS 6 V  
HS/LS Drain-source  
overvoltage 0  
VVDSMONTH0_ 0.115 0.16  
0.195  
0.25  
0.36  
0.48  
0.6  
V
V
V
V
V
V
V
VDSTH[2:0] = 000B, P_13.12.77  
VS6 V, TFVDS=00B  
CPON  
HS/LS Drain-source  
overvoltage 1  
VVDSMONTH1_ 0.16  
0.2  
0.3  
0.4  
0.5  
0.6  
0.8  
VDSTH[2:0] = 001B, P_13.12.78  
VS6 V, TFVDS=00B  
CPON  
HS/LS Drain-source  
overvoltage 2  
VVDSMONTH2_ 0.24  
VDSTH[2:0] = 010B, P_13.12.79  
VS6 V, TFVDS=00B  
CPON  
HS/LS Drain-source  
overvoltage 3  
VVDSMONTH3_ 0.32  
VDSTH[2:0] = 011B, P_13.12.80  
VS6 V, TFVDS=00B  
CPON  
HS/LS Drain-source  
overvoltage 4  
VVDSMONTH4_ 0.4  
VDSTH[2:0] = 100B, P_13.12.81  
VS6 V, TFVDS=00B  
CPON  
HS/LS Drain-source  
overvoltage 5  
VVDSMONTH5_ 0.48  
0.72  
0.96  
VDSTH[2:0] = 101B, P_13.12.82  
VS6 V, TFVDS=00B  
CPON  
HS/LS Drain-source  
overvoltage 6  
VVDSMONTH6_ 0.64  
VDSTH[2:0] = 110B, P_13.12.83  
VS6 V, TFVDS=00B  
CPON  
Datasheet  
139  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Supervision Functions  
Table 38 Electrical Characteristics (cont’d)  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current  
defined flowing into pin; unless otherwise specified.  
Parameter  
Symbol  
Values  
Typ.  
2.0  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
HS/LS Drain-source  
overvoltage 7  
VVDSMONTH7_ 1.75  
2.25  
V
VDSTH[2:0] = 111B, P_13.12.84  
VS6 V, TFVDS=00B  
CPON  
Drain-Source monitoring - Slam mode, parking braking and VS overvoltage braking, VS or VSINT 8V  
Blank time  
tBLK_BRAKE1 4.5  
7
9.5  
µs  
TBLK_BRK = 0,  
P_13.12.85  
VS or VSINT 8 V  
Blank time  
tBLK_BRAKE2  
9
11  
13  
µs  
TBLK_BRK = 1,  
P_13.12.86  
VS or VSINT 8 V  
VDS Filter time  
tFVDS_BRAKE 0.5  
VVDSMONTH0_ 0.56  
1
2.5  
µs  
V
VS or VSINT 8 V P_13.12.87  
LS Drain-source  
monitoring thresholds  
0.8  
1.05  
VS or VSINT 8 V P_13.12.89  
VDSTH_BRK = 0  
BRAKE  
LS Drain-source  
monitoring thresholds  
VVDSMONTH1_ 0.15  
0.22  
0.29  
V
VS or VSINT 8 V P_13.12.90  
VDSTH_BRK = 1  
BRAKE  
VS Overvoltage Braking Mode  
VS Overvoltage braking  
config 0 rising  
VOVBR,cfg0,r  
25.65 27  
28.35  
29.40  
30.45  
31.50  
32.55  
33.60  
34.65  
35.70  
0.85  
V
V
V
V
V
V
V
V
V
V
V
V
V
OV_BRK_TH=000B P_13.12.97  
OV_BRK_TH=001B P_13.12.98  
OV_BRK_TH=010B P_13.12.99  
OV_BRK_TH=011B P_13.12.100  
OV_BRK_TH=100B P_13.12.101  
OV_BRK_TH=101B P_13.12.102  
OV_BRK_TH=110B P_13.12.103  
OV_BRK_TH=111B P_13.12.104  
OV_BRK_TH=000B P_13.12.105  
OV_BRK_TH=001B P_13.12.109  
OV_BRK_TH=010B P_13.12.113  
OV_BRK_TH=011B P_13.12.117  
OV_BRK_TH=100B P_13.12.121  
VS Overvoltage braking  
config 1 rising  
VOVBR,cfg1,r  
VOVBR,cfg2,r  
VOVBR,cfg3,r  
VOVBR,cfg4,r  
VOVBR,cfg5,r  
VOVBR,cfg6,r  
VOVBR,cfg7,r  
VHYS,cfg0  
26.60 28  
27.55 29  
28.50 30  
29.45 31  
30.40 32  
31.35 33  
32.30 34  
VS Overvoltage braking  
config 2 rising  
VS Overvoltage braking  
config 3 rising  
VS Overvoltage braking  
config 4 rising  
VS Overvoltage braking  
config 5 rising  
VS Overvoltage braking  
config 6 rising  
VS Overvoltage braking  
config 7 rising  
VS Overvoltage braking  
config 0  
0.64  
0.74  
0.80  
0.85  
0.93  
0.75  
VS Overvoltage braking  
config 1  
VHYS,cfg1  
0.82  
0.89  
0.95  
1.03  
0.9  
VS Overvoltage braking  
config 2  
VHYS,cfg2  
0.98  
VS Overvoltage braking  
config 3  
VHYS,cfg3  
1.05  
VS Overvoltage braking  
config 4  
VHYS,cfg4  
1.13  
Datasheet  
140  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Supervision Functions  
Table 38 Electrical Characteristics (cont’d)  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current  
defined flowing into pin; unless otherwise specified.  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
VS Overvoltage braking  
config 5  
VHYS,cfg5  
VHYS,cfg6  
VHYS,cfg7  
0.97  
1.08  
1.19  
V
OV_BRK_TH=101B P_13.12.125  
OV_BRK_TH=110B P_13.12.129  
OV_BRK_TH=111B P_13.12.133  
VS Overvoltage braking  
config 6  
1.03  
1.1  
10  
1.15  
1.23  
15  
1.27  
1.36  
20  
V
VS Overvoltage braking  
config 7  
V
6)  
VS and VSINT overvoltage tOV_BR_FILT  
µs  
P_13.12.200  
braking filter time  
Current sense amplifier4)  
Operating common mode VCM  
input voltage range  
-2.0  
2.0  
V
P_13.12.138  
referred to GND (CSAP -  
GND) or (CSAN- GND)  
Common Mode Rejection CMRR  
Ratio  
63  
69  
75  
77  
dB  
6) CSAG = (0,0)  
CSAG = (0,1)  
CSAG = (1,0)  
CSAG = (1,1)  
DC to 50 kHz  
P_13.12.139  
V
V
CM = -2 … 2 V  
CSAP = VCSAN  
6)  
Settling time to 98%  
tSET  
1500  
2000  
5000  
ns  
ns  
P_13.12.140  
P_13.12.141  
Settling time to 98% after tSET_GAIN  
6) After gain  
gain change  
change from CSN  
rising edge  
Input Offset voltage  
VOS  
-1  
0
1
mV  
P_13.12.142  
P_13.12.143  
Current Sense Amplifier DC GDIFF10  
Gain (uncalibrated)  
9.91  
10.04 10.17 V/V  
CSAG = (0,0)  
CSAG = (0,1)  
CSAG = (1,0)  
CSAG = (1,1)  
Current Sense Amplifier DC GDIFF20  
Gain (uncalibrated)  
19.79 20.05 20.31 V/V  
39.53 40.05 40.57 V/V  
59.34 60.12 60.91 V/V  
P_13.12.144  
P_13.12.145  
P_13.12.146  
Current Sense Amplifier DC GDIFF40  
Gain (uncalibrated)  
Current Sense Amplifier DC GDIFF60  
Gain (uncalibrated)  
Gain drift  
GDRIFT  
VCSO  
-0.5  
0.5  
0.5  
%
V
6) Gain drift after P_13.12.151  
calibration  
6)  
CSO single ended output  
voltage range (linear  
range)  
VCC1  
0.5  
-
P_13.12.152  
Reference voltage for  
unidirectional CSAx  
VREF Unidir  
-1.25% VCC1/5 +1.25% V  
CSD = 0  
CSAP = VCSAN  
P_13.12.153  
V
Datasheet  
141  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Supervision Functions  
Table 38 Electrical Characteristics (cont’d)  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current  
defined flowing into pin; unless otherwise specified.  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Reference voltage for  
bidirectional CSAx  
VREF Bidir  
-1%  
VCC1/2 +1%  
V
CSD = 1  
CSAP = VCSAN  
P_13.12.154  
V
Overcurrent detection  
5)6)  
Overcurrent filter time  
tFOC  
4
6
8
µs  
OCFILT = 00B  
P_13.12.155  
7
40  
80  
10  
50  
100  
13  
60  
120  
OCFILT = 01B  
OCFILT = 10B  
OCFILT = 11B  
OC threshold,  
unidirectional  
VOCTH1 Unidir -4%  
VCC1/2 +4%  
V
V
CSD = 0,  
OCTH[1:0]= 00B  
P_13.12.156  
P_13.12.157  
OC threshold,  
unidirectional  
VOCTH2 Unidir -4%  
VCC1/2 +4%  
+
CSD = 0,  
OCTH[1:0]= 01B  
V
CC1/10  
OC threshold,  
unidirectional  
VOCTH3 Unidir -4%  
VCC1/2 +4%  
V
CSD = 0,  
OCTH[1:0]= 10B  
P_13.12.158  
+ 2x  
VCC1/1  
0
OC threshold,  
unidirectional  
VOCTH4 Unidir -4%  
VOCTH1 BidirH -4%  
VOCTH2 BidirH -4%  
VOCTH3 BidirH -4%  
VOCTH4 BidirH -4%  
VOCTH1 BidirL -4%  
VOCTH2 BidirL -4%  
VOCTH3 BidirL -4%  
VCC1/2 +4%  
+ 3x  
V
V
V
V
V
V
V
V
CSD = 0,  
OCTH[1:0]= 11B  
P_13.12.159  
P_13.12.160  
P_13.12.161  
P_13.12.162  
P_13.12.163  
P_13.12.164  
P_13.12.165  
P_13.12.166  
V
CC1/10  
High OC threshold,  
bidirectional  
VCC1/2 +4%  
+ 2x  
CSD = 1,  
OCTH[1:0]= 00B  
V
CC1/20  
High OC threshold,  
bidirectional  
VCC1/2 +4%  
+ 4x  
CSD = 1,  
OCTH[1:0]= 01B  
V
CC1/20  
High OC threshold,  
bidirectional  
VCC1/2 +4%  
+ 5x  
CSD = 1,  
OCTH[1:0]= 10B  
V
CC1/20  
High OC threshold,  
bidirectional  
VCC1/2 +4%  
+ 6x  
CSD = 1,  
OCTH[1:0]= 11B  
V
CC1/20  
Low OC threshold,  
bidirectional  
VCC1/2 - +4%  
2x  
CSD = 1,  
OCTH[1:0]= 00B  
V
CC1/20  
Low OC threshold,  
bidirectional  
VCC1/2 - +4%  
4x  
CSD = 1,  
OCTH[1:0]= 01B  
V
CC1/20  
Low OC threshold,  
bidirectional  
VCC1/2 - +4%  
5x  
CSD = 1,  
OCTH[1:0]= 10B  
V
CC1/20  
Datasheet  
142  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Supervision Functions  
Table 38 Electrical Characteristics (cont’d)  
VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current  
defined flowing into pin; unless otherwise specified.  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
VOCTH4 BidirL -4%  
Max.  
Low OC threshold,  
bidirectional  
VCC1/2 - +4%  
6x  
V
CSD = 1,  
OCTH[1:0]= 11B  
P_13.12.167  
V
CC1/20  
Current Sense Amplifier Dynamic Parameters  
Power Supply Rejection  
Ratio  
PSRR  
60  
dB  
°C  
6) VCP modulated P_13.12.168  
with sinewave  
(100 kHz, 1 Vpp  
Overtemperature Shutdown6)  
Thermal Prewarning  
Temperature  
TjPW  
125  
145  
165  
Tj rising  
Tj rising  
P_13.12.169  
Thermal Shutdown TSD1 TjTSD1  
Thermal Shutdown TSD2 TjTSD2  
170  
170  
185  
185  
25  
200  
200  
°C  
°C  
°C  
P_13.12.170  
P_13.12.171  
P_13.12.172  
Tj rising  
6)  
Thermal Shutdown  
hysteresis  
TjTSD,hys  
TSD/TPW Filter Time  
tTSD_TPW_F  
5
10  
15  
us  
rising and falling, P_13.12.173  
applies to all  
thermal sensors  
(TPW, TSD1, TSD2)  
2)  
Deactivation time after  
thermal shutdown TSD2  
tTSD2  
0.8  
1
1.2  
s
P_13.12.174  
1) It is ensured that the threshold VCC1,OV,r is always higher than the highest regulated VCC1 output voltage VCC1,out4  
.
.
2) Not subject to production test, tolerance defined by internal oscillator tolerance.  
3) This time applies for all failure entries except a device thermal shutdown (TSD2 has a typ. 1 s waiting time tTSD2).  
4) 6 V VS 23 V  
5) tFOC refers to the output of the current sense amplifier. The CSO settling time (2 µs max, tSET) and the analog  
propagation delay (< 1 µs)are not taken into account by the overcurrent filter time.  
6) Not subject to production test, specified by design.  
Datasheet  
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Rev.1.0  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13  
Serial Peripheral Interface  
The Serial Peripheral Interface is the communication link between the device and the microcontroller.  
The TLE9564QX is supporting multi-slave operation in full-duplex mode with 32-bit data access.  
The SPI behavior for the different device modes is as follows:  
The SPI is enabled in Init Mode, Normal Mode and Stop Mode.  
The SPI is OFF in Sleep Mode, Restart Mode and Fail-Safe Mode.  
13.1  
SPI Block Description  
The Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK provided  
by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 69 with a  
32-bit data access example).  
The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After  
the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content.  
The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for  
other use.The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is  
shifted out of the output register after every rising edge on CLK. The SPI of the device is not daisy chain  
capable.  
CSN high to low: SDO is enabled. Status information transferred to output shift register  
CSN  
time  
CSN low to high: data from shift register is transferred to output functions  
CLK  
time  
Actual data  
New data  
LSB  
MSB  
0 1  
SDI  
0 1 2 3 4 5 6  
27 28 29 30 31  
+ +  
time  
SDI: will accept data on the falling edge of CLK signal  
Actual status  
New status  
LSB  
MSB  
0
1
ERR  
SDO  
ERR  
0 1 2 3 4 5 6  
27 28 29 30 31  
-
+
+
time  
SDO: will change state on the rising edge of CLK signal  
Figure 69 SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure  
compared to the register description)  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.2  
Failure Signalization in the SPI Data Output  
When the microcontroller sends a wrong SPI command to the device, the device ignores the information.  
Wrong SPI commands are either invalid device mode commands or commands which are prohibited by the  
state machine to avoid undesired device or system states (see below). In this case the diagnosis bit SPI_FAIL  
is set and the SPI Write command is ignored (no partial interpretation). This bit can be only reset by actively  
clearing it via a SPI command.  
Invalid SPI Commands leading to SPI_FAIL are listed below (in this case the SPI command is ignored):  
Illegal state transitions:  
- Going from Stop Mode to Sleep Mode. In this case the device enters Restart Mode.  
- Trying to go to Stop Mode or Sleep Mode from Init Mode1). In this case Normal Mode is entered.  
Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored and/or  
the new watchdog settings are ignored respectively.  
In Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration, PWM  
settings and HSx configuration settings during Stop Mode, etc.;  
the SPI command is ignored in this case;  
only WD trigger, returning to Normal Mode, triggering a device soft reset, and read & clear status registers  
commands are valid SPI commands in Stop Mode; Note: No failure handling is done for the attempt to go  
to Stop Mode when all bits in the registers BUS_CTRL and WK_CTRL are cleared because the  
microcontroller can leave this mode via SPI.  
When entering Stop Mode and WK_STAT is not cleared; SPI_FAIL will not be set but the INTN pin will be  
triggered.  
Changing from Stop Mode to Normal Mode and changing the other bits of the M_S_CTRL register. The  
other modifications will be ignored.  
Sleep Mode: attempt to go to Sleep Mode without any wake source set, i.e. when all bits in the BUS_CTRL  
and WK_CTRL registers are cleared. In this case the SPI_FAIL bit is set and the device enters Restart Mode.  
Even though the Sleep Mode command is not entered in this case, the rest of the command is executed but  
restart values apply during Restart Mode; Note: At least one wake source must be activated in order to  
avoid a deadlock situation in Sleep Mode.  
If the only wake source is a timer and the timer is OFF, then the device will wake immediately from Sleep  
Mode and enter Restart Mode.  
Setting a longer or equal on-time than the timer period of the respective timer.  
SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’.  
Configured the HSx controlled by SYNC when the WK4/SYNC is not configured as SYNC-input.  
Note:  
Note:  
There is no SPI fail information for unused addresses.  
In case that the register or banking are accessed but they are not valid as address or banks, the  
SPI_FAIL is not triggered and the cmd is ignored.  
Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 69):  
The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set  
for following conditions:  
1) If the device is externally configured to use SPI with CRC (by PWM1/CRC pin), the attempt to go to Stop or Sleep from Init , will  
generate SPI_FAIL even if it is a SPI command with correct CRC. Still, the first SPI command will put the device from Init to Normal  
Mode even if CRC is not correct (CRC_FAIL status bit will be set).  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
in case the number of received SPI clocks is not 0 or 32.  
in case RSTN is LOW and SPI frames are being sent at the same time.  
Note:  
In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is  
not valid if the CLK is high on a falling edge of CSN.  
The number of received SPI clocks is not 0 or 32:  
The number of received input clocks is supervised to be 0 or 32 clock cycles and the input word is discarded in  
case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high  
during CSN edges. Both errors ( 0 or 32 bit CLK mismatch or CLK high during CSN edges ) are flagged in the  
following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the clock  
is received. The complete SPI command is ignored in this case.  
RSTN is LOW and SPI frames are being sent at the same time:  
The ERR flag will be set when the RSTN pin is triggered (during device restart) and SPI frames are being sent to  
the device at the same time. The behavior of the ERR flag will be signalized at the next SPI command for below  
conditions:  
If the command begins when RSTN is HIGH and it ends when RSTN is LOW.  
If a SPI command will be sent while RSTN is LOW.  
If a SPI command begins when RSTN is LOW and it ends when RSTN is HIGH.  
And the SDO output will behave as follows:  
Always when RSTN is LOW then SDO will be HIGH.  
When a SPI command begins when RSTN is LOW and ends when RSTN is HIGH, then the SDO should be  
ignored because wrong data will be sent.  
Note:  
It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled  
low and SDO is observed - no SPI Clocks are sent in this case.  
Note:  
The ERR flag could also be set after the device has entered Fail-Safe Mode because the SPI  
communication is stopped immediately.  
Datasheet  
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Rev. 1.0  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.3  
SPI Programming  
For the TLE9564QX, 7 bits are used for the address selection (BIT 6...0). Bit 7 is used to decide between Read  
Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the  
actual configuration and status information, 16 data bits (BIT 23...8) are used.  
Writing, clearing and reading is done word wise. The SPI status bits are not cleared automatically and must be  
cleared by the microcontroller. Some of the configuration bits will automatically be cleared by the device  
(refer to the respective register descriptions for detailed information). In Restart Mode, the device ignores all  
SPI communication, i.e. it does not interpret it.  
There are two types of SPI registers:  
Control registers: These registers are used to configure the device, e.g. mode, watchdog trigger, etc.  
Status registers: These registers indicate the status of the device, e.g. wake events, warnings, failures, etc.  
For the status registers, the requested information is given in the same SPI command in the data out (SDO).  
For the control registers, the status of each byte is shown in the same SPI command as well. However,  
configuration changes of the same register are only shown in the next SPI command (configuration changes  
inside the device become valid only after CSN changes from low to high). See Figure 70.  
Writing of control registers is possible in Init and Normal Mode. During Stop Mode only the change to Normal  
Mode and triggering the watchdog is allowed as well as reading and clearing the status registers.  
No status information can be lost, even if a bit changes right after the first 7 SPI clock cycles before the SPI  
frame ends. In this case the status information field will be updated with the next SPI command. However, the  
flag is already set in the relevant status register.The device status information from the SPI status registers is  
transmitted in a compressed format with each SPI response on SDO in the so-called Status Information Field  
register (see also Table 39). The purpose of this register is to quickly signal changes in dedicated SPI status  
registers to the microcontroller.  
Table 39 Status Information Field  
Bit in Status  
Information Field  
Corresponding  
Address Bit  
Status Register Description  
0
1
2
3
4
SUPPLY_STAT = OR of all bits on SUP_STAT register  
TEMP_STAT = OR of all bits on THERM_STAT register  
BUS_STAT= OR of all bits on BUS_STAT register  
WAKE_UP = OR of all bits on WK_STAT register  
HS_STAT = OR of all bits on HS_OL_OC_OT_STAT  
register  
5
DEV_STAT = OR of all bits on DEV_STAT except  
CRC_STAT and SW_DEV  
6
7
BD_STAT = OR of all bits on DSOV register  
SPI_CRC_FAIL = (SPI_FAIL) OR (CRC_FAIL)  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
MSB  
LSB  
DI  
0
1
2
3
4
5
6
7
8
x
9
x
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
R/W  
Address Bits  
Data Bits  
CRC or Static Pattern  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Register content of  
selected address  
DO  
0
1
2
3
4
5
6
7
8
x
9
x
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
Status Information Field  
Data Bits  
CRC or Static Pattern  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
time  
LSB is sent first in SPI message  
Figure 70 SPI Operation Mode  
13.3.1  
CRC  
The SPI interface includes also 8 Bits (bits 24 to 31) used for Cyclic Redundancy Check (CRC) to ensure data  
integrity on sent or received SPI command.  
The implemented CRC is based on Autosar specification of CRC Routines revision 4.3.0 and in particular the  
function CRC8-2FH.  
The specification are based on the follow table:  
Table 40 CRC8x2FH definition  
CRC result width:  
Polynomial  
8 bits  
2FH  
FFH  
No  
Initial Value  
Input data reflected  
Result data reflected  
XOR value  
No  
FFH  
DFH  
42H  
Check  
Magic check  
Some examples of CRC calculation are shown in the follow table:  
Table 41 CRC8x2FH calculation example  
Data Bytes (hexadecimal)  
CRC  
12  
00  
F2  
0F  
00  
33  
92  
FF  
00  
01  
AA  
FF  
22  
6B  
FF  
00  
83  
00  
55  
55  
55  
FF  
00  
C2  
C6  
77  
55  
11  
AA  
BB  
CC  
DD  
EE  
FF  
11  
33  
FF  
6C  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Polynominal  
The polynomial is:  
x8 + x5 + x3 + x2 + x1 + x0  
(13.1)  
Calculation in SDI and SDO  
The calculation of the CRC is done considering the first 24 bits (BIT 0..23) either of SDI or SDO.  
The content of SDO Payload (BIT 8..23) is referring the previous data written at the addressed register via SDI.  
SDI  
r
Add.  
Payload - Configuration  
CRC  
CRC  
w
PASS/FAIL  
SDO  
Status Info. Field  
From previous SPI cmd  
Figure 71 CRC calculation  
CRC Activation and status information  
For CRC activation, refer to Chapter 5.2.  
The CRC status (CRC_STAT)and failure (CRC_FAIL) are readable on DEV_STAT.  
Read out of the register which contains the CRC_STAT and CRC_FAIL is done ignoring the CRC field and no  
failure flag are set.  
The DEV_STAT register shall be cleared considering the CRC setting (ON or OFF).  
The CRC_STAT bit is read only.  
The CRC_FAIL is set in the follow conditions:  
If the CRC is enabled and the µC sends wrong CRC field.  
If the CRC is disabled and the µC sends wrong static pattern (no A5H).  
CRC field in case of CRC disabled  
In case that the CRC is not activated, the bits needed for CRC field have to be filled with static pattern.  
In case of SDI, the CRC field has to be filled with A5H (bits 24:31).  
In case of SDO, the device will always answer with 5AH (bits 24:31).  
The status of the CRC is updated accordingly in CRC_STAT bit.  
Datasheet  
149  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.4  
SPI Bit Mapping  
The following figures show the mapping of the registers and the SPI bits of the respective registers.  
The Control Registers are Read/Write Register with the following structure:  
Device Control Registers from 000 0001B to 000 1011B.  
Bridge Driver Control Registers from 001 0000B to 001 1101B.  
Depending on bit 7 the bits are only read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting  
of the bit after a write can be seen with a new read / write command.  
The Status Registers are Read/Clear with the following structure:  
Device Status Registers from 100 0000B to 100 0110B.  
Bridge Driver Status Registers from 101 0000B to 101 1011B.  
Product Family is 111 0000B.  
The registers can be read or can be cleared (if clearing is possible) depending on bit 7. To clear the payload of  
one of the Status Registers bit 7 must be set to 1.  
The registers WK_LVL_STAT, and FAM_PROD_STAT are an exception as they show the actual voltage level at  
the respective WKx pin (LOW/HIGH), or a fixed family/ product ID respectively and can thus not be cleared.  
It is recommended for proper diagnosis to clear respective status bits for wake events or failure.  
When changing to a different device mode, certain configurations bits will be cleared automatically or  
modified:  
The device mode bits are updated to the actual status, e.g. when returning to Normal Mode.  
When changing to a low-power mode (Stop Mode or Sleep Mode), the diagnosis bits of the integrated  
module are not cleared.  
When changing to Stop Mode, the LIN control bits will not be modified.  
When changing to Sleep Mode, the LIN control bits will be modified if they were not OFF or wake capable  
before.  
Note:  
The detailed behavior of the respective SPI bits and control functions is described in Chapter 13.5,  
Chapter 13.6.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the  
device will modify respective control bits.  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Reg.  
Type  
7 Address Bits [bits 6...0]  
16 Data Bits [bits 23...8]  
for Register Selection  
for Configuration & Status Information  
Addresses:  
0 0 0 0 0 0 1  
.
.
.
0 0 0 1 0 1 1  
Addresses:  
0 0 1 0 0 0 0  
.
.
.
0 0 1 1 1 0 1  
Addresses:  
1 0 0 0 0 0 0  
.
.
.
1 1 1 0 0 0 0  
The most important status registers are represented in the  
Status Information Field  
Figure 72 SPI Register Mapping Structure  
The detailed register mappings for control registers and status registers are shown in Table 42 and Table 68  
respectively.  
13.4.1  
Register Banking  
In order to minimize the number of configuration registers, seven registers follow a bank structure.  
The banked registers are:  
WK_CTRL  
PWM_CTRL  
CCP_BLK  
TPRECHG  
HB_ICHG  
HB_PCHG_INIT  
TDON_HB_CTRL  
TDOFF_HB_CTRL  
In these register, the first 3 bits of the payload (bit 8 to 10) select the bank that has to be configured. The rest  
of the payload is used to configure the selected bank (for more details refer to the specific banked register).  
In case that CRC is used, the CRC calculation is done considering the first 24 bits (from bit 0 to 23).  
The banked registers can be read like the other configuration registers but in the SDO one ‘0’ is automatically  
added after the status information field. Figure 73 shows the structure of SDO in banked register.  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
SDI  
B
K
0
B
K
1
B
K
2
R
e
s
Configuration of selected Bank  
Selected Bank Content  
r
w
Add.  
CRC  
CRC  
SDO  
B
K
0
B
K
1
B
K
2
Status Info. Filed  
0
Figure 73 Register read Out of banked register (3 bit banking)  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.5  
SPI control registers  
READ/WRITE Operation (see also Chapter 13.3):  
The ‘POR / Soft Reset Value’ defines the register content after POR or device reset.  
The ‘Restart Value’ defines the register content after device restart, where ‘x’ means the bit is unchanged.  
There are different bit types:  
‘r’ = READ: read only bits (or reserved bits).  
‘rw’ = READ/WRITE: readable and writable bits.  
‘rwh’ = READ/WRITE/Hardware: readable/writable bits, which can also be modified by the device  
hardware.  
Reserved bits are marked as “Reserved” and always read as “0”. The respective bits shall also be  
programmed as “0”.  
Reading a register is done word wise by setting the SPI bit 7 to “0” (= Read Only).  
SPI control bits are in general not cleared or changed automatically. This must be done by the  
microcontroller via SPI programming. Exceptions to this behavior are stated at the respective register  
description and the respective bit type is marked with a ‘h’ meaning that the device is able to change the  
register content.  
The registers are addressed wordwise.  
Table 42 Register Overview  
Register Short Name  
Register Long Name  
Offset Address Page  
Number  
SPI control registers, Device Control Registers  
M_S_CTRL  
HW_CTRL  
Mode and Supply Control  
0000001B  
0000010B  
0000011B  
0000100B  
0000101B  
0000110B  
0000111B  
0001000B  
0001001B  
0001010B  
0001011B  
155  
Hardware Control  
157  
159  
161  
162  
164  
166  
168  
170  
172  
173  
WD_CTRL  
Watchdog Control  
BUS_CTRL  
WK_CTRL  
and LIN Control  
Wake-up Control  
TIMER_CTRL  
SW_SD_CTRL  
HS_CTRL  
Timer 1 and Timer 2 Control and Selection  
High-Side Switch Shutdown Control  
High-Side Switch Control  
Interrupt Mask Control  
PWM Configuration Control  
System Status Control  
INT_MASK  
PWM_CTRL  
SYS_STAT_CTRL  
SPI control registers, Control registers bridge driver  
GENCTRL  
CSA  
General Bridge Control  
0010000B  
0010001B  
0010010B  
0010011B  
0010100B  
0010101B  
0010110B  
174  
176  
178  
180  
182  
183  
185  
Current sense amplifier  
LS_VDS  
HS_VDS  
CCP_BLK  
HBMODE  
TPRECHG  
Drain-Source monitoring threshold  
Drain-Source monitoring threshold  
CCP and times selection  
Half-Bridge MODE  
PWM pre-charge and pre-discharge time  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 42 Register Overview (cont’d)  
Register Short Name  
Register Long Name  
Offset Address Page  
Number  
186  
ST_ICHG  
Static charge/discharge current  
PWM charge/discharge current  
0010111B  
0011000B  
0011001B  
HB_ICHG  
187  
188  
HB_ICHG_MAX  
PWM max. pre-charge/pre-discharge current  
and diagnostic pull-down  
HB_PCHG_INIT  
TDON_HB_CTRL  
TDOFF_HB_CTRL  
BRAKE  
PWM pre-charge/pre-discharge initialization  
PWM inputs TON configuration  
PWM inputs TOFF configuration  
Brake control  
0011010B  
0011011B  
0011100B  
0011101B  
190  
191  
192  
193  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.5.1  
Device Control Registers  
Mode and Supply Control  
M_S_CTRL  
Mode and Supply Control  
(000 0001B)  
Reset Value: see Table 43  
15  
MODE  
rwh  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
VCC1_OV_MO  
D
RSTN_  
HYS  
I_PEA  
K_TH  
RES  
RES  
RES  
RES  
VCC1_RT  
r
rwh  
r
rw  
r
rw  
r
rw  
Field  
Bits  
15:14  
Type  
Description  
Device Mode Control  
MODE  
rwh  
00B NORMAL, Normal Mode  
01B SLEEP, Sleep Mode  
10B STOP, Stop Mode  
11B RESET, Device reset: Soft reset is executed  
(configuration of RSTN triggering in bit  
SOFT_RESET_RO)  
RES  
13:11  
10:9  
r
Reserved, always reads as 0  
VCC1_OV_MOD  
rwh  
Reaction in case of VCC1 Over Voltage  
00B NO, no reaction  
01B INTN, INTN event is generated  
10B RSTN, RSTN event is generated  
11B FAILSAFE, Fail-Safe Mode is entered  
RES  
8
7
r
Reserved, always reads as 0  
RSTN_HYS  
rw  
VCC1 Undervoltage Reset Hysteresis Selection (see  
also Chapter 12.7.1 for more information)  
0B DEFAULT, default hysteresis applies as specified  
in the electrical characteristics table  
1B HIGHEST, the highest rising threshold (VRT1,R) is  
always used for the release of the undervoltage  
reset  
RES  
6
5
r
Reserved, always reads as 0  
I_PEAK_TH  
rw  
VCC1 Active Peak Threshold Selection  
0B LOW, low VCC1 active peak threshold selected  
1B HIGH, high VCC1 active peak threshold selected  
RES  
4:2  
1:0  
r
Reserved, always reads as 0  
VCC1_RT  
rw  
VCC1 Reset Threshold Control  
00B VRT1, Vrt1 selected (highest threshold)  
01B VRT2, Vrt2 selected  
10B VRT3, Vrt3 selected  
11B VRT4, Vrt4 selected  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 43 Reset of M_S_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 0000 x0x0 00xxB  
Notes  
1. It is not possible to change from Stop Mode to Sleep Mode via SPI Command. See also the State Machine  
Chapter.  
2. After entering Restart Mode, the MODE bits will be automatically set to Normal Mode.  
3. The SPI output will always show the previously written state with a Write Command (what has been  
programmed before) .  
Datasheet  
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TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Hardware Control  
HW_CTRL  
Hardware Control  
(000 0010B)  
Reset Value: see Table 44  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
SOFT_  
RESET RES  
_RO  
WD_S  
TM_E  
N_1  
TSD2_ VS_OV SH_DI RSTN_  
DEL _SEL SABLE DEL  
RES  
RES  
RES  
RES  
r
rw  
rw  
rw  
rw  
r
rw  
r
r
rwh  
r
Field  
RES  
Bits  
Type  
Description  
Reserved, always reads as 0  
TSD2 minimum Waiting Time Selection  
15:13  
12  
r
TSD2_DEL  
rw  
0B 1s, Minimum waiting time until TSD2 is released  
again is always 1 s  
1B 64s, Minimum waiting time until TSD2 is released  
again is 1 s, after >16 TSD2 consecutive events, it  
will extended x 64  
VS_OV_SEL  
SH_DISABLE  
RSTN_DEL  
RES  
11  
10  
9
rw  
rw  
rw  
VS OV comparator threshold change  
0B 20V, Default threshold setting (VS,OVD1  
1B 30V, increased threshold setting (VS,OVD2  
)
)
Sample and hold circuitry disable  
0B ENABLED, Gate driver S&H circuitry enabled  
1B DISABLED, Gate driver S&H circuitry disabled  
Reset delay time  
0B 10ms, Reset delay time 10 ms (tRD1  
1B 2ms, Reset delay time to 2 ms (tRD2  
Reserved, always reads as 0  
Soft Reset Configuration  
)
)
8:7  
6
r
SOFT_RESET_RO  
rw  
0B RSTN, RSTN will be triggered (pulled low) during  
a Soft Reset  
1B NO_RSTN, no RSTN trigger during a Soft Reset  
RES  
5
r
Reserved, always reads as 0  
Reserved, always reads as 0  
RES  
4:3  
2
r
WD_STM_EN_1  
rwh  
Watchdog Deactivation during Stop Mode, bit1  
0B ACTIVE, Watchdog is active in Stop Mode  
1B INACTIVE, Watchdog is deactivated in Stop Mode  
RES  
1:0  
r
Reserved, always reads as 0  
Table 44 Reset of HW_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR  
0000 0000 0000 0000B  
Soft reset  
Restart  
0000 00x0 0000 0000B  
000x 00x0 0x00 0000B  
Datasheet  
157  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Notes  
1. WD_STM_EN_1 will also be cleared when changing from Stop Mode to Normal Mode .  
Datasheet  
158  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Watchdog Control  
WD_CTRL  
Watchdog Control  
(000 0011B)  
Reset Value: see Table 45  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
WD_S  
TM_E  
N_0  
WD_E  
N_WK RES  
_BUS  
CHEC  
KSUM  
WD_C  
FG  
RES  
WD_TIMER  
rw  
r
rwh  
rw  
rwh  
r
rwh  
Field  
Bits  
Type  
Description  
Watchdog Setting Check Sum Bit  
CHECKSUM  
15  
rw  
0B 0, Counts as 0 for checksum calculation  
1B 1, Counts as 1 for checksum calculation  
RES  
14:7  
6
r
Reserved, always reads as 0  
WD_STM_EN_0  
rwh  
Watchdog Deactivation during Stop Mode, bit0  
0B ACTIVE, Watchdog is active in Stop Mode  
1B INACTIVE, Watchdog is deactivated in Stop Mode  
WD_CFG  
5
4
rw  
Watchdog Configuration  
0B TIMEOUT, Watchdog works as a Time-Out  
watchdog  
1B WINDOW, Watchdog works as a Window  
watchdog  
WD_EN_ WK_BUS  
rwh  
Watchdog Enable after Bus Wake in Stop Mode  
0B DISABLED, Watchdog will not start after a or LIN  
wake-up event  
1B ENABLED, Watchdog starts with a long open  
window after or LIN Wake-up event  
RES  
3
r
Reserved, always reads as 0  
WD_TIMER  
2:0  
rwh  
Watchdog Timer Period  
000B 10ms, 10ms  
001B 20ms, 20ms  
010B 50ms, 50ms  
011B 100ms, 100ms  
100B 200ms, 200ms  
101B 500ms, 500ms  
110B 1s, 1s  
111B 10s, 10s  
Table 45 Reset of WD_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0001 0100B  
0000 0000 000x 0100B  
Datasheet  
159  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Notes  
1. See also Chapter 12.2.4 for more information on disabling the watchdog in Stop Mode.  
2. See chapter Chapter 12.2.5 for more information on the effect of the bit WD_EN_WK_BUS.  
3. See chapter Chapter 12.2.3 for calculation of checksum.  
Datasheet  
160  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
and LIN Control  
BUS_CTRL  
and LIN Control  
(000 0100B)  
Reset Value: see Table 46  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
LIN_T  
XD_T  
O
LIN_F LIN_L  
LASH SM  
RES  
LIN  
RES  
r
rw  
rw  
rw  
rwh  
r
Field  
RES  
Bits  
Type  
Description  
15:8  
7
r
Reserved, always reads as 0  
LIN_FLASH  
rw  
LIN Flash  
0B ACTIVE, Slope control mechanism active  
1B INACTIVE, Deactivation of slope control for  
baudrates up to 115 kBaud  
LIN_LSM  
6
rw  
LIN LSM  
0B NORMAL, LIN Normal Mode is activated  
1B LOW_SLOPE, LIN Low-Slope Mode (10.4 kBaud)  
activated  
LIN_TXD_TO  
LIN  
5
rw  
LIN TXD TO  
0B DISABLED, TXD Time-out feature disabled  
1B ENABLED, TXD Time-out feature enabled  
4:3  
rwh  
LIN Module Modes  
00B OFF, LIN OFF  
01B WAKE, LIN wake capable  
10B RECEIVE, LIN Receive Only Mode  
11B NORMAL, LIN Normal Mode  
RES  
2:0  
r
Reserved, always reads as 0  
Table 46 Reset of BUS_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 0000 xx0y 0000B  
Notes  
1. The reset values for LIN transceivers are marked with ‘y’ because they will vary depending on the cause of  
change.  
2. See , Figure 25 for detailed state changes of LIN transceivers for different device modes.  
3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure, then BUS_CTRL is  
modified by the device to 0000 0000 xxx0 1001B to ensure that the device can be woken again. See also the  
description in Chapter 8.1 and Chapter 9.2.1 for WK_CTRL for other wake sources when entering Fail-Safe  
Mode.  
4. When in Software Development Mode the POR/Soft Reset value are: LIN=11B.  
Datasheet  
161  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Wake-up Control  
WK_CTRL  
Wake-up Control  
(000 0101B)  
Reset Value: see Table 47  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES RES  
WK_FILT  
WK_PUPD  
RES  
WK_EN  
rw  
RES  
WK_BNK  
r
r
rw  
rw  
r
r
rw  
Field  
RES  
Bits  
Type  
Description  
15  
r
Reserved, always reads as 0  
Reserved, always reads as 0  
RES  
14  
r
WK_FILT  
13:11  
rw  
Wake-up Filter Time Configuration  
000B 16us, Filter with 16 µs filter time (static sensing)  
001B 64us, Filter with 64 µs filter time (static sensing)  
010B TIMER1, Filtering at the end of the on-time; filter  
time of 16 µs (cyclic sensing) is selected, Timer1  
011B TIMER2, Filtering at the end of the on-time; filter  
time of 16 µs (cyclic sensing) is selected, Timer2  
100B SYNC, Filter at the end of settle time (80 µs), filter  
time of 16 µs (cyclic sensing) is selected, SYNC1)2)  
101B , reserved  
110B , reserved  
111B , reserved  
WK_PUPD  
10:9  
rw  
WKx Pull-Up/Pull-Down Configuration  
00B NO, No pull-up/pull-down selected  
01B PULL_DOWN, Pull-down resistor selected  
10B PULL_UP, Pull-up resistor selected  
11B AUTO, Automatic switching to pull-up or pull-  
down  
RES  
8:7  
6:5  
r
Reserved, always reads as 0  
WK_EN  
rw  
WKx Enable  
00B WK_OFF, WKx module OFF  
01B WK_ON, WKx module ON  
10B SYNC, OFF or (in case of WK4), it is configured as  
SYNC input  
11B OFF, OFF  
RES  
4:3  
2:0  
r
Reserved, always reads as 0  
WK_BNK  
rw  
WKs input Banking  
011B WK4, WK4 Module (Bank 4)  
101B , reserved  
110B , reserved  
111B , reserved  
1) This setting is available only in case of WK4 configured as WK_EN=10B.  
2) The min TON time for cyclic sense with SYNC is 100 µs.  
Datasheet  
162  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 47 Reset of WK_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0010 0000B  
00xx xxx0 0xx0 0000B  
Notes  
1. The SYNC functionality is accessable only if the Bank 4 is selected.  
2. When selecting a filter time configuration, the user must make sure to also assign the respective timer/SYNC  
to at least one HS switch during cyclic sense operation.  
3. At Fail-Safe Mode entry WK_EN will be automatically changed (by the device) in “01”. WK4 if configured as  
SYNC previously  
4. During Fail-Safe Mode the WK_FILT bits are ignored and static-sense with 16 µs filter time is used by default.  
Datasheet  
163  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Timer 1 and Timer2 Control and Selection  
TIMER_CTRL  
Timer 1 and Timer2 Control and Selection  
(000 0110B)  
Reset Value: see Table 48  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
TIMER2_ON  
RES  
TIMER2_PER  
CYCWK  
rwh  
TIMER1_ON  
RES  
TIMER1_PER  
rwh  
r
rwh  
rwh  
r
rwh  
Field  
Bits  
Type  
Description  
Timer2 On-Time Configuration  
TIMER2_ON  
15:13  
rwh  
000B OFF_LOW, OFF / Low (timer not running, HSx  
output is low)  
001B 100us, 0.1ms on-time  
010B 300us, 0.3ms on-time  
011B 1ms, 1.0ms on-time  
100B 10ms, 10ms on-time  
101B 20ms, 20ms on-time  
110B OFF_HIGH, OFF / HIGH (timer not running, HSx  
output is high)  
111B , reserved, same behaviour as 110B  
RES  
12  
r
Reserved, always reads as 0  
TIMER2_PER  
11:9  
rwh  
Timer2 Period Configuration  
000B 10ms, 10ms  
001B 20ms, 20ms  
010B 50ms, 50ms  
011B 100ms, 100ms  
100B 200ms, 200ms  
101B 500ms, 500ms  
110B 1s, 1s  
111B 2s, 2s  
CYCWK  
8:7  
rwh  
Cyclic Wake Configuration  
00B DISABLED, Timer1 and Timer2 disabled as wake-  
up sources  
01B TIMER1, Timer1 is enabled as wake-up source  
(Cyclic Wake)  
10B TIMER2, Timer2 is enabled as wake-up source  
(Cyclic Wake)  
11B , reserved  
Datasheet  
164  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
Bits  
Type  
Description  
TIMER1_ON  
6:4  
rwh  
Timer1 On-Time Configuration  
000B OFF_LOW, OFF / Low (timer not running, HSx  
output is low)  
001B 100us, 0.1ms on-time  
010B 300us, 0.3ms on-time  
011B 1ms, 1.0ms on-time  
100B 10ms, 10ms on-time  
101B 20ms, 20ms on-time  
110B OFF_HIGH, OFF / HIGH (timer not running, HSx  
output is high)  
111B , reserved, same behaviour as 110B  
RES  
3
r
Reserved, always reads as 0  
TIMER1_PER  
2:0  
rwh  
Timer1 Period Configuration  
000B 10ms, 10ms  
001B 20ms, 20ms  
010B 50ms, 50ms  
011B 100ms, 100ms  
100B 200ms, 200ms  
101B 500ms, 500ms  
110B 1s, 1s  
111B 2s, 2s  
Table 48 Reset of TIMER_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 0000 0000 0000B  
Notes  
1. The timer must be first assigned and is then automatically activated as soon as the on-time is configured.  
2. If cyclic sense is selected and the HSx switch is cleared during Restart Mode then also the timer settings  
(period and on-time) are cleared to avoid incorrect switch detection. However, the timer settings are not  
cleared in case of failure not leading to Restart Mode.  
3. In case the timer is set as wake sources and cyclic sense is running, then both cyclic sense and cyclic wake will  
be active at the same time.  
4. Timer accuracy is linked to the oscillator accuracy (see Parameter P_13.12.43).  
Datasheet  
165  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
High-Side Switch Shutdown Control  
SW_SD_CTRL  
High-Side Switch Shutdown Control  
(000 0111B)  
Reset Value: see Table 49  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
HS3_ HS2_ HS1_  
OV_S OV_S OV_S  
DN_DI DN_DI DN_DI  
HS3_ HS2_ HS1_ HS_O  
RES OV_RE OV_RE OV_RE T_SD_ RES  
HS_O HS_U  
V_SDS V_SD_ RES  
_DIS DIS  
HS_U  
V_REC  
RES  
C
C
C
DIS  
S
S
rw  
S
rw  
r
rw  
rw  
rw  
rw  
r
rw  
rw  
rw  
r
rw  
r
Field  
RES  
Bits  
Type  
Description  
Reserved, always reads as 0  
15  
14  
r
HS3_OV_REC  
HS2_OV_REC  
HS1_OV_REC  
rw  
Switch recovery after removal of VS Overvoltage for  
HS3  
0B DISABLED, Switch recovery is disabled  
1B PREVIOUS, Previous state before VS Overvoltage  
is enabled after Overvoltage considtion is  
removed  
13  
12  
11  
rw  
rw  
rw  
Switch recovery after removal of VS Overvoltage for  
HS2  
0B DISABLED, Switch recovery is disabled  
1B PREVIOUS, Previous state before VS Overvoltage  
is enabled after Overvoltage considtion is  
removed  
Switch recovery after removal of VS Overvoltage for  
HS1  
0B DISABLED, Switch recovery is disabled  
1B PREVIOUS, Previous state before VS Overvoltage  
is enabled after Overvoltage considtion is  
removed  
HS_OT_SD_DIS  
Shutdown Disabling of all HS in case of  
Overtemperature event  
0B ALL, shudown for all HSx in case of  
Overtemperature  
1B INDIVIDUAL, individual shudown in case of  
Overtemperature  
RES  
10  
9
r
Reserved, always reads as 0  
HS3_OV_SDN_DIS  
rw  
Shutdown Disabling of HS3 in case of input supply  
overvoltage in Normal Mode  
0B ENABLED, shudown enabled in case of VS  
Overvoltage  
1B DISABLED, shudown disabled in case of VS  
Overvoltage  
Datasheet  
166  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
Bits  
Type  
Description  
HS2_OV_SDN_DIS  
8
rw  
Shutdown Disabling of HS2 in case of input supply  
overvoltage in Normal Mode  
0B ENABLED, shudown enabled in case of VS  
Overvoltage  
1B DIASBLED, shudown disabled in case of VS  
Overvoltage  
HS1_OV_SDN_DIS  
HS_OV_SDS_DIS  
HS_UV_SD_DIS  
7
6
5
rw  
rw  
rw  
Shutdown Disabling of HS1 in case of input supply  
overvoltage in Normal Mode  
0B ENABLED, shudown enabled in case of VS  
Overvoltage  
1B DISABLED, shudown disabled in case of VS  
Overvoltage  
Shutdown Disabling of HSx in case of input supply  
overvoltage in Stop Mode or Sleep Mode  
0B ENABLED, shudown enabled in case of VS  
Overvoltage  
1B DISABLED, shudown disabled in case of VS  
Overvoltage  
Shutdown Disabling of HSx in case of input supply  
undervoltage  
0B ENABLED, shudown enabled in case of VS  
Undervoltage  
1B DISABLED, shudown disabled in case of VS  
Undervoltage  
RES  
4
3
r
Reserved, always reads as 0  
HS_UV_REC  
rw  
Switch recovery after removal of Undervoltage for  
HSx  
0B DISABLED, Switch recovery is disabled  
1B PREVIOUS, Previous state before VS  
Undervoltage is enabled after Undervoltage  
considtion is removed  
RES  
2:0  
r
Reserved, always reads as 0  
Table 49 Reset of SW_SD_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0xxx x0xx xxx0 x000B  
Datasheet  
167  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
High-Side Switch Control  
HS_CTRL  
High-Side Switch Control  
(000 1000B)  
Reset Value: see Table 50  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
HS3  
HS2  
HS1  
r
rwh  
rwh  
rwh  
Field  
RES  
HS3  
Bits  
Type  
Description  
15:12  
11:8  
r
Reserved, always reads as 0  
rwh  
HS3 Configuration  
0000BOFF, OFF  
0001BON, ON  
0010BTIMER1, Controlled by Timer1  
0011BTIMER2, Controlled by Timer2  
0100BPWM1, Controlled by PWM1  
0101BPWM2, Controlled by PWM2  
0110BPWM3, Controlled by PWM3  
0111BPWM4, Controlled by PWM4  
1000BWK4_SYNC, Synchronized with WK4/SYNC  
1001B, reserved  
1010B, reserved  
1011B, reserved  
1100B, reserved  
1101B, reserved  
1110B, reserved  
1111B, reserved  
HS2  
7:4  
rwh  
HS2 Configuration  
0000BOFF, OFF  
0001BON, ON  
0010BTIMER1, Controlled by Timer1  
0011BTIMER2, Controlled byTimer2  
0100BPWM1, Controlled by PWM1  
0101BPWM2, Controlled by PWM2  
0110BPWM3, Controlled by PWM3  
0111BPWM4, Controlled by PWM4  
1000BWK4_SYNC, Synchronized with WK4/SYNC  
1001B, reserved  
1010B, reserved  
1011B, reserved  
1100B, reserved  
1101B, reserved  
1110B, reserved  
1111B, reserved  
Datasheet  
168  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
HS1  
Bits  
Type  
Description  
3:0  
rwh  
HS1 Configuration  
0000BOFF, OFF  
0001BON, ON  
0010BTIMER1, Controlled by Timer1  
0011BTIMER2, Controlled by Timer2  
0100BPWM1, Controlled by PWM1  
0101BPWM2, Controlled by PWM2  
0110BPWM3, Controlled by PWM3  
0111BPWM4, Controlled by PWM4  
1000BWK4_SYNC, Synchronized with WK4/SYNC  
1001B, reserved  
1010B, reserved  
1011B, reserved  
1100B, reserved  
1101B, reserved  
1110B, reserved  
1111B, reserved  
Table 50 Reset of HS_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 0000 0000 0000B  
PWMx in this register designates the internal PWM generators for the integrated high-side switches.  
Datasheet  
169  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Interrupt Mask Control1)  
INT_MASK  
Interrupt Mask Control  
(000 1001B)  
Reset Value: see Table 51  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
INTN_ WD_S  
CYC_E DM_DI  
SPI_C  
RC_FA  
IL  
SUPP  
LY_ST  
AT  
WD_S  
DM  
BD_ST HS_ST BUS_S TEMP  
RES  
AT  
AT  
TAT _STAT  
N
SABLE  
r
rw  
rw  
rw  
rw  
rw  
rw  
rw rw  
rw  
Field  
RES  
Bits  
Type  
Description  
15:9  
8
r
Reserved, always reads as 0  
INTN_CYC_EN  
rw  
Periodical INTN generation  
0B DISABLED, no periodical INTN event generated in  
case of pending interrupts  
1B ENABLED, periodical INTN event generated in  
case of pending interrupts  
WD_SDM_DISABLE  
WD_SDM  
7
6
5
4
3
rw  
rw  
rw  
rw  
rw  
Disable Watchdog in Software Development Mode  
0B ENABLED, WD is enabled in Software  
Development Mode  
1B DISABLED, WD is disabled in Software  
Development Mode  
Watchdog failure in Software Development Mode  
0B DISABLED, no INTN event generated in case of  
WD trigger failure in Software Development Mode  
1B ENABLED, one INTN event is generated in case of  
WD trigger failure in Software Development Mode  
SPI_CRC_FAIL  
BD_STAT  
SPI and CRC interrupt generation  
0B DISABLED, no INTN event generated in case of  
SPI_FAIL or CRC_FAIL  
1B ENABLED, one INTN event is generated n case of  
SPI_FAIL or CRC_FAIL  
Bridge Driver Interrupt generation  
0B DISABLED, no INTN event generated in case  
BD_STAT (on Status Information Field) is set  
1B ENABLED, one INTN event generated in case  
BD_STAT (on Status Information Field) is set  
HS_STAT  
High Side Interrupt generation  
0B DISABLED, no INTN event generated in case  
HS_STAT (on Status Information Field) is set  
1B ENABLED, one INTN event generated in case  
HS_STAT (on Status Information Field) is set  
1) Every event will generate a signal on the INTN pin (when masked accordingly).  
Even if the status-bit was already set in the corresponding status-register it can still trigger a signal on the INTN pin.  
Datasheet  
170  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
Bits  
Type  
Description  
BUS_STAT  
2
rw  
BUS Interrupt generation  
0B DISABLED, no INTN event generated in case  
BUS_STAT (on Status Information Field) is set  
1B ENABLED, one INTN event generated in case  
BUS_STAT (on Status Information Field) is set  
TEMP_STAT  
1
0
rw  
rw  
Temperature Interrupt generation  
0B DISABLED, no INTN event generated in case  
TEMP_STAT (on Status Information Field) is set  
1B ENABLED, one INTN event generated in case  
TEMP_STAT (on Status Information Field) is set  
SUPPLY_STAT  
SUPPLY Status Interrupt generation  
0B DISABLED, no INTN event generated in case  
SUPPLY_STAT (on Status Information Field) is set  
1B ENABLED, one INTN event generated in case  
SUPPLY_STAT (on Status Information Field) is set  
Table 51 Reset of INT_MASK  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0001 0100 0000B  
0000 000x xxxx xxxxB  
Datasheet  
171  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
PWM Configuration Control  
PWM_CTRL  
PWM Configuration Control  
(000 1010B)  
Reset Value: see Table 52  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
PWM_  
FREQ  
RES  
PWM_DC  
RES  
PWM_BNK  
r
rw  
rw  
r
rw  
Field  
RES  
Bits  
Type  
r
Description  
Reserved, always reads as 0  
15  
14  
PWM_FREQ  
rw  
PWM generator Frequency Setting  
0B 100Hz, 100Hz is selected  
1B 200Hz, 200Hz is selected  
PWM_DC  
13:4  
rw  
PWM Duty Cycle Setting (bit4 = LSB; bit13 = MSB)  
00 0000 0000B, 100% OFF, i.e. HS = OFF  
xx xxxx xxxxB, ON with duty cycle fraction of 1024  
11 1111 1111B, 100% ON, i.e. HS = ON  
RES  
3
r
Reserved, always reads as 0  
PWM_BNK  
2:0  
rw  
Internal PWM generator selection  
000B PWM1, PWM1 Module  
001B PWM2, PWM2 Module  
010B PWM3, PWM3 Module  
011B PWM4, PWM4 Module  
1xxB , Don’t care  
Table 52 Reset of PWM_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0xxx xxxx xxxx 0000B  
PWMx in this register designates the internal PWM generators for the integrated high-side switches.  
Notes  
1. 0% and 100% duty cycle settings are used to have the switch turned ON or OFF respectively.  
2. The desired duty cycle should be set first before the HSx is enabled as PWM.  
3. The PWM signal is correct only after at least one PWM pulse.  
4. PWM generator accuracy is linked to the oscillator accuracy (see parameter P_13.12.43).  
Datasheet  
172  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
System Status Control  
SYS_STAT_CTRL  
System Status Control  
(000 1011B)  
Reset Value: see Table 53  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
SYS_STAT  
rw  
Field  
Bits  
15:0  
Type  
rw  
Description  
System Status Control (bit0=LSB; bit15=MSB)  
SYS_STAT  
Dedicated bytes for system configuration, access only  
by microcontroller. Cleared after power up and soft  
reset.  
Table 53 Reset of SYS_STAT_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR / Soft reset  
Restart  
0000 0000 0000 0000B  
xxxx xxxx xxxx xxxxB  
Note:  
This register is intended for storing system configuration of the ECU by the microcontroller and is  
only accessible in Normal Mode. The register is not accessible by the TLE9564QX and is also not  
cleared after Fail-Safe or Restart Mode. It allows the microcontroller to quickly store system  
configuration without loosing data.  
Datasheet  
173  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.5.2  
Control registers bridge driver  
General Bridge Control  
GENCTRL  
General Bridge Control  
(001 0000B)  
Reset Value: see Table 54  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
EN_GE  
N_CH IHOLD  
ECK  
BDFR  
EQ  
CPUV FET_L CPST BDOV IPCHG  
POCH AGCFI  
FMOD  
E
RES RES  
AGC  
CPEN  
TH  
VL  
GA _REC ADT  
rw rw rw  
GDIS  
LT  
rw  
r
r
rw  
rw  
rw  
rw  
rw  
rw  
rw  
rw  
rw  
Field  
Bits  
Type  
Description  
BDFREQ  
15  
rw  
Bridge driver synchronization frequency  
0B 18MHz, typ. 18.75 MHz (default)  
1B 37MHz, typ. 37.5 MHz  
RES  
14  
13  
12  
r
Reserved, always reads as 0  
Reserved, always reads as 0  
RES  
r
CPUVTH  
rw  
Charge pump under voltage (referred to VS)  
0B TH1, (default) CPUV threshold 1 for FET_LVL = 0,  
CPUV threshold 1 for FET_LVL = 1  
1B TH2, CPUV threshold 2 for FET_LVL = 0, CPUV  
threshold 2 for FET_LVL = 1  
FET_LVL  
CPSTGA  
11  
10  
rw  
rw  
External MOSFET normal / logic level selection  
0B LOGIC, Logic level MOSFET selected  
1B NORMAL, Normal level MOSFET selected(default)  
Automatic switchover between dual and single  
charge pump stage  
0B INACTIVE, Automatic switch over deactivated  
(default)  
1B ACTIVE, Automatic switch over activated  
BDOV_REC  
IPCHGADT  
9
8
rw  
rw  
Bridge driver recover from VS and VSINT  
Overvoltage  
0B INACTIVE, Recover deactivated (default)  
1B ACTIVE, Recover activated  
Adaptation of the pre-charge and pre-discharge  
current  
0B 1STEP, 1 current step (default)  
1B 2STEPS, 2 current steps  
Datasheet  
174  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
AGC  
Bits  
Type  
Description  
7:6  
rw  
Adaptive gate control  
00B INACTIVE1, (default) Adaptive gate control  
disabled, pre-charge and pre-discharge disabled  
01B INACTIVE2, Adaptive gate control disabled,  
precharge is enabled with IPRECHG = IPCHGINIT,  
predischarge is enabled with IPREDCHG =  
IPDCHGINIT  
10B ACTIVE, Adaptive gate control enabled, IPRECHG  
and IPREDCHG are self adapted  
11B , reserved. Adaptive gate control enabled,  
IPRECHG and IPREDCHG are self adapted  
CPEN  
5
4
rw  
rw  
CPEN  
0B DISABLED, Charge pump disabled (default)  
1B ENABLED, Charge pump enabled  
POCHGDIS  
Postcharge disable bit  
0B ENABLED, The postcharge phase is enabled  
during PWM (default)  
1B DISABLED, The postcharge phase is disabled  
during PWM  
AGCFILT  
3
2
1
0
rw  
rw  
rw  
rw  
Filter for adaptive gate control  
0B NO_FILT, No filter applied (default)  
1B FILT_APPL, Filter applied  
EN_GEN_CHECK  
IHOLD  
Detection of active / FW MOSFET  
0B DISABLED, Detection disabled (default)  
1B ENABLED, Detection enabled  
Gate driver hold current IHOLD  
0B TH1, (default) Charge: ICHG15, discharge IDCHG15  
1B TH2, Charge: ICHG20, discharge: IDCHG20  
.
FMODE  
Frequency modulation of the charge pump  
0B NO, No modulation  
1B 15KHz, Modulation frequency 15.6 kHz (default)  
Table 54 Reset of GENCTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 1000 0000 0001B  
x00x xxxx xxxx xxxxB  
Datasheet  
175  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Current sense amplifier  
CSA  
Current sense amplifier  
(001 0001B)  
Reset Value: see Table 55  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
PWM_ CSO_  
CSA_O  
FF  
RES  
CSD  
OCFILT  
OCTH  
CSAG  
OCEN  
NB  
CAP  
r
rw  
rw  
rw  
rw  
rw  
rw  
rw  
rw  
Field  
RES  
Bits  
Type  
Description  
15:11  
10  
r
Reserved, always reads as 0  
PWM_NB  
rw  
Selection of 3 or 6 PWM inputs  
0B 3PWM, 3 PWM inputs (default)  
1B 6PWM, 6 PWM inputs  
CSO_CAP  
9
rw  
Capacitance connected to the current sense  
amplifier output (CCSO), see also Chapter 12.11.4  
0B 400pF, CCSO < 400 pF (default)  
1B 2nF, 400 pF < CCSO < 2.2 nF  
CSD  
8
rw  
rw  
Direction of the current sense amplifier  
0B UNI, Unidirectional  
1B BI, Bidirectional (default)  
OCFILT  
7:6  
Overcurrent filter time of CSO  
00B 6us, 6 µs (default)  
01B 10us, 10 µs  
10B 50us, 50 µs  
11B 100us, 100 µs  
CSA_OFF  
OCTH  
5
rw  
rw  
CSA OFF  
0B CSA_ON, CSA enabled  
1B CSA_OFF, CSA disabled (default)  
4:3  
Overcurrent detection threshold of CSO  
00B TH1, VCSO > VCC1/2+2 x VCC1/20 or VCSOx< VCC1/2- 2x  
V
CC1/20 (default)  
01B TH2, VCSO > VCC1/2+ 4x VCC1/20 or VCSOx< VCC1/2- 4x  
CC1/20  
V
10B TH3, VCSO > VCC1/2+ 5 x VCC1/20 or VCSOx< VCC1/2- 5  
xVCC1/20  
11B TH4, VCSO > VCC1/2+ 6x VCC1/20 or VCSOx< VCC1/2- 6x  
V
CC1/20  
CSAG  
2:1  
0
rw  
rw  
Gain of the current sense amplifier  
00B 10VV, GDIFF10 (default)  
01B 20VV, GDIFF20  
10B 40VV, GDIFF40  
11B 60VV, GDIFF60  
OCEN  
Overcurrent shutdown Enable  
0B DISABLED, Disabled  
1B ENABLED, Enabled (default)  
Datasheet  
176  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 55 Reset of CSA  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0001 0010 0001B  
0000 0xxx xxxx xxx1B  
Datasheet  
177  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Drain-Source monitoring threshold LS1-3  
LS_VDS  
VDS monitoring threshold LS1-3  
(001 0010B)  
Reset Value: see Table 56  
15  
14  
13  
TFVDS  
rw  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
RES  
LS3VDSTH  
LS2VDSTH  
LS1VDSTH  
r
r
rw  
rw  
rw  
Field  
RES  
Bits  
Type  
Description  
Reserved. Always read as 0  
15:14  
13:12  
r
TFVDS  
rw  
Filter time of drain-source voltage monitoring  
00B 500ns, 0.5 µs (default)  
01B 1us, 1 µs  
10B 2us, 2 µs  
11B 6us, 6 µs  
RES  
11:9  
8:6  
r
Reserved, always reads as 0  
LS3VDSTH  
LS2VDSTH  
LS1VDSTH  
rw  
LS3 drain-source overvoltage threshold  
000B 160mV, 0.16 V  
001B 200mV, 0.20 V (default)  
010B 300mV, 0.30 V  
011B 400mV, 0.40 V  
100B 500mV, 0.50 V  
101B 600mV, 0.60 V  
110B 800mV, 0.80 V  
111B 2V, 2.0 V  
5:3  
rw  
LS2 drain-source overvoltage threshold  
000B 160mV, 0.16V  
001B 200mV, 0.20 V (default)  
010B 300mV, 0.30 V  
011B 400mV, 0.40 V  
100B 500mV, 0.50 V  
101B 600mV, 0.60 V  
110B 800mV, 0.80 V  
111B 2V, 2.0 V  
2:0  
rw  
LS1 drain-source overvoltage threshold  
000B 160mV, 0.16 V  
001B 200mV, 0.20 V (default)  
010B 300mV, 0.30 V  
011B 400mV, 0.40 V  
100B 500mV, 0.50 V  
101B 600mV, 0.60 V  
110B 800mV, 0.80 V  
111B 2V, 2.0 V  
Datasheet  
178  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 56 Reset of LS_VDS  
Register Reset Type Reset Values  
Reset Short Name  
Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0100 1001B 0000 0000 0000 0000  
0000 000x xxxx xxxxB  
Datasheet  
179  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Drain-Source monitoring Threshold HS1-3  
HS_VDS  
VDS monitoring threshold HS1-3  
(001 0011B)  
Reset Value: see Table 57  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
DEEP_  
ADAP  
RES  
RES  
RES  
HS3VDSTH  
HS2VDSTH  
HS1VDSTH  
r
rw  
rw  
r
rw  
rw  
rw  
Field  
RES  
RES  
Bits  
Type  
Description  
Reserved. Always read as 0  
15:14  
13  
r
rw  
rw  
Reserved. This bit must be programmed to ‘0‘  
DEEP_ADAP  
12  
Deep adaptation enable  
0B NO_DEEP_ADAP, Deep adaptation disabled  
(default)  
1B DEEP_ADAP, Deep adaptation enabled  
RES  
11:9  
8:6  
r
Reserved, always reads as 0  
HS3VDSTH  
rw  
HS3 drain-source overvoltage threshold  
000B 160mV, 0.16 V  
001B 200mV, 0.20 V (default)  
010B 300mV, 0.30 V  
011B 400mV, 0.40 V  
100B 500mV, 0.50 V  
101B 600mV, 0.60 V  
110B 800mV, 0.80 V  
111B 2V, 2.0 V  
HS2VDSTH  
5:3  
rw  
HS2 drain-source overvoltage threshold  
000B 160mV, 0.16 V  
001B 200mV, 0.20 V (default)  
010B 300mV, 0.30 V  
011B 400mV, 0.40 V  
100B 500mV, 0.50 V  
101B 600mV, 0.60 V  
110B 800mV, 0.80 V  
111B 2V, 2.0 V  
HS1VDSTH  
2:0  
rw  
HS1 drain-source overvoltage threshold  
000B 160mV, 0.16 V  
001B 200mV, 0.20 V (default)  
010B 300mV, 0.30 V  
011B 400mV, 0.40 V  
100B 500mV, 0.50 V  
101B 600mV, 0.60 V  
110B 800mV, 0.80 V  
111B 2V, 2.0 V  
Datasheet  
180  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 57 Reset of HS_VDS  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0100 1001B  
00xx 000x xxxx xxxxB  
Datasheet  
181  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
CCP and times selection  
CCP_BLK  
CCP and times selection  
(001 0100B)  
Reset Value: see Table 58  
15  
14  
TBLANK  
rw  
13  
12  
11  
10  
TCCP  
rw  
9
8
7
6
5
4
3
2
1
0
RES  
CCP_BNK  
r
rw  
Field  
Bits  
Type  
Description  
Blank time  
TBLANK  
15:12  
rw  
nom. tHBxBLANK = 587 ns + 266 x T[3:0]D  
The CCP_BNK bits select the blank time for the FW or  
active MOSFET and the half-bridge HBx  
Reset of active and FW tHBxBLANK: 2450 ns typ.  
TCCP  
11:8  
rw  
Cross-current protection time  
nom. tHBxCCP = 587 ns + 266 x TCCP[3:0]D  
The CCP_BNK bits select the cross-current protection  
time for the FW or active MOSFET and the half-bridge  
HBx  
Reset of all active and FW tHBxCCP: 2450 ns typ.  
RES  
7:3  
2:0  
r
Reserved, always reads as 0  
CCP_BNK  
rw  
Cross-current and time banking  
000B ACT_HB1, Active blank and cross-current prot.  
times for HB1 (default)  
001B ACT_HB2, Active blank and cross-current prot.  
times for HB2  
010B ACT_HB3, Active blank and cross-current prot.  
times for HB3  
011B RES, reserved  
100B FW_HB1, FW blank and cross-current prot. times  
for HB1  
101B FW_HB2, FW blank and cross-current prot. times  
for HB2  
110B FW_HB3, FW blank and cross-current prot. for  
times for HB3  
111B RES, reserved  
Table 58 Reset of CCP_BLK  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0111 0111 0000 0000B  
xxxx xxxx 0000 0000B  
Datasheet  
182  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Half-Bridge MODE  
HBMODE  
Half-Bridge MODE  
(001 0101B)  
Reset Value: see Table 59  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
HB3_  
HB2_  
HB1_  
RES  
HB3MODE AFW3 PWM_ HB2MODE AFW2 PWM_ HB1MODE AFW1 PWM_  
EN  
EN  
EN  
r
rw  
rw  
rw  
rw  
rw  
rw  
rw  
rw  
rw  
Field  
RES  
Bits  
Type  
Description  
15:12  
11:10  
r
Reserved, always reads as 0  
HB3MODE  
rw  
Half-bridge 3 MODE selection  
00B PASSIVE_OFF, LS3 and HS3 are off by passive  
discharge (default)  
01B LS3_ON, LS3 is ON  
10B HS3_ON, HS3 is ON  
11B ACTIVE_OFF, LS3 and HS3 kept off by the active  
discharge  
AFW3  
9
rw  
rw  
rw  
Active freewheeling for half-bridge 3 during PWM  
0B DISABLED, active freewheeling disabled  
1B ENABLED, active freewheeling enabled (default)  
HB3_PWM_EN  
HB2MODE  
8
PWM mode for half-bridge 3  
0B INACTIVE, PWM deactivated for HB2(default)  
1B ACTIVE, PWM activated for HB2  
7:6  
Half-bridge 2 MODE selection  
00B PASSIVE_OFF, LS2 and HS2 are off by passive  
discharge (default)  
01B LS2_ON, LS2 is ON  
10B HS2_ON, HS2 is ON  
11B ACTIVE_OFF, LS2 and HS2 kept off by the active  
discharge  
AFW2  
5
rw  
rw  
rw  
Active freewheeling for half-bridge 2 during PWM  
0B DISABLED, active freewheeling disabled  
1B ENABLED, active freewheeling enabled (default)  
HB2_PWM_EN  
HB1MODE  
4
PWM mode for half-bridge 2  
0B INACTIVE, PWM deactivated for HB2(default)  
1B ACTIVE, PWM activated for HB2  
3:2  
Half-bridge 1 MODE selection  
00B PASSIVE_OFF, LS1 and HS1 are off by passive  
discharge (default)  
01B LS1_ON, LS1 is ON  
10B HS1_ON, HS1 is ON  
11B ACTIVE_OFF, LS1 and HS1 kept off by the active  
discharge  
Datasheet  
183  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
Bits  
Type  
Description  
AFW1  
1
rw  
Active freewheeling for half-bridge 1 during PWM  
0B DISABLED, active freewheeling disabled  
1B ENABLED, active freewheeling enabled (default)  
HB1_PWM_EN  
0
rw  
PWM mode for half-bridge 1  
0B INACTIVE, PWM deactivated for HB1 (default)  
1B ACTIVE, PWM activated for HB1  
Table 59 Reset of HBMODE  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0010 0010 0010B  
0000 0010 0010 0010B  
Datasheet  
184  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
HB pre-charge and pre-discharge time  
TPRECHG  
HB pre-charge and pre-discharge time  
(001 0110B)  
Reset Value: see Table 60  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
TPCHG3  
TPCHG2  
TPCHG1  
RES  
TPCHG_BNK  
r
rw  
rw  
rw  
r
rw  
Field  
RES  
Bits  
Type  
Description  
Reserved, always reads as 0  
15:13  
12:10  
r
TPCHG3  
TPCHG2  
TPCHG1  
rw  
If TPCHG_BNK=0: precharge time of HB 3, If  
TPCHG_BNK=1: predischarge time of HB 3  
9:7  
6:4  
rw  
rw  
If TPCHG_BNK=0: precharge time of HB 2, If  
TPCHG_BNK=1: predischarge time of HB 2  
If TPCHG_BNK=0: precharge time of HB 1, If  
TPCHG_BNK=1: predischarge time of HB 1  
RES  
3
r
Reserved, always read as 0  
TPCHG_BNK  
2:0  
rw  
Precharge/predischarge time selection  
000B PRECHARGE, Precharge time selected (default)  
001B PREDISCHARGE, Predischarge time selected  
x1xB , wrong setting of TPCHG_BNK  
1xxB , wrong setting of TPCHG_BNK  
Table 60 Reset of TPRECHG  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
000x xxxx xxxx 0000B  
Datasheet  
185  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Static charge/discharge current  
ST_ICHG  
Static charge/discharge current  
(001 0111B)  
Reset Value: see Table 61  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
ICHGST3  
ICHGST2  
ICHGST1  
r
rw  
rw  
rw  
Field  
RES  
Bits  
Type  
Description  
Reserved, always read as 0  
15:12  
11:8  
r
ICHGST3  
ICHGST2  
ICHGST1  
rw  
Static charge and discharge currents of HB3  
Refer to Table 20  
Default: 0100B - charge: ICHG16,15.3 mA typ., discharge:  
DCHG16, 15.1 mA typ.  
I
7:4  
3:0  
rw  
rw  
Static charge and discharge currents of HB2  
Refer to  
Default: 0100B - charge: ICHG16,15.3 mA typ., discharge:  
IDCHG16, 15.1 mA typ.  
Static charge and discharge currents of HB1  
Refer to Table 20  
Default: 0100B - charge: ICHG16,15.3 mA typ., discharge:  
IDCHG16, 15.1 mA typ.  
Table 61 Reset of ST_ICHG  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0100 0100 0100B  
0000 xxxx xxxx xxxxB  
Datasheet  
186  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
HB charge/discharge currents for PWM operation  
HB_ICHG  
HB charge/discharge currents for PWM operation  
(001 1000B)  
Reset Value: see Table 62  
15  
14  
13  
IDCHG  
rw  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
ICHG  
RES  
ICHG_BNK  
rw  
r
rw  
Field  
Bits  
15:10  
Type  
Description  
IDCHG  
rw  
rw  
If ICHG_BNK =0xxB: Discharge current of HBx active  
MOSFET  
If ICHG_BNK=1xxB: Reserved. Always read as ‘0’  
Default value for all active MOSFETs discharge  
currents: 001111B, IDCHG15  
Refer to Table 28 for the configuration of the discharge  
current  
ICHG  
9:4  
If ICHG_BNK=0xxB: Charge current of HBx active  
MOSFET  
If ICHG_BNK=1xxB: Charge and discharge current of  
HBx FW MOSFETs  
Default value for all active MOSFETs charge currents  
and all FW MOSFETs charge/discharge currents:  
001101B, ICHG13  
Refer to Table 27 for the configuration of the charge  
current of the active and FW MOSFET  
Refer to Table 28 for the configuration of the discharge  
current of the FW MOSFET  
RES  
ICHG_BNK  
3
r
Reserved, always read as 0  
2:0  
rw  
Banking bits for charge and discharge currents of  
active MOSFETs  
000B ACT_HB1, Active MOSFET of HB1 is selected  
(default)  
001B ACT_HB2, Active MOSFET of HB2 is selected  
010B ACT_HB3, Active MOSFET of HB3 is selected  
011B RES, reserved  
100B FW_HB1, FW MOSFET of HB1 is selected  
101B FW_HB2, FW MOSFET of HB2 is selected  
110B FW_HB3, FW MOSFET of HB3 is selected  
111B RES, reserved  
Table 62 Reset of HB_ICHG  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
0011 1100 1101 0000B  
POR value valid for  
ICHG_BNK = 0  
Restart  
xxxx xxxx xxxx 0000B  
Datasheet  
187  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
HB max. pre-charge/pre-discharge in PWM operation current and diagnostic pull-down  
HB_ICHG_MAX  
HB max. pre-charge/pre-discharge in PWM operation current and diagnostic pull-down  
(001 1001B)  
Reset Value: see Table 63  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
HB3ID HB2ID HB1ID  
RES  
RES  
RES  
ICHGMAX3  
ICHGMAX2  
ICHGMAX1  
IAG  
IAG  
IAG  
r
rrw  
rw  
rw  
r
r
rw  
rw  
rw  
Field  
RES  
Bits  
Type  
Description  
Reserved, always read as 0  
15  
14  
r
HB3IDIAG  
rrw  
Control of HB3 off-state current source and current  
sink  
0B INACTIVE, Pull-down deactivated (default)  
1B ACTIVE, Pull-down activated  
HB2IDIAG  
HB1IDIAG  
13  
12  
rw  
rw  
Control of HB2 pull-down for off-state diagnostic  
0B INACTIVE, Pull-down deactivated (default)  
1B ACTIVE, Pull-down activated  
Control of HB1 pull-down for off-state diagnostic  
0B INACTIVE, Pull-down deactivated (default)  
1B ACTIVE, Pull-down activated  
RES  
11:8  
7:6  
r
Reserved, always read as 0  
Reserved, always reads as 0  
RES  
r
ICHGMAX3  
5:4  
rw  
Maximum drive current of HB3 during the pre-  
charge and pre-discharge phases1)  
00B 31mA, charge ICHG24: typ. 31.6 mA, discharge  
IDCHG24: typ. 30.9 mA (default)  
01B 52mA, charge ICHG32: typ. 52.5 mA, discharge  
IDCHG32: typ. 51.5 mA  
10B 112mA, charge ICHG52: typ. 112.2mA, discharge  
I
DCHG52: typ. 110.8 mA  
11B 150mA, charge ICHG63: typ. 150 mA, discharge  
DCHG63: typ. 150 mA  
I
ICHGMAX2  
3:2  
rw  
Maximum drive current of HB2 during the pre-  
charge phase and pre-discharge phases1)  
00B 31mA, charge ICHG24: typ. 31.6 mA, discharge  
IDCHG24: typ. 30.9 mA (default)  
01B 52mA, charge ICHG32: typ. 52.5 mA, discharge  
I
DCHG32: typ. 51.5 mA  
10B 112mA, charge ICHG52: typ. 112.2mA, discharge  
DCHG52: typ. 110.8 mA  
I
11B 150mA, charge ICHG63: typ. 150 mA, discharge  
IDCHG63: typ. 150 mA  
Datasheet  
188  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
Bits  
Type  
Description  
ICHGMAX1  
1:0  
rw  
Maximum drive current of HB1 during the pre-  
charge and pre-discharge phases1)  
00B 31mA, charge ICHG24: typ. 31.6 mA, discharge  
IDCHG24: typ. 30.9 mA (default)  
01B 52mA, charge ICHG32: typ. 52.5 mA, discharge  
I
DCHG32: typ. 51.5 mA  
10B 112mA, charge ICHG52: typ. 112.2mA, discharge  
DCHG52: typ. 110.8 mA  
I
11B 150mA, charge ICHG63: typ. 150 mA, discharge  
IDCHG63: typ. 150 mA  
1) ICHGMAX is also the current applied during the post-charge of the PWM MOSFET.  
Table 63 Reset of HB_ICHG_MAX  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0xxx 0000 00xx xxxxB  
Datasheet  
189  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
HBx pre-charge/pre-dischage initialization configuration in PWM operation  
HB_PCHG_INIT  
HBx pre-charge/pre-discharge initialization configuration in PWM operation  
(001 1010B)  
Reset Value: see Table 64  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
PDCHGINIT  
PCHGINIT  
RES  
INIT_BNK  
rw  
rw  
r
rw  
Field  
Bits  
Type  
Description  
PDCHGINIT  
15:10  
rw  
Initial predischarge current of HBx, IPDCHGINITx  
The INIT_BNK bits select the addressed half-bridge  
Default: 001111B  
Refer to Table 27  
PCHGINIT  
9:4  
rw  
Initial precharge current of HBx, IPCHGINITx  
The INIT_BNK bits select the addressed half-bridge  
Default: 001101B  
Refer to Table 27  
RES  
3
r
Reserved, always reads as 0  
INIT_BNK  
2:0  
rw  
Banking bits for Precharge an Predischarge Initial  
Current  
000B HB1, precharge/discharge init. for HB1 selected  
(default)  
001B HB2, precharge/discharge init. for HB2 selected  
010B HB3, precharge/discharge init. for HB3 selected  
010B RES, reserved  
011B RES, reserved  
1xxB , wrong setting of INIT_BANK  
Table 64 Reset of HB_PCHG_INIT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0011 1100 1101 0000B  
xxxx xxxx xxxx 0000B  
Datasheet  
190  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
HBx inputs TDON configuration  
TDON_HB_CTRL  
HBx inputs TDON configuration  
(001 1011B)  
Reset Value: see Table 65  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
TDON  
RES  
HB_TDON_BNK  
r
rw  
r
rw  
Field  
RES  
Bits  
Type  
Description  
Reserved, always read as 0  
15:14  
13:8  
r
TDON  
rw  
Turn-on delay time of active MOSFET of HBx  
The HB_TDON_BNK bits selects the turn-on delay time  
of the active MOSFET of the half-bridge HBx  
Nominal tDON = 53.3 ns x TDON[5:0]D  
Default: 00 1100B : 640 ns typ.  
RES  
7:3  
2:0  
r
Reserved, always read as 0  
HB_TDON_BNK  
rw  
Banking bits for turn-on delay time  
000B HB1, tDON of HB1 selected (default)  
001B HB2, tDON of HB2 selected  
010B HB3, tDON of HB3 selected  
011B RES, reserved  
1xxB , wrong setting of PWM_TDON_BNK  
Table 65 Reset of TDON_HB_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 1100 0000 0000B  
00xx xxxx 0000 0000B  
Datasheet  
191  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
HBx TDOFF configuration  
TDOFF_HB_CTRL  
HBx TDOFF configuration  
(001 1100B)  
Reset Value: see Table 66  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
TDOFF  
RES  
HB_TDOFF_BNK  
r
rw  
r
rw  
Field  
RES  
Bits  
Type  
Description  
Reserved, always read as 0  
15:14  
13:8  
r
TDOFF  
rw  
Turn-off delay time of active MOSFET of HBx  
The HB_TDOFF_BNK bits selects the turn-off delay  
time of the active MOSFET of the half-bridge HBx  
Nominal tDOFF = 53.3 ns x TDOFF[5:0]D  
Default: 0000 1100B : 640 ns  
RES  
7:3  
2:0  
r
Reserved, always read as 0  
HB_TDOFF_BNK  
rw  
Banking bits for turn-off delay time  
000B HB1, tDOFF of HB1 selected (default)  
001B HB2, tDOFF of HB2 selected  
010B HB3, tDOFF of HB3 selected  
1xxB , wrong setting of PWM_TDOFF_BNK  
Table 66 Reset of TDOFF_HB_CTRL  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 1100 0000 0000B  
00xx xxxx 0000 0000B  
Datasheet  
192  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Brake control  
BRAKE  
Brake control  
(001 1101B)  
Reset Value: see Table 67  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
SLAM SLAM SLAM  
RES _LS3_ _LS2_ _LS1_ SLAM H_BR  
VDST  
PARK_ OV_B  
BRK_E RK_E  
TBLK_  
BRK  
RES  
RES  
OV_BRK_TH  
DIS  
DIS  
DIS  
K
N
N
r
r
rw  
rw  
rw  
rw  
rw  
rw  
rw  
rw  
rw  
rw  
Field  
RES  
RES  
Bits  
Type  
Description  
15:14  
13  
r
Reserved, always read as 0  
Reserved, always read as 0  
r
SLAM_LS3_DIS  
SLAM_LS2_DIS  
SLAM_LS1_DIS  
12  
rw  
LS3 output disable during SLAM mode  
0B ACTIVE, LS3 control active in Slam mode  
(default)  
1B DISABLED, LS3 control disabled in Slam mode  
11  
10  
rw  
rw  
LS2 output disable during SLAM mode  
0B ACTIVE, LS2 control active in Slam mode  
(default)  
1B DISABLED, LS2 control disabled in Slam mode  
LS1 output disable during SLAM mode  
0B ACTIVE, LS1 control active in Slam mode  
(default)  
1B DISABLED, LS1 control disabled in Slam mode  
SLAM  
9
rw  
rw  
rw  
rw  
rw  
rw  
Slam mode  
0B INACTIVE, Slam mode deactivated (default)  
1B AVTIVE, Slam mode activated  
VDSTH_BRK  
TBLK_BRK  
PARK_BRK_EN  
OV_BRK_EN  
RES  
8
VDS Overvoltage for LS1-3 during braking  
0B 800mV, VVDSMONTH0_BRAKE, 0.8 V, typ. (default)  
1B 220mV, VVDSMONTH1_BRAKE, 0.22 V typ.  
7
Blank time of VDS overvoltage during braking  
0B 7uS, tBLK_BRAKE1,7 µs typ.  
1B 11uS, tBLK_BRAKE2, 11 µs typ. (default)  
6
Parking brake enable  
0B DISABLED, Parking brake disabled (default)  
1B ENABLED, Parking brake enabled  
5
Overvoltage brake enable  
0B DISABLED, Overvoltage brake disabled  
1B ENABLED, Overvoltage brake enabled (default)  
4:3  
Reserved, to be set to 0  
Datasheet  
193  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
Bits  
Type  
Description  
OV_BRK_TH  
2:0  
rw  
Overvoltage brake threshold  
000B 27V, typ. 27V (default)  
001B 28V, typ. 28V  
010B 29V, typ. 29V  
011B 30V, typ. 30V  
100B 31V, typ. 31V  
101B 32V, typ. 32V  
110B 33V, typ. 33V  
111B 34V, typ. 34V  
Table 67 Reset of BRAKE  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 1010 0000B  
000x xxxx xxx0 0xxxB  
Note:  
For min and max values of OV_BRK_TH, refer to Chapter 12.12.  
Datasheet  
194  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.6  
SPI status information registers  
READ/CLEAR Operation (see also Chapter 13.3):  
One 32-bit SPI command consist of four bytes:  
- The 7-bit address and one additional bit for the register access mode and  
- following the two data bytes and the CRC.  
The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to  
the SPI bits 8...23 (see also figure).  
There are two different bit types:  
- ‘r’ = READ: read only bits (or reserved bits).  
- ‘rc’ = READ/CLEAR: readable and clearable bits.  
Reading a register is done word wise by setting the SPI bit 7 to “0” (= Read Only).  
Clearing a register is done word wise by setting the SPI bit 7 to “1”. No single bits can be cleared. Therefore  
the content of a SPI message (bit 8..23) doesn’t matter.  
SPI status registers are in general not cleared or changed automatically (an exception are the x bits). This  
must be done by the microcontroller via SPI command.  
The registers are addressed wordwise.  
Table 68 Register Overview  
Register Short Name  
Register Long Name  
Offset Address Page  
Number  
SPI status information registers, Device Status Registers  
SUP_STAT  
Supply Voltage Fail Status  
Thermal Protection Status  
Device Information Status  
Bus Communication Status  
Wake-up Source and Information Status  
WK Input Level  
1000000B  
1000001B  
1000010B  
1000011B  
1000100B  
1000101B  
1000110B  
196  
THERM_STAT  
DEV_STAT  
198  
199  
201  
202  
203  
204  
BUS_STAT  
WK_STAT  
WK_LVL_STAT  
HS_OL_OC_OT_STAT  
High-Side Switch Status  
SPI status information registers, Status registers bridge driver  
GEN_STAT  
TDREG  
GEN Status register  
1010000B  
1010001B  
1010010B  
206  
208  
210  
212  
Turn-on/off delay regulation register  
Drain-source overvoltage HBVOUT  
DSOV  
EFF_TDON_OFF1  
Effective MOSFET turn-on/off delay - PWM half- 1010011B  
bridge 1  
EFF_TDON_OFF2  
EFF_TDON_OFF3  
Effective MOSFET turn-on/off delay - PWM half- 1010100B  
bridge 2  
213  
214  
Effective MOSFET turn-on/off delay - PWM half- 1010101B  
bridge 3  
TRISE_FALL1  
TRISE_FALL2  
TRISE_FALL3  
MOSFET rise/fall time - PWM half-bridge 1  
MOSFET rise/fall time - PWM half-bridge 2  
MOSFET rise/fall time - PWM half-bridge 3  
1010111B  
1011000B  
1011001B  
215  
216  
217  
SPI status information registers, Family and product information register  
FAM_PROD_STAT  
Family and Product Identification Register  
1110000B  
218  
Datasheet  
195  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.6.1  
Device Status Registers  
Supply Voltage Fail Status  
SUP_STAT  
Supply Voltage Fail Status  
(100 0000B)  
Reset Value: see Table 69  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
CP_O VCC1_ HS_U HS_O VSINT VSINT  
VCC1_ VCC1_ VCC1_ VCC1_  
POR  
RES  
VS_UV VS_OV CP_UV  
T
UV_FS  
V
V
_UV _OV  
rc rc  
SC  
UV  
OV WARN  
rc  
r
rc  
rc  
rc  
rc  
rc  
rc  
rc  
rc  
rc  
rc rc  
Field  
POR  
Bits  
15  
Type  
Description  
rc  
Power-On reset detection  
0B NO_POR, No POR  
1B POR, POR occurred  
RES  
14:13  
12  
r
Reserved, always reads as 0  
CP_OT  
rc  
Charge pump overtemperature  
0B NO_CP_OT, No charge pump OT detected  
1B CP_OT, Charge pump OT detected  
VCC1_UV_FS  
11  
rc  
4th consecutive VCC1 UV-Detection  
0B NO_FAILSAFE, No Fail-Safe Mode entry due to  
4th consecutive VCC1_UV  
1B FAILSAFE, Fail-Safe Mode entry due to 4th  
consecutive VCC1_UV  
HS_UV  
10  
9
rc  
rc  
rc  
rc  
rc  
HS Supply UV-Detection  
0B NO_UV, No Undervoltage  
1B UV_EVENT, HS Supply Undervoltage detected  
HS_OV  
HS Supply OV-Detection  
0B NO_OV, No Overvoltage  
1B OV_EVENT, HS Supply Overvoltage detected  
VSINT_UV  
VSINT_OV  
VS_UV  
8
VSINT UV-Detection  
0B NO_UV, No Undervoltage  
1B UV_EVENT, VSINT Undervoltage detected  
7
VSINT OV-Detection  
0B NO_OV, No Overvoltage  
1B OV_EVENT, VSINT Overvoltage detected  
6
VS Undervoltage Detection (VS,UV)  
0B NO_VS, No VS undervoltage detected  
1B VS_EVENT, VS undervoltage detected (detection  
is only active when VCC1 is enabled)  
VS_OV  
5
rc  
VS Overvoltage Detection (VS,OV)  
0B NO_OV, No VS overvoltage detected  
1B OV_EVENT, VS overvoltage detected (detection is  
only active when VCC1 is enabled)  
Datasheet  
196  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
Bits  
Type  
Description  
CP_UV  
4
rc  
CP_UV  
0B NO_UV, No CP undervoltage detected  
1B UV_EVENT, CP undervoltage detected  
VCC1_SC  
3
2
1
0
rc  
rc  
rc  
rc  
VCC1 SC  
0B NO_SC, No VCC1 short to GND detected  
1B SC_EVENT, VCC1 short to GND  
VCC1_UV  
VCC1_OV  
VCC1_WARN  
VCC1 UV-Detection (due to Vrtx reset)  
0B NO_UV, No VCC1_UV detection  
1B UV_EVENT, VCC1 undervoltage detected  
VCC1 Overvoltage Detection  
0B NO_OV, No VCC1 overvoltage warning  
1B OV_EVENT, VCC1 overvoltage detected  
VCC1 Undervoltage Prewarning  
0B NO_UV, No VCC1 undervoltage prewarning  
1B UV_PREWARN, VCC1 undervoltage prewarning  
detected  
Table 69 Reset of SUP_STAT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
y000 0000 0000 0000B  
x00x xxxx xxxx xxxxB  
Notes  
1. The VCC1 undervoltage prewarning threshold VPW,f / VPW,r is a fixed threshold and independent of the VCC1  
undervoltage reset thresholds.  
2. VSINT undervoltage monitoring is not available in Stop Mode due to current consumption saving  
requirements. Exception: VSINT undervoltage detection is also available in Stop Mode if the VCC1 load current  
is above the active peak threshold (I_PEAK_TH) or if VCC1 is below the VCC1 prewarning threshold  
(VCC1_WARN is set).  
3. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on  
reset (POR value = 1000 0000). However it will be cleared after a device Soft Reset command (Soft Reset value  
= 0000 0000).  
4. During Sleep Mode, the bits VCC1_SC, VCC1_OV and VCC1_UV will not be set when VCC1 is off.  
5. The VCC1_UV bit is never updated in Restart Mode, in Init Mode it is only updated after RSTN was released, it  
is always updated in Normal Mode and Stop Mode, and it is always updated in any device modes in a VCC1_SC  
condition (after VCC1_UV = 1 for > 2 ms).  
Datasheet  
197  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Thermal Protection Status  
THERM_STAT  
Thermal Protection Status  
(100 0001B)  
Reset Value: see Table 70  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
TSD2_  
SAFE  
RES  
TSD2 TSD1 TPW  
rc rc rc  
r
rc  
Field  
RES  
Bits  
Type  
Description  
Reserved, always reads as 0  
15:4  
3
r
TSD2_SAFE  
rc  
TSD2 Thermal Shut-Down Safe State Detection  
0B NO_TSD2_SF, No TSD2 safe state detected  
1B TSD2_SF, TSD2 safe state detected: >16  
consecutive TSD2 events occurred, next TSD2  
waiting time will be 64s  
TSD2  
TSD1  
TPW  
2
1
0
rc  
rc  
rc  
TSD2 Thermal Shut-Down Detection  
0B NO_TSD2, No TSD2 event  
1B TSD2_EVENT, TSD2 OT detected - leading to Fail-  
Safe Mode  
TSD1 Thermal Shut-Down Detection  
0B NO_TSD1, No TSD1 fail  
1B TSD1_EVENT, TSD1 OT detected (affected  
module is disabled)  
Thermal Pre Warning  
0B NO_TPW, No Thermal Pre warning  
1B TPW, Thermal Pre warning detected  
Table 70 Reset of THERM_STAT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 0000 0000 xxxxB  
Note:  
Temperature warning and shutdown bits are not reset automatically, even if the temperature pre  
warning or the TSD condition is not present anymore.  
Datasheet  
198  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Device Information Status  
DEV_STAT  
Device Information Status  
(100 0010B)  
Reset Value: see Table 71  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
CRC_S CRC_F  
SW_D  
EV  
SPI_F FAILU  
RES  
DEV_STAT  
RES  
WD_FAIL  
TAT  
AIL  
AIL  
RE  
r
r
rc  
rc  
r
rh  
rh  
rc  
rc  
Field  
RES  
Bits  
Type  
Description  
15:10  
9
r
r
Reserved, always read as 0  
CRC_STAT  
CRC_FAIL  
DEV_STAT  
CRC STAT Information  
0B DISABLED, CRC disabled  
1B ENABLED, CRC enabled  
CRC Fail Information1)  
0B NO_FAIL, No CRC Failure  
8
rc  
rc  
1B FAIL, CRC Failure detected  
7:6  
Device Status before Restart Mode  
00B CLEARED, Cleared (Register must be actively  
cleared)  
01B RESTART, Restart due to failure (WD fail, TSD2,  
VCC1_UV, trial to access Sleep Mode without any  
wake source activated); also after a wake from  
Fail-Safe Mode  
10B SLEEP, Sleep Mode  
11B , reserved  
RES  
5
4
r
Reserved, always reads 0  
SW_DEV  
rh  
Status of Operating Mode  
0B NORMAL, Normal operation  
1B SW_DEV, Software Development Mode is  
enabled  
WD_FAIL  
3:2  
rh  
Number of WD-Failure Events  
00B NO_FAIL, No WD Fail  
01B 1x, 1x WD Fail,  
10B 2x, 2x WD Fail  
11B 3x, more than 3xWD Fail  
SPI_FAIL  
FAILURE  
1
0
rc  
rc  
SPI Fail Information  
0B NO_FAIL, No SPI fail  
1B INVALID, Invalid SPI command detected  
Failure detection  
0B NO_FAIL, No Failure  
1B FAIL, Failure occured  
1) The CRC_FAIL bit will not be set in case the static CRC enabling / disabling sequence is sent (see Chapter 5.2).  
Datasheet  
199  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 71 Reset of DEV_STAT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 00xx xx0x xxxxB  
Notes  
1. The bits DEV_STAT show the status of the device before exiting Restart Mode. Either the device came from  
regular Sleep Mode or a failure (Restart Mode or Fail-Safe Mode) occurred. Coming from Sleep Mode will also  
be shown if there was a trial to enter Sleep Mode without having cleared all wake flags before.  
2. The WD_FAIL bits are implemented as a counter and are the only status bits, which are cleared automatically  
by the device.  
3. The SPI_FAIL bit can only be cleared via SPI command.  
4. The bit CRC_STAT and CRC_FAIL can be read regardless the CRC setting. The SPI read command on  
DEV_STAT ignores the CRC field.  
Datasheet  
200  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Bus Communication Status  
BUS_STAT  
Bus Communication Status  
(100 0011B)  
Reset Value: see Table 72  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
LIN_FAIL  
RES  
RES  
r
rc  
r
r
Field  
RES  
Bits  
Type  
Description  
15:7  
6:5  
r
Reserved, always reads as 0  
LIN_FAIL  
rc  
LIN failure status  
00B NO_FAIL, No failures  
01B LIN_TSD, LIN Thermal shutdown  
10B LIN_TXD_DOM_TO, LIN_TXD_DOM: detected a  
TXDLIN dominant timeout  
11B LIN_BUS_DOM_TO, LIN_BUS_DOM: detected a  
LIN dominant timeout  
RES  
RES  
4:3  
2:0  
r
r
Reserved, always reads as 0  
Reserved, always reads as 0  
Table 72 Reset of BUS_STAT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 0000 0xxx xxxxB  
Notes  
1. The VCAN_UV comparator is enabled if CAN Normal or CAN Receive Only Mode.  
Datasheet  
201  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Wake-up Source and Information Status  
WK_STAT  
Wake-up Source and Information Status  
(100 0100B)  
Reset Value: see Table 73  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
LIN_W  
U
TIMER TIMER  
2_WU 1_WU  
WK4_  
WU  
RES  
RES  
RES  
RES  
RES RES RES  
r
rc  
r
rc  
rc  
r
r
rc  
r
r
r
Field  
Bits  
Type  
Description  
RES  
15:11  
10  
r
Reserved, always reads as 0  
LIN_WU  
rc  
LIN wake up  
0B NO_WU, No Wake up  
1B WU, Wake up detected  
RES  
9
8
r
Reserved, always reads as 0  
TIMER2_WU  
rc  
Wake up via Timer2  
0B NO_WU, No Wake up  
1B WU, Wake up detected  
TIMER1_WU  
7
rc  
Wake up via Timer1  
0B NO_WU, No Wake up  
1B WU, Wake up detected  
RES  
6:5  
4
r
Reserved, always reads as 0  
Reserved, always reads as 0  
RES  
r
WK4_WU  
3
rc  
Wake up via WK4  
0B NO_WU, No Wake up  
1B WU, Wake up detected  
RES  
RES  
RES  
2
1
0
r
r
r
Reserved, always reads as 0  
Reserved, always reads as 0  
Reserved, always reads as 0  
Table 73 Reset of WK_STAT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 0xxx x000 00x0B  
Note:  
At Fail-Safe Mode entry, the WK_STAT register is automatically cleared by the device.  
Datasheet  
202  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
WK Input Level  
WK_LVL_STAT  
WK Input Level  
(100 0101B)  
Reset Value: see Table 74  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
WK4_  
LVL  
RES  
RES  
RES RES RES  
r
r
r
r
r
r
Field  
RES  
RES  
Bits  
Type  
Description  
15:5  
4
r
r
r
Reserved, always reads as 0  
Reserved, always reads as 0  
WK4_LVL  
3
Status of WK4  
0B LOW, Low Level (=0)  
1B HIGH, High Level (=1)  
RES  
RES  
RES  
2
1
0
r
r
r
Reserved, always reads as 0  
Reserved, always reads as 0  
Reserved, always reads as 0  
Table 74 Reset of WK_LVL_STAT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 00x0B  
0000 0000 0000 00x0B  
Note:  
WK_LVL_STAT is updated in Normal Mode and Stop Mode and also in Init and Restart Mode. In cyclic  
sense or wake mode, the registers contain the sampled level, i.e. the registers are updated after  
every sampling.  
Datasheet  
203  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
High-Side Switch Status  
HS_OL_OC_OT_STAT  
High-Side Switch Status  
(100 0110B)  
Reset Value: see Table 75  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
HS3_ HS2_ HS1_  
HS3_ HS2_ HS1_  
HS3_ HS2_ HS1_  
RES  
RES  
RES RES  
RES RES  
OT  
OT  
OT  
OL  
OL  
OL  
OC  
OC  
OC  
r
r
rc  
rc  
rc  
r
r
rc  
rc  
rc  
r
r
rc  
rc  
rc  
Field  
RES  
Bits  
Type  
Description  
15:14  
13  
r
Reserved, always reads as 0  
Reserved, always reads as 0  
RES  
r
HS3_OT  
12  
rc  
Overtemperature Detection on HS3  
0B NO_OT, No OT  
1B OT, OT detected  
HS2_OT  
HS1_OT  
11  
10  
rc  
rc  
Overtemperature Detection on HS2  
0B NO_OT, No OT  
1B OT, OT detected  
Overtemperature Detection on HS1  
0B NO_OT, No OT  
1B OT, OT detected  
RES  
9
8
7
r
Reserved, always reads as 0  
Reserved, always reads as 0  
RES  
r
HS3_OL  
rc  
Open-Load Detection on HS3  
0B NO_OL, No OL  
1B OL, OL detected  
HS2_OL  
HS1_OL  
6
5
rc  
rc  
Open-Load Detection on HS2  
0B NO_OL, No OL  
1B OL, OL detected  
Open-Load Detection on HS1  
0B NO_OL, No OL  
1B OL, OL detected  
RES  
4
3
2
r
Reserved, always reads as 0  
Reserved, always reads as 0  
RES  
r
HS3_OC  
rc  
Overcurrent Detection on HS3  
0B NO_OC, No OC  
1B OC, OC detected  
HS2_OC  
HS1_OC  
1
0
rc  
rc  
Overcurrent Detection on HS2  
0B NO_OC, No OC  
1B OC, OC detected  
Overcurrent Detection on HS1  
0B NO_OC, No OC  
1B OC, OC detected  
Datasheet  
204  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 75 Reset of HS_OL_OC_OT_STAT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
00xx xxxx xxxx xxxxB  
Datasheet  
205  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.6.2  
Status registers bridge driver  
General Status register  
GEN_STAT  
General Status register  
(101 0000B)  
Reset Value: see Table 76  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
HB3V HB2V HB1V PWM6 PWM5 PWM4 PWM3 PWM2 PWM1  
OUT OUT OUT STAT STAT STAT STAT STAT STAT  
RES  
RES  
r
r
r
r
r
r
r
r
r
r
r
Field  
RES  
RES  
Bits  
Type  
Description  
15:10  
r
r
r
Reserved, always reads as 0  
Reserved, always reads as 0  
9
8
HB3VOUT  
HB2VOUT  
HB1VOUT  
Voltage level at VSH3 when HB3MODE[1:0] = 11 and  
CPEN=11)  
0B LOW, VSH3 = Low : VS - VSH3 > VHS3VDSTHx  
1B HIGH, VSH3 = High: VS - VSH3 VHS3VDSTHx  
7
6
r
r
Voltage level at VSH2 when HB2MODE[1:0] = 11 and  
CPEN=11)  
0B LOW, VSH2 = Low : VS - VSH2 > VHS2VDSTHx  
1B HIGH, VSH2 = High: VS - VSH2 VHS2VDSTHx  
Voltage level at VSH1 when HB1MODE[1:0] = 11 and  
CPEN=11)  
0B LOW, VSH1 = Low : VS - VSH1 > VHS1VDSTHx  
1B HIGH, VSH1 = High: VS - VSH1 VHS1VDSTHx  
PWM6STAT  
PWM5STAT  
PWM4STAT  
PWM3STAT  
PWM2STAT  
PWM1STAT  
5
4
3
2
1
0
r
r
r
r
r
r
PWM6 status  
0B LOW, PWM6 is Low  
1B HIGH, PWM6 is High  
PWM5 status  
0B LOW, PWM5 is Low  
1B HIGH, PWM5 is High  
PWM4 Status  
0B LOW, PWM4 is Low  
1B HIGH, PWM4 is High  
PWM3 status  
0B LOW, PWM3 is Low  
1B HIGH, PWM3 is High  
PWM2 Status  
0B LOW, PWM2 is Low  
1B HIGH, PWM2 is High  
PWM1/CRC status  
0B LOW, PWM1/CRC is Low  
1B HIGH, PWM1/CRC is High  
1) HBxVOUT = 0 if (CPEN=1 and HBxMODE 11) or CPEN=0.  
Datasheet 206  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 76 Reset of GEN_STAT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 0000 xx00 000xB  
Datasheet  
207  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Turn-on/off delay regulation register  
TDREG  
Turn-on/off delay regulation register  
(101 0001B)  
Reset Value: see Table 77  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
IPDCH IPDCH IPDCH  
G3_ST G2_ST G1_ST  
IPCHG IPCHG IPCHG  
3_ST 2_ST 1_ST  
TDRE TDRE TDRE  
RES  
RES  
RES  
RES  
G3  
G2  
G1  
r
r
r
r
r
r
r
r
r
r
r
r
r
Field  
RES  
RES  
Bits  
Type  
Description  
15:12  
11  
r
r
r
Reserved, always reads as 0  
Reserved, always reads as 0  
HB3 predischarge status  
IPDCHG3_ST  
IPDCHG2_ST  
IPDCHG1_ST  
10  
0B CLAMP, the predischarge current is equal to  
0.5 mA typ. or ICHGMAX3 if AGC[1:0] = 10B or 11B,  
and HB3_PWM_EN = 11)  
1B NO_CLAMP, 0.5 mA < predischarge current <  
ICHGMAX31)  
9
8
r
r
HB2 predischarge status  
0B CLAMP, the predischarge current is equal to  
0.5 mA typ. or ICHGMAX2 if AGC[1:0] = 10B or 11B,  
and HB2_PWM_EN = 11)  
1B NO_CLAMP, 0.5 mA < predischarge current <  
ICHGMAX21)  
HB1 predischarge status  
0B CLAMP, the predischarge current is equal to the  
0.5 mA typ. or ICHGMAX1 if AGC[1:0] = 10B or 11B,  
and HBx_PWM_EN = 11)  
1B NO_CLAMP, 0.5 mA < predischarge current <  
ICHGMAX11)  
RES  
7
6
r
r
Reserved, always reads as 0  
IPCHG3_ST  
HB3 precharge status  
0B CLAMP, the precharge current is equal to 0.5 mA  
typ. or ICHGMAX3 if AGC[1:0] = 10B or 11B, and  
HB3_PWM_EN = 11)  
1B NO_CLAMP, 0.5 mA < precharge current <  
ICHGMAX31)  
IPCHG2_ST  
5
r
HB2 precharge status  
0B CLAMP, the precharge current is equal to 0.5 mA  
typ. or ICHGMAX2 if AGC[1:0] = 10B or 11B, and  
HB2_PWM_EN = 11)  
1B NO_CLAMP, 0.5 mA < precharge current <  
ICHGMAX21)  
Datasheet  
208  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
Bits  
Type  
Description  
IPCHG1_ST  
4
r
HB1 precharge status  
0B CLAMP, the precharge current is equal to the  
0.5 mA typ. or ICHGMAX1 if AGC[1:0] = 10B or 11B,  
and HB1_PWM_EN = 11)  
1B NO_CLAMP, 0.5 mA < precharge current <  
ICHGMAX11)  
RES  
3
2
r
r
Reserved, always reads as 0  
TDREG3  
HB3 Regulation of turn-on/off delay  
0B NO_REG, tDON3 and tDOFF3 are not in regulation  
1B REG, tDON3 and/or tDOFF3 are in regulation  
TDREG2  
TDREG1  
1
0
r
r
HB2 Regulation of turn-on/off delay  
0B NO_REG, tDON2 and tDOFF2 are not in regulation  
1B REG, tDON2 and/or tDOFF2 are in regulation  
HB1 Regulation of turn-on/off delay  
0B NO_REG, tDON and tDOFF are not in regulation  
1B REG, tDON and/or tDOFF are in regulation  
1) IPCHGx_ST = 1 otherwise (PWM disabled, HB in high impedance or AGC[1:0] = 00B or 01B ).  
Table 77 Reset of TDREG  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0000 0000 xx00 000xB  
Datasheet  
209  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Drain-source overvoltage status  
DSOV  
Drain-source overvoltage  
(101 0010B)  
Reset Value: see Table 78  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
VSINT  
OVBR  
AKE_S  
T
VSOV  
LS3DS LS2DS LS1DS  
OC_C  
SA  
LS3DS HS3D LS2DS HS2D LS1DS HS1D  
RES  
BRAK RES OV_B OV_B OV_B RES RES  
E_ST  
OV  
SOV  
OV  
SOV  
OV  
SOV  
RK  
RK  
RK  
r
rc  
rc  
rc  
r
rc  
rc  
rc  
r
r
rc  
rc  
rc  
rc  
rc  
rc  
Field  
RES  
Bits  
15  
Type  
Description  
r
Reserved, always reads as 0  
OC_CSA  
14  
rc  
CSA Overcurrent detection  
0B NO_OC, No overcurrent detected  
1B OC, Overcurrent detected  
VSINTOVBRAKE_ST  
VSOVBRAKE_ST  
13  
12  
rc  
rc  
VSINT Brake status  
0B NOT_DETECT, VSINT overvoltage brake  
condition is not detected  
1B DETECT, VSINT overvoltage brake conditions is  
detected  
VS Brake status  
0B NOT_DETECT, VS overvoltage brake conditions is  
not detected  
1B DETECT, VS overvoltage brake conditions is  
detected  
RES  
11  
10  
r
Reserved, always reads as 0  
LS3DSOV_BRK  
rc  
Drain-source overvoltage on low-side 3 during  
braking  
0B NO_OV, No drain-source overvoltage on LS3  
1B OV, Drain-source overvoltage on LS3  
LS2DSOV_BRK  
LS1DSOV_BRK  
9
8
rc  
rc  
Drain-source overvoltage on low-side 2 during  
braking  
0B NO_OV, No drain-source overvoltage on LS2  
1B OV, Drain-source overvoltage on LS2  
Drain-source overvoltage on low-side 1 during  
braking  
0B NO_OV, No drain-source overvoltage on LS1  
1B OV, Drain-source overvoltage on LS1  
RES  
7
6
5
r
Reserved, always reads as 0  
Reserved, always reads as 0  
RES  
r
LS3DSOV  
rc  
Drain-source overvoltage on low-side 3  
0B NO_OV, No drain-source overvoltage on LS3  
1B OV, Drain-source overvoltage on LS3  
Datasheet  
210  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Field  
Bits  
Type  
Description  
HS3DSOV  
4
rc  
Drain-source overvoltage on high-side 3  
0B NO_OV, No drain-source overvoltage on HS3  
1B OV, Drain-source overvoltage on HS3  
LS2DSOV  
HS2DSOV  
LS1DSOV  
HS1DSOV  
3
2
1
0
rc  
rc  
rc  
rc  
Drain-source overvoltage on low-side 2  
0B NO_OV, No drain-source overvoltage on LS2  
1B OV, Drain-source overvoltage on LS2  
Drain-source overvoltage on high-side 2  
0B NO_OV, No drain-source overvoltage on HS2  
1B OV, Drain-source overvoltage on HS2  
Drain-source overvoltage on low-side 1  
0B NO_OV, No drain-source overvoltage on LS1  
1B OV, Drain-source overvoltage on LS1  
Drain-source overvoltage on high-side 1  
0B NO_OV, No drain-source overvoltage on HS1  
1B OV, Drain-source overvoltage on HS1  
Table 78 Reset of DSOV  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
0xxx 0xxx 00xx xxxxB  
Datasheet  
211  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Effective MOSFET turn.on/off delay - PWM half-bridge 1  
EFF_TDON_OFF1  
Effective MOSFET turn.on/off delay - HB1  
(101 0011B)  
Reset Value: see Table 79  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
TDOFF1EFF  
RES  
TDON1EFF  
r
r
r
r
Field  
RES  
Bits  
Type  
Description  
Reserved, always reads as 0  
Effective active MOSFET turn-off delay HB1  
15:14  
13:8  
r
r
TDOFF1EFF  
Nominal effective tDOFF1 = 53.3 ns x TDOFF1EFF[13:8]D  
RES  
7:6  
5:0  
r
r
Reserved, always reads as 0  
TDON1EFF  
Effective active MOSFET turn-on delay HB1  
Nominal effective tDON1 = 53.3 ns x TDON1EFF[5:0]D  
Table 79 Reset of EFF_TDON_OFF1  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
00xx xxxx 00xx xxxxB  
Datasheet  
212  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Effective MOSFET turn.on/off delay - PWM half-bridge 2  
EFF_TDON_OFF2  
Effective MOSFET turn.on/off delay - HB 2  
(101 0100B)  
Reset Value: see Table 80  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
TDOFF2EFF  
RES  
TDON2EFF  
r
r
r
r
Field  
RES  
Bits  
Type  
Description  
Reserved, always reads as 0  
Effective active MOSFET turn-off delay HB2  
15:14  
13:8  
r
r
TDOFF2EFF  
Nominal effective tDOFF2 = 53.3 ns x TDOFF2EFF[13:8]D  
RES  
7:6  
5:0  
r
r
Reserved, always reads as 0  
TDON2EFF  
Effective active MOSFET turn-on delay HB2  
Nominal effective tDON2 = 53.3 ns x TDON2EFF[5:0]D  
Table 80 Reset of EFF_TDON_OFF2  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
00xx xxxx 00xx xxxxB  
Datasheet  
213  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Effective MOSFET turn.on/off delay - PWM half-bridge 3  
EFF_TDON_OFF3  
Effective MOSFET turn.on/off delay - HB3  
(101 0101B)  
Reset Value: see Table 81  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
TDOFF3EFF  
RES  
TDON3EFF  
r
r
r
r
Field  
RES  
Bits  
Type  
Description  
Reserved, always reads as 0  
Effective active MOSFET turn-off delay HB3  
15:14  
13:8  
r
r
TDOFF3EFF  
Nominal effective tDOFF3 = 53.3 ns x TDO3EFF[13:8]D  
RES  
7:6  
5:0  
r
r
Reserved, always reads as 0  
TDON3EFF  
Effective active MOSFET turn-on delay HB3  
Nominal effective tDON3 = 53.3 ns x TDON3EFF[5:0]D  
Table 81 Reset of EFF_TDON_OFF3  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
00xx xxxx 00xx xxxxB  
Datasheet  
214  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
MOSFET rise/fall time - PWM half-bridge 1  
TRISE_FALL1  
MOSFET rise/fall time - HB1  
(101 0111B)  
Reset Value: see Table 82  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
TFALL1  
RES  
TRISE1  
r
r
r
r
Field  
RES  
Bits  
Type  
Description  
15:14  
13:8  
r
r
Reserved, always reads as 0  
TFALL1  
Active MOSFET fall time HB1  
Nominal tFALL1 = 53.3 ns x TFALL1[5:0]D  
RES  
7:6  
5:0  
r
r
Reserved, always reads as 0  
TRISE1  
Active MOSFET rise time HB1  
Nominal tRISE1 = 53.3 ns x TRISE1[5:0]D  
Table 82 Reset of TRISE_FALL1  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
00xx xxxx 00xx xxxxB  
Datasheet  
215  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
MOSFET rise/fall time - PWM half-bridge 2  
TRISE_FALL2  
MOSFET rise/fall time - HB2  
(101 1000B)  
Reset Value: see Table 83  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
TFALL2  
RES  
TRISE2  
r
r
r
r
Field  
RES  
Bits  
Type  
Description  
15:14  
13:8  
r
r
Reserved, always reads as 0  
TFALL2  
Active MOSFET fall time HB2  
Nominal tFALL2 = 53.3 ns x TFALL2[5:0]D  
RES  
7:6  
5:0  
r
r
Reserved, always reads as 0  
TRISE2  
Active MOSFET rise time HB2  
Nominal tRISE2 = 53.3 ns x TRISE2[5:0]D  
Table 83 Reset of TRISE_FALL2  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
00xx xxxx 00xx xxxxB  
Datasheet  
216  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
MOSFET rise/fall time - PWM half-bridge 3  
TRISE_FALL3  
MOSFET rise/fall time - HB3  
(101 1001B)  
Reset Value: see Table 84  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
TFALL3  
RES  
TRISE3  
r
r
r
r
Field  
RES  
Bits  
Type  
Description  
15:14  
13:8  
r
r
Reserved, always reads as 0  
TFALL3  
Active MOSFET fall time HB3  
Nominal tFALL3 = 53.3 ns x TFALL3[5:0]D  
RES  
7:6  
5:0  
r
r
Reserved, always reads as 0  
TRISE3  
Active MOSFET rise time HB3  
Nominal tRISE3 = 53.3 ns x TRISE3[5:0]D  
Table 84 Reset of TRISE_FALL3  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0000 0000 0000B  
00xx xxxx 00xx xxxxB  
Datasheet  
217  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.6.3  
Family and product information register  
Family and Product Identification Register  
FAM_PROD_STAT  
Family and Product Identification Register (111 0000B)  
Reset Value: see Table 85  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
RES  
FAM  
PROD  
r
r
r
Field  
RES  
Bits  
Type  
Description  
15:11  
10:7  
r
r
Reserved, always reads as 0  
FAM  
Device Family Identifier  
1000B, BLDC Motor System IC  
PROD  
6:0  
r
Device Product Identifier  
000 0000BTLE9562-3QX/QX, TLE9562-3QX/-3QXJ/QX  
000 0001BTLE9561-3QX/QX, TLE9561-3QX/-3QXJ/QX  
000 0010BTLE9563-3QX, TLE9563-3QX/-3QXJ  
000 0011BTLE9564QX, TLE9564QX,TLE9185QX  
001 0000BTLE9562-3QX V33, TLE9562-3QX V33  
001 0010BTLE9563-3QX V33, TLE9563-3QX V33  
001 0011BTLE9564QX V33,  
TLE9564QX V33,TLE9185QX V33  
001 1000BTLE9560QX, TLE9560-3QX/-3QXJ  
Table 85 Reset of FAM_PROD_STAT  
Register Reset Type Reset Values  
Reset Short Name Reset Mode  
Note  
POR/Soft reset  
Restart  
0000 0100 0000 0011B  
0000 0100 0000 0011B  
Datasheet  
218  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
13.7  
Electrical Characteristics  
Table 86 Electrical Characteristics: Power Stage  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
SPI frequency  
1)  
Maximum SPI frequency  
fSPI,max  
6.0  
MHz  
V
> 3 V  
P_14.7.1  
CC1  
SPI Interface; Logic Inputs SDI, CLK and CSN  
H-input Voltage Threshold VIH  
L-input Voltage Threshold VIL  
Hysteresis of input Voltage VIHY  
0.7 ×  
VCC1  
V
P_14.7.2  
P_14.7.3  
P_14.7.4  
P_14.7.5  
0.3 ×  
VCC1  
V
1)  
0.12 ×  
VCC1  
V
Pull-up Resistance at pin  
CSN  
RICSN  
20  
20  
40  
40  
10  
80  
80  
kΩ  
kΩ  
pF  
Pull-down Resistance at pin RICLK/SDI  
SDI and CLK  
VSDI/CLK = 0.2 × VCC1 P_14.7.6  
1)  
Input Capacitance at pin  
CSN, SDI or CLK  
CI  
V
, VSDI, VCLK  
=
P_14.7.7  
CSN  
VCC1  
Logic Output SDO  
H-output Voltage Level  
VSDOH  
VSDOL  
0.8 ×  
VCC1  
V
IDOH = -2 mA  
P_14.7.8  
P_14.7.9  
P_14.7.11  
P_14.7.38  
L-output Voltage Level  
0.2 ×  
VCC1  
V
IDOL = 2 mA  
1)  
‘Tri-state Input Capacitance CSDO  
10  
15  
pF  
µA  
V
, VSDI, VCLK =  
CSN  
VCC1  
1)  
Tri-state Leakage Current  
ISDOLK  
–10  
10  
V
= VCC1,  
CSN  
0V < VSDO< VCC1  
Data Input Timing1)  
Clock Period  
tpCLK  
tCLKH  
tCLKL  
160  
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
P_14.7.12  
P_14.7.13  
P_14.7.14  
P_14.7.15  
P_14.7.16  
P_14.7.17  
P_14.7.18  
P_14.7.19  
P_14.7.20  
Clock HIGH Time  
Clock LOW Time  
70  
Clock LOW before CSN LOW tbef  
70  
CSN Setup Time  
CLK Setup Time  
tlead  
tlag  
160  
160  
70  
Clock LOW after CSN HIGH tbeh  
SDI Setup Time  
SDI Hold Time  
tDISU  
tDIHO  
60  
40  
Datasheet  
219  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Serial Peripheral Interface  
Table 86 Electrical Characteristics: Power Stage (cont’d)  
VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Input Signal Rise Time at pin trIN  
SDI, CLK and CSN  
20  
ns  
ns  
µs  
µs  
P_14.7.21  
P_14.7.22  
P_14.7.23  
P_14.7.24  
Input Signal Fall Time at pin tfIN  
SDI, CLK and CSN  
3
20  
5
3)  
Delay Time for Mode  
Changes2)  
tDel,Mode  
CSN HIGH Time  
tCSN(high)  
Data Output Timing1)  
SDO Rise Time  
trSDO  
tfSDO  
30  
30  
40  
40  
ns  
ns  
CL = 50 pF, 0.2 × VCC1 P_14.7.25  
to 0.8 × VCC1  
SDO Fall Time  
CL = 50 pF, 0.8 × VCC1 P_14.7.26  
to 0.2 × VCC1  
SDO Enable Time  
SDO Disable Time  
SDO Valid Time  
tENSDO  
tDISSDO  
tVASDO  
40  
40  
40  
ns  
ns  
ns  
LOW impedance  
HIGH impedance  
CL = 50 pF  
P_14.7.27  
P_14.7.28  
P_14.7.29  
1) Not subject to production test; specified by design.  
2) Applies to all mode changes triggered via SPI commands.  
3) Guaranteed by design.  
24  
CSN  
15  
16  
17  
18  
13  
14  
CLK  
SDI  
19  
20  
LSB  
MSB  
MSB  
not defined  
27  
28  
29  
SDO  
Flag  
LSB  
Figure 74 SPI Timing Diagram  
Note:  
Numbers in drawing correlate with the last 2 digits of the Number field in the Electrical  
Characteristics table.  
Datasheet  
220  
Rev. 1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Application Information  
14  
Application Information  
Note:  
The following information is given as a hint for the implementation of the device only and shall not  
be regarded as a description or warranty of a certain functionality, condition or quality of the device.  
14.1  
Application Diagrams  
VCC1  
Drev1  
CVCC1  
VSINT  
L1  
Trev1  
SDI  
VS  
VBAT  
Cin1  
SDO  
CLK  
CSN  
CCP  
Cin5  
CP  
CPC1N  
CPC1P  
CPC2N  
CPC2P  
Rrev2  
CCP1  
Trev2  
RSTN  
INTN  
Drev3  
CCP2  
RLED  
HS1  
CHS2  
CHS2  
CHS2  
CHS1  
CHS1  
CHS1  
RLED  
HS2  
HS3  
GHx  
Q1  
RLED  
SHx  
GLx  
CHB1x  
CHB2x  
TLE9564  
Microcontroller  
Q2  
VBAT  
to other bridges  
SL  
WK4  
RWK1  
CSAP  
CSAN  
RFILT1  
PWM1  
PWM2  
PWM3  
PWM4  
RFILT2  
RCSO  
CSO  
ADC IN  
CCSO  
PWM5  
PWM6  
VSHS  
DLIN  
RLIN  
LIN  
TxD_LIN  
RxD_LIN  
CLIN  
GND  
Figure 75 TLE9564QX Application Diagram  
Note:  
This is a very simplified example of an application circuit. The function must be always verified in the  
real application.  
Datasheet  
221  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Application Information  
Table 87 Bill of Material  
Ref.  
Typical Value  
Purpose / Comment  
Capacitances  
Cin1  
100 nF ±20%  
ceramic  
Input filter battery capacitor for optimum EMC behavior  
Cin2  
100 µF ±20%, 50 V  
Electrolytic  
Buffering capacitor to cut off battery spikes, depending on the  
application  
Cin2b  
Cin3  
470 µF ±20%, 50 V  
Electrolytic  
Buffering capacitor for bridges. Cut off battery spikes,  
depending on the application  
100 nF ±20%, 50 V  
Ceramic  
Input capacitor  
Cin4  
100 nF ±20%, 50 V  
Ceramic  
Input capacitor  
Cin5  
470 µF ±20%, 50 V  
Electrolytic  
Buffering capacitor for bridges. Cut off battery spikes,  
depending on the application  
CCP  
470 nF ±20%, 50 V  
Ceramic  
Charge-Pump buffering capacitor  
CCP1/ CCP2  
220 nF ±20%, 50 V  
Ceramic  
Charge-Pump flying capacitor to be placed as closed as possible  
to the device pins, in order to minimize the length of the PCB  
tracks  
CFILT1  
1.5 nF ±20%, 16 V  
Ceramic  
Current-sense filtering  
CFILT2 / CFILT3  
CCSO  
22 nF ±20%, 16 V  
Ceramic  
Current-sense filtering  
16 V  
Ceramic  
CSO buffering cap for a stable ADC voltage. Max 400 pF in case no  
resistor is used. With 50 resistor up to 2.2 nF. (See CSA  
configuration register)  
CLIN  
1 nF / OEM dependent  
2.2 uF ±20%, 16 V  
LIN master termination  
CVCC1  
Blocking capacitor. Low ESR. Minimum 1 uF effective  
capacitance  
CHB1x  
10 nF ±20%, 50 V  
Ceramic  
Half-Bridge EME (electromagnetic emission) and ESD  
suppression filter to be placed close to the connector. Other  
capacitance values might be needed depending on application  
CHB2x  
560 pF ±20%, 50 V  
Ceramic  
Optional filter for EMI immunity to be placed close to the SHx pin  
(PCB footprints highly recommended). Other capacitance values  
might be needed depending on application  
CHS1  
47 pF / OEM dependent  
33 nF / OEM dependent  
47 nF / OEM dependent  
Only required om case of off-board connection to optimize  
EMC behavior, place close to pin  
CHS2  
As required by application, mandatory protection for off-board  
connection  
CWK1 / CWK2  
Spike filtering, as required by application, mandatory protection  
for off-board connections  
Datasheet  
222  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Application Information  
Table 87 Bill of Material (cont’d)  
Ref.  
Typical Value  
Purpose / Comment  
Inductances  
L1  
4 uH ... 6 uH  
Input filter for power stage - consider high current rating  
(application dependent)  
Resistances  
RREV1  
100 k±5%  
10 k±5%  
10 k±5%  
5 m±1%  
4.7 ±5%  
50 ±5%  
Other values needed depending on application  
Device protection against reverse battery  
RREV2  
RREV3  
RSENSE  
Current-sense resistor  
Current-sense filtering  
RFILT1 / RFILT2  
RCSO  
Compensation for internal opamp.Depending on SPI  
configuration  
RLIN  
1 k ±5%  
1 k  
LIN master termination  
Limit LED-current  
RLED  
RWK1 / RWK2  
RWK3 / RWK4  
/
10 k±5%  
Active Components  
DREV1  
DREV2  
DREV3  
TREV1  
TREV2  
Q1 / Q2  
DLIN  
RR268MM600  
Reverse polarity protection  
Gate protection. Limit VGS  
BZX84C16  
BAS21  
IPZ40N04S5L-2R8  
BC846  
Reverse battery protection, N-MOS  
Main power switches  
IPZ40N04S5-3R1  
BAS70  
Requested by LIN standard; reverse polarity protection of  
network  
Datasheet  
223  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Application Information  
14.2  
ESD Tests  
14.2.1  
ESD according to IEC61000-4-2  
Tests for ESD robustness according to IEC61000-4-2 “GUN test” (150 pF, 330 ) have been performed.  
The results and test condition are available in a test report. The values for the test are listed below.  
Table 88 ESD “GUN test”1)2)  
Performed Test  
Result  
Unit  
Remarks  
ESD at pin LIN, HSx, VS,VSINT,VS, > 6  
kV  
positive pulse  
WKx  
versus GND  
ESD at pin LIN, HSx, VS,VSINT,VS, < -6  
kV  
negative pulse  
WKx  
versus GND  
1) ESD susceptibility “ESD GUN” according to EMC 1.3 Test specification, Section 4.3 (IEC 61000-4-2). Tested by external  
test house (IBEE Zwickau, EMC Test report Nr. 20.12.20).  
2) ESD Test “Gun Test” is specified with external components for pins VS, VSINT, VS, WKx, HSx. See the application  
diagram in Chapter 14.1 for more information.  
14.2.2  
ESD according to SAE J2962  
Tests for ESD robustness according to SAE J2962 have been performed.  
Table 89 ESD according to SAE J2962  
Performed Test  
ESD at pin  
Result  
± 4  
Unit  
kV  
Remarks  
Unpowered, contact discharge  
1)Powered, contact discharge  
1)Powered, air discharge  
ESD at pin  
± 8  
kV  
ESD at pin  
± 25  
kV  
1) For ESD pulses - 6 kV, VCC1 undervoltage may be detected.  
Datasheet  
224  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Application Information  
14.3  
Thermal Behavior of Package  
Bottom view  
cooling area  
Detail solder  
pads and vias  
Top view  
Figure 76 Board Setup  
Board setup is defined according JESD 51-2, -5, -7.  
Board: 76.2 × 114.3 × 1.5 mm3 with 2 inner copper layers (35 µm thick), with thermal via array under the  
exposed pad contacting the first inner copper layer and 300 mm2 cooling area on the bottom layer (70 µm).  
14.4  
Further Application Information  
The VS pin supplies the bridge driver and the charge pump, and is the sense pin for the high-side MOSFETs  
drain voltage. It is therefore highly recommended to connect a 100 nF / 50V ceramic by-pass capacitor as  
close as possible to the VS pin with a short PCB trace to GND.  
Please contact us for information regarding the FMEA pin  
For further information you may contact http://www.infineon.com/  
Datasheet  
225  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Package Outlines  
15  
Package Outlines  
0ꢀ9 MAXꢀ  
(0ꢀ65)  
11 x 0ꢀ5 = 5ꢀ5  
0ꢀ5  
0ꢀ1  
7
A
0ꢀ03  
6ꢀ8  
0ꢀ1  
+0ꢀ031)  
2)  
37  
B
36  
25  
24  
13  
48x  
0ꢀ08  
48  
1
12  
Index Marking  
48x  
0ꢀ1  
0ꢀ4 x 45°  
0ꢀ05  
Index Marking  
0ꢀ23  
M
A B C  
(0ꢀ2)  
0ꢀ05 MAXꢀ  
(5ꢀ2)  
(6)  
C
1) Vertical burr 0ꢀ03 maxꢀ, all sides  
2) These four metal areas have exposed diepad potential  
PG-VQFN-48-29, -31-PO V05  
Figure 77 PG-VQFN-481)  
Green Product (RoHS compliant)  
To meet the world-wide customer requirements for environmentally friendly products and to be compliant  
with government regulations the device is available as a green product. Green products are RoHS-Compliant  
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).  
Further information on packages  
https://www.infineon.com/packages  
1) Dimensions in mm  
Datasheet  
226  
Rev.1.0  
2021-01-21  
TLE9564QX  
BLDC Motor System IC  
Revision History  
16  
Revision History  
Revision Date  
Changes  
1.0  
2021-01-21  
First release  
Datasheet  
227  
Rev.1.0  
2021-01-21  
Trademarks  
All referenced product or service names and trademarks are the property of their respective owners.  
IMPORTANT NOTICE  
The information given in this document shall in no For further information on technology, delivery terms  
Edition 2021-01-21  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest  
characteristics ("Beschaffenheitsgarantie").  
Infineon Technologies Office (www.infineon.com).  
With respect to any examples, hints or any typical  
values stated herein and/or any information regarding  
the application of the product, Infineon Technologies  
hereby disclaims any and all warranties and liabilities  
of any kind, including without limitation warranties of  
non-infringement of intellectual property rights of any  
third party.  
In addition, any information given in this document is  
subject to customer's compliance with its obligations  
stated in this document and any applicable legal  
requirements, norms and standards concerning  
customer's products and any use of the product of  
Infineon Technologies in customer's applications.  
The data contained in this document is exclusively  
intended for technically trained staff. It is the  
responsibility of customer's technical departments to  
evaluate the suitability of the product for the intended  
application and the completeness of the product  
information given in this document with respect to  
such application.  
WARNINGS  
Due to technical requirements products may contain  
dangerous substances. For information on the types  
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