TLE9278-3BQX [INFINEON]
A high-efficient switch mode power supply (SMPS) buck regulator provides an external 5.0 V output voltage at up to 750 mA, while an additional DC/DC boost converter supports applications or conditions at low input supply voltages. The device is controlled and monitored via a 16-bit serial peripheral interface (SPI). Additional features include a time-out/window watchdog circuit with reset, fail output and undervoltage reset. The device offers low-power modes in order to support applications that are connected permanently to the battery. A wake-up from the low-power mode is possible via LIN/CAN bus, via the bi-level sensitive monitoring/wake-up input as well as via the timer. The TLE9278-3BQX is offered in a very small footprint, exposed pad PG-VQFN-48 (7 x 7 mm2) power package.;
| 型号： | TLE9278-3BQX |
| 厂家： | 
Infineon |
| 描述： | A high-efficient switch mode power supply (SMPS) buck regulator provides an external 5.0 V output voltage at up to 750 mA, while an additional DC/DC boost converter supports applications or conditions at low input supply voltages. The device is controlled and monitored via a 16-bit serial peripheral interface (SPI). Additional features include a time-out/window watchdog circuit with reset, fail output and undervoltage reset. The device offers low-power modes in order to support applications that are connected permanently to the battery. A wake-up from the low-power mode is possible via LIN/CAN bus, via the bi-level sensitive monitoring/wake-up input as well as via the timer. The TLE9278-3BQX is offered in a very small footprint, exposed pad PG-VQFN-48 (7 x 7 mm2) power package. |
| 文件： | 总194页 (文件大小：5048K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
1
Overview
Features
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SMPS with integrated switches up to 750 mA (DC/DC buck) with 5.0 V
output voltage
DC/DC Boost converter for low Vsup supply voltage with integrated switch
at 6.5 V, 8 V, 10 V and 12 V
Low-Drop Voltage Regulator with external PNP device with configurable 5.0 V, 3.3 V, 1.8 V and 1.2 V output
voltage, protected for off-board usage
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Very low quiescent current consumption in Stop and Sleep Mode
Dedicated pin for I/O voltage supply selection
Four CAN Transceivers compliant to CAN Flexible Data-rate (FD)
ISO 11898-2: 2016 standard up to 5 Mb
Partial Networking (PN) support
One universal High-Voltage Wake Input for voltage level monitoring including wake up capability
Cyclic wake feature via an integrated timer
Reset Output to ensure stable supply to the MCU
Fail Output to activate external load in case of system malfunctions are detected
Output voltage supervision functions in all output supply voltages
Fast Battery Voltage Monitoring Feature
16-bit Serial Perpheral Interface (SPI)
Overtemperature and short circuit protection feature
Wide input voltage and temperature range
Software Compatibility to other SBC family members for the TLE926x and TLE927x families
Green Product (RoHS compliant) & AEC Qualified
7 × 7 mm PG-VQFN-48 package
Potential applications
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Gateways
Body control modules
Driver assistance
Chasis control
Datasheet
www.infineon.com
Rev. 1.5
2019-09-27
1
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Overview
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100/101.
Description
Infineon’s TLE9278-3BQX offers the highest level of integration at smallest footprint for automotive
applications requiring multiple channels of CAN transceivers like gateways and high-end Body Control
Modules (BCM). A high-efficient Switch Mode Power Supply (SMPS) buck regulator provides an external 5.0 V
output voltage at up to 750 mA while an additional DC/DC boost converter supports applications or conditions
at low supply input voltages. The device is controlled and monitored via a 16-bit Serial Peripheral Interface
(SPI). Additional features include a time-out/window watchdog circuit with reset, fail output and
undervoltage reset. The device offers low-power modes in order to support applications that are connected
permanently to the battery. A wake-up from the low-power mode is possible via a message on the buses, via
the bi-level sensitive monitoring/wake-up input as well as via the timer. The TLE9278-3BQX is offered in a very
small footprint, exposed pad PG-VQFN-48 (7 × 7 mm) power package.
Type
Package
Marking
TLE9278-3BQX
PG-VQFN-48
TLE9278-3BQX
Datasheet
2
Rev.1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
3.2
3.3
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
4.2
4.3
4.4
5
5.1
System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
State Machine Description and SBC Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device Configuration and SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Supply and Power up configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Watchdog trigger failure configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SBC Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SBC Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SBC Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SBC Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CAN Partial Networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CAN Partial Networking - Selective Wake Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SBC Partial Networking Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Activation of SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Wake-up Pattern (WUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Wake-up Frame (WUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CAN Protocol Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Diagnoses Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PWRON/RESET-FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
BUSERR-Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TxD Dominant Time-out flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
WUP_x Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.1
5.1.1.1
5.1.1.2
5.1.1.3
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.2.1
5.3.2.2
5.3.2.3
5.3.2.4
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.3.4
Datasheet
3
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
5.3.3.5
5.3.3.6
5.3.3.7
5.3.3.8
5.3.3.9
5.3.3.10
5.3.3.11
5.3.4
5.3.4.1
5.3.4.2
5.3.4.3
5.3.4.4
5.3.4.5
5.3.5
5.3.6
5.3.7
5.3.8
5.3.8.1
5.3.8.2
5.3.9
WUF Flag (WUF_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SYSERR Flag (SYSERR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CAN BUS Time-out-Flag (CANTO_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CAN BUS Silence-Flag (CANSIL_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SYNC-FLAG (SYNC_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SWK_SET FLAG (SWK_SET_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SBC Modes for Selective Wake (SWK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SBC Normal Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SBC Stop Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SBC Sleep Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SBC Restart Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SBC Fail-Safe Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Configuration for SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CAN Flexible Data Rate (CAN FD) Tolerant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Configuring the Clock Data Recovery for SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Setup of Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6
6.1
DC/DC Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Functional Description of the Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Startup Procedure (Soft Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Buck regulator Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Functional Description of the Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Boost Regulator Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Power Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Buck behavior in SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Buck behavior in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Automatic Transition from PFM to PWM in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Manual Transition from PFM to PWM in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SBC Stop to Normal Mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Buck behavior in SBC Sleep or Fail Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SBC Sleep/Fail Safe Mode to SBC Normal Mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.1.1
6.1.1.1
6.1.1.2
6.1.1.3
6.1.2
6.1.2.1
6.1.2.2
6.2
6.2.1
6.2.2
6.2.2.1
6.2.2.2
6.2.2.3
6.2.3
6.2.3.1
6.3
7
External Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Calculation of RSHUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.1
7.2
7.2.1
7.3
7.4
7.5
7.6
Datasheet
4
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
8
8.1
8.2
High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
CAN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CAN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CAN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CAN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.3
9
Wake Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.1
9.2
9.2.1
9.3
10
10.1
10.2
Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
11
11.1
11.2
Fail Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12
12.1
Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Watchdog during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Watchdog Start in SBC Stop Mode due to BUS Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
VS Power ON Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Measurement Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Fast Battery Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
VBSENSE Boost deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
VIO Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VIO Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VIO Short Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
VEXT Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.1.1
12.1.2
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.4.1
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
12.11.1
12.12
13
13.1
13.2
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SPI Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Datasheet
5
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
13.3
13.4
SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPI Mapping Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPI Register Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPI Mapping Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Selective Wake Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Selective Wake Trimming and Calibration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SPI Status Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Selective Wake Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Family and Product Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.4.1
13.4.2
13.4.3
13.5
13.5.1
13.5.2
13.5.3
13.6
13.6.1
13.6.2
13.6.3
13.7
14
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.1
14.2
14.3
15
16
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Datasheet
6
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Block Diagram
2
Block Diagram
VS
VS
BSTD
BSTD
GND
VCC1
Buck
Boost
BCKSW
VCC1
GND
Vint.
VEXTIN
VEXTSH
VEXTB
FO/TEST
Fail Safe
Vext
PCFG
VIO
VEXT REF
SBC
STATE
SDI
SDO
SPI
CLK
CSN
MACHINE
INTN
Interrupt
Control
VBSENSE
Window Watchdog
RSTN
RESET
GENERATOR
4
4
WAKE
REGISTER
WK
WK
Selective Wake
Logic
4
TXDCAN0
RXDCAN0
TXDCAN2
RXDCAN2
CAN
Module 0
CAN
Module 2
CANH0
CANL0
CANH2
CANL2
VCAN
TXDCAN3
RXDCAN3
TX DCAN1
RXDCAN1
CAN
Module 1
CAN
Module 3
CANH3
CANL3
CANH1
CANL1
GND
Figure 1
Block Diagram
Datasheet
7
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
CSN 37
SDO 38
24 RSTN
23 VIO
SDI 39
22 VCC1
CLK 40
GND 41
WK 42
21 RXDCAN3
20 TXDCAN3
19 VCAN
TLE9278
VBSENSE 43
VEXTIN 44
VEXTSH 45
VEXTB 46
VEXTREF 47
FO/TEST 48
18 RXDCAN2
17 TXDCAN2
16 RXDCAN1
15 TXDCAN1
14 RXDCAN0
13 TXDCAN0
PG-VQFN-48
Figure 2
Pin Configuration TLE9278-3BQX
Datasheet
8
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Pin Configuration
3.2
Pin Definitions and Functions
Pin
1
Symbol
CANH0
CANL0
GND
Function
CAN High 0 Bus Pin.
2
CAN Low 0 Bus Pin.
3
Ground. CAN0 and CAN1 common ground.
CAN Low 1 Bus Pin.
4
CANL1
CANH1
GND
5
CAN High 1 Bus Pin.
6
Ground. Analog GND.
7
CANH2
CANL2
GND
CAN High 2 Bus Pin.
8
CAN Low 2 Bus Pin.
9
Ground. CAN2 and CAN3 common ground.
CAN Low 3 Bus Pin.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CANL3
CANH3
PCFG
CAN High 3 Bus Pin.
Configuration pin. For power up hardware configuration (refer to Chapter 5.1.1).
Transmit CAN0.
TXDCAN0
RXDCAN0
TXDCAN1
RXDCAN1
TXDCAN2
RXDCAN2
VCAN
Receive CAN0.
Transmit CAN1.
Receive CAN1.
Transmit CAN2.
Receive CAN2.
Supply Input for internal HS-CAN modules.
Transmit CAN3.
TXDCAN3
RXDCAN3
VCC1
Receive CAN3.
Buck Regulator. Input feedback for Buck Converter.
VIO
I/O voltage supply, reference voltage for over-/undervoltage monitoring
(see Chapter 5.1.1).
24
25
26
27
28
29
RSTN
INTN
GND
BCKSW
n.c.
Reset Output. Active LOW, internal pull-up.
Interrupt Output. Active LOW.
Ground. Buck regulator ground.
Buck regulator switch node output.
not connected. Not bondend internally.
VS
Buck Supply Voltage. Connected to Battery Voltage or Boost output voltage
with reverse protection diode. Use a filter against EMC in case that the Boost is
not used.
30
VS
Buck Supply Voltage. Connected to Battery Voltage or Boost output voltage
with reverse protection diode. Use a filter against EMC in case that the Boost is
not used.
31
32
33
n.c.
not connected. Not bondend internally.
Ground. Boost regulator ground.
Ground. Boost regulator ground.
GND
GND
Datasheet
9
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Pin Configuration
Pin
34
Symbol
n.c.
Function
not connected. Not bondend internally.
35
BSTD
Boost Transistor Drain. Connected between inductor and diode for boost
functionality (refer to Chapter 14.1 for additional information). Connect to
ground if the Boost regulator is not used.
36
BSTD
Boost Transistor Drain. Connected between inductor and diode for boost
functionality (refer to Chapter 14.1 for additional information). Connect to
ground if the Boost regulator is not used.
37
38
39
40
41
42
43
44
CSN
SPI Chip Select Not Input.
SPI Data Output. Out of SBC (=MISO).
SPI Data Input. Into SBC (=MOSI).
SPI Clock Input.
SDO
SDI
CLK
GND
Ground. Common digital ground.
Wake Input.
WK
VBSENSE
VEXTIN
Battery Voltage Monitoring Input.
Input Supply Voltage for VEXT. Connected to Battery Voltage with Reverse
Protection Diode and Filter against EMC.
45
46
47
48
VEXTSH
VEXTB
VEXTSH. Emitter connection for external PNP, shunt connection to VEXTIN.
VEXTB. Base connection for external PNP.
VEXTREF
FO/TEST
VextREF. Collector connection for external PNP, reference input.
Fail Output. active LOW, open-drain;
TEST. Connect to GND to activate SBC Development Mode; Integrated pull-up
resistor. Connect to VS with a pull-up resistor or leave open for normal operation.
Cooling GND
Tab
Cooling Tab - Exposed Die Pad; For cooling purposes only, do not use as an
electrical ground.1)
1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the SBC via the PCB.
The exposed die pad is not connected to any active part of the IC and can be left floating or it can be connected to
GND (recommended) for the best EMC performance.
Note:
All VS pins must be connected to battery potential or insert a reverse polarity diodes where required;
All GND pins as well as the Cooling Tab must be connected to one common GND potential.
Datasheet
10
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Pin Configuration
3.3
Unused Pins
It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that
they are disabled via SPI:
•
•
•
•
•
CANHx, CANLx, TXDCANx, RXDCANx: leave pins open.
BSTD: connect to GND.
WK: connect to GND and disable WK input via SPI.
RSTN / INTN: leave open.
FO/TEST: connect to GND during power-up to activate SBC Development Mode; connect to VS or leave
open for normal user mode operation.
•
VBSENSE: connect to VS in case that Fast Battery Voltage Monitoring and Boost deactivation features are
not used and keep them disabled.
•
•
•
VEXT: See Chapter 7.5.
n.c.: leave open.
Unused pins routed to an external connector which leaves the ECU should feature a zero ohm jumper
(depopulated if unused) or ESD protection.
Datasheet
11
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Voltages
Supply Voltage VS and
VEXTIN pin
VS1, max
VS2, max
-0.3
-0.3
–
–
–
–
28
40
28
40
V
V
V
V
–
P_4.1.1
P_4.1.2
P_4.1.3
P_4.1.4
Supply Voltage VS and
VEXTIN pin
Load Dump,
max. 400 ms
Boost drain Voltage BSTD
pin
VBSTD2, max -0.3
VBSTD2, max -0.3
VBCKSW, max -0.3
–
Boost drain Voltage BSTD
pin
Load Dump,
max. 400 ms
Buck switch BCKSW pin
–
–
VS + 0.3
5.5
V
V
–
–
P_4.1.8
P_4.1.9
Buck Regulator feedback,
pin VCC1
VCC1, max
-0.3
External Voltage Regulator VEXTREF, max -0.3
(VEXTREF)
–
–
28
V
V
VEXTREF = 40 V for P_4.1.26
Load Dump,
max. 400 ms
External Voltage Regulator VEXTB, max -0.3
(VEXTB)
VEXTIN
+ 10
VEXTB = 40 V for
Load Dump,
max. 400 ms
P_4.1.27
External Voltage Regulator VEXTSH, max VEXTIN
–
–
VEXTIN
+ 0.3
V
V
–
P_4.1.11
P_4.1.12
(VEXTSH)
- 0.3
Battery Voltage Monitoring VVBSENSE, -18
40
–
max
Wake Input
VWK, max
VHV, max
-0.3
-0.3
–
–
–
40
40
5.5
V
V
V
–
–
–
P_4.1.13
P_4.1.14
P_4.1.15
Fail Pins FO/TEST
Interrupt/Configuration Pin VINTN, max -0.3
INTN
Configuration Pin PCFG
Configuration Pin VIO
CANH, CANL
VPCFG, max -0.3
–
–
–
–
–
–
40
V
V
V
V
V
V
–
–
–
–
–
–
P_4.1.25
P_4.1.28
P_4.1.16
P_4.1.17
P_4.1.18
P_4.1.30
VVIO, max
VBUS, max
-0.3
-40
5.5
40
Digital Input / Output pin’s VIO, max
VCAN Input Voltage
-0.3
5.5
5.5
10
VVCAN, max -0.3
Maximum Differential CAN VCAN_DIFF, -5
Bus Voltage
max
Datasheet
12
Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
General Product Characteristics
Table 1
Absolute Maximum Ratings1) (cont’d)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Temperatures
Junction Temperature
Storage Temperature
ESD Susceptibility
ESD Resistivity to GND
Tj
-40
-55
–
–
150
150
°C
°C
–
P_4.1.19
P_4.1.20
Tstg
–
VESD
VESD
-2
-8
–
–
2
8
kV
kV
HBM2)
HBM2)3)
P_4.1.21
P_4.1.22
ESD Resistivity to GND,
CANH, CANL
ESD Resistivity to GND
VESD
-500
–
–
500
750
V
V
CDM4)
CDM4)
P_4.1.23
P_4.1.24
ESD Resistivity Pin 1,
12,13,24,25,36,37,48 (corner
pins) to GND
VESD1,12,13,2 -750
4,25,36,37,48
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF).
3) ESD “GUN” Resistivity with ±6 KV (according to IEC61000-4-2 “GUN test” (300 Ω, 150 pF)) it is shown in Application
Information and test will be provided from IBEE institute.
4) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1, usually not tested but rather
ESD SDM.
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Datasheet
13
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
1)
Supply Voltage
VS,func
VPOR
28
V
V
seesection P_4.2.1
POR
Chapter 12.12
CANx Supply Voltage
SPI frequency
VCAN
fSPI
4.75
–
–
–
5.25
4
V
–
P_4.2.2
P_4.2.3
MHz see
Chapter 13.7 for
fSPI,max
Junction Temperature
Tj
-40
–
150
°C
–
P_4.2.4
1) Including Power-On Reset, Over- and Undervoltage Protection.
Note:
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
Device Behavior Outside of Specified Functional Range:
•
28 V < VS,func < 40 V: Device will still be functional; the specified electrical characteristics might not be
ensured anymore. The absolute maximum ratings are not violated. However, a thermal shutdown might
occur due to high power dissipation.
•
•
•
VCAN < 4.75 V: The undervoltage bit VCAN_UV will be set in the SPI register BUS_STAT_0 and the transmitter
will be disabled as long as the UV condition is present.
5.25 V < VCAN < 5.5 V: CANx transceiver still functional. However, the communication might fail due to out-
of-spec operation.
V
POR,f < VS < 5.5 V: Device will be still functional; the specified electrical characteristics might not be ensured
anymore:
–
–
The voltage regulators will enter the low-drop operation mode.
VIO_UV reset could be triggered depending on the VRTx settings.
Datasheet
14
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
General Product Characteristics
4.3
Thermal Resistance
Table 3
Thermal Resistance1)
Symbol
Parameter
Values
Typ.
7
Unit Note or
Test Condition
Number
Min.
Max.
Junction to Soldering Point RthJSP
Junction to Ambient RthJA
–
–
–
–
K/W Exposed Pad
P_4.3.1
P_4.3.2
2)
33
K/W
1) Not subject to production test, specified by design.
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for 1.5 W. Board: 76.2 × 114.3 × 1.5 mm3
with 2 inner copper layers (35 µm thick), with thermal via array under the exposed pad . Top and bottom layers are
70 µm thick.
4.4
Current Consumption
Table 4
Current Consumption
Current consumption values are specified at Tj = 25°C, VS = 13.5 V, all outputs open
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
SBC Normal Mode
Normal Mode current
consumption
INormal
–
10
16
mA
VS = 5.5 V to 28 V;
Tj = -40°C to +150°C;
BOOST/VEXT/CANx=
OFF
P_4.4.1
SBC Stop Mode
Stop Mode current
Consumption
IStop,25
–
–
55
70
µA
1) Buck in PFM
P_4.4.2
P_4.4.3
BOOST/VEXT = OFF;
No load on VCC1
VBSENSE_EN = 0B
CANx/WK not wake
capable
Watchdog = OFF
2) Tj = 85°C;
Stop Mode current
IStop,85
95
–
µA
Consumption, Tj = 85°C
Buck in PFM
BOOST/VEXT = OFF;
No load on VCC1
VBSENSE_EN = 0B
CANx/WK not wake
capable
Watchdog = OFF
SBC Sleep Mode
Sleep Mode current
consumption
ISleep,25
–
30
50
µA
BOOST/VEXT = OFF; P_4.4.4
VBSENSE_EN = 0B
CANx/WK not wake
capable
Datasheet
15
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
General Product Characteristics
Table 4
Current Consumption (cont’d)
Current consumption values are specified at Tj = 25°C, VS = 13.5 V, all outputs open
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
65
Unit Note or
Test Condition
Number
Min.
Max.
Sleep Mode current
ISleep,85
–
–
µA
2) Tj = 85°C;
P_4.4.5
consumption, Tj = 85°C
BOOST/VEXT = OFF;
VBSENSE_EN = 0B
CANx/WK not wake
capable
Feature Incremental Current Consumption
Current consumption per
CAN module, recessive state
ICAN,rec
–
2
3
3
mA
mA
SBC Normal Mode; P_4.4.6
CAN Normal Mode;
V
V
CAN = 5 V;
TXDCAN = VIO;
no RL on CANx
2) SBC Normal Mode; P_4.4.7
CAN Normal Mode;
Current consumption per
CAN module, dominant
state
ICAN,dom
–
4.5
V
V
CAN = 5 V;
TXDCAN= GND;
no RL on CANx
Current consumption per
CAN module, Receive Only
Mode, SBC Normal Mode
ICAN,RcvOnly,N
–
–
–
0.4
1
0.6
1.4
790
mA
mA
µA
2) CAN Receive Only P_4.4.8
Mode; VCAN = 5 V;
M
V
TXDCAN = VIO;
no RL on CANx
Current consumption per
CAN module, Receive Only
Mode, SBC Stop Mode
ICAN,RcvOnly,St
2) CAN Receive Only P_4.4.25
Mode; VCAN = 5 V;
VTXDCAN = VIO;
M
no RL on CANx
2)3)4)
Currentconsumptionduring ICAN,SWK,25
CAN Partial Networking
frame detect mode for one
CAN module
700
Tj = 25°C;
VEXT = OFF;
P_4.4.9
WK not wake
capable;
CAN SWK wake
capable, SWK
Receiver enabled,
WUF detect;
no RL on CANx
Currentconsumptionduring ICAN,SWK,85
CAN Partial Networking
frame detect mode for one
CAN module
–
750
830
µA
2)3)4) Tj = 85°C;
VEXT= OFF;
WK not wake
capable;
P_4.4.10
CAN SWK wake
capable, SWK
Receiver enabled,
WUF detect;
no RL on CANx
Datasheet
16
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
General Product Characteristics
Table 4
Current Consumption (cont’d)
Current consumption values are specified at Tj = 25°C, VS = 13.5 V, all outputs open
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
250
Unit Note or
Test Condition
Number
Min.
Max.
Currentconsumptionduring ICAN,SWK2,25
CAN Partial Networking
frame detect mode per
–
300
µA
2) Tj = 25°C; SBC Stop P_4.4.22
Mode; VEXT = OFF;
WK not wake
additional CAN module
capable;
CAN SWK wake
capable, WUF
detect;
no RL on CANx
Current consumption for WK IWake,WK,25
wake capability
–
–
0.5
2.0
1.5
4.0
µA
µA
4)5) SBC Sleep Mode; P_4.4.11
CANx = OFF
2)4)5) SBCSleep Mode; P_4.4.12
Tj = 85°C;
Current consumption for WK IWake,WK,85
wake capability Tj = 85°C
CANx = OFF
Current consumption for
CAN wake capability
IWake,CAN,25
–
–
4.5
6
6
µA
µA
1)4) SBC Sleep Mode; P_4.4.13
WK = OFF
tSILENCE expired
Current consumption for
CAN wake capability
IWake,CAN,85
10
1)2)4) SBCSleep Mode; P_4.4.14
Tj = 85°C;
WK = OFF
t
SILENCE expired
Current consumption for
VEXT in SBC Sleep Mode
ISleep,VEXT,25
–
–
45
55
60
70
µA
µA
4) SBC Sleep Mode;
VEXT = ON (no load);
CANx / WK = OFF
P_4.4.15
Current consumption for
VEXT in SBC Sleep Mode,
Tj = 85°C
ISleep,VEXT,85
2)4) SBC Sleep Mode; P_4.4.16
Tj = 85°C; VEXT = ON
(no load);
CANx / WK = OFF
Current consumption for
cyclic wake function
IStop,C25
IStop,C85
–
–
20
24
26
35
µA
µA
4)6) SBC Stop Mode; P_4.4.17
WD = OFF
2)4)6) SBC Stop Mode; P_4.4.18
Tj = 85°C;
Current consumption for
cyclic wake function,
Tj = 85°C
WD = OFF
Current consumption for
watchdog active in Stop
Mode
IStop,WD25
IStop,WD85
IStop,FO
–
–
–
20
24
0.5
26
35
1.5
µA
µA
mA
2) SBC Stop Mode;
Watchdog running
P_4.4.19
P_4.4.20
P_4.4.21
Current consumption for
watchdog active in Stop
Mode
2) SBC Stop Mode;
Tj = 85°C;
Watchdog running
2) All SBC Modes;
Tj = 25°C;
Current consumption for
active fail output (FO)
FO = ON (no load);
Datasheet
17
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
General Product Characteristics
Table 4
Current Consumption (cont’d)
Current consumption values are specified at Tj = 25°C, VS = 13.5 V, all outputs open
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
5
Unit Note or
Test Condition
Number
Min.
Max.
Current consumption Fast IStop,FBM
Battery Monitoring in SBC
Stop Mode
–
–
µA
2) SBC Stop Modes; P_4.4.30
VBSENSE_EN = 1B
Tj = 25°C;
Additional VS current
consumption with Boost
Module Active
IBOOST,ON
–
10
20
mA
2) SBC Normal / Stop P_4.4.31
Modes;
V
BSTx < VS< VBST,thx
BOOST_EN = 1B;
1) Current consumption for CANx transceiver and WK input to be added if set to be wake capable or receiver only.
2) Not subject to production test, specified by design.
3) Current consumption adder applies during WUF detection (frame detect mode) when CAN Partial Networking is
activated. The current consumption will be reduced per module when multiple CAN transceivers are activated for
SWK.
4) Current consumption adders of features defined for SBC Sleep Mode also apply for SBC Stop Mode and vice versa
(unless otherwise specified).
5) No pull-up or pull-down configuration selected.
6) Cyclic wake configuration: Timer with 20 ms period.
Datasheet
18
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
System Features
5
System Features
This chapter describes the system features and behavior of the TLE9278-3BQX:
•
•
•
•
•
State machine and SBC mode control.
Device configurations.
State of supply and peripherals.
Wake features.
Supervision and diagnosis functions.
The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in
Chapter 13. The configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the TLE9278-
3BQX is compatible to other devices of TLE926x and TLE927x family.
The System Basis Chip (SBC) offers six operating modes:
•
•
•
•
•
SBC Init Mode: power-up of the device and after soft reset.
SBC Normal Mode: the main operating mode of the device.
SBC Stop Mode: the first-level power saving mode with the main voltage regulator enabled.
SBC Sleep Mode: the second-level power saving mode with Buck regulator disable.
SBC Restart Mode: an intermediate mode after a wake event from SBC Sleep or SBC Fail-Safe Mode or after
a failure (e.g. WD failure in config 1/3) to bring the microcontroller into a defined state via a reset. Once the
failure condition is not present anymore, the device will automatically change to SBC Normal Mode after a
delay time (tRD1).
•
SBC Fail-Safe Mode: a safe-state mode after critical failures (e.g. TSD2 thermal shutdown) to bring the
system into a safe state and to ensure a proper restart of the system. Buck regulator is disabled.
A special mode called SBC Development Mode is available during software development or debugging of the
system. All of the operating modes mentioned above can be accessed in this mode. However, the watchdog
counter is stopped and does not need to be triggered. This mode can be accessed by setting the TEST pin to
GND during SBC Init Mode.
5.1
State Machine Description and SBC Mode Control
The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register
M_S_CTRL.
The SBC MODE bits are cleared when going trough SBC Restart Mode, so the current SBC mode is always
shown.
Figure 3Figure 4 shows the SBC State Diagram.
Datasheet
19
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
System Features
First battery connection
SBC Soft Reset
Config.: settings can be configured in
this SBC mode;
SBC Init Mode
*
(Long open window )
VEXT(2) def.
by PCFG pin
Boost
OFF
Fixed: settings stay as defined in
SBC Normal Mode
VCC1
ON (2)
FO
CAN WD
Cyc.Wake
OFF
inact. OFF (3) Config.
*
The SBC Development Mode is a
super set of state machine where the
WD timer is stopped and CANx
Any SPI
command
behavior differs in SBC Init Mode.
Otherwise, there are no differences in
behavior (see also Chapter 5.1.7).
(1) After Fail-Safe Mode entry , the device will stay for at least
typ. 1s in this mode (with RO low) after a TSD2 event and min.
typ. 100ms after other Fail -Safe Events. Only then the device
can leave the mode via a wake-up event. Wake events are
stored during this time.
SBC Normal Mode
VCC1 (2) VEXT(2) def.
Boost(6)
ON
by PCFG pin conf./OFF
(2) The behaviour depends of the PCFG configuration . If PCFG
is open, the VEXT is by default off and it can be acivated from
the µC with one of the four configurable output voltages . If
PCFG = GND, the VEXT follows the VCC1 in the state machine
with fixed output voltage value at 3.3V.
WD trigger
FO
CAN
WD
Cyc.Wake
config.
act/inact Config.(3) Config.
(3) For SBC Development Mode CAN is in Normal Mode in
SBC Init Mode and will stay ON when going from there to SBC
Normal Mode
Automatic
SPI cmd
(4) See chapter CAN for detailed behavior in SBC Restart Mode
(5) CAN transceiver can be SWK capable , depending on
configuration
§
§
Reset is released
WD starts with long open window
SPI cmd
SPI cmd
(6) The Boost regulator activation depends from the VS value.
SBC Sleep Mode
SBC Stop Mode
VCC1
OFF
VEXT(2) def.
by PCFG pin
Boost
OFF
VCC1 (2) VEXT(2) def.
Boost(6)
ON
by PCFG pin fixed/OFF
VIO over voltage
Config 1/3 (if VIO_OV_RST set)
CAN (5)
CAN (5)
fixed
FO
fixed
WD
Cyc.Wake
OFF
FO
fixed
WD
fixed
Cyc.Wake
fixed
Wake
OFF
cap./OFF
SBC Restart Mode
(RO pin is asserted)
Wake up event
via CANx or WK
Watchdog Failure :
Config 1/3 (MAX_3_RST not set)
& 1st WD failure in Config4
4th consecutive VIO
under voltage event
(if VS > VS_UV_TO)
VCC1 (2) VEXT(2) def.
Boost(6)
fixed/OFF
VIO over voltage
Config 2/4 (if VIO_OV_RST set)
ON
by PCFG pin
VIO Undervoltage
CAN (4)
FO
active/
fixed
WD
OFF
Cyc.Wake
OFF
Woken /
OFF
TSD2 event
SBC Fail-Safe Mode (1)
1st Watchdog Failure Config 2,
2nd Watchdog Failure , Config 4
VCC1
OFF
VEXT
OFF
Boost
OFF
CAN
VIO Short to GND
FO
fixed
WD
OFF
Cyc.Wake
OFF
Wake
capable
CANx, WK wake-up event
Figure 3
State Diagram showing the SBC Operating Modes
Datasheet
20
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
System Features
First battery connection
SBC Soft Reset
Config.: settings can be configured in
this SBC mode;
SBC Init Mode
*
(Long open window )
VEXT(2) def.
by PCFG pin
Boost
OFF
Fixed: settings stay as defined in
SBC Normal Mode
VCC1
ON (2)
FO
CAN WD
Cyc.Wake
OFF
inact. OFF (3) Config.
*
The SBC Development Mode is a
super set of state machine where the
WD timer is stopped and CANx
Any SPI
command
behavior differs in SBC Init Mode.
Otherwise, there are no differences in
behavior (see also Chapter 5.1.7).
SBC Normal Mode
(1) After Fail-Safe Mode entry , the device will stay for at least
typ. 1s in this mode (with RO low) after a TSD2 event and min.
typ. 100ms after other Fail -Safe Events. Only then the device
can leave the mode via a wake-up event. Wake events are
stored during this time.
VCC1 (2) VEXT(2) def.
Boost(5)
ON
by PCFG pin conf./OFF
WD trigger
(2) The behaviour depends of the PCFG configuration . If PCFG
is open, the VEXT is by default off and it can be acivated from
the µC with one of the four configurable output voltages . If
PCFG = GND, the VEXT follows the VCC1 in the state machine
with fixed output voltage value at 3.3V.
FO
CAN
WD
Cyc.Wake
config.
act/inact Config.(3) Config.
(3) For SBC Development Mode CAN is in Normal Mode in
SBC Init Mode and will stay ON when going from there to SBC
Normal Mode
Automatic
SPI cmd
§
§
Reset is released
WD starts with long open window
(4) See chapter CAN for detailed behavior in SBC Restart Mode
(5) The Boost regulator activation depends from the VS value.
SPI cmd
SPI cmd
SBC Sleep Mode
SBC Stop Mode
VCC1
OFF
VEXT(2) def.
by PCFG pin
Boost
OFF
VCC1 (2) VEXT(2) def.
Boost(5)
ON
by PCFG pin fixed/OFF
VIO over voltage
Config 1/3 (if VIO_OV_RST set)
CAN
Wake
cap./OFF
FO
fixed
WD
OFF
Cyc.Wake
OFF
FO
fixed
WD
fixed
Cyc.Wake
fixed
CAN
fixed
SBC Restart Mode
(RO pin is asserted)
Wake up event
via CANx or WK
Watchdog Failure :
Config 1/3 (MAX_3_RST not set)
& 1st WD failure in Config4
4th consecutive VIO
under voltage event
(if VS > VS_UV_TO)
VCC1 (2) VEXT(2) def.
Boost(5)
fixed/OFF
VIO over voltage
Config 2/4 (if VIO_OV_RST set)
ON
by PCFG pin
VIO Undervoltage
CAN (4)
FO
active/
fixed
WD
OFF
Cyc.Wake
OFF
Woken /
OFF
TSD2 event
SBC Fail-Safe Mode (1)
1st Watchdog Failure Config 2,
2nd Watchdog Failure , Config 4
VCC1
OFF
VEXT
OFF
Boost
OFF
CAN
VIO Short to GND
FO
fixed
WD
OFF
Cyc.Wake
OFF
Wake
capable
CANx, WK wake-up event
Figure 4
State Diagram showing the SBC Operating Modes
Datasheet
21
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
System Features
5.1.1
Device Configuration and SBC Init Mode
The SBC Init Mode is the mode where the hardware configuration of the SBC is stored and where the
microcontroller finishes the initialization phase.
The SBC starts up in SBC Init Mode after crossing the power-on reset VPOR,r threshold (see also Chapter 12.3)
and the watchdog will start with a long open window (tLW typical 200ms) after the RSTN is released.
During this power-on phase following configurations are stored in the device:
•
•
Supply and Power up configurability.
The device behavior regarding a watchdog trigger failure and a VIO overvoltage condition is determined by
the external circuitry on the INTN pin (see below).
•
The selection of the normal device operation or the SBC Development Mode (watchdog disabled for
debugging purposes) will be set depending on the voltage level of the FO/TEST pin (see also
Chapter 5.1.7).
5.1.1.1 Supply and Power up configurability
The TLE9278-3BQX has the possibility to define the level of the digital IO’s using a dedicated pin (VIO). A
separate pin (PCFG) is available to store the I/O supply voltage configuration during power-up. The respective
configuration will be stored for all conditions and can only be changed by powering down the device (VS <
VPOR,f).
Depending of the configuration, the supervision functions can refer to VCC1 or VEXT.
The Table 5 shows the only allowed combinations and related behavior.
Table 5
Supply and power up Configurability
VCC1
Output
Voltage
PCFG pin
VIO Supply µC Supply VEXT
VEXT
Supervision
Functions
Output voltage Behavior
V
CC1 = 5 V
Open
VCC1
VEXT
VCC1
VEXT
Configurable via SPI
Supervision
functions on VIO
SPI using
configurable,
VEXT_VCFG
OFF after Power with 5 V level;
Up
VREG_UV SPI
status bit active
VCC1 = 5 V
GND
VEXT = 3.3 V
Follow the VCC1 Supervision
(fixed)
(ON at Power up functions on VIO
/SBC Normal /
Stop / Sleep /
with 3.3 V level;
VREG_UV status
Fails-Safe Mode) not active but
reroutedtoVCC1
Note:
VIO can be connected only to VCC1 or VEXT.
5.1.1.2 Watchdog trigger failure configuration
There are four different device configurations (Table 6) available defining the watchdog failure and the VIO
overvoltage behavior. The configurations can be selected via the external connection on the INTN pin and the
SPI bit CFG2 in the HW_CTRL_0 register (see also Chapter 13.4):
•
A watchdog trigger failures leads to SBC Restart Mode (Config 1/3) and depending on CFG2 the Fail Output
(FO) are activated after the 1st or 2nd watchdog trigger failure;
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Multi-CAN Power+ System Basis Chip
System Features
If VIO_OV_RST is set and in Config 1/3, then SBC Restart Mode will be entered in case of VIO_OV and the
FO is activated.
•
A watchdog trigger failures leads to SBC Fail-Safe Mode (Config 2/4) and depending on CFG2 the Fail
Output (FO) are activated after the 1st or 2nd watchdog trigger failure. The first watchdog trigger failure in
Config 4 will lead to SBC Restart Mode;
If VIO_OV_RST is set and in Config 2/4, then SBC Fail-Safe Mode will be entered in case of VIO_OV and the
FO is activated.
The respective device configuration can be identified by reading the SPI bits CFG2_STATE and CFG1_STATE
in the WK_LVL_STAT register.
Table 6
Watchdog Trigger Failure Configuration
FO Activation SBC Mode Entry
Config Event
SPI Bit CFG2 INTN Pin
(CFG1_STATE)
1
2
3
4
1 × Watchdog Failure after 1st WD Failure SBC Restart Mode
1 × Watchdog Failure after 1st WD Failure SBC Fail-Safe Mode
2 × Watchdog Failure after 2nd WD Failure SBC Restart Mode
2 × Watchdog Failure after 2nd WD Failure SBC Fail-Safe Mode
1
1
0
0
External pull-up
No ext. pull-up
External pull-up
No ext. pull-up
The respective configuration will be stored for all conditions and can only be changed by powering down the
device (VS < VPOR,f).
Table 7 shows the possible SBC hardware configurations.
Table 7
SBC Configuration
Configuration Description
FO/Test
Pin
INTN Pin CFG2_STA CFG1_STA
(CFG1_ST TE
ATE)
TE
Config 0
Config 1
SBC Development Mode: no reset is
triggered in case of watchdog trigger
failure. After the Power Up, one
0
-
X
X
arbitrary SPI command must be sent.
After missing the WD trigger for the first Open or
External
pull-up to
VIO
1
1
time, the state of VCC1 remains
unchanged, FO pin is active, SBC in
Restart Mode
>VTEST,H
Config 2
Config 3
After missing the WD trigger for the first Open or
time,VCC1 turns OFF, FO pin are active, >VTEST,H
SBC in Fail-Safe mode
Open or
GND
1
0
0
1
After missing the WD trigger for the
Open or
External
pull-up to
VIO
second time, the state of VCC1 remains >VTEST,H
unchanged, FO pin is active, SBC in
Restart Mode
Config 4
After missing the WD trigger for the
second time,VCC1 turns OFF, FO pin is >VTEST,H
Open or
Open or
GND
0
0
active, SBC in Fail-Safe mode
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Multi-CAN Power+ System Basis Chip
System Features
In case of 3 consecutive resets due to WD fail, it is possible in Config 1 and 3 not to generate additional reset
by setting the MAX_3_RST on WD_CTRL.
Figure 5 shows the timing diagram of the hardware configuration selection. The hardware configuration is
defined during SBC Init Mode. The INTN pin is internally pulled LOW with a weak pull-down resistor during the
reset delay time tRD1, i.e. after VIO crosses the reset threshold VRT1 and before the RSTN pin goes HIGH. The
INTN pin is monitored during this time and the configuration (depending on the voltage level at INTN) is read
and stored at the rising edge of RSTN (with a filter time of tCFG_F).
VS
VPOR,r
t
VIO
VRT1,r
t
RSTN
tCFG_F
Config Select filter time
t
tRD1
Configuration selection monitoring period
Figure 5
Hardware Selection Timing Diagram
Note:
If the POR bit is not cleared then the internal pull-down resistor will be reactivated every time RSTN
is pulled LOW the configuration will be updated at the rising edge of RSTN. Therefore it is
recommended to clear the POR bit right after initialization.
5.1.1.3 SBC Init Mode
In SBC Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. In
the SBC Init Mode any SPI command will bring the SBC to SBC Normal Mode. During the long open window
the watchdog has to be triggered. Thereby the watchdog will be automatically configured. A missing
watchdog trigger during the long open window will cause a watchdog failure and the device will enter SBC
Restart Mode.
Wake events are ignored during SBC Init Mode and will therefore be lost.
Note:
Note:
Any SPI command will bring the SBC to SBC Normal Mode even if non-valid (see Chapter 13.2).
For a safe start-up, it is recommended to use the first SPI command to trigger and to configure the
watchdog (see Chapter 12.2).
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Multi-CAN Power+ System Basis Chip
System Features
Note:
At power up, no VIO_UV will be issued nor will FO be triggered as long as VIO is below the VRT1
threshold and VS is below the VIO short circuit detection threshold VS,UV. The RSTN pin will be kept
low as long as VIO is below the selected VRT1 threshold. As soon as the VIO is higher than VRT1, the
RSTN is released after tRD1
.
5.1.2
SBC Normal Mode
The SBC Normal Mode is the standard operating Mode for the SBC. All configurations have to be done in SBC
Normal Mode before entering a low-power mode (see also Chapter 5.1.6 for the device configuration defining
the Fail-Safe Mode behavior). A wake-up event on CANx and WK will create an interrupt on pin INTN however,
no change of SBC Mode will occur. The configuration options are listed below:
•
•
•
VCC1 is active, Buck in PWM Mode.
VEXT can be switched ON or OFF in accordance with Table 5.
CANx is configurable (OFF coming from SBC Init Mode; OFF or wake capable coming from SBC Restart
Mode, see also Chapter 5.1.5).
•
•
•
•
Wake pin level can be monitored and can be selected to be wake capable.
Cyclic wake period can be configured using TIMER_CTRL_0 and enabled by setting TIMER1_WK_ EN.
Watchdog is configurable.
FO is OFF by default.
In SBC Normal Mode, there is the possibility of testing the FO output, i.e. to verify if setting the FO pin to low
will create the intended behavior within the system. The FO output can be enabled and then disabled again
by the microcontroller by setting the FO_ON SPI bit. This feature is only intended for testing purposes.
5.1.3
SBC Stop Mode
The SBC Stop Mode is the first level technique to reduce the overall current consumption. All kind of settings
have to be done before entering SBC Stop Mode. In SBC Stop Mode any kind of SPI write commands are
ignored and the SPI_FAIL bit is set, except for changing to SBC Normal Mode, triggering a SBC Soft Reset,
refreshing the watchdog, changing modulation of the buck. The configuration options are listed below:
•
•
•
•
•
•
VCC1 is ON, Buck in PFM Mode if IVCC1 < IPFM-PWM,TH.
VEXT is fixed ON or OFF in accordance with Table 5 and SPI configuration.
CANx can be selected for ‘Receive Only Mode’, to be wake capable or OFF.
WK pin can be selected to be wake capable, PWM_BY_WK (switch PFM/PWM buck modulation) or OFF.
Wake capability via cyclic wake can be selected.
Watchdog is fixed or OFF (if WD disable sequence was executed).
A wake-up event on CANx and WK will create an interrupt on pin INTN however, no change of SBC Mode will
occur.
In SBC Stop Mode, it is allowed to use the Boost module (enabled before to enter in SBC Stop Mode) in case of
the VS is dropping. The Boost works only in PWM and therefore the total amount of current consumption will
increase.
Note:
It is not possible to switch directly from SBC Stop Mode to SBC Sleep Mode. Doing so will also set the
SPI_FAIL flag and will bring the SBC into Normal Mode via SBC Restart Mode.
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Multi-CAN Power+ System Basis Chip
System Features
5.1.4
SBC Sleep Mode
The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum
needed to react on wake-up events.
All settings must be done before entering SBC Sleep Mode. In case that SPI configurations in Sleep Mode have
been sent to the SBC, the commands are ignored and no reactions from the SBC.
The configuration options are listed below:
•
•
•
•
VCC1 is OFF.
VEXT is fixed ON or OFF in accordance with Table 5 and SPI configuration.
CANx can be selected to be wake capable or OFF.
WK pin can be selected to be wake capable or OFF.
A wake-up event on CANx or WK pin will bring the device via SBC Restart Mode into SBC Normal Mode again
and signal the wake event and corresponding sources.
It is not possible to switch off all wake sources in Sleep Mode. This will lead to SBC Normal Mode via SBC
Restart Mode instead.
In order to enter SBC Sleep Mode successfully, all wake source signalization flags from WK_STAT_0 and
WK_STAT_2 need to be cleared. If a failure to do so, will result in an immediate wake-up from SBC Sleep Mode
by going via SBC Restart to Normal Mode.
Note:
As soon as the Sleep Command is sent, the Reset will go low to avoid any undefined behavior
between SBC and microcontroller.
5.1.5
SBC Restart Mode
There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the
microcontroller:
•
From SBC Normal and Stop Mode, it is reached in case of undervoltage on VIO. In case of 4 consecutive
VIO_UV events, SBC Fail-Safe Mode is entered.
•
From SBC Normal and Stop Mode it is reached in case of overvoltage on VIO in config 1/3 if VIO_OV_RST is
set.
•
•
Incorrect Watchdog triggering (depending of the configuration).
From SBC Sleep and Fail-Safe Mode to ramp up VIO supply after wake event.
From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode, i.e the mode is left automatically
by the SBC without any microcontroller influence once the VIO_UV condition is not present anymore and
when the reset delay time (tRD1) has expired. The Reset Output (RSTN) is released at the transition.
Entering or leaving the SBC Restart Mode will not result in deactivation of the Fail output.
The following functions are not changed in SBC Restart mode:
•
•
•
VEXT is fixed ON or OFF in accordance with Table 5 and SPI configuration.
VCC1 is ON or ramping up.
BOOST is fixed or OFF.
Table 8 contains detailed descriptions of the reason to restart:
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Multi-CAN Power+ System Basis Chip
System Features
Table 8
Reasons for Restart - State of SPI Status Bits after Return to Normal Mode
SBC Mode
Normal
Event
DEV_STAT WD_FAIL
VIO_UV
VIO_OV
Watchdog Failure
VIO undervoltage reset
01
01
01
xx
xx
xx
01
xx
xx
x
1
x
x
x
1
x
x
x
1
x
x
x
1
Normal
Normal
VIO overvoltage (VIO_OV_RST=1) 01
Sleep Mode
Stop Mode
Stop Mode
Stop Mode
Fail-Safe
Wake-up event
10
01
01
Watchdog Failure
VIO undervoltage reset
VIO overvoltage (VIO_OV_RST=1) 01
Wake-up event
01
see “Reasons for Fail-Safe, Table 9”
5.1.6
SBC Fail-Safe Mode
The purpose of this mode is to bring the system in a safe status after a failure condition by turning off the VCC1
and VEXT supply and the FO pin is automatically activated. After a wake-up event the system is then able to
restart again.
The Fail-Safe Mode is automatically reached in case of:
•
•
•
•
•
•
Overtemperature condition (TSD2).
After 1 or 2 watchdog fails (depending on config setting).
At the 4th consecutive VIO undervoltage event.
From SBC Normal and Stop Mode, in case of overvoltage on VIO in config 2/4, if VIO_OV_RST is set.
VIO is shorted to GND.
VIO is below the VRTx for time longer than tVIO,SC
.
In this case, the default wake sources are activated, the wake-up events are cleared in the register WK_STAT_0
and WK_STAT_2.
The mode will be maintained for at least tTSD2 in case of TSD2 event and tFS,min in case of other failure events
to avoid any fast toggling behavior. All wake sources will be masked during this time but the wake-up events
will be stored. Stored wake-up events and wake-up event after this minimum waiting time, will lead to SBC
Restart Mode. Leaving the SBC Fail-Safe Mode will not result in deactivation of the Fail Output pin.
The following functions are influenced during SBC Fail-Safe Mode:
•
•
•
•
•
•
FO output is activated.
VCC1 is OFF.
VEXT is OFF.
CANx is wake capable.
WK is wake capable (in case that PWM_BY_WK was set, moving to SBC Fail-Safe Mode will clear the bit).
Cyclic wake is disabled.
Table 9
Mode
Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode
Config Event DEV_STAT TSD2 WD_FAIL VIO_UV VIO_SC VIO_OV
Normal
2
1 × watchdog
01
x
01
x
0
x
failure
Normal
4
2 × watchdog
failure
01
x
10
x
0
x
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Multi-CAN Power+ System Basis Chip
System Features
Table 9
Mode
Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode (cont’d)
Config Event
DEV_STAT TSD2
WD_FAIL VIO_UV VIO_SC VIO_OV
Normal
Normal
Normal
1, 2, 3, 4 TSD2
01
01
01
1
x
x
xx
xx
xx
x
1
x
0
1
0
x
x
1
1, 2, 3, 4 VIO short to GND
2, 4
VIO overvoltage
(VIO_OV_RST=1,
CFG2=1)
Stop Mode
Stop Mode
2
4
1 × watchdog
failure
01
01
x
x
01
10
x
x
0
0
x
x
2 × watchdog
failure
Stop Mode 1, 2, 3, 4 TSD2
01
01
01
1
x
x
xx
xx
xx
x
1
x
0
1
0
x
x
1
Stop Mode 1, 2, 3, 4 VIO short to GND
Stop Mode 2, 4
VIO overvoltage
(VIO_OV_RST=1,
CFG2=1)
5.1.7
SBC Development Mode
The SBC Development Mode is used during development phase of the application, especially for software
development.
Compared to the default SBC user mode operation, this mode is a super set of the state machine. The device
will start also in SBC Init Mode and it is possible to use all the SBC Modes and functions with following
differences:
•
•
•
Watchdog is stopped and does not need to be triggered. Therefore no reset is triggered due to watchdog
failure.
SBC Fail-Safe and Restart Mode are not reached due to watchdog failure but the other reasons to enter
these modes are still valid.
CANx default value in SBC INIT MODE is ON instead of OFF.
The mode is reached by setting the FO/TEST pin to LOW for the entire SBC INIT Mode and by sending an
arbitrary SPI command. The SBC Init Mode is reachable after the power-up or sending a software reset.
SBC Development Mode can only be left by a power-down or by providing a SBC Software Reset using the
MODE bits on M_S_CTRL register regardless the FO/TEST pin level.
When the FO/TEST pin is left open, or connected to VS during the start-up, the SBC starts into normal
operation. The FO/TEST pin has an integrated pull-up resistor (switched ON only during SBC Init Mode) to
prevent the SBC device from starting in SBC Development Mode during normal life of the vehicle. To avoid any
disturbances, the FO/TEST pin is monitored during the SBC Init Mode when the RSTN is HIGH until SBC Init
Mode is left. Only if the FO/TEST pin is LOW for the Init Mode time when the RSTN is HIGH, SBC Development
Mode is reached and stored.
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Multi-CAN Power+ System Basis Chip
System Features
5.2
Wake Features
Following wake sources are implemented in the device:
•
•
•
Static Sense: WK input is permanently active (see Chapter 9).
Cyclic Wake: internal wake source controlled via internal timer (see Chapter 5.2.1).
CANx wake: wake-up via CAN message (see Chapter 8).
The wake source must be set before entering in SBC Sleep Mode. In case of critical situation, when the device
will be set into SBC Fail-Safe mode, all default wake sources will be activated. For additional information
about setting, refer to the respective chapters.
5.2.1
Cyclic Wake
The cyclic wake feature is intended to reduce the quiescent current of the device and application.
When the cyclic wake is enabled, a periodic INTN is generated in SBC Normal and Stop Mode based on the
setting of TIMER_CTRL_0.
The correct sequence to configure the cyclic wake is shown in Figure 6. The sequence is as follows:
•
Disable the cyclic wake feature to ensure that there is not unintentional interrupt when activating cyclic
wake (TIMER1_WK_ EN = 0).
•
•
Configure the cyclic wake timer period in TIMER_CTRL_0 register.
Enable the cyclic wake as a wake-up source in the register WK_CTRL_0 (TIMER1_WK_ EN = 1).
Cyclic Wake Configuration
Reset the TIMER1_WK_EN bit on
To avoid unintentional interrupts
WK_CTRL_0 register
Select Timer Period in
Periods: 10, 20, 50, 100, 200ms, 1s, 2s
TIMER_CTRL_0
No interrupt will be generated,
if the timer is not enabled as a wake source
Set the TIMER1_WK_EN bit on
WK_CTRL_0 register
Cyclic Wake starts / ends by
setting / clearing On-time
INT is pulled low at every rising edge
of On-time except first one
Figure 6
Cyclic Wake: Configuration and Sequence
5.2.2
Internal Timer
The integrated timer is typically used to wake up the microcontroller periodically (cyclic wake).
Following periods can be selected via the register TIMER_CTRL_0:
•
Period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s
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Multi-CAN Power+ System Basis Chip
5.3
CAN Partial Networking
5.3.1
CAN Partial Networking - Selective Wake Feature
The CAN Partial Networking feature can be activated for SBC Normal Mode, in SBC Sleep Mode and in SBC Stop
Mode. For SBC Sleep Mode the Partial Networking has to be activated before sending the SBC to Sleep Mode.
For SBC Stop Mode the Partial Networking has to be activated before going to SBC Stop Mode.
There are 2 detection mechanism available:
•
WUP (Wake-Up Pattern) this is a CAN wake, that reacts on the CAN dominant time, with 2 dominant signals
as defined in ISO WG11898-6.
•
WUF (Wake-Up frame) this is the wake-up on a CAN frame that matches the programmed message filter
configured in the SBC via SPI.
The default baud rate is set to 500 kBaud. Besides the commonly used baud rate of 125 kBaud and 250 kBaud,
other baud rate up to 1 MBaud can be selected (see Chapter 13.5.2 and Chapter 13.6.2 for more details).
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Multi-CAN Power+ System Basis Chip
5.3.2
SBC Partial Networking Function
The CAN Partial Networking Modes are shown in Figure 7.
CAN
OFF
SPI
SPI
CAN WK Mode
without PN
CAN Receive Only
Mode
CAN
Normal Mode
SPI
SPI
SPI
CAN PN
Config Check
Enable/ Disable
max. 4
CAN frames
CAN Wakable Mode
CAN Woken UP 1)
CAN Wake
WUP
CAN
WUF
CAN Wake
WUP
CAN
Wake detection
(WUP)
CAN WUF
detection
Sleep Mode: SBC goes to Restart Mode,
RxD is low, SPI bits are set
tsilence
Stop Mode: SBC stays in Stop Mode,
Interrupt is triggered, RxD is low, SPI bits
are set
Normal Mode: SBC stays in Normal Mode,
Interrupt is triggered, SPI bits are set, RxD
is low (only in case of CAN WK or SWK
Mode, not in Receive Only with SWK or
CAN Normal Mode with SWK)
CAN frame error
detection
CAN Protocoll Error
Counter
valid
N-1
not valid
N+
rearming
Tsilent
1) CFG_VAL is cleared in
Reastart Mode
N>0
Error counter
overvlow
N = 0
N = 0
N>32
SYSERR
CAN WUP
detection
SYSERR
Figure 7
CAN Selective Wake State Diagram
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5.3.2.1 Activation of SWK
Figure 8 shows the principal of the SWK activation.
SBC Normal Mode
SW not enabled
CAN OFF
Enabling CANx (not OFF) enables also
the selective wake block. Block gets
synchronous to the CAN bus .
If one CAN Frame is received the bit
SYNC_x = 1 is set
SYNC_x = 1
CANx
Enable CAN
Set SWK wake data. e.g.
ID, ID_Mask, DATA
Setting the data can also be done as
first task
Clear
the wake-up status
register related the
selected CANx
To avoid invalid configuration
Bit set to confirm by the microcontroller
that valid data are programmed .
Set
CFG_VAL = 1
Clear
SYSERR_x
To activate Selective Wake
In case SWK not enabled :
CANx Normal with SW -> CANx Normal
CANx Rx Only with SW -> CANx Rx Only
CANx Wakable with SW -> CANx Wakable
1
SYSERR_x
0
SWK not enabled
Handle wake
event
(incl. CAN
mode toggling )
Selective Wake is now enabled
Enable a CAN
Mode with SWK
via CANx Bits
(INTN is generated in case of WUF )
CAN Mode must be toggled before
(re-)enabling wake capable mode
SWK_SET_x = 1,
CAN_x_WUP & WUF_x = 0,
SYNC_x = 1
Check SWK_STAT_x
Check & Clear
the wake-up status
register related the
selected CANx
To ensure that no wake -up event
has taken place in meantime
MODE = 10
Select SBC
low-power mode
via MODE Bits
MODE = 01
SBC Sleep Mode
In case of WUF detection :
CAN_x_WU = 1; WUF_x = 1;
CFG_VAL = 0; SWK_SET_x = 0
SBC Stop Mode
INTN generation
Wake-up: VCC1 Power-up
change to SBC Normal Mode
stays in SBC Stop Mode
Notes:
- Tsilence handling not shown in drawing
- SYNC_x will only be set once CANx is „rearmed“
and at least one CAN frame was sent successfully
Figure 8
Flow for activation of SWK
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Multi-CAN Power+ System Basis Chip
5.3.2.2 Wake-up Pattern (WUP)
A WUP is signaled on the bus by two consecutive dominant bus levels for at least tWake1, each separated by a
recessive bus level.
Entering low-power mode,
when selective wake-up
function is disabled
or not supported
Bus recessive > tWAKE1
Ini
Wait
Bias off
Bias off
Bus dominant > tWAKE1
optional:
tWAKE2 expired
1
Bias off
Bus recessive > tWAKE1
optional:
tWAKE2 expired
2
Bias off
Bus dominant > tWAKE1
Silence expired AND
t
Entering CAN Normal
or CAN Recive Only
Device in low-power mode
3
Bias on
Bus dominant > tWAKE1
Bus recessive > tWAKE1
tSilence expired AND
device in low-power mode
4
Bias on
Figure 9
WUP detection following the definition in ISO 11898-5
5.3.2.3 Wake-up Frame (WUF)
The wake-up frame is defined in ISO11898-6.
Only CAN frames according ISO11898-1 are considered as potential wake-up frames.
A bus wake-up shall be performed, if selective wake-up function is enabled and a “valid WUF” has been
received. The transceiver may ignore up to four consecutive CAN data frames that start after switching on the
bias.
A received frame is a “valid WUF” in case all of the following conditions are met:
•
The ID of the received frame is exactly matching a configured ID in the relevant bit positions. The relevant
bit positions are given by an ID mask. The ID and the ID mask might have either 11 bits or 29 bits.
•
•
The DLC of the received frame is exactly matching the configured DLC.
In case DLC is greater than 0, the data field of the received frame has at least one bit set in a bit position,
where also in the configured data mask in the corresponding bit position the bit is set.
•
No error exists according to ISO 11898-1 excepting errors which are signalled in the ACK field and EOF field.
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Multi-CAN Power+ System Basis Chip
5.3.2.4 CAN Protocol Error Counter
The counter is incremented when a bit stuffing, CRC or form error according to ISO11898-1 is detected. If a
frame has been received that is valid up to the end of the CRC field and the counter is not zero, the counter is
decremented. If the counter has reached a value of 31, the following actions is performed on the next
increment of this counter:
•
•
•
The selective wake function is disabled.
The CANx transceiver is woken.
SYSERR_x is set and the error counter value = 32 can be read.
On each increment or decrement of the counter the decoder unit waits for at least 6 and most 10 recessive bits
before considering a dominant bit as new start of frame.
The error counter is enabled:
•
Whenever the CANx is in Normal Mode, Receive Only Mode or in WUF detection state.
The error counter is cleared under the following conditions:
•
At the transition from WUF detection to WUP detection 1 (after tSILENCE expiration, while SWK is correctly
enabled).
•
•
•
When WUF detection state is entered (in this way the counter will start from 0 when SWK is enabled).
At SBC or CANx rearming (when exiting the woken state).
When the CANx Mode bits are selected ‘000’, ‘100’ (CANx OFF) or ‘001’ (CANx Wake Capable without SWK
function enabled).
•
While CAN_FD_EN = ‘1’ and DIS_ERR_CNT = ‘1’ (the counter is cleared and stays cleared when these two
bits are set in the SPI registers).
The Error Counter us frozen:
After a wake-up being in woken state.
•
The counter value can be read out of the bits ECNT_x_0 to ECNT_x_5.
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Multi-CAN Power+ System Basis Chip
5.3.3
Diagnoses Flags
5.3.3.1 PWRON/RESET-FLAG
The power-on reset can be detected and read by the POR bit in the SBC Status register.
The VS power on resets all register in the SBC to reset value. SWK is not configured.
5.3.3.2 BUSERR-Flag
Bus Dominant Time-out detection is implemented and signaled by CAN_x_Fail bits in the status register
related the selected CAN transceiver (BUS_STAT_0 or BUS_STAT_2 or BUS_STAT_3).
5.3.3.3 TxD Dominant Time-out flag
TxD Dominant Time-out is shown in the SPI bit CAN_x_FAIL in register in the status register related the
selected CAN transceiver.
5.3.3.4 WUP_x Flag
The WUP_x bit in the SWK_STAT_x register shows that a Wake-Up Pattern (WUP) has caused a wake of the CAN
transceiver. It can also indicate an internal mode change from WUP detection to WUF detection after a valid
WUP.
In the following case the bit is set:
•
SWK is activated: due to tSILENCE, the CAN goes into WUP detection. If a WUP is detected in this state, then
the WUP_x bit is set.
•
•
SWK is deactivated: the WUP_x bit is set if a WUP wakes up the CAN. In addition, the CAN_x_WU bit is set.
In case WUP is detected during WUP detection 2 state (after a SYSERR_x) the bits WUP_x and CAN_x_WU
are set.
The WUP_x bit is cleared automatically by the SBC at the next rearming of the CAN transceiver.
Note:
It is possible that WUF and WUP bit are set at the same time if a WUF causes a wake out of SWK, by
setting the interrupt or by restart out of SBC Sleep Mode. The reason is because the CAN has been in
WUP detection mode during the time of SWK mode (because of tSILENCE). See also Figure 10.
5.3.3.5 WUF Flag (WUF_x)
The WUF_x bit in the SWK_STAT_x register shows that a Wake-Up frame (WUF) has caused a wake of the CANx
block. In SBC Sleep Mode this wake causes a restart, in SBC Normal Mode and in SBC Stop Mode it causes an
interrupt. Also in case of this wake the bit CAN_x_WU in the register WK_STAT_x is set.
The WUF_x bit is cleared automatically by the SBC at the next rearming of the CAN SWK function.
5.3.3.6 SYSERR Flag (SYSERR_x)
The bit SYSERR_x is set in case of an configuration error and in case of an error counter overflow. The bit is only
updated (set to 1) if a CANx mode with SWK is enabled via CANx bits.
When programming selective wake via CANx, SYSERR_x = 0 signals that the SWK function has been enabled.
The bit can be cleared via SPI. The bit is ‘0’ after Power on reset of the SBC.
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Multi-CAN Power+ System Basis Chip
5.3.3.7 Configuration Error
A configuration error sets the SYSERR_x bit to 1. When enabling SWK via the bits CANx a config check is done.
If the check is successful SWK is enabled, the bit SYSERR_x is set to 0. In SBC Normal Mode it is also possible to
detect a Configuration Error while SWK is enabled, this will happen if the CFG_VAL bit is cleared, e.g. by
changing the SWK register (from address 010 0001 to address 011 0011). In SBC Stop Mode and SBC Sleep
Mode this is not possible as the SWK registers can not be changed.
Configuration Check:
in SBC Restart Mode, the CFG_VAL bit is cleared by the SBC. If the SBC Restart Mode was not triggered by a
WUF wake up from SBC Sleep Mode and the CAN was with SWK enabled, than the SYSERR_x bit will be set.
The SYSERR_x bit has to be cleared by the microcontroller.
The SYSERR_x bit cannot be cleared when CANx_2 is ‘1’ and below conditions occur:
•
•
Data Valid bit not set by the microcontroller, e.g. CFG_VAL is not set to ‘1’. The CFG_VAL bit is reset after
SWK wake and needs to be set by the microcontroller before activation SWK again.
CFG_VAL bit reset by the SBC when data are changed via SPI programming. (Only possible in SBC Normal
Mode).
Note:
The SWK configuration is still valid if only the SWK_CTRL register is modified.
5.3.3.8 CAN BUS Time-out-Flag (CANTO_x)
In CAN WUF detection and CAN WUP detection 2 state, the bit CANTO_x is set to 1 if the time tSILENCE expires.
The bit can be cleared by the microcontroller. If the interrupt function for CANTO_x is enabled an Interrupt is
generated in SBC Stop and SBC Normal Mode when the CANTO_x set to 1. The interrupt is enabled by setting
the bit CANTO_MASK to 1. Each CANTO_x event will trigger a interrupt even if the CANTO_x bit is not cleared.
There is no wake out of SBC Sleep Mode because of CAN time-out.
5.3.3.9 CAN BUS Silence-Flag (CANSIL_x)
In CAN WUF detection and CAN WUP detection 2 state the bit CANSIL_x is set to ‘1’ if the time tSILENCE expires.
The CANSIL_x bit is set back to ‘0’ with a WUP. With this bit the microcontroller can monitor if there is activity
on the CAN bus while being in SWK Mode. The bit can be read in SBC Stop and Normal Mode.
5.3.3.10 SYNC-FLAG (SYNC_x)
The bit SYNC_x shows that SWK is working and synchronous to the CAN bus. To get a SYNC_x bit set it is
required to enable the CAN (CANx bits), no CAN Mode with SWK needs to be enabled.
The bit is set to 1 if a valid CAN frame has been received. It is set back to 0 if a CAN protocol error is detected.
When switching into SWK mode the SYNC_x bit indicates to the µC that the frame detection is running and the
next CAN frame can be detected as a WUF, CAN wake-up can now be handled by the SBC. It is possible to enter
a SBC low-power mode with SWK even if the bit is not set to 1, as this is necessary in case of a silent bus.
5.3.3.11 SWK_SET FLAG (SWK_SET_x)
The status bit SWK_SET_x is set to signalize the following states (see also Figure 7):
•
•
•
When SWK was correctly enabled in WUF Detection state.
When SWK was correctly enabled when WUP Detection 1 state.
After a SYSERR_x before a wake event in WUP Detection 2 state.
The bit is cleared if following conditions:
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Multi-CAN Power+ System Basis Chip
•
•
After a wake-up (ECNT_x overflow, WUP_x in WUP detection 2, WUF_x in WUF detection).
If CANx_2 is cleared.
5.3.4
SBC Modes for Selective Wake (SWK)
The SBC mode is selected via the MODE bits as described in Chapter 5.1.
The mode of the CAN transceiver needs to be selected in SBC Normal Mode. The CAN mode is programed the
bits CANx_0, CANx_1 and CANx_2. In the low-power modes (SBC Stop and Sleep Mode) the CAN mode can not
be changed via SPI.
The detailed SBC state machine diagram including the CAN selective wake feature is shown in Figure 3.
The application must now distinguish between the normal CAN operation an the selective wake function:
•
•
WK Mode: This is the normal CAN wake capable mode without the selective wake function.
SWK Mode: This is the CAN wake capable mode with the selective wake function enabled.
Figure 10 shows the possible CAN transceiver modes.
CAN OFF Mode
CAN Normal Mode
(no SWK)
CAN Receive-Only
Mode
CAN WK Mode
SPI CAN_x
CAN Normal mode with SWK
CAN Normal mode
CAN RX Only Mode with SWK
CAN RX Only Mode
CAN Wakable Mode
with SWK
OK
OK
OK
Config.
Check
CAN
SWK
Config.
Check
CAN
SWK
Config.
Check
CAN
SWK
Not OK
Not OK
Not OK
CAN WK
CAN WK
CAN WK
Figure 10 CAN SWK State Diagram
5.3.4.1 SBC Normal Mode with SWK
In SBC Normal Mode the CANx Transceiver can be switched into the following CAN Modes:
•
•
•
•
•
•
CAN OFF
CAN WK Mode (without SWK)
CAN SWK Mode
CAN Receive Only (No SWK activated)
CAN Receive Only Mode with SWK
CAN Normal Mode (No SWK activated)
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•
CAN Normal Mode with SWK
In the CAN Normal Mode with SWK the CANx Transceiver works as in SBC Normal Mode, so bus data is received
through RXDCANx, data is transmitted through TXDCANx and sent to the bus. In addition the SWK block is
active. It monitors the data on the CAN bus, updates the error counter and sets the CANSIL_x flag if there is no
communication on the bus.
It will generate an CAN Wake interrupt in case a WUF is detected (RXDCANx is not pulled to LOW in this
configuration).
In CAN Receive Only Mode with SWK, CAN data can be received on RXDCANx and SWK is active, no data can be
sent to the bus.
The bit SYSERR_x = 0 indicates that the SWK function is enabled, and no frame error counter overflow is
detected.
Table 10 CAN Modes selected via SPI in SBC Normal Mode
CAN Mode
CANx_2
CANx_1
CANx_0
CAN OFF
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
CAN WK Mode (no SWK)
CAN Receive Only (no SWK)
CAN Normal Mode (no SWK)
CAN OFF
1
0x
1
0
CAN SWK Mode
1
CAN Receive Only with SWK
CAN Normal Mode with SWK
0
1
When reading back CAN_x the programmed mode is shown in SBC Normal Mode. To read the real CAN mode
the bits SYSERR_x, SWK_SET_x and CAN_x have to be evaluated. A change out of SBC Normal Mode can
change the CAN_x_0 and CAN_x_1 bits.
5.3.4.2 SBC Stop Mode with SWK
In SBC Stop Mode the CANx Transceiver can be operated with the following CAN Modes:
•
•
•
•
CAN OFF
CAN WK Mode (no SWK)
CAN SWK Mode
CAN Receive Only (no SWK)
To enable CAN SWK Mode the CANx has to be switched to “CAN Normal Mode with SWK”, “CAN Receive Only
Mode with SWK” or to “CAN SWK Mode” in SBC Normal Mode before sending the SBC to SBC Stop Mode. The
bit SYSERR_x = 0 indicates that the SWK function is enabled. The table shows the change of CAN Mode when
switching from SBC Normal Mode to SBC Stop Mode.
Note:
CAN Receive Only Mode in SBC Stop Mode is implemented to also enable pretended networking
(Partial networking done in the microcontroller).
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Multi-CAN Power+ System Basis Chip
Table 11 CAN Modes change when switching from SBC Normal Mode to SBC Stop Mode
Programmed CAN Mode in SBC
Normal Mode
CANx
Modes x bit
SYSERR_ CAN Mode in SBC Stop Mode
CANx
Modes
CAN OFF
000
001
010
011
100
101
101
110
110
111
111
0
0
0
0
0
0
1
0
1
0
1
CAN OFF
000
001
010
001
100
101
101
110
110
101
101
CAN WK Mode (no SWK)
CAN Receive Only (no SWK)
CAN Normal Mode (no SWK)
CAN OFF
CAN WK Mode (no SWK)
CAN Receive Only (no SWK)
CAN WK Mode (no SWK)
CAN OFF
CAN SWK Mode
CAN SWK Mode
CAN SWK Mode
CAN WK Mode (no SWK)
CAN Receive Only with SWK
CAN Receive Only (no SWK)
CAN WK Mode with SWK
CAN WK Mode (no SWK)
CAN Receive Only with SWK
CAN Receive Only with SWK
CAN Normal Mode with SWK
CAN Normal Mode with SWK
Note:
When SYSERR_x is set it is true that we will not detect WUF frames, so no selective wake function
active (no SWK), but the MSB of CAN mode is not changed in the register.
5.3.4.3 SBC Sleep Mode with SWK
In SBC Sleep Mode the CANx Transceiver can be switched into the following CAN Modes:
•
•
•
CAN OFF
CAN WK Mode (without SWK)
CAN SWK Mode
To enable “CAN SWK Mode” the CAN has to be switched to “CAN Normal Mode with SWK”, “CAN Receive Only
Mode with SWK” or to “CAN SWK Mode” in SBC Normal Mode before sending the device to SBC Sleep Mode.
The table shows the change of CAN mode when switching from SBC Normal Mode to Sleep Mode.
A wake from Sleep Mode with Selective Wake (Valid WUF) leads to SBC Restart Mode. In SBC Restart Mode the
CFG_VAL bit will be cleared by the SBC, the SYSERR_x bit is not set. In the BUS_CTRL_x register, the
programmed CAN SWK Mode (101) can be read.
To enable the CAN SWK Mode again and to enter SBC Sleep Mode the following sequence can be used;
Program a CAN Mode different from CAN SWK Mode (101, 110, 111), set the CFG_VAL, clear SYSERR_x bit, set
CANx transceiver to CAN SWK Mode (101), switch SBC to SBC Sleep Mode.
To enable the CAN WK Mode or CAN SWK Mode again after a wake on CANx, a rearming is required. The
rearming is done by programming the CANx transceiver into a different mode and back into the CAN WK Mode
or CAN SWK Mode. To avoid lock-up when switching the SBC into SBC Sleep Mode with an already woken CANx
transceiver, the SBC does an automatic rearming of the CANx transceiver when switching into Sleep Mode. So
after switching into SBC Sleep Mode the CANx transceiver is either in CAN SWK Mode or CAN WK Mode
depending on CANx_2 setting and SYSERR_x bit (If CAN is switched to OFF Mode it is also OFF in Sleep Mode)
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Multi-CAN Power+ System Basis Chip
Table 12 CAN Modes change when switching to SBC Sleep Mode
Programmed CAN Mode in SBC
Normal Mode
CANx
Modes x bit
SYSERR_ CAN Mode in SBC Sleep Mode
CANx
Modes
CAN OFF
000
001
010
011
100
101
101
110
110
111
111
0
0
0
0
0
0
1
0
1
0
1
CAN OFF
000
001
001
001
100
101
101
101
101
101
101
CAN WK Mode (no SWK)
CAN Receive Only (no SWK)
CAN Normal Mode (no SWK)
CAN OFF
CAN WK Mode (no SWK)
CAN WK Mode (no SWK)
CAN WK Mode (no SWK)
CAN OFF
CAN SWK Mode
CAN SWK Mode
CAN SWK Mode
CAN WK Mode (no SWK)
CAN SWK Mode
CAN Receive Only with SWK
CAN Receive Only with SWK
CAN Normal Mode with SWK
CAN Normal Mode with SWK
CAN WK Mode (no SWK)
CAN SWK Mode
CAN WK Mode (no SWK)
5.3.4.4 SBC Restart Mode with SWK
If SBC Restart Mode is entered the transceiver can change the CAN mode. During Restart or after Restart the
following modes are possible:
•
•
•
CAN OFF
CAN WK Mode (either still wake cable or already woken up)
CAN SWK Mode (WUF Wake from Sleep)
Table 13 CAN Modes change in case of Restart out of SBC Normal Mode
Programmed CAN Mode in SBC CANx SYSERR_ CAN Mode in and after SBC CANx
SYSERR
_x bit
Normal Mode
Modes x bit
Restart Mode
Modes
000
001
001
001
100
101
101
101
101
101
101
CAN OFF
000
001
010
011
100
101
101
110
110
111
111
0
0
0
0
0
0
1
0
1
0
1
CAN OFF
0
0
0
0
0
1
1
1
1
1
1
CAN WK Mode (no SWK)
CAN Receive Only (no SWK)
CAN Normal Mode (no SWK)
CAN OFF
CAN WK Mode (no SWK)
CAN WK Mode (no SWK)
CAN WK Mode (no SWK)
CAN OFF
CAN SWK Mode
CAN WK Mode (no SWK)
CAN WK Mode (no SWK)
CAN WK Mode (no SWK)
CAN WK Mode (no SWK)
CAN WK Mode (no SWK)
CAN WK Mode (no SWK)
CAN SWK Mode
CAN Receive Only with SWK
CAN Receive Only with SWK
CAN Normal Mode with SWK
CAN Normal Mode with SWK
The various reasons for entering SBC Restart Mode and the respective status flag settings are shown in
Table 14.
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Multi-CAN Power+ System Basis Chip
Table 14 CAN Modes change in case of Restart out of SBC Sleep Mode
CAN Mode in SBC
Sleep Mode
CAN Mode in
and after SBC Modes ERR_ x_WU _x
CANx SYS
CAN_ WUP WUF_ ECNT_ Reason for Restart
x
x bits
Restart Mode
x
CAN OFF
CAN OFF
000
0
0
0
0
0
Wake on other wake
source
CAN WK Mode
CAN WK Mode
CAN woken up 001
CAN WK Mode 001
0
0
1
0
1
0
0
0
0
0
Wake (WUP) on CAN
Wake on other wake
source
CAN SWK Mode
CAN SWK Mode
CAN woken up 101
CAN woken up 101
0
1
1
1
0/11)
0/12)
1
0
x
Wake (WUF) on CAN
100000 Wake due to error
counter overflow
CAN SWK selected, CAN woken up 101
CAN WK active
1
1
1
0
1
0
0
0
Wake (WUP) on CAN,
config check was not
pass
CAN SWK Mode
CAN WK Mode 101
0/1
x
Wake on other wake
source
1) In case there is a WUF detection within tSILENCE then the WUP_x bit will not be set. Otherwise it will always be set
together with the WUF_x bit.
2) In some cases the WUP_x bit might stay cleared even after tSILENCE, e.g. when the error counter expires without
detecting a wake up pattern
5.3.4.5 SBC Fail-Safe Mode with SWK
When SBC Fail-Safe Mode is entered the CAN transceiver is automatically set into WK Mode (wake capable)
without the selective wake function.
5.3.5
Wake-up
A wake-up via CAN leads to a restart out of SBC Sleep Mode and to an interrupt in SBC Normal Mode, and in
SBC Stop Mode. After the wake event the bit CAN_x_WU is set, and the details about the wake can be read out
of the bits WUP_x, WUF_x, SYSERR_x and ECNT_x bits.
5.3.6
Configuration for SWK
The CAN protocol handler settings can be configured in following registers:
•
SWK_BTL1_CTRLdefines the number of time quanta in a bit time. This number depends also on the
internal clock settings performed in the register SWK_CDR_CTRL2.
•
•
•
SWK_BTL2_CTRLdefines the sampling point position.
The respective receiver during frame detection mode can be selected via the bit RX_WK_SEL.
The clock and data recovery (see also Chapter 5.3.8.2) can be configured in the registers
SWK_CDR_CTRL1, SWK_CDR_CTRL2, SWK_CDR_LIMIT_HIGH_CTRL and SWK_CDR_LIMIT_LOW_CTRL.
The actual configuration for selective wake is done via the Selective Wake Control Registers SWK_IDx_CTRL,
SWK_MASK_IDx_CTRL, SWK_DLC_CTRL, SWK_DATAx_CTRL.
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The oscillator has the option to be trimmed by the microcontroller. To measure the oscillator, the SPI bit
OSC_CAL needs to be set to 1 and a defined pulse needs to be given to the TXDCANx pin by the microcontroller
(e.g. 1µs pulse, CANx needs to be switched off before). The SBC measures the length of the pulse by counting
the time with the integrated oscillator. The counter value can be read out of the register
SWK_OSC_CAL_H_STAT and SWK_OSC_CAL_L_STAT. To change the oscillator the trimming function needs
to be enabled by setting the bits TRIM_EN_x = 11 (and OSC_CAL = 1). The oscillator can then be adjusted by
writing into the registers SWK_OSC_TRIM_CTRL and SWK_OPT_CTRL. To finish the trimming, the bits
TRIM_EN_x need to be set back to “00”.
5.3.7
CAN Flexible Data Rate (CAN FD) Tolerant Mode
The CAN FD tolerant mode can be activated by setting the bit CAN_FD_EN = 1 in the register
SWK_CAN_FD_CTRL. With this mode the internal CANx frame decoding will be stopped for CAN FD frame
formats:
•
•
The high baud rate part of a CAN FD frame will be ignored.
No Error Handling (Bit Stuffing, CRC checking, Form Errors) will be applied to remaining CAN frame Fields
(Data Field, CRC Field, …).
•
No wake up is done on CAN FD frames.
The internal CAN frame decoder will be ready for new CAN frame reception when the End of frame (EOF) of a
CAN FD frame is detected.The identification for a CAN FD frame is based on the EDL Bit, which is sent in the
Control Field of a CAN FD frame:
•
•
EDL Bit = 1 identifies the current frame as an CAN FD frame and will stop further decoding on it.
EDL Bit = 0 identifies the current frame as CAN 2.0 frame and processing of the frame will be continued.
In this way it is possible to send mixed CAN frame formats without affecting the selective wake functionality
by error counter increment and subsequent misleading wake up.In addition to the CAN_FD_EN bit also a filter
setting must be provided for the CAN FD tolerant mode. This filter setting defines the minimum dominant time
for a CAN FD dominant bit which will be considered as a dominant bit from the CAN FD frame decoder. This
value must be aligned with the selected high baud rate of the data field in the CAN network.
To support programming via CAN during CAN FD mode a dedicated SPI bit DIS_ERR_CNT is available to avoid
an overflow of the implemented error counter (see also Chapter 5.3.2.4).
The behavior of the error counter depends on the setting of the bits DIS_ERR_CNT and CAN_FD_EN and is
show in below table:
Table 15 Error Counter Behavior
DIS_ERR_CNT setting CAN_FD_EN setting
Error Counter Behavior
0
0
Error Counter counts up when a CAN FD frame or an
incorrect/corrupted CAN frame is received; counts down
when a CAN frame is received properly
(as specified in ISO 11898-6)
1
0
Error Counter counts up when a CAN FD frame or an
incorrect/corrupted CAN frame is received; counts down
when a CAN frame is received properly
(as specified in ISO 11898-6)
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Multi-CAN Power+ System Basis Chip
Table 15 Error Counter Behavior (cont’d)
DIS_ERR_CNT setting CAN_FD_EN setting
Error Counter Behavior
0
1
Error Counter counts down when correct CAN (incl. CAN FD)
frame is received
1
1
Error Counter is and stays cleared to avoid an overflow
during programming via CAN
The DIS_ERR_CNT bit is automatically cleared at tSILENCE expiration.
5.3.8
Clock and Data Recovery
In order to compensate possible deviations on the CAN oscillator frequency caused by assembly and lifetime
effects, the device features an integrated clock and data recovery (CDR).
It is recommended to always enable the CDR feature during SWK operation.
5.3.8.1 Configuring the Clock Data Recovery for SWK
The Clock and Data Recovery can be optionally enabled or disabled with the CDR_EN Bit in the
SWK_CDR_CTRL1 SPI Register. In case the feature is enabled, the CAN bit stream will be measured and the
internal clock used for the CAN frame decoding will be updated accordingly. Before the Clock and Data
Recovery can be used it must be configured properly related to the used baud rate and filtering characteristics
(refer to Chapter 5.3.8.2).
It is strongly recommended to not enable/disable the Clock Recovery during a active CAN Communication.
To ensure this it is recommended to enable/disable it during CAN OFF.
CDR
Aquisition
80 Mhz Oscilator
(analog)
CAN
Protocoll
Handler
Filter
Fractional
Divider
RX
CAN Receiver
(analog)
Figure 11 Clock and Data Recovery Block Diagram
5.3.8.2 Setup of Clock and Data Recovery
It is strongly recommended to enable the clock and data recovery feature only when the setup of the clock and
data recovery is finished.
The following sequence should be followed for enabling the clock and data recovery feature:
•
Step 1: Switch CANx to OFF and CDR_EN to OFF
Write SPI Register BUS_CTRL_x (CANx = 000).
•
Step 2: Configure CDR Input clock frequency
Write SPI Register SWK_CDR_CTRL2 (SEL_OSC_CLK[1:0]).
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•
•
Step 3: Configure Bit timing Logic
Write SPI Register SWK_BTL1_CTRL and adjusting SWK_CDR_LIMIT_HIGH_CTRL and
SWK_CDR_LIMIT_LOW_CTRL according to Table 33.
Step 4: Enable Clock and Data Recovery
Choose filter settings for Clock and Data recovery. Write SPI Register SWK_CDR_CTRL1 with CDR_EN = 1
Additional hints for the CDR configuration and operation:
•
Even if the CDR is disabled, when the baud rate is changed, the settings of SEL_OSC_CLK in the register
SWK_CDR_CTRL1 and SWK_BTL1_CTRL have to be updated accordingly.
•
The SWK_CDR_LIMIT_HIGH_CTRL and SWK_CDR_LIMIT_LOW_CTRL registers have to be also updated
when the baud rate or clock frequency is changed (the CDR is discarding all the acquisitions and looses all
acquired information, if the limits are reached - the SWK_BTL1_CTRL value is reloaded as starting point
for the next acquisitions).
•
•
When updating the CDR registers, it is recommended to disable the CDR and to enable it again only after
the new settings are updated.
The SWK_BTL2_CTRL register represents the sampling point position. It is recommended to be used at
default value: 11 0011 (~80%).
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5.3.9
Electrical Characteristics
Table 16 Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
CAN Partial Network Timing
1)
Time-out for bus inactivity tSILENCE
0.6
–
–
–
1.2
s
P_5.3.1
1) Load RL = 60 Ω, P_5.3.2
CL = 100 pF,
Bias reaction time
tbias
200
µs
CGND = 100 pF
Wake-up reaction time
(WUP or WUF)
tWU_WUP/WUF
–
–
100
µs
1)2)3) Wake-up
reaction time
after a valid WUP
or WUF;
P_5.3.3
1)4)
Min. Bit Time
CAN FD Tolerance5)
tBit_min
1
6
–
–
–
µs
P_5.3.4
P_5.3.5
SOF acceptance
nBits_idle
10
bits
6)Number of
recessive bits
before a new SOF
shall be accepted
Dominant signals which
are ignored
(up to 2 MBit/s)
tFD_Glitch_4
0
–
–
–
–
5
%
%
%
%
6)7)8) of
P_5.3.6
P_5.3.7
P_5.3.8
P_5.3.9
arbitration bit
time; to be
configured via
FD_FILTER;
Dominant signals which
are ignored
(up to 5 MBit/s)
tFD_Glitch_10
0
2.5
–
6)7)9) of
arbitration bit
time; to be
configured via
FD_FILTER;
Signals which are detected tFD_DOM_4
as a dominant data bit after
the FDF bit and before EOF
bit
17.5
8.75
6)7)8) of
arbitration bit
time; to be
configured via
FD_FILTER;
(up to 2 MBit/s)
Signals which are detected tFD_DOM_10
as a dominant data bit after
the FDF bit and before EOF
bit
–
6)7)9) of
arbitration bit
time; to be
configured via
FD_FILTER;
(up to 5 MBit/s)
1) Not subject to production test, tolerance defined by internal oscillator tolerance.
2) Wake-up is signalized via INTN pin activation in SBC Stop Mode and via VCC1 ramping up with wake from SBC Sleep
Mode.
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Multi-CAN Power+ System Basis Chip
3) For WUP: time starts with end of last dominant phase of WUP; for WUF: time starts with end of CRC delimiter of the
WUF.
4) The minimum bit time corresponds to a maximum bit rate of 1 Mbit/s. The lower end of the bit rate depends on the
protocol IC or the permanent dominant detection circuitry preventing a permanently dominant clamped bus.
5) Applies for an arbitration rate of up to 500 kbps until the FDF bit is detected.
6) Not subject to production test; specified by design.
7) Parameter applies only for the Normal Mode CAN receiver (RX_WK_sel = 0).
8) A data phase bit rate less or equal to four times of the arbitration bit rate or 2 Mbit/s, whichever is lower.
9) A data phase bit rate less or equal to ten times of the arbitration bit rate or 5 Mbit/s, whichever is lower.
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
DC/DC Regulator
6
DC/DC Regulator
6.1
Block Description
The SMPS module in the TLE9278-3BQX is implemented as a cascade of a step-up regulator followed by a step-
down post-regulator. The step-up regulator (DC/DC Boost converter) provides a VS level which permits the
step-down post-regulator (DC/DC Buck converter) to regulate without entering a low-drop condition.
The SMPS module is active in SBC Normal, Stop and Restart Mode. In SBC Sleep and Fail-Safe Mode, the SMPS
module is disabled.
Comparator
VS
D1
L1
D2
Vbat
SPI
VSUP
VS
Boost
Converter
C1
C2
C3
Cf1
BSTD
BSTD
GND
GND
Feedforward
Buck
Converter
L2
BCKSW
C4
C5
GND
Bandgap
Reference
VCC1
Soft Start
Ramp
Generator
Figure 12 DC/DC Block Diagram
Functional Features
•
•
•
•
5 V SMPS (DC/DC) Buck Regulator with integrated high-side and low-side power switching transistor.
SMPS (DC/DC) Boost Regulator for low VSUP supply voltage with integrated power transistor.
Adjustable output DC/DC Boost pre-regulator voltage via SPI.
Fixed switching frequency for Buck and Boost Regulator in SBC Normal Mode in PWM (Pulse Width
Modulation).
•
•
•
PFM (Pulse Frequency Modulation) for Buck converter in SBC Stop Mode to reduce the quiescent current.
Automatic transition PFM to PWM in SBC Stop Mode.
Soft start-up.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
DC/DC Regulator
•
•
•
Edge Shaping for better EMC performances for Buck and Boost regulator.
Undervoltage monitoring via VIO pin with adjustable reset level (refer to Chapter 12.7).
Overvoltage detection via VIO pin activates the FO pin in case that VIO_OV_RST bit is set and if PCFG is
open (refer to Chapter 12.8).
•
•
•
•
Buck short circuit detection.
Buck 100% Duty Cycle at low VS operation.
Buck overcurrent peak detection.
Boost overcurrent peak detection.
6.1.1
Functional Description of the Buck Converter
SPI
Logic
L1
D1
VS
C3
VSUP
Vbat
Feedforward
C2
C1
Buck
Converter
L2
BCKSW
C5
C6
GND
Bandgap
Reference
VCC1
Soft Start
Ramp
Generator
Figure 13 Buck Block Diagram
The DC/DC Buck converter is intended as post-regulator (VCC1) and it provides a step down converter function
transferring energy from VS to a lower output voltage with high efficiency (typically more than 80%). The
output voltage is 5 V in a current range up to 750 mA. It is regulated via a digital loop with a precision of ±2%.
It requires an external inductor and capacitor filter on the output switching pin (BCKSW). The Buck regulator
has integrated high-side and low-side power switching transistors. The compensation of the regulation loop
is done internally and no additional external components are needed.
A typical application example and external components proposal is available in Chapter 14.1.
The Buck converter is active in SBC Normal, Stop and Restart Mode and it is disabled in SBC Sleep and Fail-
Safe Mode.
Depending on the SBC Mode, the Buck converter works in two different modes:
•
PWM Mode (Pulse Width Modulation): This mode is available in SBC Normal Mode, SBC Restart Mode and
SBC Stop Mode (only for automatic or manual PFM to PWM transitions. Refer to Chapter 6.2.2). In PWM,
the Buck converter operates with a fixed switching frequency (fBUK). The duty cycle is calculated internally
based on input voltage, output voltage and output current. The precision is ±2% or ±3% based on input
supply and output current range (refer to Figure 18 for more information). In PWM Mode, the Buck
converter is capable of a 100% duty cycle in case of low VS conditions. In order to reduce EMC, the edge
shaping feature has been implemented to control the activation and deactivation of the two power
switches.
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Multi-CAN Power+ System Basis Chip
DC/DC Regulator
•
PFM Mode (Pulse Frequency Modulation): This mode is activated automatically when the SBC Stop Mode
is entered. The PFM Mode is an asynchronous mode. PFM Mode does not have a controller switching
frequency. The switching frequency depends on conditions of the Buck regulator such as the following:
input supply voltage, output voltage, output current and external components. A typical timing diagram is
shown in Figure 14. The Buck converter in PFM Mode has a tolerance of ±4%. The transition from PFM
mode to PWM mode is described in Chapter 6.2.2.
Tristate
HS
LS
Tristate
Feedback Voltage VCC 1
LVL
UCL
LCL
Coil Current
start biasing
&
oscillator
OFF
ON
OFF
ON
PFM active
Iq
Iq
Quiescent Current
Figure 14 Typical PFM timing diagram
6.1.1.1 Startup Procedure (Soft Start)
The Startup Procedure (Soft Start) permits to achieve the Buck regulator output voltage avoiding large
overshoot on the output voltage. This feature is activated during the power-up, from SBC Sleep to Restart
Mode and from SBC Fail-Safe to SBC Restart Mode.
When the Buck regulator is activated, it starts in open loop with a minimum duty cycle which is maintained for
a limited number of switching periods. After this first phase, the duty cycle is linearly increased by a fixed step
and it is maintained for a limited number of switching periods for each duty cycle step. This procedure is
repeated until the target output voltage value of the Buck regulator is reached. As soon as the Buck regulator
output voltage is reached, the regulation loop is closed and it starts to operate normally using PWM Mode
adjusting the duty cycle according to the Buck input and output voltages and the output current.
6.1.1.2 Buck regulator Status register
The register SMPS_STAT contains information about the open or short conditions on BCKSW pin. No SBC
Mode or configuration changes are triggered if one bit on SMPS_STAT register is set.
6.1.1.3 External components
The Buck converter needs one inductor and output capacitor filter. The inductor has a fixed value of 47 µH.
Secondary parameters such as saturation current must be selected based on the maximum current capability
needed in the application.
The output filter capacitors are two parallel 22 µF ceramic capacitor. For additional information, refer to
Chapter 14.1.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
DC/DC Regulator
6.1.2
Functional Description of the Boost Converter
Comparator
VS
VS
D1
L1
D2
Vbat
SPI
VSUP
Boost
Converter
C1
C3
C4
C2
BSTD
BSTD
GND
GND
VS
Figure 15 Boost Block Diagram
The Boost converter is intended as a pre-regulator and it provides a step up converter function. It transfers
energy from an input supply VSUP (battery voltage after reverse protection circuit) to a higher output voltage
(VS) with high efficiency (typically more than 80%).
The regulator integrates the power switching and the sense resistor for overcurrent detection.
The Boost regulator can be enabled in SBC Normal Mode via SPI (register HW_CTRL_0, bit BOOST_EN) and
four output voltage values are selectable via BOOST_V. The Boost regulator can also be active in SBC Stop and
Restart Mode. The selected boost output voltage will automatically define the voltage thresholds where the
boost will be ON (VBST,TH1, VBST,TH2, VBST,TH3 and VBST,TH4). If the Boost regulator is enabled, it switches ON
automatically when VS falls below the selected threshold voltage and switches OFF when crossing this
threshold including hysteresis again. The bit BST_ACT on SMPS_STAT register indicates that the Boost has
been activated.
The Boost output voltage can be changed only if BOOST_EN is set to 0. In case that the boost output voltage
configuration changes with BOOST_EN set to 1, the SPI_FAIL bit is set and the command is ignored.
Figure 16 shows the typical timing for enabling the Boost converter.
VSUP
VS
VBST,THx
VBSTx
VBST,HYSx
0
1
0
BST_ACT
BSTD
Figure 16 Boost converter activation
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Multi-CAN Power+ System Basis Chip
DC/DC Regulator
The Boost regulator works in PWM Mode with fixed frequency (fBST) and a tolerance of ±3%.
If the Boost is enabled in Stop Mode, the quiescent current in the SBC is increased (P_4.4.31).
6.1.2.1 Boost Regulator Status register
The register SMPS_STAT contains information about the open or short conditions on Boost pins including loss
of GND detection. No SBC mode or configuration is triggered if one bit is set on the SMPS_STAT register.
6.1.2.2 External Components
The Boost converter requires a number of external components such as the following: input buffer capacitor
on the battery voltage, inductor, freewheeling diode and filter capacitors.
For recommend external components and corresponding values, refer to Chapter 14.1.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
DC/DC Regulator
6.2
Power Scenarios
The chapter describes the features and performance of the Buck regulator according to SBC modes. The Boost
module works only in SBC Normal or Stop Mode using PWM modulation (refer also to Chapter 6.1.2).
6.2.1
Buck behavior in SBC Normal Mode
In SBC Normal Mode the Buck works is in PWM mode with fixed switching frequency. All supervision functions
for Buck converter are available in SBC Normal Mode and available depending the device configuration
(Chapter 5.1.1). For additional details on the supervision functions, refer to Chapter 12.7, Chapter 12.8,
Chapter 12.9 and Chapter 12.11.
6.2.2
Buck behavior in SBC Stop Mode
The SBC Stop Mode operation is intended to reduce the total amount of quiescent current while still providing
output voltage. In order to achieve this, the Buck regulator changes the modulation from PWM (Pulse Width
Modulation) to PFM (Pulse Frequency Modulation) when entering SBC Stop Mode.
In SBC Stop Mode, the Buck modulation can change as follow:
•
•
•
Buck module always in PFM modulation (default setting).
Automatically change from PFM to PWM (setting PWM_AUTO).
Modulation is controlled by the WK pin (setting PWM_BY_WK).
If the PWM_BY_WK and PWM_AUTO are set at the same time, the PWM_AUTO has highest priority and PWM
automatic transition will be used.
If PWM_BY_WK and PWM_AUTO are at the same time set to 0, the buck module remains in PFM in SBC Stop
Mode.
If in SBC Stop Mode the Buck modulation is PWM, the buck output voltage tolerance and output current
capability are like SBC Normal Mode (P_6.5.1 and P_6.5.45).
6.2.2.1 Automatic Transition from PFM to PWM in SBC Stop Mode
If more current is needed, an automatic transition from PFM to PWM mode is implemented. When the Buck
regulator output current exceeds the IPFM-PWM,TH threshold, the Buck module changes the modulation to PWM
and an INTN event is generated. In addition, the PFM_PWM bit on WK_STAT_0 is set.
In order to set the Buck modulation again in PFM mode, a SBC Stop Mode command has to be write to
M_S_CTRL register. This command has to be sent when the required Buck output current is below the IPFM-
PWM,TH threshold.
By default, the feature is disable. To enable the automatic transition from PFM to PWM, the PWM_AUTO bit in
HW_CTRL_0 has to be set before entering SBC Stop Mode.
When entering SBC Stop Mode, the automatic transition from PFM to PWM mode is activated after the
transition time (tlag), during which the Buck regulator loop changes the modulation technique. Figure 17
shows the timing transition from SBC Normal to Stop Mode.
The transition time tlag is always implemented in case of transition from PWM to PFM modulation.
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Multi-CAN Power+ System Basis Chip
DC/DC Regulator
SPI Commands
Buck modulation
Normal Mode
PWM
Stop Mode
Auto PFM ↔ PWM
PWM
t
tlag
Figure 17 Transition from SBC Normal to SBC Stop Mode
The tlag can be configured via SPI using the PWM_TLAG in HW_CTRL_0 register.
The automatic transition from PFM to PWM can be disabled by setting the PWM_AUTO to 0 in the HW_CTRL_0
register.
6.2.2.2 Manual Transition from PFM to PWM in SBC Stop Mode
The PFM to PWM transition can also be controlled by the microcontroller or an external signal by using the WK
pin as a trigger signal in SBC Stop Mode.
When the PWM_BY_WK bit is set to 1, the Buck regulator can be switched from PFM to PWM using the WK pin.
A LOW level at the WK pin will switch the Buck converter to PFM mode, a HIGH level will switch the Buck
converter to PWM Mode. In this configuration, the transition time tlag is not taken into account because a
defined signal from microcontroller or external source is expected.
6.2.2.3 SBC Stop to Normal Mode transition
The microcontroller sends an SPI command to switch from SBC Stop Mode to SBC Normal Mode. In this
transition, the Buck regulator changes the modulation from PFM to PWM.
Once the SPI command for the SBC Normal Mode transition is received, the Buck output current is able to rise
above the specified maximum Stop Mode current (IPFM-PWM,TH).
If the transition from SBC Stop Mode to SBC Normal Mode is carried out when the Boost is enabled and
operating, it will continue to operate without any changes.
6.2.3
Buck behavior in SBC Sleep or Fail Safe Mode
In SBC Sleep or Fail Safe Mode, the Buck and Boost converter are off and not operating. The lowest quiescent
current is achievable.
6.2.3.1 SBC Sleep/Fail Safe Mode to SBC Normal Mode transition
In case of a wake-up event from WK pin or transceivers, the SBC will be set to SBC Restart Mode and as soon
as the reset is released, into SBC Normal Mode.
In SBC Restart Mode, the Buck regulator is activated and ramping-up. The Boost regulator is activated and
ramping-up again (in case the VS is below the selected threshold) in according the configuration selected in
SBC Normal Mode. As soon as the Buck output voltage exceeds the reset threshold, the RSTN pin is released.
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Multi-CAN Power+ System Basis Chip
DC/DC Regulator
6.3
Electrical Characteristics
Table 17 Electrical Characteristics
Tj = -40°C to +150°C; VS = 5.5 V to 28 V; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Buck Regulator
Output Voltage PWM including VCC1,out1 4.9
Line and Load regulation
5.0
5.1
V
V
SBC Normal Mode
(PWM)
1 mA < IVCC1 < 750 mA
6.5 V < VS < 28 V
1) SBC Normal Mode
(PWM)
P_6.5.1
Output Voltage PWM including VCC1,out1 4.85 5.0
Line and Load regulation
5.15
P_6.5.45
IVCC1 = 400 mA
VS = 5.5 V
Boost Disable
Output Voltage PFM including VCC1,out2 4.8
Line and Load regulation
5.0
5.2
V
V
SBC Stop Mode (PFM) P_6.5.2
10 µA < IVCC1 < IPFM-
PWM,TH
6.5 V < VS < 28 V
Output Voltage PFM including VCC1,out3 4.85 5.0
Line and Load regulation
5.15
SBC Stop Mode (PFM) P_6.5.47
10 µA < IVCC1 < 50 mA
6.5 V < VS < 28 V
Power Stage on-resistance
High-Side
RDSON1,HS
RDSON1,LS
–
–
–
–
1.3
1.3
Ω
Ω
A
VS = 6.5 V
VS = 100 mA
P_6.5.3
P_6.5.20
P_6.5.40
P_6.5.5
P_6.5.6
I
Power Stage on-resistance
Low-Side
IBCKSW = 100 mA
Overcurrent peak limitation
internal high side
IBCK_LIM,TH 0.85 1.05 1.2
VS > 6.5 V
Buck switching frequency
fBUK
405 450 495 kHz SBC Normal Mode
(PWM)
Automatic transition PFM to
PWM threshold
80
110 150 mA
1) SBC Stop Mode
(PFM)
IPFM-
PWM,TH
6.5 V < VS < 28 V
Transition time from PWM to tlag
PFM
–
–
1
–
–
ms
µs
1) PWM_TLAG=1
(on HW_CTRL_0)
1) PWM_TLAG=0
(on HW_CTRL_0)
P_6.5.15
P_6.5.16
Transition time from PWM to tlag
PFM
100
Boost Regulator
Boost Voltage 1 including Line VBST1
6.5
6.7
6.9
V
2) SBC Normal Mode
P_6.5.7
and Load regulation
VSUP = 3 V
IVS = 550 mA
Boost enabled
BOOST_V = 00B
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
DC/DC Regulator
Table 17 Electrical Characteristics (cont’d)
Tj = -40°C to +150°C; VS = 5.5 V to 28 V; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Boost Voltage 2 including Line VBST2
and Load regulation
7.76
8
8.24
V
V
2) SBC Normal Mode
SUP = 3V
VS = 450 mA
Boost enabled
BOOST_V = 01B
P_6.5.8
V
I
Boost Voltage 3 including Line VBST3
and Load regulation
9.7
10
10.3
2) SBC Normal Mode
P_6.5.28
P_6.5.31
V
SUP = 3 V
IVS = 300 mA
Boost enabled
BOOST_V = 10B
2) SBC Normal Mode
Boost Voltage 4 including Line VBST4
11.64 12
12.36 V
and Load regulation
V
SUP = 3 V
IVS = 250 mA
Boost enabled
BOOST_V = 11B
Boost Switch ON voltage
Boost Switch ON voltage
Boost Switch ON voltage
Boost Switch ON voltage
VBST,TH1
6.50
7
7.30
8.90
V
V
Boost enabled, VS
falling
BOOST_V = 00B
P_6.5.9
VBST,TH2
VBST,TH3
VBST,TH4
VBST,HYS
7.90 8.5
Boost enabled, VS
falling
BOOST_V = 01B
P_6.5.18
P_6.5.34
P_6.5.35
9.80 10.5 10.80 V
Boost enabled, VS
falling
BOOST_V = 10B
11.7 12.5 13.0
V
Boost enabled, VS
falling
BOOST_V = 11B
Boost Switch ON/OFF
hysteresis
0.35 0.5
2.0
0.70
2.3
V
A
Boost enabled
P_6.5.10
P_6.5.11
P_6.5.12
Overcurrent peak limitation
internal switch
IBST_LIM,TH 1.7
fBST
Boost enable
VSUP ≥ 3 V
Boost switching frequency
405 450 495 kHz SBC Normal Mode
(PWM)
1) Not subject to production test, specified by design.
2) Values verified in characterization with Boost converter external components specified in Chapter 14.1. No subject
to production test; specified by design. Refer to Figure 19 for additional information.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
DC/DC Regulator
800
VCC1 tolerance +/-3%
VCC1 tolerance +/-2%
750
700
650
600
550
500
450
400
5.5
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
6.5
8
10
12
18
20
24
28
VS (V)
Figure 18 Maximum DCDC Buck current capability versus VS
Note:
Figure 18is based on characterization results overtemperature with external components specified
in Chapter 14.1.
1.8
1.6
1.4
1.2
1
0.8
VBST1
0.6
VBST2
VBST3
VBST4
11
0.4
0.2
3
4
5
6
7
8
9
10
12
VSUP (V)
Figure 19 Maximum DCDC Boost current capability versus VSUP
Note:
Figure 19 is based on simulation results (specified by design), with Boost converter external
components specified in Chapter 14.1.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
External Voltage Regulator
7
External Voltage Regulator
7.1
Block Description
VEXTIN
VEXTSH
VEXTB
VEXTREF
RBE
IEXTbase
VEXTIN - VEXTshunt
> Vshunt_threshold
+
-
VREF
State Machine
Figure 20 Functional Block Diagram
Functional Features
•
•
•
Low-drop voltage regulator with external PNP transistor (up to 400 mA with 470 mΩ shunt resistor).
Four high voltage pins are used: VEXTIN, VEXTB, VEXTSH, VEXTREF.
Dedicated supply input VEXTIN to supply from VS or from VCC1 (Buck regulator output voltage) depending
on the application.
•
•
Configurable output voltages via SPI: 5.0 V, 3.3 V (default), 1.8 V and 1.2 V.
≥ 4.7 µF ceramic capacitor at output voltage for stability, with ESR < 150 mΩ @ f = 10 kHz to achieve the
voltage regulator control loop stability based on the safe phase margin (bode diagram).
•
Overcurrent limitation can be configured with external shunt resistor.
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Multi-CAN Power+ System Basis Chip
External Voltage Regulator
7.2
General Description
The external voltage regulator can be used as an independent voltage regulator or as microcontroller supply
with fixed VEXT output voltage (depending on the PCFG pin setting). For additional information, refer to
Chapter 5.1.1.1, in particular the Table 5.
The regulator will act in the respective SBC Mode as described in Table 18.
The maximum current IEXT_max is defined by the shunt used. To protect the VEXT against overtemperature
condition, the base driver has a dedicate temperature sensor. For detailed temperature protection features,
refer to Chapter 12.11.
The status of VEXT is reported in the SUP_STAT_1 register (for detailed protection features refer to
Chapter 12.10).
Table 18 External Voltage Regulator State by SBC Mode
SBC Mode
Voltage Regulator Behavior
(PCFG = Open)
Voltage Regulator Behavior
(PCFG = GND)
INIT Mode
OFF
ON, VEXT = 3.3 V
VEXT = 3.3 V (fixed)
VEXT = 3.3 V (fixed)
OFF
Normal Mode
Stop Mode
Configurable
Fixed
Sleep Mode
Restart Mode
Fail-Safe Mode
Fixed
Fixed
VEXT = 3.3 V (fixed)
OFF
OFF
Note:
The configuration of the VEXT voltage regulator behavior must be implemented immediately when
the SBC Normal Mode is reached after power-up of the device. As soon as the bit VEXT_ON is set for
the first time, the configuration for VEXT cannot be changed anymore. The configuration cannot be
changed as long as the device is supplied.
Note:
If the VEXT output voltage is supplying external off-board loads, the application must consider the
series resonance circuit built by cable inductance and decoupling capacitor at load. Sufficient
damping must be provided(e.g. series resistor with capacitor directly at device or 100 Ω Resistor
between PNP collector and VEXTREF with 10 µF cap on collector (see Figure 21).
7.2.1
Functional Description
This regulator offers with VEXT a second supply which could be used as off-board supply e.g. for sensors due
to the integrated HV pins VEXTB, VEXTSH, VEXTREF.
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Multi-CAN Power+ System Basis Chip
External Voltage Regulator
VS ,VCC1 or VSUP
VEXT
RSHUNT
T1
IEXT
C2
C1
RLim
100Ω
VEXTIN
VEXTSH
VEXTB
RBE
VEXTREF
IEXTbase
VEXTIN - VEXTshunt
> Vshunt_threshold
+
-
VREF
State Machine
Figure 21 VEXT Hardware Setup
VEXT can be switched ON or OFF but the output voltage configuration cannot no longer be changed once
activated.
An overcurrent detection function is realized with the external shunt (see Chapter 7.4 for calculating the
desired shunt value) and output current shunt voltage threshold (Vshunt_threshold). When this threshold is
reached, IEXT is limited and only the overcurrent detection bit VEXT_OC is set (no other reactions). This bit can
be cleared via SPI once the overcurrent condition is no longer present. If the overcurrent detection feature is
not needed, connect the VEXTSH pin to VEXT supply (VEXTIN pin).
If PCFG pin is left open, VEXT has the undervoltage signaling enabled and an undervoltage event is signaled
with the bit VREG_UV in the SUP_STAT_0. If PCFG is connected to GND, the VEXT undervoltage is signaled
with the bit VIO_UV on SUP_STAT_1 register (refer to Chapter 12.7 for additional information).
7.3
External Components
The characterization is done with the BCP52-16 from Infineon (IEXT < 200 mA) and with MJD253 from ON
Semi.Other PNP transistors can be used. The functionality must be checked in the application.
Figure 21 shows the hardware set up used.
Table 19 Bill of Materials for VEXT with BCP52-16
Device
C2
Vendor
Murata
–
Reference / Value
10 µF/10V GCM31CR71A106K64L
RSHUNT
T1
1 Ω
Infineon
BCP52-16
Note:
The SBC is not able to ensure a thermal protection of the external PNP transistor. The power
handling capabilities for the application must therefore be chosen according to the selected PNP
device and according to the PCB layout and the properties of the application to prevent thermal
damage.
Datasheet
59
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
External Voltage Regulator
Table 20 Bill of Materials for VEXT with MJD-253
Device
C2
Vendor
Murata
–
Reference / Value
10 µF/10V GCM31CR71A106K64L
470 mΩ
RSHUNT
T1
ON-Semi
MJD253
7.4
Calculation of RSHUNT
The maximum current IEXT_max where the overcurrent detection bit is set (VEXT_OC = 1 on the SUP_STAT_1
register), is determined by the shunt resistor RSHUNT and the Output Current Shunt Voltage Threshold
(Vshunt_threshold).
The resistor can be calculated as following:
Vshunt _ threshold
(7.1)
RSHUNT
=
IEXT _ max
7.5
Unused Pins
In case the VEXT is not used in the application, connect the unused pins of VEXT as followed:
•
•
•
•
Connect VEXTSH, VEXTIN to VS or leave open.
Leave VEXTB open.
Leave VEXTREF open.
Keep VEXT disabled.
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
External Voltage Regulator
7.6
Electrical Characteristics
Table 21 Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; SBC Normal Mode; all outputs open; all voltages with respect to ground;
positive current defined flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition Number
Min.
Parameters independent from Test Set-up
Max.
External Regulator IEXTbase
Control Drive
40
60
80
mA
VEXTbase = 13.5 V
P_7.6.1
Current Capability
Input Current
VEXTref
IEXTref
–
1
3
10
µA
µA
mV
VEXTref = 3.3 V, 5 V, 1.8 V, P_7.6.2
1.2 V
Input Current VEXT IEXTshunt
Shunt Pin
3
10
VEXTshunt = VS
P_7.6.3
P_7.6.4
1)
Output Current
Shunt Voltage
Threshold
Vshunt_threshold 180
245
310
Leakage current of IEXTbase_lk
EXTbase when VEXT
disabled
–
–
–
–
5
5
µA
µA
VEXTbase = VS;
Tj = 25°C
P_7.6.7
V
Leakage current of IEXTshunt_lk
VEXTshunt when VEXT
disabled
VEXTshunt = VS;
Tj = 25°C
P_7.6.25
Base to emitter
resistor
RBE
120
–
150
50
185
–
kΩ
VEXTbase = VS - 0.3 V;
VEXT OFF
2) Drive current I_EXTbase
IEXTbase rising
P_7.6.9
Active Peak
Threshold VEXT
(Transition
IVEXT,Ipeak,r
µA
;
P_7.6.26
VS =13.5 V;
threshold between
high-power and
low-power mode
regulator)
-40°C < Tj < 150°C
Active Peak
Threshold VEXT
(Transition
IVEXT,Ipeak,f
–
30
–
µA
2) Drive current I_EXTbase
IEXTbase falling
VS = 13.5 V;
;
P_7.6.27
P_7.6.10
threshold between
high-power and
low-power mode
regulator)
-40°C < Tj < 150°C
Parameters dependent on the Test Set-up (with external PNP device MJD-253)
External Regulator VEXT,out1
Output Voltage
4.9
5
5.1
V
3) SBC Normal Mode;
VEXT_VCFG=00B
including Line and
Load regulation
5.5 V < VINEXT < 28 V
10 mA < IEXT < 400 mA;
Datasheet
61
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
External Voltage Regulator
Table 21 Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; SBC Normal Mode; all outputs open; all voltages with respect to ground;
positive current defined flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
5
Unit Note or Test Condition Number
Min.
Max.
External Regulator VEXT,out2
Output Voltage
including Line and
Load regulation
4.8
5.2
V
V
V
V
V
V
V
3) SBC Stop, Sleep Mode; P_7.6.21
VEXT_VCFG=00B
5.5 V < VINEXT < 28 V
10 µA < IEXT < 20 mA;
External Regulator VEXT,out3
Output Voltage
including Line and
Load regulation
3.23
3.15
1.75
1.7
3.3V
3.3V
1.8
3.37
3.45
1.85
1.9
3) SBC Normal Mode;
VEXT_VCFG=01B
P_7.6.11
5.5 V < VINEXT < 28 V
10 mA < IEXT < 300 mA;
3) SBC Stop, Sleep Mode; P_7.6.12
VEXT_VCFG=01B
5.5 V < VINEXT < 28 V
10 µA < IEXT < 20 mA;
External Regulator VEXT,out4
Output Voltage
including Line and
Load regulation
External Regulator VEXT,out5
Output Voltage
including Line and
Load regulation
3) SBC Normal Mode;
VEXT_VCFG=10B
P_7.6.13
5.5 V < VINEXT < 28 V
10 mA < IEXT < 300 mA;
3) SBC Stop, Sleep Mode; P_7.6.14
VEXT_VCFG=10B
5.5 V < VINEXT < 28 V
10 µA < IEXT < 20 mA;
External Regulator VEXT,out6
Output Voltage
including Line and
Load regulation
1.8
External Regulator VEXT,out7
Output Voltage
including Line and
Load regulation
1.16
1.15
1.2
1.24
1.25
3) SBC Normal Mode;
VEXT_VCFG=11B
P_7.2.22
5.5 V < VINEXT < 28 V
10 mA < IEXT < 300 mA;
3) SBC Stop, Sleep Mode; P_7.6.23
VEXT_VCFG=11B
External Regulator VEXT,out8
Output Voltage
1.2
including Line and
Load regulation
5.5 V < VINEXT < 28 V
10 µA < IEXT < 20 mA;
1) Threshold at which the current limitation starts to operate.
2) Not subject to production test, specified by design.
3) Tolerance includes load regulation and line regulation.
Datasheet
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Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
8
High Speed CAN Transceiver
8.1
Block Description
VCAN
VIO
SPI Mode
Control
RTD
Driver
CANHx
CANLx
Output
Stage
TXDCANx
Temp.-
Protection
+
timeout
To SPI diagnostic
VCAN
VIO
RXDCANx
MUX
Receiver
Vs
Wake
Receiver
Figure 22 Functional Block Diagram
8.2
Functional Description
The Controller Area Network (CAN) transceiver part of the SBC provides high-speed (HS) differential mode
data transmission (up to 5 Mb) and reception in automotive and industrial applications. It works as an
interface between the CAN protocol controller and the physical bus lines compatible with ISO 11898-2, 11898-
5 and ISO11898-6 as well as SAE J2284.
The CAN transceiver offers low power modes to reduce current consumption. This supports networks with
partially powered down nodes. To support software diagnostic functions, a CAN Receive-only Mode is
implemented.
It is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks,
clamp15/30 applications).
A wake-up from the CAN wake capable mode is possible via a message on the bus. Thus, the microcontroller
can be powered down or idled and will be woken up by the CAN bus activities.
The CAN transceiver is designed to withstand the severe conditions of automotive applications and to support
12 V applications.
The different transceiver modes can be controlled via the SPI CANx bits.
Figure 23 shows the possible transceiver mode transitions when changing the SBC mode.
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
SBC Mode
CAN Transceiver Mode
SBC Stop Mode
Receive Only Wake Capable
OFF
OFF
SBC Normal Mode
SBC Sleep Mode
SBC Restart Mode
SBC Fail-Safe Mode
Receive Only Wake Capable Normal Mode
Wake Capable
OFF
OFF
Woken1
Wake Capable
1after a wake event on CAN Bus
Behavior after SBC Restart Mode - not coming from SBC Sleep Mode due to a wake up of the respective transceive:r
If the transceivers had been configured to NormalMode, or Receive Only Mode, then the mode will be changed toWake
Capable. If it was Wake Capable, then it will remainWake Capable. If it had been OFF before SBC Restart Mode, then it
will remain OFF.
Behavior in SBC Development Mode:
CAN default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF.
Figure 23 CAN Mode Control Diagram
CAN FD Support
CAN FD stands for ‘CAN with Flexible Data Rate’. It is based on the well established CAN protocol as specified
in ISO 11898-1. CAN FD still uses the CAN bus arbitration method. The benefit is that the bit rate can be
increased by switching to a shorter bit time at the end of the arbitration process and then returning to the
longer bit time at the CRC delimiter before the receivers transmit their acknowledge bits. See also Figure 24.
In addition, the effective data rate is increased by allowing longer data fields. CAN FD allows the transmission
of up to 64 data bytes compared to the 8 data bytes from the standard CAN.
Standard CAN
message
Data phase
(Byte 0 – Byte 7)
CAN Header
CAN Footer
Example:
- 11 bit identifier + 8Byte data
CAN FD with
reduced bit time
Data phase
(Byte 0 – Byte 7)
CAN Header
CAN Footer
- Arbitration Phase
- Data Phase
500kbps
2Mbps
à average bit rate
1.14Mbps
Figure 24 Bit Rate Increase with CAN FD vs. Standard CAN
CAN FD has to be supported by both the physical layer and the CAN controller. If the CAN controller cannot
support CAN FD, then the respective CAN node must at least tolerate CAN FD communication. This CAN FD
tolerant mode is implemented in the physical layer.
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
8.2.1
CAN OFF Mode
The CAN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is
intended to completely stop CAN activities or when CAN communication is not needed. The CANH/L bus
interface acts as a high impedance input with a very small leakage current. In CAN OFF Mode, a wake-up event
on the bus will be ignored.
8.2.2
CAN Normal Mode
The CAN Transceiver is enabled via SPI in SBC Normal Mode. CAN Normal Mode is designed for normal data
transmission/reception within the HS-CAN network. The mode is only available in SBC Normal Mode or SBC
Init Mode if the SBC Development Mode is used. The bus biasing is set to VCAN/2.
Transmission
The signal from the microcontroller is applied to the TXDCANx input of the SBC. The bus driver switches the
CANH/L output stages to transfer this input signal to the CAN bus lines.
Enabling sequence
The CAN transceiver requires an enabling time tCAN,EN before a message can be sent on the bus. This means
that the TXDCANx signal can only be pulled LOW after the enabling time. If this is not ensured, then the
TXDCANx needs to be set back to HIGH (=recessive) until the enabling time is completed. Only the next
dominant bit will be transmitted on the bus. Figure 25 shows different scenarios and explanations for CAN
enabling.
V
TXDCAN
t
CAN
Mode
t CAN,EN
tCAN,EN
t CAN,EN
CAN
NORMAL
CAN
OFF
t
t
V
CANDIFF
Dominant
Recessive
recessive
TXDCAN
level required
recessive TXDCAN
level required before
start of transmission
Correct sequence ,
Bus is enabled after tCAN,
tCAN, EN not ensured , no
transmission on bus
tCAN, EN not ensured ,
no transmission on bus
EN
Figure 25 CAN Transceiver Enabling Sequence
Reduced Electromagnetic Emission
To reduce electromagnetic emissions (EME), the bus driver controls CANH/L slopes symmetrically.
The slope control can be disabled using the CAN_x_Flash bits to achieve bite rate higher than 5 Mb.
Reception
Analog CAN bus signals are converted into digital signals at RXDCANx via the differential input receiver.
8.2.3
CAN Receive Only Mode
In CAN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still operational. This
mode is available in SBC Normal and Stop Mode. The bus biasing is set to VCAN/2.
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
8.2.4
CAN Wake Capable Mode
This mode can be used in SBC Stop, Sleep, Restart and Normal Mode and it is used to monitor bus activities. It
is automatically accessed in SBC Fail-Safe Mode. A valid wake-up pattern (WUP) on the bus results in a change
of behavior of the SBC, as described in Table 22. As a signalization to the microcontroller, the RXDCANx pin is
set LOW and will stay LOW until the CANx transceiver is changed to any other mode. After a wake-up event, the
transceiver can be switched to CAN Normal Mode for communication using SPI command.
As shown in Figure 26, a wake-up pattern is signaled on the bus by two consecutive dominant bus levels for
at least tWake1 (filter time t > tWake1), each separated by a recessive bus level of less than tWake2
.
Entering low-power mode,
when selective wake-up
function is disabled
or not supported
Bus recessive > tWAKE1
Ini
Wait
Bias off
Bias off
Bus dominant > tWAKE1
optional:
tWAKE2 expired
1
Bias off
Bus recessive > tWAKE1
optional:
tWAKE2 expired
2
Bias off
Bus dominant > tWAKE1
Silence expired AND
t
Entering CAN Normal
or CAN Recive Only
Device in low-power mode
3
Bias on
Bus dominant > tWAKE1
Bus recessive > tWAKE1
tSilence expired AND
device in low-power mode
4
Bias on
Figure 26 WUP detection following the definition in ISO 11898-5
Rearming the Transceiver for Wake Capability
After a bus wake-up event, the transceiver is woken. However, the CANx transceiver mode bits will still show
wake capable (=‘01’) so that the RXDCAN signal will be pulled low. There are two possibilities how the CAN
transceiver’s wake capable mode is enabled again after a wake event:
•
The CAN transceiver mode must be toggled, i.e. switched from Wake Capable Mode to CAN Normal Mode,
CAN Receive Only Mode or CAN Off, before switching to CAN Wake Capable Mode again.
•
Rearming is done automatically when the SBC is changed to SBC Stop, Sleep, or SBC Fail-Safe Mode to
ensure wake-up capability.
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
Note:
It is not necessary to clear the CAN wake-up bit CAN_x_WU to become wake capable again. It is
sufficient to toggle the CAN mode.
Wake-Up in SBC Stop and Normal Mode
In SBC Stop Mode, if a wake-up is detected, it is always signaled by the INTN output and in the WK_STAT_0,
WK_STAT_2 SPI registers. It is also signaled by RXDCANx pulled to low. The same applies for the SBC Normal
Mode. The microcontroller should set the device from SBC Stop Mode to SBC Normal Mode; there is no
automatic transition to SBC Normal Mode.
For functional safety reasons, the watchdog will be automatically enabled in SBC Stop Mode after a bus wake
event in case it was disabled before (if bit WD_EN_WK_ BUS was configured to HIGH before).
Wake-Up in SBC Sleep Mode
Wake-up is possible via a CAN message (filter time t > tWake1). The wake-up automatically transfers the SBC into
the SBC Restart Mode and from there to Normal Mode the corresponding RXDCANx pin in set to LOW. The
microcontroller is able to detect the low signal on RXDCANx and to read the wake source out of the
WK_STAT_0 or WK_STAT_2 register via SPI. No interrupt is generated when coming out of SBC Sleep Mode.
The microcontroller can now for example switch the CAN transceiver into CAN Normal Mode via SPI to start
communication.
Table 22 Action due to CAN Bus Wake-Up
SBC Mode
SBC Mode after Wake
Normal Mode
Stop Mode
VCC1
INTN
LOW
LOW
HIGH
HIGH
HIGH
RXD
LOW
LOW
LOW
LOW
LOW
Normal Mode
Stop Mode
ON
ON
Sleep Mode
Restart Mode
Fail-Safe Mode
Restart Mode
Restart Mode
Restart Mode
Ramping Up
ON
Ramping up
8.2.5
TXD Time-out Feature
If the TXDCANx signal is dominant for a time t > tTXD_CAN_TO, in CAN Normal Mode, the TXD time-out function
deactivates the transmission of the signal at the bus. This is implemented to prevent the bus from being
blocked permanently due to an error. The transmitter is disabled and the transceiver is switched to Receive
Only Mode. The failure is stored in the SPI flag CAN_x_FAIL. The CAN transmitter stage is activated again after
the dominant time-out condition is removed and the transceiver is automatically switched back to CAN
Normal Mode.The transceiver configuration stays unchanged.
8.2.6
Bus Dominant Clamping
If the HS-CAN bus signal is dominant for a time t > tBUS_CAN_TO, regardless of the CAN transceiver mode a bus
dominant clamping is detected and the SPI bit CAN_x_FAIL is set. The transceiver configuration stays
unchanged.
8.2.7
Undervoltage Detection
The voltage at the CAN supply pin is monitored in CAN Normal Mode and CAN Receiver Only Mode . In case of
VCAN undervoltage, the bit VCAN_UV is set and the SBC disables the transmitter stage. If the undervoltage
condition is not present anymore (VCAN > VCAN_UV,f), the transceiver is automatically switched back to CAN
Normal Mode. The transceiver configuration stays unchanged.
Datasheet
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Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
8.3
Electrical Characteristics
Table 23 Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
CAN Supply Voltage
CAN Supply undervoltage
detection threshold
VCAN_UV,f
4.5
–
4.75
V
V
CAN Normal Mode;
VCAN falling;
P_8.3.1
P_8.3.2
CAN Bus Receiver
Differential Receiver
Threshold Voltage,
recessive to dominant edge
Vdiff,rd_N
–
0.80
0.90
8.0
–
Vdiff = VCANH - VCANL;
-12 V ≤ VCM(CAN) ≤
+12 V;
CAN Normal Mode
1)
Dominant state differential Vdiff_D_range 0.9
input voltage range
–
V
V
V
V
= VCANH - VCANL
;
P_8.3.60
P_8.3.3
P_8.3.61
P_8.3.4
diff
-12 V ≤ VCM(CAN) ≤
+12 V;
CAN Normal Mode
Differential Receiver
Threshold Voltage,
dominant to recessive edge
Vdiff,dr_N
0.50
0.60
–
Vdiff = VCANH -VCANL;
-12 V ≤ VCM(CAN) ≤
+12 V;
CAN Normal Mode
1)
Recessive state differential Vdiff_R_range -3.0
input voltage range
0.5
V
= VCANH - VCANL
diff
;
-12 V ≤ VCM(CAN) ≤
+12 V;
CAN Normal Mode
1)
Common Mode Range
CMR
-12
20
–
12
50
V
CANH, CANL Input
Resistance
Ri
40
kΩ
CAN Normal / Wake P_8.3.5
capable Mode;
-2 V ≤ VCANH/L ≤ +7 V
Recessive state
Differential Input Resistance Rdiff
40
80
100
kΩ
CAN Normal / Wake P_8.3.6
capable Mode;
-2 V ≤ VCANH/L ≤ +7 V
Recessive state
Input Resistance Deviation DRi
between CANH and CANL
-3
–
–
3
%
1) Recessive state
VCANH = VCANL =5 V
2)
P_8.3.7
P_8.3.8
P_8.3.9
Input Capacitance CANH,
CANL versus GND
Cin
20
10
40
20
pF
pF
V
= 5 V
TXD
2)
Differential Input
Capacitance
Cdiff
–
V
= 5 V
TXD
Datasheet
68
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
Table 23 Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
0.8
Unit Note or
Test Condition
Number
Min.
Max.
Wake-up Receiver
Threshold Voltage,
recessive to dominant edge
Vdiff, rd_W
–
1.15
V
V
V
V
-12 V ≤ VCM(CAN) ≤
+12 V;
CAN Wake Capable
Mode
1) -12 V ≤ VCM(CAN) ≤ P_8.3.62
+12 V;
P_8.3.10
Wake-up Receiver Dominant Vdiff,D_range_ 1.15
state differential input
voltage range
–
8.0
–
W
CAN Wake Capable
Mode
Wake-up Receiver
Threshold Voltage,
dominant to recessive edge
Vdiff, dr_W
0.4
0.7
–
-12 V ≤ VCM(CAN) ≤
+12 V;
CAN Wake Capable
Mode
P_8.3.11
Wake-up Receiver Recessive Vdiff,R_range_W -3.0
state differential input
0.4
1) -12 V ≤ VCM(CAN) ≤ P_8.3.63
+12 V;
voltage range
CAN Wake Capable
Mode
CAN Bus Transmitter
CANH/CANL Recessive
Output Voltage
(CAN Normal Mode)
VCANL/H_NM 2.0
–
–
–
–
3.0
0.1
50
V
CAN Normal Mode;
TXD = VIO;
no load
P_8.3.12
P_8.3.13
P_8.3.14
P_8.3.15
V
CANH/CANL Recessive
Output Voltage
(CAN Wake Capable Mode)
VCANL/H_LP
-0.1
V
CAN Wake Capable
Mode; VTXD = VIO;
no load
CANH, CANL Recessive
Output Voltage Difference
Vdiff_r_N
-500
-100
mV
mV
CAN Normal Mode
VTXD = VIO;
no load
Vdiff = VCANH - VCANL
CANH, CANL Recessive
Output Voltage Difference
Vdiff = VCANH - VCANL
Vdiff_r_W
100
CAN Wake Capable
Mode;
V
TXD = VIO;
no load
CANL Dominant Output
Voltage
VCANL
0.5
–
2.25
4.5
V
V
V
CAN Normal Mode;
P_8.3.16
P_8.3.17
P_8.3.18
V
TXD = 0 V;
50 Ω ≤ RL ≤ 65 Ω
CANH Dominant Output
Voltage
VCANH
2.75
1.5
–
CAN Normal Mode;
VTXD = 0 V;
50 Ω ≤ RL ≤ 65 Ω
CANH, CANL Dominant
Vdiff_d_N
2.0
2.5
CAN Normal Mode;
Output Voltage Difference
V
TXD = 0 V;
Vdiff = VCANH - VCANL
50 Ω ≤ RL ≤ 65 Ω
Datasheet
69
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
Table 23 Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
CANH, CANL Dominant
Vdiff_d_N
1.5
5.0
V
1) CAN Normal Mode; P_8.3.58
Output Voltage Difference
V
TXD = 0 V;
Vdiff = VCANH - VCANL on
RL = 2240 Ω
extended bus load range
CANH, CANL output voltage Vdiff_slope_rd
difference slope, recessive
to dominant
–
–
–
–
70
70
V/us 1) 30% to 70% of
measured
P_8.3.47
P_8.3.48
differential bus
voltage,
CL = 100 pF, RL = 60 Ω
CANH, CANL output voltage Vdiff_slope_dr
difference slope, dominant
to recessive
V/us 1) 70% to 30% of
measured
differential bus
voltage,
CL = 100 pF, RL = 60 Ω
CANH Short Circuit Current ICANHsc
CANL Short Circuit Current ICANLsc
-100
50
–
-80
80
5
-50
100
7.5
mA
mA
µA
CAN Normal Mode;
VCANHshort = -3 V
P_8.3.20
P_8.3.21
P_8.3.22
CAN Normal Mode
VCANLshort = 18 V
Leakage Current
ICANH,lk
ICANL,lk
VS = VCAN = 0 V;
(unpowered device)
0 V < VCANH,L ≤ 5 V;
3)
R
= 0 / 47 kΩ
test
Receiver Output RXD
HIGH level Output Voltage VRXD,H
0.8 ×
VIO
–
–
–
V
V
CAN Normal Mode
IRXD(CAN) = -2 mA;
P_8.3.23
P_8.3.24
LOW Level Output Voltage
VRXD,L
–
0.2 ×
CAN Normal Mode
VIO
IRXD(CAN) = 2 mA;
Transmission Input TXD
HIGH Level Input Voltage
Threshold
VTXD,H
VTXD,L
–
–
–
0.7 ×
VIO
V
CAN Normal Mode
recessive state
P_8.3.25
P_8.3.26
P_8.3.27
P_8.3.28
LOW Level Input Voltage
Threshold
0.3 ×
VIO
–
–
V
CAN Normal Mode
dominant state
1)
TXD Input Hysteresis
VTXD,hys
–
0.12 ×
VIO
mV
TXD Pull-up Resistance
RTXD
20
8
40
13
80
18
kΩ
–
CAN Transceiver Enabling
Time
tCAN,EN
µs
8) CSN = HIGH to first P_8.3.29
valid transmitted
TXD dominant
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Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
Table 23 Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Dynamic CAN-Transceiver Characteristics
Max.
Driver Symmetry
VSYM = VCANH + VCANL
VSYM
4.5
0.5
–
5.5
V
1)4) CAN Normal
Mode;
P_8.3.19
V
V
TXD = 0 V / 5 V;
CAN= 5 V;
CSPLIT = 4.7 nF;
50 Ω ≤ RL ≤ 60 Ω
Min. Dominant Time for Bus tWake1
Wake-up
1.2
1.8
µs
-12 V ≤ VCM(CAN) ≤
+12 V;
P_8.3.30
CAN Wake capable
Mode
Wake-up Time-out,
Recessive Bus
tWake2
0.5
–
–
–
10
ms
µs
8) CAN Wake capable P_8.3.31
Mode
WUP Wake-up
Reaction Time
tWU_WUP
100
5)6)8) Wake-up
reaction time after a
valid WUP on CAN
bus;
P_8.3.32
ISO: Loop Delay (recessive to tloop,f
dominant)
–
–
150
150
255
255
ns
ns
CAN Normal Mode
CL = 100 pF;
RL = 60 Ω;
P_8.3.33
C
RXD = 15 pF
(see Figure 27)
ISO: Loop Delay (dominant tloop,r
to recessive)
CAN Normal Mode
CL = 100 pF;
P_8.3.34
RL = 60 Ω;
C
RXD = 15 pF
(see Figure 27)
Propagation Delay
TXD LOW to bus dominant
td(L),T
td(H),T
td(L),R
–
–
–
50
–
–
–
ns
ns
ns
CAN Normal Mode
CL = 100 pF;
RL = 60 Ω;
P_8.3.35
P_8.3.36
P_8.3.37
(see Figure 27)
Propagation Delay
TXD HIGH to bus recessive
50
CAN Normal Mode
CL = 100 pF;
RL = 60 Ω;
(see Figure 27)
Propagation Delay
bus dominant to RXD LOW
100
CAN Normal Mode
CL = 100 pF;
RL = 60 Ω;
CRXD = 15 pF
(see Figure 27)
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Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
Table 23 Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
100
Unit Note or
Test Condition
Number
Min.
Max.
Propagation Delay
bus recessive to RXD HIGH
td(H),R
–
–
ns
ns
CAN Normal Mode
CL = 100 pF;
RL = 60 Ω ;
CRXD = 15 pF
(see Figure 27)
P_8.3.38
Received Recessive bit width tbit(RXD)
CAN FD up to 2 Mbps
400
435
120
155
–
–
–
–
550
530
220
210
CAN Normal Mode
CL = 100 pF
P_8.3.45
P_8.3.52
P_8.3.46
P_8.3.53
RL = 60 Ω
CRXD = 15 pF
tbit(TXD) = 500 ns
Parameter definition
in according to
Figure 28.
Transmitted Recessive bit
width
CAN FD up to 2 Mbps
tbit(BUS)
ns
ns
ns
CAN Normal Mode
CL = 100 pF
RL = 60 Ω
CRXD = 15 pF
tbit(TXD) = 500 ns
Parameter definition
in according to
Figure 28.
Received Recessive bit width tbit(RXD)
CAN FD up to 5 Mbps
CAN Normal Mode
CL = 100 pF
RL = 60 Ω
CRXD = 15 pF
tbit(TXD) = 200 ns
Parameter definition
in according to
Figure 28.
Transmitted Recessive bit
width
tbit(BUS)
CAN Normal Mode
CL = 100 pF
CAN FD up to 5 Mbps
RL = 60 Ω
C
RXD = 15 pF
tbit(TXD) = 200ns
Parameter definition
in according to
Figure 28.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
Table 23 Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
Receiver timing symmetry7) ∆tRec
CAN FD up to 2 Mbps
-65
40
ns
7) CAN Normal Mode P_8.3.39
CL = 100 pF
RL = 60 Ω
CRXD = 15 pF
tbit(TXD) = 500 ns
Parameter definition
according to
Figure 28.
Receiver timing symmetry
CAN FD up to 5 Mbps
∆tRec
-45
–
15
ns
7) CAN Normal Mode P_8.3.43
CL = 100 pF
RL = 60 Ω
CRXD = 15 pF
tbit(TXD) = 200 ns
Parameter definition
according to
Figure 28.
TXD Permanent Dominant tTXD_CAN_TO
Time-out
–
2
2
–
–
ms
ms
s
8) CAN Normal Mode P_8.3.40
BUS Permanent Dominant tBUS_CAN_TO
Time-out
–
–
8) CAN Normal Mode P_8.3.41
8)
Time-out for bus inactivity tSILENCE
0.6
1.2
P_8.3.44
1) Not subject to production test, specified by design.
2) Not subject to production test, specified by design, S2P - Method; f = 10 MHz.
3) Rtest between VS/VCAN and 0 V (GND).
4) VSYM shall be observed during dominant and recessive state and also during the transition from dominant to recessive
and vice versa while TxD is simulated by a square signal (50% duty cycle) a frequency of 1 MHz.
5) Wake-up is signalized via INTN pin activation in SBC Stop Mode and via VCC1 ramping up with wake from SBC Sleep
Mode.
6) Time starts with end of last dominant phase of WUP.
7) ∆tRec = tbit(RXD) - tbit(BUS)
8) Not subject to production test, tolerance defined by internal oscillator tolerance.
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Multi-CAN Power+ System Basis Chip
High Speed CAN Transceiver
V
TXDCAN
VIO
GND
t
t
VDIFF
td(L),T
td(H),T
Vdiff, rd_N
Vdiff, dr_N
t d(L),R
td(H),R
t
t
loop,r
VRXDCAN
VIO
loop,f
0.8 x VIO
0.2 x VIO
GND
t
Figure 27 Timing Diagrams for Dynamic Characteristics
70%
TXDCAN
30%
tLoop_f
5x tBit(TXD)
tBit(TXD)
Vdiff=CANH-CANL
900mV
tBit(Bus)
500mV
70%
RXDCAN
30%
tLoop_r
tBit(RXD)
Figure 28 From ISO 11898-2: tLoop, tBit(TXD), tBit(RXD) Definition
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Wake Input
9
Wake Input
9.1
Features
V5V,in
IPU_WK
WK
+
-
tWK
IPD_WK
Logic
Figure 29 Wake Input Block Diagram
Features
•
•
•
•
•
•
One HIGH-voltage inputs with VWKth threshold voltage.
Wake-up capability for power saving modes.
Switch feature for DC/DC Mode (PFM/PWM) in SBC Stop Mode.
Sensitive for level changes LOW to HIGH and HIGH to LOW.
Pull-up and Pull-down current, selectable via SPI.
In SBC Normal and Stop Mode, the WK pin level can be read via SPI.
9.2
Functional Description
The SBC can wake up following a voltage level change at the wake input. The WK input pin is sensitive to level
changes. This means that both transitions, HIGH to LOW and LOW to HIGH, result in SBC signalling (see also
Figure 30). The signal is created in one of the following ways:
•
•
By triggering the interrupt in SBC Normal and SBC Stop Mode.
By waking up the device in SBC Sleep and SBC Fail-Safe Mode.
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Multi-CAN Power+ System Basis Chip
Wake Input
WK_LVL_STAT
WK
VWKth,hys
1
0
VWKth,min
VWKth,max VWK
Figure 30 Wake Input Threshold Levels and Hysteresis
The wake-up capability, using WK pin, can be enabled or disabled via SPI command.
When the WK is enabled (WK_EN set to 1 on WK_CTRL_1 register), the device wakes up from Sleep Mode with
a HIGH to LOW or LOW to HIGH transition on the WK pin. In SBC Stop and Normal Mode, an Interrupt will be
generated after tFWK (filter time). In SBC Fail-Safe Mode, the WK is automatically selected as wake-up source
and the device will always go to SBC Restart Mode with a HIGH to LOW or LOW to HIGH transition. The wake
source for WK pin can be read in the register WK_STAT_0 at the bit WK_WU.The state of the WK pin (LOW or
HIGH) can always be read in SBC Normal and Stop Mode at the bit WK on register WK_LVL_STAT.
The WK pin can also be configured as a selection pin for PFM / PWM mode in SBC Stop Mode using the bit
PWM_BY_WK of register HW_CTRL_0. In this case a LOW level at the WK pin will switch the Buck converter to
PFM mode, a HIGH level will switch the Buck converter to PWM Mode maintaining the SBC in SBC Stop Mode.
The filter time is not taken into account because a defined signal is expected (refer to Chapter 6.2.2.2).
In case that the PWM_BY_WK is used, it is still possible to use the WK pin to wake-up from SBC Sleep Mode to
SBC Normal Mode.
Figure 31 shows a typical wake-up timing:
VWK
VWKth
VWKth
t
t
VINTN
tFWK
tFWK
tINTN
No Wake Event
Wake Event
Figure 31 Wake-up Filter Timing for Static Sense
9.2.1
Wake Input Configuration
To ensure a defined and stable voltage level at the internal comparator input, it is possible to configure an
integrated current source via the SPI register WK_PUPD_CTRL.
Table 24 shows the possible pull-up and pull-down current configuration.
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Multi-CAN Power+ System Basis Chip
Wake Input
Table 24 Pull-Up / Pull-Down Resistor
WK_PUPD_1 WK_PUPD_0 Output Current Note
0
0
no current
source
WK is floating if left open (default setting)
0
1
pull-down
current
WK input internally pulled to GND
1
1
0
1
pull-up current WK input internally pulled to 5V
automatic
switching
If a HIGH level is detected, the pull-up current is activated
If low level is detected, the pull down current is activated.
Note:
If there is no pull-up or pull-down configured on the WK input, then the respective input should be
tied to GND or VS on board to avoid unintended floating and waking of the pin.
VWKth_min
VWKth_max
IWK
VWKth
Figure 32 Illustration for Pull-Up / Down Current Sources with Automatic Switching Configuration
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Multi-CAN Power+ System Basis Chip
Wake Input
9.3
Electrical Characteristics
Table 25 Electrical Characteristics
Tj = -40°C to +150°CTj = -40°C to +150°C; VS = 5.5 V to 28 V; all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Numbe
r
Min.
Max.
WK Input Pin characteristics
Wake-up/monitoringthreshold VWKth
voltage
2
3
4
V
Falling and rising
edge included
2)
P_9.3.1
Threshold hysteresis
WK pin Pull-up Current
WK pin Pull-down Current
Input leakage current
Timing
VWKNth,hys 0.1
–
0.7
-3
20
2
V
P_9.3.2
P_9.3.3
P_9.3.4
IPU_WK
IPD_WK
ILK,l
-20
3
-10
10
–
µA
µA
µA
VWK_IN = 4 V
VWK_IN = 2 V
0 V < VWK_IN < VS+0.3 V1) P_9.3.5
-2
2)
Wake-up filter time
tFWK
12
16
20
µs
P_9.3.6
1) With pull-up, pull down current disabled.
2) Not subject to production test; specified by design.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Interrupt Function
10
Interrupt Function
10.1
Block and Functional Description
VIO
INTN
Time
out
Interrupt logic
Figure 33 Interrupt Block Diagram
The interrupt is used to signal wake-up events in real time to the microcontroller. The interrupt block is
designed as a push/pull output stage as shown in Figure 33. An interrupt is triggered and the INTN pin is pulled
low (active low) for tINTN in SBC Normal and Stop Mode and it is released again once tINTN is expired. The
minimum HIGH-time of INTN between two consecutive interrupts is tINTD. An interrupt does not automatically
cause a SBC mode change.
The following wake-up events will be signalized via INTN:
•
•
•
•
•
All wake-up events stored in the wake status SPI register WK_STAT_0 and WK_STAT_2.
If the bit CANTO_x is set and if it was not masked out.
The VBAT (at pin VBSENSE) monitoring threshold is triggered.
An interrupt is only triggered if the respective function is also enabled as a wake source.
Automatic transition from PFM to PWM mode in SBC Stop Mode.
The register WK_LVL_STAT is not generating interrupt events.
In addition to this behavior, an INTN will be triggered when the SBC is sent to SBC Stop Mode and not all bits
were cleared in the WK_STAT_0 and WK_STAT_2registers.
The SPI status registers are updated at every falling edge of the INTN pulse. All interrupt events are stored in
the respective register (except the register WK_LVL_STAT) until the register is read and cleared via an SPI
command. The interrupt behavior is shown in Figure 34.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Interrupt Function
WK event 1
WK event 2
INTN
tINTD
tINT
Update of
WK_STAT register
Update of
WK_STAT register
optional
no WK
SPI
Read & Clear
WK_STAT
contents
WK event 1
no WK
WK event 2
SPI
Read & Clear
No SPI Read & Clear
Command sent
WK event 1 and WK
event 2
WK_STAT
contents
no WK
Figure 34 Interrupt Signaling Behavior
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Interrupt Function
10.2
Electrical Characteristics
Table 26 Interrupt Output
VS = 6 V to 28 V; Tj = -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Interrupt output; Pin INTN
INTN HIGH Output Voltage VINTN,H 0.8 × VIO
–
–
–
V
V
IINTN = -2 mA;
INTN = OFF
P_10.2.1
P_10.2.2
INTN LOW Output Voltage VINTN,L
–
0.2 × VIO
IINTN = 2 mA;
INTN = ON
1)
INTN Pulse Width
tINTN
tINTD
80
80
100
100
120
120
µs
µs
P_10.2.3
P_10.2.4
INTN Pulse Minimum
Delay Time
1) Between
consecutive pulses
Configuration Select; Pin INTN
Config Pull-down
Resistance
RCFG
–
6
250
8
–
kΩ
VINTN = 5 V
P_10.2.5
P_10.2.6
1)
Config Select Filter Time tCFG_F
10
µs
1) Not subject to production test; specified by design.
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Fail Output
11
Fail Output
11.1
Functional Description
5V_int
Ttest
SBC Init
Mode
RTEST
FO/TEST
TFO
Failure Logic
Figure 35 Fail Output Block Diagram
The Fail Output consists of a failure logic block and one LOW-side switch. In case of a failure, the FO output is
activated and the SPI bit FO_ON_STATE, in the register DEV_STAT, is set.
The Failure Output is activated due to the following failure conditions.
Failure Conditions
•
•
•
•
•
After one or two Watchdog Trigger failures depending on the configuration.
Thermal Shutdown TSD2.
VIO short to GND.
VIO overvoltage in case that VIO_OV_RST bit is set.
After four consecutive VIO undervoltage detection.
Configurations
Four different configurations can be selected. The selection is done using the pin INTN and the SPI bit CFG2.
Table 27 Reasons for Fail
Config
Event
Fail-Safe Mode Entered SPI CFG2 bit
INTN pin
1
1 × watchdog failure
no
1
External pull-up
2
1 × watchdog failure
yes
1
No ext. pull-up
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Fail Output
Table 27 Reasons for Fail (cont’d)
Config
Event
Fail-Safe Mode Entered SPI CFG2 bit
INTN pin
3
2 × watchdog failure
no
0
External pull-up
4
2 × watchdog failure
yes
0
No ext. pull-up
In order to deactivate the Fail Output, the failure conditions (e.g. TSD2) must not be present anymore and the
bit FO_ON_STATE needs to be cleared via SPI command.
In case of Watchdog fail, the deactivation of the Fail Output is only allowed after a successful WD trigger, i.e.
the FO_ON_STATE bit must be cleared.
Note:
The Fail Output pin is triggered for any of the above described failure and not only for failures
leading to the SBC Fail-Safe Mode.
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Multi-CAN Power+ System Basis Chip
Fail Output
11.2
Electrical Characteristics
Table 28 Interrupt Output
VS = 6 V to 28 V; Tj = -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Fail Output; Pin FO/TEST
FO LOW output voltage
(active)
VFO,L
IFO,H
–
0.6
–
1
V
IFO = 5 mA
P_11.2.1
P_11.2.2
P_11.2.3
P_11.2.4
P_11.2.6
P_11.2.7
FO HIGH output leakage
current (inactive)
0
2
µA
V
VFO = 28 V
FO/TEST HIGH-input voltage VTEST,H
threshold
–
–
3.5
–
–
FO/TEST LOW-input voltage VTEST,L
threshold
1.5
2.5
52
–
V
–
1)
FO/Pull-up Resistance at pin RTEST
TEST
5
10
81
kΩ
µs
V
= 0 V
TEST
1)
FO/TEST Input Filter Time
tTEST
64
1) Not subject to production test; specified by design.
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Supervision Functions
12
Supervision Functions
12.1
Reset Function
VIO
RSTN
Resetlogic
Incl. filter & delay
Figure 36 Reset Block Diagram
12.1.1
Reset Output Description
The reset output pin RSTN provides a reset information to the microcontroller, e.g. when the VIO voltage falls
below the undervoltage threshold VRT1/2/3/4. In case of a reset event due to an undervoltage on VIO, the reset
output RSTN is pulled to LOW after the filter time tRF and stays LOW as long as the reset event is present plus
a reset delay time tRD1. When connecting the SBC to battery voltage, the reset signal remains LOW initially.
When the output voltage VIO has reached the default reset threshold VRT1,f, the reset output RSTN is released
to HIGH after the reset delay time tRD1. A reset can also occur due to a Watchdog trigger failure. The reset
threshold can be adjusted via SPI; the default reset threshold is VRT1,f. The RSTN pin has an integrated pull-up
resistor. In case reset is triggered, RSTN will pull LOW for VS ≥ VPOR,f
.
The RSTN trigger timing regarding the VIO undervoltage and watchdog trigger is shown in Figure 37.
VIO
VRT1
t < tRF
The reset threshold can be
configured via SPI in SBC
Normal Mode, default is VRT1
undervoltage
t
t
tCW
tOW
tRD1
tCW
tLW
tRD1
tLW
tCW
tOW
SPI
SPI
Init
WD
Trigger
WD
Trigger
SPI
Init
tRF
RSTN
tLW= long open window
tCW= closed window
tOW= open window
t
SBC Init
SBC Normal
SBC Restart
SBC Normal
Figure 37 Reset Timing Diagram
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Multi-CAN Power+ System Basis Chip
Supervision Functions
12.1.2
Soft Reset Description
In SBC Normal and Stop Mode, It is also possible to trigger a Soft Reset via an SPI command in order to bring
the SBC into a defined state in case of failures. In this case the microcontroller must send an SPI command and
set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as this command becomes valid, the SBC is set
back to SBC Init Mode and all SPI registers are set to their default values (see SPI Chapter 13.5 and
Chapter 13.6).
As soon as the SBC is in SBC Init Mode due to a software reset, it is possible to change the device configuration
according to the FO/Test, INTN pins and CFG2 bit value. For more information, refer to Chapter 5.1.1.
Two different soft reset configurations are possible via the SPI bit SOFT_RESET_ RSTN:
•
The reset output (RSTN) is triggered when the soft reset is executed (default setting, the same reset delay
time tRD1 applies).
•
The reset output (RSTN) is not triggered when the soft reset is executed.
Note:
The device must be in SBC Normal Mode or SBC Stop Mode when sending this command.
Otherwise, the command will be ignored.
12.2
Watchdog
The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the
microcontroller stops serving the watchdog due to a lock up in the software.
Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN on the
WD_CTRL register:
•
•
Time-Out Watchdog (default value).
Window Watchdog.
The respective watchdog function can be selected and programmed in SBC Normal Mode. The configuration
remains unchanged in SBC Stop Mode.
Refer to Table 29 to match the SBC Modes with the respective Watchdog Modes.
Table 29 Watchdog Functionality by SBC Modes
SBC Mode
Watchdog Mode
Remarks
INIT Mode
Start with Long Open Window Watchdog starts with Long Open Window after RSTN
is released.
Normal Mode
WD Programmable
Window Watchdog, Time-Out watchdog or switched
OFF for SBC Stop Mode.
Stop Mode
Sleep Mode
Watchdog is fixed or OFF
OFF
SBC will start with Long Open Window when
entering Normal Mode.
Restart Mode
OFF
OFF
SBC will start with Long Open Window when
entering Normal Mode.
Fail-Safe Mode
SBC will start with Long Open Window when
entering Normal Mode.
Watchdog timing is programmed via an SPI command. As soon as the Watchdog is programmed, the timer
starts with the new setting and the Watchdog must be served.
The Watchdog is triggered by sending a valid SPI command with write access to WD_CTRL register. The trigger
SPI command is executed when the Chip Select input (CSN) becomes HIGH.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Supervision Functions
When coming from SBC Init, Restart or in certain cases Stop Mode, the watchdog timer starts with a long open
window.
The long open window (tLW) allows the microcontroller to run its initialization sequences and then to trigger
the Watchdog via the SPI.
The watchdog timer period can be selected via the watchdog timing bit field (WD_TIMER on WD_CTRL
register) and it is in the range of 10 ms up to 1000 ms. The timer setting is valid for both watchdog types.
The following Watchdog timer periods are available:
•
•
•
•
•
•
•
WD Setting 1: 10 ms
WD Setting 2: 20 ms
WD Setting 3: 50 ms
WD Setting 4: 100 ms
WD Setting 5: 200 ms (reset value)
WD Setting 6: 500 ms
WD Setting 7: 1000 ms
In case of a watchdog reset, SBC Restart Mode is started or SBC Fail-Safe Mode is entered according to the
configuration and WD_FAIL bits are set.
Once the RSTN goes HIGH again, the watchdog immediately starts with a long open window and the SBC
enters automatically in SBC Normal Mode.
In SBC Development Mode, no reset is generated due to watchdog failure; the watchdog is OFF.
In case of 3 consecutive resets due to WD fail, it is possible in config 1/3 not to generate additional resets by
setting the MAX_3_RST bit on WD_CTRL register.
12.2.1
Time-Out Watchdog
The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog
trigger can become active at any time within the configured watchdog timer period.
A correct watchdog service immediately results in starting a new watchdog timer period. Taking the
tolerances of the internal oscillator into account leads to the safe trigger area defined in Figure 38.
Typical timout watchdog trigger period
tWD x 1.50
open window
uncertainty
Watchdog Timer Period (WD_TIMER)
tWD x 1.20
tWD x 1.80
t / [tWD_TIMER
]
safe trigger area
Figure 38 Time-Out Watchdog Definitions
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Multi-CAN Power+ System Basis Chip
Supervision Functions
If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RSTN LOW
and the SBC switches to SBC Restart or SBC Fails-Safe Mode.
12.2.2
Window Watchdog
Compared to the time-out watchdog, the characteristic of the window watchdog is that the watchdog timer
period is divided between a closed and an open window. The watchdog must be triggered inside the open
window.
A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an
open window.
The watchdog timer period is at the same time the typical trigger time and defines the middle of the open
window.
Taking the oscillator tolerances into account leads to a safe trigger area of:
tWD × 0.72 < safe trigger area < tWD × 1.20.
The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking
the tolerances of the internal oscillator into account leads to the timings as defined in Figure 39.
A correct Watchdog service immediately results in starting the next closed window.
Should the trigger signal meet the closed window or should the watchdog timer period elapse, a watchdog
reset is created by setting the reset output RSTN LOW and the SBC switches to SBC Restart or Fail-Safe Mode.
tWD x 0.6
tWD x 0.9
Typ. closed window
Typ. open window
tWD x 0.48
tWD x 0.72
tWD x 1.0
tWD x 1.20
tWD x 1.80
closed window
uncertainty
open window
uncertainty
Watchdog Timer Period (WD_TIMER)
t / [tWD_TIMER
]
safe trigger area
Figure 39 Window Watchdog Definitions
12.2.3
Checksum
A checksum bit is part of the SPI command to trigger the watchdog and to set the watchdog setting. The sum
of the 8 bits in the register WD_CTRL needs to be even. This is realized by either setting the bit CHECKSUM to
“0” or “1”. If the checksum is wrong, the SPI command is ignored (watchdog not triggered, settings not
changed) and the bit SPI_FAIL is set.
The checksum is calculated by taking all 8 data bits into account.
(12.1)
CHKSUM = Bit15
…
Bit8
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Multi-CAN Power+ System Basis Chip
Supervision Functions
12.2.4
Watchdog during Stop Mode
The watchdog can be disabled via SPI in Stop Mode.
For safety reasons, there is a special sequence to be ensured in order to disable the watchdog as described in
Figure 40. Two dedicated SPI bits (WD_STM_EN_0 and WD_STM_EN_1) in the registers WD_CTRL and
WK_CTRL_0.
If this sequence is not fulfilled, then the bit WD_STM_EN_1 will be cleared and the sequence has to be started
again. As soon as the SBC is set to SBC Normal Mode, then the bits WD_STM_EN_1 and WD_STM_EN_0 are
cleared and this sequence must be followed again to switch OFF the watchdog.
The watchdog can be enabled by triggering the watchdog in SBC Stop Mode or by switching back to SBC
Normal Mode via SPI. In both cases, the watchdog will start with a long open window and the bits
WD_STM_EN_1 and WD_STM_EN_0 are cleared. After the long open window, the watchdog has to be served
as configured in the WD_CTRL register.
Correct WD disabling
Sequence Errors
sequence
•
Missing to set bit
Set bit
WD_STM_EN_1 = 1
WD_STM_EN_0 with the
next watchdog trigger after
having set WD_STM_EN_1
with next WD Trigger
•
Staying in Normal Mode
Set bit
WD_STM_EN_0 = 1
Before subsequent WD Trigger
Will enable the WD :
Change to
SBC Stop Mode
•
Switching back to SBC
Normal Mode
•
Triggering the watchdog
WD is switched off
Figure 40 Watchdog Disabling Sequence
Note:
The bit WD_STM_EN_0 will be cleared automatically when the sequence is started and it was “1”
before.
12.2.4.1 Watchdog Start in SBC Stop Mode due to BUS Wake
In SBC Stop Mode the watchdog can be disabled. In addition a feature can be enabled to start the watchdog
with any BUS wake during Stop Mode. The feature is enabled by setting the bit WD_EN_WK_ BUS. The bit can
only be changed in SBC Normal Mode and needs to be programmed before entering SBC Stop Mode: it is not
reset by the SBC. The sequence described in Chapter 12.2.4 needs to be followed to disable the WD.
With the function enabled, the watchdog will start again with any wake on CANx. The wake on CANx will
generate an interrupt and the RXDCANx is pulled to low. The watchdog starts a with long open window. The
watchdog can be triggered in SBC Stop Mode or the SBC can be switched to SBC Normal Mode. To disable the
watchdog again, the SBC needs to be switched to Normal Mode and the sequence needs to be sent again.
The sequence is shown in Figure 41.
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Multi-CAN Power+ System Basis Chip
Supervision Functions
Correct WD disabling
sequence
Sequence Errors
•
Missing to set bit
Set bit
WD_EN_WK_BUS = 1
WD_STM_EN_0 with the
next watchdog trigger after
having set WD_STM_EN_1
•
Staying in Normal Mode
Set bit
WD_STM_EN_1 = 1
with next WD Trigger
Will enable the WD:
Set bit
WD_STM_EN_0 = 1
•
Switching back to SBC
Normal Mode
Before subsequent WD Trigger
•
•
Triggering the watchdog
Wake on CANx
Change to
SBC Stop Mode
WD is switched off
Figure 41 Watchdog Disabling Sequence (with wake via BUS)
12.3
VS Power ON Reset
When powering up, the device detects the VS Power ON Reset when VS > VPOR,f, and the POR is set to indicate
that all SPI registers are set to POR default setting. The Buck regulator starts up. The RSTN output is kept LOW
and is only released when VIO has exceeded VRT1,r and after tRD1 has elapsed.
If VS<VPOR,f, an internal reset is generated and the SBC is switched OFF. The SBC will restart in SBC INIT Mode
when VS>VPOR,r rising. Timing behavior is shown in Figure 42.
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Multi-CAN Power+ System Basis Chip
Supervision Functions
VS
VPOR,r
VPOR,f
t
t
VIO
VRT1,r
The reset threshold can be
configured via SPI in SBC
Normal Mode, default is VRT1
VRTx,f
RSTN
SBC Restart Mode is
entered whenever the
Reset is triggered
t
tRD1
SBC Mode
Re-
start
SBC OFF
SBC INIT MODE
Any SBC MODE
SBC OFF
t
SPI
Command
Figure 42 Ramp up / down example of Supply Voltage
12.4
Measurement Interface
The measurement interface is sensing the voltage on WK and VBSENSE pin, converting to digital using a 8 bit
SAR high input voltage analog to digital converter and store the value in ADC_STAT.
The input selection (between WK pin or VBSENSE pin) is made by ADC_SEL bit on HW_CTRL_1 register.
The feature is available only in SBC Normal Mode. In SBC Stop, Sleep and Fail Safe Mode, the feature is
automatically disabled to reduce current consumption. Figure 43 shows the block diagram.
WK
8 bit ADC
External Voltage 1
External Voltage 2
ADC_STAT
MUX
VBSENSE
ADC_sel bit
On HW_CTRL_1
Figure 43 Measure Interface: basic concept implementation.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Supervision Functions
12.5
Fast Battery Voltage Monitoring
A battery monitoring feature is implemented in the TLE9278-3BQX in order to provide a fast signalization path
to the microcontroller in case of low battery voltage condition.
The block diagram is shown in Figure 44. The functionality is as follows:
•
The battery voltage is monitored on the dedicated pin VBSENSE (see also the application diagram in
Chapter 14.1).
•
If the voltage falls below the selected threshold, an interrupt is triggered at the INTN pin and the bit
VBAT_UV_ LATCH in the register WK_STAT_2 is set.
•
•
The bit can be cleared via an SPI if the voltage is above the thresholds again.
The bit VBAT_UV_ STATE in the register WK_LVL_STAT is showing the actual level of the comparator
output, i.e. if the battery voltage is below or above the selected monitoring threshold.
•
•
The monitoring threshold can be selected via SPI bit with VBSENSE_CFG in the WK_CTRL_0 register. The
feature can be enable in SBC Normal, Stop and Restart Mode using VBSENSE_EN bit on the WK_CTRL_0
register. Four thresholds are available: VBSENSE0,f...VBSENSE3,f
.
The Fast Battery voltage monitoring feature is filtered with the time tF_VBSENSE
.
VBSENSE
Vref
State
Machine
INTN
SPI
controlled
GND
Figure 44 Fast Battery Voltage Monitoring Block Diagram
12.6
VBSENSE Boost deactivation
In case of low battery voltage conditions, where the Boost module can operate out of nominal functional
range, it is possible to disable the boost and supply the VS pin only with the output boost capacitor.
The BST_VB_UV_ OFF bit enable this feature.
As soon as the battery voltage is crossing the BoostOFF,th threshold, the boost is disabled and VB_UV_BST is
set.
The Boost is automatically enabled when the VBSENSE is crossing BoostON,th threshold.
The VB_UV_BST bit has to be cleared manually.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Supervision Functions
12.7
VIO Undervoltage and Undervoltage Prewarning
A first-level voltage detection threshold is implemented as a prewarning for microcontroller. The prewarning
event is signaled with the bit VIO_WARN. No other actions are taken.
As described in Chapter 12.1 and shown in Figure 45, when the VIO voltage reaches the undervoltage
threshold (VRTx), a reset will be triggered (RSTN pulled ‘LOW’), the bit VIO_UV is set and the SBC will enter SBC
Restart Mode.
Note:
The VIO_WARN and VIO_UV bits are not set in SBC Sleep Mode as VIO = 0 V in this case.
VIO
VRTx
t
t
tRF
tRD1
RSTN
SBC Normal
Figure 45 VIO Undervoltage Timing Diagram
SBC Restart
SBC Normal
An additional safety mechanism is implemented to avoid repetitive VIO undervoltage resets:
•
•
•
A counter is increased for every consecutive VIO undervoltage event.
The counter is active in SBC Init, Normal and Stop Mode and as VS > VS,UV
.
A 4th consecutive VIO undervoltage events will lead to SBC Fail-Safe Mode entry and to setting the bit
VIO_UV_FS.
•
The counter is cleared when:
–
–
–
SBC Fail-Safe Mode is entered.
The bit VIO_UV is cleared.
A Soft Reset is triggered.
Note:
It is recommended to clear the VIO_UV bit once it was set and detected.
12.8
VIO Overvoltage
For fail safe reasons, a configurable VIO overvoltage detection feature is implemented.
In case the VIO,OV,r threshold is crossed, the SBC triggers following measures depending on the configuration:
•
•
The bit VIO_OV is always set.
If the bit VIO_OV_RST is set in config 1/3, then SBC Restart Mode is entered. The FO output is activated.
After the reset delay time (tRD1), the SBC Restart Mode is exited and SBC Normal Mode is resumed even if
the VIO overvoltage event is still present (see also Figure 46). The VIO_OV_RST bit is cleared
automatically.
•
If the bit VIO_OV_RST is set in config 2/4, then SBC Fail-Safe Mode is entered and FO output is activated.
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Multi-CAN Power+ System Basis Chip
Supervision Functions
If the VIO_OV_RST bit is not set, one overvoltage event on VIO pin will set the VIO_OV bit but no reset is
generated and FO remains OFF. The SBC doesn’t change the SBC mode.
VIO
VIO,OV
t
tOV_filt
RSTN
tRD1
t
SBC Normal
SBC Restart
SBC Normal
Figure 46 VIO Overvoltage Timing Diagram
12.9
VIO Short Circuit
The following protection feature is implemented for VIO:
•
If PCFG = GND: when VIO stays below the undervoltage threshold VRTx for more than tVIO,SC, the SBC enters
SBC Fail-Safe Mode and turns off VCC1 and VEXT. This feature is available only if VS > VS,UV and
VCC1 > VCC1,UV. In addition, the SPI status bit VIO_SC is set. The SBC can exited SBC Fail Safe Mode via a
wake-up event on CANx and/or WK pin.
•
If PCFG = Open: when VIO stays below the undervoltage threshold VRTx for more than tVIO,SC, the SBC
enters SBC Fail-Safe Mode and turns off VCC1. This feature is available only if Vs > VS,UV. In addition the SPI
status bit VIO_SC is set. The SBC can exited SBC Fail Safe Mode via a wake-up event on CANx and/or WK pin.
12.10
VEXT Undervoltage
Following protection feature is implemented for VEXT if PCFG = Open:
If VEXT drops below the VEXT,UV threshold, the SPI bit VREG_UV is set and can only be cleared via SPI.
If PCFG = GND, the VREG_UV refers to VCC1 undervoltage (VCC1 < VCC1,UV).
•
Note:
The VREG_UV flag is not set during turn-on or turn-off of VEXT.
12.11
Thermal Protection
The thermal protection mechanism is designed in such a way that the individual modules (VCC1, CANx, Boost
and VEXT) can remain active on as long as possible in case of high temperature. The following thermal
protection features are available and signaled via SPI:
•
•
Thermal Prewarning TjPW
Overtemperature Protection:
–
Overtemperature shut down with 2 levels of priority (TSD1 for peripherals and TSD2 for
microcontroller supply).
–
–
The TSD1 status bit is a combination of CANx, Boost and VEXT thermal shutdown (if PCFG is open).
The TSD2 status bit is related to VCC1 only if PCFG = open, and VCC1 together with VEXT if PCFG=GND.
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Multi-CAN Power+ System Basis Chip
Supervision Functions
–
If PCFG is open and the VEXT base driver sensor detected that TjTSD1 has been reached, it is switched
OFF as an initial protection measure. The control bits (VEXT_ON bits on M_S_CTRL register) are reset
and the bits VEXT_OT and TSD1 are set. The other output stages are not affected if their TjTSD1
threshold is not reached. When the overtemperature event is not present anymore, the VEXT must be
switched ON by setting the VEXT_ON bit.
–
–
If PCFG = GND and the VEXT base driver sensor detected that TjTSD2 has been reached, it is switched OFF
as an initial protection measure. The VEXT_OT and TSD2 are set.
If one of the CANx output stages reaches the TjTSD1 temperature threshold, then the transmitter is
switched OFF individually as first-level protection measure. The respective control bits are not reset
and the TSD1 and CAN_x_FAIL bits are set. The CANx drivers are automatically switched on again when
the overtemperature condition is no longer present. The user has to reset the BUS_STAT_0 and
BUS_STAT_2 registers via SPI.
–
If VCC1 reaches the TjTSD2 temperature threshold, the SBC is sent to SBC Fail-Safe Mode. The SBC stays
in SBC Fail-Safe Mode for at least tTSD2 (typ.1s) after the TSD2 event is not present anymore. The
VCC1_OT is set.The default wake sources CANx and WK are enabled together with the Fail Safe output.
–
–
Boost Switched OFF in case of TSD1 along with the BOOST_OT bit. The Boost has to activate again
setting the BOOST_EN after the thermal shutdown event.
Once the respective bits (TSD1, TSD2) are set, they can be cleared via SPI if the condition is not present
anymore.
12.11.1 Temperature Prewarning
As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1
reaches the thermal prewarning temperature threshold TjPW. Then the status bit TPW is set. This bit can only
be cleared via SPI once the overtemperature is not present anymore. The thermal prewarning is only active if
the VCC1 is in PWM mode.
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Multi-CAN Power+ System Basis Chip
Supervision Functions
12.12
Electrical Characteristics
Table 30 Electrical Specification
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
VIO Monitoring, Reset Generator with VIO = VCC1 = 5 V and PCFG open; Pin RSTN
Undervoltage Prewarning
Threshold Voltage
VPW,f
4.6
4.7
4.85
V
VIO falling,
VIO_WARN bit is
set
P_12.10.50
Undervoltage Prewarning
Threshold Voltage
VPW,r
VRT1,f
VRT1,r
VRT2,f
VRT2,r
VRT3,f
4.65
4.5
4.80
4.6
4.7
3.9
4.0
3.3
4.95
4.75
4.85
4.05
4.15
3.45
V
V
V
V
V
V
VIO rising
P_12.10.51
P_12.10.1
P_12.10.2
P_12.10.3
P_12.10.4
P_12.10.5
Reset Threshold
Voltage RT1,f
default setting;
VIO falling
Reset Threshold
Voltage RT1,r
4.6
Default setting;
VIO rising
Reset Threshold
Voltage RT2,f
3.75
3.85
3.15
SPI option;
VIO falling
Reset Threshold
Voltage RT2,r
SPI option;
VIO rising
Reset Threshold
Voltage RT3,f
SPI option;
VS ≥ 4 V;
VIO falling
Reset Threshold
Voltage RT3,r
VRT3,r
VRT4,f
VRT4,r
3.25
2.4
3.4
3.55
2.8
V
V
V
SPI option;
VS ≥ 4V ;
VIO rising
P_12.10.6
P_12.10.52
P_12.10.53
Reset Threshold
Voltage RT4,f
2.55
2.75
SPI option;
VS ≥ 4 V;
VIO falling
Reset Threshold
Voltage RT4,r
2.5
2.9
SPI option;
VS ≥ 4 V;
VIO rising
VIO Monitoring, Reset Generator with VIO = VEXT = 3.3 V and PCFG to GND; Pin RSTN
Undervoltage Prewarning
Threshold Voltage
VPW,f
3.0
3.1
3.2
V
VIO falling,
VIO_WARN bit is
set
P_12.10.57
Undervoltage Prewarning
Threshold Voltage
VPW,r
VRT1,f
VRT1,r
3.10
2.95
3.0
3.2
3.27
3.15
3.2
V
V
V
VIO rising
P_12.10.58
P_12.10.34
P_12.10.35
Reset Threshold
Voltage RT1,f
3.05
3.1
Default setting;
VIO falling
Reset Threshold
Voltage RT1,r
Default setting;
VIO rising
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Multi-CAN Power+ System Basis Chip
Supervision Functions
Table 30 Electrical Specification (cont’d)
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
2.6
Unit Note or
Test Condition
Number
Min.
Max.
Reset Threshold
Voltage RT2,f
VRT2,f
VRT2,r
VRT3,f
2.5
2.7
V
V
V
SPI option;
VIO falling
P_12.10.36
P_12.10.37
P_12.10.38
Reset Threshold
Voltage RT2,r
2.55
2.2
2.65
2.3
2.75
2.4
SPI option;
VIO rising
Reset Threshold
Voltage RT3,f
SPI option;
VS ≥ 4 V;
VIO falling
Reset Threshold
Voltage RT3,r
VRT3,r
VRT34f
VRT4,r
2.25
2.0
2.35
2.1
2.45
2.2
V
V
V
SPI option;
VS ≥ 4 V;
VIO rising
P_12.10.39
P_12.10.55
P_12.10.56
Reset Threshold
Voltage RT4,f
SPI option;
VS ≥ 4 V;
VIO falling
Reset Threshold
Voltage RT4,r
2.05
2.15
2.25
SPI option;
VS ≥ 4 V;
VIO rising
VIO Monitoring, Overvoltage detection
VIO Overvoltage Detection VIO,OV,r
Threshold
5.3
5.2
3.5
3.45
12
5.5
5.7
5.6
3.75
3.7
21
V
V
V
V
1) Rising VIO
VCC1 = VIO = 5 V;
PCFG = open;
1) Falling VIO
VCC1 = VIO = 5 V;
PCFG = open;
1) Rising VIO
VEXT = VIO = 3.3 V
PCFG = GND
1) Falling VIO
VEXT = VIO = 3.3 V
PCFG = GND
1)
P_12.10.8
P_12.10.44
P_12.10.41
P_12.10.45
VIO Overvoltage Detection VIO,OV,f
Threshold
5.4
VIO Overvoltage Detection VIO,OV,r
Threshold
3.63
3.56
15
VIO Overvoltage Detection VIO,OV,f
Threshold
VIO Overvoltage filter time tVIO,OV
µs
V
P_12.10.60
P_12.10.11
VIO Monitoring, Reference Supply Undervoltage detection
VS Undervoltage Detection VS,UV
5.3
5.65
6.0
Supply UV
Threshold
supervision for
VIO PCFG = open;
includesrisingand
falling threshold
VCC1 Undervoltage
Detection Threshold
VCC1,UV
4.5
3.2
4.6
4.75
4.8
V
Supply UV
supervision for
VIO
1)
P_12.10.78
P_12.10.10
VIO Short to GND Filter Time tVIO,SC
4
ms
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Supervision Functions
Table 30 Electrical Specification (cont’d)
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Electrical Characteristics RSTN
Reset LOW Output Voltage VRSTN,LOW
–
0.2
–
0.4
V
V
IRSTN = 1 mA for
VIO≥ 1 V
P_12.10.12
P_12.10.13
Reset HIGH Output Voltage VRSTN,HIGH
0.7 ×
VIO
+
IRSTN = -20 µA
VIO
0.3 V
Reset Pull-up Resistor
Reset Filter Time
RRSTN
tRF
10
4
20
10
40
kΩ
VRSTN = 0 V
P_12.10.14
P_12.10.15
1)
26
µs
V < VRT1×
IO
to RSTN = L
1)2)
Reset Delay Time
tRD1
1.5
4.5
2
2.5
ms
V
P_12.10.16
P_12.10.17
VEXT Monitoring (PCFG = Open)
VEXT Undervoltage Detection VEXT,UV
4.6
4.75
5 V option
VEXT_VCFG=00B
falling
V
EXT Undervoltage Detection VEXT,UV
2.65
1.45
0.94
20
2.85
1.52
1.03
100
3.00
1.6
V
3.3 V option
VEXT_VCFG=01B
falling
P_12.10.46
P_12.10.61
P_12.10.62
P_12.10.63
VEXT Undervoltage Detection VEXT,UV
VEXT Undervoltage Detection VEXT,UV
V
1.8 V option
VEXT_VCFG=10B
falling
1.1
V
1.2 V option
VEXT_VCFG=11B
falling
1)
VEXT Undervoltage detection VEXT,UV, hys
250
mV
hysteresis
Watchdog Generator
Long Open Window
Internal Oscillator
1)
tLW
160
0.8
200
1.0
240
1.2
ms
P_12.10.18
P_12.10.19
fCLKSBC
MHz
Minimum Waiting Time during SBC Fail-Safe Mode
1)3)
Min. waiting time in Fail-Safe tFS,min
80
100
120
ms
P_12.10.20
Power-ON Reset, Over-/Undervoltage Protection
Vs Power ON reset rising
Vs Power ON reset falling
Battery Voltage Monitoring
VPOR,r
VPOR,f
4.5
–
–
–
5
3
V
V
Vs increasing
Vs decreasing
P_12.10.21
P_12.10.22
VBSENSE Monitoring
Threshold 0
VBSENSE0,f
VBSENSE1,f
7.5
5.7
8.0
6.0
8.5
6.3
V
V
VBSENSE
decreasing
P_12.10.24
P_12.10.25
VBSENSE Monitoring
Threshold 1
VBSENSE
decreasing
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Supervision Functions
Table 30 Electrical Specification (cont’d)
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
4.5
Unit Note or
Test Condition
Number
Min.
Max.
VBSENSE Monitoring
Threshold 2
VBSENSE2,f
VBSENSE3,f
4.2
4.8
V
VBSENSE
P_12.10.26
P_12.10.27
P_12.10.28
P_12.10.48
P_12.10.49
P_12.10.80
decreasing
VBSENSE Monitoring
Threshold 3
3.2
3.5
3.8
200
21
2
V
VBSENSE
decreasing
1)
VBSENSE Monitoring
Threshold Hysteresis
VBSENSE,hys 50
100
16
mV
µs
V
1)
VBSENSE Monitoring Filter tF_VBSENSE
Time
13
VBSENSEBoostdeactivation BoostOFF,th 1.5
threshold
1.75
2.75
VBSENSE falling
VBSENSE rising
VBSENSE Boost activation
threshold
BoostON,th 2.5
3
V
Overtemperature Shutdown
1)
Thermal Prewarning ON
Temperature
TjPW
125
145
165
°C
P_12.10.29
1)
1)
1)
Thermal Shutdown TSD1
Thermal Shutdown TSD2
TjTSD1
TjTSD2
THYS
165
165
–
185
185
20
200
200
–
°C
°C
°C
P_12.10.30
P_12.10.31
P_12.10.81
Thermal Shutdown
Hysteresis
1)
Deactivation time after
thermal shutdown TSD2
tTSD2
0.8
1
1.2
s
P_12.10.32
Measurement Interface
Resolution
–
–
8
–
Bits
Input voltage full P_12.10.70
scale = 0V ..39 V
Guarantee offset error
-1
+1
LSB Input voltage full P_12.10.71
scale = 0V ..39 V
Gain error
–
–
-1.5
-1.5
–
–
1.5
1.5
%FSR Full scale range
P_12.10.72
Differential non-linearity
(DNL)
LSB Input voltage full P_12.10.73
scale = 0 V..39 V
Integral non-linearity (INL)
–
-1.5
–
1.5
LSB Input voltage full P_12.10.74
scale = 0 V..39 V
1) Not subject to production test; specified by design.
2) The reset delay time will start when VIO crosses above the selected VRTx threshold.
3) This time applies for all failure entries except a device thermal shutdown (TSD2 has a 1 s waiting time tTSD2).
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13
Serial Peripheral Interface
13.1
SPI Protocol Description
The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input
CLK provided by the microcontroller. The output word appears synchronously at the data output SDO (see
Figure 47).The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW
active. After the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to
the content. The SDO output switches to tristate status (HIGH impedance) at this point, thereby releasing the
SDO bus for other use.The state of SDI is shifted into the input register with every falling edge on CLK. The state
of SDO is shifted out of the output register after every rising edge on CLK. The SPI of the SBC is not daisy-chain
capable.
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
time
CSN low to high: data from shift register is transferred to output functions
CLK
time
Actual data
New data
0 1
+ +
SDI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
time
SDI: will accept data on the falling edge of CLK signal
Actual status
New status
0
1
+
ERR
SDO
ERR
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-
+
time
SDO: will change state on the rising edge of CLK signal
Figure 47 SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure
compared to the register description)
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.2
Failure Signalization in the SPI Data Output
When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong
SPI commands are either invalid SBC mode commands or commands which are prohibited by the state
machine to avoid undesired device or system states (see below). In this case the diagnosis bit ‘SPI_FAIL’ is set
and the SPI Write command is ignored (mostly no partial interpretation). This bit can only be reset by actively
clearing it via a SPI command.
Invalid SPI Commands leading to SPI_FAIL are listed below:
•
Illegal state transitions: going from SBC Stop to SBC Sleep Mode. In this case the SBC additionally enters
the SBC Restart Mode.
Trying to go to SBC Stop or SBC Sleep mode from SBC Init Mode. In this case SBC Normal Mode is entered.
•
•
Uneven parity in the data bit of the WD_CTRL register. In this case either the watchdog trigger is ignored
or the new watchdog settings are ignored.
In SBC Stop Mode: attempting to change any SPI settings , e.g. changing the watchdog configuration
during SBC Stop Mode.
the SPI command is ignored in this case.
The following are allowed in SBC Stop Mode: WD trigger, returning to SBC Normal Mode , triggering a SBC
Soft Reset, set to SBC Stop Mode (to return from PWM to PFM following an automatic Buck mode
transition) and Read & Clear status register commands are valid SPI commands in SBC Stop Mode.
•
•
•
When entering SBC Stop Mode and WK_STAT_0 and WK_STAT_2 are not cleared; SPI_FAIL will not be set
but the INTN pin will be triggered.
When changing from SBC Stop to Normal Mode, any attempt to change the bits on the M_S_CTRL register
will be ignored (SBC remains in SBC Stop Mode). Only VIO_OV_RST and VIO_RT set the SPI_FAIL bit.
SBC Sleep Mode: attempt to go to Sleep Mode when all bits in the BUS_CTRL_0, BUS_CTRL_2,
BUS_CTRL_3 and WK_CTRL_1 registers are cleared (i.e. no wake sources are activated). In this case the
SPI_FAIL bit is set and the SBC enters SBC Restart Mode.
Even though the SBC Sleep Mode command is not entered in this case, the rest of the command (e.g
modifying VEXT) is executed and the values stay unchanged during SBC Restart Mode.
Note: at least one wake source must be activated in order to avoid a deadlock situation in SBC Sleep Mode,
i.e. the SBC would not be able to wake up anymore.
No failure handling occurs for the attempt to go to SBC Stop Mode when all bits in the registers
BUS_CTRL_0, BUS_CTRL_2, BUS_CTRL_3 and WK_CTRL_1 are cleared because the microcontroller can
leave this mode via SPI.
•
After the first VEXT on command, the VEXT_VCFG bits can no longer be changed. if the microcontroller
tries to modify the VEXT_VCFG bits, then the rest of the command is executed but VEXT_VCFG will remain
unchanged.
•
•
The Boost output voltage can be changed only if BOOST_EN is set to 0. If the Boost output voltage is
changed with BOOST_EN=1, the SPI_FAIL bit is set and the SPI command is ignored.
SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’.
Signalization of the ERR flag in the SPI data output (see Figure 47):
The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set
for the following conditions:
•
•
In case the number of received SPI clocks is not 0 or 16.
In case RSTN is LOW and SPI frames are being sent at the same time.
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Note:
In order to read the SPI ERR flag property, CLK must be low when CSN is triggered, i.e. the ERR bit is
not valid if the CLK is high on a falling edge of CSN.
The number of received SPI clocks is not 0 or 16:
The number of received input clocks is supervised to be 0 or 16 clock cycles and the input word is discarded in
case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high
during the CSN edges. Both errors, 0 bit and 16 bit CLK mismatch or CLK high during CSN edges are flagged in
the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the
clock is received. The error logic also recognizes if CLK was HIGH during CSN edges. The entire SPI command
is ignored in these cases.
RSTN is LOW and SPI frames are being sent at the same time:
The ERR flag will be set when the RSTN pin is triggered (during SBC Restart Mode) and SPI frames are being
sent to the SBC at the same time. The behavior of the ERR flag signaled at the next SPI command when the
condition below are present:
•
•
•
If the command begins when RSTN is HIGH and ends when RSTN is LOW.
If an SPI command is sent while RSTN is LOW.
If an SPI command begins when RSTN is LOW and ends when RSTN is HIGH.
And the SDO output will behave as follows:
•
•
When RSTN is LOW, SDO is always HIGH.
When SPI command begins with RSTN is LOW and ends when RSTN is HIGH, then the SDO should be
ignored because wrong data will be sent.
Note:
Note:
It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled
low and SDO is observed - no SPI clocks are sent in this case.
The ERR flag could also be set after the SBC has entered SBC Fail-Safe Mode because SPI
communication stops immediately.
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.3
SPI Programming
For TLE9278, 7 bits are used for the address selection (6...0). Bit 7 is used to control the SPI Access, i.e. to decide
between Read Only (if set to ‘0’) and Read_Clear (if set to ‘1’) for the status bits, and between Write (if set to
‘1’) and Read Only (if set to ‘0’) for configuration bits. For the actual configuration and status information, 8
data bits (15...8) are used.
Writing, clearing and reading is done byte wise. SPI configuration and status bits are not cleared automatically
and must be cleared by the microcontroller, e.g. if the TSD2 was set due to overtemperature. The
configuration bits will be partially automatically cleared by the SBC (refer to the description of the individual
registers for detailed information). During SBC Restart, Sleep or Fail-Safe mode, the SPI communication is
ignored by the SBC, i.e. it is not interpreted.
There are two types of SPI registers:
•
•
Control registers: Those are the registers to configure the SBC, e.g. SBC mode, watchdog trigger, etc.
Status registers: Those are the registers where the status of the SBC is signalled, e.g. wake-up events,
warnings, failures, etc.
For the status registers, the requested information is given in the same SPI command in DO.
For the control registers, also the status of the respective bit is shown in the same SPI command, but if the
setting is changed this is only shown with the next SPI command (it is only valid after CSN HIGH) of the same
register.
The SBC status information from the SPI status registers, is transmitted in a compressed way with each SPI
response on SDO in the so called Status Information Field register (see also Figure 48).
LSB
MSB
DI
0
1
2
3
4
5
6
7
8
x
9
x
10 11 12 13 14 15
R/W
Address Bits
Data Bits
x
x
x
x
x
x
Register content of
selected address
DO
0
1
2
3
4
5
6
7
8
x
9
x
10 11 12 13 14 15
Data Bits
Status Information Field
x
x
x
x
x
x
time
LSB is sent first in SPI message
Figure 48 SPI Operation Mode
The purpose of this register is to quickly signal the information to the microcontroller if there was a change in
one of the SPI status registers. In this way, the microcontroller does not need to read constantly all the SPI
status registers but only those registers, which were changed. Each bit in the Status Information Field
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
represents a SPI status register or a combinational OR of two status registers (see Table 31). As soon as one
bit is set in one of the status registers, the respective bit in the Status Information Field register is set. The
register WK_LVL_STAT is not included in the status information field. This is listed in Table 31:
Table 31 Status Information Field
Status Information Bit Symbol Address Bit
Status Register
0
100 0001
SUP_STAT_0 & SUP_STAT_1 (Combinational OR):
Supply Status (VCC1 and VEXT), POR
1
2
100 0010
100 0011
THERM_STAT: Thermal Protection Status
DEV_STAT: Device Status - Mode before Wake, WD Fail,
SPI Fail, Failure
3
4
100 0100
100 0101
BUS_STAT_0: Bus Failure Status: CAN0, VCAN
BUS_STAT_2 & BUS_STAT_3 (Combinational OR): Bus
Failure Status: CAN1, CAN2 and CAN3
5
6
7
100 0110
100 1001
100 1100
WK_STAT_0: Wake Source Status for CAN0, WK, Timer
and PFM-to-PWM transition
WK_STAT_2: Wake Source Status for CAN1, CAN2,
CAN3, and VBAT_UV
SMPS_STAT: SMPS Status
For example if bit 2 in the Status Information Field is set to 1, one or more bits of the register DEV_STAT is set
to 1. Then this register needs to be read in a second SPI command. The bit in the Status Information Field will
be set to 0 when all bits in the register DEV_STAT are set back to 0.
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.4
SPI Bit Mapping
13.4.1
SPI Mapping Structure
Figure 49 and Figure 49 show the mapping of the SPI bits and the respective registers.
Depending on bit 7, the bits are only read or also written. The Control Registers ‘000 0001’ to ‘011 1111’ are
READ/WRITE Registers.
The new setting of the bit after write can be seen with the next read / write command. An exception are the
registers ‘011 101x’, which are Read Only registers needed for the oscillator re-configuration.
The registers ‘100 0000’ to ‘111 1110’ are Status Registers and can be read or read with clearing the bit (if
possible) depending on bit 7. To clear a Data Byte of one of the Status Registers, bit 7 must be set to 1. The
register WK_LVL_STAT is an exception as it shows the actual voltage level at the respective pin (LOW/HIGH)
and thus can not be cleared.
When changing to a different SBC Mode, certain configurations and status bits will be modified by the SBC:
•
•
The SBC Mode bits are updated to the actual status, e.g. when returning to SBC Normal Mode.
In SBC Sleep Mode the CANx control bits will be modified in CANx wake capable if they were ON before.
FO will stay activated if it was triggered before.
•
•
In general, the configurations is only possible in SBC Normal Mode. Diagnosis are also active in SBC Stop
Mode (e.g. UV, OT). VEXT can be also active in Low power mode (Stop/Sleep).
Depending on the respective configuration, CANx transceivers will be either OFF, woken or still wake
capable.
13.4.2
SPI Register Banking
The CAN Selective Wake configuration registers consume a lot of address space but do not need to be
accessed very often.
Therefore, the CAN Selective Wake configuration for the CAN modules is managed by banking. The respective
bank is selected via the CAN_SWK bits in BUS_CTRL_3. All registers with the attribute “banked”, as shown in
Chapter 13.4.3, will then be accessible for the selected CAN module.
The Status Registers for the CAN Selective wake are not banked to allow a quick diagnosis.
Datasheet
105
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.4.3
SPI Mapping Tables
7
6...0
Register Short Name
banked
Access
Control
Address
A6…A0
C O N T R O L R E G I S T E R S
M_S_CTRL
HW_CTRL_0
WD_CTRL
no
no
no
no
no
no
no
no
no
no
no
no
read/write
0000001
0000010
0000011
0000100
0000110
0000111
0001000
0001010
0001011
0001100
0001110
0011110
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
BUS_CTRL_0
WK_CTRL_0
WK_CTRL_1
WK_PD_CTRL
BUS_CTRL_2
BUS_CTRL_3
TIMER_CTRL
HW_CTRL_1
SYS_STAT_CTRL
S E L E C T I V E W A K E R E G I S T E R S
SWK_CTRL
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
SWK_BTL1_CTRL
SWK_BTL2_CTRL
SWK_ID3_CTRL
SWK_ID2_CTRL
SWK_ID1_CTRL
SWK_ID0_CTRL
SWK_MASK_ID3_CTRL
SWK_MASK_ID2_CTRL
SWK_MASK_ID1_CTRL
SWK_MASK_ID0_CTRL
SWK_DLC_CTRL
SWK_DATA7_CTRL
SWK_DATA6_CTRL
SWK_DATA5_CTRL
SWK_DATA4_CTRL
SWK_DATA3_CTRL
SWK_DATA2_CTRL
SWK_DATA1_CTRL
SWK_DATA0_CTRL
SWK_CAN_FD_CTRL
S W K T R I M & C O N F I G. R E G I S T E R S
SWK_OSC_TRIM_CTRL
SWK_OPT_CTRL
SWK_OSC_CAL_H_STAT
SWK_OSC_CAL_L_STAT
SWK_CDR_CTRL1
SWK_CDR_CTRL2
SWK_CDR_LIMIT_HIGH_CTRL
SWK_CDR_LIMIT_LOW_CTRL
no
no
no
read/write
read/write
read
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
no
read
yes
yes
yes
yes
read/write
read/write
read/write
read/write
S T A T U S R E G I S T E R S
SUP_STAT_1
no
no
no
no
no
no
no
no
no
no
no
no
read/clear
1000000
1000001
1000010
1000011
1000100
1000110
1001000
1001001
1001010
1001011
1001100
1011000
SUP_STAT_0
THERM_STAT
DEV_STAT
read/clear
read/clear
read/clear
read/clear
read/clear
read
read/clear
read/clear
read/clear
read/clear
read/clear
BUS_STAT_0
WK_STAT_0
WK_LVL_STAT
WK_STAT_2
BUS_STAT_2
BUS_STAT_3
SMPS_STAT
ADC_STAT
S E L E C T I V E W A K E S T A T U S R E G I S T E R S
SWK_STAT_3
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
read
read
read
read
read
read
read
read
read
read
read
read
read
read
read
read
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
SWK_ECNT_STAT_3
SWK_CDR_STAT_3_1
SWK_CDR_STAT_3_0
SWK_STAT_2
SWK_ECNT_STAT_2
SWK_CDR_STAT_2_1
SWK_CDR_STAT_2_0
SWK_STAT_1
SWK_ECNT_STAT_1
SWK_CDR_STAT_1_1
SWK_CDR_STAT_1_0
SWK_STAT_0
SWK_ECNT_STAT_0
SWK_CDR_STAT_0_1
SWK_CDR_STAT_0_2
F A M I LY A N D P R O D U C T R E G I S T E R S
FAM_PROD_STAT
no read 1111110
Figure 49 SPI Register Mapping
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
15
14
13
12
Data Bit 15…8
D4
11
10
9
8
7
6...0
Address
A6…A0
Register Short Name
banked
Read-Only (1)
D7
D6
D5
D3
D2
D1
D0
C O N T R O L R E G I S T E R S
MODE_1
reserved
CHECKSUM
reserved
reserved
reserved
MODE_0
PWM_TLAG
WD_STM_EN_0
reserved
TIMER_WK_EN VBSENSE_CFG_1 VBSENSE_CFG_0
reserved
reserved
CAN_1_FLASH
CAN_SWK_0
reserved
SOFT_RESET_RSTNBST_VB_UV_OFF
SYS_STAT_6
VEXT_ON
FO_ON
WD_WIN
reserved
reserved
PWM_BY_WK
WD_EN_WK_BUS
reserved
reserved
PWM_AUTO
MAX_3_RST
reserved
reserved
reserved
reserved
CAN2_0
CAN_3_FLASH
reserved
BOOST_V_1
SYS_STAT_3
VIO_OV_RST
reserved
WD_TIMER_2
CAN0_2
WD_STM_EN_1
reserved
reserved
CAN1_2
CAN3_2
TIMER_PER_2
BOOST_V_0
SYS_STAT_2
VIO_RT_1
BOOST_EN
WD_TIMER_1
CAN0_1
reserved
reserved
WK_PUPD_1
CAN1_1
CAN3_1
TIMER_PER_1
VEXT_VCFG_1
SYS_STAT_1
VIO_RT_0
CFG2
WD_TIMER_0
CAN0_0
VBSENSE_EN
WK_EN
WK_PUPD_0
CAN1_0
no
no
no
no
no
no
no
no
no
no
no
no
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
0000001
0000010
0000011
0000100
0000110
0000111
0001000
0001010
0001011
0001100
0001110
0011110
M_S_CTRL
HW_CTRL_0
WD_CTRL
BUS_CTRL_0
WK_CTRL_0
WK_CTRL_1
WK_PUPD_CTRL
BUS_CTRL_2
BUS_CTRL_3
TIMER_CTRL_0
HW_CTRL_1
SYS_STAT_CTRL
reserved
reserved
CAN2_2
reserved
reserved
reserved
reserved
CAN2_1
CAN_0_FLASH
reserved
reserved
reserved
CAN_2_FLASH
CAN_SWK_1
reserved
reserved
SYS_STAT_7
CAN3_0
TIMER_PER_0
VEXT_VCFG_0
SYS_STAT_0
SYS_STAT_5
SYS_STAT_4
S E L E C T I V E W A K E R E G I S T E R S
OSC_CAL
TBIT_7
reserved
ID28
ID20
ID12
TRIM_EN_1
TBIT_6
reserved
ID27
ID19
ID11
TRIM_EN_0
TBIT_5
SP_5
ID26
ID18
CANTO_MASK
TBIT_4
reserved
TBIT_3
SP_3
ID24
ID16
reserved
TBIT_2
SP_2
ID23
ID15
reserved
TBIT_1
SP_1
ID22
ID14
CFG_VAL
TBIT_0
SP_0
ID21
ID13
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
SWK_CTRL
SWK_BTL1_CTRL
SWK_BTL2_CTRL
SWK_ID3_CTRL
SWK_ID2_CTRL
SWK_ID1_CTRL
SP_4
ID25
ID17
ID9
ID10
ID3
ID8
ID1
ID7
ID0
ID6
RTR
ID5
IDE
reserved
MASK_ID28
MASK_ID20
MASK_ID12
reserved
reserved
DATA7_7
DATA6_7
DATA5_7
DATA4_7
DATA3_7
DATA2_7
DATA1_7
DATA0_7
reserved
ID4
ID2
SWK_ID0_CTRL
MASK_ID27
MASK_ID19
MASK_ID11
MASK_ID4
reserved
DATA7_6
DATA6_6
DATA5_6
DATA4_6
DATA3_6
DATA2_6
DATA1_6
DATA0_6
reserved
MASK_ID26
MASK_ID18
MASK_ID10
MASK_ID3
reserved
DATA7_5
DATA6_5
DATA5_5
DATA4_5
DATA3_5
DATA2_5
DATA1_5
DATA0_5
DIS_ERR_CNT
MASK_ID25
MASK_ID17
MASK_ID9
MASK_ID2
reserved
DATA7_4
DATA6_4
DATA5_4
DATA4_4
DATA3_4
DATA2_4
DATA1_4
DATA0_4
reserved
MASK_ID24
MASK_ID16
MASK_ID8
MASK_ID1
DLC_3
DATA7_3
DATA6_3
DATA5_3
DATA4_3
DATA3_3
DATA2_3
DATA1_3
DATA0_3
FD_FILTER_2
MASK_ID23
MASK_ID15
MASK_ID7
MASK_ID0
DLC_2
DATA7_2
DATA6_2
DATA5_2
DATA4_2
DATA3_2
DATA2_2
DATA1_2
DATA0_2
FD_FILTER_1
MASK_ID22
MASK_ID14
MASK_ID6
reserved
DLC_1
DATA7_1
DATA6_1
DATA5_1
DATA4_1
DATA3_1
DATA2_1
DATA1_1
DATA0_1
FD_FILTER_0
MASK_ID21
MASK_ID13
MASK_ID5
reserved
DLC_0
DATA7_0
DATA6_0
DATA5_0
DATA4_0
DATA3_0
DATA2_0
DATA1_0
DATA0_0
CAN_FD_EN
SWK_MASK_ID3_CTRL
SWK_MASK_ID2_CTRL
SWK_MASK_ID1_CTRL
SWK_MASK_ID0_CTRL
SWK_DLC_CTRL
SWK_DATA7_CTRL
SWK_DATA6_CTRL
SWK_DATA5_CTRL
SWK_DATA4_CTRL
SWK_DATA3_CTRL
SWK_DATA2_CTRL
SWK_DATA1_CTRL
SWK_DATA0_CTRL
SWK_CAN_FD_CTRL
S E L E C T I V E W A K E T R I M & C O N F I G U R A T I O N S R E G I S T E R S
TRIM_OSC_7
RX_WK_SEL
OSC_CAL_H_7
OSC_CAL_L_7
reserved
reserved
CDR_LIM_H_7
CDR_LIM_L_7
TRIM_OSC_6
reserved
OSC_CAL_H_6
OSC_CAL_L_6
reserved
reserved
CDR_LIM_H_6
CDR_LIM_L_6
TRIM_OSC_5
reserved
OSC_CAL_H_5
OSC_CAL_L_5
reserved
reserved
CDR_LIM_H_5
CDR_LIM_L_5
TRIM_OSC_4
TRIM_OSC_12
OSC_CAL_H_4
OSC_CAL_L_4
reserved
reserved
CDR_LIM_H_4
CDR_LIM_L_4
TRIM_OSC_3
TRIM_OSC_11
OSC_CAL_H_3
OSC_CAL_L_3
SELFILT_1
reserved
CDR_LIM_H_3
CDR_LIM_L_3
TRIM_OSC_2
TRIM_OSC_10
OSC_CAL_H_2
OSC_CAL_L_2
SELFILT_0
reserved
CDR_LIM_H_2
CDR_LIM_L_2
TRIM_OSC_1
TRIM_OSC_9
OSC_CAL_H_1
OSC_CAL_L_1
reserved
SEL_OSC_CLK_1 SEL_OSC_CLK_0 yes
CDR_LIM_H_1
CDR_LIM_L_1
TRIM_OSC_0
TRIM_OSC_8
OSC_CAL_H_0
OSC_CAL_L_0
CDR_EN
no
no
no
no
yes
read/write
read/write
read
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
SWK_OSC_TRIM_CTRL
SWK_OPT_CTRL
SWK_OSC_CAL_H_STAT
SWK_OSC_CAL_L_STAT
SWK_CDR_CTRL1
SWK_CDR_CTRL2
SWK_CDR_LIMIT_HIGH_CTRL
SWK_CDR_LIMIT_LOW_CTRL
read
read/write
read/write
read/write
read/write
CDR_LIM_H_0
CDR_LIM_L_0
yes
yes
S T A T U S R E G I S T E R S
BVB_UV_BST
POR
reserved
DEV_STAT_1
reserved
PFM_PWM
TEST
VBAT_UV_LATCH
CANTO_2
reserved
VS_UV
reserved
VCC1_OT
DEV_STAT_0
reserved
reserved
CFG1_STATE
reserved
reserved
reserved
BOOST_OT
reserved
VEXT_OC
reserved
reserved
reserved
CANTO_0
TIMER_WU
VREG_UV
reserved
reserved
WD_FAIL_1
SYSERR_0
reserved
VEXT_OT
VIO_SC
TSD2
WD_FAIL_0
CAN_0_FAIL_1
reserved
VIO_OV
VIO_UV_FS
TSD1
SPI_FAIL
CAN_0_FAIL_0
reserved
VIO_WARN
VIO_UV
TPW
FO_ON_STATE
VCAN_UV
WK_WU
no
no
no
no
no
no
no
no
no
no
no
read/clear
read/clear
read/clear
read/clear
read/clear
read/clear
read
read/clear
read/clear
read/clear
read/clear
1000000
1000001
1000010
1000011
1000100
1000110
1001000
1001001
1001010
1001011
1001100
SUP_STAT_1
SUP_STAT_0
THERM_STAT
DEV_STAT
BUS_STAT_0
WK_STAT_0
WK_LVL_STAT
WK_STAT_2
BUS_STAT_2
BUS_STAT_3
SMPS_STAT
reserved
CAN_0_WU
CFG2_STATE
reserved
CAN_2_FAIL_1
reserved
PCFG_STATE VBAT_UV_STATE
reserved
reserved
WK
reserved
CAN_2_FAIL_0
reserved
reserved
CANTO_1
CANTO_3
reserved
CAN_3_WU
SYSERR_1
SYSERR_3
BCK_SH
CAN_2_WU
CAN_1_FAIL_1
CAN_3_FAIL_1
BCK_OP
CAN_1_WU
CAN_1_FAIL_0
CAN_3_FAIL_0
reserved
SYSERR_2
reserved
BST_SH
BST_ACT
BST_OP
reserved
S E L E C T I V E W A K E S T A T U S R E G I S T E R S
reserved
reserved
N_AVG_3_11
N_AVG_3_3
reserved
SYNC_3
reserved
N_AVG_3_10
N_AVG_3_2
SYNC_2
reserved
ECNT_3_5
N_AVG_3_9
N_AVG_3_1
reserved
ECNT_2_5
N_AVG_2_9
N_AVG_2_1
reserved
ECNT_1_5
N_AVG_1_9
N_AVG_1__1
reserved
ECNT_0_5
N_AVG_0_9
N_AVG_0_1
reserved
ECNT_3_4
N_AVG_3_8
N_AVG_3_0
reserved
ECNT_2_4
N_AVG_2_8
N_AVG_2_0
reserved
ECNT_1_4
N_AVG_1_8
N_AVG_1_0
reserved
ECNT_0_4
N_AVG_0_8
N_AVG_0_0
CANSIL_3
ECNT_3_3
N_AVG_3_7
reserved
CANSIL_2
ECNT_2_3
N_AVG_2_7
reserved
CANSIL_1
ECNT_1_3
N_AVG_1_7
reserved
CANSIL_0
ECNT_0_3
N_AVG_0_7
reserved
SWK_SET_3
ECNT_3_2
N_AVG_3_6
reserved
SWK_SET_2
ECNT_2__2
N_AVG_2_6
reserved
SWK_SET_1
ECNT_1_2
N_AVG_1_6
reserved
SWK_SET_0
ECNT_0_2
N_AVG_0_6
reserved
WUP_3
ECNT_3_1
N_AVG_3_5
reserved
WUF_3
ECNT_3_0
N_AVG_3_4
reserved
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
read
read
read
read
read
read
read
read
read
read
read
read
read
read
read
read
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
SWK_STAT_3
SWK_ECNT_STAT_3
SWK_CDR_STAT_3_1
SWK_CDR_STAT_3_0
SWK_STAT_2
SWK_ECNT_STAT_2
SWK_CDR_STAT_2_1
SWK_CDR_STAT_2_0
SWK_STAT_1
SWK_ECNT_STAT_1
SWK_CDR_STAT_1_1
SWK_CDR_STAT_1_0
SWK_STAT_0
SWK_ECNT_STAT_0
SWK_CDR_STAT_0_1
SWK_CDR_STAT_0_0
WUP_2
WUF_2
reserved
reserved
ECNT_2_1
N_AVG_2_5
reserved
ECNT_2_0
N_AVG_2_4
reserved
N_AVG_2_11
N_AVG_2_3
reserved
N_AVG_2_10
N_AVG_2_2
SYNC_1
WUP_1
WUF_1
reserved
reserved
ECNT_1_1
N_AVG_1_5
reserved
ECNT_1_0
N_AVG_1_4
reserved
N_AVG_1_11
N_AVG_1_3
reserved
reserved
N_AVG_0_11
N_AVG_0_3
N_AVG_1_10
N_AVG_1_2
SYNC_0
reserved
N_AVG_0_1_0
N_AVG_0_2
WUP_0
WUF_0
ECNT_0_1
N_AVG_0_5
reserved
ECNT_0__0
N_AVG_0_4
reserved
F A M I LY A N D P R O D U C T R E G I S T E R S
FAM_1 FAM_0 PROD_3 PROD_2
FAM_3
FAM_2
PROD_1
PROD_0
no
read
1111110
FAM_PROD_STAT
Figure 50 Detailed SPI Bit Mapping
Note:
The CAN Selective Wake configuration for the 4 CAN modules is managed by banking. The relevant
bank is selected via CAN_SWK[1:0] in BUS_CTRL_3.
Datasheet
107
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.5
SPI Control Registers
Read / Write Operation (see Chapter 13.3):
•
•
•
•
The ‘POR / Soft Reset Value’ defines the register content after POR or SBC Software Reset.
The ‘Restart Value’ defines the register content after SBC Restart; ‘x’ means the bit is unchanged.
‘y’ in ‘Restart Value’ means the bit can be changed by SBC.
One 16-bit SPI command consist of two bytes:
- the 7-bit address and one additional bit for the register access mode and
- following the data byte
The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to
the SPI bits 8...15.
•
There are three different bit types:
–
–
–
‘r’ = READ; read only bits (or reserved bits).
‘rw’ = READ/WRITE; readable and writable bits.
‘rwh’ = READ/WRITE/HARDWARE; as rw with the possibility that the hardware can change the bits.
•
•
•
Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only).
Writing to a register is done byte wise by setting the SPI bit 7 to “1”.
SPI control bits are not cleared or changed automatically. This must be done by the microcontroller via SPI
programming.
The registers are addressed wordwise.
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.5.1
General Control Registers
Mode- and Supply Control
M_S_CTRL
Mode- and Supply Control (Address 000 0001B)
POR / Soft Reset Value: 0000 0000B; Restart Value: 00x1)0 00xxB
7
6
5
4
3
2
1
0
MODE
VEXT_ON
Reserved
VIO_OV_RST
VIO_RT
rwh
rwh
r
rwh
rw
1) The value is x in case of PCFG=1. The value is 1 if PCFG=0.
Field
Bits
Type Description
MODE
7:6
rwh
SBC Mode Control
00B SBC Normal Mode
01B SBC Sleep Mode
10B SBC Stop Mode
11B SBC Reset: Soft Reset is executed (configuration of RSTN triggering
in bit SOFT_RESET_ RSTN)
VEXT_ON
5
rwh
If PCFG is left open, VEXT Mode Control
0B VEXT OFF
1B VEXT is enabled (as independent voltage regulator)
If PCFG is connect to GND, VEXT Mode Control always reads as 1 (VEXT
is enable)
Reserved
4:3
2
r
Reserved, always reads as 0
VIO_OV_RST
rwh
VIO Overvoltage Reset / Fail-Safe enable
0B VIO_OV is set in case of VIO_OV; no SBC Restart or Fail-Safe is
entered for VIO_OV
1B VIO_OV is set in case of VIO_OV; depending on the device
configuration SBC Restart or SBC Fail-Safe Mode is entered (see
Chapter 5.1.1);
VIO_RT
Notes
1:0
rw
VIO Reset Threshold Control
00B Vrt1 selected (highest threshold)
01B Vrt2 selected
10B Vrt3 selected
11B Vrt4 selected
1. It is not possible to change from SBC Stop to Sleep Mode via an SPI Command. See also the State Machine
Chapter.
2. After entering SBC Restart Mode, the MODE bits will be automatically set to SBC Normal Mode.
3. The SPI output will always show the previously written state with a Write Command (what has been
programmed before).
Datasheet
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Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Hardware Control 0
HW_CTRL_0
Hardware Control 0 (Address 000 0010B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0x0x xxxxB
7
6
5
4
3
2
1
0
Reserved
PWM_TLAG
FO_ON
PWM_BY_WK PWM_AUTO
rwh rw
Reserved
BOOST_EN
CFG2
r
rw
rwh
r
rwh
rw
Field
Bits
7
Type Description
Reserved
r
Reserved, always reads as 0
PWM Lag time
PWM_TLAG
6
rw
This bit permits to set the time between the PWM to PFM transition.
0B 100µs
1B 1ms
FO_ON
5
4
3
rwh
rwh
rw
Failure Output activation
This bit is used to activate the Fail Output by software.
0B FO not activated by software, FO can be activated by defined failure
1B FO activated by software.
PWM_BY_WK
PWM_AUTO
PWM of Buck converter enabled by WK pin
0B Buck converter uses PFM in SBC Stop Mode
1B Buck converter can be switched between PFM and PWM by the WK
pin in SBC Stop Mode.
Automatic transition PFM-PWM in SBC Stop Mode
This bit is used to activate the automatic transition PFM to PWM.
0B Buck converter always uses PFM in SBC Stop Mode (default)
1B Buck converter uses automatic transition PFM to PWM in case large
current needed in SBC Stop Mode. To come back in PFM, write a SBC
Stop Mode command to M_S_CTRL.
Reserved
2
1
r
Reserved, always reads as 0
BOOST_EN
rwh
Boost converter enable
0B Boost Off
1B Boost enabled, automatic switch ON for LOW VS Voltage
CFG2
0
rw
Configuration Select 2
0B Fail Output (FO) enabled after 2nd watchdog trigger fail
Config 3/4
1B Fail Output (FO) enabled after 1st watchdog trigger fail
Config 1/2
Notes
1. The FO_ON bit is cleared by the SBC after SBC Restart Mode. Clearing the bit via SPI or via SBC Restart Mode
will not disable the FO output, if the failure condition is still present. See also Chapter 11for FO activation and
deactivation. Setting the FO output via an SPI should be used for testing purposes only.
2. The selection between Config 1/3 respectively Config 2/4 is done by the pin INTN. The INTN pin defines if the
SBC enters to SBC Fail-Safe Mode with VCC1 OFF in case of a watchdog failure.
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Watchdog Control
WD_CTRL
Watchdog Control (Address 000 0011B)
POR / Soft Reset Value: 0001 0100B;
Restart Value: x0xx x100B
7
6
5
4
3
2
1
0
WD_STM_EN
_0
WD_EN_WK_
BUS
CHECKSUM
WD_WIN
MAX_3_RST
WD_TIMER
rw
rwh
rw
rw
rw
rwh
Field
CHECKSUM
Bits
Type Description
7
rw
Watchdog Setting Checksum Bit
The sum of bits 7:0 needs to have even parity
0B Counts as 0 for checksum calculation
1B Counts as 1 for checksum calculation
WD_STM_EN_0
WD_WIN
6
5
4
3
rwh
rw
Watchdog Deactivation during SBC Stop Mode, bit 0 (Chapter 12.2.4)
0B Watchdog is active in Stop Mode
1B Watchdog is deactivated in Stop Mode
Watchdog Type Selection
0B Watchdog works as a Time-Out watchdog
1B Watchdog works as a Window watchdog
WD_EN_WK_
BUS
rw
Watchdog Enable after Bus (CANx) Wake in SBC Stop Mode
0B Watchdog will not start after a CANx wake
1B Watchdog starts with a long open window after CANx Wake
MAX_3_RST
rw
Limit number of resets due to a Watchdog failure
0B Always generate a reset in case of WD fail
1B After 3 consecutive resets due to WD fail, no further reset is
generated (only valid in config 1/3)
WD_TIMER
2:0
rwh
Watchdog Timer Period
000B 10ms
001B 20ms
010B 50ms
011B 100ms
100B 200ms
101B 500ms
110B 1000ms
111B reserved
Notes
1. See Chapter 12.2.3 for calculating the checksum.
2. See also Chapter 12.2.4 for more information on disabling the watchdog in SBC Stop Mode.
3. See Chapter 12.2.4 for more information on the effect of the bit WD_EN_WK_BUS.
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Bus Control 0
BUS_CTRL_0
Bus Control 0 (Address 000 0100B)
POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 0xyyB
7
6
5
4
3
2
1
0
Reserved
CAN0
r
rwh
Field
Bits
7:3
Type Description
Reserved
CAN0
r
Reserved, always reads as 0
2:0
rwh
HS-CAN_0 Module Modes
000B CAN OFF
001B CAN is wake capable (no SWK)
010B CAN Receive Only Mode (no SWK)
011B CAN Normal Mode (no SWK)
100B CAN OFF
101B CAN is wake capable with SWK
110B CAN Receive Only Mode with SWK
111B CAN Normal Mode with SWK
Notes
1. See Figure 23 for detailed state changes of the CAN Transceiver for different SBC modes.
2. The bit CAN0_2 is not modified by the SBC but can only be changed by the user. Therefore, the access type is
‘rw’ compared to bits CAN0_0 and CAN0_1.
3. In case SYSERR_0 = 0 and the CAN transceiver is configured to ‘x11’ while going to SBC Sleep Mode, it will be
automatically set to wake capable (‘x01’). The SPI bits will be changed to wake capable. If configured to ‘x10’
and SBC Sleep Mode is entered, then the transceiver is set to wake capable, while it will stay in Receive Only
Mode when it had been configured to ‘x10’ when going to SBC Stop Mode. If it had been configured to wake
capable or OFF then the mode will remain unchanged.The Receive Only Mode has to be selected by the user
before entering SBC Stop Mode. Refer to Chapter 5.3.4 for detailed information on the Selective Wake mode
changes.
4. Failure Handling Mechanism: When the SBC enters SBC Fail-Safe Mode due to a failure (e.g. TSD2, WD-
Failure), then the bus and wake registers are modified by the SBC in order to ensure that the device can be
woken again. Refer to the respective register descriptions.
Datasheet
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Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Internal Wake Input Control 0
WK_CTRL_0
Internal Wake Input Control 0 (Address 000 0110B)
POR / Soft Reset Value: 0000 0001B;
Restart Value: 0xxx 000xB
7
6
5
4
3
2
1
0
TIMER1_WK_
EN
WD_STM_EN
_1
Reserved
VBSENSE_CFG
Reserved
Reserved VBSENSE_EN
rw
r
rw
rw
r
rwh
r
Field
Bits
7
Type Description
Reserved
r
Reserved, always reads as 0
TIMER1_WK_
EN
6
rw
Wake Source Control (for cyclic wake)
0B Cyclic wake disabled
1B Cyclic wake enabled as a wake source
VBSENSE_CFG 5:4
rw
Battery Voltage Monitoring Threshold Selection
00B VBSENSE0 threshold selected (highest threshold)
01B VBSENSE1 threshold selected
10B VBSENSE2 threshold selected
11B VBSENSE3 threshold selected
Reserved
3
2
r
Reserved, always reads as 0
WD_STM_EN_1
rwh
Watchdog Deactivation during Stop Mode, bit 1 (Chapter 12.2.4)
0B Watchdog is active in Stop Mode
1B Watchdog is deactivated in Stop Mode
Reserved
1
0
r
Reserved, always reads as 0
VBSENSE_EN
rw
Enable the fast battery voltage monitoring
0B Fast Vbatt Monitoring disabled
1B Fast Vbatt Monitoring enabled
Note:
See also Chapter 12.2.4 for more information on disabling the watchdog in SBC Stop Mode.
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
External Wake Source Control 1
WK_CTRL_1
External Wake Source Control 1 (Address 000 0111B)
POR / Soft Reset Value: 0000 0001B;
Restart Value: 0000 000xB
7
6
5
4
3
2
1
0
Reserved
WK_EN
r
rwh
Field
Bits
7:1
0
Type Description
Reserved
WK_EN
r
Reserved, always reads as 0
rwh
WK Wake Source Control
0B WK wake disabled
1B WK is enabled as a wake source
Notes
1. Failure Handling Mechanism: When the device enters SBC Fail-Safe Mode due to a failure (e.g. TSD2, WD-
Failure), the WK_CTRL_1 is modified to the value ‘0000 0001’ in order to ensure that the device can be woken
again.
Datasheet
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Rev. 1.5
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Wake Input Level Control
WK_PUPD_CTRL
Wake Input Level Control (Address 000 1000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 00xxB
7
6
5
4
3
2
1
0
Reserved
WK_PUPD
r
rw
Field
Bits
7:2
Type Description
Reserved
WK_PUPD
r
Reserved, always reads as 0
1:0
rw
WK Pull-Up / Pull-Down Configuration
00B No pull-up / pull-down selected
01B Pull-down resistor selected
10B Pull-up resistor selected
11B Automatic switching to pull-up or pull-down
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Bus Control 2
BUS_CTRL_2
Bus Control 2 (Address 000 1010B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxy yxyyB
7
6
5
4
3
2
1
0
CAN_2_Flash CAN_1_Flash
CAN2
CAN1
rw
rw
rwh
rwh
Field
Bits
Type Description
CAN_2_Flash
CAN_1_Flash
CAN2
7
rw
CAN2 Flash Mode activation
0B Flash Mode disabled: CAN communication up to 5MBaud
1B Flash Mode enabled: CAN communication for higher than 5MBaud
(higher emission on CAN bus - no slew rate control)
6
rw
CAN1 Flash Mode activation
0B Flash Mode disabled: CAN communication up to 5MBaud
1B Flash Mode enabled: CAN communication for higher than 5MBaud
(higher emission on CAN bus - no slew rate control)
5:3
rwh
HS-CAN_2 Module Modes
000B CAN OFF
001B CAN is wake capable (no SWK)
010B CAN Receive Only Mode (no SWK)
011B CAN Normal Mode (no SWK)
100B CAN OFF
101B CAN is wake capable with SWK
110B CAN Receive Only Mode with SWK
111B CAN Normal Mode with SWK
CAN1
2:0
rwh
HS-CAN_1 Module Modes
000B CAN OFF
001B CAN is wake capable (no SWK)
010B CAN Receive Only Mode (no SWK)
011B CAN Normal Mode (no SWK)
100B CAN OFF
101B CAN is wake capable with SWK
110B CAN Receive Only Mode with SWK
111B CAN Normal Mode with SWK
Notes
1. See Figure 23 for detailed state changes of the CAN Transceiver for different SBC modes.
2. The bit CANx_2 is not modified by the SBC but can only be changed by the user. Therefore, the access type is
‘rw’ compared to bits CANx_0 and CANx_1.
3. In case SYSERR_x = 0 and the CAN transceiver is configured to ‘x11’ while going to SBC Sleep Mode, it will be
automatically set to wake capable (‘x01’). The SPI bits will be changed to wake capable. If configured to ‘x10’
and SBC Sleep Mode is entered, then the transceiver is set to wake capable, while it will stay in Receive Only
Mode when it had been configured to ‘x10’ when going to SBC Stop Mode. If it had been configured to wake
capable or OFF then the mode will remain unchanged.The Receive Only Mode has to be selected by the user
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
before entering SBC Stop Mode. Refer to Chapter 5.3.4 for detailed information on the Selective Wake mode
changes.
4. Failure Handling Mechanism: When the device enters SBC Fail-Safe Mode due to a failure (e.g. TSD2, WD-
Failure), then the bus and wake registers are modified by the SBC in order to ensure that the device can be
woken again. Refer to the respective register descriptions.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Timer_0 Control and Selection
TIMER_CTRL_0
Timer_0 Control and Selection (Address 000 1100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0000B
7
6
5
4
3
2
1
0
Reserved
TIMER_0_PER
r
rwh
Field
Reserved
Bits
Type Description
7:3
r
Reserved, always reads as 0
TIMER_0_PER 2:0
rwh
Cyclic Wake Period Configuration
000B 10ms
001B 20ms
010B 50ms
011B 100ms
100B 200ms
101B 1s
110B 2s
111B reserved
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Hardware Control 1
HW_CTRL_1
Hardware Control 1 (Address 000 1110B)
POR / Soft Reset Value: 0000 00yyB; Restart Value: 0x0x xxxxB
7
6
5
4
3
2
1
0
SOFT_RESET BST_VB_UV_
ADC_SEL
Reserved
BOOST_V
VEXT_VCFG
_RSTN
OFF
rw
rw
rw
r
rw
rwh
Field
Bits
Type Description
ADC_SEL
7
rw
rw
rw
8 bit ADC input channel selector
0B WK pin is selected
1B VBSENSE pin is selected
SOFT_RESET_
RSTN
6
5
Soft Reset Configuration
0B RSTN will be triggered (pulled low) during a Soft Reset (default)
1B No RSTN triggering during a Soft Reset
BST_VB_UV_
OFF
Boost switch-off control on VBSENSE low voltage condition
0B Boost automatic switch-off disable
1B Boost automatic switch-off enable
Reserved
BOOST_V
4
r
Reserved, always reads as 0
3:2
rw
BOOST Output voltage configuration
00B 6.7V output (default)
01B 8V output
10B 10V output
11B 12V output
VEXT_VCFG
1:0
rwh
VEXT Output voltage configuration
00B 5.0V output
01B 3.3V output (default)
10B 1.8V output
11B 1.2V output
Notes
1. After triggering a SBC Software Reset the bits VEXT_VCFG remain unchanged, as shown by the ‘y’ in the
POR/Soft Reset Value.
2. The VEXT_VCFG can not be accessed if the PCFG pin is connected to GND. Always read ‘01’.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Bus Control 3
BUS_CTRL_3
Bus Control 3 (Address 000 1011B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xx0x xxyyB
7
6
5
4
3
2
1
0
CAN_SWK
Reserved CAN_0_Flash CAN_3_Flash
rw rw
CAN3
rw
r
rwh
Field
Bits
Type Description
CAN_SWK
7:6
rw
Banking Control for CAN Selective Wake Configurations
00B CAN0 Module
01B CAN1 Module
10B CAN2 Module
11B CAN3 Module
Reserved
5
4
r
Reserved, always reads as 0
CAN_0_Flash
rw
CAN0 Flash Mode activation
0B Flash Mode disabled: CAN communication up to 5MBaud
1B Flash Mode enabled: CAN communication for higher than 5MBaud
(higher emission on CAN bus - no slew rate control)
CAN_3_Flash
CAN3
3
rw
CAN3 Flash Mode activation
0B Flash Mode disabled: CAN communication up to 5MBaud
1B Flash Mode enabled: CAN communication for higher than 5MBaud
(higher emission on CAN bus - no slew rate control)
2:0
rwh
HS-CAN_3 Module Modes
000B CAN OFF
001B CAN is wake capable (no SWK)
010B CAN Receive Only Mode (no SWK)
011B CAN Normal Mode (no SWK)
100B CAN OFF
101B CAN is wake capable with SWK
110B CAN Receive Only Mode with SWK
111B CAN Normal Mode with SWK
Notes
1. SPI Register Banking for CAN Selective Wake configuration is managed with the bits CAN_SWK[1:0]. See also
Chapter 13.4.2.
2. See Figure 23 for detailed state changes of CAN Transceiver for different SBC modes.
3. The bit CAN3_2 is not modified by the SBC but can only be changed by the user. Therefore, the access type is
‘rw’ compared to bits CAN3_0 and CAN3_1.
4. In case SYSERR_3 = 0 and the CAN transceiver is configured to ‘x11’ while going to SBC Sleep Mode, it will be
automatically set to wake capable (‘x01’). The SPI bits will be changed to wake capable. If configured to ‘x10’
and SBC Sleep Mode is entered, then the transceiver is set to wake capable, while it will stay in Receive Only
Mode when it had been configured to ‘x10’ when going to SBC Stop Mode. If it had been configured to wake
capable or OFF then the mode will remain unchanged.The Receive Only Mode has to be selected by the user
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
before entering SBC Stop Mode. Refer to Chapter 5.3.4 for detailed information on the Selective Wake mode
changes.
5. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (e.g. TSD2, WD-Failure),
then the bus and wake registers are modified by the SBC in order to ensure that the device can be woken
again. Refer to the respective register descriptions.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
System Status Control
SYS_STATUS_CTRL
System Status Control (Address 001 1110B)
POR Value: 0000 0000B;
Restart Value/Soft Reset Value: xxxx xxxxB
7
6
5
4
3
2
1
0
SYS_STAT
rw
Field
Bits
Type Description
rw System Status Control Byte (bit0=LSB; bit7=MSB)
SYS_STAT
7:0
Dedicated byte for system configuration, access only by
microcontroller
Notes
1. The SYS_STATUS_CTRL register is an exception for the default values, i.e. it will keep its configured value
even after a Software Reset.
2. This byte is intended for storing system configurations of the ECU by the microcontroller and is only accessible
in SBC Normal Mode. The byte is not accessible by the SBC and is also not cleared after SBC Fail-Safe or
Restart Mode. It allows the microcontroller to quickly store the system configuration without losing the data.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.5.2
Selective Wake Control Registers
CAN Selective Wake Control
SWK_CTRL
CAN Selective Wake Control (Address 010 0000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxx0B
7
6
5
4
3
2
1
0
CANTO_MAS
K
OSC_CAL
TRIM_EN
Reserved
CFG_VAL
rw
rw
rw
r
rwh
Field
Bits
Type Description
OSC_CAL
7
rw
Oscillator Calibration Mode
0B Oscillator Calibration is disabled
1B Oscillator Calibration is enabled
TRIM_EN
6:5
4
rw
(Un)locking mechanism of oscillator recalibration
00B locked
01B locked
10B locked
11B unlocked
CANTO_MASK
rw
CAN Time Out Masking
0B CAN time-out is masked - no interrupt (on pin INTN) is triggered
1B CAN time-out is signaled on INTN
Reserved
CFG_VAL
3:1
0
r
Reserved, always reads as 0
rwh
SWK Configuration valid
0B Configuration is not valid (SWK not possible)
1B SWK configuration valid, written by up to enable SWK
Notes
1. TRIM_EN unlocks the oscillation calibration mode. Only the bit combination ‘11’ is the valid unlock. The pin
TXDCANx is used for oscillator synchronisation (trimming).
2. The microcontroller needs to validate the SWK configuration and set CFG_VAL to ‘1’. The SBC will only enable
SWK if CFG_VAL is set to ‘1’. The bit will be cleared automatically by the SBC after a wake up or POR or if a SWK
configuration data is changed by the microcontroller.
3. CANTO_x bit will only be updated inside BUS_STAT_x while CANx_2 is set. Therefore, an interrupt is only
signaled upon occurrence of CANTO_x while CANx_2 (SWK is enabled) is set in SBC Normal and Stop Mode.
4. TRIM_EN also unlocks the writing to the SWK_OPT_CTRL register in order to enable the alternate low-power
Receiver. Only the bit combination ‘11’ unlocks the calibrations / configurations.
5. In case, the microcontroller writes a command to a CAN configuration register during SBC stop-mode, the
SWK configuration gets invalid.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Bit Timing Logic Control 1
SWK_BTL1_CTRL
SWK Bit Timing Logic Control 1 (Address 010 0001B)
POR / Soft Reset Value: 1010 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
TBIT
rw
Field
TBIT
Bits
Type Description
rw Number of Time Quanta in a Bit Time
7:0
Represents the number of time quanta in a bit time. Quanta is depending
on SEL_OSC_CLK<1:0> from the SWK_CDR_CTRL2 register.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Bit Timing Control 2
SWK_BTL2_CTRL
SWK Bit Timing Control 2 (Address 010 0010B)
POR / Soft Reset Value: 0011 0011B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
SP
r
rw
Field
Bits
7:6
Type Description
Reserved
SP
r
Reserved, always reads as 0
Sampling Point Position
5:0
rw
Represents the sampling point position (fractional number < 1).
Example: 0011 0011 = 0.796875 (~80%)
B
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK WUF Identifier bits 28...21
SWK_ID3_CTRL
SWK WUF Identifier bits 28...21 (Address 010 0011B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
ID28_21
rw
Field
Bits
Type Description
rw WUF Identifier Bits 28...21
ID28_21
7:0
Note:
Please note the configuration of the standard identifier and extended identifier. The standard
identifier is configured with the bits ID18...ID28.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK WUF Identifier bits 20...13
SWK_ID2_CTRL
SWK WUF Identifier bits 20...13 (Address 010 0100B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
ID20_13
rw
Field
Bits
Type Description
ID20_13
7:0
rw
WUF Identifier Bits 20...13
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK WUF Identifier bits 12...5
SWK_ID1_CTRL
SWK WUF Identifier bits 12...5 (Address 010 0101B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
ID12_5
rw
Field
Bits
Type Description
ID12_5
7:0
rw
WUF Identifier Bits 12...5
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK WUF Identifier bits 4...0
SWK_ID0_CTRL
SWK WUF Identifier bits 4...0 (Address 010 0110B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
ID4_0
RTR
IDE
r
rw
rw
rw
Field
Bits
7
Type Description
Reserved
ID4_0
r
Reserved, always reads as 0
WUF Identifier Bits 4..0
6:2
1
rw
rw
RTR
Remote Transmission Request Field (acc. ISO 11898-1)
0B Normal Data Frame
1B Remote Transmission Request
IDE
0
rw
Identifier Extension Bit
0B Standard Identifier Length (11 bit)
1B Extended Identifier Length (29 bit)
Note:
The setting RTR = 1 is not allowed for wake-up frames according to the ISO11898-6.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK WUF Identifier Mask bits 28...21
SWK_MASK_ID3_CTRL
SWK WUF Identifier Mask bits 28...21 (Address 010 0111B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
MASK_ID28_21
rw
Field
Bits
Type Description
MASK_ID28_21 7:0
rw
WUF Identifier Mask Bits 28...21
0B Unmasked - bit is ignored
1B Masked - bit is compared in CAN frame
Note:
WUF bits are masked by setting the respective MASK bit to ‘1’.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK WUF Identifier Mask bits 20...13
SWK_MASK_ID2_CTRL
SWK WUF Identifier Mask bits 20...13 (Address 010 1000B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
MASK_ID20_13
rw
Field
Bits
Type Description
MASK_ID20_13 7:0
rw
WUF Identifier Mask Bits 20...13
0B Unmasked - bit is ignored
1B Masked - bit is compared in CAN frame
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK WUF Identifier Mask bits 12...5
SWK_MASK_ID1_CTRL
SWK WUF Identifier Mask bits 12...5 (Address 010 1001B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
MASK_ID12_5
rw
Field
Bits
Type Description
MASK_ID12_5 7:0
rw
WUF Identifier Mask Bits 12...5
0B Unmasked - bit is ignored
1B Masked - bit is compared in CAN frame
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK WUF Identifier bits 4...0
SWK_MASK_ID0_CTRL
SWK WUF Identifier bits 4...0 (Address 010 1010B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xx00B
7
6
5
4
3
2
1
0
Reserved
MASK_ID4_0
Reserved
r
rw
r
Field
Bits
7
Type Description
Reserved
r
Reserved, always reads as 0
MASK_ID4_0
6:2
rw
WUF Identifier MASK Bits 4..0
0B Unmasked - bit is ignored
1B Masked - bit is compared in CAN frame
Reserved
1:0
r
Reserved, always reads as 0
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Frame Data Length Code Control
SWK_DLC_CTRL
SWK Frame Data Length Code Control (Address 010 1011B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
DLC
r
rw
Field
Bits
7:4
Type Description
Reserved
DLC
r
Reserved, always reads as 0
3:0
rw
Payload length in number of bytes
0000B Frame Data Length = 0 or cleared
0001B Frame Data Length = 1
0010B Frame Data Length = 2
0011B Frame Data Length = 3
0100B Frame Data Length = 4
0101B Frame Data Length = 5
0110B Frame Data Length = 6
0111B Frame Data Length = 7
from 1000B to 1111B Frame Data Length = 8
Note:
The number of bytes in the data field has to be indicated by the DLC. This DLC consists of four bits.
The admissible number of data bytes for a data frame is in a range from zero to eight. DLCs in the
range of zero to seven indicates data fields of length of zero to seven bytes. DLCs in the range from
eight to fifteen indicate data fields of length of eight byte.The configured DLC value has to match bit
by bit with the DLC in the received wake-up frame (refer also to Chapter 5.3.2.3).
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Data7 Register
SWK_DATA7_CTRL
SWK Data7 Register (Address 010 1100B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
DATA7
rw
Field
Bits
Type Description
DATA7
7:0
rw
Data7 byte content(bit0=LSB; bit7=MSB)
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Data6 Register
SWK_DATA6_CTRL
SWK Data6 Register (Address 010 1101B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
DATA6
rw
Field
Bits
Type Description
DATA6
7:0
rw
Data6 byte content (bit0=LSB; bit7=MSB)
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Data5 Register
SWK_DATA5_CTRL
SWK Data5 Register (Address 010 1110B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
DATA5
rw
Field
Bits
Type Description
DATA5
7:0
rw
Data5 byte content (bit0=LSB; bit7=MSB)
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Data4 Register
SWK_DATA4_CTRL
SWK Data4 Register (Address 010 1111B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
DATA4
rw
Field
Bits
Type Description
DATA4
7:0
rw
Data4 byte content (bit0=LSB; bit7=MSB)
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Data3 Register
SWK_DATA3_CTRL
SWK Data3 Register (Address 011 0000B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
DATA3
rw
Field
Bits
Type Description
DATA3
7:0
rw
Data3 byte content (bit0=LSB; bit7=MSB)
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Data2 Register
SWK_DATA2_CTRL
SWK Data2 Register (Address 011 0001B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
DATA2
rw
Field
Bits
Type Description
DATA2
7:0
rw
Data2 byte content (bit0=LSB; bit7=MSB)
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Data1 Register
SWK_DATA1_CTRL
SWK Data1 Register (Address 011 0010B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
DATA1
rw
Field
Bits
Type Description
DATA1
7:0
rw
Data1 byte content (bit0=LSB; bit7=MSB)
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Data0 Register
SWK_DATA0_CTRL
SWK Data0 Register (Address 011 0011B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
DATA0
rw
Field
Bits
Type Description
DATA0
7:0
rw
Data0 byte content (bit0=LSB; bit7=MSB)
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CAN FD Configuration Control Register
SWK_CAN_FD_CTRL
CAN FD Configuration Control Register (Address 011 0100B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
DIS_ERR_CN
T
Reserved
Reserved
FD_FILTER
CAN_FD_EN
r
rwh
r
rw
rw
Field
Bits
7:6
5
Type Description
Reserved
r
Reserved, always reads as 0
DIS_ERR_CNT
rwh
Error Counter Disable Function
0B Error Counter is enabled during SWK
1B Error counter is disabled during SWK only if CAN_FD_EN = ‘1’
Reserved
4
r
Reserved, always reads as 0
FD_FILTER
3:1
rw
CAN FD Dominant Filter Time
000B 50 ns
001B 100 ns
010B 150 ns
011B 200 ns
100B 250 ns
101B 300 ns
110B 350 ns
111B 775 ns
CAN_FD_EN
0
rw
Enable CAN FD Tolerant Mode
0B CAN FD Tolerant Mode disabled
1B CAN FD Tolerant Mode enabled
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.5.3
Selective Wake Trimming and Calibration Control Registers
SWK Oscillator Trimming Register
SWK_OSC_TRIM_CTRL
SWK Oscillator Trimming Register (Address 011 1000B)
POR / Soft Reset Value: xxxx xxxxB; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
TRIM_OSC
rw
Field
Bits
Type Description
TRIM_OSC
7:0
rw
Oscillator trimming (bit0=LSB; bit7=MSB);
(only writable if TRIM_EN = ‘11’)
Note:
TRIM_OSC[0:4] represent the 32-steps fine trimming range with a monotonous behavior from slower
to faster frequency. The step width is ~0.25 MHz.
TRIM_OSC[5:7] changes the oscillator temperature coefficient. It is strongly recommended not to
chance these values.
Due to CDR functionality, it is not required to change these values.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Selective Wake Options Register
SWK_OPT_CTRL
Selective Wake Options Register (Address 011 1001B)
POR / Soft Reset Value: 000x xxxxB;
Restart Value: x00x xxxxB
7
6
5
4
3
2
1
0
RX_WK_SEL
Reserved
TRIM_OSC
rw
r
rw
Field
Bits
Type Description
RX_WK_SEL
7
rw
SWK Receiver selection (only accessible if TRIM_EN = ‘11’)
0B Standard Receiver selected during SWK
1B Wake Receiver selected during SWK
Reserved
6:5
4:0
r
Reserved, always reads as 0
TRIM_OSC
rw
Oscillator trimming (bit8=LSB; bit12=MSB);
(only writable if TRIM_EN = ‘11’)
Notes
1. The bit RX_WK_SEL is used to switch between different receivers. Therefore the same registers are described
below again except for the RX_WK_SEL bit. The bit might be not needed in case one receiver is used for Normal
Mode and SWK detection.
2. TRIM_OSC[8:12] represent the 32-steps coarse trimming range, which is not monotonous.
It is not recommended to change these values.
3. If only the RX_WK_SEL bit needs to be changed, read the TRIM_OSC [8:12] bits and keep these values for the
next write command on SWK_OPT_CRTL.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Oscillator Calibration High Register
SWK_OSC_CAL_H_STAT
SWK Oscillator Calibration High Register (Address 011 1010B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
OSC_CAL_H
r
Field
Bits
Type Description
OSC_CAL_H
7:0
r
Oscillator Calibration High Register
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Oscillator Calibration Low Register
SWK_OSC_CAL_L_STAT
SWK Oscillator Calibration Low Register (Address 011 1011B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
OSC_CAL_L
r
Field
Bits
Type Description
OSC_CAL_L
7:0
r
Oscillator Calibration Low Register
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Control 1 Register
SWK_CDR_CTRL1
CDR Control 1 Register (Address 011 1100B)
POR / Soft Reset Value: 0000 0100B; Restart Value: 0000 xxxxB
7
6
5
4
3
2
1
0
Reserved
SEL_FILT
Reserved
CDR_EN
r
rw
r
rw
Field
Bits
7:4
Type Description
Reserved
SEL_FILT
r
Reserved, always reads as 0
3:2
rw
Select Time Constant of Filter
00B Time constant 8
01B Time constant 16 (default)
10B Time constant 32
11B adapt
distance between falling edges 2, 3 bit: Time constant 32
distance between f. edges 4, 5, 6, 7, 8 bit: Time constant 16
distance between falling edges 9, 10 bit: Time constant 8
Reserved
CDR_EN
1
0
r
Reserved, always reads as 0
rw
Enable CDR
0B CDR disabled
1B CDR enabled
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Control 2 Register
SWK_CDR_CTRL2
CDR Control 2 Register (Address 011 1101B)
POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 00xxB
7
6
5
4
3
2
1
0
Reserved
SEL_OSC_CLK
rw
r
Field
Reserved
Bits
Type Description
7:2
r
Reserved, always reads as 0
SEL_OSC_CLK 1:0
rw
Input Frequency for CDR module
See Table 32 and Table 33
Table 32 Frequency Settings of Internal Clock for the CDR
SEL_OSC_CLK[1:0]
int. Clock for CDR
00
01
10
11
80 MHz
40 MHz
20 MHz
10 MHz
Table 33 Recommended CDR Settings for Different Baud Rates
SEL_OSC_CLK
[1:0]
Baudrate SWK_BTL1_CTRL Value SWK_CDR_LIMIT_HIGH SWK_CDR_LIMIT_LOW_
_CTRL Value
1010 1000
0101 0100
CTRL Value
1001 1000
0100 1100
00
01
10
11
00
01
10
11
00
01
10
11
500k
500k
500k
500k
250k
250k
250k
250k
125k
125k
125k
125k
1010 0000
0101 0000
CDR Setting not recommended for this baudrate due to insufficient precision
CDR Setting not recommended for this baudrate due to insufficient precision
CDR Setting not to be used due to excessive time quanta (counter overflow)
1010 0000
0101 0000
1010 1000
0101 0100
1001 1000
0100 1100
CDR Setting not recommended for this baudrate due to insufficient precision
CDR Setting not to be used due to excessive time quanta (counter overflow)
CDR Setting not to be used due to excessive time quanta (counter overflow)
1010 0000
0101 0000
1010 1000
0101 0100
1001 1000
0100 1100
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK CDR Upper Limit Control
SWK_CDR_LIMIT_HIGH_CTRL
SWK CDR Upper Limit Control (Address 011 1110B)
POR / Soft Reset Value: 1010 1000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
CDR_LIM_H
rw
Field
Bits
Type Description
CDR_LIM_H
7:0
rw
Upper Bit Time Detection Range of Clock and Data Recovery
SWK_BTL1_CTRL values > + 5% will be clamped
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK CDR Lower Limit Control
SWK_CDR_LIMIT_LOW_CTRL
SWK CDR Lower Limit Control (Address 011 1111B)
POR / Soft Reset Value: 1001 1000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
CDR_LIM_L
rw
Field
Bits
Type Description
CDR_LIM_L
7:0
rw
Lower Bit Time Detection Range of Clock and Data Recovery
SWK_BTL1_CTRL values < - 5% will be clamped
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Serial Peripheral Interface
13.6
SPI Status Information Registers
Read/Clear Operation (see Chapter 13.3):
•
One 16-bit SPI command consist of two bytes:
- the 7-bit address and one additional bit for the register access mode and
- following the data byte will be ignored when accessing a status register
The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to
the SPI bits 8...15.
•
There are three different bit types:
- ‘r’ = READ: read only bits (or reserved bits)
- ‘rc’ = READ/CLEAR: readable and clearable bits
- ‘rh’ = READ/HARDWARE: readable and the possibility that the hardware can change the bits
•
•
•
Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only)
Clearing a register is done byte wise by setting the SPI bit 7 to “1”
SPI status registers are in general not cleared or changed automatically (an exception are the WD_FAIL
bits). This must be done by the microcontroller via SPI command
The registers are addressed wordwise.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.6.1
General Status Registers
Supply Voltage Fail Status 1
SUP_STAT_1
Supply Voltage Fail Status 1 (Address 100 0000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xx0x xxxxB
7
6
5
4
3
2
1
0
VB_UV_BST
VS_UV
Reserved
VEXT_OC
VREG_UV
VEXT_OT
VIO_OV
VIO_WARN
rc
rc
r
rc
rc
rc
rc
rc
Field
Bits
Type Description
VB_UV_BST
7
rc
VBSENSE low voltage detection
0B No VBSENSE low voltage detected
1B VBSENSE low voltage detected
VS_UV
6
rc
VS Undervoltage Detection (VS,UV
0B No VS undervoltage detected
1B VS undervoltage detected
)
Reserved
VEXT_OC
5
4
r
Reserved, always reads as 0
rc
VEXT Overcurrent Detection
0B No OC
1B OC detected
VREG_UV
3
rc
If PCFG is left open, the status is related to VEXT
0B No VEXT UV detection
1B VEXT UV Fail detected
If PCFG is connect to GND, the status is related to VCC1
0B No VCC1 UV detection
1B VCC1 UV Fail detected
VEXT_OT
VIO_OV
2
1
0
rc
rc
rc
VEXT Overtemperature Detection
0B No overtemperature
1B VEXT overtemperature detected
VIO Overvoltage Detection (VIO,OV,r
0B No VIO overvoltage warning
1B VIO overvoltage detected
)
VIO_WARN
VIO Undervoltage Prewarning (VPW,f)
0B No VIO undervoltage prewarning
1B VIO undervoltage prewarning detected
Notes
1. The VIO undervoltage prewarning threshold VPW,f is a fixed threshold and independent of the VIO
undervoltage reset thresholds.
2. VIO_WARN bit setting: It is never updated in SBC Restart Mode. In SBC Init Mode it is only updated after RSTN
was released for the first time. It is always updated in SBC Normal and Stop Mode. It is never updated in SBC
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Sleep Mode and it is always updated in any SBC modes in a VIO_SC condition (after VIO_UV = 1 longer than
t
VIO,SC).
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Supply Voltage Fail Status 0
SUP_STAT_0
Supply Voltage Fail Status 0 (Address 100 0001B)
POR / Soft Reset Value: y000 0000B;
Restart Value: x000 0xxxB
7
6
5
4
3
2
1
0
POR
Reserved
VIO_SC
VIO_UV_FS
VIO_UV
rc
r
rc
rc
rc
Field
Bits
Type Description
POR
7
rc
Power-On Reset Detection
0B No POR
1B POR occurred
Reserved
VIO_SC
6:3
2
r
Reserved, always reads as 0
rc
VIO Short to GND Detection
0B No short
1B VIO short to GND detected
VIO_UV_FS
VIO_UV
1
0
rc
rc
VIO UV-Detection (due to VRTx reset)
0B No Fail-Safe Mode entry due to 4th consecutive VIO_UV
1B Fail-Safe Mode entry due to 4th consecutive VIO_UV
VIO UV-Detection (due to VRTx reset)
0B No VIO_UV detection
1B VIO UV-Fail detected
Notes
1. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on
reset (POR value = 1000 0000). However it will be cleared after a SBC Software Reset command (Soft Reset
value = 0000 0000).
2. During SBC Sleep Mode, the bits VIO_SC, VIO_OV and VIO_UV will not be set because the regulator suppling
VIO is off.
3. The VIO_UV bit is never updated in SBC Restart Mode. In SBC Init Mode, it is only updated after RSTN was
released for the first time. It is always updated in SBC Normal and Stop Mode, and it is always updated in any
SBC modes in a VIO_SC condition (after VIO_UV = 1 longer than tVIO,SC).
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Thermal Protection Status
THERM_STAT
Thermal Protection Status (Address 100 0010B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0xx0 0xxxB
7
6
5
4
3
2
1
0
Reserved
VCC1_OT
BOOST_OT
Reserved
TSD2
TSD1
TPW
r
rc
rc
r
rc
rc
rc
Field
Bits
7
Type Description
Reserved
VCC1_OT
r
Reserved, always reads as 0
6
rc
VCC1 Overtemperature detection
0B No VCC1 overtemperature
1B VCC1 overtemperature detected
BOOST_OT
5
rc
Boost Overtemperature detection
0B No Boost overtemperature
1B Boost overtemperature detected
Reserved
TSD2
4:3
2
r
Reserved, always reads as 0
rc
TSD2 Thermal Shut-Down Detection
0B No TSD2 event
1B TSD2 OT detected - leading to SBC Fail-Safe Mode
TSD1
TPW
1
0
rc
rc
TSD1 Thermal Shut-Down Detection
0B No TSD1 fail
1B TSD1 OT detected
Thermal Pre Warning
0B No Thermal Pre warning
1B Thermal Pre warning detected
Note:
TPW, TSD1 and TSD2 are not reset automatically, even if the overtemperature pre warning or TSD1/2
conditions are not longer present.
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Serial Peripheral Interface
Device Information Status
DEV_STAT
Device Information Status (Address 100 0011B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xx00 xxxxB
7
6
5
4
3
2
1
0
FO_ON_STAT
E
DEV_STAT
Reserved
WD_FAIL
SPI_FAIL
rc
r
rh
rc
rc
Field
Bits
Type Description
DEV_STAT
7:6
rc
Device Status before Restart Mode
00B Cleared (Register must be actively cleared)
01B Restart due to failure described in Table 8 and Table 9.
10B Sleep Mode
11B Reserved
Reserved
WD_FAIL
5:4
3:2
r
Reserved, always reads as 0
rh
Number of WD-Failure Events (1/2 WD failures depending on INTN)
00B No WD Fail
01B 1x WD Fail, FOx activation- Config 1/2
10B 2x WD Fail, FOx activation- Config 3/4
11B Reserved (never reached)
SPI_FAIL
1
0
rc
rc
SPI Fail Information
0B No SPI fail
1B Invalid SPI command detected
FO_ON_STATE
Activation of Fail Output FO
0B No Failure
1B Failure occurred, FO is activated
Notes
1. The WD_FAIL bits are configured as a counter and are the only status bits, which are cleared automatically
by the SBC. They are cleared after a successful watchdog trigger and when the watchdog is stopped (also in
SBC Sleep and Fail-Safe Mode unless it was reached due to a watchdog failure). See also Chapter 11.1.
2. The SPI_FAIL bit is cleared only by SPI command.
3. With Config 2/4, the WD_Fail counter is frozen in case of WD trigger failure until a successful WD trigger occurs.
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Serial Peripheral Interface
Bus Communication Status 0
BUS_STAT_0
Bus Communication Status 0 (Address 100 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 000x xxxxB
7
6
5
4
3
2
1
0
Reserved
CANTO_0
SYSERR_0
CAN_0_FAIL
VCAN_UV
r
rc
rc
rc
rc
Field
Bits
7:5
4
Type Description
Reserved
CANTO_0
r
Reserved, always reads as 0
rc
CAN_0 Time Out Detection
0B Normal operation
1B CAN Time Out detected
SYSERR_0
3
rc
rc
CAN_0 SWK System Error
0B Selective Wake Mode is possible
1B System Error detected, SWK enabling not possible
CAN_0_FAIL
2:1
CAN_0 Failure Status
00B No error
01B CAN TSD shutdown
10B CAN_TXD_DOM: TXD dominant time out for more than 2ms
11B CAN_BUS_DOM: BUS dominant time out for more than 2ms
VCAN_UV
Notes
0
rc
Undervoltage CAN Bus Supply
0B Normal operation
1B CAN Supply undervoltage detected. Transmitter disabled
1. CAN0 Recovery Conditions:
1.) TXD Time Out: TXDCAN0 goes HIGH or transmitter is switched off or the transceiver is wake capable;
2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off.
3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VCAN > VCAN_UV
4.) In all cases (also for TSD shutdown): to enable the Bus transmission again, TXDCAN0 needs to be HIGH for
a certain time (transmitter enable time).
2. The VCAN_UV comparator is enabled if the mode bit CANx_1 = ‘1’, i.e. in CAN Normal or CAN Receive Only
Mode.
3. CANTO_x is set only if CANx_2 = 1 (=SWK Mode enabled). It is set as soon as CANSIL_x is set and stays set even
in CANSIL_x is reset. An interrupt is issued in SBC Stop and SBC Normal Mode as soon as CANTO_x is set and
the interrupt is not masked out, i.e. CANTO_x must be set to 1.
4. The SYSERR_x flag is set in case of a configuration error and in case of an error counter overflow (n>32).
It is only updated if SWK is enabled (CANx_2 = ‘1’). See also Chapter 5.3.3.
5. CANTO_x is set asynchronously to the INTN pulse. In order to prevent undesired clearing of CANTO_x and thus
possibly missing this interrupt, the bit will be prevented from clearing (i.e. cannot be cleared) until the next
falling edge of INTN.
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Wake-up Source and Information Status 0
WK_STAT_0
Wake-up Source and Information Status 0 (Address 100 0110B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: x0xx 000xB
7
6
5
4
3
2
1
0
PFM_PWM
Reserved
CAN_0_WU TIMER_0_WU
rc rc
Reserved
WK_WU
rc
r
r
rc
Field
Bits
Type Description
PFM_PWM
7
rc
PFM_PWM automatic transition detected
0B No automatic PFM_PWM transition detected
1B Automatic PFM_PWM transition detected
Reserved
6
5
r
Reserved, always reads as 0
CAN_0_WU
rc
Wake up via CAN_0 Bus
0B No Wake up
1B Wake up
TIMER_0_WU
4
rc
Wake up via cyclic wake
0B No Wake up
1B Wake up
Reserved
WK_WU
3:1
0
r
Reserved, always reads as 0
rc
Wake up via WK
0B No Wake up
1B Wake up
Note:
The respective wake source bit will also be set when the device is woken from SBC Fail-Safe Mode.
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WK Input Level
WK_LVL_STAT
WK Input Level (Address 100 1000B)
POR / Soft Reset Value: xx0x 000xB;
Restart Value: xxxx x00xB
7
6
5
4
3
2
1
0
VBAT_UV_ST
ATE
TEST
CFG1_STATE CFG2_STATE PCFG_STATE
Reserved
WK
r
r
r
r
r
r
r
Field
Bits
Type Description
TEST
7
r
r
r
Status of SBC Development Mode
0B LOW Level (=0), Normal User Operation, SBC Development Mode is
disabled
1B HIGH Level (=1), SBC Development Mode is enabled, no reset
triggered due to wrong Watchdog trigger
CFG1_STATE
CFG2_STATE
6
5
Status of INTN Pin
This bit shows the level of the INTN pin regarding the device configuration
0B LOW Level; Fail-Safe Mode entered due to WD failure (1 or 2 failure)
depending on CFG2 bit) Config 2/4
1B HIGH Level; Fail-Safe Mode not entered, due to WD failure, Config 1/3
Status of CFG2 bit on HW_CTRL_0 register
This bit shows the setting in bit CFG2
0B LOW Level (=0), Fail Outputs (FOx) are active after 2nd watchdog
trigger fail Config 3/4
1B HIGH Level (=1); Fail Outputs (FOx) are active after 1st watchdog
trigger fail Config 1/2
PCFG_STATE
4
3
r
r
Status of PCFG Pin
0B LOW Level; the VEXT is fix at 3.3V and it has to be connected to VIO to
supply the microcontroller (connected to GND)
1B HIGH Level; the microcontroller is supplied from the VCC1 and
VIO=VCC1. The VEXT is fully configurable (left OPEN)
VBAT_UV_
STATE
VBSENSE Undervoltage Detection Status
0B No VBSENSE undervoltage detected
1B VBSENSE undervoltage detected
Reserved
WK
2:1
0
r
r
Reserved, always reads as 0
Status of WK
0B LOW Level (=0)
1B HIGH Level (=1)
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Serial Peripheral Interface
Wake-up Source and Information Status 2
WK_STAT_2
Wake-up Source and Information Status 2 (Address 100 1001B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: x000 0xxxB
7
6
5
4
3
2
1
0
VBAT_UV_LA
TCH
Reserved
CAN_3_WU CAN_2_WU CAN_1_WU
rc rc rc
rc
r
Field
Bits
Type Description
VBAT_UV_
LATCH
7
rc
VBSENSE Undervoltage Detection
0B No VBSENSE undervoltage detected
1B VBSENSE undervoltage detected (latched status)
Reserved
6:3
2
r
Reserved, always reads as 0
CAN_3_WU
rc
Wake up via CAN_3 Bus
0B No wake up
1B Wake up
CAN_2_WU
CAN_1_WU
1
0
rc
rc
Wake up via CAN_2 Bus
0B No wake up
1B Wake up
Wake up via CAN_1 Bus
0B No wake up
1B Wake up
Note:
The respective wake source bit will also be set when the device is woken from SBC Fail-Safe Mode.
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Bus Communication Status 2
BUS_STAT_2
Bus Communication Status 2 (Address 100 1010B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
CANTO_2
SYSERR_2
CAN_2_FAIL
CANTO_1
SYSERR_1
CAN_1_FAIL
rc
rc
rc
rc
rc
rc
Field
Bits
Type Description
CANTO_2
7
rc
rc
rc
CAN_2 Time Out Detection
0B Normal operation
1B CAN Time Out detected
SYSERR_2
CAN_2_FAIL
6
CAN_2 SWK System Error
0B Selective Wake Mode is possible
1B System Error detected, SWK enabling not possible
5:4
CAN_2 Failure Status
00B No error
01B CAN TSD shutdown
10B CAN_TXD_DOM: TXD dominant time out for more than 2ms
11B CAN_BUS_DOM: BUS dominant time out for more than 2ms
CANTO_1
3
rc
rc
rc
CAN_1 Time Out Detection
0B Normal operation
1B CAN Time Out detected
SYSERR_1
CAN_1_FAIL
2
CAN_1 SWK System Error
0B Selective Wake Mode is possible
1B System Error detected, SWK enabling not possible
1:0
CAN_1 Failure Status
00B No error
01B CAN TSD shutdown
10B CAN_TXD_DOM: TXD dominant time out for more than 2ms
11B CAN_BUS_DOM: BUS dominant time out for more than 2ms
Notes
1. CAN Recovery Conditions:
1.) TXD Time Out: TXDCANx goes HIGH or transmitter is switched off or the transceiver is wake capable.
2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off.
3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VCAN > VCAN_UV.
4.) In all cases (also for TSD shutdown): to enable the Bus transmission again, TXDCANx needs to be HIGH for
a certain time (transmitter enable time).
2. CANTO_x is set only if CANx_2 = 1 (=SWK Mode enabled). It is set as soon as CANSIL_x is set and remains set
even in CANSIL_x is reset. An interrupt is issued in SBC Stop and SBC Normal Mode as soon as CANTO_x is set
and the interrupt is not masked out, i.e. CANTO_x must be set to 1.
3. The SYSERR_x Flag is set in case of a configuration error and in case of an error counter overflow (n>32).
It is only updated if SWK is enabled (CANx_2 = ‘1’). See also Chapter 5.3.3.
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4. CANTO_x is set asynchronously to the INTN pulse. In order to prevent undesired clearing of CANTO_x and thus
possibly missing this interrupt, the bit will be prevented from clearing (i.e. cannot be cleared) until the next
falling edge of INTN.
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Serial Peripheral Interface
Bus Communication Status 3
BUS_STAT_3
Bus Communication Status 3 (Address 100 1011B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 xxxxB
7
6
5
4
3
2
1
0
Reserved
CANTO_3
SYSERR_3
CAN_3_FAIL
r
rc
rc
rc
Field
Bits
7:4
3
Type Description
Reserved
CANTO_3
r
Reserved, always reads as 0
rc
CAN_3 Time Out Detection
0B Normal operation
1B CAN Time Out detected
SYSERR_3
2
rc
rc
CAN_3 SWK System Error
0B Selective Wake Mode is possible
1B System Error detected, SWK enabling not possible
CAN_3_FAIL
1:0
CAN_3 Failure Status
00B No error
01B CAN TSD shutdown
10B CAN_TXD_DOM: TXD dominant time out for more than 2ms
11B CAN_BUS_DOM: BUS dominant time out for more than 2ms
Notes
1. CAN Recovery Conditions:
1.) TXD Time Out: TXDCAN3 goes HIGH or transmitter is switched off or the transceiver is wake capable.
2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off.
3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VCAN > VCAN_UV.
4.) In all cases (also for TSD shutdown): to enable the Bus transmission again, TXDCAN3 needs to be HIGH for
a certain time (transmitter enable time).
2. CANTO_x is set only if CANx_2 = 1 (=SWK Mode enabled). It is set as soon as CANSIL_x is set and will stay set
even in CANSIL_x it is reset. An interrupt is issued in SBC Stop and SBC Normal Mode as soon as CANTO_x is set
and the interrupt is not masked out, i.e. CANTO_x must be set to 1.
3. The SYSERR_x Flag is set in case of a configuration error and in case of an error counter overflow (n>32).
It is only updated if SWK is enabled (CANx_2 = ‘1’). See also Chapter 5.3.3.
4. CANTO_x is set asynchronously to the INTN pulse. In order to prevent undesired clearing of CANTO_x and thus
possibly missing this interrupt, the bit will be prevented from clearing (i.e. cannot be cleared) until the next
falling edge of INTN.
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SMPS state
SMPS_STAT
SMPS state (Address 100 1100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxx0 0xx0B
7
6
5
4
3
2
1
0
BST_ACT
BST_SH
BST_OP
Reserved
BCK_SH
BCK_OP
Reserved
rc
rc
rc
r
rc
rc
r
Field
Bits
Type Description
BST_ACT
BST_SH
BST_OP
7
rc
rc
rc
Boost Regulator Active
0B Boost not active
1B Boost active
6
5
BSTD short detection
0B No short detected on BSTD pin
1B BSTD short to supply
BSTD open detection
0B No open detected on BSTD pin
1B BSTD loss of diode detected or loss of Boost GND
Reserved
BCK_SH
4:3
2
r
Reserved, always reads as 0
rc
BCKSW pin short detection
0B No BCKSW short detected
1B Short to GND or short to VS detected on BCKSW pin
BCK_OP
1
0
rc
r
BCKSW pin open detection
0B No BCKSW open detected
1B BCKSW loss of freewheeling or BCKSW loss of GND
Reserved
Reserved, always reads as 0
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
ADC state
ADC_STAT
ADC state (Address 101 1000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
ADC
rc
Field
ADC
Bits
Type Description
rc ADC output
7:0
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.6.2
Selective Wake Status Registers
Selective Wake Status CAN_3
SWK_STAT_3
Selective Wake Status CAN_3 (Address 110 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
SYNC_3
Reserved
CANSIL_3
SWK_SET_3
WUP_3
WUF_3
r
r
r
r
r
r
r
Field
Bits
7
Type Description
Reserved
SYNC_3
r
r
Reserved, always reads as 0
6
CAN_3 Synchronisation (at least one CAN frame without fail must
have been received)
0B SWK function not working or not synchronous to CAN bus
1B Valid CAN frame received, SWK function is synchronous to CAN_3
bus
Reserved
CANSIL_3
5:4
3
r
r
Reserved, always reads as 0
CAN_3 Silent Time during SWK operation
0B tsilence not exceeded
1B
set if tsilence is exceeded.
SWK_SET_3
WUP_3
2
1
0
r
r
r
CAN_3 Selective Wake Activity
0B Selective Wake is not active
1B Selective Wake is activated
CAN_3 Wake-up Pattern Detection
0B No WUP
1B WUP detected
WUF_3
CAN_3 SWK Wake-up Frame Detection (acc. ISO 11898-6)
0B No WUF
1B WUF detected
Note:
SWK_SET_x is set to flag that the selective wake functionality is activated (SYSERR_x = 0,
CFG_VAL = 1, CANx_2 = 1). The selective wake function is activated via a CAN mode change, except if
CANx = ‘100’.
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Error Counter Status CAN_3
SWK_ECNT_STAT_3
SWK Error Counter Status CAN_3 (Address 110 0101B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
ECNT_3
r
r
Field
Bits
7:6
Type Description
Reserved
ECNT_3
r
r
Reserved, always reads as 0
5:0
SWK CAN_3 Frame Error Counter
00 0000B No Frame Error
01 1111B 31 Frame Errors have been counted
10 0000B Error counter overflow - SWK function will be disabled
Note:
If a frame has been received that is valid according to ISO 11898-1 and the counter is not zero, then
the counter shall be decremented. If the counter has reached a value of 32, the following actions
shall be performed: Selective Wake function shall be disabled, SYSERR_x shall be set and the CAN
wake capable function shall be enabled, which leads to a wake with the next WUP.
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Status CAN_3_1
SWK_CDR_STAT_3_1
CDR Status CAN_3_1 (Address 110 0110B)
POR / Soft Reset Value: 1010 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
NAVG_SAT_3
r
Field
Bits
Type Description
Output Value from Filter Block
NAVG_SAT_3
7:0
r
N_AVG is representing the integer part of the number of selected input
clock frequency per CAN bus bit.
N_AVG[11:4] e.g.160.75
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Status CAN_3_0
SWK_CDR_STAT_3_0
CDR Status CAN_3_0 (Address 110 0111B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
NAVG_SAT_3
Reserved
r
r
Field
Bits
Type Description
NAVG_SAT_3
7:4
r
r
Output Value from Filter Block
N_AVG is representing the fractional part of the number of selected input
clock frequency per CAN bus bit.
N_AVG[3:0] e.g.160.75
Reserved
3:0
Reserved, always reads as 0
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Selective Wake Status CAN_2
SWK_STAT_2
Selective Wake Status CAN_2 (Address 110 1000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
SYNC_2
Reserved
CANSIL_2
SWK_SET_2
WUP_2
WUF_2
r
r
r
r
r
r
r
Field
Bits
7
Type Description
Reserved
SYNC_2
r
r
Reserved, always reads as 0
6
CAN_2 Synchronisation (at least one CAN frame without fail must
have been received)
0B SWK function not working or not synchronous to CAN bus
1B Valid CAN frame received, SWK function is synchronous to CAN_2
bus
Reserved
CANSIL_2
5:4
3
r
r
Reserved, always reads as 0
CAN_2 Silent Time during SWK operation
0B tsilence not exceeded
1B
set if tsilence is exceeded.
SWK_SET_2
WUP_2
2
1
0
r
r
r
CAN_2 Selective Wake Activity
0B Selective Wake is not active
1B Selective Wake is activated
CAN_2 Wake-up Pattern Detection
0B No WUP
1B WUP detected
WUF_2
CAN_2 SWK Wake-up Frame Detection (acc. ISO 11898-6)
0B No WUF
1B WUF detected
Note:
SWK_SET_x is set to flag that the selective wake functionality is activated (SYSERR_x = 0,
CFG_VAL = 1, CANx_2 = 1). The selective wake function is activated via a CAN mode change, except if
CANx = ‘100’.
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Error Counter Status CAN_2
SWK_ECNT_STAT_2
SWK Error Counter Status CAN_2 (Address 110 1001B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
ECNT_2
r
r
Field
Bits
7:6
Type Description
Reserved
ECNT_2
r
r
Reserved, always reads as 0
5:0
SWK CAN_2 Frame Error Counter
00 0000B No Frame Error
01 1111B 31 Frame Errors have been counted
10 0000B Error counter overflow - SWK function will be disabled
Note:
If a frame has been received that is valid according to ISO 11898-1 and the counter is not zero, then
the counter shall be decremented. If the counter has reached a value of 32, the following actions
shall be performed: Selective Wake function shall be disabled, SYSERR_x shall be set and the CAN
wake capable function shall be enabled, which leads to a wake with the next WUP.
Datasheet
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Rev. 1.5
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Status CAN_2_1
SWK_CDR_STAT_2_1
CDR Status CAN_2_1 (Address 110 1010B)
POR / Soft Reset Value: 1010 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
NAVG_SAT_2
r
Field
Bits
Type Description
Output Value from Filter Block
NAVG_SAT_2
7:0
r
N_AVG is representing the integer part of the number of selected input
clock frequency per CAN bus bit.
N_AVG[11:4] e.g.160.75
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Status CAN_2_0
SWK_CDR_STAT_2_0
CDR Status CAN_2_0 (Address 110 1011B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
NAVG_SAT_2
Reserved
r
r
Field
Bits
Type Description
NAVG_SAT_2
7:4
r
r
Output Value from Filter Block
N_AVG is representing the fractional part of the number of selected input
clock frequency per CAN bus bit.
N_AVG[3:0] e.g.160.75
Reserved
3:0
Reserved, always reads as 0
Datasheet
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TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Selective Wake Status CAN_1
SWK_STAT_1
Selective Wake Status CAN_1 (Address 110 1100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
SYNC_1
Reserved
CANSIL_1
SWK_SET_1
WUP_1
WUF_1
r
r
r
r
r
r
r
Field
Bits
7
Type Description
Reserved
SYNC_1
r
r
Reserved, always reads as 0
6
CAN_1 Synchronisation (at least one CAN frame without fail must
have been received)
0B SWK function not working or not synchronous to CAN bus
1B Valid CAN frame received, SWK function is synchronous to CAN_1
bus
Reserved
CANSIL_1
5:4
3
r
r
Reserved, always reads as 0
CAN_1 Silent Time during SWK operation
0B tsilence not exceeded
1B
set if tsilence is exceeded.
SWK_SET_1
WUP_1
2
1
0
r
r
r
CAN_1 Selective Wake Activity
0B Selective Wake is not active
1B Selective Wake is activated
CAN_1 Wake-up Pattern Detection
0B No WUP
1B WUP detected
WUF_1
CAN_1 SWK Wake-up Frame Detection (acc. ISO 11898-6)
0B No WUF
1B WUF detected
Note:
SWK_SET_x is set to flag that the selective wake functionality is activated (SYSERR_x = 0,
CFG_VAL = 1, CANx_2 = 1). The selective wake function is activated via a CAN mode change, except if
CANx = ‘100’.
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Error Counter Status CAN_1
SWK_ECNT_STAT_1
SWK Error Counter Status CAN_1 (Address 110 1101B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
ECNT_1
r
r
Field
Bits
7:6
Type Description
Reserved
ECNT_1
r
r
Reserved, always reads as 0
5:0
SWK CAN_1 Frame Error Counter
00 0000B No Frame Error
01 1111B 31 Frame Errors have been counted
10 0000B Error counter overflow - SWK function will be disabled
Note:
If a frame has been received that is valid according to ISO 11898-1 and the counter is not zero, then
the counter shall be decremented. If the counter has reached a value of 32, the following actions
shall be performed: Selective Wake function shall be disabled, SYSERR_x shall be set and the CAN
wake capable function shall be enabled, which leads to a wake with the next WUP.
Datasheet
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Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Status CAN_1_1
SWK_CDR_STAT_1_1
CDR Status CAN_1_1 (Address 110 1110B)
POR / Soft Reset Value: 1010 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
NAVG_SAT_1
r
Field
Bits
Type Description
Output Value from Filter Block
NAVG_SAT_1
7:0
r
N_AVG is representing the integer part of the number of selected input
clock frequency per CAN bus bit.
N_AVG[11:4] e.g.160.75
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Status CAN_1_0
SWK_CDR_STAT_1_0
CDR Status CAN_1_0 (Address 110 1111B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
NAVG_SAT_1
Reserved
r
r
Field
Bits
Type Description
NAVG_SAT_1
7:4
r
r
Output Value from Filter Block
N_AVG is representing the fractional part of the number of selected input
clock frequency per CAN bus bit.
N_AVG[3:0] e.g.160.75
Reserved
3:0
Reserved, always reads as 0
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Selective Wake Status CAN_0
SWK_STAT_0
Selective Wake Status CAN_0 (Address 111 0000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
SYNC_0
Reserved
CANSIL_0
SWK_SET_0
WUP_0
WUF_0
r
r
r
r
r
r
r
Field
Bits
7
Type Description
Reserved
SYNC_0
r
r
Reserved, always reads as 0
6
CAN_0 Synchronisation (at least one CAN frame without fail must
have been received)
0B SWK function not working or not synchronous to CAN bus
1B Valid CAN frame received, SWK function is synchronous to CAN_0
bus
Reserved
CANSIL_0
5:4
3
r
r
Reserved, always reads as 0
CAN_0 Silent Time during SWK operation
0B tsilence not exceeded
1B
set if tsilence is exceeded.
SWK_SET_0
WUP_0
2
1
0
r
r
r
CAN_0 Selective Wake Activity
0B Selective Wake is not active
1B Selective Wake is activated
CAN_0 Wake-up Pattern Detection
0B No WUP
1B WUP detected
WUF_0
CAN_0 SWK Wake-up Frame Detection (acc. ISO 11898-6)
0B No WUF
1B WUF detected
Note:
SWK_SET_x is set to flag that the selective wake functionality is activated (SYSERR_x = 0,
CFG_VAL = 1, CANx_2 = 1). The selective wake function is activated via a CAN mode change, except if
CANx = ‘100’.
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
SWK Error Counter Status CAN_0
SWK_ECNT_STAT_0
SWK Error Counter Status CAN_0 (Address 111 0001B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
Reserved
ECNT_0
r
r
Field
Bits
7:6
Type Description
Reserved
ECNT_0
r
r
Reserved, always reads as 0
5:0
SWK CAN_0 Frame Error Counter
00 0000B No Frame Error
01 1111B 31 Frame Errors have been counted
10 0000B Error counter overflow - SWK function will be disabled
Note:
If a frame has been received that is valid according to ISO 11898-1 and the counter is not zero, then
the counter shall be decremented. If the counter has reached a value of 32, the following actions
shall be performed: Selective Wake function shall be disabled, SYSERR_x shall be set and the CAN
wake capable function shall be enabled, which leads to a wake with the next WUP.
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Status CAN_0_1
SWK_CDR_STAT_0_1
CDR Status CAN_0_1 (Address 111 0010B)
POR / Soft Reset Value: 1010 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
NAVG_SAT_0
r
Field
Bits
Type Description
Output Value from Filter Block
NAVG_SAT_0
7:0
r
N_AVG is representing the integer part of the number of selected input
clock frequency per CAN bus bit.
N_AVG[11:4] e.g.160.75
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
CDR Status CAN_0_0
SWK_CDR_STAT_0_0
CDR Status CAN_0_0 (Address 111 0011B)
POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
NAVG_SAT_0
Reserved
r
r
Field
Bits
Type Description
NAVG_SAT_0
7:4
r
r
Output Value from Filter Block
N_AVG is representing the fractional part of the number of selected input
clock frequency per CAN bus bit.
N_AVG[3:0] e.g.160.75
Reserved
3:0
Reserved, always reads as 0
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.6.3
Family and Product Information Register
Family and Product Identification Register
FAM_PROD_STAT
Family and Product Identification Register (Address 111 1110B)
POR / Soft Reset Value: 0100 yyyy B; Restart Value: 0100 yyyyB
7
6
5
4
3
2
1
0
FAM
PROD
r
r
Field
FAM
Bits
Type Description
7:4
r
SBC Family Identifier (bit4=LSB; bit7=MSB)
0 0 01BDriver SBC Family
0 0 10BDC/DC-SBC Family
0 0 11BMid-Range SBC Family
0 1 00BMulti-CAN Power+ SBC Family
0 1 01BLITE SBC Family
0 1 00BMid-Range+ SBC Family
PROD
Notes
3:0
r
SBC Product Identifier (bit0=LSB; bit3=MSB)
0 0 0 0BTLE9278-3BQX
0 0 0 1BTLE9278-3BQX V33
0 0 1 0BTLE9278BQX
0 0 1 1BTLE9278BQX V33
1. The actual default register value after POR, Soft Reset or Restart of PROD depends on the respective product.
Therefore the value ‘y’ is specified.
Datasheet
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Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
13.7
Electrical Characteristics
Table 34 Electrical Characteristics: Power Stage
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
SPI frequency
1)
Maximum SPI frequency
fSPI,max
–
–
4.0
MHz
P_13.7.1
SPI Interface; Logic Inputs SDI, CLK and CSN
H-input Voltage Threshold VIH
L-input Voltage Threshold VIL
Hysteresis of input Voltage VIHY
–
–
–
0.7 ×
VIO
V
–
–
P_13.7.2
P_13.7.3
P_13.7.4
P_13.7.5
P_13.7.6
P_13.7.7
0.3 ×
VIO
–
V
1)
–
0.2 ×
VIO
–
V
–
Pull-up Resistance at pin
CSN
RICSN
20
20
–
40
40
10
80
80
–
kΩ
kΩ
pF
VCSN = 0.7 × VIO
Pull-down Resistance at pin RICLK/SDI
SDI and CLK
VSDI/CLK = 0.2 × VIO
1)
Input Capacitance at pin
CSN, SDI or CLK
CI
Logic Output SDO
H-output Voltage Level
L-output Voltage Level
Tri-state Leakage Current
VSDOH
VSDOL
ISDOLK
VIO - 0.4 VIO - 0.2 –
V
IDOH = -1.6 mA
IDOL = 1.6 mA
P_13.7.8
P_13.7.9
P_13.7.10
–
0.2
–
0.4
10
V
-10
µA
VCSN = VIO;
0 V < VDO < VIO
1)
‘Tri-state Input Capacitance CSDO
–
10
15
pF
P_13.7.11
Data Input Timing1)
Clock Period
tpCLK
tCLKH
tCLKL
250
125
125
125
250
250
125
100
50
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
P_13.7.12
P_13.7.13
P_13.7.14
P_13.7.15
P_13.7.16
P_13.7.17
P_13.7.18
P_13.7.19
P_13.7.20
P_13.7.21
Clock HIGH Time
Clock LOW Time
–
–
Clock LOW before CSN LOW tbef
–
CSN Setup Time
CLK Setup Time
tlead
tlag
–
–
Clock LOW after CSN HIGH tbeh
–
SDI Setup Time
SDI Hold Time
tDISU
tDIHO
–
–
Input Signal Rise Time at pin trIN
–
50
SDI, CLK and CSN
Input Signal Fall Time at pin tfIN
–
–
50
ns
–
P_13.7.22
SDI, CLK and CSN
Datasheet
184
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Serial Peripheral Interface
Table 34 Electrical Characteristics: Power Stage
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
Delay Time for Mode
Changes2)
tDel,Mode
tCSN(high)
–
5
µs
–
P_13.7.23
P_13.7.24
CSN HIGH Time
Data Output Timing1)
SDO Rise Time
3
–
–
µs
–
trSDO
–
–
–
–
–
30
30
–
80
80
50
50
50
ns
ns
ns
ns
ns
CL = 100 pF
P_13.7.25
P_13.7.26
P_13.7.27
P_13.7.28
P_13.7.29
SDO Fall Time
tfSDO
CL = 100 pF
SDO Enable Time
SDO Disable Time
SDO Valid Time
tENSDO
tDISSDO
tVASDO
LOW impedance
HIGH impedance
CL = 100 pF
–
–
1) Not subject to production test; specified by design.
2) Applies to all mode changes triggered via SPI commands.
24
CSN
15
16
17
18
13
14
CLK
SDI
19
20
LSB
MSB
not defined
27
28
29
SDO
Flag
LSB
MSB
Figure 51 SPI Timing Diagram
Note:
Numbers in drawing correlate with the last 2 digits of the Number field in the Electrical
Characteristics table.
Datasheet
185
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Application Information
14
Application Information
14.1
Application Diagram
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
Vext
T2
RSHUNT
C6
IC1
TDR
TXD
TDR
TXD
VCC
VSUP/VS
C8
PHY
C7
RXD
RXD
R2
GND
VCC1
VCC1
VS
Vsup
D1
C1
L1
D2
L2
VS
VS
VBAT
BCKSW
VCC1
C4
C5
C2
C3
C1fil
BSTD
BSTD
R1
VDD
CLK
CSN
SDI
CLK
CSN
SDI
GND
GND
SDO
SDO
NRO
RSTN
INTN
PCFG
NINT µC
VS
T1
TLE9278x
TXDCAN0
RXDCAN0
TXDCAN1
RXDCAN1
TXDCAN2
RXDCAN2
TXDCAN3
RXDCAN3
TXDCAN0
RXDCAN0
TXDCAN1
RXDCAN1
TXDCAN2
RXDCAN2
TXDCAN3
RXDCAN3
FO
C9
VS
FO
WK
S3
R4
VSS
R3
VCC1
CVCAN
VCAN
CANH2
CANH0
CANH0
CANH2
RCANH
RCANH
CCAN
CCAN
RCANL
RCANL
CANL0
CANH1
CANL2
CANH3
CANL0
CANH1
CANL2
CANH3
RCANH
RCANH
CCAN
CCAN
RCANL
RCANL
CANL3
CANL1
CANL3
CANL1
GND
Figure 52 TLE9278-3BQX Application Diagram
Datasheet
186
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Application Information
Vext=3.3V
C6
T2
RSHUNT
VCC1=5V
C8
R2
Vext=3.3V
IC1
VCC1=5V
TDR
TXD
TDR
TXD
VS
Vsup
D1
C1
L1
D2
L2
VS
VS
VCC
VBAT
BCKSW
PHY
C4
C5
C2
C3
C1fil
C7
RXD
RXD
GND
VCC1
BSTD
BSTD
R1
VDD
CLK
CSN
SDI
CLK
CSN
SDI
GND
GND
SDO
SDO
NRO
RSTN
INTN
PCFG
NINT µC
VS
T1
TLE9278x
TXDCAN0
RXDCAN0
TXDCAN1
RXDCAN1
TXDCAN2
RXDCAN2
TXDCAN3
RXDCAN3
TXDCAN0
RXDCAN0
TXDCAN1
RXDCAN1
TXDCAN2
RXDCAN2
TXDCAN3
RXDCAN3
FO
C9
VS
FO
WK
S3
R4
VSS
R3
VCC1
CVCAN
VCAN
CANH2
CANH0
CANH0
CANH2
RCANH
RCANH
CCAN
CCAN
RCANL
RCANL
CANL0
CANH1
CANL2
CANH3
CANL0
CANH1
CANL2
CANH3
RCANH
RCANH
CCAN
CCAN
RCANL
RCANL
CANL3
CANL1
CANL3
CANL1
GND
Figure 53 TLE9278-3BQX Application Diagram where the microcontroller is supplied by VEXT
with 3.3 V
Datasheet
187
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Application Information
Table 35 Bill of Material
Ref.
Typical Value
Purpose / Comment
Capacitances
C1
47 µF ± 20%
Electrolytic
Buffering capacitor to cut off battery spikes, depending on the
application. The voltage rating depends on the application.
C1fil
C2
100 nF ± 20%, 50 V
ceramic
Input filter battery capacitor for optimum EMC behavior.
Output Boost capacitor. ESR ≤ 1Ω over the temperature range.
Input Buck capacitor. Low ESR.
100 µF ± 20%, 50 V,
Electrolytic
C3
1..10 µF ± 20%, 50 V
Ceramic
C4, C5
C6
22 µF ± 20%, 16V
Ceramic
Output Buck capacitor, for optimum current capability and
dynamic behavior. Low ESR.
1)
10 µF ± 20%, 16 V
ceramic
V
Output capacitor. Low ESR.
EXT
C7
470 pF ± 20%, 16 V
ceramic
VEXT Filter capacitor (only needed if used for off-board supply).
VBSENSE blocking capacitor. Low ESR.
C8
22 nF ± 20%, 16 V
ceramic
C9
22 nF ± 20%, 16 V
ceramic
Spikes filtering, as required by application. Mandatory
protection for off-board connection.
CVCAN
1 µF ± 20%, 16 V
ceramic
Input filter CAN supply. The capacitor must be placed close to
the VCAN pin. For optimum EMC and CAN FD performances, the
capacitor has to be ≥ 4.7 µF
CCANx
47 nF / OEM dependent
Split termination stability.
Resistances
RSHUNT
1 Ω ± 1%
Sense shunt for VEXT current limitation (configured to typ.
235 mA with 1 Ω shunt).
R1
10 kΩ..22 kΩ ± 5%
Selection of hardware configuration 1/3, i.e. in case of WD failure
SBC Restart Mode is entered.
If not connected, then the hardware configuration 2/4 is
selected.
R2
10 kΩ ± 5% 2)
Limit the VBSENSE pin input current.
Wetting current of the switch, as required by application.
Limit the WK pin input current, e.g. for ISO pulses.
CAN bus termination.
R3
10 kΩ ± 5%
R4
10 kΩ ± 5%
RCANHx
RCANL
Inductors
L1
60 Ω / OEM dependent
60 Ω / OEM dependent
CAN bus termination.
22 µH..47 µH ± 20%
47 µH ± 20%
3) Boost regulator coil. The saturation current depends on the
application.
3) Buck regulator coil. The saturation current depends on the
application.
L2
Active Components
Datasheet
188
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Application Information
Table 35 Bill of Material (cont’d)
Ref.
Typical Value
Purpose / Comment
D1
e.g.SS34HE3/9AT (Vishay) Reverse polarity protection.
or similar
D2
T2
e.g. SL04-GS08 (Vishay) or Boost regulator power diode. Forward current depends on the
SS34HE3/9AT
application.
BCP 52-16, Infineon
Power element of VEXT, current limit to be configured via shunt
RSHUNT
.
MJD253, ON Semi
e.g. XC2xxx
Alternative power element of VEXT.
µC
Microcontroller.
1) For optimized EMC performance, one additional filter capacitor ≤ 10 nF ± 20% 16 V ceramic is required.
2) For ISO7637-2 pulse robustness, a higher value might be needed.
3) The saturation current must be define according to the maximum current capability by the application.
5V_int
Ttest
SBC Init
Mode
RTEST
Connector/
FO/TEST Jumper
REXT
TFO
Failure Logic
Figure 54 Hint for Increasing the Robustness of pin FO/TEST during Debugging or Programming
Datasheet
189
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Application Information
14.2
ESD Tests
Tests for ESD robustness according to IEC61000-4-2 “GUN test” (150 pF, 330 Ω) have been performed.
The results and test condition are available in a test report. The values for the tests are listed below.
Table 36 ESD “GUN Test”1)2)
Performed Test
Result
Unit
Remarks
ESD at pin VS, VBSENSE,
VEXTIN, VEXTREF, WK,
CANHx, CANLx versus GND
> 6
kV
positive pulse
ESD at pin VS, VBSENSE,
VEXTIN, VEXTREF, WK,
CANHx, CANLx versus GND
< -6
kV
negative pulse
1) ESD susceptibility “ESD GUN” according to EMC 1.3 Test Specification, Section 4.3 (IEC 61000-4-2). Tested by external
test house (IBEE Zwickau, EMC Test report No. 09-12-18).
2) ESD Test “GUN Test” is specified with external components for pins VS, VBSENSE, VEXTIN, VEXTREF and WK. See the
application diagrams in Chapter 14.1 for more information.
EMC and ESD susceptibility tests according to SAE J2962-2 (V. 2014-01-23) have been performed. Tested by
external test house (Jakob Mooser GmbH, Test report No. 434/2016).
Datasheet
190
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Application Information
14.3
Thermal Behavior of Package
The figure below shows the thermal resistance (Rth_JA) of the device vs. the cooling area on the bottom of the
PCB for Ta = 85°C. Every line reflects a different PCB and thermal via design.
70
Tamb=85°C
60
50
40
30
20
10
0
100
200
300
400
500
600
Bottom Cooling area (mm2)
2s2p - 16 vias(standard)
2s0p - 25vias (standard)
2s2p - 25vias (standard)
2s2p - 16vias (35µm)
2s0p - 16vias (standard)
2s2p - 25vias (35µm)
Figure 55 Thermal Resistance (Rth_JA) vs. Cooling Area
Cross Section (JEDEC 2s2p) with Cooling Area
Cross Section (JEDEC 2s0p) with Cooling Area
70µm modelled (traces)
35µm, 90% metalization*
35µm, 90% metalization*
70µm / 5% metalization + cooling area
*: means percentual Cu metalization on each layer
PCB (top view)
PCB (bottom view)
standard solder pads
Figure 56 Board Setup
The Board setup is defined according to JESD 51-2,-5,-7.
Board: 76.2 × 114.3 × 1.5 mm3 with 2 inner copper layers (35 µm thick), with thermal via array under the
exposed pad contacting the first inner copper layer and the cooling area on the bottom layer (70 µm).
Datasheet
191
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Package Outlines
15
Package Outlines
0.9 MAX.
(0.65)
11 x 0.5 = 5.5
0.5
±0.1
7
A
±0.03
0.1
6.8
+0.03 1)
2)
37
B
36
25
24
48x
0.08
48
13
1
12
Index Marking
48x
0.1
0.4 x 45°
±0.05
Index Marking
0.23
M
A B C
(0.2)
0.05 MAX.
(5.2)
(6)
C
1) Vertical burr 0.03 max., all sides
2) These four metal areas have exposed diepad potential
PG-VQFN-48-29, -31-PO V05
Figure 57 PG-VQFN-481)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
1) Dimensions in mm
Datasheet
192
Rev. 1.5
2019-09-27
TLE9278-3BQX
Multi-CAN Power+ System Basis Chip
Revision History
16
Revision History
Revision Date
Changes
1.5 2019-09-27 Datasheet updated:
•
General
–
–
corrected typo “ISO 11989-1” to “11898-1”
changed “SBC Software Development Mode” to “SBC Development Mode”
•
Updated description of the leave procedure in SBC Development Mode (FO/TEST
pin condition)
•
•
Figure 12 and Figure 15: added dot between VS and Boost Converter
Updated Table 23
–
–
–
added P_8.3.47 and P_8.3.48 (no product change)
tightened P_8.3.18
tightened P_8.3.8 and P_8.3.9 by additional footnote
•
•
•
Corrected Bit 6 Address (Status Information Field) in Table 31
Added footnote for R2 in Table 35 (Bill of Material)
Added Figure 54
1.4
2019-01-23 Initial Release.
Datasheet
193
Rev. 1.5
2019-09-27
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
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Edition 2019-09-27
Published by
Infineon Technologies AG
81726 Munich, Germany
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest
characteristics ("Beschaffenheitsgarantie").
Infineon Technologies Office (www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
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responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
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