TLE9260QX_技术文档

System Basis Chip

TLE9260QX

Mid-Range System Basis Chip Family

Body System IC with Integrated Voltage Regulators, Power Management Functions,

HS-CAN Transceiver supporting CAN FD .

Featuring Multiple High-Side Switches and High-Voltage Wake Inputs.

Data Sheet

Rev. 1.1, 2014-09-26

Automotive Power

TLE9260QX

Table of Contents

1

2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hints for Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Hints for Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1

3.2

3.3

3.4

4

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1

4.2

4.3

4.4

5

5.1

System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Block Description of State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Device Configuration and SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

SBC Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SBC Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SBC Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SBC Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Configuration and Operation of Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Cyclic Sense in Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Supervision Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.1.1

5.1.1.1

5.1.1.2

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.2

5.2.1

5.2.1.1

5.2.1.2

5.2.2

5.2.3

5.3

6

Voltage Regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.1

6.2

6.3

7

Voltage Regulator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Short to Battery Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.1

7.2

7.2.1

7.3

8

8.1

8.2

8.2.1

8.2.2

8.2.3

8.2.4

High-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Over and Under Voltage Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Over Current Detection and Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

HSx Operation in Different SBC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Data Sheet

2

Rev. 1.1, 2014-09-26

TLE9260QX

Table of Contents

8.2.5

8.3

PWM and Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9

9.1

9.2

High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

CAN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

CAN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

CAN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

CAN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Under Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

9.2.7

9.3

10

10.1

10.2

10.2.1

10.2.2

10.2.2.1

10.2.2.2

10.3

Wake and Voltage Monitoring Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Alternate Measurement Function with WK1 and WK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

11

11.1

11.2

Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

12

Fail Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

General Purpose I/O Functionality of FO2 and FO3 as Alternate Function . . . . . . . . . . . . . . . . . . 74

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12.1

12.1.1

12.2

13

13.1

Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Watchdog Setting Check Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Watchdog during SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Watchdog Start in SBC Stop Mode due to Bus Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

VS Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Under Voltage VS and VSHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Over Voltage VSHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

VCC1 Over-/ Under Voltage and Under Voltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

VCC1 Under Voltage and Under Voltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

VCC1 Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

VCC1 Short Circuit Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

VCC2 Undervoltage and VCAN Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Individual Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

13.1.1

13.1.2

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.2.5

13.3

13.4

13.5

13.6

13.6.1

13.6.2

13.7

13.8

13.9

13.9.1

13.9.2

Data Sheet

3

Rev. 1.1, 2014-09-26

TLE9260QX

Table of Contents

13.9.3

13.10

SBC Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

SPI Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

SPI Status Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Family and Product Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.1

14.2

14.3

14.4

14.5

14.5.1

14.6

14.6.1

14.6.2

14.7

15

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

15.1

15.2

15.3

16

17

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Data Sheet

4

Rev. 1.1, 2014-09-26

Mid-Range System Basis Chip Family

TLE9260QX

1

Overview

Scalable System Basis Chip Family

•

Product family with various products for complete scalable application

coverage.

•

Dedicated Data Sheets are available for the different product variants

Complete compatibility (hardware and software) across the family

TLE9263 with 2 LIN transceivers, 3 voltage regulators

TLE9262 with 1 LIN transceiver, 3 voltage regulators

PG-VQFN-48-31

TLE9261 without LIN transceivers, 3 voltage regulators

TLE9260 without LIN transceivers, 2 voltage regulators

Product variants for 5V (TLE926xQX) and 3.3V (TLE926xQXV33) output voltage for main voltage regulator

CAN Partial Networking variants for 5V (TLE926x-3QX) and 3.3V (TLE926x-3QXV33) output voltage

Device Description

The TLE9260QX is a monolithic integrated circuit in an exposed pad VQFN-48 (7mm x 7mm) power package with

Lead Tip Inspection (LTI) feature to support Automatic Optical Inspection (AOI).

The device is designed for various CAN automotive applications as main supply for the microcontroller and as

interface for a CAN bus network.

To support these applications, the System Basis Chip (SBC) provides the main functions, such as a 5V low-

dropout voltage regulator (LDO) for e.g. a microcontroller supply, another 5V low-dropout voltage regulator with

off-board protection for e.g. sensor supply, a HS-CAN transceiver supporting CAN FD for data transmission, high-

side switches with embedded protective functions and a 16-bit Serial Peripheral Interface (SPI) to control and

monitor the device. Also implemented are a configurable timeout / window watchdog circuit with a reset feature,

three Fail Outputs and an under voltage reset feature.

The device offers low-power modes in order to minimize current consumption on applications that are connected

permanently to the battery. A wake-up from the low-power mode is possible via a message on the buses, via the

bi-level sensitive monitoring/wake-up inputs as well as via cyclic wake.

The device is designed to withstand the severe conditions of automotive applications.

Type

Package

Marking

TLE9260QX

PG-VQFN-48-31

TLE9260QX

Data Sheet

5

Rev. 1.1, 2014-09-26

TLE9260QX

Overview

Key Features

•

Very low quiescent current consumption in Stop- and Sleep Mode

Periodic Cyclic Wake in SBC Normal- and Stop Mode

Periodic Cyclic Sense in SBC Normal-, Stop- and Sleep Mode

Low-Drop Voltage Regulator 5V, 250mA

Low-Drop Voltage Regulator 5V, 100mA, protected features for off-board usage

High-Speed CAN Transceiver:

–

fully compliant to ISO11898-2 and ISO11898-5

suitable for chokeless operation up to 500kbps

supporting CAN FD communication up to 2 Mbps

•

Fully compliant to “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications”

Revision 1.3, 2012-05-04

•

Four High-Side Outputs 7Ω typ.

Dedicated supply pin for High-Side Outputs

Two General Purpose High-Voltage In- and Outputs (GPIOs) configurable as add. Fail Outputs, Wake Inputs,

Low-Side switches or High-Side switches

•

Three universal High-Voltage Wake Inputs for voltage level monitoring

Alternate High-Voltage Measurement Function, e.g. for battery voltage sensing

Configurable wake-up sources

Reset Output

Configurable timeout and window watchdog

Up to three Fail Outputs (depending on configuration)

Over temperature and short circuit protection feature

Wide supply input voltage and temperature range

Software compatible to all SBC families TLE926x and TLE927x

Green Product (RoHS compliant) & AEC Qualified

PG-VQFN-48 leadless exposed-pad power package with Lead Tip Inspection (LTI) feature to support

Automatic Optical Inspection (AOI)

Data Sheet

6

Rev. 1.1, 2014-09-26

TLE9260QX

Block Diagram

2

Block Diagram

VSHS

VS

V_S

V_CC1

HS1

HS2

High Side

HS3

HS4

FO1

FO2

V_CC2

VCC2

FO3/TEST

Fail Safe

Alternative function

for FO2/3: GPIO1/2

SDI

SDO

SPI

SBC

STATE

CLK

CSN

MACHINE

INT

Interrupt

Control

Window Watchdog

RO

RESET

GENERATOR

WK1

WK

Alternative

VCAN

function for WK 1/2:

WAKE

REGISTER

Voltage measurement

WK2

TXDCAN

RXDCAN

WK

CAN cell

CANH

CANL

WK3

WK

GND

Figure 1

Block Diagram

Data Sheet

7

Rev. 1.1, 2014-09-26

TLE9260QX

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment

VCAN 37

GND 38

CANL 39

CANH 40

n.c. 41

24 WK3

23 WK2

22 WK1

21 FO1

20 GND

19 n.c.

TLE9260

N.U. 42

GND 43

N.U. 44

n.c. 45

18 VCC2

17 VCC1

16 n.c.

PG-VQFN-48

n.c. 46

15 VS

FO2 47

14 VS

FO3/TEST 48

13 VSHS

TLE9260.vsd

Figure 2

Pin Configuration

Data Sheet

8

Rev. 1.1, 2014-09-26

TLE9260QX

Pin Configuration

3.2

Pin Definitions and Functions

1

Symbol

Function

GND

n.c.

Ground

2

not connected; internally not bonded.

3

N.U.

n.c.

Not Used; Used for internal testing purpose. Do not connect, leave open

not connected; internally not bonded.

4

5

6

7

n.c.

not connected; internally not bonded.

8

HS1

HS2

HS3

HS4

n.c

High Side Output 1; typ. 7Ω

9

High Side Output 2; typ. 7Ω

10

11

12

13

High Side Output 3; typ. 7Ω

High Side Output 4; typ. 7Ω

not connected; internally not bonded.

VSHS

Supply Voltage HS and GPIO1/2 in HS configuration; Supply voltage for High-

Side Switches modules and respective UV-/OV supervision; Connected to

battery voltage with reverse protection diode and filter against EMC; connect

to VS if separate supply is not needed

14

15

VS

Supply Voltage; Supply voltage for chip internal supply and voltage

regulators; Connected to Battery Voltage with external reverse protection

Diode and Filter against EMC

Supply Voltage; Supply voltage for chip internal supply and voltage

regulators; Connected to Battery Voltage with external reverse protection

Diode and Filter against EMC

16

17

18

19

20

21

22

n.c.

not connected; internally not bonded.

Voltage Regulator Output 1

Voltage Regulator Output 2

not connected; internally not bonded.

GND

VCC1

VCC2

n.c.

GND

FO1

WK1

Fail Output 1

Wake Input 1; Alternative function: HV-measurement function input pin

(only in combination with WK2, see Chapter 10.2.2)

23

WK2

Wake Input 2; Alternative function: HV-measurement function output pin

(only in combination with WK1, see Chapter 10.2.2)

24

25

26

27

28

29

30

WK3

N.U.

CLK

SDI

Wake Input 3

Not Used; Used for internal testing purpose. Do not connect, leave open

SPI Clock Input

SPI Data Input; into SBC (=MOSI)

SDO

CSN

SPI Data Output; out of SBC (=MISO)

SPI Chip Select Not Input

Data Sheet

9

Rev. 1.1, 2014-09-26

TLE9260QX

Pin Configuration

Symbol

Function

31

INT

Interrupt Output; used as wake-up flag for microcontroller in SBC Stop or Normal

Mode and for indicating failures. Active low.

During start-up used to set the SBC configuration. External pull-up sets config 1/3,

no external pull-up sets config 2/4.

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

RO

Reset Output

N.U.

Not Used; Used for internal testing purpose. Do not connect, leave open

N.U.

Not Used; Used for internal testing purpose. Do not connect, leave open

TXDCAN

RXDCAN

VCAN

GND

CANL

CANH

n.c.

Transmit CAN

Receive CAN

Supply Input; for internal HS-CAN cell

GND

CAN Low Bus Pin

CAN High Bus Pin

not connected; internally not bonded.

Not Used; Used for internal testing purpose. Do not connect, leave open

Ground

N.U.

GND

N.U.

Not Used; Used for internal testing purpose. Do not connect, leave open

not connected; internally not bonded.

n.c.

FO2

Fail Output 2 - Side Indicator; Side indicators 1.25Hz 50% duty cycle output;

Open drain. Active LOW.

Alternative Function: GPIO1; configurable pin as WK, or LS, or HS supplied by

VSHS (default is FO2, see also Chapter 12.1.1)

48

FO3/TEST

Fail Output 3 - Pulsed Light Output; Break/rear light 100Hz 20% duty cycle output;

Open drain. Active LOW

TEST; Connect to GND to activate SBC Software Development Mode;

Integrated pull-up resistor. Connect to VS with pull-up resistor or leave open for

normal operation.

Alternative Function: GPIO2; configurable pin as WK, or LS, or HS supplied by

VSHS (default is FO3, see also Chapter 12.1.1)

Cooling GND

Tab

Cooling Tab - Exposed Die Pad; For cooling purposes only, do not use as an

electrical ground.¹⁾

1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the SBC via the PCB. The

exposed die pad is not connected to any active part of the IC an can be left floating or it can be connected to GND

(recommended) for the best EMC performance.

Note:all VS Pins must be connected to battery potential or insert a reverse polarity diodes where required;

all GND pins as well as the Cooling Tab must be connected to one common GND potential;

Data Sheet

10

Rev. 1.1, 2014-09-26

TLE9260QX

Pin Configuration

3.3

Hints for Unused Pins

It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that they

are disabled via SPI:

•

WK1/2/3: connect to GND and disable WK inputs via SPI

HSx: leave open

CANH/L, RXDCAN, TXDCAN: leave all pins open

RO / FOx: leave open

INT: leave open

TEST: connect to GND during power-up to activate SBC Development Mode;

connect to VS or leave open for normal user mode operation

•

VCC2: leave open and keep disabled

VCAN: connect to VCC1

n.c.: not connected; internally not bonded; connect to GND

N.U.: Not Used; Used for internal testing purposes only. Do not connect, leave open, i.e. not connected to any

potential on the board. In case N.U. pins are connected on the board an open bridge has to be foreseen to

avoid external disturbances. The bridge can be shorted by a 0 Ω resistance if signal is needed.

3.4

Hints for Alternate Pin Functions

In case of alternate pin functions, selectable via SPI, it must be ensured that the correct configurations are also

selected via SPI, in case it is not done automatically. Please consult the respective chapter. In addition, following

topics shall be considered:

•

WK1..2: The pins can be either used as HV wake / voltage monitoring inputs or for a voltage measurement

function (via bit WK_MEAS). In the second case, the WK1..2 pins shall not be used / assigned for any wake

detection nor cyclic sense functionality, i.e. WK1 and WK2 must be disabled in the register WK_CTRL_2 and

the level information is to be ignored in the register WK_LVL_STAT.

FO2..3: The pins can also be configured as GPIOs in the GPIO_CTRL register. In this case, the pins shall not

be used for any fail output functionality. The default function after Power on Reset (POR) is FOx.

Data Sheet

11

Rev. 1.1, 2014-09-26

TLE9260QX

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings¹⁾

T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Voltages

Supply Voltage (VS, VSHS) VS_{x, max}

-0.3

–

28

40

V

–

P_4.1.1

P_4.1.2

Load Dump,

max. 400 ms

Voltage Regulator 1

Voltage Regulator 2

V_{CC1, max}

V_{CC2, max}

-0.3

–

5.5

28

V

–

P_4.1.3

P_4.1.4

V

_CC2= 40V for

Load Dump,

max. 400 ms;

Wake Inputs WK1..3

Fail Pin FO1

V_{WK, max}

V_{FO1, max}

-0.3

–

40

V

–

P_4.1.6

P_4.1.7

P_4.1.23

Fail Pins FO2, FO3/TEST

V_{FO2_3, max}-0.3

V_S

+ 0.3

CANH, CANL

V_{BUS, max}

-27

–

40

V

–

P_4.1.8

P_4.1.9

Logic Input Pins (CSN, CLK, V_{I, max}

-0.3

V_CC1

SDI, TXDCAN)

+ 0.3

Logic Output Pins (SDO, RO, V_{O, max}

-0.3

–

V_CC1

V

–

P_4.1.10

INT, RXDCAN)

+ 0.3

VCAN Input Voltage

High Side 1...4

V_{VCAN, max}

-0.3

–

5.5

V

–

P_4.1.11

P_4.1.12

V_{HS, max}

V_SHS

+ 0.3

Currents

2)

Wake input WK1

Wake input WK2

Temperatures

I_WK1,max

I_WK2,max

0

–

500

0

µA

P_4.1.13

P_4.1.14

-500

Junction Temperature

Storage Temperature

ESD Susceptibility

ESD Resistivity

T_j

-40

-55

–

150

°C

–

P_4.1.15

P_4.1.16

T_stg

V_ESD,11

-2

-8

–

2

8

kV

HBM³⁾

HBM⁴⁾³⁾

P_4.1.17

P_4.1.18

P_4.1.19

ESD Resistivity to GND, HSx V_ESD,12

ESD Resistivity to GND,

CANH, CANL

V_ESD,13

Data Sheet

12

Rev. 1.1, 2014-09-26

TLE9260QX

General Product Characteristics

Table 1

Absolute Maximum Ratings¹⁾(cont’d)

T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note /

Test Condition

Number

Min.

-500

-750

Typ.

Max.

500

ESD Resistivity to GND

V_ESD,21

V_ESD,22

–

V

CDM⁵⁾

P_4.1.20

P_4.1.21

ESD Resistivity Pin 1,

12,13,24,25,36,37,48 (corner

pins) to GND

750

1) Not subject to production test, specified by design.

2) Applies only if WK1 and WK2 are configured as alternative HV-measurement function

3) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kꢀ, 100 pF)

4) For ESD “GUN” Resistivity 6KV (according to IEC61000-4-2 “gun test” (150pF, 330ꢀ)), will be shown in Application

Information and test report will be provided from IBEE

5) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not

designed for continuous repetitive operation.

Data Sheet

13

Rev. 1.1, 2014-09-26

TLE9260QX

General Product Characteristics

4.2

Functional Range

Table 2

Functional Range

Parameter

Symbol

Values

Typ.

–

Unit Note /

Number

Test Condition

Min.

Max.

Supply Voltage

V_S,func

V_POR

28

V

¹⁾V_PORsee

section

P_4.2.1

Chapter 13.10

CAN Supply Voltage

SPI frequency

V_CAN,func

f_SPI

4.75

–

5.25

4

V

–

P_4.2.3

MHz seeChapter 14.7 P_4.2.4

for f_SPI,max

Junction Temperature

T_j

-40

–

150

°C

–

P_4.2.5

1) Including Power-On Reset, Over- and Under voltage Protection

Note:Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics table.

Device Behavior Outside of Specified Functional Range:

•

28V < V_S,func< 40V: Device will still be functional including the state machine; the specified electrical

characteristics might not be ensured anymore. The regulators VCC1/2/3 are working properly, however, a

thermal shutdown might occur due to high power dissipation. HSx switches might be turned OFF depending

on VSHS_OV configurations. The specified SPI communication speed is ensured; the absolute maximum

ratings are not violated, however the device is not intended for continuous operation of VS >28V. The device

operation at high junction temperatures for long periods might reduce the operating life time;

•

V_CAN< 4.75V: The undervoltage bit VCAN_UV will be set in the SPI register BUS_STAT_1 and the transmitter

will be disabled as long as the UV condition is present;

5.25V < V_CAN< 5.50V: CAN transceiver still functional. However, the communication might fail due to out-of-

spec operation;

V_POR,f< VS < 5.5V: Device will still be functional; the specified electrical characteristics might not be ensured

anymore.

–

The voltage regulators will enter the low-drop operation mode,

A VCC1_UV reset could be triggered depending on the Vrtx settings,

HSx switch behavior will depend on the respective configuration:

- HS_UV_SD_EN = ‘0’ (default): HSx will be turned OFF for VSHS < VSHS_UV and will stay OFF;

- HS_UV_SD_EN = ‘1’: HSx stays on as long as possible. An unwanted over current shut down may occur.

OC shut down bit set and the respective HSx switch will stay OFF;

–

FOx outputs will remain ON if they were enabled before VS > 5.5V,

The specified SPI communication speed is ensured.

Data Sheet

14

Rev. 1.1, 2014-09-26

TLE9260QX

General Product Characteristics

4.3

Thermal Resistance

Table 3

Thermal Resistance¹⁾

Symbol

Parameter

Values

Typ.

6

Unit Note /

Number

Test Condition

Min.

Max.

Junction to Soldering Point

Junction to Ambient

R_thJSP

R_thJA

–

K/W

Exposed Pad

2)

P_4.3.1

P_4.3.2

33

1) Not subject to production test, specified by design.

2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for 1.5W. Board: 76.2x114.3x1.5mm³ with 2

inner copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and

300mm2 cooling area on the bottom layer (70µm).

Data Sheet

15

Rev. 1.1, 2014-09-26

TLE9260QX

General Product Characteristics

4.4

Current Consumption

Table 4

Current Consumption

Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note / Test Condition Number

Min.

Max.

SBC Normal Mode

Normal Mode current

consumption

I_Normal

–

3.5

44

6.5

mA

µA

V_S= 5.5 V to 28 V;

T_j= -40 °C to +150 °C;

VCC2, CAN, HSx =

OFF

P_4.4.1

SBC Stop Mode

Stop Mode current

consumption

I_{Stop_1,25}

–

60

70

¹⁾VCC2, HSx = OFF; P_4.4.2

CAN, WKx not wake

capable;

Watchdog = OFF;

no load on VCC1;

I_PEAK_TH = ‘0’

¹⁾²⁾T_j= 85°C;

VCC2, HSx = OFF;

CAN, WKx not wake

capable;

Stop Mode current

consumption

I_{Stop_1,85}

50

µA

P_4.4.3

Watchdog = OFF;

no load on VCC1;

I_PEAK_TH = ‘0’

Stop Mode current

consumption

(high active peak threshold)

I_{Stop_2,25}

–

64

70

90

µA

¹⁾VCC2, HSx = OFF; P_4.4.35

CAN, WKx not wake

capable;

Watchdog = OFF;

no load on VCC1;

I_PEAK_TH = ‘1’

Stop Mode current

consumption

(high active peak threshold)

I_{Stop_2,85}

100

¹⁾²⁾Tj = 85°C;

P_4.4.36

VCC2, HSx = OFF;

CAN, WKx not wake

capable;

Watchdog = OFF;

no load on VCC1;

I_PEAK_TH = ‘1’

SBC Sleep Mode

Sleep Mode current

consumption

I_Sleep,25

–

15

25

35

µA

VCC2, HSx = OFF;

CAN, WKx not wake

capable

²⁾T_j= 85°C;

VCC2, HSx = OFF;

CAN, WKx not wake

capable

P_4.4.5

P_4.4.6

Sleep Mode current

consumption

I_Sleep,85

Data Sheet

16

Rev. 1.1, 2014-09-26

TLE9260QX

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note / Test Condition Number

Min.

Feature Incremental Current Consumption

Max.

Current consumption for CAN I_CAN,rec

module, recessive state

–

2

3

mA

SBC Normal/Stop

Mode; CAN Normal

Mode; VCC1

connected to VCAN;

VTXDCAN = VCC1;

no RL on CAN

²⁾SBC Normal/Stop

Mode; CAN Normal

Mode; VCC1

connected to VCAN;

VTXDCAN = GND;

no RL on CAN

²⁾SBC Normal/Stop

Mode; CAN Receive

Only Mode; VCC1

connected to VCAN;

VTXDCAN = VCC1;

no RL on CAN

P_4.4.7

P_4.4.8

P_4.4.9

Current consumption for CAN I_CAN,dom

module, dominant state

3

4.5

1.2

Current consumption for CAN I_CAN,RcvOnly

module, Receive Only Mode

0.9

Current consumption for

WK1..3 wake capability

(all wake inputs)

I_Wake,WKx,25

–

0.2

0.5

2

3

µA

³⁾⁴⁾⁵⁾SBC Sleep Mode; P_4.4.13

WK1..3 wake capable

(all WKx enabled);

CAN = OFF

Current consumption for

WK1..3 wake capability

(all wake inputs)

I_Wake,WKx,85

^2)3)4)5)SBC Sleep

Mode; T_j= 85°C;

WK1..3 wake capable;

(all WKx enabled);

CAN = OFF

P_4.4.14

Current consumption for CAN I_Wake,CAN,25

wake capability

–

4.5

5.5

6

7

µA

³⁾SBC Sleep Mode;

CAN wake capable;

WK1..3

P_4.4.17

Current consumption for CAN I_Wake,CAN,85

²⁾³⁾SBC Sleep Mode; P_4.4.18

wake capability

T_j= 85°C;

CAN wake capable;

WK1..3

VCC2 Normal Mode current I_Normal,VCC2

consumption

–

2.5

25

3.5

35

mA

µA

V_S= 5.5 V to 28 V;

T_j= -40 °C to +150 °C;

VCC2 = ON (no load)

¹⁾³⁾SBC Sleep Mode; P_4.4.19

VCC2 = ON (no load);

CAN,

P_4.4.32

Current consumption for

VCC2 in SBC Sleep Mode

I_{Sleep,VCC2,25}

WK1..3 = OFF

Data Sheet

17

Rev. 1.1, 2014-09-26

TLE9260QX

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)

Parameter

Symbol

Values

Typ.

30

Unit Note / Test Condition Number

Min.

Max.

Current consumption for

VCC2 in SBC Sleep Mode

I_{Sleep,VCC2,85}

–

40

µA

¹⁾²⁾³⁾SBC Sleep Mode; P_4.4.20

T_j= 85°C; VCC2 = ON

(no load); CAN,

WK1..3 = OFF

Current consumption for HSx I_Stop,HSx,25

in SBC Stop Mode

–

525

575

650

700

µA

³⁾⁶⁾SBC Stop Mode;

Cyclic Sense & HSx=

ON (no load);

CAN,

WK1..3 = OFF

²⁾³⁾⁶⁾SBC Stop Mode; P_4.4.34

P_4.4.33

Current consumption for HSx I_Stop,HSx,85

µA

in SBC Stop Mode

T_j= 85°C;

Cyclic Sense & HSx =

ON (no load);

CAN,

WK1..3 = OFF

Current consumption for

cyclic sense function

I_Stop,CS25

I_Stop,CS85

–

20

24

26

35

µA

³⁾⁷⁾⁸⁾SBC Stop Mode; P_4.4.23

WD = OFF

^2)3)7)8)SBC Stop Mode; P_4.4.27

T_j= 85°C;

Current consumption for

cyclic sense function

WD = OFF

Current consumption for

watchdog active in Stop

Mode

I_Stop,WD25

I_Stop,WD85

I_Stop,FOx

–

20

24

1.0

26

35

2.0

µA

mA

²⁾SBC Stop Mode;

Watchdog running

P_4.4.30

P_4.4.31

P_4.4.24

Current consumption for

watchdog active in Stop

Mode

²⁾SBC Stop Mode;

T_j= 85°C;

Watchdog running

Current consumption for

active fail outputs (FO1..3)

²⁾all SBC Modes;

T_j= 25°C; FOx = ON

(no load);

1) If the load current on VCC1 will exceed the configured VCC1 active peak threshold I_{VCC1,Ipeak1,r}or I_{VCC1,Ipeak2,r}

,

the current consumption will increase by typ. 2.9mA to ensure optimum dynamic load behavior. Same applies to VCC2..

see also Chapter 5.1.5)

•

HS Outputs can be switched ON or OFF (default = OFF) or can be controlled by PWM; HS Outputs are OFF

coming from SBC Restart Mode

•

Wake pins show the input level and can be selected to be wake capable (interrupt)

Cyclic sense can be configured with HS1...4 and Timer1 or Timer 2

Cyclic wake can be configured with Timer1 or Timer2

Watchdog is configurable

All FOx outputs are OFF by default. Coming from SBC Restart Mode FOx can be active (due to a failure event,

e.g. watchdog trigger failure, VCC1 short circuit, etc.) or inactive (no failure occurred)

In SBC Normal Mode, there is the possibility of testing the FO outputs, i.e. to verify if setting the FO pin to low will

create the intended behavior within the system. The FO output can be enabled and then disabled again by the

microcontroller by setting the FO_ON SPI bit. This feature is only intended for testing purposes.

Data Sheet

25

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

5.1.3

SBC Stop Mode

The SBC Stop Mode is the first level technique to reduce the overall current consumption by setting the voltage

regulators VCC1, VCC2 into a low-power mode. In this mode VCC1 is still active and supplying the

microcontroller, which can enter a power down mode. The VCC2 supply, CAN mode as well as the HSx outputs

can be configured to stay enabled. All kind of settings have to be done before entering SBC Stop Mode. In SBC

Stop Mode any kind of SPI WRITE commands are ignored and the SPI_FAIL bit is set, except for changing to

SBC Normal Mode, triggering a SBC Soft Reset, refreshing the watchdog as well as for reading and clearing the

SPI status registers. A wake-up event on CAN and WKx will create an interrupt on pin INT - however, no change

of the SBC mode will occur. The configuration options are listed below:

•

VCC1 is ON

VCC2 is fixed as configured in SBC Normal Mode

CAN mode is fixed as configured in SBC Normal Mode

WK pins are fixed as configured in SBC Normal Mode

HS Outputs are fixed as configured in SBC Normal Mode

Cyclic sense is fixed as configured in SBC Normal Mode

Cyclic wake is fixed as configured in SBC Normal Mode

Watchdog is fixed as configured in SBC Normal Mode

SBC Soft Reset can be triggered

FOx outputs are fixed, i.e. the state from SBC Normal Mode is maintained

An interrupt is triggered on the pin INT when SBC Stop Mode is entered and not all wake source signalization flags

from WK_STAT_1 and WK_STAT_2 were cleared.

Note:If switches are enabled during SBC Stop Mode, e.g. HSx on with or without PWM, then the SBC current

consumption will increase (see Chapter 4.4).

Note:It is not possible to switch directly from SBC Stop Mode to SBC Sleep Mode. Doing so will also set the

SPI_FAIL flag and will bring the SBC into Restart Mode.

Note:When WK1 and WK2 are configured for the alternate measurement function (WK_MEAS = 1) then the wake

inputs cannot be selected as wake input sources.

Data Sheet

26

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

5.1.4

SBC Sleep Mode

The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum

needed to react on wake-up events or for the SBC to perform autonomous actions (e.g. cyclic sense). In this mode,

VCC1 is OFF and not supplying the microcontroller anymore.The VCC2 supply as well as the HSx outputs can be

configured to stay enabled. The settings have to be done before entering SBC Sleep Mode. A wake-up event on

CAN or WKx will bring the device via SBC Restart Mode into SBC Normal Mode again and signal the wake source.

The configuration options are listed below:

•

VCC1 is OFF

VCC2 is fixed as configured in SBC Normal Mode

CAN mode changes automatically from ON or Receive Only Mode to wake capable mode or can be selected

to be OFF

•

WK pins are fixed as configured in SBC Normal Mode

HS Outputs are fixed as configured in SBC Normal Mode

Cyclic sense is fixed as configured in SBC Normal Mode

Cyclic wake is not available

Watchdog is OFF

FOx outputs are fixed, i.e. the state from SBC Normal Mode is maintained

As VCC1 is OFF during SBC Sleep Mode, no SPI communication is possible;

The Sleep Mode entry is signalled in the SPI register DEV_STAT with the bit DEV_STAT

It is not possible to switch all wake sources off in SBC Sleep Mode. Doing so will set the SPI_FAIL flag and will

bring the SBC into SBC Restart Mode.

In order to enter SBC Sleep Mode successfully, all wake source signalization flags from WK_STAT_1 and

WK_STAT_2 need to be cleared. A failure to do so will result in an immediate wake-up from SBC Sleep Mode by

going via SBC Restart to Normal Mode.

All settings must be done before entering SBC Sleep Mode.

Note:If switches are enabled during SBC Sleep mode, e.g. HSx on with or without PWM, then the SBC current

consumption will increase (see Chapter 4.4).

Note:Cyclic Sense function will not work properly anymore in case of an overcurrent, over temperature, under- or

overvoltage (in case function is selected) event because the respective HS switch will be disabled.

Note:When WK1 and WK2 are configured for the alternate measurement function (WK_MEAS = 1) then the wake

inputs cannot be selected as wake input sources.

Data Sheet

27

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

5.1.5

SBC Restart Mode

There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the

microcontroller:

•

in case of under voltage on VCC1 in SBC Normal and in SBC Stop Mode,

in case of over voltage on VCC1 if the bit VCC1_OV_RST is set and if CFGP = ‘1’,

due to 1st incorrect Watchdog triggering (only if Config1, Config3 or Config 4 is selected, otherwise SBC Fail-

Safe Mode is immediately entered),

•

In case of a wake event from SBC Sleep or SBC Fail-Safe Mode or a release of over temperature shutdown

(TSD2) out of SBC Fail-Safe Mode this transition is used to ramp up VCC1 after a wake in a defined way.

From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode, i.e the mode is left automatically by

the SBC without any microcontroller influence. The SBC MODE bits are cleared. As shown in Figure 35 the Reset

Output (RO) is pulled low when entering Restart Mode and is released at the transition to Normal Mode after the

reset delay time (t_RD1). The watchdog timer will start with a long open window starting from the moment of the rising

edge of RO and the watchdog period setting in the register WD_CTRL will be changed to the respective default

value ‘100’.

Leaving the SBC Restart Mode will not result in changing / deactivating the Fail outputs.

The behavior of the blocks is listed below:

•

All FOx outputs are activated in case of a 1st watchdog trigger failure (if Config1 or Config2 is selected) or

in case of VCC1 over voltage detection (if VCC1_OV_RST is set)

•

VCC1 is ON or ramping up

VCC2 will be disabled if it was activated before

CAN is “woken” due to a wake event or OFF depending on previous SBC and transceiver mode (see also

Chapter 9). It is wake capable when it was in CAN Normal-, Receive Only or wake capable mode before SBC

Restart Mode

•

HS Outputs will be disabled if they were activated before

RO is pulled low during SBC Restart Mode

SPI communication is ignored by the SBC, i.e. it is not interpreted

The Restart Mode entry is signalled in the SPI register DEV_STAT with the bits DEV_STAT

Table 7

Reasons for Restart - State of SPI Status Bits after Return to Normal Mode

Prev. SBC Mode

Normal

Stop

Event

DEV_STAT WD_FAIL VCC1_UV VCC1_OV VCC1_SC

1x Watchdog Failure

2x Watchdog Failure

01

10

xx

01

10

xx

x

1

x

1

x

1

x

1

x

VCC1 under voltage reset 01

VCC1 over voltage reset 01

1x Watchdog Failure

2x Watchdog Failure

01

Stop

VCC1 under voltage reset 01

VCC1 over voltage reset 01

Stop

Sleep

Wake-up event

10

01

Fail-Safe

see “Reasons for Fail Safe, Table 8”

Note:An over voltage event on VCC1 will only lead to SBC Restart Mode if the bit VCC1_OV_RST is set and if

CFGP = ‘1’ (Config 1/3).

Note:The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures.

Data Sheet

28

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

5.1.6

SBC Fail-Safe Mode

The purpose of this mode is to bring the system in a safe status after a failure condition by turning off the VCC1

supply and powering off the microcontroller. After a wake event the system is then able to restart again.

The Fail-Safe Mode is automatically reached for following events:

•

after an SBC thermal shutdown (TSD2) (see also Chapter 13.9.3),

in case of over voltage on VCC1 if the bit VCC1_OV_RST is set and if CFGP = ‘0’,

after a 1st incorrect watchdog trigger in Config2 (CFG = 1) and after a 2nd incorrect watchdog trigger in Config4

(CFG = 0) (see also Chapter 5.1.1),

•

if VCC1 is shorted to GND (see also Chapter 13.7),

After 4 consecutive VCC1 under voltage events (only if VS > V_S,UV, see Chapter 13.6).

In this case, the default wake sources (CAN, WK1...3, see also registers WK_CTRL_2, BUS_CTRL_1) are

activated, the wake events are cleared in the register WK_STAT_1, and all output drivers and all voltage

regulators are switched off. When WK1 and WK2 are configured for the alternate measurement function

(WK_MEAS = 1) then WK1 and WK2 will stay configured for the measurement function when SBC Fail-Safe Mode

is entered, i.e. they will not be activated as wake sources.

The SBC Fail-Safe Mode will be maintained until a wake event on the default wake sources occurs. To avoid any

fast toggling behavior a filter time of typ. 100ms (t_FS,min) is implemented. Wake events during this time will be

stored and will automatically lead to entering SBC Restart Mode after the filter time.

In case of an VCC1 over temperature shutdown (TSD2) the SBC Restart Mode will be reached automatically after

a filter time of typ. 1s (t_TSD2) without the need of a wake event.

Leaving the SBC Fail-Safe Mode will not result in deactivation of the Fail Output pins.

The following functions are influenced during SBC Fail-Safe Mode:

•

All FOx outputs are activated (see also Chapter 12)

VCC1 is OFF

VCC2 is OFF

CAN is wake capable

HS Outputs are OFF

WK pins are wake capable through static sense (with default 16µs filter time)

Cyclic sense and Cyclic wake is disabled

SPI communication is disabled because VCC1 is OFF

The Fail-Safe Mode activation is signalled in the SPI register DEV_STAT with the bits FAILURE and

DEV_STAT

Data Sheet

29

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

Table 8

Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode

Prev. SBC Failure Event

Mode

DEV_

STAT

TSD2

WD_

FAIL

VCC1_

UV

VCC1_

UV_FS

VCC1_

OV

VCC1_

SC

Normal

Stop

1 x Watchdog Failure 01

2 x Watchdog Failure 01

x

1

x

1

x

01

10

xx

01

10

xx

x

1

x

1

x

1

x

1

x

1

x

1

x

TSD2

01

x

VCC1 short to GND

4x VCC1 UV

x

VCC1 over voltage

1

x

1 x Watchdog Failure 01

2 x Watchdog Failure 01

Stop

x

Stop

TSD2

01

x

Stop

VCC1 short to GND

4x VCC1 UV

x

Stop

x

Stop

VCC1 over voltage

1

Note:An over voltage event on VCC1 will only lead to SBC Fail-Safe Mode if the bit VCC1_OV_RST is set and if

CFGP = ‘0’ (Config 2/4).

Note:The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures.

Note:See Chapter 13.6.1 for detailed description of the 4x VCC1 under voltage behavior.

5.1.7

SBC Development Mode

The SBC Development Mode is used during the development phase of the module. It is especially useful for

software development.

Compared to the default SBC user mode operation, this mode is a super set of the state machine. The device will

start also in SBC Init Mode and it is possible to use all the SBC Modes and functions with following differences:

•

Watchdog is stopped and does not need to be triggered. Therefore no reset is triggered due to watchdog failure

SBC Fail-Safe and SBC Restart Mode are not reached due to watchdog failure but the other reasons to enter

these modes are still valid

•

CAN and VCC2 default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON

instead of OFF

The SBC Software Development Mode is reached automatically if the FO3/TEST pin is set and kept LOW during

SBC Init Mode. The voltage level monitoring is started as soon as VS > V_POR,f. The Software Development Mode

is configured and maintained if SBC Init Mode is left by sending any SPI command while FO3/TEST is LOW. In

case the FO3/TEST level will be HIGH for longer than t_TESTduring the monitoring period then the SBC

Development Mode is not reached .

The SBC will remain in this mode for all conditions and can only be left by powering down the device

(VS < V_POR,f).

Data Sheet

30

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

5.2

Wake Features

Following wake sources are implemented in the device:

•

Static Sense: WK inputs are permanently active (see Chapter 10)

Cyclic Sense: WK inputs only active during on-time of cyclic sense period (see below)

Cyclic Wake: internal wake source controlled via internal timer (see below)

CAN wake: Wake-up via CAN message (see Chapter 9)

5.2.1

Cyclic Sense

The cyclic sense feature is intended to reduce the quiescent current of the device and the application.

In the cyclic sense configuration, one or more high-side drivers are switched on periodically controlled by

TIMER1_CTRL and TIMER2_CTRL. The respective high-side drivers supply external circuitries e.g. switches

and/or resistor arrays, which are connected to one or more wake inputs (see Figure 5). Any edge change of the

WKx input signal during the on-time of the cyclic sense period causes a wake. Depending on the SBC mode, either

the INT is pulled low (SBC Normal Mode and Stop Mode) or the SBC is woken enabling the VCC1 (after SBC

Sleep and SBC Fail-Safe Mode).

High Side

1-4

HS x

HS_CTRL

Signals

GND

Switching

Circuitry

TIMER_CTRL

Period / On-Time

INT

SBC

to uC

STATE

MACHINE

WK x

WK

1-3

WK_FLT_CTRL

Figure 5

Cyclic Sense Working Principle

Data Sheet

31

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

5.2.1.1

Configuration and Operation of Cyclic Sense

The correct sequence to configure the cyclic sense is shown in Figure 6. All the configurations have to be

performed before the on-time is set in the TIMERx_CTRL registers. The settings “OFF / LOW” and “OFF / HIGH”

define the voltage level of the respective HS driver before the start of the cyclic sense. The intention of this

selection is to avoid an unintentional wake due to a voltage level change at the start of the cyclic sense.

Cyclic Sense (=TimerX) will start as soon as the respective on-time has been selected independently from the

assignment of the HS and filter configuration. The selection of the respective timer (Config C/D see

Chapter 10.2.1) must therefore be done before starting the timer. The correct configuration sequence is as

follows:

•

Configure the initial level

Mapping of a Timer to the respective HSx outputs

Configuring the respective filter timing and WK pins

Configuring the timer period and on-time

Cyclic Sense Configuration

Assign TIMERx_ON to OFF/Low or

Timer1, Timer2

OFF/High in TIMERx_CTRL

Assign Timer to selected HS switch

in HS_CTRL_X

Enable WKx as wake source with

configured Timer in WK_FLT_CTRL

WK1, WK2, WK3 with

above selected timer

Select WKx pull-up / pull-down

configuration in WK_PUPD_CTRL

No pull-up/-down, pull-down or pull-up

selected, automatic switching

Select Timer Period and desired

Period: 10, 20, 50, 100, 200ms, 1s, 2s

On-Time: 0.1, 0.3, 1.0, 10, 20ms

On-Time in TIMERx_CTRL

Changing the settings can be done on the

fly, changes become effective at the next

on-time or period

Cyclic Sense starts / ends by

setting / clearing On-time

Figure 6

Cyclic Sense: Configuration and Sequence

Note:All configurations of period and on-time can be selected. However, recommended on-times for cyclic sense

are 0.1ms, 0.3ms and 1ms. The SPI_FAIL will be set if the on-time is longer than the period.

Data Sheet

32

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

The first sample of the WK input value (HIGH or LOW) is taken as the reference for the next cycle. A change of

the WK input value between the first and second cycle recognized during the on-time of the second cycle will

cause a wake from SBC Sleep Mode or an interrupt during SBC Normal or SBC Stop Mode.

A filter time of 16µs is implemented to avoid a parasitic wake-up due to transients or EMC disturbances. The filter

time t_FWK1is triggered right at the end of the selected on-time and a wake signal is recognized if:

•

the input level will not cross the switching threshold level of typ. 3V during the selected filter time (i.e. if the

signal will keep the HIGH or LOW level) and

•

there was an input level change between the current and previous cycle

Data Sheet

33

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

A wake event due to cyclic sense in SBC Mode will set the respective bit WK1_WU, WK2_WU, or WK3_WU.

During Cyclic Sense, WK_LVL_STAT is updated only with the sampled voltage levels of the WKx pins in SBC

Normal or SBC Stop Mode.

The functionality of the sampling and different scenarios are depicted in Figure 7 to Figure 9. The behavior in SBC

Stop and SBC Sleep Mode is identical except that in Stop Mode INT will be triggered to signal a change of WK

input levels and in SBC Sleep Mode, VCC1 will power-up instead.

HS on

Cyclic Sense

Periode

HS switch

Filter time

t_FWK1

Filter time

t_FWK1

On Time

t

1st sample taken

as reference

Wake detection possible

on 2nd sample

Figure 7

Wake Input Timing

HS

Filter time

High

Low

Switch

open

closed

WK

High

Low

n-1

Learning

Cycle

WK_n-1= High

n

n+1

n+2

WK_n+1= Low

WK_n= WK_n+1

ꢁ

WK_n+2= High

WK_n+2≠WK_{n+ 1}

ꢁwake event

WK_n= Low

WK_n≠WK_n-1

ꢁwake event

no wake

INT

High

Low

INT &

WK Bit Set

Figure 8

Cyclic Sense Example in SBC Stop Mode, HSx starts “OFF”/LOW, GND based WKx input

Data Sheet

34

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

HS

Filter time

High

Low

Spike

Switch

open

closed

WK

High

Low

n-1

n

n+1

n+2

WK = WK_n+1= Low

n

(but ignored because

change during filter time )

WK_n= WK_n+1

WK_n+2= High

WK_n+2≠WK_{n+ 1}

ꢁwake event

Learning

Cycle

WK_n-1= Low

WK_n= Low

WK_n= WK_n-1

ꢁno wake event

VCC1

ꢁ

^{no wak}T^er^ea^venⁿs^tition to:

High

SBC Sleep Mode

SBC Normal Mode

INT &

WK Bit Set

Low

Start of

Cyclic Sense

Figure 9

Cyclic Sense Example in SBC Sleep Mode, HSx starts “OFF”/HIGH,

GND based WKx input

The cyclic sense function will not work properly anymore in case of following conditions:

•

in case SBC Fail-Safe Mode is entered: The respective HS Switch will be disabled and the respective wake

pin will be changed to static sensing

•

In SBC Normal, Stop, or Sleep Mode in case of an overcurrent, overtemperature, under- or overvoltage (in

case function is selected) event: the respective HS switch will be disabled

Note:The internal timers for cyclic sense are not disabled automatically in case the HS switch is turned off due to

above mentioned failures.This must be considered to avoid loss of wake events.

5.2.1.2

Cyclic Sense in Low Power Mode

If cyclic sense is intended for SBC Stop or SBC Sleep Mode mode, it is necessary to activate the cyclic sense in

SBC Normal Mode before going to the low power mode. A wake event due to cyclic sense will set the respective

bit WK1_WU, WK2_WU or WK3_WU. In Stop Mode the wake event will trigger an interrupt, in Sleep Mode the

wake event will send the device via Restart Mode to Normal Mode. Before returning to SBC Sleep Mode, the wake

status register WK_STAT_1 and WK_STAT_2 needs to be cleared. Trying to go to SBC Sleep mode with

uncleared wake flags, such as WKx_WU the SBC will directly wake-up from Sleep Mode by going via Restart

Mode to Normal Mode, a reset is issued. The WKx_WU bit is seen as source for the wake. This is implemented

in order not to loose an wake event during the transition.

Data Sheet

35

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

5.2.2

Cyclic Wake

The cyclic wake feature is intended to reduce the quiescent current of the device and application.

For the cyclic wake feature one or both timers are configured as internal wake-up source and will periodically

trigger an interrupt in SBC Normal and SBC Stop Mode.

The correct sequence to configure the cyclic wake is shown in Figure 10. The sequence is as follows:

•

First, disable the timers to ensure that there is not unintentional interrupt when activating cyclic wake,

Enable Timer1 and/or Timer2 as a wake-up source in the register WK_CTRL_1,

Configure the respective period Timer1 and/or Timer2. Also an on-time (any value) must be selected to start

the cyclic wake even if the value is ignored.

Cyclic Wake Configuration

Disable Timer1 and/or Timer2 as a

To avoid unintentional interrupts

wake source in WK_CTRL_1

Periods : 10, 20, 50, 100, 200ms, 1s, 2s

On-times: any

(OFF/LOW & OFF/HIGH are not allowed)

Select Timer Period and any

On-Time in TIMERX_CTRL

No interrupt will be generated ,

if the timer is not enabled as a wake source

Select Timer1 and/or Timer2 as a

wake source in WK_CTRL_1

Cyclic Wake starts / ends by

setting / clearing On-time

INT is pulled low at every rising edge

of On-time except first one

Figure 10 Cyclic Wake: Configuration and Sequence

As in cyclic sense, the cyclic wake function will start as soon as the on-time is configured. An interrupt is generated

for every start of the on time except for the very first time when the timer is started

Data Sheet

36

Rev. 1.1, 2014-09-26

TLE9260QX

System Features

5.2.3

Internal Timer

The integrated Timer1 and Timer2 are typically used to wake up the microcontroller periodically (cyclic wake) or

to perform cyclic sense on the wake inputs. Therefore, the timers can be mapped to the dedicated HS switches

by SPI (via HS_CTRL1...2).

Following periods and on-times can be selected via the register TIMER1_CTRL and TIMER2_CTRL respectively:

•

Period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s

On time: 0.1ms / 0.3ms / 1.0ms / 10ms / 20ms / OFF at HIGH or LOW

5.3

Supervision Features

The device offers various supervision features to support functional safety requirements. Please see Chapter 13

for more information.

Data Sheet

37

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 1

6

Voltage Regulator 1

6.1

Block Description

VS

VCC1

Vref

1

Overtemperature

Shutdown

State

Machine

Bandgap

Reference

INH

GND

Figure 11 Module Block Diagram

Functional Features

•

5V low-drop voltage regulator

Under voltage monitoring with adjustable reset level, VCC1 prewarning and VCC1 short circuit detection

(V_RT1/2/3/4, V_PW,f). Please refer to Chapter 13.6 and Chapter 13.7 for more information.

•

Short circuit detection and switch off with under voltage fail threshold, device enters SBC Fail-Safe Mode

≥470nF ceramic capacitor at voltage output for stability, with ESR < 1ꢀ @ f = 10 kHz, to achieve the voltage

regulator control loop stability based on the safe phase margin (bode diagram).

•

Output current capability up to I_VCC1,lim.

Data Sheet

38

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 1

6.2

Functional Description

The Voltage Regulator 1 (=VCC1) is “ON” in SBC Normal and SBC Stop Mode and is disabled in SBC Sleep and

in SBC Fail-Safe Mode. The regulator can provide an output current up to I_VCC1,lim

.

For low-quiescent current reasons, the output voltage tolerance is decreased in SBC Stop Mode because only a

low-power mode regulator with a lower accuracy (V_CC1,out41) will be active for small loads. If the load current on

VCC1 exceeds the selected threshold (I_{VCC1,Ipeak1,r}or I_{VCC1,Ipeak2,r}) then the high-power mode regulator will be also

activated to support an optimum dynamic load behavior. The current consumption will then increase by typ. 2.9mA.

If the load current on VCC1 falls below the selected threshold (I_{VCC1,Ipeak1,f}or I_{VCC1,Ipeak2,f}), then the low-quiescent

current mode is resumed again by disabling the high-power mode regulator.

Both regulators (low-power mode and high-power mode) are active in SBC Normal Mode.

Two different active peak thresholds can be selected via SPI:

•

I_PEAK_TH = ‘0’(default): the lower VCC1 active peak threshold 1 is selected with lowest quiescent current

consumption in SBC Stop Mode (I_{Stop_1,25}, I_{Stop_1,85});

•

I_PEAK_TH = ‘1’: the higher VCC1 active peak threshold 2 is selected with an increased quiescent current

consumption in SBC Stop Mode (I_{Stop_2,25}, I_{Stop_2,85});

Data Sheet

39

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 1

6.3

Electrical Characteristics

Table 9

Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note / Test Condition Number

Min. Typ. Max.

Output Voltage including line

and Load regulation

V_CC1,out1

4.9

5.0

5.1

V

¹⁾SBC Normal Mode;

10µA < I_VCC1< 250mA

6V < V_S< 28V

P_6.3.1

Output Voltage including line

and Load regulation

V_CC1,out2

V_CC1,out3

4.9

5.0

–

5.1

V

¹⁾SBC Normal Mode;

10µA < I_VCC1< 150mA

¹⁾²⁾SBC Normal Mode; P_6.3.12

20mA < IVCC1 < 90mA

8V < VS < 18V

P_6.3.7

Output Voltage including line

and Load regulation

4.97

5.07

25°C < Tj < 125°C

Output Voltage including line

and Load regulation

V_CC1,out414.9

V_CC1,out424.9

5.05 5.2

V

SBC Stop Mode;

1mA < I_VCC1< I_VCC1,Ipeak

P_6.3.2

P_6.3.20

P_6.3.3

P_6.3.4

P_6.3.13

Output Voltage including line

and Load regulation

5.05 5.25

V

SBC Stop Mode;

10µA < I_VCC1< 1mA

Output Drop

V_CC1,d1

V_CC1,d2

–

500

3.5

mV

mA

I

_VCC1= 50mA

V_S=3V

I_VCC1= 150mA

Output Drop

–

V_S=5V

²⁾I_CC1rising;

V_S= 13.5V

-40°C < T_j< 150°C;

I_PEAK_TH = ‘0’

VCC1 Active Peak Threshold 1 I_{VCC1,Ipeak1,r}

(Transition threshold between

low-power and high-power

mode regulator)

1.9

VCC1 Active Peak Threshold 1 I_{VCC1,Ipeak1,f}0.5

(Transition threshold between

high-power and low-power

1.3

4.3

3.4

–

mA

²⁾I_CC1falling;

V_S= 13.5V

-40°C < T_j< 150°C;

I_PEAK_TH = ‘0’

²⁾I_CC1rising;

V_S= 13.5V

-40°C < T_j< 150°C;

I_PEAK_TH = ‘1’

²⁾I_CC1falling;

V_S= 13.5V

-40°C < T_j< 150°C;

I_PEAK_TH = ‘1’

P_6.3.17

P_6.3.18

P_6.3.19

P_6.3.6

mode regulator)

VCC1 Active Peak Threshold 2 I_{VCC1,Ipeak2,r}

(Transition threshold between

low-power and high-power

mode regulator)

–

7.0

–

VCC1 Active Peak Threshold 2 I_{VCC1,Ipeak2,f}1.7

(Transition threshold between

high-power and low-power

mode regulator)

Over Current Limitation

I_VCC1,lim

250

1200²⁾mA

current flowing out of

pin, V_CC1= 0V

1) In SBC Stop Mode, the specified output voltage tolerance applies when I_VCC1has exceeded the selected active peak

threshold (I_{VCC1,Ipeak1,r}or I_{VCC1,Ipeak2,r}) but with increased current consumption.

2) Not subject to production test, specified by design.

Data Sheet

40

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 1

Figure 12 Typical on-resistance of VCC1 pass device during low drop operation for I_CC1= 100mA

Data Sheet

41

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 1

Figure 13 On-resistance range of VCC1 pass device during low drop operation for I_CC1= 150mA

Data Sheet

42

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 2

7

Voltage Regulator 2

7.1

Block Description

VS

VCC2

Vref

1

Overtemperature

Shutdown

State

Machine

Bandgap

Reference

INH

GND

Figure 14 Module Block Diagram

Functional Features

•

5 V low-drop voltage regulator

Protected against short to battery voltage, e.g. for off-board sensor supply

Can also be used for CAN supply

VCC2 under voltage monitoring. Please refer to Chapter 13.8 for more information

Can be active in SBC Normal, SBC Stop, and SBC Sleep Mode (not SBC Fail-Safe Mode)

VCC2 switch off after entering SBC Restart Mode. Switch off is latched, LDO must be enabled via SPI after

shutdown.

•

Over temperature protection

≥ 470nF ceramic capacitor at output voltage for stability, with ESR < 1ꢀ @ f = 10 kHz, to achieve the voltage

regulator control loop stability based on the safe phase margin (bode diagram).

•

Output current capability up to I_VCC2,lim.

Data Sheet

43

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 2

7.2

Functional Description

In SBC Normal Mode VCC2 can be switched on or off via SPI.

For SBC Stop- or Sleep Mode, the VCC2 has to be switched on or off before entering the respective SBC mode.

The regulator can provide an output current up to I_VCC2,lim

.

For low-quiescent current reasons, the output voltage tolerance is decreased in SBC Stop Mode because only a

low-power mode regulator with a lower accuracy (V_CC2,out5) will be active for small loads. If the load current on

VCC2 exceeds I_VCC2> I_VCC2,Ipeak,rthen the high-power mode regulator will also be enabled to support an optimum

dynamic load behavior. The current consumption will then increase by typ. 2.9mA.

If the load current on VCC2 falls below the threshold (I_VCC2< I_VCC2,Ipeak,f), then the low-quiescent current mode is

resumed again by disabling the high-power mode regulator.

Both regulators are active in SBC Normal Mode.

Note:If the VCC2 output voltage is supplying external off-board loads, the application must consider the series

resonance circuit built by cable inductance and decoupling capacitor at the load. Sufficient damping must be

provided.

7.2.1

Short to Battery Protection

The output stage is protected for short to VBAT.

Data Sheet

44

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 2

7.3

Electrical Characteristics

Table 10

Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note / Test Condition Number

Min. Typ. Max.

Output Voltage including line

and Load regulation

(SBC Normal Mode)

V_CC2,out1

4.9

5.0

5.1

V

¹⁾SBC Normal Mode;

10µA < I_VCC2< 100mA

6.5V < V_S< 28V

P_7.3.1

Output Voltage including line

and Load regulation

(SBC Normal Mode)

V_CC2,out2

4.9

5.0

5.1

V

¹⁾SBC Normal Mode;

10µA < IVCC2 < 80mA

6V < VS < 28V

P_7.3.16

Output Voltage including line

and Load regulation

(SBC Normal Mode)

V_CC2,out3

4.9

5.0

–

5.1

V

¹⁾SBC Normal Mode;

10µA < I_VCC2< 40mA

P_7.3.2

Output Voltage including line

and Load regulation

(SBC Normal Mode)

V_CC2,out4

4.97

5.07

²⁾SBC Normal Mode;

10µA < I_VCC2< 5mA

8V < V_S< 18V

P_7.3.14

25°C < T_j< 125°C

Output Voltage including line

and Load regulation

(SBC Stop/Sleep Mode)

V_CC2,out5

V_CC2,out6

V_CC2,d1

4.9

5.05 5.2

V

Stop, Sleep Mode;

1mA < I_VCC2< I_VCC2,Ipeak

P_7.3.3

Output Voltage including line

and Load regulation

(SBC Stop/Sleep Mode)

5.05 5.25

Stop, Sleep Mode;

10µA < I_VCC2< 1mA

P_7.3.18

Output Drop

–

500

3.5

mV

mA

I

_VCC2= 30mA

P_7.3.4

V_S= 5V

²⁾I_CC2rising;

V_S= 13.5V

-40°C < T_j< 150°C

VCC2 Active Peak Threshold I_VCC2,Ipeak,r

(Transition threshold between

low-power and high-power

mode regulator)

1.9

P_7.3.15

VCC2 Active Peak Threshold I_VCC2,Ipeak,f0.5

(Transition threshold between

high-power and low-power

1.3

–

mA

²⁾I_CC2falling;

V_S= 13.5V

-40°C < T_j< 150°C

P_7.3.17

P_7.3.5

mode regulator)

Over Current limitation

I_VCC2,lim

100

750²⁾mA

current flowing out of

pin, V_CC2= 0V

1) In SBC Stop Mode, the specified output voltage tolerance applies when I_VCC2has exceeded the selected active peak

threshold (I_VCC2,Ipeak,r) but with increased current consumption.

2) Not subject to production test, specified by design.

Data Sheet

45

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 2

Figure 15 Typical on-resistance of VCC2 pass device during low drop operation for I_CC2= 30mA

Data Sheet

46

Rev. 1.1, 2014-09-26

TLE9260QX

Voltage Regulator 2

Figure 16 On-resistance range of VCC2 pass device during low drop operation for I_CC2= 50mA

Data Sheet

47

Rev. 1.1, 2014-09-26

TLE9260QX

High-Side Switch

8

High-Side Switch

8.1

Block Description

HSx

VSHS

HS Gate Control

Overcurrent Detection

Open Load (On)

Figure 17 High-Side Module Block Diagram

Features

•

Dedicated supply pin VSHS for high-side outputs

Over voltage and under voltage switch off - configurable via SPI

Overcurrent detection and switch off

Open load detection in ON-state

PWM capability with internal timer configurable via SPI

Switch recovery after removal of OV or UV condition configurable via SPI

8.2

Functional Description

The High-Side switches can be used for control of LEDs, as supply for the wake inputs and for other loads. The

High-Side outputs can be controlled either directly via SPI by (HS_CTRL1, HS_CTRL2), by the integrated timers

or by the integrated PWM generators.

The high-side outputs are supplied by a dedicated supply pin VSHS (different to VS). The topology supports

improved cranking condition behavior.

The configuration of the High-Side (Permanent On, PWM, cyclic sense, etc.) drivers must be done in SBC Normal

Mode. The configuration is taken over in SBC Stop- or SBC Sleep Mode and cannot be modified. When entering

SBC Restart Mode or SBC Fail-Safe Mode the HSx outputs are disabled.

Data Sheet

48

Rev. 1.1, 2014-09-26

TLE9260QX

High-Side Switch

8.2.1

Over and Under Voltage Switch Off

All HS drivers in on-state are switched off in case of over voltage on VSHS (V_SHS,OVD). If the voltage drops below

the over voltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit

HS_OV_SD_EN.

The HS drivers are switched off in case of under voltage on VSHS (V_SHS,UVD). If the voltage rises above the under

voltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit

HS_UV_SD_EN.

So after release of under voltage or over voltage condition the HS switch goes back to programmed state in which

it was configured via SPI. This behavior is only valid if the bit HS_OV_UV_REC is set to ‘1’. Otherwise the switches

will stay off and the respective SPI control bits are cleared are cleared.

The over voltage and under voltage is signaled in the bits VSHS_OV and VSHS_UV, no other error bits are set.

8.2.2

Over Current Detection and Switch Off

If the load current exceeds the over current shutdown threshold for a time longer then the over current shutdown

filter time the output is switched off.

The over current condition and the switch off is signaled with the respective HSx_OC_OT bit in the register

HS_OC_OT_STAT. The HSx configuration is then reset to 000 by the SBC. To activate the High-Side again the

HSx configuration has to be set to ON (001) or be programmed to a timer function. It is recommended to clear the

over current bit before activation the High-Side switch, as the bits are not cleared automatically by the SBC.

8.2.3

Open Load Detection

Open load detection on the High-Side outputs is done during on state of the output. If the current in the activated

output falls below then Open Load Detection current, the open load is detected and signaled via the respective bit

HS1_OL, HS2_OL, HS3_OL, or HS4_OL in the register HS_OL_STAT. The High-Side output stays activated. If

the open load condition disappears the Open Load bit in the SPI can be cleared. The bits are not cleared

automatically by the SBC.

8.2.4

HSx Operation in Different SBC Modes

•

During SBC Stop and SBC Sleep Mode the HSx outputs can be used for the cyclic sense feature. The open-

load detection, over current shut down as well as over voltage and under voltage shutdown are available. The

over current shutdown protection feature may influence the wake-up behavior¹⁾.

•

the HSx output can also be enabled for SBC Stop and SBC Sleep Mode as well as controlled by the PWMx

generator. The HSx outputs must be configured in SBC Normal Mode before entering a low-power mode.

The HSx outputs are switched off during SBC Restart or SBC Fail-Safe Mode. They can be enabled via SPI if

the failure condition is removed.

1) For the wake feature, the forced over current shut down case must be considered in the user software for all SBC Modes,

i.e. due to disabled HSx switches a level change might not be detected anymore at WKx pins.

Data Sheet

49

Rev. 1.1, 2014-09-26

TLE9260QX

High-Side Switch

8.2.5

PWM and Timer Function

Two 8-bit PWM generators are dedicated to generate a PWM signal on the HS outputs, e.g. for brightness

adjustment or compensation of supply voltage fluctuation. The PWM generators are mapped to the dedicated HS

outputs, and the duty cycle can be independently configured with a 8bit resolution via SPI (PWM1_CTRL,

PWM2_CTRL). Two different frequencies (200Hz, 400Hz) can be selected independently for every PWM

generator in the register PWM_FREQ_CTRL.

PWM Assignment and Configuration:

•

Configure duty cycle and frequency for respective PWM generator in PWM1_CTRL/PWM2_CTRL and

PWM_FREQ_CTRL

•

Assign PWM generator to respective HS switch(es) in HSx_CTRL

The PWM generation will start right after the HSx is assigned to the PWM generator (HS_CTRL1, HS_CTRL2)

Assignment options of HS1... HS4

•

Timer 1

Timer 2

PWM 1

PWM 2

Note:The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g.

the PWM setting ‘0000 0001’ could not be realized.

In addition, the minimum PWM setting for reliable detection of over-current and open-load measurement is

4 digits for a period of 400Hz and 2 digits for a period of 200Hz

Data Sheet

50

Rev. 1.1, 2014-09-26

TLE9260QX

High-Side Switch

8.3

Electrical Characteristics

Table 11

Target Specifications

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Output HS1, HS2, HS3, HS4

Static Drain-Source ON

Resistance HS1...HS4

R_ON,HS25

R_ON,HS150

I_leak,HS

–

7

–

ꢀ

I_ds= 60mA,

T_j< 25°C

P_9.3.1

P_9.3.2

P_9.3.11

Static Drain-Source ON

Resistance HS1...HS4

11.5

–

16

2

ꢀ

I_ds= 60mA,

T_j< 150°C

¹⁾0 V < VHSx

Leakage Current HSx / per

channel

µA

< VSHS;

Tj < 85°C

Output Slew Rate (rising)

Output Slew Rate (falling)

Switch-on time HSx

SR_raise,HS

SR_fall,HS

t_ON,HS

0.8

-2.5

3

–

2.5

-0.8

30

V/µs ¹⁾20 to 80%

P_9.3.3

P_9.3.4

P_9.3.5

V_SHS= 6 to 18V

R_L= 220ꢀ

V/µs ¹⁾80 to 20%

V_SHS= 6 to 18V

R_L= 220ꢀ

µs

CSN = HIGH to

0.8*VSHS;

R_L= 220ꢀ;

V_SHS= 6 to 18V

Switch-off time HSx

t_OFF,HS

3

–

30

µs

CSN = HIGH to

0.2*VSHS;

P_9.3.6

R_L= 220ꢀ;

V_SHS= 6 to 18V

Short Circuit Shutdown

Current

I_SD,HS

150

245

300

mA

V

_SHS= 6 to 20V, P_9.3.7

hysteresis

included

2) 3)

Short Circuit Shutdown Filter t_SD,HS

Time

16

–

µs

,

P_9.3.8

P_9.3.9

P_9.3.14

P_9.3.10

Open Load Detection Current I_OL,HS

0.4

–

3

–

mA

µs

hysteresis

included

1)

Open Load Detection

hysteresis

I_OL,HS,hys

t_OL,HS

0.45

64

2) 3)

Open Load Detection Filter

Time

–

,

1) Not subject to production test, specified by design.

2) Not subject to production test, tolerance defined by internal oscillator tolerance.

3) The minimum PWM setting for reliable detection of over current and open load measurement is 5 digits for a period of

200Hz and 3 digits for a period of 150Hz.

Data Sheet

51

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

9

High Speed CAN Transceiver

9.1

Block Description

VCAN

V_CC1

SPI Mode

Control

R_TXD

Driver

CANH

Output

TXDCAN

Stage

Temp.-

Protection

+

CANL

timeout

To SPI diagnostic

VCAN

V_BIAS= 2.5V

V_CC1

RXDCAN

MUX

Receiver

Vs

Wake

Receiver

Figure 18 Functional Block Diagram

9.2

Functional Description

The Controller Area Network (CAN) transceiver part of the SBC provides high-speed (HS) differential mode data

transmission (up to 2 Mbaud) and reception in automotive and industrial applications. It works as an interface

between the CAN protocol controller and the physical bus lines compatible to ISO/DIS 11898-2, 11898-5 and SAE

J2284.

The CAN transceiver offers low power modes to reduce current consumption. This supports networks with partially

powered down nodes. To support software diagnostic functions, a CAN Receive-only Mode is implemented.

It is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks,

clamp15/30 applications).

A wake-up from the CAN wake capable mode is possible via a message on the bus. Thus, the microcontroller can

be powered down or idled and will be woken up by the CAN bus activities.

The CAN transceiver is designed to withstand the severe conditions of automotive applications and to support

12 V applications.

The different transceiver modes can be controlled via the SPI CAN bits.

Data Sheet

52

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

Figure 19 shows the possible transceiver mode transitions when changing the SBC mode.

SBC Mode

CAN Transceiver Mode

SBC Stop Mode

Receive Only Wake Capable Normal Mode

OFF

SBC Normal Mode

SBC Sleep Mode

SBC Restart Mode

SBC Fail-Safe Mode

Receive Only Wake Capable Normal Mode

Wake Capable

OFF

Woken¹

Wake Capable

¹after a wake event on CAN Bus

Behavior after SBC Restart Mode - not coming from SBC Sleep Mode due to a wake up of the respective transceive:r

If the transceivers had been configured to Normal Mode, or Receive Only Mode, then the mode will be changed to Wake

Capable. If it was Wake Capable, then it will remainWake Capable. If it had been OFF before SBC Restart Mode, then it

will remain OFF.

Behavior in SBC Development Mode:

CAN default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF.

Figure 19 CAN Mode Control Diagram

CAN FD Support

CAN FD stands for ‘CAN with Flexible Data Rate’. It is based on the well established CAN protocol as specified in

ISO 11898-1. CAN FD still uses the CAN bus arbitration method. The benefit is that the bit rate can be increased

by switching to a shorter bit time at the end of the arbitration process and then to return to the longer bit time at

the CRC delimiter, before the receivers transmit their acknowledge bits. See also Figure 20.

In addition, the effective data rate is increased by allowing longer data fields. CAN FD allows the transmission of

up to 64 data bytes compared to the 8 data bytes from the standard CAN.

Standard CAN

message

Data phase

(Byte 0 – Byte 7)

CAN Header

CAN Footer

Example:

- 11bit identifier + 8Byte data

CAN FD with

reduced bit time

Data phase

(Byte 0 – Byte 7)

CAN Footer

- Arbitration Phase

- Data Phase

500kbps

2Mbps

ꢂaverage bit rate

1.14Mbps

Figure 20 Bite Rate Increase with CAN FD vs. Standard CAN

Not only the physical layer must support CAN FD but also the CAN controller. In case the CAN controller is not

able to support CAN FD then the respective CAN node must at least tolerate CAN FD communication. This CAN

FD tolerant mode is realized in the physical layer in combination with CAN Partial Networking. The TLE926x-3QX

variants of this family also support the CAN FD tolerant mode.

Data Sheet

53

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

9.2.1

CAN OFF Mode

The CAN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is intended

to completely stop CAN activities or when CAN communication is not needed. The CANH/L bus interface acts as

a high impedance input with a very small leakage current. In CAN OFF Mode, a wake-up event on the bus will be

ignored.

9.2.2

CAN Normal Mode

The CAN Transceiver is enabled via SPI in SBC Normal Mode. CAN Normal Mode is designed for normal data

transmission/reception within the HS-CAN network. The Mode is available in SBC Normal Mode and in SBC Stop

Mode. The bus biasing is set to VCAN/2.

Transmission

The signal from the microcontroller is applied to the TXDCAN input of the SBC. The bus driver switches the

CANH/L output stages to transfer this input signal to the CAN bus lines.

Enabling sequence

The CAN transceiver requires an enabling time t_CAN,ENbefore a message can be sent on the bus. This means that

the TXDCAN signal can only be pulled LOW after the enabling time. If this is not ensured, then the TXDCAN needs

to be set back to HIGH (=recessive) until the enabling time is completed.

Only the next dominant bit will be transmitted on the bus.

Figure 21 shows different scenarios and explanations for CAN enabling.

V

TXDCAN

t

CAN

Mode

t _CAN,EN

t_CAN,EN

t _CAN,EN

CAN

NORMAL

CAN

OFF

t

V

CANDIFF

Dominant

Recessive

recessive TXD level

required bevor start of

transmission

Correct sequence ,

Bus is enabled after t_CAN,

t_CAN,_ENnot ensured , no

transmission on bus

t_CAN,not ensured ,

no transmission on bus

recessive TXD

level required

EN

Figure 21 CAN Transceiver Enabling Sequence

Reduced Electromagnetic Emission

To reduce electromagnetic emissions (EME), the bus driver controls CANH/L slopes symmetrically.

Reception

Analog CAN bus signals are converted into digital signals at RXD via the differential input receiver.

Data Sheet

54

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

9.2.3

CAN Receive Only Mode

In CAN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still operational. This mode

is accessible by an SPI command in Normal Mode and in Stop Mode. The bus biasing is set to VCAN/2.

9.2.4

CAN Wake Capable Mode

This mode can be used in SBC Stop, Sleep, Restart and Normal Mode and it is used to monitor bus activities.

It is automatically accessed in SBC Fail-Safe Mode. Both bus pins CANH/L are connected to GND via the input

resistors.

A wake-up signal on the bus results in a change of behavior of the SBC, as described in Table 12. The pins

CANH/L are terminated to typ. 2.5V through the input resistors. As a wake-up signalization to the microcontroller,

the RXD_CAN pin is set LOW and will stay LOW until the CAN transceiver is changed to any other mode. After a

wake-up event, the transceiver can be switched to CAN Normal Mode for communication via SPI.

As shown in Figure 22, a wake-up pattern is signaled on the bus by two consecutive dominant bus levels for at

least t_Wake1(filter time t > t_Wake1), each separated by a recessive bus level of less than t_Wake2

.

Entering low-power mode,

when selective wake-up

function is disabled

or not supported

Bus recessive > tWAKE1

Ini

Wait

Bias off

Bus dominant > tWAKE1

optional:

tWAKE2 expired

1

Bias off

Bus recessive > t^WAKE1

optional:

tWAKE2 expired

2

Bias off

Bus dominant > tWAKE1

Silence expired AND

t

Entering CAN Normal

or CAN Recive Only

Device in low-power mode

3

Bias on

Bus dominant > tWAKE1

Bus recessive > tWAKE1

tSilence expired AND

device in low-power mode

4

Bias on

Figure 22 WUP detection following the definition in ISO 11898-5

Data Sheet

55

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

Rearming the Transceiver for Wake Capability

After a BUS wake-up event, the transceiver is woken. However, the CAN transceiver mode bits will still show wake

capable (=‘01’) so that the RXD signal will be pulled low. There are two possibilities how the CAN transceiver’s

wake capable mode is enabled again after a wake event:

•

The CAN transceiver mode must be toggled, i.e. switched from Wake Capable Mode to CAN Normal Mode,

CAN Receive Only Mode or CAN Off, before switching to CAN Wake Capable Mode again.

•

Rearming is done automatically when the SBC is changed to SBC Stop, SBC Sleep, or SBC Fail-Safe Mode

to ensure wake-up capability.

Note:It is not necessary to clear the CAN wake-up bit CAN_WU to become wake capable again. It is sufficient to

toggle the CAN mode.

Note:The CAN module is supplied by an internal voltage when in CAN Wake Capable Mode, i.e. the module must

not be supplied through the VCAN pin during this time. Before changing the CAN Mode to Normal Mode, the

supply of VCAN has to be activated first.

Wake-Up in SBC Stop and Normal Mode

In SBC Stop Mode, if a wake-up is detected, it is always signaled by the INT output and in the WK_STAT_1 SPI

register. It is also signaled by RXDCAN pulled to low. The same applies for the SBC Normal Mode. The

microcontroller should set the device from SBC Stop Mode to SBC Normal Mode, there is no automatic transition

to Normal Mode.

For functional safety reasons, the watchdog will be automatically enabled in SBC Stop Mode after a Bus wake

event in case it was disabled before (if bit WD_EN_ WK_BUS was configured to HIGH before).

Wake-Up in SBC Sleep Mode

Wake-up is possible via a CAN message (filter time t > t_Wake1). The wake-up automatically transfers the SBC into

the SBC Restart Mode and from there to Normal Mode the corresponding RXD pin in set to LOW. The

microcontroller is able to detect the low signal on RXD and to read the wake source out of the WK_STAT_1

register via SPI. No interrupt is generated when coming out of Sleep Mode. The microcontroller can now for

example switch the CAN transceiver into CAN Normal Mode via SPI to start communication.

Table 12

Action due to CAN Bus Wake-Up

SBC Mode after Wake

SBC Mode

VCC1

INT

RXD

LOW

Normal Mode

Stop Mode

Normal Mode

Stop Mode

ON

LOW

HIGH

ON

Sleep Mode

Restart Mode

Fail-Safe Mode

Restart Mode

Ramping Up

ON

Ramping up

Data Sheet

56

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

9.2.5

TXD Time-out Feature

If the TXD signal is dominant for a time t > t_{TXD_CAN_TO}, in CAN Normal Mode, the TXD time-out function deactivates

the transmission of the signal at the bus. This is implemented to prevent the bus from being blocked permanently

due to an error. The transmitter is disabled and the transceiver is switched to Receive Only Mode. The failure is

stored in the SPI flag CAN_FAIL. The CAN transmitter stage is activated again after the dominant time-out

condition is removed and the transceiver is automatically switched back to CAN Normal Mode.The transceiver

configuration stays unchanged.

9.2.6

Bus Dominant Clamping

If the HS CAN bus signal is dominant for a time t > t_{BUS_CAN_TO}, regardless of the CAN transceiver mode a bus

dominant clamping is detected and the SPI bit CAN_FAIL is set. The transceiver configuration stays unchanged.

9.2.7

Under Voltage Detection

The voltage at the CAN supply pin is monitored in CAN Normal Mode only. In case of VCAN under voltage a

signalization via SPI bit VCAN_UV is triggered and the SBC disables the transmitter stage. If the CAN supply

reaches a higher level than the under voltage detection threshold (VCAN > VCAN_UV), the transceiver is

automatically switched back to CAN Normal Mode. The transceiver configuration stays unchanged.

Data Sheet

57

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

9.3

Electrical Characteristics

Table 13

Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60ꢀ; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

CAN Bus Receiver

Differential Receiver

Threshold Voltage,

recessive to dominant edge

V_{diff,rd_N}

–

0.80

0.60

0.90

V

V_CANL

-12V ≤ V_CM(CAN)

≤ +12 V;

CAN Normal

Mode

_diff= V_CANH

-

P_10.3.2

;

Differential Receiver

Threshold Voltage,

V_{diff,dr_N}

0.50

–

V_diff= V_CANH

-

P_10.3.3

V_CANL

;

dominant to recessive edge

-12V ≤ V_CM(CAN)

≤ +12 V;

CAN Normal

Mode

1)

Common Mode Range

CMR

-12

20

–

12

50

V

P_10.3.4

P_10.3.6

CANH, CANL Input

Resistance

R_in

40

kꢀ

CAN Normal /

Wake capable

Mode;

Recessive state

Differential Input Resistance R_diff

40

80

100

kꢀ

CAN Normal /

Wake capable

Mode;

P_10.3.7

Recessive state

Input Resistance Deviation

between CANH and CANL

∆R_i

-3

–

3

%

¹⁾Recessive state P_10.3.38

Input Capacitance CANH,

CANL versus GND

C_in

20

40

pF

¹⁾VTXD = 5V

P_10.3.39

DifferentialInputCapacitance C_diff

–

10

20

pF

V

¹⁾VTXD = 5V

P_10.3.40

Wake-up Receiver

V_{diff, rd_W}

0.8

1.15

-12V ≤ V_CM(CAN) P_10.3.8

≤ +12 V;

Threshold Voltage,

recessive to dominant edge

CAN Wake

Capable Mode

Wake-up Receiver

Threshold Voltage,

V_{diff, dr_W}

0.4

0.7

–

V

-12V ≤ V_CM(CAN) P_10.3.9

≤ +12 V;

dominant to recessive edge

CAN Wake

Capable Mode

Data Sheet

58

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

Table 13

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60ꢀ; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

CAN Bus Transmitter

CANH/CANL Recessive

Output Voltage

(CAN Normal Mode)

V_{CANL/H_NM}2.0

–

3.0

V

CAN Normal

Mode;

V_TXD= V_CC1;

P_10.3.11

no load

CANH/CANL Recessive

Output Voltage

(CAN Wake Capable Mode)

V_{CANL/H_LP}

V_{diff_r_N}

V_{diff_r_W}

V_CANL

-0.1

-500

0.5

0.1

50

V

CAN Wake

Capable Mode;

P_10.3.43

P_10.3.12

P_10.3.41

P_10.3.13

V_TXD= V_CC1

;

no load

CANH, CANL Recessive

Output Voltage Difference

V_diff= V_CANH- V_CANL

mV

V

CAN Normal

Mode

V_TXD= V_CC1;

(CAN Normal Mode)

no load

CANH, CANL Recessive

Output Voltage Difference

V_diff= V_CANH- V_CANL

50

CAN Wake

Capable Mode;

_TXD= V_CC1

no load

V

;

(CAN Wake Capable Mode)

CANL Dominant Output

Voltage

2.25

CAN Normal

Mode;

V

_TXD= 0 V;

_CAN= 5 V;

50ꢀ ≤ R_L≤ 65ꢀ

CANH Dominant Output

Voltage

V_CANH

V_{diff_d_N}

V_SYM

2.75

1.5

–

4.5

3.0

5.5

V

CAN Normal

Mode;

P_10.3.14

P_10.3.16

P_10.3.42

V

_TXD= 0 V;

_CAN= 5 V;

50ꢀ ≤ R_L≤ 65ꢀ

CANH, CANL Dominant

Output Voltage Difference

CAN Normal

Mode;

V_diff= V_CANH- V_CANL

V

_TXD= 0 V;

_CAN= 5 V;

50ꢀ ≤ R_L≤ 65ꢀ

²⁾CAN Normal

Mode;

Driver Symmetry

_SYM= V_CANH+ V_CANL

4.5

V

_TXD= 0 V / 5 V;

_CAN= 5 V;

C

_SPLIT= 4.7nF;

50ꢀ ≤ R_L≤ 60ꢀ

CANH Short Circuit Current I_CANHsc

-100

-80

-50

mA

CAN Normal

Mode;

P_10.3.17

V_CANHshort= 0 V

Data Sheet

59

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

Table 13

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60ꢀ; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

80

Unit Note /

Test Condition

Number

Min.

Max.

CANL Short Circuit Current I_CANLsc

50

100

mA

CAN Normal

Mode

P_10.3.18

V_CANLshort= 18 V

Leakage Current

(unpowered device)

I_CANH,lk

I_CANL,lk

–

5

7.5

–

µA

V_S= V_CAN= 0V;

0V < V_CANH,L≤ 5V;

³⁾R_test= 0 / 47 kΩ

P_10.3.19

Receiver Output RXD

HIGH level Output Voltage

V_RXD,H

0.8 ×

V_CC1

–

V

CAN Normal

Mode

P_10.3.21

P_10.3.22

I

_RXD(CAN)= -2 mA;

LOW Level Output Voltage

V_RXD,L

–

0.2 ×

V_CC1

CAN Normal

Mode

I

_RXD(CAN)= 2 mA;

Transmission Input TXD

HIGH Level Input Voltage

Threshold

V_TXD,H

–

0.7 ×

V_CC1

V

CAN Normal

Mode

recessive state

P_10.3.23

P_10.3.24

LOW Level Input Voltage

Threshold

V_TXD,L

0.3 ×

V_CC1

–

V

CAN Normal

Mode

dominant state

1)

TXD Input Hysteresis

V_TXD,hys

–

0.12 ×

V_CC1

mV

P_10.3.25

P_10.3.26

TXD Pull-up Resistance

R_TXD

20

–

40

10

80

–

kꢀ

–

CAN Transceiver Enabling

Time

t_CAN,EN

µs

⁴⁾CSN = HIGH to P_10.3.27

first valid

transmitted TXD

dominant

Dynamic CAN-Transceiver Characteristics

Min. Dominant Time for Bus t_Wake1

Wake-up

0.50

–

3

µs

-12V ≤ V_CM(CAN) P_10.3.28

≤ +12 V;

CAN Wake

capable Mode

Wake-up Time-out,

Recessive Bus

t_Wake2

0.5

–

10

ms

µs

⁴⁾CAN Wake

capable Mode

⁴⁾⁵⁾⁶⁾Wake-up

reactiontimeafter

a valid WUP on

CAN bus;

P_10.3.29

P_10.3.44

WUP Wake-up

Reaction Time

t_{WU_WUP}

100

Data Sheet

60

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

Table 13

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60ꢀ; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Propagation Delay

TXD-to-RXD LOW

(recessive to dominant)

t_d(L),TR

–

150

255

ns

²⁾CAN Normal

Mode

C_L= 100 pF;

R_L= 60 ꢀ;

P_10.3.30

V_CAN= 5 V;

C_RXD= 15 pF

Propagation Delay

TXD-to-RXD HIGH

(dominant to recessive)

t_d(H),TR

–

150

255

ns

²⁾CAN Normal

Mode

C_L= 100 pF;

R_L= 60 ꢀ;

P_10.3.31

V_CAN= 5 V;

C_RXD= 15 pF

Propagation Delay

TXD LOW to bus dominant

t_d(L),T

t_d(H),T

t_d(L),R

–

50

–

ns

CAN Normal

Mode

C_L= 100pF;

R_L= 60 ꢀ;

P_10.3.32

P_10.3.33

P_10.3.34

V_CAN= 5 V;

Propagation Delay

TXD HIGH to bus recessive

50

CAN Normal

Mode

C_L= 100 pF;

R_L= 60 ꢀ;

V_CAN= 5 V;

Propagation Delay

bus dominant to RXD LOW

100

CAN Normal

Mode

C_L= 100pF;

R_L= 60 ꢀ;

V_CAN= 5 V;

C_RXD= 15 pF

Propagation Delay

bus recessive to RXD HIGH

t_d(H),R

–

100

–

ns

CAN Normal

Mode

C_L= 100pF;

R_L= 60 ꢀ

P_10.3.35

P_10.3.46

V_CAN= 5 V;

C_RXD= 15 pF

Recessive Bit Width on RXD t_bit(RXD)

(CAN FD up to 2Mbps)

400

–

550

CAN Normal

Mode

C_L= 100pF;

R_L= 60 ꢀ;

V

_CAN= 5 V;

_RXD= 15 pF;

_bit(TXD)= 500ns;

C

t

Refer to

Figure 24

Data Sheet

61

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

Table 13

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60ꢀ; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

2

Unit Note /

Test Condition

Number

Min.

Max.

TXD Permanent Dominant

Time-out

t_{TxD_CAN_TO}

t_{BUS_CAN_TO}

–

ms

⁴⁾CAN Normal

Mode

P_10.3.36

P_10.3.37

BUS Permanent Dominant

Time-out

–

2

–

ms

⁴⁾CAN Normal

Mode

1) Not subject to production test, specified by design.

2) f_TXD= 250 kHz rectangular signal, duty cycle = 50%;

3) Rtest between supply (VS / VCAN) and 0V (GND);

4) Not subject to production test, tolerance defined by internal oscillator tolerance;

5) Wake-up is signalized via INT pin activation in SBC Stop Mode and via VCC1 ramping up with wake from SBC Sleep Mode;

6) Time starts with end of last dominant phase of WUP;

V _TXD

V _CC1

GND

t

V_DIFF

t_{d(L ),T}

t_d(H),T

V _{diff, rd_N}

V _{diff, dr_N}

t

t _d(L),R

t _d(H),R

t_d(L),TR

t

d(H),TR

V _RXD

V _{CC 1}

0.8 x V

CC1

0.2 x V_CC1

GND

CAN dynamic characteristics.vsd

Figure 23 Timing Diagrams for Dynamic Characteristics

Data Sheet

62

Rev. 1.1, 2014-09-26

TLE9260QX

High Speed CAN Transceiver

Figure 24 Timing Diagrams for RXD recessive bit width definition t_bit(RXD)

Data Sheet

63

Rev. 1.1, 2014-09-26

TLE9260QX

Wake and Voltage Monitoring Inputs

10

Wake and Voltage Monitoring Inputs

10.1

Block Description

Internal Supply

I_{PU_WK}

WKx

+

-

t_WK

I_{PD_WK}

V_Ref

Logic

MONx_Input_Circuit_ext.vsd

Figure 25 Wake Input Block Diagram

Features

•

Three High-Voltage inputs with a 3V (typ.) threshold voltage

Alternate Measurement function for high-voltage sensing via WK1 and WK2

Wake-up capability for power saving modes

Edge sensitive wake feature LOW to HIGH and HIGH to LOW

Pull-up and Pull-down current sources, configurable via SPI

Selectable configuration for static sense or cyclic sense working with TIMER1, TIMER2

In SBC Normal and SBC Stop Mode the level of the WK pin can be read via SPI even if the respective WK is

not enabled as a wake source.

Data Sheet

64

Rev. 1.1, 2014-09-26

TLE9260QX

Wake and Voltage Monitoring Inputs

10.2

Functional Description

The wake input pins are edge-sensitive inputs with a switching threshold of typically 3V. This means that both

transitions, HIGH to LOW and LOW to HIGH, result in a signalization by the SBC. The signalization occurs either

in triggering the interrupt in SBC Normal Mode and SBC Stop Mode or by a wake up of the device in SBC Sleep

and SBC Fail-Safe Mode.

Two different wake detection modes can be selected via SPI:

•

Static sense: WK inputs are always active

Cyclic sense: WK inputs are only active for a certain time period (see Chapter 5.2.1)

Two different filter times of 16µs or 64µs can be selected to avoid a parasitic wake-up due to transients or EMC

disturbances in static sense configuration.

The filter time (t_FWK1, t_FWK2) is triggered by a level change crossing the switching threshold and a wake signal is

recognized if the input level will not cross again the threshold during the selected filter time.

Figure 26 shows a typical wake-up timing and parasitic filter.

V_WK

V_WK,th

t

V_INT

t_WK,f

t_INT

No Wake Event

Wake Event

Figure 26 Wake-up Filter Timing for Static Sense

The wake-up capability for each WK pin can be enabled or disabled via SPI command in the WK_CTRL_2

register.

The wake source for a wake via a WKx pin can always be read in the register WK_STAT_1 at the bits WK1_WU,

WK2_WU, and WK3_WU.

The actual voltage level of the WK pin (LOW or HIGH) can always be read in SBC Normal and SBC Stop Mode

in the register WK_LVL_STAT. During Cyclic Sense, the register show the sampled levels of the respective WK

pin.

If FO2...3 are configured as WK inputs in its alternative function (16µs static filter time), then the wake events will

be signalled in the register WK_STAT_2.

Data Sheet

65

Rev. 1.1, 2014-09-26

TLE9260QX

Wake and Voltage Monitoring Inputs

10.2.1

Wake Input Configuration

To ensure a defined and stable voltage levels at the internal comparator input it is possible to configure integrated

current sources via the SPI register WK_PUPD_CTRL. In addition, the wake detection modes (including the filter

time) can be configured via the SPI register WK_FLT_CTRL. An example illustration for the automatic switching

configuration is shown in Figure 27.

Table 14

Pull-Up / Pull-Down Resistor

WKx_PUPD WKx_PUPD Current Sources Note

_1

0

_0

0

no current source WKx input is floating if left open (default setting)

0

1

pull-down

pull-up

WKx input internally pulled to GND

1

0

WKx input internally pulled to internal 5V supply

1

Automatic

switching

If a high level is detected at the WKx input the pull-up source is

activated, if low level is detected the pull down is activated.

Note:If there is no pull-up or pull-down configured on the WK input, then the respective input should be tied to

GND or VS on board to avoid unintended floating of the pin and subsequent wake events.

I_{WKth_min}

I_{WKth_max}

I_WK

V_WKth

Figure 27 Illustration for Pull-Up / Down Current Sources with Automatic Switching Configuration

Table 15

Wake Detection Configuration and Filter Time

WKx_FLT_1 WKx_FLT_0 Filter Time

Description

0

1

0

1

0

Config A

Config B

Config C

static sense, 16µs filter time

static sense, 64µs filter time

Cyclic sense, Timer 1, 16µs filter time. Period, On-time

configurable in register TIMER1_CTRL

1

Config D

Cyclic sense, Timer 2, 16µs filter time. Period, On-time

configurable in register TIMER2_CTRL

Config A and B are intended for static sense with two different filter times.

Config C or D are intended for cyclic sense configuration. With the filter settings, the respective timer needs to be

assigned to one or more HS output, which supplies an external circuit connected to the WKx pin, e.g. HS1

controlled by Timer 2 (HS1 = 010) and connected to WK3 via an switch circuitry - see also Chapter 5.2.

Data Sheet

66

Rev. 1.1, 2014-09-26

TLE9260QX

Wake and Voltage Monitoring Inputs

10.2.2

Alternate Measurement Function with WK1 and WK2

10.2.2.1 Block Description

This function provides the possibility to measure a voltage, e.g. the unbuffered battery voltage, with the protected

WK1 HV-input. The measured voltage is routed out at WK2. It allows for example a voltage compensation for LED

lighting by changing the duty cycle of the High-Side outputs. A simple voltage divider needs to be placed externally

to provide the correct voltage level to the microcontroller A/D converter input.

The function is available in SBC Normal Mode and it is disabled in all other modes to allow a low-quiescent current

operation.The measurement function can be used instead of the WK1 and WK2 wake and level signalling

capability.

The benefits of the function is that the signal is measured by a HV-input pin and that there is no current flowing

through the resistor divider during low-power modes.

The functionality is shown in a simplified application diagram in Figure 48.

10.2.2.2 Functional Description

This measurement function is by default disabled. In this case, WK1 and WK2 have the regular wake and voltage

level signalization functionality. The switch S1 is open for this configuration (see Figure 48).

The measurement function can be enabled via the SPI bit WK_MEAS.

If WK_MEAS is set to ‘1’, then the measurement function is enabled and switch S1 is closed in SBC Normal Mode.

S1 is open in all other SBC modes. If this function the pull-up and down currents of WK1 and WK2 are disabled,

and the internal WK1 and WK2 signals are gated. In addition, the settings for WK1 and WK2 in the registers

WK_PUPD_CTRL, WK_FLT_CTRL and WK_CTRL_2 are ignored but changing these setting is not prevented.

The registers WK_STAT_1 and WK_LVL_STAT are not updated with respect to the inputs WK1 and WK2.

However, if only WK1 or WK2 are set as wake sources and a SBC Sleep Mode command is set, then the SPI_FAIL

flag will be set and the SBC will be changed into SBC Restart Mode (see Chapter 5.1 also for wake capability of

WK1 and WK2).

Table 16

Differences between Normal WK Function and Measurement Function

Affected Settings/Modules

for WK1 and WK2 Inputs

WK_MEAS = 0

WK_MEAS = 1

S1 configuration

‘open’

‘closed’ in SBC Normal Mode,

‘open’ in all other SBC Modes

Internal WK1 & WK2 signal

processing

Default wake and level signaling

‘WK1...2 inputs are gated internally,

function, WK_STAT_1, WK_STAT_2 WK_STAT_1, WK_STAT_2 are not

are updated accordingly updated

Wake-up via WK1 and WK2 possible if setting the bits is ignored and not

WK1_EN, WK2_EN

bits are set

prevented. If only WK1_EN, WK2_EN

are set while trying to go to SBC Sleep

Mode, then the SPI_FAIL flag will be

set and the SBC will be changed into

SBC Restart Mode.

WK_PUPD_CTRL

WK_FLT_CTRL

normal configuration is possible

no pull-up or pull-down enabled

setting the bits is ignored and not

prevented

Note:There is a diode in series to the switch S1 (not shown in the Figure 48), which will influence the temperature

behavior of the switch.

Data Sheet

67

Rev. 1.1, 2014-09-26

TLE9260QX

Wake and Voltage Monitoring Inputs

10.3

Electrical Characteristics

Table 17

Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note / Test Condition Number

Min.

WK1...WK3 Input Pin Characteristics

Max.

Wake-up/monitoring

threshold voltage

V_WKth

2

3

4

V

without external serial P_12.3.1

resistor R_S(with R_S:

∆V = I_PD/PU* R_S);

hysteresis included

Threshold hysteresis

V_WKNth,hys0.1

-

0.7

without external serial P_12.3.2

resistor R_S(with R_S:

∆V = I_PD/PU* R_S);

WK pin Pull-up Current I_{PU_WK}

-20

3

-10

10

-3

µA

V

_{WK_IN}= 4V

_{WK_IN}= 2V

P_12.3.3

P_12.3.4

WK pin Pull-down

Current

I_{PD_WK}

20

Input leakage current

I_LK,l

-2

–

2

–

µA

0 V < V_{WK_IN}< 40V

¹⁾Drop Voltage

P_12.3.5

Drop Voltage across S1 V_Drop,S1

1000

mV

P_12.3.13

switch

between WK1 and

WK2 when enabled for

voltage measurement;

I

_WK1= 500µA;

T_j= 25°C

Refer to Figure 28

Timing

Wake-up filter time 1

Wake-up filter time 2

t_FWK1

t_FWK2

-

16

64

-

µs

²⁾SPI Setting

P_12.3.6

P_12.3.7

1) Not subject to production test; specified by design

2) Not subject to production test, tolerance defined by internal oscillator tolerance

Data Sheet

68

Rev. 1.1, 2014-09-26

TLE9260QX

Wake and Voltage Monitoring Inputs

1100

1000

900

800

700

600

500

VS = 13.5V

500 μA

250 μA

100 μA

50 μA

ꢁ50

0

50

100

150

Tjꢀꢀꢀꢁ JUNCTIONꢀTEMPERATUREꢀ(°C)

Figure 28 Typical Drop Voltage Characteristics of S1 (between WK1 & WK2)

Data Sheet

69

Rev. 1.1, 2014-09-26

TLE9260QX

Interrupt Function

11

Interrupt Function

11.1

Block and Functional Description

V_cc1

INT

Time

out

Interrupt logic

Figure 29 Interrupt Block Diagram

The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is designed

as a push/pull output stage as shown in Figure 29. An interrupt is triggered and the INT pin is pulled low (active

low) for t_INTin SBC Normal and Stop Mode and it is released again once t_INTis expired. The minimum HIGH-time

of INT between two consecutive interrupts is t_INTD. An interrupt does not cause a SBC mode change.

Two different interrupt classes could be selected via the SPI bit INT_ GLOBAL:

•

Class 1 (wake interrupt - INT_ GLOBAL=0): all wake-up events stored in the wake status SPI register

(WK_STAT_1 and WK_STAT_2) cause an interrupt (default setting). An interrupt is only triggered if the

respective function is also enabled as a wake source (including GPIOx if configured as a wake input).

•

Class 2 (global interrupt - INT_ GLOBAL=1): in addition to the wake-up events, all signalled failures stored in

the other status registers cause an interrupt (the register WK_LVL_STAT is not generating interrupts)

Note:The errors which will cause SBC Restart or SBC Fail-Safe Mode (Vcc1_UV, WD_FAIL, VCC1_SC, TSD2,

FAILURE) are the exceptions of an INT generation on status bits. Also POR and DEV_STAT_x and will not

generate interrupts.

In addition to this behavior, an INT will be triggered when the SBC is sent to SBC Stop Mode and not all bits were

cleared in the WK_STAT_1 and WK_STAT_2register.

The SPI status registers are updated at every falling edge of the INT pulse. All interrupt events are stored in the

respective register (except the register WK_LVL_STAT) until the register is read and cleared via SPI command.

A second SPI read after reading out the respective status register is optional but recommended to verify that the

interrupt event is not present anymore. The interrupt behavior is shown in Figure 30 for class 1 interrupts. The

behavior for class 2 is identical.

The INT pin is also used during SBC Init Mode to select the hardware configuration of the device. See

Chapter 5.1.1 for further information.

Data Sheet

70

Rev. 1.1, 2014-09-26

TLE9260QX

Interrupt Function

WK1

WK2

INT

t_INTD

t_INT

Update of

WK_STAT register

Update of

WK_STAT register

optional

SPI

Read & Clear

WK_STAT

contents

WK1

no WK

WK2

no WK

SPI

Read & Clear

No SPI Read & Clear

Command sent

WK_STAT

contents

WK1 + WK2

no WK

Interrupt_Behavior.vsd

Figure 30 Interrupt Signalization Behavior

Data Sheet

71

Rev. 1.1, 2014-09-26

TLE9260QX

Interrupt Function

11.2

Electrical Characteristics

Table 18

Interrupt Output

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Number

Min.

Max.

Interrupt Output; Pin INT

1)

INT High Output Voltage

V_INT,H

V_INT,L

t_INT

0.8 ×

V_CC1

–

V

I

= -1 mA;

P_13.2.1

P_13.2.2

INT

INT = OFF

¹⁾I_INT= 1 mA;

INT = ON

2)

INT Low Output Voltage

INT Pulse Width

–

0.2 ×

V_CC1

–

100

–

µs

P_13.2.3

P_13.2.4

INT Pulse Minimum Delay t_INTD

²⁾between

Time

consecutive pulses

Configuration Select; Pin INT

Config Pull-down

Resistance

R_CFG

–

250

7

–

kꢀ

V

_INT= 5 V

P_13.2.5

P_13.2.6

2)

Config Select Filter Time

t_{CFG_F}

µs

1) Output Voltage Value also determines device configuration during SBC Init Mode

2) Not subject to production test, tolerance defined by internal oscillator tolerance.

Data Sheet

72

Rev. 1.1, 2014-09-26

TLE9260QX

Fail Outputs

12

Fail Outputs

12.1

Block and Functional Description

5V_int

T _test

SBC Init

Mode

R_TEST

FO1/2

Failure logic

FO3/TEST

T_{FO_PL}

Failure Logic

Figure 31 Simplified Fail Output Block Diagram for FO1/2 and for FO3/TEST

The fail outputs consist of a failure logic block and three open-drain outputs (FO1, FO2, FO3) with active-low

signalization.

The fail outputs are activated due to following failure conditions:

•

Watchdog trigger failure (For config 3&4 only after the 2nd watchdog trigger failure and for config 1&2 after 1st

watchdog trigger failure)

•

Thermal shutdown TSD2

VCC1 short to GND

VCC1 over voltage (only if the SPI bit VCC1_OV_RST is set)

After 4 consecutive VCC1 under voltage event (see Chapter 13.6 for details)

At the same time SBC Fail-Safe Mode is entered (exceptions are watchdog trigger failures depending on selected

configurations - see Chapter 5.1.1).

The fail output activation is signalled in the SPI bit FAILURE of the register DEV_STAT.

For testing purposes only the Fail Outputs can also be activated via SPI by setting the bit FO_ON. This bit is

independent of the FO failure bits. In case that there is no failure condition, the FO outputs can also be turned off

again via SPI, i.e. no successful watchdog trigger is needed.

The entry of SBC Fail-Safe Mode due to a watchdog failure can be configured as described in Chapter 5.1.1.

In order to deactivate the fail outputs in SBC Normal Mode the failure conditions must not be present anymore

(e.g. TSD2, VCC1 short circuit, etc) and the bit FAILURE needs to be cleared via SPI command. In case of a

FAILURE bit setting due to a watchdog fail, a successful WD trigger is needed in addition, i.e. WD_FAIL must be

cleared. WD_FAIL will also be cleared when going to SBC Sleep or SBC Fail-Safe Mode due to another failure

(not a WD failure) or if the watchdog is disabled in SBC Stop Mode.

Note:The Fail output pin is triggered for any of the above described failures. No FAILURE is caused for the 1st

watchdog failure if selected for Config2.

The three fail outputs are activated simultaneously with following output functionalities:

•

FO1: Static fail output

FO2: 1.25Hz, 50% (typ.) duty cycle, e.g. to generate an indicator signal

Data Sheet

73

Rev. 1.1, 2014-09-26

TLE9260QX

Fail Outputs

•

FO3: 100Hz PWM, 20% (typ.) duty cycle, e.g. to generate a dimmed rear light from a break light.

Note:The duty cycle for FO3 can be configured via SPI option to 20%, 10%, 5% or 2.5%. Default value is 20%.

See the register FO_DC for configuration.

12.1.1

General Purpose I/O Functionality of FO2 and FO3 as Alternate Function

In case that FO2 and FO3 are not used in the application, those pins can also be configured with an alternate

function as high-voltage (VSHS related) General Purpose I/O pins.

VSHS

Config &

Control Logic

FOx/

GPIOx

Figure 32 Simplified General Purpose I/O block diagram for FO2 and FO3/TEST

The pins are by default configured as FO pins. The configuration is done via the SPI register GPIO_CTRL. The

alternate function can be:

•

Wake Inputs: The detection threshold V_GPIOI,this similar as for the WK inputs. The wake-up detection behavior

is the same as for WKx pins. Wake events are stored and reported in WK_STAT_2.

Low-Side Switches: The switch is able to drive currents of up to 10mA (see also V_GPIOL,L1). It is self-protected

with regards to current limitation. No other diagnosis is implemented.

High-Side Switches: The switch is able to drive currents up to 10mA (see also V_GPIOH,H1). It is self-protected

with regards to current limitation. No other diagnosis is implemented.

If configured as GPIO then the respective level at the pin will be shown in WK_LVL_STAT in SBC Normal and

Stop Mode. This is also the case if configured as LS/HS and can serve as a feedback about the respective

state. GPIO2 is shared with the TEST level bit.

Figure 33 describes the behavior of the FO/GPIO pins in their different configurations and SBC modes.

Function

Normal Mode

Stop Mode

Sleep Mode

Fail-Safe Mode

FOx

WK

HS

keeps the state

wake capable

as configured in Normal Mode

keeps the state

wake capable

OFF

active

OFF

configurable

LS

OFF

Figure 33 FO / GPIO behavior for the respective SBC modes

Note:In order to avoid unintentional entry of SBC Development Mode care must be taken that the level of

FO3/TEST is HIGH during device power up and SBC Init Mode.

Note:The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by

VSHS

Data Sheet

74

Rev. 1.1, 2014-09-26

TLE9260QX

Fail Outputs

12.2

Electrical Characteristics

Table 19

Interrupt Output

V

_SHS= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.¹⁾

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Number

Min.

Max.

Pin FO1

FO1 low output voltage

(active)

V_FO,L1

I_FO,H

–

0

–

1.0

2

V

I

_FO= 4mA

P_14.2.1

P_14.2.2

FO1 high output current

(inactive)

µA

V

_FO= 28V

Pin FO2

3)

FO2 side indicator

frequency

f_FO2SI

1.00

–

1.25

50

1.50

–

Hz

%

P_14.2.3

P_14.2.4

FO2 side indicator duty

cycle

d_FO2SI

Pin FO3/TEST²⁾

Pull-up Resistance at pin R_TEST

2.5

5

10

kꢀ

V

_TEST=0V;

P_14.2.5

FO3/TEST

SBC Init Mode

3)

TEST Input Filter Time

t_TEST

–

64

–

µs

P_14.2.6

P_14.2.7

3)

FO3 pulsed

f_FO3PL

80

100

120

Hz

light frequency

FO3 pulsed

d_FO3PL

–

20

–

%

³⁾⁴⁾default setting

P_14.2.8

light duty cycle

Alternate FO2...3

Electrical Characteristics: GPIO

GPIO low-side output

voltage (active)

V_GPIOL,L1

–

1

V

I

_GPIO= 10mA

⁵⁾I_GPIO= 50µA

_GPO= -10mA

⁵⁾I_GPO= -50µA

P_14.2.9

GPIO low-side output

voltage (active)

V_GPIOL,L2

5

mV

V

P_14.2.17

P_14.2.10

P_14.2.18

GPIO high-side output

voltage (active)

V_GPIOH,H1VSHS-1 –

V_GPIOH,H2VSHS-5 –

–

I

GPIO high-side output

voltage (active)

–

mV

V

GPIO input threshold

voltage

V_GPIOI,th1.5

V_GPIOI,hys100

I_GPIOL,max10

I_GPIOH,max-45

2.5

3.5

700

30

-10

⁶⁾hysteresis included P_14.2.11

5)

GPIO input threshold

hysteresis

400

–

mV

mA

P_14.2.12

GPIO low-side current

limitation

V

_GPIO= 28V

_GPIO= 0V

P_14.2.13

P_14.2.14

GPIO high-side current

limitation

–

1) The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by VSHS

Data Sheet

75

Rev. 1.1, 2014-09-26

TLE9260QX

Fail Outputs

2) The external capacitance on this pin must be limited to less than 10nF to ensure proper detection of SBC Development

Mode and SBC User Mode operation.

3) Not subject to production test, tolerance defined by internal oscillator tolerance.

4) The duty cyclic is adjustable via the SPI bits FO_DC.

5) Not subject to production test, specified by design.

6) Applies also for TEST voltage input level

Data Sheet

76

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

13

Supervision Functions

13.1

Reset Function

VCC1

RO

Resetlogic

Incl. filter & delay

Figure 34 Reset Block Diagram

13.1.1

Reset Output Description

The reset output pin RO provides a reset information to the microcontroller, for example, in the event that the

output voltage has fallen below the under voltage threshold V_RT1/2/3/4. In case of a reset event, the reset output RO

is pulled to low after the filter time t_RFand stays low as long as the reset event is present plus a reset delay time

t_RD1. When connecting the SBC to battery voltage, the reset signal remains LOW initially. When the output voltage

V_cc1has reached the reset default threshold V_RT1,r, the reset output RO is released to HIGH after the reset delay

time t_RD1. A reset can also occur due to a watchdog trigger failure. The reset threshold can be adjusted via SPI,

the default reset threshold is V_RT1,f. The RO pin has an integrated pull-up resistor. In case reset is triggered, it will

be pulled low for V_cc1≥ 1V and for VS ≥ V_POR,f(see also Chapter 13.3).

The timings for the RO triggering regarding VCC1 under voltage and watchdog trigger is shown in Figure 35.

Data Sheet

77

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

VCC

V_RT1

t < t_RF

The reset threshold can be

configured via SPI in SBC

Normal Mode, default is V_RT1

undervoltage

t

t_CW

t_OW

t_RD1

t_CW

t_LW

t_RD1

t_LW

t_CW

t_OW

SPI

RO

SPI

Init

WD

Trigger

WD

Trigger

SPI

Init

t

t_RF

t_LW= long open window

t_CW= closed window

t_OW= open window

SBC Init

SBC Normal

SBC Restart

SBC Normal

Figure 35 Reset Timing Diagram

13.1.2

Soft Reset Description

In SBC Normal and SBC Stop Mode, it is also possible to trigger a device internal reset via a SPI command in

order to bring the SBC into a defined state in case of failures. In this case the microcontroller must send a SPI

command and set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as this command becomes valid, the

SBC is set back to SBC INIT Mode and all SPI registers are set to their default values (see SPI Chapter 14.5 and

Chapter 14.6).

Two different soft reset configurations are possible via the SPI bit SOFT_ RESET_RO:

•

The reset output (RO) is triggered when the soft reset is executed (default setting, the same reset delay time

t_RD1applies)

•

The reset output (RO) is not triggered when the soft reset is executed

Note:The device must be in SBC Normal Mode or SBC Stop Mode when sending this command.

Otherwise, the command will be ignored.

Data Sheet

78

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

13.2

Watchdog Function

The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the

microcontroller stops serving the watchdog due to a lock up in the software.

Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN:

•

Time-Out Watchdog (default value)

Window Watchdog

The respective watchdog functions can be selected and programmed in SBC Normal Mode. The configuration

stays unchanged in SBC Stop Mode.

Please refer to Table 20 to match the SBC Modes with the respective watchdog modes.

Table 20

Watchdog Functionality by SBC Modes

Watchdog Mode

SBC Mode

INIT Mode

Remarks

Starts with Long Open Window Watchdog starts with Long Open Window after RO is

released

Normal Mode

WD Programmable

Window Watchdog, Time-Out watchdog or switched

OFF for SBC Stop Mode

Stop Mode

Watchdog is fixed or OFF

OFF

Sleep Mode

SBC will start with Long Open Window when entering

SBC Normal Mode.

Restart Mode

OFF

SBC will start with Long Open Window when entering

SBC Normal Mode.

The watchdog timing is programmed via SPI command. As soon as the watchdog is programmed, the timer starts

with the new setting and the watchdog must be served. The watchdog is triggered by sending a valid SPI-write

command to the watchdog configuration register. The trigger SPI command is executed when the Chip Select

input (CSN) becomes HIGH.

When coming from SBC Init, SBC Restart Mode or in certain cases from SBC Stop Mode, the watchdog timer is

always started with a long open window. The long open window (t_LW= 200ms) allows the microcontroller to run its

initialization sequences and then to trigger the watchdog via SPI.

The watchdog timer period can be selected via the watchdog timing bit field (WD_TIMER) and is in the range of

10 ms to 1000 ms. This setting is valid for both watchdog types.

The following watchdog timer periods are available:

•

WD Setting 1: 10ms

WD Setting 2: 20ms

WD Setting 3: 50ms

WD Setting 4: 100ms

WD Setting 5: 200ms

WD Setting 6: 500ms

WD Setting 7: 1000ms

In case of a watchdog reset, SBC Restart or SBC Fail-Safe Mode is entered according to the configuration and

the SPI bits WD_FAIL are set. Once the RO goes HIGH again the watchdog immediately starts with a long open

window the SBC enters automatically SBC Normal Mode.

In SBC Software Development Mode the watchdog is OFF and therefore no reset and interrupt are generated due

to a watchdog failure.

Data Sheet

79

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

Depending on the configuration, the WD_FAIL bits will be set after a watchdog trigger failure as follows:

•

In case an incorrect WD trigger is received (triggering in the closed watchdog window or when the watchdog

counter expires without a valid trigger) then the WD_FAIL bits will be increased (showing the number of

incorrect WD triggers)

•

For config 2: the bits can have the maximum value of ‘01’

For config 1, 3 and 4: the bits can have the maximum value of ‘10’

The WD_FAIL bits are cleared automatically when following conditions apply:

•

After a successful watchdog trigger

When the watchdog is OFF: in SBC Stop Mode after successfully disabling it, in SBC Sleep Mode, or in SBC

Fail-Safe Mode (except for a watchdog failure)

13.2.1

Time-Out Watchdog

The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog trigger

can be done at any time within the configured watchdog timer period.

A correct watchdog service immediately results in starting a new watchdog timer period. Taking the tolerances of

the internal oscillator into account leads to the safe trigger area as defined in Figure 36.

If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RO low and the

SBC switches to SBC Restart or SBC Fail-Safe Mode.

Typical timout watchdog trigger period

t

_WDx 1.50

open window

uncertainty

Watchdog Timer Period (WD_TIMER)

t_WDx 1.20

t_WDx 1.80

t / [t_{WD_TIMER}

]

safe trigger area

Wd1_TimeOut_per.vsd

Figure 36 Time-out Watchdog Definitions

Data Sheet

80

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

13.2.2

Window Watchdog

Compared to the time-out watchdog the characteristic of the window watchdog is that the watchdog timer period

is divided between an closed and an open window. The watchdog must be triggered within the open window.

A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an open

window.

The watchdog timer period is at the same time the typical trigger time and defines the middle of the open window.

Taking the oscillator tolerances into account leads to a safe trigger area of:

t_WDx 0.72 < safe trigger area < t_WDx 1.20.

The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking the

tolerances of the internal oscillator into account leads to the timings as defined in Figure 37.

A correct watchdog service immediately results in starting the next closed window.

Should the trigger signal meet the closed window or should the watchdog timer period elapse, then a watchdog

reset is created by setting the reset output RO low and the SBC switches to SBC Restart or SBC Fail-Safe Mode.

t_WDx 0.6

t_WDx 0.9

Typ. closed window

Typ. open window

t_WDx 0.48

t_WDx 0.72

t_WDx 1.0

t_WDx 1.20

t_WDx 1.80

closed window

uncertainty

open window

uncertainty

Watchdog Timer Period (WD_TIMER)

t / [t_{WD_TIMER}

]

safe trigger area

Figure 37 Window Watchdog Definitions

13.2.3

Watchdog Setting Check Sum

A check sum bit is part of the SPI commend to trigger the watchdog and to set the watchdog setting.

The sum of the 8 data bits in the register WWD_CTRL needs to have even parity (see Equation (1)). This is

realized by either setting the bit CHECKSUM to 0 or 1. If the check sum is wrong, then the SPI command is

ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set.

The checksum is calculated by taking all 8 data bits into account. The written value of the reserved bit 3 of the

WWD_CTRL register is considered (even if read as ‘0’ in the SPI output) for checksum calculation, i.e. if a 1 is

written on the reserved bit position, then a 1 will be used in the checksum calculation.

(1)

CHKSUM = Bit15 ⊕ … ⊕ Bit8

Data Sheet

81

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

13.2.4

Watchdog during SBC Stop Mode

The watchdog can be disabled for SBC Stop Mode in SBC Normal Mode. For safety reasons, there is a special

sequence to be followed in order to disable the watchdog as described in Figure 38. Two different SPI bits

(WD_STM_ EN_0, WD_STM_ EN_1) in the registers WK_CTRL_1 and WD_CTRL need to be set.

Correct WD disabling

Sequence Errors

sequence

•

Missing to set bit

WD_STM_EN_0 with the

next watchdog trigger after

having set WD_STM_EN_1

Set bit

WD_STM_EN_1 = 1

with next WD Trigger

•

Staying in Normal Mode

instead of going to Stop

Mode with the next trigger

Set bit

WD_STM_EN_0 = 1

Before subsequent WD Trigger

Will enable the WD:

Change to

SBC Stop Mode

•

Switching back to SBC

Normal Mode

•

Triggering the watchdog

WD is switched off

Figure 38 Watchdog disabling sequence in SBC Stop Mode

If a sequence error occurs, then the bit WD_STM_ EN_1 will be cleared and the sequence has to be started again.

The watchdog can be enabled by triggering the watchdog in SBC Stop Mode or by switching back to SBC Normal

Mode via SPI command. In both cases the watchdog will start with a long open window and the bits

WD_STM_EN_1 and WD_STM_ EN_0 are cleared. After the long open window the watchdog has to be served

as configured in the WD_CTRL register.

Note:The bit WD_STM_ EN_0 will be cleared automatically when the sequence is started and it was 1 before.

13.2.5

Watchdog Start in SBC Stop Mode due to Bus Wake

In SBC Stop Mode the Watchdog can be disabled. In addition a feature is available which will start the watchdog

with any BUS wake (CAN) during SBC Stop Mode. The feature is enabled by setting the bit WD_EN_ WK_BUS = 1

(= default value after POR). The bit can only be changed in SBC Normal Mode and needs to be programmed

before starting the watchdog disable sequence.

A wake on CAN will generate an interrupt and the RXD pin for CAN is pulled to low. By these signals the

microcontroller is informed that the watchdog is startedwith a long open window. After the long open window the

watchdog has to be served as configured in the WD_CTRL register.

To disable the watchdog again, the SBC needs to be switched to Normal Mode and the sequence needs to be

sent again.

Data Sheet

82

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

13.3

VS Power On Reset

At power up of the device, the VS Power on Reset is detected when VS > V_POR,rand the SPI bit POR is set to

indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be kept

LOW and will only be released once VCC1 has crossed V_RT1,rand after t_RD1has elapsed.

In case VS < V_POR,f, an device internal reset will be generated and the SBC is switched OFF and will restart in INIT

mode at the next VS rising. This is shown in Figure 39.

VS

V_POR,r

V_POR,f

t

VCC1

V_RT1,r

The reset threshold can be

configured via SPI in SBC

V_RTx,f

Normal Mode, default is V_RT1

RO

SBC Restart Mode is

entered whenever the

Reset is triggered

t

t_RD1

SBC Mode

Re-

start

SBC OFF

SBC INIT MODE

Any SBC MODE

SBC OFF

t

SPI

Command

Figure 39 Ramp up / down example of Supply Voltage

Data Sheet

83

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

13.4

Under Voltage VS and VSHS

If the supply voltage VS reaches the under voltage threshold V_S,UVthen the SBC does the following measures:

•

SPI bit VS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present

anymore,

The VCC1 short circuit protection becomes inactive (see Chapter 13.7). However, the thermal protection of

the device remains active.

If the under voltage threshold is exceeded (VS rising) then functions will be automatically enabled again.

If the supply voltage VSHS passes below the under voltage threshold (V_SHS,UVD) the SBC does the following

measures:

•

HS1...4 are acting accordingly to the SPI setting (see Chapter 8)

SPI bit VSHS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present

anymore,

•

VCC1, VCC2, WKx and CAN are not affected by VSHS under voltage

13.5

Over Voltage VSHS

If the supply voltage VSHS reaches the over voltage threshold (V_SHS,OVD) the SBC triggers the following measures:

•

HS1...4 are acting accordingly to the SPI setting (see Chapter 8)

SPI bit VSHS_OV is set. No other error bits are set. The bit can be cleared once the condition is not present

anymore,

•

VCC1, VCC2, WKx and CAN are not affected by VS over voltage

13.6

VCC1 Over-/ Under Voltage and Under Voltage Prewarning

VCC1 Under Voltage and Under Voltage Prewarning

13.6.1

A first-level voltage detection threshold is implemented as a prewarning for the microcontroller. The prewarning

event is signaled with the bit VCC1_ WARN. No other actions are taken.

As described in Chapter 13.1 and Figure 40, a reset will be triggered (RO pulled ‘low’) when the V_CC1output

voltage falls below the selected under voltage threshold (V_RTx). The bit VCC1_UV is set and the SBC will enter

SBC Restart Mode.

Note:The VCC1_ WARN or VCC1_UV bits are not set in Sleep Mode as V_CC1= 0V in this case

Data Sheet

84

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

VCC1

RO

V_RTx

t

t_RF

t_RD1

SBC Normal

Figure 40 VCC1 Under Voltage Timing Diagram

SBC Restart

SBC Normal

An additional safety mechanism is implemented to avoid repetitive VCC1 under voltage resets due to high dynamic

loads on VCC1:

•

A counter is increased for every consecutive VCC1 under voltage event (regardless on the selected reset

threshold),

•

The counter is active in SBC Init-, Normal-, and Stop Mode,

For VS < V_S,UVthe counter will be stopped in SBC Normal Mode (i.e. the VS UV comparator is always enabled

in SBC Normal Mode),

•

A 4th consecutive VCC1 under voltage event will lead to SBC Fail-Safe Mode entry and to setting the bit

VCC1_UV _FS

This counter is cleared:

–

when SBC Fail-Safe Mode is entered,

when the bit VCC1_UV is cleared,

when a Soft Reset is triggered.

Note:It is recommended to clear the VCC1_UV bit once it was set and detected.

13.6.2

VCC1 Over Voltage

For fail-safe reasons a configurable VCC1 over voltage detection feature is implemented. It is active in SBC Init-,

Normal-, and Stop Mode.

In case the V_CC1,OV,rthreshold is crossed, the SBC triggers following measures depending on the configuration:

•

The bit VCC1_ OV is always set;

If the bit VCC1_OV_RST is set and CFGP = ‘1’, then SBC Restart Mode is entered. The FOx outputs are

activated. After the reset delay time (t_RD1), the SBC Restart Mode is left and SBC Normal Mode is resumed

even if the VCC1 over voltage event is still present (see also Figure 41). The VCC1_OV_RST bit is cleared

automatically;

•

If the bit VCC1_OV_RST is set and CFGP = ‘0’, then SBC Fail-Safe Mode is entered and FOx outputs are

activated.

Note:In case the VCC1 output current in SBC STOP Mode is below the active peak threshold (I_VCC1,Ipeak) it should

be considered to clear the bit VCC1_OV_RST before entering SBC Stop Mode to avoid unintentional SBC

Restart or Fail-Safe Mode entry and to ignore the VCC1_ OV bit due to external noise.

Data Sheet

85

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

VCC1

V_CC1,OV

t

t_{OV_filt}

RO

t_RD1

SBC Normal

Figure 41 VCC1 Over Voltage Timing Diagram

SBC Restart

SBC Normal

13.7

VCC1 Short Circuit Diagnostics

The short circuit protection feature for V_CC1is implemented as follows (VS needs to be higher than V_S,UV):

•

If VCC1 is not above the V_RTxwithin t_VCC1,SCafter device power up or after waking from SBC Sleep Mode then

the SPI bit VCC1_SC bit is set, VCC1 is turned OFF, the FOx pins are enabled, FAILURE is set and SBC Fail-

Safe Mode is entered. The SBC can be activated again via wake on CAN, WKx.

•

The same behavior applies, if V_CC1falls below V_RTxfor more than t_VCC1,SC

.

Note:The VCC1_SC flag is not set during power up of V_CC1

.

13.8

VCC2 Undervoltage and VCAN Undervoltage

An undervoltage warning is implemented for VCC2 and VCAN as follows:

•

V

_CC2undervoltage Detection: In case V_CC2will drop below the V_CC2,UV,fthreshold, then the SPI bit VCC2_UV

is set and can be only cleared via SPI.

_CANundvervoltage Detection: In case the voltage on V_CANwill drop below the V_{CAN_UV}threshold, then the SPI

bit VCAN_UV is set and can be only cleared via SPI.

Note:The VCC2_UV flag is not set during turn-on or turn-off of V_CC2.

•

V

Data Sheet

86

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

13.9

Thermal Protection

Three independent and different thermal protection features are implemented in the SBC according to the system

impact:

•

Individual thermal shutdown of specific blocks

Temperature prewarning of main microcontroller supply VCC1

SBC thermal shutdown due to VCC1 over temperature

13.9.1

Individual Thermal Shutdown

As a first-level protection measure the output stages VCC2, CAN, and HSx are independently switched OFF if the

respective block reaches the temperature threshold T_jTSD1. Then the TSD1 bit is set. This bit can only be cleared

via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the thermal shutdown

protection is only active if the respective block is ON.

The respective modules behave as follows:

•

VCC2: Is switched to OFF and the control bits VCC2_ON are cleared. The status bit VCC2_OT is set. Once

the over temperature condition is not present anymore, then VCC2 has to be configured again by SPI.

•

CAN: The transmitter is disabled and stays in CAN Normal Mode acting like CAN Receive only mode. The

status bits CAN_FAIL = ‘01’ are set. Once the over temperature condition is not present anymore, then the

CAN transmitter is automatically switched on.

•

HSx: If one or more HSx switches reach the TSD1 threshold, then all HSx switches are turned OFF and the

control bits for HSx are cleared (see registers HS_CTRL1 and HS_CTRL2). The status bits HSx_OC_OT are

set (see register HS_OC_OT_STAT). Once the over temperature condition is not present anymore, then HSx

has to be configured again by SPI.

Note:The diagnosis bits are not cleared automatically and have to be cleared via SPI once the overtemperature

condition is not present anymore.

Data Sheet

87

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

13.9.2

Temperature Prewarning

As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1 reaches

the thermal prewarning temperature threshold T_jPW. Then the status bit TPW is set. This bit can only be cleared

via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the thermal prewarning

is only active if the VCC1 is ON.

13.9.3

SBC Thermal Shutdown

As a highest level of thermal protection a temperature shutdown of the SBC is implemented if the main supply

VCC1 reaches the thermal shutdown temperature threshold T_jTSD2. Once a TSD2 event is detected SBC Fail-Safe

Mode is entered for t_TSD2to allow the device to cool down. After this time has expired, the SBC will automatically

change via SBC Restart Mode to SBC Normal Mode (see also Chapter 5.1.6).

When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in SBC Normal

Mode once the overtemperature is not present anymore. Independent of the SBC Mode the thermal shutdown is

only active if VCC1 is ON.

Data Sheet

88

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

13.10

Electrical Characteristics

Table 21

Electrical Specification

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

VCC1 Monitoring; VCC1 = 5.0V Version

Undervoltage Prewarning

Threshold Voltage PW,f

V_PW,f

V_RT1,f

V_RT1,r

V_RT2,f

V_RT2,r

V_RT3,f

V_RT3,r

V_RT4,f

V_RT4,r

4.6

4.7

4.6

4.7

3.9

4.0

3.3

3.4

2.65

2.75

4.85

4.75

4.85

4.05

4.15

3.45

3.55

2.8

V

VCC1 falling,

SPI bit is set

P_15.10.1

P_15.10.3

P_15.10.4

P_15.10.5

P_15.10.6

P_15.10.7

P_15.10.8

P_15.10.9

P_15.10.10

Reset Threshold

Voltage RT1,f

4.5

default setting;

VCC1 falling

Reset Threshold

Voltage RT1,r

4.6

default setting;

VCC1 rising

Reset Threshold

Voltage RT2,f

3.75

3.85

3.15

3.25

2.4

VCC1 falling

Reset Threshold

Voltage RT2,r

VCC1 rising

Reset Threshold

Voltage RT3,f

VS ≥ 4V;

VCC1 falling

Reset Threshold

Voltage RT3,r

VS ≥ 4V;

VCC1 rising

Reset Threshold

Voltage RT4,f

VS ≥ 4V;

VCC1 falling

Reset Threshold

Voltage RT4,r

2.5

2.9

VS ≥ 4V;

VCC1 rising

Reset Threshold Hysteresis V_RT,hys

50

100

–

200

5.5

mV

V

–

P_15.10.11

P_15.10.50

VCC1 Over Voltage

V_CC1,OV,r

5.2

¹⁾⁵⁾rising VCC1

Detection Threshold Voltage

3)

VCC1 Short to GND Filter

Time

t_VCC1,SC

–

4

–

ms

P_15.10.12

Reset Generator; Pin RO

Reset Low Output Voltage

V_RO,L

0.2

–

0.4

V

I

_RO= 1 mA for

_CC1≥ 1 V &

V_S≥ V_POR,f

I_RO= -20 µA

P_15.10.14

P_15.10.15

V

Reset High Output Voltage

V_RO,H

0.8 x

V_CC1

+

V_CC1

0.3 V

Reset Pull-up Resistor

Reset Filter Time

R_RO

t_RF

10

4

20

10

40

26

kꢀ

V

_RO= 0 V

P_15.10.16

P_15.10.17

µs

³⁾V_CC1< V_RT1x

to RO = L see also

Chapter 13.3

2) 3)

Reset Delay Time

t_RD1

1.5

2

2.5

ms

P_15.10.18

Data Sheet

89

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

Table 21

Electrical Specification (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

4.5

Max.

4.75

4.9

VCC2 Monitoring

VCC2 Undervoltage

Threshold Voltage (falling)

V_CC2,UV,f

V_CC2,UV,r

–

V

VCC2 falling

VCC2 rising

–

P_15.10.19

P_15.10.77

P_15.10.20

VCC2 Undervoltage

Threshold Voltage (rising)

4.6

–

V

V_CC2Undervoltage detection V_{CC2,UV, hys}20

100

250

mV

hysteresis

VCAN Monitoring

CAN Supply under voltage

detection threshold

V_{CAN_UV}

4.45

–

4.85

V

CAN Normal

Mode,

P_15.10.23

hysteresis

included;

Watchdog Generator

Long Open Window

Internal Oscillator

3)

t_LW

–

200

1.0

–

ms

P_15.10.24

P_15.10.25

f_CLKSBC

0.8

1.2

MHz

–

Minimum Waiting time during SBC Fail-Safe Mode

Min. waiting time Fail-Safe

Power-on Reset, Over / Under Voltage Protection

3)4)

t_FS,min

–

100

–

ms

P_15.10.75

VS Power on reset rising

VS Power on reset falling

V_POR,r

V_POR,f

–

4.5

3

V

VS increasing

VS decreasing

P_15.10.26

P_15.10.27

P_15.10.13

–

VS Under Voltage Detection V_S,UV

5.3

–

6.0

Supply UV

Threshold

supervision for

VCC1 SC

detection;

hysteresis included

VSHS Over Voltage

Detection Threshold

V_SHS,OVD

20

22

V

Supply OV

supervision for

HSx;

P_15.10.28

hysteresisincluded

5)

VSHS Over Voltage

Detection hysteresis

V_SHS,OVD,hys

V_SHS,UVD

–

500

–

mV

V

P_15.10.29

P_15.10.30

VSHS Under Voltage

Detection Threshold

4.8

5.5

Supply UV

supervision for

HSx, and HS of

GPIOx;

hysteresisincluded

5)

VSHS Under Voltage

Detection hysteresis

V_SHS,UVD,hys

–

200

–

mV

P_15.10.31

Data Sheet

90

Rev. 1.1, 2014-09-26

TLE9260QX

Supervision Functions

Table 21

Electrical Specification (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Over Temperature Shutdown⁵⁾

Thermal Prewarning

Temperature

T_jPW

125

145

165

°C

P_15.10.32

Thermal Shutdown TSD1

Thermal Shutdown TSD2

T_jTSD1

165

–

185

25

200

–

°C

P_15.10.33

P_15.10.34

P_15.10.68

T_jTSD2

Thermal Shutdown

hysteresis

T_jTSD,hys

3)

Deactivation time after

thermal shutdown TSD2

t_TSD2

–

1

–

s

P_15.10.35

1) It is ensured that the threshold V_CC1,OV,ris always higher than the highest regulated V_CC1output voltage V_CC1,out42

.

2) The reset delay time will start when VCC1 crosses above the selected Vrtx threshold

3) Not subject to production test, tolerance defined by internal oscillator tolerance.

4) This time applies for all failure entries except a device thermal shutdown (TSD2 has a typ. 1s waiting time t_TSD2

)

5) Not subject to production test, specified by design.

Data Sheet

91

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14

Serial Peripheral Interface

14.1

SPI Block Description

The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK

provided by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 42).

The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After

the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content.

The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for other

use.The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is shifted

out of the output register after every rising edge on CLK. The SPI of the SBC is not daisy chain capable.

CSN high to low: SDO is enabled. Status information transferred to output shift register

CSN

time

CSN low to high: data from shift register is transferred to output functions

CLK

time

Actual data

New data

0 1

+ +

SDI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

time

SDI: will accept data on the falling edge of CLK signal

Actual status

New status

0

1

+

ERR

SDO

ERR

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

-

+

time

SDO: will change state on the rising edge of CLK signal

Figure 42 SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure

compared to the register description)

Data Sheet

92

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14.2

Failure Signalization in the SPI Data Output

When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI

commands are either invalid SBC mode commands or commands which are prohibited by the state machine to

avoid undesired device or system states (see below). In this case the diagnosis bit ‘SPI_FAIL’ is set and the SPI

Write command is ignored (mostly no partial interpretation). This bit can be only reset by actively clearing it via a

SPI command.

Invalid SPI Commands leading to SPI_FAIL are listed below:

•

Illegal state transitions: Going from SBC Stop to SBC Sleep Mode. In this case the SBC enters in addition the

SBC Restart Mode;

Trying to go to SBC Stop or SBC Sleep mode from SBC Init Mode. In this case SBC Normal Mode is entered;

•

Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored or the new

watchdog settings are ignored respectively;

In SBC Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration, PWM

settings and HS configuration settings during SBC Stop Mode, etc.;

the SPI command is ignored in this case;

only WD trigger, returning to Normal Mode, triggering a SBC Soft Reset, and Read & Clear status registers

commands are valid SPI commands in SBC Stop Mode;

•

When entering SBC Stop Mode and WK_STAT_1 and WK_STAT_2 are not cleared; SPI_FAIL will not be set

but the INT pin will be triggered;

Changing from SBC Stop to Normal Mode and changing the other bits of the M_S_CTRL register. The other

modifications will be ignored;

SBC Sleep Mode: attempt to go to Sleep Mode when all bits in the BUS_CTRL_1 and WK_CTRL_2 registers

are cleared. In this case the SPI_FAIL bit is set and the SBC enters Restart Mode.

Even though the Sleep Mode command is not entered in this case, the rest of the command (e.g modifying

VCC2 ) is executed and the values stay unchanged during SBC Restart Mode;

Note: At least one wake source must be activated in order to avoid a deadlock situation in SBC Sleep Mode,

i.e. the SBC would not be able to wake up anymore.

If the only wake source is a timer and the timer is OFF then the SBC will wake immediately from Sleep Mode

and enter Restart Mode;

No failure handling is done for the attempt to go to SBC STOP Mode when all bits in the registers

BUS_CTRL_1 and WK_CTRL_2 are cleared because the microcontroller can leave this mode via SPI;

•

Attempt to enter SBC Sleep Mode if WK_MEAS is set to ‘1’ and only WK1_EN or WK2_EN are set as wake

sources. Also in this case the SPI_FAIL bit is set and the SBC enters Restart Mode;

•

Setting a longer or equal on-time than the timer period of the respective timer;

SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’;

Note:There is no SPI fail information for unused addresses.

Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 42):

The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set

for following conditions:

•

in case the number of received SPI clocks is not 0 or 16,

in case RO is LOW and SPI frames are being sent at the same time.

Note: In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is not

valid if the CLK is high on a falling edge of CSN

Data Sheet

93

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

The number of received SPI clocks is not 0 or 16:

The number of received input clocks is supervised to be 0- or 16 clock cycles and the input word is discarded in

case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high

during CSN edges. Both errors - 0 bit and 16 bit CLK mismatch or CLK high during CSN edges - are flagged in

the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the clock

is received. The complete SPI command is ignored in this case.

RO is LOW and SPI frames are being sent at the same time:

The ERR flag will be set when the RO pin is triggered (during SBC Restart) and SPI frames are being sent to the

SBC at the same time. The behavior of the ERR flag will be signalized at the next SPI command for below

conditions:

•

if the command begins when RO is HIGH and it ends when RO is LOW,

if a SPI command will be sent while RO is LOW,

If a SPI command begins when RO is LOW and it ends when RO is HIGH.

and the SDO output will behave as follows:

•

always when RO is LOW then SDO will be HIGH,

when a SPI command begins with RO is LOW and ends when RO is HIGH, then the SDO should be ignored

because wrong data will be sent.

Note:It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled low

and SDO is observed - no SPI Clocks are sent in this case

Note:The ERR flag could also be set after the SBC has entered SBC Fail-Safe Mode because the SPI

communication is stopped immediately.

Data Sheet

94

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14.3

SPI Programming

For the TLE9260QX, 7 bits are used or the address selection (BIT6...0). Bit 7 is used to decide between Read

Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the actual

configuration and status information, 8 data bits (BIT15...8) are used.

Writing, clearing and reading is done byte wise. The SPI status bits are not cleared automatically and must be

cleared by the microcontroller, e.g. if the TSD2 was set due to over temperature. The configuration bits will be

partially automatically cleared by the SBC - please refer to the individual registers description for detailed

information. During SBC Restart Mode the SPI communication is ignored by the SBC, i.e. it is not interpreted.

There are two types of SPI registers:

•

Control registers: Those are the registers to configure the SBC, e.g. SBC mode, watchdog trigger, etc

Status registers: Those are the registers where the status of the SBC is signalled, e.g. wake events, warnings,

failures, etc.

For the status registers, the requested information is given in the same SPI command in DO.

For the control registers, also the status of the respective byte is shown in the same SPI command. However, if

the setting is changed this is only shown with the next SPI command (it is only valid after CSN high) of the same

register.

The SBC status information from the SPI status registers, is transmitted in a compressed way with each SPI

response on SDO in the so called Status Information Field register (see also Figure 43). The purpose of this

register is to quickly signal the information to the microcontroller if there was a change in one of the SPI status

registers. In this way, the microcontroller does not need to read constantly all the SPI status registers but only

those registers, which were changed.

Each bit in the Status Information Field represents a SPI status register (see Table 22). As soon as one bit is set

in one of the status registers, then the respective bit in the Status Information Field register will be set. The register

WK_LVL_STAT is not included in the status Information field. This is listed in Table 22.

For Example if bit 0 in the Status Information Field is set to 1, one or more bits of the register 100 0001

(SUP_STAT_1) is set to 1. Then this register needs to be read in a second SPI command. The bit in the Status

Information Field will be set to 0 when all bits in the register 100 0001 are set back to 0.

Table 22

Status Information Field

Bit in Status

Information Field

Corresponding

Address Bit

Status Register Description

0

100 0001

100 0010

100 0011

SUP_STAT_1: Supply Status -VSHS fail, VCCx fail, POR

THERM_STAT: Thermal Protection Status

1

2

DEV_STAT: Device Status - Mode before Wake, WD Fail,

SPI Fail, Failure

3

4

100 0100

100 0110

BUS_STAT: Bus Failure Status: CAN;

WK_STAT_1, WK_STAT_2: Wake Source Status;

Status bit is set as combinational OR of both registers

5

6

7

100 0000

101 0100

101 0101

SUP_STAT_2:VCC1_WARN/OV

HS_OC_OT_STAT: High-Side Over Load Status

HS_OL_STAT: High-Side Open Load Status

Data Sheet

95

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

LSB

MSB

DI

0

1

2

3

4

5

6

7

8

x

9

x

10 11 12 13 14 15

R/W

Address Bits

Data Bits

x

Register content of

selected address

DO

0

1

2

3

4

5

6

7

8

x

9

x

10 11 12 13 14 15

Data Bits

Status Information Field

x

time

LSB is sent first in SPI message

Figure 43 SPI Operation Mode

Data Sheet

96

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14.4

SPI Bit Mapping

The following figures show the mapping of the registers and the SPI bits of the respective registers.

The Control Registers ‘000 0000’ to ‘001 1110’ are Read/Write Register. Depending on bit 7 the bits are only read

(setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting of the bit after write can be seen with a new

read / write command.

The registers ‘100 0000’ to ‘111 1110’ are Status Registers and can be read or read with clearing the bit (if

possible) depending on bit 7. To clear a Data Byte of one of the Status Registers bit 7 must be set to 1. The

registers WK_LVL_STAT, and FAM_PROD_STAT are an exception as they show the actual voltage level at the

respective WK pin (LOW/HIGH), or a fixed family/ product ID respectively and can thus not be cleared. It is

recommended for proper diagnosis to clear respective status bits for wake events or failure. However, in general

it is possible to enable drivers without clearing the respective failure flags.

When changing to a different SBC Mode, certain configurations bits will be cleared automatically or modified:

•

The SBC Mode bits are updated to the actual status, e.g. when returning to Normal Mode

When changing to a low-power mode (Stop/Sleep), the diagnosis bits of the switches and transceivers are not

cleared. FOx will stay activated if it was triggered before.

•

When changing to SBC Stop Mode, the CAN control bits will not be modified.

When changing to SBC Sleep Mode, the CAN control bits will be modified if they were not OFF or wake

capable before.

•

HSx, VCC2 will stay on when going to Sleep-/Stop Mode (configuration can only be done in Normal Mode).

Diagnosis is active (OC, OL, OT). In case of a failure the switch is turned off and no wake-up is issued

The configuration bits for HSx and VCC2 in stand-alone configuration are cleared in SBC Restart Mode. FOx

will stay activated if it was triggered before. Depending on the respective configuration, CAN transceivers will

be either OFF, woken or still wake capable.

Note:The detailed behavior of the respective SPI bits and control functions is described in Chapter 14.5,

Chapter 14.6.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the SBC will

modify respective control bits.

Data Sheet

97

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

MSB

LSB

15 14 13 12 11 10

8 Data Bits [bits 8...15]

9

8

7

6

5

4

3

2

1

0

Reg.

Type

7 Address Bits [bits 0...6]

for Register Selection

0 0 0 0 0 0 1

0 0 0 0 0 1 0

0 0 0 0 0 1 1

0 0 0 0 1 0 0

0 0 0 0 1 0 1

0 0 0 0 1 1 0

0 0 0 0 1 1 1

0 0 0 1 0 0 0

0 0 0 1 0 0 1

0 0 0 1 1 0 0

0 0 0 1 1 0 1

0 0 1 0 0 0 0

0 0 1 0 1 0 0

0 0 1 0 1 0 1

0 0 1 0 1 1 1

0 0 1 1 0 0 0

for Configuration & Status Information

M_S_CTRL

rw

HW_CTRL

WD_CTRL

BUS_CTRL_1

BUS_CTRL_2

WK_CTRL_1

WK_CTRL_2

WK_PUPD_CTRL

WK_FLT_CTRL

TIMER1_CTRL

TIMER2_CTRL

SW_SD_CTRL

HS_CTRL_1

HS_CTRL_2

GPIO_CTRL

PWM1_CTRL

PWM2_CTRL

0 0 1 1 0 0 1

0 0 1 1 1 0 0

0 0 1 1 1 1 0

1 0 0 0 0 0 0

1 0 0 0 0 0 1

PWM_FREQ_CTRL

SYS_STAT_CTRL

SUP_STAT_2

rw

rc

5

0

SUP_STAT_1

rc

THERM_STAT

DEV_STAT

rc

r

1

2

3

4

-

1 0 0 0 0 1 0

1 0 0 0 0 1 1

1 0 0 0 1 0 0

1 0 0 0 1 1 0

1 0 0 0 1 1 1

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 0 1 0 1 0 1

1 1 1 1 1 1 0

BUS_STAT_1

WK_STAT_1

WK_STAT_2

WK_LVL_STAT

HS_OC_OT_STAT

HS_OL_STAT

FAM_PROD_STAT

rc

r

6

7

Figure 44

SPI Register Mapping

Data Sheet

98

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

Figure 45 TLE9260QX SPI Bit Mapping

Data Sheet

99

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14.5

SPI Control Registers

READ/WRITE Operation (see also Chapter 14.3):

•

The ‘POR / Soft Reset Value’ defines the register content after POR or SBC Reset.

The ‘Restart Value’ defines the register content after SBC Restart, where ‘x’ means the bit is unchanged.

One 16-bit SPI command consist of two bytes:

- the 7-bit address and one additional bit for the register access mode and

- following the data byte

The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to the

SPI bits 8...15 (see also figure before).

•

There are three different bit types:

- ‘r’ = READ: read only bits (or reserved bits)

- ‘rw’ = READ/WRITE: readable and writable bits

- ‘rwh’ = READ/WRITE/Hardware: readable/writable bits, which can also be modified by the SBC hardware

Reserved bits are marked as “Reserved” and always read as “0”. The respective bits shall also be programmed

as “0”.

•

Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only).

Writing to a register is done byte wise by setting the SPI bit 7 to “1”.

SPI control bits are in general not cleared or changed automatically. This must be done by the microcontroller

via SPI programming. Exceptions to this behavior are stated at the respective register description and the

respective bit type is marked with a ‘h’ meaning that the SBC is able to change the register content.

The registers are addressed wordwise.

Data Sheet

100

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14.5.1

General Control Registers

M_S_CTRL

Mode- and Supply Control (Address 000 0001_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 0000 00xx_B

7

6

5

4

3

2

1

0

VCC1_OV_RS

T

MODE_1

MODE_0

Reserved

VCC2_ON_1 VCC2_ON_0

VCC1_RT_1 VCC1_RT_0

r

rwh

rw

Field

Bits

Type

Description

MODE

7:6

rwh

SBC Mode Control

00_B, SBC Normal Mode

01_B, SBC Sleep Mode

10_B, SBC Stop Mode

11_B, SBC Reset: Soft Reset is executed (configuration of RO

triggering in bit SOFT_ RESET_RO)

Reserved

VCC2_ON

5

r

Reserved, always reads as 0

4:3

rwh

VCC2 Mode Control

00_B, VCC2 off

01_B, VCC2 on in Normal Mode

10_B, VCC2 on in Normal and Stop Mode

11_B, VCC2 always on (except in SBC Fail-Safe Mode)

VCC1_OV_R 2

ST

rwh

rw

VCC1 Over Voltage leading to Restart / Fail-Safe Mode enable

0_B

, VCC1_ OV is set in case of VCC1_OV; no SBC Restart or Fail-

Safe is entered for VCC1_OV

1_B

, VCC1_ OV is set in case of VCC1_OV; depending on the

device configuration SBC Restart or SBC Fail-Safe Mode is

entered (see Chapter 5.1.1);

VCC1_RT

1:0

VCC1 Reset Threshold Control

00_B, Vrt1 selected (highest threshold)

01_B, Vrt2 selected

10_B, Vrt3 selected

11_B, Vrt4 selected

Notes

1. It is not possible to change from Stop to Sleep Mode via SPI Command. See also the State Machine Chapter

2. After entering SBC Restart Mode, the MODE bits will be automatically set to SBC Normal Mode. The

VCC2_ON bits will be automatically set to OFF after entering SBC Restart Mode and after OT.

3. The SPI output will always show the previously written state with a Write Command (what has been

programmed before)

Data Sheet

101

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

HW_CTRL

Mode- and Supply Control (Address 000 0010_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0x00 000x_B

7

6

5

4

3

2

1

0

SOFT_RESET

_RO

Reserved

FO_ON

Reserved

CFG

r

rw

rwh

r

rw

Field

Bits

7

Type

Description

Reserved

r

Reserved, always reads as 0

SOFT_

6

rw

Soft Reset Configuration

RESET_RO

0_B

1_B

, RO will be triggered (pulled low) during a Soft Reset

, No RO triggering during a Soft Reset

FO_ON

5

rwh

Failure Output Activation (FO1..3)

0_B

, FOx not activated by software, FO can be activated by defined

failures (see Chapter 12)

1_B

, FOx activated by software (via SPI)

Reserved

CFG

4

3

2

1

0

r

Reserved, always reads as 0

Configuration Select (see also Table 5)

r

rw

0_B

, Depending on hardware configuration, SBC Restart or Fail-

Safe Mode is reached after the 2. watchdog trigger failure

(=default) - Config 3/4

1_B

, Depending on hardware configuration, SBC Restart or Fail-

Safe Mode is reached after the 1. watchdog trigger failure -

Config 1/2

Notes

1. Clearing the FO_ON bit will not disable the FOx outputs for the case a failure occurred which triggered the FOx

outputs. In this case the FOx outputs have to be disabled by clearing the FAILURE bit.

If the FO_ON bit is set by the software then it will be cleared by the SBC after SBC Restart Mode was entered

and the FOx outputs will be disabled. See also Chapter 12 for FOx activation and deactivation.

Data Sheet

102

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

WD_CTRL

Watchdog Control (Address 000 0011_B)

POR / Soft Reset Value: 0001 0100_B;

Restart Value: x0xx 0100_B

7

6

5

4

3

2

1

0

WD_STM_

EN_0

WD_EN_

WK_BUS

CHECKSUM

WD_WIN

Reserved WD_TIMER_2 WD_TIMER_1 WD_TIMER_0

r

rw

rwh

rw

r

rwh

Field

Bits

Type

Description

CHECKSUM 7

rw

Watchdog Setting Check Sum Bit

The sum of bits 7:0 needs to have even parity (see Chapter 13.2.3)

0_B

1_B

, Counts as 0 for checksum calculation

, Counts as 1 for checksum calculation

WD_STM_

EN_0

6

5

4

3

rwh

rw

Watchdog Deactivation during Stop Mode, bit 0 (Chapter 13.2.4)

0_B

1_B

, Watchdog is active in Stop Mode

, Watchdog is deactivated in Stop Mode

WD_WIN

Watchdog Type Selection

0_B

1_B

, Watchdog works as a Time-Out watchdog

, Watchdog works as a Window watchdog

WD_EN_

WK_BUS

rwh

Watchdog Enable after Bus (CAN) Wake in SBC Stop Mode

0_B

1_B

, Watchdog will not start after a CAN wake

, Watchdog starts with a long open window after CAN Wake

Reserved

r

Reserved, always reads as 0

WD_TIMER 2:0

rwh

Watchdog Timer Period

000_B, 10ms

001_B, 20ms

010_B, 50ms

011_B, 100ms

100_B, 200ms

101_B, 500ms

110_B, 1000ms

111_B, reserved

Notes

1. See also Chapter 13.2.4 for more information on disabling the watchdog in SBC Stop Mode.

2. See Chapter 13.2.5 for more information on the effect of the bit WD_EN_WK_BUS.

3. See Chapter 13.2.3 for calculation of checksum.

Data Sheet

103

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

BUS_CTRL_1

Bus Control (Address 000 0100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 00yy_B

7

6

5

4

3

2

1

0

Reserved

CAN_1

CAN_0

r

rwh

Field

Bits

Type

Description

Reserved

CAN

7:3

2

r

Reserved, always reads as 0

r

1:0

rwh

HS-CAN Module Modes

00_B, CAN OFF

01_B, CAN is wake capable

10_B, CAN Receive Only Mode

11_B, CAN Normal Mode

Notes

1. The reset values for the CAN transceivers are marked with ‘y’ because they will vary depending on the cause

of change - see below.

2. see Figure 19 for detailed state changes of CAN Transceiver for different SBC modes.

3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),

then the wake registers BUS_CTRL_1, and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0

1001’, ‘0000 0001’ and ‘x0xx 0111’ in order to ensure that the device can be woken again.

Data Sheet

104

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

BUS_CTRL_2

Bus Control (Address 000 0101_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 00x0 0000_B

7

6

5

4

3

2

1

0

Reserved

I_PEAK_TH

Reserved

r

rw

r

Field

Bits

Type

Description

Reserved

7:6

5

r

Reserved, always reads as 0

VCC1 Active Peak Threshold Selection

I_PEAK_TH

rw

0_B

1_B

, low VCC1 active peak threshold selected (ICC1,peak_1)

, higher VCC1 active peak threshold selected (ICC1,peak_2)

Reserved

4:0

r

Reserved, always reads as 0

Notes

1. The bit I_PEAK_TH can be modified in SBC Init and Normal Mode. In SBC Stop Mode this bit is Read only but

SPI_FAIL will not be set when trying to modify the bit in SBC STOP Mode and no INT is triggered in case INT_

GLOBAL is set.

2. see Figure 19 for detailed state changes of CAN Transceiver for different SBC modes

3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),

then the wake registers BUS_CTRL_1, BUS_CTRL_2 and WK_CTRL_2 are reset to following values (=wake

sources) ‘xxx0 1001’, ‘0000 0001’ and ‘x0xx 0111’ in order to ensure that the device can be woken again.

Data Sheet

105

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

WK_CTRL_1

Internal Wake Input Control (Address 000 0110_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xx00 0000_B

7

6

5

4

3

2

1

0

TIMER2_WK_ TIMER1_WK_

WD_STM_

EN_1

Reserved

EN

r

rw

r

rwh

r

Field

Bits

Type

Description

TIMER2_WK 7

rw

Timer2 Wake Source Control (for cyclic wake)

_EN

0_B

1_B

, Timer2 wake disabled

, Timer2 is enabled as a wake source

TIMER1_WK 6

rw

Timer1 Wake Source Control (for cyclic wake)

_EN

0_B

1_B

, Timer1 wake disabled

, Timer1 is enabled as a wake source

Reserved

5:3

r

Reserved, always reads as 0

Watchdog Deactivation during Stop Mode, bit 1 (Chapter 13.2.4)

WD_STM_

EN_1

2

rwh

0_B

1_B

, Watchdog is active in Stop Mode

, Watchdog is deactivated in Stop Mode

Reserved

1:0

r

Reserved, always reads as 0

Data Sheet

106

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

WK_CTRL_2

External Wake Source Control (Address 000 0111_B)

POR / Soft Reset Value: 0000 0111_B;

Restart Value: x0x0 0xxx_B

7

6

5

4

3

2

1

0

INT_GLOBAL Reserved

WK_MEAS

Reserved

WK3_EN

WK2_EN

WK1_EN

w

r

rw

r

rw

r

rw

Field

INT_

Bits

Type

Description

7

rw

Global Interrupt Configuration (see also Chapter 11.1)

GLOBAL

0_B

1_B

, Only wake sources trigger INT (default)

, All status information register bits will trigger INT (including all

wake sources)

Reserved

6

5

r

Reserved, always reads as 0

WK_MEAS

rw

WK / Measurement selection (see also Chapter 10.2.2)

0_B

1_B

, WK functionality enabled for WK1 and WK2

, Measurement functionality enabled; WK1 & WK2 are disabled

as wake sources, i.e. bits WK1/2_EN bits are ignored

Reserved

WK3_EN

4:3

2

r

Reserved, always reads as 0

rw

WK3 Wake Source Control

0_B

1_B

, WK3 wake disabled

, WK3 is enabled as a wake source

WK2_EN

WK1_EN

1

0

rw

WK2 Wake Source Control

0_B

1_B

, WK2 wake disabled

, WK2 is enabled as a wake source

WK1 Wake Source Control

0_B

1_B

, WK1 wake disabled

, WK1 is enabled as a wake source

Notes

1. WK_MEAS is by default configured for standard WK functionality (WK1 and WK2). The bits WK1_EN and

WK2_EN are ignored in case WK_MEAS is activated. If the bit is set to ‘1’ then the measurement function is

enabled during Normal Mode & the bits WK1_EN and WK2_EN are ignored. The bits WK1/”_LVL bits need to

be ignored as well.

2. The wake sources CAN are selected in the register BUS_CTRL_1 by setting the respective bits to ‘wake

capable’

3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),

then the wake registers BUS_CTRL_1 and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0

1001’, ‘0000 0001’ and ‘x0xx 0111’ in order to ensure that the device can be woken again.

Data Sheet

107

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

WK_PUPD_CTRL

Wake Input Level Control (Address 000 1000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 00xx xxxx_B

7

6

5

4

3

2

1

0

Reserved

Reserved WK3_PUPD_1 WK3_PUPD_0 WK2_PUPD_1 WK2_PUPD_0 WK1_PUPD_1 WK1_PUPD_0

r

rw

Field

Reserved

Bits

Type

Description

7:6

r

Reserved, always reads as 0

WK3_PUPD 5:4

WK2_PUPD 3:2

WK1_PUPD 1:0

rw

WK3 Pull-Up / Pull-Down Configuration

00_B, No pull-up / pull-down selected

01_B, Pull-down resistor selected

10_B, Pull-up resistor selected

11_B, Automatic switching to pull-up or pull-down

rw

WK2 Pull-Up / Pull-Down Configuration

00_B, No pull-up / pull-down selected

01_B, Pull-down resistor selected

10_B, Pull-up resistor selected

11_B, Automatic switching to pull-up or pull-down

WK1 Pull-Up / Pull-Down Configuration

00_B, No pull-up / pull-down selected

01_B, Pull-down resistor selected

10_B, Pull-up resistor selected

11_B, Automatic switching to pull-up or pull-down

Data Sheet

108

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

WK_FLT_CTRL

Wake Input Filter Time Control (Address 000 1001_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 00xx xxxx_B

7

6

5

4

3

2

1

0

Reserved

WK3_FLT_1 WK3_FLT_0 WK2_FLT_1 WK2_FLT_0 WK1_FLT_1 WK1_FLT_0

r

rw

Field

Bits

Type

Description

Reserved

WK3_FLT

7:6

5:4

r

Reserved, always reads as 0

rw

WK3 Filter Time Configuration

00_B, Configuration A: Filter with 16µs filter time (static sensing)

01_B, Configuration B: Filter with 64µs filter time (static sensing)

10_B, Configuration C: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer1

11_B, Configuration D: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer2

WK2_FLT

WK1_FLT

3:2

1:0

rw

WK2 Filter Time Configuration

00_B, Configuration A: Filter with 16µs filter time (static sensing)

01_B, Configuration B: Filter with 64µs filter time (static sensing)

10_B, Configuration C: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer1

11_B, Configuration D: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer2

WK1 Filter Time Configuration

00_B, Configuration A: Filter with 16µs filter time (static sensing)

01_B, Configuration B: Filter with 64µs filter time (static sensing)

10_B, Configuration C: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer1

11_B, Configuration D: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer2

Note:When selecting a filter time configuration, the user must make sure to also assign the respective timer to at

least one HS switch during cyclic sense operation

Data Sheet

109

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

TIMER1_CTRL

Timer1 Control and Selection (Address 000 1100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0000_B

7

6

5

4

3

2

1

0

TIMER1_

ON_2

TIMER1_

ON_1

TIMER1_

ON_0

TIMER1_

PER_2

TIMER1_

PER_1

TIMER1_

PER_0

Reserved

r

rwh

r

rwh

Field

Bits

Type

Description

Reserved

7

r

Reserved, always reads as 0

TIMER1_

ON

6:4

rwh

Timer1 On-Time Configuration

000_B, OFF / Low (timer not running, HSx output is low)

001_B, 0.1ms on-time

010_B, 0.3ms on-time

011_B, 1.0ms on-time

100_B, 10ms on-time

101_B, 20ms on-time

110_B, OFF / HIGH (timer not running, HSx output is high)

111_B, reserved

Reserved

3

r

Reserved, always reads as 0

TIMER1_

PER

2:0

rwh

Timer1 Period Configuration

000_B, 10ms

001_B, 20ms

010_B, 50ms

011_B, 100ms

100_B, 200ms

101_B, 1s

110_B, 2s

111_B, reserved

Notes

1. A timer must be first assigned and is then automatically activated as soon as the on-time is configured.

2. If cyclic sense is selected and the HS switches are cleared during SBC Restart Mode, then also the timer

settings (period and on-time) are cleared to avoid incorrect switch detection.

3. in case the timer are set as wake sources and cyclic sense is running, then both cyclic sense and cyclic wake

will be active at the same time.

Data Sheet

110

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

TIMER2_CTRL

Timer2 Control and selection (Address 000 1101_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0000_B

7

6

5

4

3

2

1

0

TIMER2_

ON_2

TIMER2_

ON_1

TIMER2_

ON_0

TIMER2_

PER_2

TIMER2_

PER_1

TIMER2_

PER_0

Reserved

r

rwh

r

rwh

Field

Bits

Type

Description

Reserved

7

r

Reserved, always reads as 0

TIMER2_

ON

6:4

rwh

Timer2 On-Time Configuration

000_B, OFF / Low (timer not running, HSx output is low)

001_B, 0.1ms on-time

010_B, 0.3ms on-time

011_B, 1.0ms on-time

100_B, 10ms on-time

101_B, 20ms on-time

110_B, OFF / HIGH (timer not running, HSx output is high)

111_B, reserved

Reserved

3

r

Reserved, always reads as 0

TIMER2_

PER

2:0

rwh

Timer2 Period Configuration

000_B, 10ms

001_B, 20ms

010_B, 50ms

011_B, 100ms

100_B, 200ms

101_B, 1s

110_B, 2s

111_B, reserved

Notes

1. A timer must be first assigned and is then automatically activated as soon as the on-time is configured.

2. If cyclic sense is selected and the HS switches are cleared during SBC Restart Mode, then also the timer

settings (period and on-time) are cleared to avoid incorrect switch detection.

Data Sheet

111

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

SW_SD_CTRL

Switch Shutdown Control (Address 001 0000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0xxx 0000_B

7

6

5

4

3

2

1

0

HS_OV_SD_E HS_UV_SD_E HS_OV_UV_R

Reserved

N

EC

r

rw

r

Field

Reserved

Bits

Type

Description

7

r

Reserved, always reads as 0

HS_OV_SD_ 6

rw

Shutdown Disabling of HS1...4 in case of VSHS OV

EN

0_B

1_B

, shutdown enabled in case of VSHS OV

, shutdown disabled in case of VSHS OV

HS_UV_SD_ 5

EN

rw

Shutdown Disabling of HS1...4 in case of VSHS UV

0_B

1_B

, shutdown enabled in case of VSHS UV

, shutdown disabled in case of VSHS UV

HS_OV_UV_ 4

Switch Recovery after Removal of VSHS OV/UV for HS1...4

REC

0_B

1_B

, Switch recovery is disabled

, Previous state before VSHS OV/UV is enabled after OV/UV

condition is removed

Reserved

3:0

r

Reserved, always reads as 0

Data Sheet

112

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

HS_CTRL1

High-Side Switch Control 1 (Address 001 0100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0000_B

7

6

5

4

3

2

1

0

Reserved

HS2_2

HS2_1

HS2_0

Reserved

HS1_2

HS1_1

HS1_0

r

rw

rwh

r

rwh

Field

Bits

Type

Description

Reserved

HS2

7

r

Reserved, always reads as 0

6:4

rwh

HS2 Configuration

000_B, Off

001_B, On

010_B, Controlled by Timer1

011_B, Controlled by Timer2

100_B, Controlled by PWM1

101_B, Controlled by PWM2

110_B, Reserved

111_B, Reserved

Reserved

HS1

3

r

Reserved, always reads as 0

2:0

rwh

HS1 Configuration

000_B, Off

001_B, On

010_B, Controlled by Timer1

011_B, Controlled by Timer2

100_B, Controlled by PWM1

101_B, Controlled by PWM2

110_B, Reserved

111_B, Reserved

Note:The bits for the switches are also reset in case of overcurrent and overtemperature.

Data Sheet

113

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

HS_CTRL2

High-Side Switch Control 2 (Address 001 0101_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0000_B

7

6

5

4

3

2

1

0

Reserved

HS4_2

HS4_1

HS4_0

Reserved

HS3_2

HS3_1

HS3_0

r

rwh

r

rwh

Field

Bits

Type

Description

Reserved

HS4

7

r

Reserved, always reads as 0

6:4

rwh

HS4 Configuration

000_B, Off

001_B, On

010_B, Controlled by Timer1

011_B, Controlled by Timer2

100_B, Controlled by PWM1

101_B, Controlled by PWM2

110_B, Reserved

111_B, Reserved

Reserved

HS3

3

r

Reserved, always reads as 0

2:0

rwh

HS3 Configuration

000_B, Off

001_B, On

010_B, Controlled by Timer1

011_B, Controlled by Timer2

100_B, Controlled by PWM1

101_B, Controlled by PWM2

110_B, Reserved

111_B, Reserved

Note:The bits for the switches are also reset in case of overcurrent and overtemperature.

Data Sheet

114

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

GPIO_CTRL

GPIO Configuration Control (Address 001 0111_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

FO_DC_1

FO_DC_0

GPIO2_2

GPIO2_1

GPIO2_0

GPIO1_2

GPIO1_1

GPIO1_0

r

rw

Field

Bits

Type

Description

FO_DC

7:6

rw

Duty Cycle Configuration of FO3 (if selected)

00_B, 20%

01_B, 10%

10_B, 5%

11_B, 2.5%

GPIO2

5:3

rw

GPIO2 Configuration

000_B, FO3 selected

001_B, FO3 selected

010_B, FO3 selected

011_B, FO3 selected

100_B, OFF

101_B, Wake input enabled (16µs static filter)

110_B, Low-Side Switch ON

111_B, High-Side Switch ON

GPIO1

2:0

rw

GPIO1 Configuration

000_B, FO2 selected

001_B, FO2 selected

010_B, FO2 selected

011_B, FO2 selected

100_B, OFF

101_B, Wake input enabled (16µs static filter)

110_B, Low-Side Switch ON

111_B, High-Side Switch ON

Note:When selecting a filter time configuration, the user must make sure to also assign the respective timer to at

least one HS switch during cyclic sense operation

Data Sheet

115

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

PWM1_CTRL

PWM1 Configuration Control (Address 001 1000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

PWM1_DC_7 PWM1_DC_6 PWM1_DC_5 PWM1_DC_4 PWM1_DC_3 PWM1_DC_2 PWM1_DC_1 PWM1_DC_0

r

rw

Field

PWM1_DC

Bits

Type

rw

Description

7:0

PWM1 Duty Cycle (bit0=LSB; bit7=MSB)

0000 0000_B, 100% OFF

xxxx xxxx _B, ON with DC fraction of 255

1111 1111_B, 100% ON

Note:The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g.

the PWM setting ‘000 0001’ could not be realized.

PWM2_CTRL

PWM2 Configuration Control (Address 001 1001_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

PWM2_DC_7 PWM2_DC_6 PWM2_DC_5 PWM2_DC_4 PWM2_DC_3 PWM2_DC_2 PWM2_DC_1 PWM2_DC_0

r

rw

Field

PWM2_DC

Bits

Type

rw

Description

7:0

PWM2 Duty Cycle (bit0=LSB; bit7=MSB)

0000 0000_B, 100% OFF

xxxx xxxx_B, ON with DC fraction of 255

1111 1111_B, 100% ON

Note:The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g.

the PWM setting ‘000 0001’ could not be realized.

Data Sheet

116

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

PWM_FREQ_CTRL

PWM Frequency Configuration Control (Address 001 1100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0x0x_B

7

6

5

4

3

2

1

0

Reserved

Reserved PWM2_FREQ Reserved PWM1_FREQ

r

rw

r

rw

Field

Bits

Type

Description

Reserved

7:3

2

r

Reserved, always reads as 0

PWM2_

FREQ

rw

PWM2 Frequency Selection

0_B

1_B

, 200Hz configuration

, 400Hz configuration

Reserved

1

0

r

Reserved, always reads as 0

PWM1_

FREQ

rw

PWM1 Frequency Selection

0_B

1_B

, 200Hz configuration

, 400Hz configuration

Note:The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g.

the PWM setting ‘000 0001’ could not be realized.

SYS_STATUS_CTRL

System Status Control (Address 001 1110_B)

POR Value: 0000 0000_B;

Restart Value/Soft Reset Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

SYS_STAT_7 SYS_STAT_6 SYS_STAT_5 SYS_STAT_4 SYS_STAT_3 SYS_STAT_2 SYS_STAT_1 SYS_STAT_0

r

rw

Field

Bits

Type

rw

Description

SYS_STAT 7:0

System Status Control Byte (bit0=LSB; bit7=MSB)

Dedicated byte for system configuration, access only by

microcontroller. Cleared after power up and Soft Reset

Notes

1. The SYS_STATUS_CTRL register is an exception for the default values, i.e. it will keep its configured value

also after a Soft Reset.

2. This byte is intended for storing system configurations of the ECU by the microcontroller and is only accessible

in SBC Normal Mode. The byte is not accessible by the SBC and is also not cleared after Fail-Safe or SBC

Restart Mode. It allows the microcontroller to quickly store system configuration without loosing the data.

Data Sheet

117

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14.6

SPI Status Information Registers

READ/CLEAR Operation (see also Chapter 14.3):

•

One 16-bit SPI command consist of two bytes:

- the 7-bit address and one additional bit for the register access mode and

- following the data byte

The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to the

SPI bits 8...15 (see also figure).

•

There are two different bit types:

- ‘r’ = READ: read only bits (or reserved bits)

- ‘rc’ = READ/CLEAR: readable and clearable bits

•

Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only)

Clearing a register is done byte wise by setting the SPI bit 7 to “1”

SPI status registers are in general not cleared or changed automatically (an exception are the WD_FAIL bits).

This must be done by the microcontroller via SPI command

The registers are addressed wordwise.

Data Sheet

118

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14.6.1

General Status Registers

SUP_STAT_2

Supply Voltage Fail Status (Address 100 0000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0x00 00xx_B

7

6

5

4

3

2

1

0

Reserved

VS_UV

Reserved

VCC1_OV VCC1_WARN

rc rc

r

rc

r

Field

Bits

Type

Description

Reserved

VS_UV

7

6

r

Reserved, always reads as 0

rc

VS Under-Voltage Detection (V_S,UV)

0_B

1_B

, No VS under voltage detected

, VS under voltage detected

Reserved

5

r

Reserved, always reads as 0

4:2

1

r

VCC1_

OV

rc

VCC1 Over Voltage Detection (V_CC1,OV,r)

0_B

1_B

, No VCC1 over voltage warning

, VCC1 over voltage detected

VCC1_

WARN

0

rc

VCC1 Undervoltage Prewarning (V_PW,f)

0_B

1_B

, No VCC1 undervoltage prewarning

, VCC1 undervoltage prewarning detected

Notes

1. The VCC1 undervoltage prewarning threshold V_PW,f/ V_PW,ris a fixed threshold and independent of the VCC1

undervoltage reset thresholds.

Data Sheet

119

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

SUP_STAT_1

Supply Voltage Fail Status (Address 100 0001_B)

POR / Soft Reset Value: y000 0000_B;

Restart Value: xxxx xx0x_B

7

6

5

4

3

2

1

0

POR

VSHS_UV

VSHS_OV

VCC2_OT

VCC2_UV

VCC1_SC VCC1_UV_FS VCC1_UV

r

rc

Field

Bits

Type

Description

POR

7

6

5

4

3

2

1

0

rc

Power-On Reset Detection

0_B

1_B

, No POR

, POR occurred

VSHS_UV

VSHS_OV

VCC2_OT

VCC2_UV

VCC1_SC

rc

VSHS Under-Voltage Detection (V_SHS,UVD)

0_B

1_B

, No VSHS-UV

, VSHS-UV detected

VSHS Over-Voltage Detection (V_SHS,OVD

)

0_B

1_B

, No VSHS-OV

, VSHS-OV detected

VCC2 Over Temperature Detection

0_B

1_B

, No over temperature

, VCC2 over temperature detected

VCC2 Under Voltage Detection (V_CC2,UV,f

)

0_B

1_B

, No VCC2 Under voltage

, VCC2 under voltage detected

VCC1 Short to GND Detection (<Vrtx for t>4ms after switch on)

0_B

1_B

, No short

, VCC1 short to GND detected

VCC1_UV

_FS

VCC1 UV-Detection (due to Vrtx reset)

0_B

1_B

, No Fail-Safe Mode entry due to 4th consecutive VCC1_UV

, Fail-Safe Mode entry due to 4th consecutive VCC1_UV

VCC1_UV

VCC1 UV-Detection (due to Vrtx reset)

0_B

1_B

, No VCC1_UV detection

, VCC1 UV-Fail detected

Notes

1. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on

reset (POR value = 1000 0000). However it will be cleared after a SBC Soft Reset command (Soft Reset value

= 0000 0000).

2. During Sleep Mode, the bits VCC1_SC,VCC1_OV and VCC1_UV will not be set when VCC1 is off

3. The VCC1_UV bit is never updated in SBC Restart Mode, in SBC Init Mode it is only updated after RO was

released for the first time, it is always updated in SBC Normal and Stop Mode, and it is always updated in any

SBC modes in a VCC1_SC condition (after VCC1_UV = 1 for >4ms).

Data Sheet

120

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

THERM_STAT

Thermal Protection Status (Address 100 0010_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0xxx_B

7

6

5

4

3

2

1

0

Reserved

TSD2

TSD1

TPW

r

rc

Field

Bits

Type

Description

Reserved

TSD2

7:3

2

r

Reserved, always reads as 0

rc

TSD2 Thermal Shut-Down Detection

0_B

1_B

, No TSD2 event

, TSD2 OT detected - leading to SBC Fail-Safe Mode

TSD1

TPW

1

0

rc

TSD1 Thermal Shut-Down Detection

0_B

1_B

, No TSD1 fail

, TSD1 OT detected

Thermal Pre Warning

0_B

1_B

, No Thermal Pre warning

, Thermal Pre warning detected

Note:TSD1 and TSD2 are not reset automatically, even if the temperature pre warning or TSD1 OT condition is

not present anymore. Also TSD2 is not reset.

Data Sheet

121

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

DEV_STAT

Device Information Status (Address 100 0011_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xx00 xxxx_B

7

6

5

4

3

2

1

0

DEV_STAT_1 DEV_STAT_0 Reserved

rc rc

Reserved

WD_FAIL_1 WD_FAIL_0

rh rh

SPI_FAIL

FAILURE

r

rc

Field

Bits

Type

Description

DEV_STAT 7:6

rc

Device Status before Restart Mode

00_B, Cleared (Register must be actively cleared)

01_B, Restart due to failure (WD fail, TSD2, VCC1_UV); also after a

wake from Fail-Safe Mode

10_B, Sleep Mode

11_B, Reserved

Reserved

WD_FAIL

5:4

3:2

r

Reserved, always reads as 0

rh

Number of WD-Failure Events (1/2 WD failures depending on

CFG)

00_B, No WD Fail

01_B, 1x WD Fail, FOx activation - Config 2 selected

10_B, 2x WD Fail, FOx activation - Config 1 / 3 / 4 selected

11_B, Reserved (never reached)

SPI_FAIL

FAILURE

1

0

rc

SPI Fail Information

0_B

1_B

, No SPI fail

, Invalid SPI command detected

Activation of Fail Output FO

0_B

1_B

, No Failure

, Failure occurred

Notes

1. The bits DEV_STAT show the status of the device before it went through Restart. Either the device came from

regular Sleep Mode (‘10’) or a failure (‘01’ - SBC Restart or SBC Fail-Safe Mode: WD fail, TSD2 fail, VCC_UV

fail or VCC1_OV if bit VCC1_OV_RST is set) occurred. Failure is also an illegal command from SBC Stop to

SBC Sleep Mode or going to SBC Sleep Mode without activation of any wake source. Coming from SBC Sleep

Mode (‘10’) will also be shown if there was a trial to enter SBC Sleep Mode without having cleared all wake

flags before.

2. The WD_FAIL bits are configured as a counter and are the only status bits, which are cleared automatically

by the SBC. They are cleared after a successful watchdog trigger and when the watchdog is stopped (also in

SBC Sleep and Fail-Safe Mode unless it was reached due to a watchdog failure). See also Chapter 12.1.

3. The SPI_FAIL bit is cleared only by SPI command

4. In case of Config 2/4 the WD_Fail counter is frozen in case of WD trigger failure until a successful WD trigger.

5. If CFG = ‘0’ then a 1st watchdog failure will not trigger the FO outputs or the FAILURE bit but only force the

SBC into SBC Restart Mode.

Data Sheet

122

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

BUS_STAT_1

Bus Communication Status (Address 100 0100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0xxx_B

7

6

5

4

3

2

1

0

Reserved

CAN_FAIL_1 CAN_FAIL_0 VCAN_UV

r

rc

Field

Bits

Type

Description

Reserved

CAN_FAIL

7

r

Reserved, always reads as 0

6:5

4:3

2:1

r

rc

CAN Failure Status

00_B, No error

01_B, CAN TSD

10_B, CAN_TXD_DOM: TXD dominant time out for more than 4ms

11_B, CAN_BUS_DOM: BUS dominant time out for more than 4ms

VCAN_UV

0

rc

Under Voltage CAN Bus Supply

0_B

1_B

, Normal operation

, CAN Supply under voltage detected. Transmitter disabled

Notes

1. The VCAN_UV comparator is enabled if the mode bit CAN_1 = ‘1’, i.e. in CAN Normal or CAN Receive Only

Mode.

Data Sheet

123

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

WK_STAT_1

Wake-up Source and Information Status (Address 100 0110_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 00xx 0xxx_B

7

6

5

4

3

2

1

0

Reserved

CAN_WU

TIMER_WU

Reserved

WK3_WU

WK2_WU

WK1_WU

r

rc

r

rc

Field

Bits

Type

Description

Reserved

CAN_WU

7

6

5

r

Reserved, always reads as 0

Wake up via CAN Bus

r

rc

0_B

1_B

, No Wake up

, Wake up

TIMER_WU

4

rc

Wake up via TimerX

0_B

1_B

, No Wake up

, Wake up

Reserved

WK3_WU

3

2

r

Reserved, always reads as 0

rc

Wake up via WK3

0_B

1_B

, No Wake up

, Wake up

WK2_WU

WK1_WU

1

0

rc

Wake up via WK2

0_B

1_B

, No Wake up

, Wake up

Wake up via WK1

0_B

1_B

, No Wake up

, Wake up

Note:The respective wake source bit will also be set when the device is woken from SBC Fail-Safe Mode

Data Sheet

124

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

WK_STAT_2

Wake-up Source and Information Status (Address 100 0111_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 00xx 0000_B

7

6

5

4

3

2

1

0

Reserved

GPIO2_WU

GPIO1_WU

Reserved

r

rc

r

Field

Bits

Type

Description

Reserved

7:6

5

r

Reserved, always reads as 0

GPIO2_WU

rc

Wake up via GPIO2

0_B

1_B

, No Wake up

, Wake up

GPIO1_WU

Reserved

4

rc

r

Wake up via GPIO1

0_B

1_B

, No Wake up

, Wake up

3:0

Reserved, always reads as 0

Data Sheet

125

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

WK_LVL_STAT

WK Input Level (Address 100 1000_B)

POR / Soft Reset Value: xx00 0xxx_B;

Restart Value: xxxx 0xxx_B

7

6

5

4

3

2

1

0

SBC_DEV

_LVL

CFGP

GPIO2_LVL GPIO1_LVL

Reserved

WK3_LVL

WK2_LVL

WK1_LVL

r

Field

Bits

Type

Description

SBC_DEV

_LVL

7

6

5

4

r

Status of SBC Operating Mode at FO3/TEST Pin

0_B

1_B

, User Mode activated

, SBC Software Development Mode activated

CFGP

r

Device Configuration Status

0_B

1_B

, No external pull-up resistor connected on INT (Config 2/4)

, External pull-up resistor connected on INT (Config 1/3)

GPIO2_LVL

GPIO1_LVL

Status of GPIO2 (if selected as GPIO)

0_B

1_B

, Low Level (=0)

, High Level (=1)

Status of GPIO1 (if selected as GPIO)

0_B

1_B

, Low Level (=0)

, High Level (=1)

Reserved

WK3_LVL

3

2

r

Reserved, always reads as 0

Status of WK3

0_B

1_B

, Low Level (=0)

, High Level (=1)

WK2_LVL

WK1_LVL

1

0

r

Status of WK2

0_B

1_B

, Low Level (=0)

, High Level (=1)

Status of WK1

0_B

1_B

, Low Level (=0)

, High Level (=1)

Note:GPIOx_LVL is updated in SBC Normal and Stop Mode if configured as wake input, low-side switch or high-

side switch.

In cyclic sense or wake mode, the registers contain the sampled level, i.e. the registers are updated after

every sampling. The GPIOs are not capable of cyclic sensing.

If selected as GPIO then the respective level is shown even if configured as low-side or high-side.

Data Sheet

126

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

HS_OC_OT_STAT

High-Side Switch Overload Status (Address 101 0100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 xxxx_B

7

6

5

4

3

2

1

0

Reserved

HS4_OC_OT HS3_OC_OT HS2_OC_OT HS1_OC_OT

r

rc

Field

Reserved

Bits

7:4

Type

Description

r

Reserved, always reads as 0

HS4_OC_OT 3

HS3_OC_OT 2

HS2_OC_OT 1

HS1_OC_OT 0

rc

Over-Current & Over-Temperature Detection HS4

0_B

1_B

, No OC or OT

, OC or OT detected

rc

Over-Current & Over-Temperature Detection HS3

0_B

1_B

, No OC or OT

, OC or OT detected

Over-Current & Over-Temperature Detection HS2

0_B

1_B

, No OC or OT

, OC or OT detected

Over-Current & Over-Temperature Detection HS1

0_B

1_B

, No OC or OT

, OC or OT detected

Note:The OC/OT bit might be set for V_POR,f< VS < 5.5V (see also Chapter 4.2)

Data Sheet

127

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

HS_OL_STAT

High-Side Switch Open-Load Status (Address 101 0101_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 xxxx_B

7

6

5

4

3

2

1

0

Reserved

HS4_OL

HS3_OL

HS2_OL

HS1_OL

r

rc

Field

Bits

Type

Description

Reserved

HS4_OL

7:4

3

r

Reserved, always reads as 0

rc

Open-Load Detection HS4

0_B

1_B

, No OL

, OL detected

HS3_OL

HS2_OL

HS1_OL

2

1

0

rc

Open-Load Detection HS3

0_B

1_B

, No OL

, OL detected

Open-Load Detection HS2

0_B

1_B

, No OL

, OL detected

Open-Load Detection HS1

0_B

1_B

, No OL

, OL detected

Data Sheet

128

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14.6.2

Family and Product Information Register

FAM_PROD_STAT

Family and Product Identification Register (Address 111 1110_B)

POR / Soft Reset Value: 0011 yyyy _B; Restart Value: 0011 yyyy_B

7

6

5

4

3

2

1

0

FAM_3

FAM_2

FAM_1

FAM_0

PROD_3

PROD_2

PROD_1

PROD_0

r

Field

Bits

Type

Description

FAM

7:4

r

SBC Family Identifier (bit4=LSB; bit7=MSB)

0 0 01_B, Driver SBC Family

0 0 10_B, DC/DC-SBC Family

0 0 11_B, Mid-Range SBC Family

x x x x_B, reserved for future products

PROD

3:0

r

SBC Product Identifier (bit0=LSB; bit3=MSB)

0 0 0 0_B, TLE9260QX (5V, no LIN, no VCC3, no SWK)

0 1 0 0_B, TLE9261QX (5V, no LIN, VCC3, no SWK)

1 0 0 0_B, TLE9262QX (5V, 1 LIN, VCC3, no SWK)

1 1 0 0_B, TLE9263QX (5V, 2 LIN, VCC3, no SWK)

Notes

1. The actual default register value after POR, Soft Reset or Restart of PROD will depend on the respective

product. Therefore the value ‘y’ is specified.

2. SWK = Selective Wake feature in CAN Partial Networking standard

Data Sheet

129

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

14.7

Electrical Characteristics

Table 23

Electrical Characteristics

V_S= 5.5 V to 28 V, T_j= -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

SPI frequency

1)

Maximum SPI frequency

f_SPI,max

–

4.0

MHz

P_16.7.1

SPI Interface; Logic Inputs SDI, CLK and CSN

H-input Voltage Threshold

L-input Voltage Threshold

Hysteresis of input Voltage

V_IH

–

0.7*

V_CC1

V

–

P_16.7.2

P_16.7.3

V_IL

0.3*

V_CC1

–

1)

V_IHY

–

0.12*

P_16.7.4

V_CC1

Pull-up Resistance at pin CSN R_ICSN

20

40

80

kꢀ

V

_CSN= 0.7 x V_CC1P_16.7.5

Pull-down Resistance at pin

SDI and CLK

R_ICLK/SDI

V_SDI/CLK

0.2 x V_CC1

1)

=

P_16.7.6

Input Capacitance at pin CSN, C_I

SDI or CLK

–

10

–

pF

V

P_16.7.7

Logic Output SDO

H-output Voltage Level

V_SDOH

V_CC1

0.4

-

V_CC1

0.2

-

I

_DOH= -1.6 mA

_DOL= 1.6 mA

P_16.7.8

L-output Voltage Level

V_SDOL

I_SDOLK

–

0.2

–

0.4

10

V

P_16.7.9

Tristate Leakage Current

-10

µA

V

_CSN= V_CC1

;

P_16.7.10

0 V < V_DO< V_CC1

1)

Tristate Input Capacitance

Data Input Timing¹⁾

Clock Period

C_SDO

–

10

15

pF

P_16.7.11

t_pCLK

t_CLKH

t_CLKL

t_bef

250

125

250

125

100

50

–

ns

–

P_16.7.12

P_16.7.13

P_16.7.14

P_16.7.15

P_16.7.16

P_16.7.17

P_16.7.18

P_16.7.19

P_16.7.20

P_16.7.21

Clock High Time

–

Clock Low Time

–

Clock Low before CSN Low

CSN Setup Time

–

t_lead

t_lag

–

CLK Setup Time

–

Clock Low after CSN High

SDI Set-up Time

t_beh

–

t_DISU

t_DIHO

–

SDI Hold Time

–

Input Signal Rise Time at pin t_rIN

–

50

SDI, CLK and CSN

Input Signal Fall Time at pin

SDI, CLK and CSN

t_fIN

–

50

6

ns

µs

–

P_16.7.22

P_16.7.23

Delay Time for Mode

Changes²⁾

t_Del,Mode

includes internal

oscillator tolerance

Data Sheet

130

Rev. 1.1, 2014-09-26

TLE9260QX

Serial Peripheral Interface

Table 23

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V, T_j= -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note /

Test Condition

Number

Min.

Max.

CSN High Time

t_CSN(high)

3

–

µs

–

P_16.7.24

Data Output Timing¹⁾

SDO Rise Time

t_rSDO

–

30

–

80

50

ns

C_L= 100 pF

P_16.7.25

P_16.7.26

P_16.7.27

P_16.7.28

P_16.7.29

SDO Fall Time

t_fSDO

C_L= 100 pF

SDO Enable Time

SDO Disable Time

SDO Valid Time

t_ENSDO

t_DISSDO

t_VASDO

low impedance

high impedance

C_L= 100 pF

–

1) Not subject to production test; specified by design

2) Applies to all mode changes triggered via SPI commands

24

CSN

15

16

17

18

13

14

CLK

SDI

19

20

LSB

MSB

not defined

27

28

29

SDO

Flag

LSB

MSB

Figure 46 SPI Timing Diagram

Note:Numbers in drawing correlate to the last 2 digits of the Number field in the Electrical Characteristics table.

Data Sheet

131

Rev. 1.1, 2014-09-26

TLE9260QX

Application Information

15

Application Information

15.1

Application Diagram

Note:The following information is given as a hint for the implementation of the device only and shall not be

regarded as a description or warranty of a certain functionality, condition or quality of the device.

VBAT

VS

D₁

VBAT

C₁

D₂

C₂

C₃

R₈

VS

VSHS

V_CC1

V_S

VCC1

VCC2

D₃

V_CC2

C₅

C₇

C₄

HS1

HS2

HS3

R₉

C₆

V_S

VSHS

C₁₇

V_DD

CSN

CLK

SDI

R₇

CLK

SDI

µC

D₄

SDO

C₁₈

C₈

Other loads , e.g.

sensor , opamp, ...

LOGIC

State

Machine

TxD CAN

RxD CAN

INT

TxD CAN

RxD CAN

INT

VSHS

RO

Reset

Hall1

Q1

Q2

HS4

Hall2

V_SS

R₅

R₃

R₆

R₄

TLE9260

WK1

WK2

WK3

S₃

C₉

VBAT

S₂

C₁₀

S₁

V_CC2

R₂

VCAN

CANH

C₁₁

R₁

CANH

CANL

CAN cell

R₁₀

C₁₂

R₁₁

V_S

T1

CANL

FOx

GND

LH

Note: The external capacitance on FO3/TEST must be

<=10nF in oder to ensure proper detection of SBC

Development Mode und SBC user mode operation

Application _information _TLE9260. vsd

Figure 47 Simplified Application Diagram

Data Sheet

132

Rev. 1.1, 2014-09-26

TLE9260QX

Application Information

Note:Unused outputs are recommended to be left unconnected on the application board. If unused output pins

are routed to an external connector which leaves the ECU, then these pins should have provision for a zero

ohm jumper (depopulated if unused) or ESD protection.

Table 24

Ref.

Bill of Material for Simplified Application Diagram

Typical Value

Purpose / Comment

Capacitances

C1

C2

C3

68µF

100nF

22µF

Buffering capacitor to cut off battery spikes, depending on application

EMC, blocking capacitor

Buffering capacitor to cut off battery spikes from VSHS as separate supply

input; Depending on application, only needed if VSHS is not connected to

VS;

C4

C5

2.2µF low ESR

100nF ceramic

As required by application, min. 470nF for stability

Spike filtering, improve stability of supply for microcontroller;

not needed for SBC

C6

2.2µF low ESR

Blocking capacitor, min. 470nF for stability;

if used for CAN supply place a 100nF ceramic capacitor in addition very

close to VCAN pin for optimum EMC behavior

C7

33nF

47pF

As required by application, mandatory protection for off-board connections

C8

C17

Only required in case of off-board connection to optimize EMC behavior,

place close to pin

C18

C9

47pF

10nF

Only required in case of off-board connection to optimize EMC behavior,

place close to pin

Spike filtering, as required by application, mandatory protection for off-board

connections (see also Simplified Application Diagram with the Alternate

Measurement Function)

C10

C11

C12

10nF

Spike filtering, as required by application, mandatory protection for off-board

connections

10nF

Spike filtering, as required by application, mandatory protection for off-board

connections

4.7nF / OEM dependent

Split termination stability

Data Sheet

133

Rev. 1.1, 2014-09-26

TLE9260QX

Application Information

Table 24

Ref.

Bill of Material for Simplified Application Diagram (cont’d)

Typical Value Purpose / Comment

Resistances

R1

R2

R3

R4

R5

R6

R7

R8

R9

10kꢀ

Wetting current of the switch, as required by application

Limit the WK pin current, e.g. for ISO pulses

Wetting current of the switch, as required by application

Limit the WK pin current, e.g. for ISO pulses

Wetting current of the switch, as required by application

Limit the WK pin current, e.g. for ISO pulses

depending on LED config. LED current limitation, as required by application

47kꢀ

Selection of hardware configuration 1/3, i.e. in case of WD failure SBC

Restart Mode is entered.

If not connected, then hardware configuration 2/4 is selected

R10

R11

R15

60ꢀ / OEM dependent

10kꢀ

CAN bus termination

WK1 pin current limitation, e.g. for ISO pulses, for alternate measurement

function (see also Simplified Application Diagram with the Alternate

Measurement Function)

R16

depending on application Voltage Divider resistor to adjust measurement voltage to microcontroller

and microcontroller

ADC input range (see also Simplified Application Diagram with the Alternate

Measurement Function)

R17

depending on application Voltage Divider resistor to adjust measurement voltage to microcontroller

and microcontroller

ADC input range (see also Simplified Application Diagram with the Alternate

Measurement Function)

Active Components

D1

D2

e.g. BAS 3010A, Infineon Reverse polarity protection for VS supply pins

e.g. BAS 3010A, Infineon Reverse polarity protection for VSHS supply pin; if separate supplies are not

needed, then connect VSHS to VS pins

D3

D4

T1

µC

LED

As required by application, configure series resistor accordingly

High active FO control

LED

e.g. BCR191W

e.g. TC2xxx

Microcontroller

Note:This is a simplified example of an application circuit. The function must be verified in the real application.

Data Sheet

134

Rev. 1.1, 2014-09-26

TLE9260QX

Application Information

VBAT

VS

D₁

VBAT

C₂

C₁

D₂

e.g.

470uF

VS

V_CC1

VCC1

CSN

C₅

C₄

V_S

V_DD

CSN

CLK

SDI

CLK

SDI

SDO

µC

SDO

LOGIC

State

Machine

TxD CAN

RxD CAN

TxD CAN

RxD CAN

INT

RO

INT

Reset

ADC_x

Vbat_uC

TLE9260

max.

500uA

R₆

≥10k

WK1

V_SS

ISO Pulse

protection

C₉

≥10n

S₁

WK2

Note:

Vbat_uC

R₁₇

Max. WK1 input current limited to

500µA to ensure accuracy and

proper operation ;

R₁₆

GND

Figure 48 Simplified Application Diagram with the Alternate Measurement Function via WK1 and WK2

Note:This is a very simplified example of an application circuit. The function must be verified in the real

application.WK1 must be connected to signal to be measured and WK2 is the output to the microcontroller

supervision function. The maximum current into WK1 must be <500uA. The minimum current into WK1

should be >5uA to ensure proper operation.

Data Sheet

135

Rev. 1.1, 2014-09-26

TLE9260QX

Application Information

15.2

ESD Tests

Note:Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) will been performed. The

results and test condition will be available in a test report. The target values for the test are listed in Table 25

below.

Table 25

ESD “Gun Test”

Result

Performed Test

Unit

Remarks

ESD at pin CANH, CANL, >6

VS, WK1..3, HSx, VCC2

versus GND

kV

¹⁾²⁾positive pulse

ESD at pin CANH, CANL, < -6

VS, WK1..3, HSx, VCC2

versus GND

kV

¹⁾²⁾negative pulse

1)ESD Test “Gun Test” is specified with external components for pins VS, WK1..3, HSx and VCC2. See the

application diagram in Chapter 15.1 for more information.

2) ESD susceptibility “ESD GUN” according LIN EMC 1.3 Test Specification, Section 4.3 (IEC 61000-4-2). Tested by external

test house (IBEE Zwickau, EMC Test report Nr. 07-10-13)

EMC and ESD susceptibility tests according to SAE J2962-2 (2010) have been performed. Tested by external test

house (UL LLC, Test report Nr. 2013-474A)

Data Sheet

136

Rev. 1.1, 2014-09-26

TLE9260QX

Application Information

15.3

Thermal Behavior of Package

Below figure shows the thermal resistance (R_{th_JA}) of the device vs. the cooling area on the bottom of the PCB for

Ta = 85°C. Every line reflects a different PCB and thermal via design.

Figure 49 Thermal Resistance (R_{th_JA}) vs. Cooling Area

Data Sheet

137

Rev. 1.1, 2014-09-26

TLE9260QX

Application Information

Cross Section(JEDEC 2s2p) with Cooling Area

Cross Section(JEDEC 1s0p) with Cooling Area

70µm modelled(traces)

35µm, 90% metalization*

70µm / 5% metalization+ cooling area

*: means percentual Cu metalization on each layer

PCB (top view)

PCB (bottom view)

Detail SolderArea

Figure 50 Board Setup

Board setup is defined according to JESD 51-2,-5,-7.

Board: 76.2x114.3x1.5mm³ with 2 inner copper layers (35µm thick), with thermal via array under the exposed pad

contacting the first inner copper layer and 300mm²cooling area on the bottom layer (70µm).

Data Sheet

138

Rev. 1.1, 2014-09-26

TLE9260QX

Package Outlines

16

Package Outlines

0ꢀ9 MAXꢀ

(0ꢀ65)

11 x 0ꢀ5 = 5ꢀ5

0ꢀ5

0ꢀ1

7

A

0ꢀ03

6ꢀ8

0ꢀ1

+0ꢀ03¹⁾

2)

37

B

36

25

24

48x

0ꢀ08

48

13

1

12

Index Marking

0ꢀ4 x 45°

48x

0ꢀ1

0ꢀ05

Index Marking

0ꢀ23

(5ꢀ2)

(6)

(0ꢀ35)

M

A B C

(0ꢀ2)

0ꢀ05 MAXꢀ

C

1) Vertical burr 0ꢀ03 maxꢀ, all sides

2) This four metal areas have exposed diepad potential

PG-VQFN-48-29, -31-PO V03

Figure 51 PG-VQFN-48-31

Note:For assembly recommendations please also refer to the documents "Recommendations for Board Assembly

(VQFN and IQFN)" and "VQFN48 Layout Hints" on the Infineon website (www.infineon.com).

The PG-VQFN-48-31 package is a leadless exposed pad power package featuring Lead Tip Inspection (LTI) to

support Automatic Optical Inspection (AOI).

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with

government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e

Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Data Sheet

139

Rev. 1.1, 2014-09-26

Edition 2014-09-26

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.


型号：	TLE9260QX
厂家：	Infineon
描述：	The device is designed for various CAN automotive applications as main supply for the microcontroller and as interface for a CAN bus network.
文件：	总141页 (文件大小：5610K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLE9260QX [INFINEON]

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