TLE9140EQW [INFINEON]
As the market strives for cars and trucks with bet;
| 型号： | TLE9140EQW |
| 厂家： | 
Infineon |
| 描述： | As the market strives for cars and trucks with bet |
| 文件： | 总100页 (文件大小：1294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLE9140EQW
Preliminary datasheet
MOTIX™ 48 V/24 V bridge driver
Features
• Drive B6-bridge for BLDC motors in 24 V/48 V platforms with protection features
• Compatible with general microcontroller and MOTIXTM MCU
• High voltage capability/robustness up to 100 V helps to simplify PCB design
• 16-bit serial peripheral interface
• Charge pump concept to support 100% duty cycle
• Undervoltage shutdown
• Overvoltage shutdown
• Overtemperature protection
• Drain-source monitoring
• Timeout watchdog
• Cross-current protection
• Off-state diagnostic
• Adaptive MOSFET control
Potential applications
• Can be used to drive B6-bridge for BLDC motors with battery voltage up to 72 V (load dump) for
24 V/48 V applications for example engine cooling fan, water pump and oil pump
• Can be used together with general microcontroller to transfer the applications to 24 V/48 V
platforms
• Can be used together with MOTIXTM MCU to transfer the applications to 24V/48V platforms with
minor sofꢀare development effort
Product validation
Qualified for automotive applications.
Product validation according to AEC-Q100.
Description
This device is a 48 V MOSFET gate driver compatible with general microcontrollers and MOTIXTM MCU to drive max. 3 half-bridges
in 24 V/48 V platform. It provides protection features and the possibility to use the diagnosis features integrated in the MOTIXTM
MCU.
TLE9140EQW
VSM
UV & OV
Detection
Charge Pump
Temperature
warning and
shutdown
DH
VDD
Internal Supply
B6 - Bridge
Control Logic
16-bit SPI
SPI
EN
Watchdog
Protections
Diagnostic
Gate Drivers
MCU/MOTIXTM
MCU
M
MOSFET
Control
VDS
Monitoring
Safe Switch
Off Path
Safe Switch
Off Path
ILx/IHx
CSA
Datasheet
www.infineon.com
Please read the sections "Important notice" and "Warnings" at the end of this document
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
Description
Table 1
Product summary
Parameter
Symbol
VS(nor)
Value
Specified supply voltage range
Max. total charge driver capability
Max. undervoltage threshold
Min. overvoltage threshold
Max. total quiescent current
8.0 V to 72 V
231 nC * 6 @ 25 kHz
20.0 V/8.0 V
72.0 V/48.0 V
26 µA
Qtot_max
VSUV_ON
VSOV_ON
IDDQ + ISQ
Package
Marking
PG-TSDSO-32
TLE9140EQW
Datasheet
2
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
Table of contents
Table of contents
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1
3.2
3.3
4
4.1
4.1.1
4.1.2
4.1.3
4.2
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.3
4.4
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.9
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Drain-source voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Off-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Timeout watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Cross-current protection and drain-source overvoltage blank time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Drain-source overvoltage blank time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Overvoltage and undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VSM undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
VSM overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VDD undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Charge pump undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Electrical characteristics protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
6.1
6.2
Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Gate driver control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Electrical characteristics of gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7
BEMF comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8
Serial Peripheral Interface - SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8.1
SPI description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Datasheet
3
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
Table of contents
8.2
8.3
8.4
8.5
Global error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SPI error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Electrical characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9
9.1
9.2
Register specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
General control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
General control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
General control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
General control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
General control register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
General control register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
General control register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
General control register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
General control register 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
General control register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
General control register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
General status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Global status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Global status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Global status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Global status register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Effective MOSFET turn-on/-off delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Effective MOSFET rise/fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10
9.2.11
9.2.12
9.2.13
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
10
11
12
Application figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Datasheet
4
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
1 Block diagram
1
Block diagram
UV & OV
detection
Charge pump
EN
Temperature
warning and
shutdown
VDD
SDI
Internal supply
Control logic
16-bit SPI
DH
Watchdog
Protections
SDO
VSM
CP1
CP2
SCLK
CSN
EN
Diagnostic
VDS
monitoring
MOSFET
control
GHM1
SHM1
Safe
switch-off
path
Safe switch-
off path
GLM1
GHM2
SHM2
IH1
IH2
IH3
GLM2
GHM3
IL1
IL2
IL3
SHM3
GLM3
SLM
GND
Figure 1
Block diagram
Datasheet
5
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
2 Pin configuration
2
Pin configuration
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
GND
VDD
SCLK
SDO
CSN
SDI
IL1
IL2
IL3
IH1
IH2
IH3
SLM
GLM1
GLM2
GLM3
DH
VSM
CP2
CP2P
N.C.
GHM3
SHM3
CP2N
SHM2
GHM2
EN
GHM1
SHM1
CP1P
CP1N
CP1
9
10
11
12
13
14
15
16
exposed pad (bottom)
Figure 2
Table 2
Pin configuration
Pin definitions and functions
Pin
1
Symbol
GND
Function
Ground
2
VDD
VDD supply voltage (connect to MCU/MOTIXTM MCU)
Power supply for digital circuits
3
SCLK
SDO
CSN
SDI
IL1
Serial clock input (connect to MCU/MOTIXTM MCU)
Serial data output (connect to MCU/MOTIXTM MCU)
Chip select not (connect to MCU/MOTIXTM MCU)
Serial data input (connect to MCU/MOTIXTM MCU)
Low-side 1 gate control (connect to MCU/MOTIXTM MCU)
Low-side 2 gate control (connect to MCU/MOTIXTM MCU)
Low-side 3 gate control (connect to MCU/MOTIXTM MCU)
High-side 1 gate control ((connect to MCU/MOTIXTM MCU)
High-side 2 gate control (connect to MCU/MOTIXTM MCU)
High-side 3 gate control (connect to MCU/MOTIXTM MCU)
4
5
6
7
8
IL2
9
IL3
10
11
12
13
IH1
IH2
IH3
SLM
Source low-side
Common connection to the source of the low-side MOSFETs
14
15
GLM1
GLM2
Gate low-side 1
Gate low-side 2
(table continues...)
Datasheet
6
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
2 Pin configuration
Table 2
(continued) Pin definitions and functions
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Symbol
GLM3
CP1
Function
Gate low-side 3
Output of charge pump 1
Negative connection to charge pump capacitor 1
Positive connection to charge pump capacitor 1
Source high-side 1
CP1N
CP1P
SHM1
GHM1
EN
Gate high-side 1
Enable
GHM2
SHM2
CP2N
SHM3
GHM3
N.C.
Gate high-side 2
Source high-side 2
Negative connection to charge pump capacitor 2
Source high-side 3
Gate high-side 3
Unconnected pin
CP2P
CP2
Positive connection to charge pump capacitor 2
Output of charge pump 2
VSM
Voltage supply
Connect to supply voltage (battery) with reverse polarity protection circuit
32
DH
Drain high-side
Connect to the drain of high-side MOSFETs
Datasheet
7
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
3 General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 3
Absolute maximum ratings
Tj = -40°C to 175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
Voltages
Supply voltage
VSM
VDD
-0.3
–
78
V
V
–
–
P_GPC_01_01
P_GPC_01_02
Logic supply
voltage
-0.3
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
5.5
Logic input voltages VILX, VIHX
(IHx, ILx)
20
V
–
P_GPC_01_03
P_GPC_01_04
P_GPC_01_05
P_GPC_01_06
Logic input voltages VSCLK, VCSN
(SCLK, CSN)
VDD + 0.3 V
VDD + 0.3 V
VDD + 0.3 V
VDD + 0.3 V
–
Logic input voltages VSDI
(SDI)
I < 10mA
I < 10 mA
Logic input voltages VEN
(EN)
Voltage at SDO
VSDO
-0.3
–
–
–
–
–
–
P_GPC_01_07
P_GPC_01_08
P_GPC_01_09
Voltage range at DH VDH
-0.3
90
V
V
Voltage range at
GHMx
VGHMx
-10.0
100
Dynamic voltage
range at GHMx
VGHMx
VSHMx
VSHMx
VGLMx
VSLM
–
–
–
–
–
–
–
110
100
110
20
V
V
V
V
V
V
< 500 ns
P_GPC_01_10
P_GPC_01_11
P_GPC_01_12
P_GPC_01_13
P_GPC_01_14
P_GPC_01_15
Voltage range at
SHMx
-10.0
–
–
Dynamic voltage
range at SHMx
< 500 ns
Voltage range at
GLMx
-7.0
-7.0
-0.3
–
–
–
Voltage range at
SLM
6.0
13
Voltage difference VGSM
between GHMx-
SHMx and GLMx-
SLM
Voltage range at
charge pump pin
CP1
VCP1
-0.3
–
20
V
–
P_GPC_01_16
(table continues...)
Datasheet
8
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
3 General product characteristics
Table 3
(continued) Absolute maximum ratings
Tj = -40°C to 175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
-0.3
Max.
VCP1
0.3
Voltage range at
charge pump pin
CP1N
VCP1N
–
+
V
V
V
V
V
V
–
–
–
–
–
–
P_GPC_01_17
Voltage range at
charge pump pin
CP1P
VCP1P
-0.3
-0.3
–
–
78
P_GPC_01_25
P_GPC_01_26
P_GPC_01_18
P_GPC_01_19
P_GPC_01_20
Voltage difference VSM - VCP1N
between VSM and
CP1N pins
VSM
100
100
100
Voltage range at
charge pump pin
CP2P
VCP2P
VSM - 0.3 –
VSM - 0.6 –
Voltage range at
charge pump pin
CP2
VCP2
Voltage range at
charge pump pin
CP2N
VCP2N
-0.3
-40
–
–
Temperatures
Junction
temperature
175
°C
–
P_GPC_01_21
Tj
ESD susceptibility
ESD susceptibility
all pins 1
VESDHBM1
VESDCDM1
VESDCDM2
-2
–
–
–
2
kV
V
HBM 1)
CDM 2)
CDM 2)
P_GPC_01_22
P_GPC_01_23
P_GPC_01_24
ESD susceptibility
all pins 2
-500
-750
500
750
ESD susceptibility
pin corner pins
V
1)
2)
ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF).
ESD susceptibility, Charged device model (CDM) according JEDEC JESD22-C101.
Datasheet
9
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
3 General product characteristics
3.2
Functional range
Table 4
Functional range
Tj = -40°C to 175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
8.0
Max.
60
Supply voltage
range for normal
operation
VSM(nor)
–
V
V
–
P_GPC_02_01
Extended supply
voltage range
VSM(ext)
8.0
–
75
Note: All parameters
are specified with
the condition
P_GPC_02_02
8.0 V < VSM < 60 V. They
may have deviations
in extended supply
voltage range.
Voltage range at DH VDH
8.0
3.0
–
–
85
V
V
–
–
P_GPC_02_03
P_GPC_02_04
Logic supply
voltage
VDD
5.5
Junction
-40
-40
–
–
150
175
°C
°C
–
–
P_GPC_02_05
P_GPC_02_06
Tj
temperature
Extended junction Tj_ext
temperature
3.3
Thermal resistance
Thermal resistance
Symbol
Table 5
Parameter
Values
Typ.
1.93
27.12
Unit Note or condition
P-Number
Min.
Max.
Junction to case
RthJC
RthJA
–
–
–
–
k/W Ta = 85°C
k/W Ta = 85°C;
P_GPC_03_01
P_GPC_03_02
Junction to
ambient
Package on JEDEC 2s2p
with thermal VIAs
Datasheet
10
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
4 General description
4
General description
Operation modes
4.1
EN = High
Sleep mode
EN = Low
Low current
consumption
Gate drivers OFF
Normal mode
EN = High
EN = Low
EN = Low
Watchdog
continuously
retriggered
Watchdog error
1. ST = 0
Stop mode
2. Send watchdog pattern
with correct CHECKSUM
EN = High
ST = 1
External MOSFETs
are turned OFF
Figure 3
State diagram
4.1.1
Normal mode
The device enters normal operation mode if EN pin is set to high for a duration longer than SPI setup time tSET_SPI
.
The device will stay in the normal operation mode if the watchdog is retriggered in the defined watchdog period and
the EN is kept to high.
In normal operation mode, the device behaves as follows:
•
•
All functions and all diagnostics are available
The output drivers can be enabled and configured through the SPI in error free condition
Note:
In case of SPI error, the SPI frame which contains an error will be ignored and the SPIE bit will be set. The
next valid SPI frame will be accepted, but the SPIE bit remains until it is cleared by the SPI command.
Datasheet
11
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
4 General description
4.1.2
Sleep mode
Sleep mode is a low power mode with quiescent current of VDD and VSM reduced respectively to IDD_Q and ISMQ
.
If EN is set to low for a duration longer than EN filter time tEN_FILT, the device will:
•
•
Turn-off the external MOSFETs actively
Enter sleep mode with a delay defined by tDSLEEP
In sleep mode, the device behaves as follows:
•
•
•
Turn-off the external MOSFETs with pull down resistors
Deactivate the internal circuits and the power supply structure
Reset the SPI registers
4.1.3
Stop mode
In case of watchdog error, the device will:
•
•
•
Turn-off external MOSFETs
Set ST bit (see STAT and Global status byte)
Enter stop mode
In stop mode, the device behaves as follows:
•
•
•
•
The control registers are reset to default values
Any write command or clear command (except ST bit in STAT) will be discarded
A clear command to status registers does not reset any failure flag except ST bit in STAT
Control and status registers are allowed to be read in this mode
The device will resume normal mode from stop mode if the microcontroller executes the following sequence:
1.
2.
Clear the ST bit in STAT
Send watchdog pattern with correct CHECKSUM bit
Note:
Only a correct SPI protocol transaction in between can interrupt the exit sequence.
4.2
Reset behavior
The device resumes normal operation mode, and the nPOR bit in STAT and Global status byte is reset to 0 to report
the reset condition if the following conditions are fulfilled:
•
•
EN is set to high for a duration longer than tSET_SPI
VDD > VDD_POR
In case of VDD undervoltage, if VDD is rising above VDD_POR again, the device behaves as follows:
•
•
•
Reset the digital block
Set NPOR bit to 0 to report the reset condition
Resume normal operation mode
4.3
Power supply
The device is supplied by VDD and VSM. The VDD supplies the digital I/O ports, and VSM supplies the buck/boost charge
pump (charge pump 1) and the single stage charge pump (charge pump 2).
The output of the buck/boost charge pump (CP1) is regulated at VCP1, and supplies:
•
•
The low side gate drivers
The single stage charge pump
The output voltage of the single stage CP2 is used to supply the high side gate drivers.
Datasheet
12
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
4 General description
VSM
CCP2
CVCP2
SHx<3:1>
GHx<3:1>
CP2P CP2N
CP2
HS gate
driver
Charge pump 2
CCP1
CP1P CP1N
GLx<3:1>
SL
CP1
Charge pump 1
(buck/boost)
LS gate
driver
CVCP1
Figure 4
Power supply
4.4
Electrical characteristics
Table 6
Supply
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
Current consumption, EN = low
Supply quiescent
current
ISMQ
–
–
–
–
7
15
µA
µA
μA
μA
Tj < 85 °C
P_GEN_01_01
P_GEN_01_03
P_GEN_01_04
P_GEN_01_06
Supply quiescent
current extended
ISMQ_EXT
IDDQ
–
3
–
40
150°C < Tj ≤ 175°C
Tj < 85 °C
Logic supply
quiescent current
10
Logic supply
quiescent current
extended
IDDQ_EXT
120
150° < Tj ≤ 175°C
Total quiescent
current
IDDQ + ISMQ
–
8.5
26
μA
Tj < 85 °C
P_GEN_01_07
Sleep mode delay
EN low filter time
tDSLEEP
tEN_FILT
2.5
1
4.4
2.4
10
μs
–
–
P_GEN_01_08
P_GEN_01_09
4.5
μs
Current consumption, EN = high
Supply current
ISM_NOR1
–
–
125
62
150
85
mA 13 V < VSM < 19 V,
BD_EN = 1b,
P_GEN_01_20
P_GEN_01_21
ILoad_CP1 = 19.1mA,
ILoad_CP2 = 19.1mA
Supply current
ISM_NOR2
mA 19 V < VSM < 60 V,
BD_EN = 1b, ILoad_CP1
=
19.1 mA, ILoad_CP2
19.1 mA
=
(table continues...)
Datasheet
13
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
4 General description
Table 6
(continued) Supply
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
Logic supply
current
IDD1
–
3.75
6
mA Tj ≤ 150 °C;
CP_EN = 0b;
P_GEN_01_22
BD_EN = 0b
VS
UV switch
ON voltage
VSMUV_ON1
18
19
20
V
VSM increasing
P_GEN_01_23
(VSM_COVUVTH =
000B, 001B,010B or
011B)
UV switch
VSMUV_ON2
7.0
7.5
8.0
V
V
VSM increasing
VSM decreasing
P_GEN_01_24
P_GEN_01_25
ON voltage
(VSM_COVUVTH =
100B)
UV switch
VSMUV_OFF1
17.5
18.5
19.5
OFF voltage
(VSM_COVUVTH =
000B, 001B,010B or
011B)
UV switch
VSMUV_OFF2
6.5
7.0
7.5
V
VSM decreasing
P_GEN_01_26
OFF voltage
(VSM_COVUVTH =
100B)
UV ON/OFF
hysteresis
VSMUV_HY
0.3
53
0.5
55
0.7
57
V
V
VSMUV_ON - VSMUV_OFF
VSM decreasing
P_GEN_01_27
P_GEN_01_28
OV switch
VSMCOV_ON1
ON voltage
(VSM_COVUVTH =
000B)
OV switch
VSMCOV_ON2
VSMCOV_ON3
VSMCOV_ON4
55
57
59
57
59
61
59
61
63
V
V
V
VSM decreasing
VSM decreasing
VSM decreasing
P_GEN_01_29
P_GEN_01_30
P_GEN_01_31
ON voltage
(VSM_COVUVTH =
001B)
OV switch
ON voltage
(VSM_COVUVTH =
010B)
OV switch
ON voltage
(VSM_COVUVTH =
011B)
(table continues...)
Datasheet
14
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
4 General description
Table 6
(continued) Supply
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
50
Unit Note or condition
P-Number
Min.
48
Max.
52
OV switch
VSMCOV_ON5
V
VSM decreasing
P_GEN_01_32
ON voltage
(VSM_COVUVTH =
100B)
Hard OV switch ON VSMOV_ON
71
54
74
56
76
58
V
V
VSM decreasing
VSM increasing
P_GEN_01_33
P_GEN_01_34
voltage
OV switch
VSMCOV_OFF1
VSMCOV_OFF2
VSMCOV_OFF3
VSMCOV_OFF4
VSMCOV_OFF5
OFF voltage
(VSM_COVUVTH =
000B)
OV switch
56
58
60
49
58
60
62
51
60
62
64
53
V
V
V
V
VSM increasing
VSM increasing
VSM increasing
VSM increasing
VSM increasing
P_GEN_01_35
P_GEN_01_36
P_GEN_01_37
P_GEN_01_38
P_GEN_01_39
OFF voltage
(VSM_COVUVTH =
001B)
OV switch
OFF voltage
(VSM_COVUVTH =
010B)
OV switch
OFF voltage
(VSM_COVUVTH =
011B)
OV switch
OFF voltage
(VSM_COVUVTH =
100B)
Hard OV switch OFF VSMOV_OFF
voltage
72
75
1
77
2
V
V
OV ON/OFF
hysteresis
VSMOV_HY
0.5
VSMOV_ON - VSMOV_OFF or P_GEN_01_40
VSMCOV_ONx - VSMCOV_OFFx
VDD
VDD Power-On-
Reset
VDD_POR
2.50
2.40
30
2.70
2.60
–
2.90
2.80
–
V
VDD increasing
P_GEN_01_41
P_GEN_01_42
P_GEN_01_43
VDD Poꢀer-Off-
Reset
VDD_POFFR
VDD_POR_HY
V
VDD decreasing
VDD_POR - VDD_POFFR
VDD Power-On-
Reset hysteresis
mV
Datasheet
15
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
4 General description
Table 7
EN
VSM = 8.0 V to 60 V, Tj = -40°C to + 175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
VDD
EN high level
EN low level
EN hysteresis
VENH
VENL
0.75∗VD
–
V
V
–
–
P_GEN_02_01
P_GEN_02_02
D
–
–
0.25∗VD
D
VENHY
50
25
400
40
–
mV
–
–
P_GEN_02_03
P_GEN_02_04
EN pull-down
resistor
RPD_EN
60
kΩ
Table 8
Charge pumps
VSM = 8.0 V to 60 V, Tj = -40°C to + 175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
Charge pump 1
Charge pump 1
frequency
fCP1
225
250
18
275
kHz
V
–
P_GEN_03_01
P_GEN_03_02
Output voltage (13 VCP1
V < VSM < 60 V): CP1
vs. GND
16
14
19.5
19
13 V < VSM < 60
V, ICP1 = 19.1 mA,
ICP2 = 19.1 mA,
BD_EN = 1b
-40°C ≤ Tj ≤ 150°C
Output voltage HT VCP1
(13 V < VSM < 60 V):
CP1 vs. GND
16.5
V
13 V < VSM < 60
V, ICP1 = 19.1 mA,
ICP2 = 19.1 mA,
BD_EN = 1b
P_GEN_03_03
150°C < Tj ≤ 175°C
Output voltage
(VSM = 8 V): CP1 vs.
GND
VCP1
11
12.5
11.5
500
14
V
VSM = 8 V, ICP1 = 5.6 mA, P_GEN_03_08
ICP2 = 5.6 mA, CPEN =
1b, BD_EN = 1b
-40°C ≤ Tj ≤ 150°C
Output voltage HT VCP1
(VSM = 8V): CP1 vs.
GND
10.7
400
12.5
600
V
VSM = 8 V, ICP1
=
P_GEN_03_09
P_GEN_03_10
5.6 mA, ICP2 = 5.6 mA,
BD_EN = 1b
150°C < Tj ≤ 175°C
CP1 blanking time tBLK_VCP1
µs
8.0 V < VSM < 60 V,
CVCP1= 1 μF, CCP1 = 470
nF, ICP1 = 0 1)
(table continues...)
Datasheet
16
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
4 General description
Table 8
(continued) Charge pumps
VSM = 8.0 V to 60 V, Tj = -40°C to + 175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
300
Rise time of CP1
tRISE_VCP1
–
105
μs
V
8.0 V < VSM < 60 V (25% P_GEN_03_11
to 75%), CCP1 = 470 nF,
ICP1 = 0 1)
Charge pump
1 undervoltage
threshold
VCP1UV
9.0
51
10.0
64
12.0
77
–
P_GEN_03_12
Charge pump 1
undervoltage filter
time
tCP1UV
μs
–
P_GEN_03_13
Charge pump 2
Charge pump 2
frequency
fCP2
225
250
275
kHz
V
–
P_GEN_03_14
P_GEN_03_15
Output voltage (13 VCP2
V < VSM < 60 V): CP2
vs. VSM
11.5
13.5
15.5
13 V < VSM < 60
V, ICP1 = 19.1 mA,
ICP2 = 19.1 mA,
BD_EN = 1b
-40°C ≤ Tj ≤ 150°C
Output voltage HT VCP2
(13 V < VSM < 60 V):
CP2 vs. VSM
10.5
12.5
14
V
13 V < VSM < 60
V, ICP1 = 19.1 mA,
ICP2 = 19,1 mA,
BD_EN = 1b
P_GEN_03_16
150°C < Tj ≤ 175°C
Output voltage
(VSM = 8 V): CP2 vs.
VSM
VCP2
8
9.2
7.5
450
10
–
VSM = 8 V, ICP1 = 5.6 mA, P_GEN_03_21
ICP2 = 5.6 mA, CPEN =
1b, BD_EN = 1b
-40°C ≤ Tj ≤ 150°C
Output voltage HT VCP2
(VSM = 8 V): CP2 vs.
VSM
7.0
–
9.0
600
–
VSM = 8 V, ICP1 = 5.6 mA, P_GEN_03_22
ICP2 = 5.6 mA, CPEN =
1b, BD_EN = 1b
150°C < Tj ≤ 175°C
Turn-on time of CP2 tON_VCP2
μs
8.0 V < VSM < 60 V (25%), P_GEN_03_23
CCP2 = 220 nF, ICP2 = 0 1)
Typ. value at 48V
Rise time of CP2
tRISE_VCP2
–
150
900
350
μs
μs
8.0 V < VSM < 60 V (25% P_GEN_03_24
to 75%), CCP2 = 220 nF,
ICP2 = 0 1)
CP2 blanking time tBLK_VCP2
720
1080
8.0 V < VSM < 60 V,
CVCP2= 470 nF,
P_GEN_03_25
CCP2 = 220 nF, ICP1 = 0 1)
(table continues...)
Datasheet
17
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
4 General description
Table 8
(continued) Charge pumps
VSM = 8.0 V to 60 V, Tj = -40°C to + 175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
Charge pump 2
undervoltage
VCP2UV
tCP2UV
6
7
8
V
–
–
P_GEN_03_26
P_GEN_03_27
Charge pump 2
undervoltage filter
time
51
64
77
μs
1)
Parameter dependent on the capacitance.
Datasheet
18
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
5 Protections and diagnostics
5
Protections and diagnostics
This device provides protection and monitoring functions. All detected errors will be sent back to the general
microcontroller or the MOTIXTM MCU via SPI.
5.1
Reverse polarity protection
Although reverse polarity protection is 48 V standard, it could be required by the applications. In case it is required,
the following structures can be used:
•
•
For 48 V applications, a simple reverse polarity protection including one diode and one resistor can also be used.
Refer to Figure 5
The output of the charge pump 2 (CP2) can be used to supply an external n-channel MOSFET, building an active
reverse polarity protection. Refer to Figure 6
For 24 V applications the solution in Figure 5 is not recommended due to the voltage drop of the resistance.
VSM
CVS
LPFILT
RVS
D3
VBAT
CPFILT2
CPFILT1
Figure 5
Reverse polarity for 48 V applications
VSM
CVS
LPFILT
VBAT
CPFILT2
CPFILT1
CP2
Figure 6
Reverse polarity
5.2
Drain-source voltage monitoring
MOSFETs are protected by VDS monitoring from a short circuit respectively to ground and to battery during on-state:
•
•
HSxDSOV is set to high if the voltage difference between DH and SHMx exceeds the threshold voltage configured
by VDSTH (see Table 9)
LSxDSOV is set to high if the voltage difference between SHMx and SL exceeds the threshold voltage configured by
VDSTH (see Table 9)
If a drain-source overvoltage is detected by a voltage comparator when HSLSOV_DIS = 1, the following actions will be
performed:
•
The gate driver discharge the gate capacitance of the corresponding half-bridge with configured discharge
current IDISCHG_ST during TCCP
•
•
•
The gate capacitance is discharged by IHOLD afer TCCP
The corresponding half bridge will be latched off
The corresponding bit (LSxDSOV/HSxDSOV) in STAT2 is set
Datasheet
19
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
5 Protections and diagnostics
•
•
The DSOV bit in STAT and Global status byte is set
The error signal (GEF) will be sent back to the general microcontroller or
the MOTIXTM MCUhttps://www.infineon.com/cms/en/product/microcontroller/embedded-power-ics-system-on-
chip-/3-phase-bridge-driver-integrated-arm-cortex-m3/via the SPI
If a drain-source overvoltage is detected by a voltage comparator when HSLSOV_DIS = 0, the following actions will be
performed:
•
The gate driver discharge the gate capacitance of the all half-bridges with configured discharge current
IDISCHG_ST during TCCP
•
•
•
•
•
The gate capacitance is discharged by IHOLD afer TCCP
All half bridge will be latched off
The corresponding bit (LSxDSOV/HSxDSOV) in STAT2 is set
The DSOV bit in STAT and Global status byte is set
The error signal (GEF) will be sent back to the general microcontroller or the MOTIXTM MCU via the SPI
The device reports a drain-source voltage error if both conditions are met:
•
•
Afer expiration of the blank time
Drain-source voltage exceeds the configured threshold for a duration longer than the configured filter time
Table 9
Drain-source overvoltage threshold
Drain-source overvoltage threshold
HBxVDSTH[2:0]
000B
145 mV
195 mV (default)
245 mV
295 mV
390 mV
490 mV
590 mV
2 V
001B
010B
011B
100B
101B
110B
111B
The gate drive resume normal operation once the corresponding bit in STAT2 is cleared by the microcontroller.
5.3
Overtemperature protection
If the temperature sensor reaches TjW and the TWDIS is set to 0, then TW bit in STAT1, TE bit in STAT and Global status
byte will be set and latched.
The outputs stages however remain activated. Refer to Figure 7.
The TW bit is reset by clearing STAT1 if the thermal warning condition has disappeared.
If the temperature sensor reaches TjSD, the device behaves as follows:
•
•
•
•
•
Discharge the gate capacitances of the MOSFETs with configured discharge current IDISCHG_ST
All gate drivers are latched off
Deactivate the charge pump
Set TSD bit in STAT1
Set TE bit in STAT and Global status byte
All outputs remain deactivated until the temperature shutdown condition has disappeared and STAT1 is cleared. See
Figure 7.
To resume normal functionality of the gate drivers, the following conditions need to be met:
•
The temperature shutdown condition has disappeared
Datasheet
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Preliminary datasheet
5 Protections and diagnostics
•
•
The the general microcontroller or the MOTIXTM MCU clears TSD bit in STAT1
The charge pump blanking time tBLK_VCPX and the gate driver filter time tGD_filt expire
Tj
TjSD
TjW
t
OUTx
Output is switched off if
ON
TjSD is reached, can be
reactivated if TSD bit is
cleared
High Z
t
no error
TW error bit
High
TW is latched, can be
cleared via SPI
Low
t
t
no error
TSD error bit
High
Low
TSD is latched, can be
cleared via SPI
no error
TE error bit
High
TE is latched, can be cleared when
TW and TSD are cleared via SPI
Low
t
no error
Figure 7
Overtemperature behavior
5.4
Input error
The MOSFETs are protected by input monitoring. When both IHx and ILx of the same bridge are set to high at the same
time:
•
•
•
All external MOSFETs are actively discharged for the duration TCCP
All external MOSFETs are discharged by IHOLD afer TCCP
INEx bits in STAT3, STAT and Global status byte are set and latched
The gate drivers resume normal operation once the input error disappears and the INEx bits are reset by clearing
STAT3.
The INE bit is reset by clearing STAT3.
5.5
Off-state diagnostic
In order to support the off-state diagnostic, the gate driver of each MOSFET provides pull-up and pull-down currents
at the SHx pins.
The pull-up current sources are always active when BD_EN = 1 and CPEN = 1 in normal operation mode.
The pull-down currents of each gate driver are activated by the control bits HBxIDIAG in GENCTRL3. During the off-
state diagnostic routine performed by the general microcontroller or the MOTIXTM MCU, the drain-source overvoltage
threshold of the relevant half-bridges must be set to 2 V nominal. Refer to Table 9. Once the routine is finished, it
is highly recommended to decrease the drain-source overvoltage threshold to a lower value, to have a proper VDS
monitoring threshold and avoid additional current consumption from the VSM input.
Datasheet
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Preliminary datasheet
5 Protections and diagnostics
The corresponding HBxVOUT bit in STAT3 is set if any of the following failures are detected:
•
•
•
MOSFET short circuit to GND
MOSFET short circuit the battery
Open load (disconnected motor)
In normal operation mode the status of the output voltage SHx can be read back with status bit HBxVOUT in
STAT3 when BD_EN = 1, CPEN = 1 and the corresponding half-bridge is in off-state ((IHx, ILx) = (0, 0))
Note:
HBxVOUT = 0 if the half-bridge x is not in off-state ((IHx, ILx) = (1, 0) or (0, 1)). INE is reported if ((IHx, ILx) = (1,
1)).
5.6
Timeout watchdog
An integrated timeout watchdog supervises the integrity of the communication with the general microcontroller or
the MOTIXTM MCU. The watchdog period is programmable by setting the WDPER bits in GENCTRL2 in the range of 2 ms
to 512 ms.
Afer a power-on-reset, if the watchdog is not retriggered by receiving a valid SPI-write command to the watchdog
configuration register (GENCTRL2) from the general microcontroller or the MOTIXTM MCU in the programmable
watchdog period in GENCTRL2, the device will:
•
•
•
•
Set and latch the ST bit in STAT and Global status byte
Reset the control registers to their default values
Actively switch off all external MOSFETs with IDISCHG_ST
Enter the stop mode
The device resumes normal operation, if the general microcontroller or the MOTIXTM MCU device:
1.
2.
Clears the ST bit in STAT when the device is in stop mode
Sends watchdog pattern with correct CHECKSUM bit in normal mode
A checksum bit is part of the SPI command to trigger the watchdog and to set the watchdog setting. The sum of the 8
data bits 7:0 in the register GENCTRL2 needs to have even parity. This is realized by either setting the bit CHECKSUM
to 0 or 1. The checksum is calculated by taking all 8 data bits into account. The written value of the reserved bits of
the register is also considered (even if read as 0 in the SPI output) for checksum calculation, that is if a 1 is written on
the reserved bit position, then a 1 is used in the checksum calculation.
The SPI command is ignored and SPIE bit is set and latched in STAT and Global status byte, if the a watchdog trigger
with an incorrect CHECKSUM is sent.
CHECKSUM = Bit7⊕...⊕Bit0
During normal operation the status bits WDMON[1:0] in STAT2 report the relative position of the watchdog timer to
the watchdog period. Refer to Table 10 and Figure 8.
This allows the detection of a potential latent failure associated to the watchdog timer: the general microcontroller or
the MOTIXTM MCU can indeed verify that the watchdog timer is running.
Table 10
Watchdog monitoring
WDMON[1:0]
Position of the watchdog timer
00B
01B
10B
11B
Watchdog timer is between [0%, 25%] of the watchdog period
Watchdog timer is between [25%, 50%] of the watchdog period
Watchdog timer is between [50%, 75%] of the watchdog period
Watchdog timer is between [75%, 100%] of the watchdog period
Datasheet
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Preliminary datasheet
5 Protections and diagnostics
WD Timer / WD Period
WD trigger
WD timeout
WD trigger
100%
75%
50%
25%
0%
t
00B
01B
00B
01B
10B 11B
00B
01B
10B
11B
00B
WDMON[1:0]
Figure 8
Example of watchdog monitoring and watchdog timeout
The watchdog is enabled by default.
It can be disabled only if the following SPI sequence is sent:
1.
First frame: Set UNLOCK bit in GENCTRL1 to 1
Note: UNLOCK is automatically reset to 0 at the end of the next frame.
Following frame: Set WDDIS bit in GENCTRL3 to 1
2.
The watchdog is directly re-enabled by setting WDDIS to 0.
5.7
Cross-current protection and drain-source overvoltage blank time
All gate drivers feature a cross-current protection time and a drain-source overvoltage blank time. The cross-current
protection avoids the simultaneous activation of the high-side and the low-side MOSFETs of the same half-bridge.
During the blank time, the drain-source overvoltage detection is disabled, to avoid a wrong fault detection during the
activation phase of a MOSFET.
5.7.1
Cross-current protection
If IHx/ILx is set to high in the duration of the other input's TCCP, to avoid the cross current the device will:
•
•
Switch on the corresponding MOSFET with a delay defined by cross-current protection time in GENCTRL12
Discharge the other MOSFET in the same half bridge actively for a duration defined by the remaining cross-
current protection time
Table 11
Cross-current protection time
Cross-current protection time tCCPx (typical)
TCCP[2:0]
000B
0.5 μs
1.0 μs
1.5 μs
001B
010B
(table continues...)
Datasheet
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Preliminary datasheet
5 Protections and diagnostics
Table 11
(continued) Cross-current protection time
TCCP[2:0]
011B
Cross-current protection time tCCPx (typical)
2.0 μs
2.5 μs
3.0 μs
3.5 μs
4.0 μs
100B
101B
110B
111B
5.7.2
Drain-source overvoltage blank time
When the MOSFETs are switched on, afer the expiration of the cross-current protection time, a drain-source
overvoltage error will be masked during the blank time defined in GENCTRL12 for the drain-source monitoring.
Table 12
Drain-source overvoltage blank time
Drain-source overvoltage blank time tBLANKx (nominal)
TBLK[2:0]
000B
0.5 μs
1.0 μs
1.5 μs
2.0 μs
2.5 μs
3.0 μs
3.5 μs
4.0 μs
001B
010B
011B
100B
101B
110B
111B
5.8
Overvoltage and undervoltage shutdown
5.8.1
VSM undervoltage
If VSM drops below VSMUV_OFFx and VDD > VDD_POR, the device will:
•
Switch off the external MOSFETs actively for the duration TCCP with the discharge current corresponding to the
settings of IDISCHG_ST
•
•
•
•
•
Deactivate the charge pumps
Activate passive discharge afer TCCP
Set and latch VSMUV bit in STAT1
Set and latch SUPE bit in STAT and Global status byte
Keep logic information
If VSM rises above VSMUV_ONx as shown in Figure 9, afer clearing the VSMUV bit the device resumes normal operation
when tBLK_VCPX and tGD_filt expire.
The SUPE is reset if the following conditions are fulfilled:
•
•
VSM > VSMUV_ONx (see Figure 9)
The device receives a clear command to STAT1
Datasheet
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Preliminary datasheet
5 Protections and diagnostics
VSM
VSMCOV_CFG = 1B
VSMOV_OFF
VSMOV_HY
VSMOV_ON
VSMCOV_OFFx
VSMUV_HY
VSMUV_OFF
VSMUV_ON
t
t
tBLK_VCPX + tGD_filt
tBLK_VCPX + tGD_filt
Output
reactivated
Output
reactivated
OUTx
OUTx
ON
ON
High Z
High Z
t
VSMUV in STAT1 is cleared
VSMOV_PROT in STAT1 is cleared
VSMUV
VSMOV_PROT
High
Low
High
Low
t
t
Figure 9
VSM monitoring
Datasheet
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Preliminary datasheet
5 Protections and diagnostics
VSM
VSMCOV_CFG = 0B
VSMCOV_OFFx
VSMOV_HY
VSMCOV_ONx
VSMUV_HY
VSMUV_OFF
VSMUV_ON
t
t
tBLK_VCPX + tGD_filt
tBLK_VCPX + tGD_filt
LSAFW_CFG = 0B
Output
reactivated
Output
reactivated
OUTx
OUTx
ON
ON
High Z
High Z
t
VSMUV in STAT1 is cleared
LSAFW_CFG = 1B
VSMUV
Output
reactivated
OUTx
Output is deactivated.
Switch on LS according
to LSAFW bits.
High
Low
ON
t
High Z
t
t
VSMOV in STAT1 is cleared
VSMOV
High
Low
Figure 10
Configurable VSM monitoring
5.8.2
VSM overvoltage
If VSM rises above VSMOV_OFF, VDD > VDD_POR, the device will:
•
Switch off the external MOSFETs actively for the duration TCCP with the discharge current corresponding to the
settings of IDISCHG_ST
•
•
•
•
•
Deactivate the charge pumps
Activate passive discharge afer TCCP
Set and latch VSMOV_PROT bit in STAT1
Set and latch SUPE bit in STAT and Global status byte
Keep logic information
A configurable overvoltage threshold below VSMCOV_OFFx can be selected by set VSM_COVUVTH bit in GENCTRL13.
When the conditions below are met:
•
•
•
•
VSMOV_CFG is set to 0B
VSM rises above the selected VSMCOV_OFFx
VDD > VDD_POR
LSAFW_CFG = 0B
The device will:
•
Switch off the external MOSFETs actively for the duration TCCP with the discharge current corresponding to the
settings of IDISCHG_ST
•
•
Deactivate the charge pumps
Activate passive discharge afer TCCP
Datasheet
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Preliminary datasheet
5 Protections and diagnostics
•
•
•
Set and latch VSMOV bit in STAT1
Set and latch SUPE bit in STAT and Global status byte
Keep logic information
When the conditions below are met:
•
•
•
•
VSMOV_CFG is set to 0B
VSM rises above the selected VSMCOV_OFFx
VDD > VDD_POR
LSAFW_CFG = 1B
The device will:
•
•
•
•
•
•
•
•
•
Set and latch VSMOV bit in STAT1
Set and latch SUPE bit in STAT and Global status byte
Switch off the external high-side MOSFETs actively for the duration TCCP
Switch on the corresponding low-side MOSFET based on the LSAFW bits in GENCTRL13
Switch on all low-side MOSFETs if LSAFW = 00B (the one was in on-state will be kept switched on)
The low-side MOSFETs will be latched on till the VSMOV bit is cleared
Keep charge pumps activated with auto-recovery
Ignore CPREC bit
Keep logic information
Note:
The low-side MOSFETs are switched on based on the same sequence for normal switching on.
When the conditions below are met:
•
•
•
VSMOV_CFG is set to 1B
VSM rises above the selected VSMCOV_OFFx
VDD > VDD_POR
The device will:
•
•
•
•
•
Ignore the configurable overvoltage event
Not set the VSMOV bit in STAT1
Not set SUPE bit in STAT and Global status byte
Keep charge pumps activated
Keep logic information
If VSM drops below VSMOV_ON / VSMCOV_ONx as shown in Figure 9 and Figure 10, afer clearing VSMOV _PROT bit and
VSMOV bit the device will resume normal operation when tBLK_VCPX nd tGD_filt expires.
The SUPE is reset if the following conditions are fulfilled:
•
•
VSM < VSMOV_ON or VSM < VSMCOV_ONx when VSMOV_CFG is 0B (see Figure 9 and Figure 10)
The device receives a clear command to STAT1
5.8.3
VDD undervoltage protection
If the VDD logic supply drops below the undervoltage threshold VDD_POFFR (power off reset), the device behaves as
follows:
•
•
•
•
•
Deactivate the SPI interface
Reset the digital block
Switch off the gate driver
Activate the passive discharge path for the external MOSFETs
Switch off the charge pump
Datasheet
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Preliminary datasheet
5 Protections and diagnostics
5.8.4
Charge pump undervoltage
The voltage of the buck/boost charge pump output (CP1) is monitored in order to ensure a correct control of the
external MOSFETs.
If CP1 falls below the configured charge pump undervoltage threshold VCP1UV, the device will:
•
•
•
•
•
Discharge the external MOSFETs actively with IDISCHG_ST for the duration TCCP
Turn-off the gate drivers
Activate the passive discharge path
Set and latch CP1UV bit in STAT1
Set and latch SUPE bit in STAT and Global status byte
Note:
The charge pump undervoltage event is ignored during blanking time, and will be reported afeꢀ filter time
as shown in Figure 11.
If STAT1 is cleared when VCP1 > VCP1UV, the device resets the SUPE bit and resumes normal operation afer the
charge pump blanking time and the filter time.
Note:
CPREC setting bit is ignored for charge pump undervoltage event. It is only related to the VSM undervoltage
and VSM overvoltage events.
The voltage of the charge pump output (CP2) is monitored in order to ensure a correct control of the external
MOSFETs.
If CP2 falls below the configured charge pump undervoltage threshold VCP2UV, the device will:
•
•
•
•
•
Discharge the external MOSFETs actively with IDISCHG_ST for the duration TCCP
Turn-off the gate drivers
Activate the passive turn-off path
Set and latch CP2UV bit in STAT1
Set and latch SUPE bit in STAT and Global status byte
Note:
The charge pump undervoltage event is ignored during blanking time, and will be reported afeꢀ filter time
as shown in Figure 11.
If STAT1 is cleared when VCP2 > VCP2UV, afer charge pump blanking time and the filter time the device resumes
normal operation and resets the SUPE bit.
Note:
CPREC setting bit is ignored for the charge pump undervoltage event. It is only related to the VSM
undervoltage and VSM overvoltage events.
CP UV event is
CP UV event is
ignored during
reported
VCPx
blanking time
VCPxUV
Time
tBLK_VCPx
tCPxUV
CPEN
Time
Time
CPxUV bit
Figure 11
Charge pump undervoltage event
Datasheet
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Preliminary datasheet
5 Protections and diagnostics
5.9
Electrical characteristics protection and diagnosis
Table 13
Electrical characteristics
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
Watchdog
Watchdog period
tWDPER
–
2
4
8
16
64
128
256
512
–
ms
WDPER[2:0] = 000B
WDPER[2:0] = 001B
WDPER[2:0] = 010B
WDPER[2:0] = 011B
WDPER[2:0] = 100B
WDPER[2:0] = 101B
WDPER[2:0] = 110B
WDPER[2:0] = 111B
P_PRO_01_01
Watchdog period
accuracy
tWDPER_ACC
-10
–
+10
%
–
P_PRO_01_02
P_PRO_01_03
Filter time to avoid false VDS error during recovery from the errors
Gate driver filter
time
tGD_filt
60
72
86
μs
–
Off-state open load diagnosis
Pull-up diagnosis
current
IPUDiag
-0.9
4.5
2.7
-2
7
-3.0
10.5
–
mA 8 V ≤ HBOUTx ≤ 60 V
HBOUTx = VBAT
P_PRO_01_04
P_PRO_01_05
P_PRO_01_06
Pull-down
diagnosis current
IPDDiag
mA 8 V ≤ HBOUTx ≤ 60 V
HBOUTx = VBAT
Pull-down pull-up IPDDiag /
diagnosis current
ratio
–
–
–
IPUDiag
Drain-source monitoring threshold
Drain-source
monitoring
threshold
VVDSMONTHx
–
0.145
0.195
0.245
0.295
0.39
0.49
0.59
2
–
V
HBxVDSTH[2:0] = 000B P_PRO_01_07
HBxVDSTH[2:0] = 001B
HBxVDSTH[2:0] = 010B
HBxVDSTH[2:0] = 011B
HBxVDSTH[2:0] = 100B
HBxVDSTH[2:0] = 101B
HBxVDSTH[2:0] = 110B
HBxVDSTH[2:0] = 111B
Drain-source
monitoring
threshold accuracy
low
VVDSMONTH_ACC1 -30
–
+30
%
VDSTH[2:0] = 000B
P_PRO_01_08
(table continues...)
Datasheet
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TLE9140EQW
Preliminary datasheet
5 Protections and diagnostics
Table 13
(continued) Electrical characteristics
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
VVDSMONTH_ACC2 -20
Max.
+20
Drain-source
monitoring
threshold accuracy
high
–
%
VDSTH[2:0] = 001B
VDSTH[2:0] = 010B
VDSTH[2:0] = 011B
VDSTH[2:0] = 100B
VDSTH[2:0] = 101B
VDSTH[2:0] = 110B
VDSTH[2:0] = 111B
P_PRO_01_09
Drain-source monitoring filter time
VDS monitoring
filter time
tDSMON_FILT
–
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
–
μs
TFVDS[2:0] = 000B
TFVDS[2:0] = 001B
TFVDS[2:0] = 010B
TFVDS[2:0] = 011B
TFVDS[2:0] = 100B
TFVDS[2:0] = 101B
TFVDS[2:0] = 110B
TFVDS[2:0] = 111B
P_PRO_01_10
VDS monitoring
tDSMONFILT_ACC
-10
–
–
+10
–
%
–
P_PRO_01_11
P_PRO_01_12
filter time accuracy
Drain-source monitoring blank time
Drain-source
monitoring blank
time
tDSMON_BLK
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
μs
TBLK[2:0] = 000B
TBLK[2:0] = 001B
TBLK[2:0] = 010B
TBLK[2:0] = 011B
TBLK[2:0] = 100B
TBLK[2:0] = 101B
TBLK[2:0] = 110B
TBLK[2:0] = 111B
Drain-source
tDSMONBLK_ACC
-10
–
+10
%
–
P_PRO_01_13
monitoring blank
time accuracy
(table continues...)
Datasheet
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TLE9140EQW
Preliminary datasheet
5 Protections and diagnostics
Table 13
(continued) Electrical characteristics
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
Cross current protection
Cross current
protection time
tHBxCCPx
–
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–
μs
TCCP[2:0] = 000B
TCCP[2:0] = 001B
TCCP[2:0] = 010B
TCCP[2:0] = 011B
TCCP[2:0] = 100B
TCCP[2:0] = 101B
TCCP[2:0] = 110B
TCCP[2:0] = 111B
P_PRO_01_14
Cross current
protection time
accuracy
tHBxCCPx_ACC
-10
–
+10
%
–
P_PRO_01_15
Thermal warning and shutdown
Thermal
warning junction
temperature
TjW
156
196
5
170
210
10
185
225
–
°C
°C
°C
–
–
–
P_PRO_01_16
P_PRO_01_17
P_PRO_01_18
Thermal
shutdown junction
temperature
TjSD
Thermal shutdown
hysteresis
TjHYS
Datasheet
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Preliminary datasheet
6 Gate driver
6
Gate driver
Gate driver control
6.1
The device integrates six floating gate drivers capable of controlling a wide range of N-channel MOSFETs. They are
configured as three high-sides and three low-sides, building for 3-phase BLDC.
The MOSFETs can be:
•
•
Deactivated with BD_EN = 0
Activated in PWM mode with BD_EN = 1 and CPEN = 1
The MOSFETs are controlled as shown in Figure 12, Figure 13, Figure 14 and Figure 15.
Datasheet
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Preliminary datasheet
6 Gate driver
External IHx
Synchronized IHx
t
t
Charge phase
Precharge phase
Charge phase M
Postcharge phase
IG_HSx
IPOSTCHG
IPRECHG
ICHGM
ICHG
0
t
IPRECHG_T
HSx internal
drive signal
TBLK
TFVDS
IPOSTCHG
IPRECHG
IHOLD
ICHGM
ICHG
0
IHOLD
ICHGM
ICHG
t
-
IHOLD
VGS_HSx
VSHMx
t
t
TRISEHSx
VDH
VSHH
TDONHSx
VSHL
IDS_HSx
IPHASE
t
External ILx
TCCP
t
t
Synchronized ILx
IG_LSx
IHOLD
Predischarge phase
Holding phase
Discharge phase M
t
-
IHOLD
-IDISCHGM
-IPREDISCHG
LSx internal
drive signal
IPREDISCHG_T
IPREDISCHG_T_XT
IHOLD
tOFF_timeout
t
-
IHOLD
-
IHOLD
-IDISCHGM
-IPREDISCHG
Hard off
-
IDISCHG_MAX
VGS_LSx
t
t
IDS_LSx
IPHASE
Figure 12
Turn-on of the high-side MOSFET
Datasheet
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Preliminary datasheet
6 Gate driver
External IHx
Synchronized IHx
t
t
IG_HSx
Discharge phase
Discharge phase M
Predischarge phase
Holding phase
0
t
- IDISCHG
- IDISCHGM
- IPREDISCHG
tOFF_timeout
HSx internal
drive signal
IPREDISCHG_T
IPREDISCHG_T_XT
IHOLD
IHOLD
0
-
IHOLD
t
- IDISCHG
- IDISCHGM
- IPREDISCHG
Hard off
-
IDISCHG_MAX
VGS_HSx
t
t
TFALLHSx
VSHMx
VDH
VSHH
TDOFFHSx
VSHL
IDS_HSx
IPHASE
t
External ILx
Synchronized ILx
IG_LSx
t
t
TCCP
postcharge phase
Precharge phase
IPOSTCHG
IPRECHG
ICHGM
t
t
IPRECHG_T
LSx internal
drive signal
TBLK
TFVDS
IPOSTCHG
IPRECHG
ICHGM
IHOLD
IHOLD
-
IHOLD
t
-
IHOLD
VGS_LSx
t
t
IDS_LSx
IPHASE
Figure 13
Turn-off of the high-side MOSFET
Datasheet
34
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
6 Gate driver
External ILx
Synchronized ILx
t
t
Charge phase
Postcharge phase
IG_LSx
Precharge phase
Charge phase M
IPOSTCHG
IPRECHG
ICHGM
ICHG
0
t
LSx internal
drive signal
IPRECHG_T
TBLK
TFVDS
IPOSTCHG
IPRECHG
IHOLD
ICHGM
ICHG
0
ICHGM
ICHG
IHOLD
t
-
IHOLD
- IDISCHGM
VGS_LSx
VSHMx
t
t
t
TRISELSx
VDH
VSHH
TDONLSx
VSHL
IDS_LSx
IPHASE
External IHx
Synchronized IHx
t
t
TCCP
IG_HSx
IHOLD
Predischarge phase
Holding phase
Discharge phase M
t
-
IHOLD
-IDISCHGM
-IPREDISCHG
IPREDISCHG_T
IPREDISCHG_T_XT
HSx internal
drive signal
tOFF_timeout
IHOLD
t
-
IHOLD
-IDISCHGM
-
IHOLD
-IPREDISCHG
Hard off
-
IDISCHG_MAX
VGS_HSx
t
t
IDS_HSx
IPHASE
Figure 14
Turn-on of the low-side MOSFET
Datasheet
35
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
6 Gate driver
External ILx
Synchronized ILx
t
t
IG_LSx
Discharge phase
Discharge phase M
Predischarge phase
0
t
- IDISCHG
- IDISCHGM
- IPREDISCHG
tOFF_timeout
LSx internal
drive signal
IPREDISCHG_T
IPREDISCHG_T_XT
IHOLD
IHOLD
0
-
IHOLD
t
- IDISCHG
- IDISCHGM
- IPREDISCHG
Hard off
-
IDISCHG_MAX
VGS_LSx
t
t
TFALLLSx
VSHMx
VDH
VSHH
TDOFFLSx
VSHL
IDS_LSx
IPHASE
t
External IHx
t
t
Synchronized IHx
IG_HSx
TCCP
postcharge phase
Precharge phase
IPOSTCHG
IPRECHG
ICHGM
t
HSx internal
drive signal
TBLK
TFVDS
IPOSTCHG
IPRECHG
ICHGM
IHOLD
IHOLD
-
IHOLD
t
-
IHOLD
VGS_HSx
t
t
IDS_HSx
IPHASE
Figure 15
Turn-off of the low-side MOSFET
The turn-on of the high-side MOSFET is done in five phases (refer to Figure 12):
Datasheet
36
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
6 Gate driver
1.
2.
3.
Cross-current protection phase: the cross-current protection time TCCP starts at the falling edge of ILx.
During TCCP, the low-side MOSFET is turned off while the high-side is kept off with IHOLD. Only afer TCCP IHx
is allowed to set to high. The low-side will be kept off with hard off current until TFVDS has elapsed
Pre-charge phase: once the TCCP has elapsed and IHx is set to high, the gate of the high-side MOSFET is
pre-charged with the current IPRECHG for a duration IPRECHG_T. When IPRECHG_T expires it will jump to
charge phase
Charge phase: afer the pre-charge phase the charge current is decreased from IPRECHG down to ICHG. The
gate of the high-side MOSFET will be charged with ICHG until VSHMx reaches GND + 2 V. If VSHMx reaches VDH -
2 V during the charge phase, it will jump to post-charge phase
4.
5.
Middle-charge phase: afer the charge phase the gate of the high-side MOSFET will be charged with ICHGM
until VSHMx reaches VDH - 2 V
Post-charge phase: afer the middle-charge phase the control signal for the charge current is set to IPOSTCHG
until the end of TFVDS. If the device is still in the ramping phase of the post-charge current when TFVDS has
expired, the ramp phase will be extended until it reaches IPOSTCHG. Afer TFVDS expires and IPOSTCHG is
reached, the charge current will be switched to IHOLD
Cross-current protection time TCCP represents the time afer which the complementary transistor in the same
half-bridge can be activated. Therefore TCCP is the minimum discharge phase for the MOSFET. tOFF_timeout is the
maximum time for discharge.
The turn-off of the high-side MOSFET is done in four phases (refer to Figure 13):
1.
2.
3.
Pre-discharge phase: once IHx is set to low, the gate of the high-side MOSFET is pre-discharged with the
current IPREDISCHG for a duration based on IPREDISCHG_T and IPREDISCHG_T_XT. It will jump to middle-
discharge phase afer pre-discharge time expires
Middle-discharge phase: afer the pre-discharge phase the gate current is decreased from IPREDISCHG down
to IDISCHGM. The gate of the high-side MOSFET will be discharged with IDISCHGM until VSHMx reaches GND + 2
V
Discharge phase: afer the middle-discharge phase the device will enter discharge phase. The gate of the
high-side MOSFET will be discharged with IDISCHG until tOFF_timeout expires
4.
Holding phase: afer the tOFF_timeout expires the high-side MOSFET will be kept off with IHOLD
Note:
If a INE failure comes, all MOSFETs will be discharged with IDISCHG_ST for a duration of TCCP.
The turn-on of the low-side MOSFET is done in five phases (refer to Figure 14):
1.
Cross-current protection phase: the cross-current protection time TCCP starts at the falling edge of IHx.
During TCCP, the high-side MOSFET is turned off while the low-side is kept off with IHOLD. Only afer TCCP ILx is
allowed to set to high. The high-side will be kept off with hard off current until TFVDS has elapsed
Pre-charge phase: once the TCCP has elapsed and ILx is set to high, the gate of the low-side MOSFET is
pre-charged with the current IPRECHG for a duration IPRECHG_T. Afer IPRECHG_T expires, it will jump to
charge phase
2.
3.
4.
5.
Charge phase: afer the pre-charge phase the charge current is decreased from IPRECHG down to ICHG. The
gate of the low-side MOSFET will be charged with ICHG until VSHMx reaches VDH - 2 V
Middle-charge phase: afer the charge phase the gate of the low-side MOSFET will be charged with ICHGM
until VSHx reaches GND + 2V
Post-charge phase: afer the middle-charge phase the control signal for the charge current is set to IPOSTCHG
until the end of TFVDS. If the device is still in the ramping phase of the post-charge current when TFVDS has
expired, the ramp phase will be extended until it reaches IPOSTCHG. Afer TFVDS expires and IPOSTCHG is
reached, the charge current will be switched to IHOLD
Cross-current protection time TCCP represents the time afer which the complementary transistor in the same
half-bridge can be activated. Therefore TCCP is the minimum discharge phase for the MOSFET. tOFF_timeout is the
maximum time for discharge.
The turn-off of the low-side MOSFET is done in four phases (refer to Figure 15):
1.
Pre-discharge phase: once ILx is set to low, the gate of the low-side MOSFET is pre-discharged with the current
IPREDISCHG for a duration based on IPREDISCHG_T and IPREDISCHG_T_XT. It will jump to middle-discharge
phase afer pre-discharge time expires
Datasheet
37
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
6 Gate driver
2.
3.
Middle-discharge phase: afer the pre-discharge phase the discharge current is decreased from IPREDISCHG
down to IDISCHGM. The gate of the low-side MOSFET will be discharged with IDISCHGM until VSHMx reaches
VDH - 2 V
Discharge phase: afer the middle-discharge phase the gate of the low-side MOSFET will be discharged with
IDISCHG until tOFF_timeout expires
4.
Holding phase: afer the tOFF_timeout expires the high-side MOSFET will be kept off with IHOLD
Note:
If a INE failure comes, all MOSFETs will be discharged with IDISCHG_ST for a duration of TCCP.
High-side MOSFET:
•
•
•
TDONHSx is counted from the rising edge of the synchronized IHx until VSHMx reaches GND + 2 V
TRISEHSx is counted from the VSHMx reaching GND + 2 V until it reaches VDH - 2 V
If VSHMx does not reach GND + 2 V until TBLK is elapsed, 0xFF and 0x00 will be saved in effective high-side
MOSFET turn-on delay register and effective high-side MOSFET rise time register respectively
•
•
If VSHMx has reached VDH - 2 V when the rising edge of the synchronized IHx comes, 0x00 will be stored in both
the effective high-side MOSFET turn-on delay register and the effective high-side MOSFET rise time register
If VSHMx reaches GND + 2 V but does not reach VDH -2V when TBLK is elapsed, 0xFF will be saved in the effective
high-side MOSFET rise time register
•
•
•
TDOFFHSx is counted from the falling edge of the synchronized IHx until VSHMx reaches VDH - 2 V
TFALLHSx is counted from the VSHMx reaching VDH - 2V until it reaches to GND + 2 V
If VSHMx does not reach VDH - 2 V until TCCP is elapsed, 0xFF and 0x00 will be saved in effective high-side
MOSFET turn-off delay register and effective high-side MOSFET fall time register respectively
•
•
If VSHMx has reached GND + 2 V when the falling edge of the synchronized IHx comes, 0x00 will be stored in both
the effective high-side MOSFET turn-off delay register and the effective high-side MOSFET fall time register
If VSHMx reaches VDH - 2 V but does not reach GND + 2 V when TCCP is elapsed, 0xFF will be saved in the effective
high-side MOSFET fall time register
Note:
•
If VDH - 2 V > VSHMx > GND + 2 V when the rising edge of the synchronized IHx comes, 0x00 will be saved in effective
high-side MOSFET turn-on delay register and the time from the IHx rising edge to VSHMx reaching VDH - 2 V will be
saved in the effective high-side MOSFET rise time register
•
•
If 0x00 is saved as the turn-on delay time, the rise time TRISEHSx might not reflect the slew rate correctly. It is not
recommended to use the TRISEHSx to adjust the switching behavior
If IHx pulse is shorter than TBLK/TCCP, the registers will keep the last value and will not be updated
Low-side MOSFET:
•
•
•
TDONLSx is counted from the rising edge of the synchronized ILx until VSHMx reaches VDH - 2 V
TRISELSx is counted from the VSHMx reaching VDH - 2 V until it reaches GND + 2 V
If VSHMx does not reach VDH - 2 V until TBLK is elapsed, 0xFF and 0x00 will be saved in effective low-side MOSFET
turn-on delay register and effective low-side MOSFET rise time register respectively
•
•
If VSHMx has reached GND + 2 V when the rising edge of the synchronized ILx comes, 0x00 will be stored in both
the effective low-side MOSFET turn-on delay register and the effective low-side MOSFET rise time register
If VSHMx reaches VDH - 2 V but does not reach GND + 2 V when TBLK is elapsed, 0xFF will be saved in the effective
low-side MOSFET rise time register
•
•
•
TDOFFLSx is counted from the falling edge of the synchronized ILx until VSH reaches GND + 2 V
TFALLLSx is counted from the VSHMx reaching GND + 2 V until it reaches to VDH - 2 V
If VSHMx does not reach GND + 2 V until TCCP is elapsed, and 0xFF and 0x00 will be saved in effective low-side
MOSFET turn-off delay register and effective low-side MOSFET fall time register respectively
•
•
If VSHMx has reached VDH - 2 V when the falling edge of the synchronized ILx comes, 0x00 will be stored in both
the effective low-side MOSFET turn-off delay register and the effective low-side MOSFET fall time register
If VSHMx reaches GND + 2 V but does not reach VDH - 2 V when TCCP is elapsed, 0xFF will be saved in the effective
low-side MOSFET fall time register
Note:
Datasheet
38
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
6 Gate driver
•
If VDH - 2 V > VSHMx > GND + 2 V when the rising edge of the synchronized ILx comes, 0x00 will be saved in effective
low-side MOSFET turn-on delay register and the time from the ILx rising edge to VSHMx reaching GND + 2 V will be
saved in the effective low-side MOSFET rise time register
•
•
If 0x00 is saved as the turn-on delay time, the rise time TRISELSx might not reflect the slew rate correctly. It is not
recommended to use the TRISELSx to adjust the switching behavior
The values in the registers are invalid if IHx/ILx pulse is active shorter than TBLK or inactive shorter than TCCP
6.2
Electrical characteristics of gate driver
Table 14
Electrical characteristics gate driver
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
2.5
Max.
High input voltage VIH1_IN
threshold of ILx, IHx
(VDD = 5 V)
–
–
–
V
V
V
V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
P_BDRV_01_01
High input voltage VIH2_IN
threshold of ILx, IHx
(VDD = 3.3 V)
1.5
–
–
–
–
P_BDRV_01_02
P_BDRV_01_03
P_BDRV_01_04
Low input voltage
threshold of ILx, IHx
(VDD = 5 V)
VIL1_IN
0.8
0.6
Low input voltage
threshold of ILx, IHx
(VDD = 3.3 V)
VIL2_IN
–
Hysteresis of ILx,
IHx (VDD = 5 V)
VIHY1_IN
VIHY2_IN
Qtot_max
100
100
–
400
150
–
–
mV
mV
nC
VDD = 5 V
P_BDRV_01_05
P_BDRV_01_06
P_BDRV_01_07
Hysteresis of ILx,
IHx (VDD = 3.3 V)
–
VDD = 3.3 V
Maximum total
charge driver
capability
1400
Due to charge pump
current capability only
6 ∗ MOSFETs +
additional external
capacitors with a
total charge of max.
1400 nC can be driven
simultaneous at a PWM
frequency of 25 kHz.
High level output
voltage low: GHMx
vs. SHMx
VGSHMx
6.5
10
–
12.5
12.5
V
V
VSM = 8 V, ICP1 = 5.6 mA, P_BDRV_01_08
ICP2 = 5.6 mA, CPEN =
1b, BD_EN = 1b
High level output
voltage high: GHMx
vs. SHMx
VGSHMx
11
VSM > 13 V, ICP1
19.1 mA, ICP2
=
P_BDRV_01_09
=
19.1 mA, CPEN = 1b,
BD_EN = 1b
(table continues...)
Datasheet
39
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
6 Gate driver
Table 14
(continued) Electrical characteristics gate driver
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
12.5V
High level output
voltage low: GLMx
vs. SLMx
VGSLMx
8
–
V
V
VSM = 8 V, ICP1 = 5.6
mA, ICP2 = 5.6 mA, CPEN
= 1b, BD_EN = 1b
P_BDRV_01_10
High level output
voltage high: GLMx
vs. SLMx
VGSLMx
10
11
12.5
VSM > 13 V, ICP1
19.1 mA, ICP2
=
P_BDRV_01_11
=
19.1 mA, CPEN = 1b,
BD_EN = 1b
Gate driver current tGDRV_RISE(ON)
20
75
120
120
360
ns
ns
ns
From 20% of ICHG to
80% of ICHG, x = 0 to 63,
CLoad = 20 nF
P_BDRV_01_12
P_BDRV_01_13
P_BDRV_01_14
turn-on rise time
Gate driver current tGDRV_RISE(OFF)
turn-off rise time
20
75
From 20% of IDISCHG
to 80% of IDISCHG,
x = 0 to 63, CLoad = 20 nF
HS delay on time
low
tdelay_on(HS)
tdelay_on(HS)
tdelay_off(HS)
tdelay_off(HS)
tdelay_on(LS)
220
280
HBFREQ = 0B
From IHx reaching
high voltage threshold
to 20% of ICHGx,
x = 0 to 63
HS delay on time
high
250
220
250
220
320
280
320
280
400
360
400
360
ns
ns
ns
ns
HBFREQ = 1B
P_BDRV_01_15
P_BDRV_01_16
P_BDRV_01_17
P_BDRV_01_18
From IHx reaching
high voltage threshold
to 20% of ICHGx,
x = 0 to 63
HS delay off time
low
HBFREQ = 0B
From IHx reaching
low voltage threshold
to 20% of IDISCHGx,
x = 0 to 63
HS delay off time
high
HBFREQ = 1B
From IHx reaching
low voltage threshold
to 20% of IDISCHGx,
x = 0 to 63
LS delay on time
low
HBFREQ = 0B
From ILx reaching
high voltage threshold
to 20% of ICHGx,
x = 0 to 63
(table continues...)
Datasheet
40
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
6 Gate driver
Table 14
(continued) Electrical characteristics gate driver
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
250
Max.
400
LS delay on time
high
tdelay_on(LS)
320
ns
ns
ns
HBFREQ = 1B
P_BDRV_01_19
From ILx reaching
high voltage threshold
to 20% of ICHGx,
x = 0 to 63
LS delay off time
low
tdelay_off(LSx)
220
250
280
320
360
400
HBFREQ = 0B
P_BDRV_01_20
P_BDRV_01_21
From ILx reaching
low voltage threshold
to 20% of IDISCHGx,
x = 0 to 63
LS delay off time
high
tdelay_off(LSx)
HBFREQ = 1B
From ILx reaching
low voltage threshold
to 20% of IDISCHGx,
x = 0 to 63
Charge/discharge
current accuracy
(00 0000B)
IACC0
-60
-40
-30
-20
–
–
–
–
+75
+40
+30
+20
%
%
%
%
ICHG / IDISCHG /
IPRECHG /
P_BDRV_01_22
P_BDRV_01_23
P_BDRV_01_24
P_BDRV_01_25
IPREDISCHG /
IPOSTCHG / ICHGM /
IDISCHGM = 00 0000B
Charge/discharge
current accuracy
(00 1111B)
IACC15
IACC31
IACC31
ICHG / IDISCHG /
IPRECHG /
IPREDISCHG /
IPOSTCHG / ICHGM /
IDISCHGM = 00 1111B
Charge/discharge
current accuracy
(01 1111B)
ICHG / IDISCHG /
IPRECHG /
IPREDISCHG /
IPOSTCHG / ICHGM /
IDISCHGM = 01 1111B
Charge/discharge
current accuracy
(10 1111B)
ICHG / IDISCHG /
IPRECHG /
IPREDISCHG /
IPOSTCHG / ICHGM /
IDISCHGM = 10 1111B,
IGx_SEL = 0B
(table continues...)
Datasheet
41
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
6 Gate driver
Table 14
(continued) Electrical characteristics gate driver
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
-25
Max.
+25
Charge/discharge
current accuracy
(10 1111B)
–
%
%
%
ICHG / IDISCHG /
IPRECHG /
P_BDRV_01_43
IACC31_H
IPREDISCHG /
IPOSTCHG / ICHGM /
IDISCHGM = 10 1111B,
IGx_SEL = 1B
Charge/discharge
current accuracy
(11 1111B)
IACC63
-20
-25
–
–
+20
+25
ICHG / IDISCHG /
IPRECHG /
IPREDISCHG /
IPOSTCHG / ICHGM /
IDISCHGM = 11 1111B,
IGx_SEL = 0B
P_BDRV_01_26
P_BDRV_01_44
Charge/discharge
current accuracy
(11 1111B)
IACC63_H
ICHG / IDISCHG /
IPRECHG /
IPREDISCHG /
IPOSTCHG / ICHGM /
IDISCHGM = 11 1111B,
IGx_SEL = 1B
Discharge_ST
current accuracy (0
0000B)
IACC_ST0
-60
-40
-30
-20
-25
-20
-25
–
–
–
–
–
–
–
+75
+40
+30
+20
+25
+20
+25
%
%
%
%
%
%
%
IDISCHG_ST = 0 0000B P_BDRV_01_27
IDISCHG_ST = 0 0111B P_BDRV_01_28
IDISCHG_ST = 0 1111B P_BDRV_01_29
Discharge_ST
current accuracy (0
0111B)
IACC_ST7
Discharge_ST
current accuracy (0
1111B)
IACC_ST15
IACC_ST23
IACC_ST23_H
IACC_ST31
IACC_ST31_H
Discharge_ST
current accuracy (1
0111B)
IDISCHG_ST = 1 0111B, P_BDRV_01_30
IGx_SEL = 0B
Discharge_ST
current accuracy (1
0111B)
IDISCHG_ST = 1 0111B, P_BDRV_01_45
IGx_SEL = 1B
Discharge_ST
current accuracy (1
1111B)
IDISCHG_ST = 1 1111B, P_BDRV_01_31
IGx_SEL = 0B
Discharge_ST
current accuracy (1
1111B)
IDISCHG_ST = 1 1111B, P_BDRV_01_46
IGx_SEL = 1B
(table continues...)
Datasheet
42
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
6 Gate driver
Table 14
(continued) Electrical characteristics gate driver
VSM = 8.0 V to 60 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
40
SHMx comparator
delay
tSHMx
–
5
ns
–
P_BDRV_01_35
Discharge timeout tOFF_timeout
3.2
4
4.8
μs
–
–
P_BDRV_01_32
P_BDRV_01_33
SHMx High
Threshold
VSHMH
VDH - 3.0 –
VDH - 2.0 V
SHMx Low
Threshold
VSHL
2
–
3.0
11
V
Referred to GND
P_BDRV_01_34
P_BDRV_01_36
P_BDRV_01_37
P_BDRV_01_38
On resistance of
gate current source
RONGX
2
–
Ω
–
BEMF comparator
accuracy
VBEMF_ACC
VBEMF_HYS
-100
–
–
+100
–
mV
mV
VSM = 48V
BEMF hysteresis
100
–
Datasheet
43
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
7 BEMF comparator
7
BEMF comparator
The device has 3 BEMF comparators integrated. GEF can be configured to show the output of each BEMF comparator
and sent back via SDO as shown in Figure 16 below.
Initialization phase
Detection phase
Reconfig phase
Detection phase
Reconfig phase
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
time
SCLK
SDI
set control register 6:
GEF_CONFIG = 01b
set control register 6:
GEF_CONFIG = 10b
set control register 6:
GEF_CONFIG = 11b
time
time
1
0
1
0
1
0
15 14
15 14
15 14
Real time output of BEMF comparator 1
Real time output of BEMF comparator 2
SDO
GEF
GEF
GEF
15 14
1
0
15 14
1
0
15 14
1
0
time
BEMF2
BEMF1
Figure 16
BEMF signal is sent back via SDO
When BEMF_POCESSING_EN bit is set to 0B, the real time signal of the outputs of the BEMF comparators can be read
from STAT4:
If the voltage at SHMx is higher than the average voltage of the other two SHM pins (SHMy + SHMz) / 2, the output of
the corresponding BEMF comparator will be set to 1, and the corresponding bit in the status register will be set to 1.
If the voltage at SHMx is lower than the average voltage of the other two SHM pins (SHMy + SHMz) / 2, the output of
the corresponding BEMF comparator will be set to 0, and the corresponding bit in the status register will be set to 0.
If the BEMF_POCESSING_EN bit is set to 1B, the BEMF signal read from STAT4 will be the output signal with the
post-processing algorithm.
Datasheet
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Preliminary datasheet
8 Serial Peripheral Interface - SPI
8
Serial Peripheral Interface - SPI
SPI description
8.1
The control input word is read via the data input SDI, which is synchronized with the clock input SCLK provided by the
general microcontroller or the MOTIXTM MCU. The output word appears synchronously at the data output SDO, see
Figure 17.
The transmission cycle begins when the chip is selected by the input CSN (chip select not), low active. Afer the CSN
input returns from low to high, the word that has been read is interpreted according to the content. The SDO output
switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for other use. The state of SDI
is shifed into the input register with every falling edge on SCLK. The state of SDO is shifed out of the output register
afer every rising edge on SCLK. The SPI of the device is not daisy chain capable.
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
time
CSN low to high: data from shift register is transferred to output functions
SCLK
time
Actual data
New data
15 14
+ +
SDI
9 8 7 6 5 4 3 2 1
0
15 14 13 12 11 10
time
SDI: will accept data on the falling edge of SCLK signal
Actual status
New status
GEF 15 14
SDO
GEF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
+
+ +
time
SDO: will change state on the rising edge of SCLK signal
Figure 17
SPI data transfer timing
A SPI communication consists of 16-bit frames:
•
•
SDI receives one address byte followed by one data byte
SDO transmits the Global error flag and the Global status byte followed by one response byte
The address byte specifies (see Figure 18):
Datasheet
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Preliminary datasheet
8 Serial Peripheral Interface - SPI
•
•
The target register (A[6:0])
The type of operation:
-
For control registers:
-
-
Read only: OP bit = 0
Read and write: OP bit = 1
-
For status registers:
-
-
Read only: OP bit = 0
Read and clear: OP bit = 1
Address Byte
Data Byte
LSB
0
MSB
15
14
A5
13
A4
12
A3
11
10
A1
9
8
7
6
5
4
3
2
1
SDI
A6
A2
A0
OP
D7
D6
D5
D4
D3
D2
D1
D0
Register content of the selected address
Global Status Byte
Data Byte (Response)
LSB
0
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SD0
0
DSOV SUPE INE
TE NPOR ST
SPIE
D7
D6
D5
D4
D3
D2
D1
D0
Time
MSB is sent first in SPI message
Figure 18
In-frame response
8.2
Global error flag
GEF bit can be configured by GEF_CONFIG in GENTRL6:
•
•
•
•
00B global error flag
01B back EMF1
10B back EMF2
11B back EMF3
The global error flag (GEF) bit is reported on SDO between the CSN falling edge and the first SCLK rising edge.
When the GEF bit is configured as a global error flag, the device is possible to have a quick diagnostic without any SPI
clock pulse in following conditions:
•
•
A fault condition is detected as in Table 15
The device comes from a power-on-reset
Datasheet
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Preliminary datasheet
8 Serial Peripheral Interface - SPI
CSN
time
0
SCLK
time
time
0
SDI
High Impedance
High Impedance
Global Error Flag
SDO
time
Figure 19
GEF - diagnostic with 0 - clock cycle
8.3
Global status byte
The SDO shifs out the general status register during the first eight SCLK cycles to provide an overview of the device
status shown in Table 15 as following (in Figure 18):
•
•
VDS monitoring error (DSOV bit): logical OR combination between HSxDSOV and LSxDSOV
Supply error (SUPE bit): logical OR combination between VSM undervoltage shutdown (VSMUV), VSM overvoltage
shutdown (VSMOV and VSMOV_PROT) and charge pump (CP1UV and CP2UV)
•
•
Input error (INE bit): logical OR combination of INEx bits
Temperature error (TE bit):
-
-
Logical OR combination between thermal warning (TW) and thermal shutdown (TSD) when TWDIS = 0
Thermal shutdown (TSD) when TSD = 1
•
•
•
Negated power-on-reset (nPOR bit)
Stop mode (ST bit)
SPI protocol error (SPIE bit)
Note:
The Global error flag is a logic OR combination of every bit of the global status byte: GEF = (DSOV) OR (SUPE)
OR (INE) OR (TE) OR (NOT(nPOR)) OR (ST) OR (SPIE).
Table 15
Failure reported in the global status byte and global error flag
Type of error
VDS monitoring error
Supply error
Failure reported in the global status byte
Global error flag
DSOV = 1
SUPE = 1
INE = 1
1
1
1
1
1
1
1
Input error
Temperature error
Power-on-reset
Stop mode
TE = 1
NPOR = 0
ST = 1
SPI protocol error
SPIE = 1
(table continues...)
Datasheet
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Rev. 0.05
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TLE9140EQW
Preliminary datasheet
8 Serial Peripheral Interface - SPI
Table 15
(continued) Failure reported in the global status byte and global error flag
Type of error
Failure reported in the global status byte
Global error flag
No error and no power-on-reset
DSOV = 0
SUPE = 0
INE = 0
0
TE = 0
NPOR = 1
ST = 0
SPIE = 0
8.4
SPI error detection
The SPI incorporates an error flag SPIE in STAT and Global status byte to supervise and preserve the data integrity.
The SPIE bit is set in the next SPI communication if following SPI errors are detected during a given frame:
•
The number of SCLK clock pulses received for the duration CSN = 0 is (protocol error):
-
-
-
Not zero
Or less than 16
Or more than 16
•
•
•
A watchdog trigger with an incorrect checksum bit is sent
The microcontroller sends an SPI command to an unused address (protocol error)
A clock polarity error is detected, see the Figure 22 below: the incoming clock signal was high during CSN rising or
falling edges (protocol error)
•
•
Any command to clear status registers in stop mode and not belonging to the exit sequence
Any command to write control registers in stop mode and not belonging to the exit sequence
To ensure a correct SPI communication, the following conditions have to be fulfilled:
•
•
SCLK must be low for a minimum tBEF before CSN falling edge and tlead afer CSN falling edge
SCLK must be low for a minimum tlag before CSN rising edge and tBEH afer CSN rising edge
tlead
tlag
tCSNH
tpCLK
0.8VDD
0.2VDD
CSN
SCLK
SDI
tSCLKH
tSCLKL
0.8VDD
0.2VDD
tSDI_hold
tSDI_setup
0.8VDD
0.2VDD
tENSDO
tVASDO
tDISSDO
0.8VDD
0.2VDD
SDO
Figure 20
SPI timing parameters
Datasheet
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TLE9140EQW
Preliminary datasheet
8 Serial Peripheral Interface - SPI
EN
EN
tSET_SPI
SPI
SPI
A) SPI message ignored
B) SPI message accepted
Figure 21
Setup time from EN rising edge to first SPI communication
The SPI error bit SPIE is reset under the following conditions:
•
•
The SPI error bit SPIE can be reset only In normal mode when the microcontroller must clear the SPIE bit in STAT
In stop mode the microcontroller must enter normal operation mode and clear the SPIE bit in STAT
Datasheet
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Preliminary datasheet
8 Serial Peripheral Interface - SPI
Case 1: Correct SCLK signal
Correct incoming clock signal
Correct clock during CSN rising edge
CSN
time
tBEF
tlead
tlag tBEH
SCLK
time
Case 2: Erroneous incoming clock signal
CSN
time
time
SCLK is High with CSN falling edge
SCLK
Case 3: Erroneous clock signal during CSN rising edge
CSN
time
time
Clock is High with CSN rising edge
SCLK
Figure 22
Polarity error
Datasheet
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Preliminary datasheet
8 Serial Peripheral Interface - SPI
8.5
Electrical characteristics SPI
Table 16
SPI electrical characteristics
VSM = 8.0 V to 60 V, VDD = 3 V to 5.5 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
SPI frequency
Maximum SPI
frequency
fSPI,max
–
–
4
MHz
–
–
P_SPI_01_01
P_SPI_01_02
Delay from EN rising edge to first SPI frame
SPI interface setup tSET_SPI
time
–
–
500
μs
SPI interface (SDI, SCLK, CSN)
High input voltage VIH1
threshold (VDD = 5
V)
2.5
1.5
–
–
–
–
–
–
V
V
V
V
VDD = 5 V
P_SPI_01_03
P_SPI_01_04
P_SPI_01_05
P_SPI_01_06
High input voltage VIH2
threshold (VDD =
3.3 V)
–
VDD = 3.3 V
VDD = 5 V
Low input voltage
threshold (VDD = 5
V)
VIL1
0.8
0.6
Low input voltage
threshold (VDD =
3.3 V)
VIL2
–
VDD = 3.3 V
Hysteresis of input VIHY1
100
100
–
–
–
–
mV
mV
VDD = 5 V
P_SPI_01_07
P_SPI_01_08
voltage (VDD = 5 V)
Hysteresis of input VIHY2
VDD = 3.3 V
voltage (VDD = 3.3
V)
Pull down resistor Rpd
at input pin ILx, IHx
25
25
25
–
40
40
40
–
60
60
60
10
kΩ
kΩ
kΩ
pF
–
P_SPI_01_09
P_SPI_01_10
P_SPI_01_11
P_SPI_01_12
Pull up resistor at
pin CSN
RPU_CSN
–
Pull down resistor RPD_SDI
,
–
at pin SDI, SCLK
RPD_SCLK
Input capacitance
at pin CSN, SDI and
SCLK
CI
0 V < VDD < 5.5 V
Input interface, logic outputs SDO
High output voltage VSDOH
level
VDD - 0.4 –
–
V
|ISDOH| = 1.6 mA
P_SPI_01_13
(table continues...)
Datasheet
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Preliminary datasheet
8 Serial Peripheral Interface - SPI
Table 16
(continued) SPI electrical characteristics
VSM = 8.0 V to 60 V, VDD = 3 V to 5.5 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
0.4
Low output voltage VSDOL
level
–
–
V
|ISDOL| = 1.6 mA
P_SPI_01_14
P_SPI_01_15
P_SPI_01_16
Tri-state leakage
current
ISDOLK
CSDO
-10
–
–
–
10
15
μA
pF
VCSN = VDD;
0 V < VSDO < VDD
Tri-state input
capacitance
–
Data input timing
SCLK period
tpCLK
250
–
–
–
ns
ns
–
–
P_SPI_01_17
P_SPI_01_18
SCLK high time
tSCLKH
0.45 *
tpCLK
0.55 *
tpCLK
SCLK low time
tSCLKL
0.45 *
tpCLK
–
0.55 *
tpCLK
ns
–
P_SPI_01_19
CSN setup time
SCLK setup time
tlead
tlag
250
250
125
–
–
–
–
–
–
ns
ns
ns
–
–
–
P_SPI_01_21
P_SPI_01_22
P_SPI_01_23
SCLK low afer CSN tBEH
high
SDI setup time
SDI hold time
tSDI_setup
tSDI_hold
trIN
100
50
–
–
–
–
–
ns
ns
ns
–
–
–
P_SPI_01_24
P_SPI_01_25
P_SPI_01_26
–
Input signal rise
time at pin SDI,
SCLK, CSN
50
Input signal fall
time at pin SDI,
SCLK, CSN
tfIN
–
3
–
–
50
–
ns
–
–
P_SPI_01_27
P_SPI_01_28
Minimum CSN high tCSNH
time
μs
Data output timing
SDO rise time
SDO fall time
trSDO
tfSDO
–
–
–
30
30
–
80
80
80
ns
ns
ns
CLoad = 100 pF
CLoad = 100 pF
–
P_SPI_01_29
P_SPI_01_30
P_SPI_01_31
SDO enable time
afer CSN falling
edge
tENSDO
SDO disable time
afer CSN
tDISSDO
–
–
50
ns
–
P_SPI_01_32
(table continues...)
Datasheet
52
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TLE9140EQW
Preliminary datasheet
8 Serial Peripheral Interface - SPI
Table 16
(continued) SPI electrical characteristics
VSM = 8.0 V to 60 V, VDD = 3 V to 5.5 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-Number
Min.
Max.
80
SDO valid time for tVASDO
VDD = 5 V
–
–
ns
VSDO < 0.2 * VDD
,
P_SPI_01_33
VSDO > 0.8 * VDD
Cload = 100 pF
Datasheet
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Preliminary datasheet
9 Register specification
9
Register specification
9.1
Register overview
Table 17
Register overview
Register short name
GENCTRL1
GENCTRL2
GENCTRL3
GENCTRL4
GENCTRL5
GENCTRL6
GENCTRL7
GENCTRL8
GENCTRL9
GENCTRL10
GENCTRL11
GENCTRL12
GENCTRL13
STAT
Register long name
General control register 1
General control register 2
General control register 3
General control register 4
General control register 5
General control register 6
General control register 7
General control register 8
General control register 9
General control register 10
General control register 11
General control register 12
General control register 13
General status register
STAT1
Global status register 1
STAT2
Global status register 2
STAT3
Global status register 3
STAT4
Global status register 4
STAT5
Effective high-side MOSFET turn-on delay PWM1
Effective high-side MOSFET turn-off delay PWM1
Effective low-side MOSFET turn-on delay PWM1
Effective low-side MOSFET turn-off delay PWM1
Effective high-side MOSFET turn-on delay PWM2
Effective high-side MOSFET turn-off delay PWM2
Effective low-side MOSFET turn-on delay PWM2
Effective low-side MOSFET turn-off delay PWM2
Effective high-side MOSFET turn-on delay PWM3
Effective high-side MOSFET turn-off delay PWM3
Effective low-side MOSFET turn-on delay PWM3
Effective low-side MOSFET turn-off delay PWM3
Effective high-side MOSFET rise time PWM1
STAT6
STAT7
STAT8
STAT9
STAT10
STAT11
STAT12
STAT13
STAT14
STAT15
STAT16
STAT17
(table continues...)
Datasheet
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Preliminary datasheet
9 Register specification
Table 17
(continued) Register overview
Register short name
STAT18
Register long name
Effective high-side MOSFET fall time PWM1
Effective low-side MOSFET rise time PWM1
Effective low-side MOSFET fall time PWM1
Effective high-side MOSFET rise time PWM2
Effective high-side MOSFET fall time PWM2
Effective low-side MOSFET rise time PWM2
Effective low-side MOSFET fall time PWM2
Effective high-side MOSFET rise time PWM3
Effective high-side MOSFET fall time PWM3
Effective low-side MOSFET rise time PWM3
Effective low-side MOSFET fall time PWM3
STAT19
STAT20
STAT21
STAT22
STAT23
STAT24
STAT25
STAT26
STAT27
STAT28
9.2
•
•
Control Registers
The control registers will be reset to default values afer power up or reset
There are different bit types:
-
-
'r' = READ: read only bits (or reserved bits)
'rw' = READ/WRITE: readable and writable bits
•
•
•
Reserved bits are marked as "Reserved" and always read as 0. The respective bits shall also be programmed as 0
Reading a register is done word wise by setting the SPI bit OP to 0 (= read only)
The SPI control registers are not cleared or changed automatically. It must be done by the microcontroller via SPI
programming
9.2.1
General control register 1
Table 18
General control register 1 (000 0001B) Reset value: 0010 0001B
7
6
5
HSLSOV_DIS
rw
4
3
IGx_SEL
rw
2
UNLOCK
rw
1
FMODE_1
rw
0
FMODE_0
rw
HBFREQ
rw
BD_EN
rw
DG
rw
Field
Bits
Type
Description
HBFREQ
7
rw
HB frequency
0B 37.5 MHz (default)
1B 18.75 MHz
BD_EN
6
rw
Bridge driver enable
0B the bridge driver is disabled
1B the bridge driver in enabled
(table continues...)
Datasheet
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Preliminary datasheet
9 Register specification
Table 18
(continued) General control register 1 (000 0001B) Reset value: 0010 0001B
HSLSOV_DIS
5
rw
Over-current protection
0B when VDS_HSx or VDS_LSx ≥ VDSTH, all gate drivers
will be switched off
1B when VDS_HSx or VDS_LSx ≥ VDSTH, the gate drivers
of the same half - bridge will be switch off (default)
DG
4
rw
Deglitch for high speed comparator
0B the deglitch feature is disabled (default)
1B the deglitch feature is enabled
Note: Enable deglitch feature can ignore small glitches at
the comparator input.
IGx_SEL
3
rw
Charge/discharge current extension bit:
0B keep the current set by corresponding bits (default)
1B enlarge all currents to max. 480 mA
Note: I represents the IPRECHG, ICHG, ICHGM, IHOLD,
IPREDISCHG, IDISCHG, IDISCHGM, IPOSTCHG and
IDISCHG_ST.
UNLOCK
FMODE
2
rw
rw
Unlock bit to disable the watchdog
0B WDDIS cannot be reset (default)
1B WDDIS can be reset in following SPI frame
[1:0]
Frequency modulation
00B no modulation
01B modulation frequency 15.6 kHz (default)
10B modulation frequency 31.2 kHz
11B modulation frequency 62.5 kHz
9.2.2
General control register 2
Table 19
General control register 2 (000 0010B) Reset value: x000 0100B
7
CHECKSUM
rw
6
RES
r
5
RES
r
4
RES
r
3
RES
r
2
1
0
WDPER
rw
Field
Bits
Type
Description
CHECKSUM
7
rw
Watchdog Setting Check Sum Bit
The sum of bits 6:0 needs to have even parity
0B counts as 0 for checksum calculation
1B counts as 1 for checksum calculation
RES
RES
RES
6
5
4
r
r
r
Reserved. Always read as 0
Reserved. Always read as 0
Reserved. Always read as 0
(table continues...)
Datasheet
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Preliminary datasheet
9 Register specification
Table 19
(continued) General control register 2 (000 0010B) Reset value: x000 0100B
RES
3
r
Reserved. Always read as 0
WDPER
[2:0]
rw
Watchdog period
000B 2 ms
001B 4 ms
010B 8 ms
011B 16 ms
100B 64 ms (default)
101B 128 ms
110B 256 ms
111B 512 ms
9.2.3
General control register 3
Table 20
General control register 3 (000 0011B) Reset value: 0000 0001B
7
6
5
HB3DIAG
rw
4
HB2DIAG
rw
3
HB1DIAG
rw
2
1
VDSTH
rw
0
WDDIS
rw
TWDIS
rw
Field
Bits
Type
Description
WDDIS
7
rw
Watchdog disable bit
0B the watchdog is enabled (default)
1B the watchdog is disabled if the previous SPI frame has set
UNLOCK bit (GENCTRL1)
Once the watchdog is disabled, it is directly re-enabled by
resetting WDDIS.
TWDIS
6
5
4
3
rw
rw
rw
rw
Thermal warning disable
0B TW is reported in GEF and set in global status register (default)
1B TW is not reported in GEF, but it is set in global status register
HB3DIAG
HB2DIAG
Control of HB3 off-state current source and current sink
0B pull-down deactivated (default)
1B pull-down activated
Control of HB2 off-state current source and current sink
0B pull-down deactivated (default)
1B pull-down activated
HB1DIAG
Control of HB1 off-state current source and current sink
0B pull-down deactivated (default)
1B pull-down activated
(table continues...)
Datasheet
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Preliminary datasheet
9 Register specification
Table 20
VDSTH
(continued) General control register 3 (000 0011B) Reset value: 0000 0001B
[2:0]
rw
Drain - source overvoltage threshold
000B : 145 mV
001B : 195 mV(default)
010B : 245 mV
011B : 295 mV
100B : 390 mV
101B : 490 mV
110B : 590 mV
111B : 2 V
9.2.4
General control register 4
Table 21
General control register 4 (000 0100B) Reset value: 0000 1111B
7
6
5
4
3
2
1
0
IPRECHG_T
IPRECHG
rw
rw
Field
Bits
Type
Description
IPRECHG_T
[7:6]
rw
Pre - charge time of HB1 - HB3
00B 100 ns (default)
01B 150 ns
10B 200 ns
11B 250 ns
Pre - charge current of HB1 - HB3
IGx_SEL = 0B
11.6 mA
14.8 mA
18.1 mA
21.3 mA
24.5 mA
27.7 mA
31.0 mA
34.2 mA
37.4 mA
40.6 mA
43.9 mA
47.1 mA
IGx_SEL = 1B
11.6 mA
15.8 mA
20.1 mA
24.3 mA
28.5 mA
32.7 mA
37.0 mA
41.2 mA
45.4 mA
49.7 mA
53.9 mA
58.1 mA
00 0000B
00 0001B
00 0010B
00 0011B
00 0100B
00 0101B
00 0110B
00 0111B
00 1000B
00 1001B
00 1010B
00 1011B
IPRECHG
[5:0]
rw
(table continues...)
Datasheet
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Preliminary datasheet
9 Register specification
Table 21
(continued) General control register 4 (000 0100B) Reset value: 0000 1111B
00 1100B
00 1101B
00 1110B
00 1111B (def.)
01 0000B
01 0001B
01 0010B
01 0011B
01 0100B
01 0101B
01 0110B
01 0111B
01 1000B
01 1001B
01 1010B
01 1011B
01 1100B
01 1101B
01 1110B
01 1111B
10 0000B
10 0001B
10 0010B
10 0011B
10 0100B
10 0101B
10 0110B
10 0111B
10 1000B
10 1001B
10 1010B
10 1011B
10 1100B
10 1101B
10 1110B
50.3 mA
62.4 mA
53.6 mA
66.6 mA
56.8 mA
70.8 mA
60.0 mA
75.0 mA
65.4 mA
82.1 mA
70.8 mA
89.3 mA
76.1 mA
96.4 mA
81.5 mA
103.5 mA
111.6 mA
117.8 mA
124.9 mA
132.0 mA
139.1 mA
146.3 mA
153.4 mA
160.5 mA
167.6 mA
174.8 mA
181.9 mA
189.0 mA
197.8 mA
206.6 mA
215.4 mA
224.2 mA
233.1 mA
241.9 mA
250.7 mA
259.5 mA
268.3 mA
277.1 mA
285.9 mA
294.7 mA
303.5 mA
312.3 mA
321.2 mA
86.9 mA
92.3 mA
97.6 mA
103.0 mA
108.4 mA
113.8 mA
119.1 mA
124.5 mA
129.9 mA
135.3 mA
140.6 mA
146.0 mA
152.9 mA
159.8 mA
166.6 mA
173.5 mA
180.4 mA
187.2 mA
194.1 mA
201.0 mA
207.9 mA
214.8 mA
221.6 mA
228.5 mA
235.4 mA
242.3 mA
249.1 mA
(table continues...)
Datasheet
59
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 21
(continued) General control register 4 (000 0100B) Reset value: 0000 1111B
10 1111B
11 0000B
11 0001B
11 0010B
11 0011B
11 0100B
11 0101B
11 0110B
11 0111B
11 1000B
11 1001B
11 1010B
11 1011B
11 1100B
11 1101B
11 1110B
11 1111B
256.0 mA
263.4 mA
270.9 mA
278.3 mA
285.8 mA
293.2 mA
300.6 mA
308.1 mA
315.5 mA
323.0 mA
330.4 mA
337.8 mA
345.3 mA
352.7 mA
360.2 mA
367.6 mA
375.0 mA
330.0 mA
339.4 mA
348.8 mA
358.1 mA
367.5 mA
376.8 mA
386.2 mA
395.6 mA
405.0 mA
414.4 mA
423.8 mA
433.1 mA
442.5 mA
451.9 mA
461.3 mA
470.6 mA
480.0 mA
9.2.5
General control register 5
Table 22
General control register 5 (000 0101B) Reset value: 0000 1111B
7
6
5
4
3
2
1
0
ICHG_T
ICHG
rw
rw
Field
Bits
Type
Description
ICHG_T
[7:6]
rw
Charge time of HB1 - HB3
00B 200 ns (default)
01B 400 ns
10B 600 ns
11B 800 ns
Charge current of HB1 - HB3
IGx_SEL = 0B
11.6 mA
IGx_SEL = 1B
11.6 mA
ICHG
[5:0]
rw
00 0000B
00 0001B
00 0010B
14.8 mA
15.8 mA
18.1 mA
20.1 mA
(table continues...)
Datasheet
60
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 22
(continued) General control register 5 (000 0101B) Reset value: 0000 1111B
00 0011B
00 0100B
00 0101B
00 0110B
00 0111B
00 1000B
00 1001B
00 1010B
00 1011B
00 1100B
00 1101B
00 1110B
00 1111B (def.)
01 0000B
01 0001B
01 0010B
01 0011B
01 0100B
01 0101B
01 0110B
01 0111B
01 1000B
01 1001B
01 1010B
01 1011B
01 1100B
01 1101B
01 1110B
01 1111B
10 0000B
10 0001B
10 0010B
10 0011B
10 0100B
10 0101B
21.3 mA
24.5 mA
27.7 mA
31.0 mA
34.2 mA
37.4 mA
40.6 mA
43.9 mA
47.1 mA
50.3 mA
53.6 mA
56.8 mA
60.0 mA
65.4 mA
70.8 mA
76.1 mA
81.5 mA
86.9 mA
92.3 mA
97.6 mA
103.0 mA
108.4 mA
113.8 mA
119.1 mA
124.5 mA
129.9 mA
135.3 mA
140.6 mA
146.0 mA
152.9 mA
159.8 mA
166.6 mA
173.5 mA
180.4 mA
187.2 mA
24.3 mA
28.5 mA
32.7 mA
37.0 mA
41.2 mA
45.4 mA
49.7 mA
53.9 mA
58.1 mA
62.4 mA
66.6 mA
70.8 mA
75.0 mA
82.1 mA
89.3 mA
96.4 mA
103.5 mA
111.6 mA
117.8 mA
124.9 mA
132.0 mA
139.1 mA
146.3 mA
153.4 mA
160.5 mA
167.6 mA
174.8 mA
181.9 mA
189.0 mA
197.8 mA
206.6 mA
215.4 mA
224.2 mA
233.1 mA
241.9 mA
(table continues...)
Datasheet
61
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 22
(continued) General control register 5 (000 0101B) Reset value: 0000 1111B
10 0110B
10 0111B
10 1000B
10 1001B
10 1010B
10 1011B
10 1100B
10 1101B
10 1110B
10 1111B
11 0000B
11 0001B
11 0010B
11 0011B
11 0100B
11 0101B
11 0110B
11 0111B
11 1000B
11 1001B
11 1010B
11 1011B
11 1100B
11 1101B
11 1110B
11 1111B
194.1 mA
201.0 mA
207.9 mA
214.8 mA
221.6 mA
228.5 mA
235.4 mA
242.3 mA
249.1 mA
256.0 mA
263.4 mA
270.9 mA
278.3 mA
285.8 mA
293.2 mA
300.6 mA
308.1 mA
315.5 mA
323.0 mA
330.4 mA
337.8 mA
345.3 mA
352.7 mA
360.2 mA
367.6 mA
375.0 mA
250.7 mA
259.5 mA
268.3 mA
277.1 mA
285.9 mA
294.7 mA
303.5 mA
312.3 mA
321.2 mA
330.0 mA
339.4 mA
348.8 mA
358.1 mA
367.5 mA
376.8 mA
386.2 mA
395.6 mA
405.0 mA
414.4 mA
423.8 mA
433.1 mA
442.5 mA
451.9 mA
461.3 mA
470.6 mA
480.0 mA
9.2.6
General control register 6
Table 23
General control register 6 (000 0110B) Reset value: 0000 1111B
7
6
5
4
3
2
1
0
GEF_CONFIG
IPOSTCHG
rw
rw
Field
Bits
Type
Description
(table continues...)
Datasheet
62
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 23
GEF_CONFIG
(continued) General control register 6 (000 0110B) Reset value: 0000 1111B
[7:6]
rw
Global Error Flag
00B GEF (default state)
01B BEMF1
10B BEMF2
11B BEMF3
Post - charge current of HB1 - HB3
IGx_SEL = 0B
IGx_SEL = 1B
11.6 mA
15.8 mA
20.1 mA
24.3 mA
28.5 mA
32.7 mA
37.0 mA
41.2 mA
45.4 mA
49.7 mA
53.9 mA
58.1 mA
62.4 mA
66.6 mA
70.8 mA
75.0 mA
82.1 mA
89.3 mA
96.4 mA
103.5 mA
111.6 mA
117.8 mA
124.9 mA
132.0 mA
139.1 mA
146.3 mA
153.4 mA
160.5 mA
00 0000B
00 0001B
00 0010B
00 0011B
00 0100B
00 0101B
00 0110B
00 0111B
00 1000B
00 1001B
00 1010B
00 1011B
00 1100B
00 1101B
00 1110B
00 1111B (def.)
01 0000B
01 0001B
01 0010B
01 0011B
01 0100B
01 0101B
01 0110B
01 0111B
01 1000B
01 1001B
01 1010B
01 1011B
11.6 mA
14.8 mA
18.1 mA
21.3 mA
24.5 mA
27.7 mA
31.0 mA
34.2 mA
37.4 mA
40.6 mA
43.9 mA
47.1 mA
50.3 mA
53.6 mA
56.8 mA
60.0 mA
65.4 mA
70.8 mA
76.1 mA
81.5 mA
86.9 mA
92.3 mA
97.6 mA
103.0 mA
108.4 mA
113.8 mA
119.1 mA
124.5 mA
IPOSTCHG
[5:0]
rw
(table continues...)
Datasheet
63
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 23
(continued) General control register 6 (000 0110B) Reset value: 0000 1111B
01 1100B
01 1101B
01 1110B
01 1111B
10 0000B
10 0001B
10 0010B
10 0011B
10 0100B
10 0101B
10 0110B
10 0111B
10 1000B
10 1001B
10 1010B
10 1011B
10 1100B
10 1101B
10 1110B
10 1111B
11 0000B
11 0001B
11 0010B
11 0011B
11 0100B
11 0101B
11 0110B
11 0111B
11 1000B
11 1001B
11 1010B
11 1011B
11 1100B
11 1101B
11 1110B
129.9 mA
135.3 mA
140.6 mA
146.0 mA
152.9 mA
159.8 mA
166.6 mA
173.5 mA
180.4 mA
187.2 mA
194.1 mA
201.0 mA
207.9 mA
214.8 mA
221.6 mA
228.5 mA
235.4 mA
242.3 mA
249.1 mA
256.0 mA
263.4 mA
270.9 mA
278.3 mA
285.8 mA
293.2 mA
300.6 mA
308.1 mA
315.5 mA
323.0 mA
330.4 mA
337.8 mA
345.3 mA
352.7 mA
360.2 mA
367.6 mA
167.6 mA
174.8 mA
181.9 mA
189.0 mA
197.8 mA
206.6 mA
215.4 mA
224.2 mA
233.1 mA
241.9 mA
250.7 mA
259.5 mA
268.3 mA
277.1 mA
285.9 mA
294.7 mA
303.5 mA
312.3 mA
321.2 mA
330.0 mA
339.4 mA
348.8 mA
358.1 mA
367.5 mA
376.8 mA
386.2 mA
395.6 mA
405.0 mA
414.4 mA
423.8 mA
433.1 mA
442.5 mA
451.9 mA
461.3 mA
470.6 mA
(table continues...)
Datasheet
64
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 23
(continued) General control register 6 (000 0110B) Reset value: 0000 1111B
11 1111B 375.0 mA 480.0 mA
9.2.7
General control register 7
Table 24
General control register 7 (000 0111B) Reset value: 0000 1111B
7
6
5
4
3
2
1
0
IPREDISCHG_T
IPREDISCHG
rw
rw
Field
Bits
Type
Description
IPREDISCHG_T
[7:6]
rw
Pre - discharge time of HB1 - HB3
00B 100 ns (default)
01B 150 ns
10B 200 ns
11B 250 ns
Pre - discharge current of HB1 - HB3
IGx_SEL = 0B
11.6 mA
IGx_SEL = 1B
11.6 mA
15.8 mA
20.1 mA
24.3 mA
28.5 mA
32.7 mA
37.0 mA
41.2 mA
45.4 mA
49.7 mA
53.9 mA
58.1 mA
62.4 mA
66.6 mA
70.8 mA
75.0 mA
82.1 mA
89.3 mA
96.4 mA
00 0000B
00 0001B
00 0010B
00 0011B
00 0100B
00 0101B
00 0110B
00 0111B
00 1000B
00 1001B
00 1010B
00 1011B
00 1100B
00 1101B
00 1110B
00 1111B (def.)
01 0000B
01 0001B
01 0010B
14.8 mA
18.1 mA
21.3 mA
24.5 mA
27.7 mA
31.0 mA
34.2 mA
37.4 mA
40.6 mA
43.9 mA
47.1 mA
50.3 mA
53.6 mA
56.8 mA
60.0 mA
65.4 mA
70.8 mA
76.1 mA
IPREDISCHG
[5:0]
rw
(table continues...)
Datasheet
65
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 24
(continued) General control register 7 (000 0111B) Reset value: 0000 1111B
01 0011B
01 0100B
01 0101B
01 0110B
01 0111B
01 1000B
01 1001B
01 1010B
01 1011B
01 1100B
01 1101B
01 1110B
01 1111B
10 0000B
10 0001B
10 0010B
10 0011B
10 0100B
10 0101B
10 0110B
10 0111B
10 1000B
10 1001B
10 1010B
10 1011B
10 1100B
10 1101B
10 1110B
10 1111B
11 0000B
11 0001B
11 0010B
11 0011B
11 0100B
11 0101B
81.5 mA
103.5 mA
111.6 mA
117.8 mA
124.9 mA
132.0 mA
139.1 mA
146.3 mA
153.4 mA
160.5 mA
167.6 mA
174.8 mA
181.9 mA
189.0 mA
197.8 mA
206.6 mA
215.4 mA
224.2 mA
233.1 mA
241.9 mA
250.7 mA
259.5 mA
268.3 mA
277.1 mA
285.9 mA
294.7 mA
303.5 mA
312.3 mA
321.2 mA
330.0 mA
339.4 mA
348.8 mA
358.1 mA
367.5 mA
376.8 mA
386.2 mA
86.9 mA
92.3 mA
97.6 mA
103.0 mA
108.4 mA
113.8 mA
119.1 mA
124.5 mA
129.9 mA
135.3 mA
140.6 mA
146.0 mA
152.9 mA
159.8 mA
166.6 mA
173.5 mA
180.4 mA
187.2 mA
194.1 mA
201.0 mA
207.9 mA
214.8 mA
221.6 mA
228.5 mA
235.4 mA
242.3 mA
249.1 mA
256.0 mA
263.4 mA
270.9 mA
278.3 mA
285.8 mA
293.2 mA
300.6 mA
(table continues...)
Datasheet
66
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 24
(continued) General control register 7 (000 0111B) Reset value: 0000 1111B
11 0110B
11 0111B
11 1000B
11 1001B
11 1010B
11 1011B
11 1100B
11 1101B
11 1110B
11 1111B
308.1 mA
315.5 mA
323.0 mA
330.4 mA
337.8 mA
345.3 mA
352.7 mA
360.2 mA
367.6 mA
375.0 mA
395.6 mA
405.0 mA
414.4 mA
423.8 mA
433.1 mA
442.5 mA
451.9 mA
461.3 mA
470.6 mA
480.0 mA
9.2.8
General control register 8
Table 25
General control register 8 (000 1000B) Reset value: 0000 1111B
7
6
5
4
3
2
1
0
IHOLD
IDISCHG
rw
rw
Field
Bits
Type
Description
Gate driver hold current IHOLD
IGx_SEL = 0B
11.6 mA
IGx_SEL = 1B
11.6 mA
00B (def.)
IHOLD
[7:6]
rw
01B
27.7 mA
32.7 mA
10B
40.6 mA
49.7 mA
11B
50.3 mA
62.4 mA
Discharge current of HB1 - HB3
IGx_SEL = 0B
11.6 mA
14.8 mA
18.1 mA
21.3 mA
24.5 mA
27.7 mA
31.0 mA
34.2 mA
37.4 mA
IGx_SEL = 1B
11.6 mA
15.8 mA
20.1 mA
24.3 mA
28.5 mA
32.7 mA
37.0 mA
41.2 mA
45.4 mA
00 0000B
00 0001B
00 0010B
00 0011B
00 0100B
00 0101B
00 0110B
00 0111B
00 1000B
IDISCHG
[5:0]
rw
(table continues...)
Datasheet
67
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 25
(continued) General control register 8 (000 1000B) Reset value: 0000 1111B
00 1001B
00 1010B
00 1011B
00 1100B
00 1101B
00 1110B
00 1111B (def.)
01 0000B
01 0001B
01 0010B
01 0011B
01 0100B
01 0101B
01 0110B
01 0111B
01 1000B
01 1001B
01 1010B
01 1011B
01 1100B
01 1101B
01 1110B
01 1111B
10 0000B
10 0001B
10 0010B
10 0011B
10 0100B
10 0101B
10 0110B
10 0111B
10 1000B
10 1001B
10 1010B
10 1011B
40.6 mA
43.9 mA
47.1 mA
50.3 mA
53.6 mA
56.8 mA
60.0 mA
65.4 mA
70.8 mA
76.1 mA
81.5 mA
86.9 mA
92.3 mA
97.6 mA
103.0 mA
108.4 mA
113.8 mA
119.1 mA
124.5 mA
129.9 mA
135.3 mA
140.6 mA
146.0 mA
152.9 mA
159.8 mA
166.6 mA
173.5 mA
180.4 mA
187.2 mA
194.1 mA
201.0 mA
207.9 mA
214.8 mA
221.6 mA
228.5 mA
49.7 mA
53.9 mA
58.1 mA
62.4 mA
66.6 mA
70.8 mA
75.0 mA
82.1 mA
89.3 mA
96.4 mA
103.5 mA
111.6 mA
117.8 mA
124.9 mA
132.0 mA
139.1 mA
146.3 mA
153.4 mA
160.5 mA
167.6 mA
174.8 mA
181.9 mA
189.0 mA
197.8 mA
206.6 mA
215.4 mA
224.2 mA
233.1 mA
241.9 mA
250.7 mA
259.5 mA
268.3 mA
277.1 mA
285.9 mA
294.7 mA
(table continues...)
Datasheet
68
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 25
(continued) General control register 8 (000 1000B) Reset value: 0000 1111B
10 1100B
10 1101B
10 1110B
10 1111B
11 0000B
11 0001B
11 0010B
11 0011B
11 0100B
11 0101B
11 0110B
11 0111B
11 1000B
11 1001B
11 1010B
11 1011B
11 1100B
11 1101B
11 1110B
11 1111B
235.4 mA
242.3 mA
249.1 mA
256.0 mA
263.4 mA
270.9 mA
278.3 mA
285.8 mA
293.2 mA
300.6 mA
308.1 mA
315.5 mA
323.0 mA
330.4 mA
337.8 mA
345.3 mA
352.7 mA
360.2 mA
367.6 mA
375.0 mA
303.5 mA
312.3 mA
321.2 mA
330.0 mA
339.4 mA
348.8 mA
358.1 mA
367.5 mA
376.8 mA
386.2 mA
395.6 mA
405.0 mA
414.4 mA
423.8 mA
433.1 mA
442.5 mA
451.9 mA
461.3 mA
470.6 mA
480.0 mA
9.2.9
General control register 9
Table 26
General control register 9 (000 1001B) Reset value: 0000 1111B
7
6
5
4
3
2
1
0
CPEN
rw
CPREC
rw
ICHGM
rw
Field
Bits
Type
Description
CPEN
7
rw
Charge pump enable
0B disable CP1 and CP2 modules (default)
1B enable CP1 and CP2 modules
CPREC
6
rw
Charge pump automatic recovery enable
0B disable the automatic recovery for CP1 and CP2 when VSM lef OV/UV
conditions (default)
1B enable the automatic recovery for CP1 and CP2 when VSM lef OV/UV
conditions
(table continues...)
Datasheet
69
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 26
(continued) General control register 9 (000 1001B) Reset value: 0000 1111B
Middle charge current of HB1 - HB3
IGx_SEL = 0B
IGx_SEL = 1B
11.6 mA
15.8 mA
20.1 mA
24.3 mA
28.5 mA
32.7 mA
37.0 mA
41.2 mA
45.4 mA
49.7 mA
53.9 mA
58.1 mA
62.4 mA
66.6 mA
70.8 mA
75.0 mA
82.1 mA
89.3 mA
96.4 mA
103.5 mA
111.6 mA
117.8 mA
124.9 mA
132.0 mA
139.1 mA
146.3 mA
153.4 mA
160.5 mA
167.6 mA
174.8 mA
181.9 mA
189.0 mA
197.8 mA
00 0000B
00 0001B
00 0010B
00 0011B
00 0100B
00 0101B
00 0110B
00 0111B
00 1000B
00 1001B
00 1010B
00 1011B
00 1100B
00 1101B
00 1110B
00 1111B (def.)
01 0000B
01 0001B
01 0010B
01 0011B
01 0100B
01 0101B
01 0110B
01 0111B
01 1000B
01 1001B
01 1010B
01 1011B
01 1100B
01 1101B
01 1110B
01 1111B
10 0000B
11.6 mA
14.8 mA
18.1 mA
21.3 mA
24.5 mA
27.7 mA
31.0 mA
34.2 mA
37.4 mA
40.6 mA
43.9 mA
47.1 mA
50.3 mA
53.6 mA
56.8 mA
60.0 mA
65.4 mA
70.8 mA
76.1 mA
81.5 mA
86.9 mA
92.3 mA
97.6 mA
103.0 mA
108.4 mA
113.8 mA
119.1 mA
124.5 mA
129.9 mA
135.3 mA
140.6 mA
146.0 mA
152.9 mA
ICHGM
[5:0]
rw
(table continues...)
Datasheet
70
Rev. 0.05
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Preliminary datasheet
9 Register specification
Table 26
(continued) General control register 9 (000 1001B) Reset value: 0000 1111B
10 0001B
10 0010B
10 0011B
10 0100B
10 0101B
10 0110B
10 0111B
10 1000B
10 1001B
10 1010B
10 1011B
10 1100B
10 1101B
10 1110B
10 1111B
11 0000B
11 0001B
11 0010B
11 0011B
11 0100B
11 0101B
11 0110B
11 0111B
11 1000B
11 1001B
11 1010B
11 1011B
11 1100B
11 1101B
11 1110B
11 1111B
159.8 mA
166.6 mA
173.5 mA
180.4 mA
187.2 mA
194.1 mA
201.0 mA
207.9 mA
214.8 mA
221.6 mA
228.5 mA
235.4 mA
242.3 mA
249.1 mA
256.0 mA
263.4 mA
270.9 mA
278.3 mA
285.8 mA
293.2 mA
300.6 mA
308.1 mA
315.5 mA
323.0 mA
330.4 mA
337.8 mA
345.3 mA
352.7 mA
360.2 mA
367.6 mA
375.0 mA
206.6 mA
215.4 mA
224.2 mA
233.1 mA
241.9 mA
250.7 mA
259.5 mA
268.3 mA
277.1 mA
285.9 mA
294.7 mA
303.5 mA
312.3 mA
321.2 mA
330.0 mA
339.4 mA
348.8 mA
358.1 mA
367.5 mA
376.8 mA
386.2 mA
395.6 mA
405.0 mA
414.4 mA
423.8 mA
433.1 mA
442.5 mA
451.9 mA
461.3 mA
470.6 mA
480.0 mA
9.2.10
General control register 10
Table 27
General control register 10 (000 1010B) Reset value: 0000 1111B
7
6
5
4
3
2
1
0
(table continues...)
Datasheet
71
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Preliminary datasheet
9 Register specification
Table 27
TFBEMF
(continued) General control register 10 (000 1010B) Reset value: 0000 1111B
IDISCHGM
rw
rw
Field
Bits
Type
Description
TFBEMF
[7:6]
rw
Back EMF filter time
00B 0.5 μs (def.)
01B 1 μs
10B 2 μs
11B 3 μs
Middle discharge current of HB1 - HB3
IGx_SEL = 0B
IGx_SEL = 1B
11.6 mA
15.8 mA
20.1 mA
24.3 mA
28.5 mA
32.7 mA
37.0 mA
41.2 mA
45.4 mA
49.7 mA
53.9 mA
58.1 mA
62.4 mA
66.6 mA
70.8 mA
75.0 mA
82.1 mA
89.3 mA
96.4 mA
103.5 mA
111.6 mA
117.8 mA
124.9 mA
132.0 mA
00 0000B
00 0001B
00 0010B
00 0011B
00 0100B
00 0101B
00 0110B
00 0111B
00 1000B
00 1001B
00 1010B
00 1011B
00 1100B
00 1101B
00 1110B
00 1111B (def.)
01 0000B
01 0001B
01 0010B
01 0011B
01 0100B
01 0101B
01 0110B
01 0111B
11.6 mA
14.8 mA
18.1 mA
21.3 mA
24.5 mA
27.7 mA
31.0 mA
34.2 mA
37.4 mA
40.6 mA
43.9 mA
47.1 mA
50.3 mA
53.6 mA
56.8 mA
60.0 mA
65.4 mA
70.8 mA
76.1 mA
81.5 mA
86.9 mA
92.3 mA
97.6 mA
103.0 mA
IDISCHGM
[5:0]
rw
(table continues...)
Datasheet
72
Rev. 0.05
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TLE9140EQW
Preliminary datasheet
9 Register specification
Table 27
(continued) General control register 10 (000 1010B) Reset value: 0000 1111B
01 1000B
01 1001B
01 1010B
01 1011B
01 1100B
01 1101B
01 1110B
01 1111B
10 0000B
10 0001B
10 0010B
10 0011B
10 0100B
10 0101B
10 0110B
10 0111B
10 1000B
10 1001B
10 1010B
10 1011B
10 1100B
10 1101B
10 1110B
10 1111B
11 0000B
11 0001B
11 0010B
11 0011B
11 0100B
11 0101B
11 0110B
11 0111B
11 1000B
11 1001B
11 1010B
108.4 mA
113.8 mA
119.1 mA
124.5 mA
129.9 mA
135.3 mA
140.6 mA
146.0 mA
152.9 mA
159.8 mA
166.6 mA
173.5 mA
180.4 mA
187.2 mA
194.1 mA
201.0 mA
207.9 mA
214.8 mA
221.6 mA
228.5 mA
235.4 mA
242.3 mA
249.1 mA
256.0 mA
263.4 mA
270.9 mA
278.3 mA
285.8 mA
293.2 mA
300.6 mA
308.1 mA
315.5 mA
323.0 mA
330.4 mA
337.8 mA
139.1 mA
146.3 mA
153.4 mA
160.5 mA
167.6 mA
174.8 mA
181.9 mA
189.0 mA
197.8 mA
206.6 mA
215.4 mA
224.2 mA
233.1 mA
241.9 mA
250.7 mA
259.5 mA
268.3 mA
277.1 mA
285.9 mA
294.7 mA
303.5 mA
312.3 mA
321.2 mA
330.0 mA
339.4 mA
348.8 mA
358.1 mA
367.5 mA
376.8 mA
386.2 mA
395.6 mA
405.0 mA
414.4 mA
423.8 mA
433.1 mA
(table continues...)
Datasheet
73
Rev. 0.05
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TLE9140EQW
Preliminary datasheet
9 Register specification
Table 27
(continued) General control register 10 (000 1010B) Reset value: 0000 1111B
11 1011B
11 1100B
11 1101B
11 1110B
11 1111B
345.3 mA
352.7 mA
360.2 mA
367.6 mA
375.0 mA
442.5 mA
451.9 mA
461.3 mA
470.6 mA
480.0 mA
9.2.11
General control register 11
Table 28
General control register 11 (000 1011B) Reset value: 0000 1111B
7
6
TFVDS
rw
5
4
3
2
1
0
IDISCHG_ST
rw
Field
Bits Type
Description
Drain - source overvoltage filter time of HB1 - HB3
000B 0.25 μs (def.)
001B 0.50 μs
010B 0.75 μs
TFVDS
[7:5]
rw 011B 1.00 μs
100B 1.25 μs
101B 1.50 μs
110B 1.75 μs
111B 2.00 μs
Static discharge current of HB1 - HB3
IGx_SEL = 0B
IGx_SEL = 1B
15.8 mA
24.3 mA
32.7 mA
41.2 mA
49.7 mA
58.1 mA
66.6 mA
75.0 mA
89.3 mA
103.5 mA
117.8 mA
0 0000B
0 0001B
14.8 mA
21.3 mA
27.7 mA
34.3 mA
40.6 mA
47.1 mA
53.6 mA
60.0 mA
70.8 mA
81.5 mA
92.3 mA
0 0010B
0 0011B
IDISCHG_ST
[4:0]
rw 0 0100B
0 0101B
0 0110B
0 0111B
0 1000B
0 1001B
0 1010B
(table continues...)
Datasheet
74
Rev. 0.05
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TLE9140EQW
Preliminary datasheet
9 Register specification
Table 28
(continued) General control register 11 (000 1011B) Reset value: 0000 1111B
0 1011B
0 1100B
0 1101B
0 1110B
0 1111B (def.)
1 0000B
1 0001B
1 0010B
1 0011B
1 0100B
1 0101B
1 0110B
1 0111B
1 1000B
1 1001B
1 1010B
1 1011B
1 1100B
1 1101B
1 1110B
1 1111B
103.0 mA
113.8 mA
124.5 mA
135.3 mA
146.0 mA
159.8 mA
173.5 mA
187.2 mA
210.0 mA
214.8 mA
228.5 mA
242.3 mA
256.0 mA
270.9 mA
285.8 mA
300.6 mA
315.5 mA
330.4 mA
345.3 mA
360.20 mA
375.0 mA
132.0 mA
146.3 mA
160.5 mA
174.8 mA
189.0 mA
206.6 mA
224.2 mA
241.9 mA
259.5 mA
277.1 mA
294.7 mA
312.3 mA
330.0 mA
348.8 mA
367.5 mA
386.2 mA
405.0 mA
423.8 mA
442.5mA
461.3 mA
480.0 mA
9.2.12
General control register 12
Table 29
General control register 12 (000 1100B) Reset value: 0001 1011B
7
6
5
4
3
2
1
0
RES
IPREDISCHG
_T_XT
TBLK
TCCP
r
rw
rw
rw
Field
RES
Bits
Type
Description
Reserved. Always read as 0
7
r
(table continues...)
Datasheet
75
Rev. 0.05
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Preliminary datasheet
9 Register specification
Table 29
(continued) General control register 12 (000 1100B) Reset value: 0001 1011B
IPREDISCHG_T_XT
6
rw
Extended pre-discharge time
0B keep the pre-discharge time defined
by IPREDISCHG_T (default)
1B extend the pre-discharge time to 300ns when
IPREDISCHG_T = 00B 350 ns when IPREDISCHG_T = 01B
400 ns when IPREDISCHG_T = 10B
450 ns when IPREDISCHG_T = 11B
TBLK
[5:3]
rw
Blank time tBLANK for HB1 - HB3
000B 0.5 μs
001B 1.0 μs
010B 1.5 μs
011B 2.0 μs (def.)
100B 2.5 μs
101B 3.0 μs
110B 3.5 μs
111B 4.0 μs
TCCP
[2:0]
rw
Cross current protection tCCP for HB1 - HB3
000B 0.5 μs
001B 1.0 μs
010B 1.5 μs
011B 2.0 μs (def.)
100B 2.5 μs
101B 3.0 μs
110B 3.5 μs
111B 4.0 μs
9.2.13
General control register 13
Table 30
General control register 13 (000 1101B) Reset value: 0000 0011B
7
RES
r
6
LSAFW_CFG
rw
5
4
3
VSMOV_CFG
rw
2
1
VSM_COVUVTH
rw
0
LSAFW
rw
Field
RES
Bits
7
Type
r
Description
Reserved. Always read as 0
LSAFW_CFG
6
rw
Overvoltage low-side freewheeling enable bit
0B switch off MOSFETs if VSMOV = 1 (default)
1B activate low-side freewheeling if VSMOV = 1
(table continues...)
Datasheet
76
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Preliminary datasheet
9 Register specification
Table 30
(continued) General control register 13 (000 1101B) Reset value: 0000 0011B
LSAFW
[5:4]
rw
Low-side freewheeling set up bit:
00B all low-side MOSFETs are switched on for
freewheeling if VSMOV = 1 (default)
01B only LS1 is switched on for freewheeling if VSMOV = 1
10B only LS2 is switched on for freewheeling if VSMOV = 1
11B only LS3 is switched on for freewheeling if VSMOV = 1
VSMOV_CFG
3
rw
rw
Configurable overvoltage/undervoltage enable bit:
0B when VSM reaches VSM_COVUVTH, the VSMOV is set
and the overvoltage event is reported in GEF (default)
1B when VSM reaches VSM_COVUVTH, the overvoltage
event is ignored
VSM_COVUVTH
[2:0]
Configurable overvoltage/undervoltage thresholds:
000B OV: 56 V, UV: 18.5 V
001B OV: 58 V, UV: 18.5 V
010B OV: 60 V, UV: 18.5 V
011B OV: 62 V, UV: 18.5 V (default)
100B OV: 51 V, UV: 7.0 V
101B keep the latest configuration settings
110B keep the latest configuration settings
111B keep the latest configuration settings
9.3
•
Status registers
One 16-bit SPI command consists of two bytes (see Figure 18):
-
-
The 7-bit address and one additional bit for the register access mode and
Following the data byte
•
There are two different bit types:
-
-
'r' = READ: read only bits (or reserved bits)
'rc' = READ/CLEAR: readable and clearable bits
•
•
•
Reading a register is done word wise by setting the SPI bit OP to 0 (= read only)
Clearing a register is done word wise by setting the SPI bit OP to 1. No single bits can be cleared
The SPI status registers are in general not cleared automatically. It must be done by the microcontroller via SPI
command
Table 31
General control register 14 (010 1011B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
RES
RES
RES
RES
RES
BEMF_PROC
ESSING_EN
BEMF_BT_TFILT_SEL
r
r
r
r
r
rw
rw
Field
RES
Bits
Type
Description
Reserved. Always read as 0
7
r
(table continues...)
Datasheet
77
Rev. 0.05
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Preliminary datasheet
9 Register specification
Table 31
(continued) General control register 14 (010 1011B) Reset value: 0000 0000B
RES
RES
RES
RES
6
5
4
3
2
r
r
Reserved. Always read as 0
Reserved. Always read as 0
Reserved. Always read as 0
Reserved. Always read as 0
r
r
BEMF_PROCESSING_EN
rw
BEMF processing enable bit:
0B BEMF processing algorithm is disabled (default)
1B BEMF processing algorithm is enabled
BEMF_BT_TFILT_SEL
[1:0]
rw
HB Blanking time for BEMF comparator output signal
00B 6 µs (default)
01B 8 µs
10B 12 µs
11B 16 µs
9.3.1
General status register
Table 32
General status register (000 1110B) Reset value: 0000 0000B
7
RES
r
6
DSOV
r
5
SUPE
r
4
INE
r
3
TE
r
2
nPOR
rc
1
0
SPIE
rc
ST
rc
Field
RES
Bits
7
Type
Description
r
r
Reserved. Always read as 0
VDS monitoring bit
DSOV
6
0B no VDS error is detected (default)
1B VDS error is detected
SUPE
INE
5
4
3
2
r
r
Supply error bit
0B no supply error is detected (default)
1B supply error is detected
Input error bit
0B no input error is detected (default)
1B input error is detected
TE
r
Temperature error bit
0B no thermal shutdown and no thermal warning is detected (default)
1B a thermal shutdown or a thermal warning is detected
nPOR
rc
Negative Power-On-Reset bit
0B a Power-On-Reset is detected (default)
1B no Power-On-Reset (afer clear)
(table continues...)
Datasheet
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Preliminary datasheet
9 Register specification
Table 32
ST
(continued) General status register (000 1110B) Reset value: 0000 0000B
1
rc
Stop mode bit
0B The device is not in stop mode state (default)
1B The device is in stop mode state
SPIE
0
rc
SPI protocol error bit
0B No SPI protocol error is detected (default)
1B A SPI protocol error is detected
9.3.2
Global status register 1
Table 33
Global status register 1 (000 1111B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
RES
TW
TSD
CP1UV
CP2UV
VSMOV_PRO
T
VSMOV
VSMUV
rc
rc
rc
rc
rc
rc
rc
rc
Field
RES
TW
Bits
7
Type
rc
Description
Reserved. Always read as 0
Thermal warning
6
rc
0B no thermal warning is detected (default)
1B a thermal warning is detected
TSD
5
4
3
2
1
0
rc
rc
rc
rc
rc
rc
Thermal shutdown
0B no thermal shutdown is detected (default)
1B a thermal shutdown is detected
CP1UV
CP2UV
Charge pump 1 undervoltage
0B no charge pump 1 undervoltage detected (default)
1B charge pump 1 undervoltage detected
Charge pump 2 undervoltage
0B no charge pump 2 undervoltage detected (default)
1B charge pump 2 undervoltage detected
VSMOV_PRO
T
VSM overvoltage Bit
0B VSM doesn't reach the hard OV threshold (default)
1B VSM reaches the hard OV threshold
VSMOV
VSMUV
VSM overvoltage Bit
0B no VSM Overvoltage is detected (default)
1B VSM Overvoltage is detected
VSM undervoltage Bit
0B no VSM Undervoltage is detected (default)
1B VSM Undervoltage is detected
Datasheet
79
Rev. 0.05
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Preliminary datasheet
9 Register specification
9.3.3
Global status register 2
Table 34
Global status register 2 (001 0000B) Reset value: 0000 0000B
7
6
5
LS3DSOV
rc
4
HS3DSOV
rc
3
LS2DSOV
rc
2
HS2DSOV
rc
1
LS1DSOV
rc
0
HS1DSOV
rc
WDMON
r
Field
Bits
Type
Description
WDMON
[7:6]
r
Watchdog monitoring
00B WD timer is between [0%;25%] of the WD period (default)
01B WD timer is between [25%;50%] of the WD period
10B WD timer is between [50%;75%] of the WD period
11B WD timer is between [75%;100%] of the WD period
LS3DSOV
HS3DSOV
LS2DSOV
HS2DSOV
LS1DSOV
HS1DSOV
5
4
3
2
1
0
rc
rc
rc
rc
rc
rc
Drain-source overvoltage on low side 3
0B no overvoltage on DS of low side 3 (default)
1B overvoltage on DS of low side 3 is detected
Drain-source overvoltage on high side 3
0B no overvoltage on DS of high side 3 (default)
1B overvoltage on DS of high side 3 is detected
Drain-source overvoltage on low side 2
0B no overvoltage on DS of low side 2 (default)
1B overvoltage on DS of low side 2 is detected
Drain-source overvoltage on high side 2
0B no overvoltage on DS of high side 2 (default)
1B overvoltage on DS of high side 2 is detected
Drain-source overvoltage on low side 1
0B no overvoltage on DS of low side 1 (default)
1B overvoltage on DS of low side 1 is detected
Drain-source overvoltage on high side 1
0B no overvoltage on DS of high side 1 (default)
1B overvoltage on DS of high side 1 is detected
9.3.4
Global status register 3
Table 35
Global status register 3 (001 0001B) Reset value: 0000 0000B
7
RES
r
6
RES
r
5
INE1
rc
4
INE2
rc
3
INE3
rc
2
1
0
HS3VOUT
HS2VOUT
HS1VOUT
r
r
r
Filed
Bits
Type
Description
(table continues...)
Datasheet
80
Rev. 0.05
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Preliminary datasheet
9 Register specification
Table 35
(continued) Global status register 3 (001 0001B) Reset value: 0000 0000B
RES
[7:6]
5
r
Reserved. Always read as 0
INE1
rc
Input 1 error
0B no input 1 error is detected (default)
1B IH1 and IL1 are high
INE2
INE3
4
3
2
rc
rc
r
Input 2 error
0B no input 2 error is detected (default)
1B IH2 and IL2 are high
Input 3 error
0B no input 1 error is detected (default)
1B IH3 and IL3 are high
HS3VOUT
Voltage level at SH3 when (IH3, IL3) = (0,0)
0B low: |VSH3 - GND| < VSHL
1B high: |VSH3 - GND| > VSHL
Note: HB3VOUT = 0 if (IH3, IL3) = (1,0) or (0,1).
HS2VOUT
HS1VOUT
1
0
r
r
Voltage level at SH2 when (IH2, IL2) = (0,0)
0B low: |VSH2 - GND| < VSHL
1B high: |VSH2 - GND| > VSHL
Note: HB2VOUT = 0 if (IH2, IL2) = (1,0) or (0,1).
Voltage level at SH1 when (IH1, IL1) = (0,0)
0B low: |VSH1 - GND| < VSHL
1B high: |VSH1 - GND| > VSHL
Note: HB1VOUT = 0 if (IH1, IL1) = (1,0) or (0,1).
9.3.5
Global status register 4
Table 36
Global status register 4 (001 0010B) Reset value: 0000 0000B
7
6
5
RES
r
4
3
2
BEMF3
r
1
BEMF2
r
0
BEMF1
r
Field
RES
Bits
Type
Description
[7:3]
r
Reserved. Always read as 0
(table continues...)
Datasheet
81
Rev. 0.05
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Preliminary datasheet
9 Register specification
Table 36
BEMF3
(continued) Global status register 4 (001 0010B) Reset value: 0000 0000B
2
1
0
r
r
r
Signal for BEMF3
1B VSHM3 > (VSHM1 + VSHM2)/2
0B VSHM3 < (VSHM1 + VSHM2)/2
Note:
If the BEMF_POCESSING_EN bit is set to 0B, the BEMF3 will be real time
signal.
If the BEMF_POCESSING_EN bit is set to 1B, the BEMF3 will be the
output signal with the post-processing algorithm.
When BD_EN = 0B, the BEMF3 = 0B
BEMF2
Signal for BEMF2
1B VSHM2 > (VSHM1 + VSHM3)/2
0B VSHM2 < (VSHM1 + VSHM3)/2
Note:
If the BEMF_POCESSING_EN bit is set to 0B, the BEMF2 will be real time
signal.
If the BEMF_POCESSING_EN bit is set to 1B, the BEMF2 will be the
output signal with the post-processing algorithm.
When BD_EN = 0B, the BEMF2 = 0B
BEMF1
Signal for BEMF1
1B VSHM1 > (VSHM2 + VSHM3)/2
0B VSHM1 < (VSHM2 + VSHM3)/2
Note:
If the BEMF_POCESSING_EN bit is set to 0B, the BEMF1 will be real time
signal.
If the BEMF_POCESSING_EN bit is set to 1B, the BEMF1 will be the
output signal with the post-processing algorithm.
When BD_EN = 0B, the BEMF1 = 0B
9.3.6
Effective MOSFET turn-on/-off delay
Table 37
Effective high-side MOSFET turn-on delay PWM1 (001 0011B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDONHS1
r
Field
Bits
Type
Description
(table continues...)
Datasheet
82
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 37
(continued) Effective high-side MOSFET turn-on delay PWM1 (001 0011B) Reset value: 0000
0000B
TDONHS1
[7:0]
r
Effective high-side MOSFET turn-on delay of PWM channel 1 1)
HBFREQ bit is 1: effective turn-on delay = 53.3 ∗ TDONHS1[7:0]D ns
HBFREQ bit is 0: effective turn-on delay = 26.7 ∗ TDONHS1[7:0]D ns
Default value: 0B
Table 38
Effective high-side MOSFET turn-off delay PWM1 (001 0100B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDOFFHS1
r
Field
Bits
Type
Description
TDOFFHS1
[7:0]
r
Effective high-side MOSFET turn-off delay of PWM channel 1 3)
HBFREQ bit is 1: effective turn-off delay = 53.3 ∗ TDOFFHS1[7:0]D ns
HBFREQ bit is 0: effective turn-off delay = 26.7 ∗ TDOFFHS1[7:0]D ns
Default value: 0B
Table 39
Effective low-side MOSFET turn-on delay PWM1 (001 0101B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDONLS1
r
Field
Bits
Type
Description
TDONLS1
[7:0]
r
Effective low-side MOSFET turn-on delay of PWM channel 1 2)
HBFREQ bit is 1: effective turn-on delay = 53.3 ∗ TDONLS1[7:0]D ns
HBFREQ bit is 0: effective turn-on delay = 26.7 ∗ TDONLS1[7:0]D ns
Default value: 0B
Table 40
Effective low-side MOSFET turn-off delay PWM1 (001 0110B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDOFFLS1
r
Field
Bits
Type
Description
TDOFFLS1
[7:0]
r
Effective low-side MOSFET turn-off delay of PWM channel 1 4)
HBFREQ bit is 1: effective turn-off delay = 53.3 ∗ TDOFFLS1[7:0]D ns
HBFREQ bit is 0: effective turn-off delay = 26.7 ∗ TDOFFLS1[7:0]D ns
Default value: 0B
Datasheet
83
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 41
Effective high-side MOSFET turn-on delay PWM2 (001 0111B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDONHS2
r
Field
Bits
Type
Description
TDONHS2
[7:0]
r
Effective high-side MOSFET turn-on delay of PWM channel 2 1)
HBFREQ bit is 1: effective turn-on delay = 53.3 ∗ TDONHS2[7:0]D ns
HBFREQ bit is 0: effective turn-on delay = 26.7 ∗ TDONHS2[7:0]D ns
Default value: 0B
Table 42
Effective high-side MOSFET turn-off delay PWM2 (001 1000B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDOFFHS2
r
Field
Bits
Type
Description
TDOFFHS2
[7:0]
r
Effective high-side MOSFET turn-off delay of PWM channel 2 3)
HBFREQ bit is 1: effective turn-off delay = 53.3 ∗ TDOFFHS2[7:0]D ns
HBFREQ bit is 0: effective turn-off delay = 26.7 ∗ TDOFFHS2[7:0]D ns
Default value: 0B
Table 43
Effective low-side MOSFET turn-on delay PWM2 (001 1001B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDONLS2
r
Field
Bits
Type
Description
TDONLS2
[7:0]
r
Effective low-side MOSFET turn-on delay of PWM channel 2 2)
HBFREQ bit is 1: effective turn-on delay = 53.3 ∗ TDONLS2[7:0]D ns
HBFREQ bit is 0: effective turn-on
delay = 53.3 ∗ 127 + 26.7 ∗ TDONLS2[7:0]D ns
Default value: 0B
Table 44
Effective low-side MOSFET turn-off delay PWM2 (001 1010B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDOFFLS2
r
(table continues...)
Datasheet
84
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 44
(continued) Effective low-side MOSFET turn-off delay PWM2 (001 1010B) Reset value: 0000
0000B
Field
Bits
Type
Description
TDOFFLS2
[7:0]
r
Effective low-side MOSFET turn-off delay of PWM channel 2 4)
HBFREQ bit is 1: effective turn-off delay = 53.3 ∗ TDOFFLS2[7:0]D ns
HBFREQ bit is 0: effective turn-off delay = 26.7 ∗ TDOFFLS2[7:0]D ns
Default value: 0B
Table 45
Effective high-side MOSFET turn-on delay PWM3 (001 1011B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDONHS3
r
Field
Bits
Type
Description
TDONHS3
[7:0]
r
Effective high-side MOSFET turn-on delay of PWM channel 3 1)
HBFREQ bit is 1: effective turn-on delay = 53.3 ∗ TDONHS3[7:0]D ns
HBFREQ bit is 0: effective turn-on delay = 26.7 ∗ TDONHS3[7:0]D ns
Default value: 0B
Table 46
Effective high-side MOSFET turn-off delay PWM3 (001 1100B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDOFFHS3
r
Field
Bits
Type
Description
TDOFFHS3
[7:0]
r
Effective high-side MOSFET turn-off delay of PWM channel 3 3)
HBFREQ bit is 1: effective turn-off delay = 53.3 ∗ TDOFFHS3[7:0]D ns
HBFREQ bit is 0: effective turn-off delay = 26.7 ∗ TDOFFHS3[7:0]D ns
Default value: 0B
Table 47
Effective low-side MOSFET turn-on delay PWM3 (001 1101B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDONLS3
r
Field
Bits
Type
Description
(table continues...)
Datasheet
85
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 47
(continued) Effective low-side MOSFET turn-on delay PWM3 (001 1101B) Reset value: 0000
0000B
TDONLS3
[7:0]
r
Effective low-side MOSFET turn-on delay of PWM channel 3 2)
HBFREQ bit is 1: effective turn-on delay = 53.3 ∗ TDONLS3[7:0]D ns
HBFREQ bit is 0: effective turn-on delay = 26.7 ∗ TDONLS3[7:0]D ns
Default value: 0B
Table 48
Effective low-side MOSFET turn-off delay PWM3 (001 1110B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TDOFFLS3
r
Field
Bits
Type
Description
TDOFFLS3
[7:0]
r
Effective low-side MOSFET turn-off delay of PWM channel 3 4)
HBFREQ bit is 1: effective turn-off delay = 53.3 ∗ TDOFFLS3[7:0]D ns
HBFREQ bit is 0: effective turn-off delay = 26.7 ∗ TDOFFLS3[7:0]D ns
Default value: 0B
1) Effective high-side turn-on delay is reported if VSHMx rises above VSHL in the duration of TBLANK.
If VSHMx > VSHL when the precharge starts, TDONHSx will be set to 0000 0000B.
If VSHMx < VSHL when TBLANK elapses, TDONHSx will be set to 1111 1111B.
2) Effective low-side turn-on delay is reported if VSHMx drops below VSHH in the duration of TBLANK.
If VSHMx < VSHH when the precharge starts, TDONLSx will be set to 0000 0000B.
If VSHMx > VSHH when TBLANK elapses, TDONLSx will be set to 1111 1111B.
3) Effective high-side turn-off delay is reported if VSHMx drops below VSHH in the duration of TCCP.
If VSHMx >VSHH when TCCP elapses, TDOFFHSx will be set to 1111 1111B.
If VSHMx < VSHH when the predischarge starts, TDOFFHSx will be set to 0000 0000B.
4) Effective low-side turn-off delay is reported if VSHMx rises above VSHL in the duration of TCCP.
If VSHMx < VSHL when TCCP elapses, TDOFFLSx will be set to 1111 1111B.
If VSHMx > VSHL when the predischarge starts, TDOFFLSx will be set to 0000 0000B.
9.3.7
Effective MOSFET rise/fall times
Table 49
Effective high-side MOSFET rise time of PWM1 (001 1111B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TRISEHS1
r
Field
Bits
Type
Description
(table continues...)
Datasheet
86
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 49
(continued) Effective high-side MOSFET rise time of PWM1 (001 1111B) Reset value: 0000
0000B
TRISEHS1
[7:0]
r
Effective high-side MOSFET rise time of PWM channel 1 1)
HBFREQ bit is 1: effective rise time = 53.3 ∗ TRISE_HS1[7:0]D ns
HBFREQ bit is 0: effective rise time = 26.7 ∗ TRISE_HS1[7:0]D ns
Default value: 0B
Table 50
Effective high-side MOSFET fall time of PWM1 (010 0000B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
0
0
TFALLHS1
r
Field
Bits
Type
Description
TFALLHS1
[7:0]
r
Effective high-side MOSFET fall time of PWM channel 1 3)
HBFREQ bit is 1: effective fall time = 53.3 ∗ TFALL_HS1[7:0]D ns
HBFREQ bit is 0: effective fall time = 26.7 ∗ TFALL_HS1[7:0]D ns
Default value: 0B
Table 51
Effective low-side MOSFET rise time of PWM1 (010 0001B) Reset value: 0000 0000B
7
6
5
4
3
2
1
TRISELS1
r
Field
Bits
Type
Description
TRISELS1
[7:0]
r
Effective low-side MOSFET rise time of PWM channel 1 2)
HBFREQ bit is 1: effective rise time = 53.3 ∗ TRISE_LS1[7:0]D ns
HBFREQ bit is 0: effective rise time = 26.7 ∗ TRISE_LS1[7:0]D ns
Default value: 0B
Table 52
Effective low-side MOSFET fall time of PWM1 (010 0010B) Reset value: 0000 0000B
7
6
5
4
3
2
1
TFALLLS1
r
Field
Bits
Type
Description
TFALLLS1
[7:0]
r
Effective low-side MOSFET fall time of PWM channel 1 4)
HBFREQ bit is 1: effective fall time = 53.3 ∗ TFALL_LS1[7:0]D ns
HBFREQ bit is 0: effective fall time = 26.7 ∗ TFALL_LS1[7:0]D ns
Default value: 0B
Datasheet
87
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 53
Effective high-side MOSFET rise time of PWM2 (010 0011B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
0
0
0
TRISEHS2
r
Field
Bits
Type
Description
TRISEHS2
[7:0]
r
Effective high-side MOSFET rise time of PWM channel 2 1)
HBFREQ bit is 1: effective rise time = 53.3 ∗ TRISE_HS2[7:0]D ns
HBFREQ bit is 0: effective rise time = 26.7 ∗ TRISE_HS2[7:0]D ns
Default value: 0B
Table 54
Effective high-side MOSFET fall time of PWM2 (010 0100B) Reset value: 0000 0000B
7
6
5
4
3
2
1
TFALLHS2
r
Field
Bits
Type
Description
TFALLHS2
[7:0]
r
Effective high-side MOSFET fall time of PWM channel 2 3)
HBFREQ bit is 1: effective fall time = 53.3 ∗ TFALL_HS2[7:0]D ns
HBFREQ bit is 0: effective fall time = 26.7 ∗ TFALL_HS2[7:0]D ns
Default value: 0B
Table 55
Effective low-side MOSFET rise time of PWM2 (010 0101B) Reset value: 0000 0000B
7
6
5
4
3
2
1
TRISELS2
r
Field
Bits
Type
Description
TRISELS2
[7:0]
r
Effective low-side MOSFET rise time of PWM channel 2 2)
HBFREQ bit is 1: effective rise time = 53.3 ∗ TRISE_LS2[7:0]D ns
HBFREQ bit is 0: effective rise time = 26.7 ∗ TRISE_LS2[7:0]D ns
Default value: 0B
Table 56
Effective low-side MOSFET fall time of PWM2 (010 0110B) Reset value: 0000 0000B
7
6
5
4
3
2
1
TFALLLS2
r
Field
Bits
Type
Description
(table continues...)
Datasheet
88
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 56
(continued) Effective low-side MOSFET fall time of PWM2 (010 0110B) Reset value: 0000
0000B
TFALLLS2
[7:0]
r
Effective low-side MOSFET fall time of PWM channel 2 4)
HBFREQ bit is 1: effective fall time = 53.3 ∗ TFALL_LS2[7:0]D ns
HBFREQ bit is 0: effective fall time = 26.7 ∗ TFALL_LS2[7:0]D ns
Default value: 0B
Table 57
Effective high-side MOSFET rise time of PWM3 (010 0111B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
0
0
TRISEHS3
r
Field
Bits
Type
Description
TRISEHS3
[7:0]
r
Effective high-side MOSFET rise time of PWM channel 3 1)
HBFREQ bit is 1: effective rise time = 53.3 ∗ TRISE_HS3[7:0]D ns
HBFREQ bit is 0: effective rise time = 26.7 ∗ TRISE_HS3[7:0]D ns
Default value: 0B
Table 58
Effective high-side MOSFET fall time of PWM3 (010 1000B) Reset value: 0000 0000B
7
6
5
4
3
2
1
TFALLHS3
r
Field
Bits
Type
Description
TFALLHS3
[7:0]
r
Effective high-side MOSFET fall time of PWM channel 3 3)
HBFREQ bit is 1: effective fall time = 53.3 ∗ TFALL_HS3[7:0]D ns
HBFREQ bit is 0: effective fall time = 26.7 ∗ TFALL_HS3[7:0]D ns
Default value: 0B
Table 59
Effective low-side MOSFET rise time of PWM3 (010 1001B) Reset value: 0000 0000B
7
6
5
4
3
2
1
TRISELS3
r
Field
Bits
Type
Description
TRISELS3
[7:0]
r
Effective low-side MOSFET rise time of PWM channel 3 2)
HBFREQ bit is 1: effective rise time = 53.3 ∗ TRISE_LS3[7:0]D ns
HBFREQ bit is 0: effective rise time = 26.7 ∗ TRISE_LS3[7:0]D ns
Default value: 0B
Datasheet
89
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
9 Register specification
Table 60
Effective low-side MOSFET fall time of PWM3 (010 1010B) Reset value: 0000 0000B
7
6
5
4
3
2
1
0
TFALLLS3
r
Field
Bits
Type
Description
TFALLLS3
[7:0]
r
Effective low-side MOSFET fall time of PWM channel 3 4)
HBFREQ bit is 1: effective fall time = 53.3 ∗ TFALL_LS3[7:0]D ns
HBFREQ bit is 0: effective fall time = 26.7 ∗ TFALL_LS3[7:0]D ns
Default value: 0B
1) Effective high-side rise time is reported if VSHMx rises above VSHH in the duration of TBLANK.
If VSHMx > VSHH when the precharge starts, TRISE_HSx will be set to 0000 0000B.
If VSHL < VSHMx < VSHH when TBLANK elapses, TRISE_HSx will be set to 1111 1111B.
2) Effective low-side rise time is reported if VSHMx drops blow VSHL in the duration of TBLANK.
If VSHMx < VSHL when the precharge starts, TRISE_LSx will be set to 0000 0000B.
If VSHL < VSHMx < VSHH when TBLANK elapses, TRISE_LSx will be set to 1111 1111B.
3) Effective high-side fall time is reported if VSHMx drops below VSHL in the duration of TCCP.
If VSHH > VSHMx > VSHL when TCCP elapses, TFALL_HSx will be set to 1111 1111B.
If VSHMx < VSHL when the predischarge starts, TFALL_HSx will be set to 0000 0000B.
4) Effective low-side fall time is reported if VSHMx rises above VSHH in the duration of TCCP.
If VSHH < VSHMx < VSHL when TCCP elapses, TFALL_LSx will be set to 1111 1111B.
If VSHMx > VSHH when the predischarge starts, TFALL_LSx will be set to 0000 0000B.
Datasheet
90
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
10 Application figure
10
Application figure
DISO
DISO
VS_12V
LPFILT1
CPFILT1
VBAT_48V
CPFILT2
TLE4267
(LDO)
CCP2
CVCP2
CP1P
CP1N
CP1
CCP1
VDD
EN
TLE9351SJ
(CAN transceiver)
Isolator
CVCP1
RVSM
DH
VSM
CVSM
RVDH
CVDH
RGATE
DH
RIN
CELKOx
GPIO
D6
D
S
G
GHM1
SHM1
SDI
SCLK
SDO
CSN
SDO
CH1
SCLK
CEMCP1
RGATE
SDI
D
G
GHM2
SHM2
CSN
CH2
CEMCP2
RGATE
S
IH1 TLE9140EQW
GPIO
GPIO
D
G
GHM3
IH2
IH3
CH3
SHM3
GLM1
MCU
U
D
CEMCP3
RGATE
S
GPIO
G
V
GPIO
GPIO
GPIO
IL1
IL2
IL3
Rpull
RGATE
S
D
G
GLM2
GLM3
W
D
Rpull
S
RGATE
G
Rpull
S
SLM
RShunt
PGND
OP2
OP1
CSA
CSA
GPIO
GND
PGND
Figure 23
TLE9140EQW is driven by the general microcontroller for 48 V applications supply concept:
isolated 12 V supply for the general MCU with diodes
Datasheet
91
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
10 Application figure
DISO
CVCP_E
DISO
CCP2_E
CCP1_E
VBAT_48V
LPFILT1
CPFILT2
VS_12V
Reverse polarity
CPFILT1
CCP2
CVCP2
CP1P
CP1N
CP1
CCP1
(12V Power supply)
VS
VDDP
VDDC
VDD
EN
CVS1
CVS2
CVDDP1
CVDDP2
CVCP1
RVSM
DH
VDH
VSD
VSM
RVSD
CVSD
CVDDC1
RIN
CVDDC2
CVSM
RVDH
DH
CELKOx
P1.2
CVDH
D6
D
RGATE
G
GHM1
SHM1
SDI
SCLK
SDO
CSN
P0.2
P0.3
CH1
CEMCP1
S
P0.4
P1.1
D
RGATE
G
GHM2
SHM2
CH2
LIN
CEMCP2
RGATE
S
IH1 TLE9140EQW
GH1
GH2
D
GND_LIN
G
GHM3
IH2
IH3
CH3
SHM3
GLM1
U
D
CEMCP3
RGATE
S
GH3
G
MOTIXTM MCU
(TLE987x)
V
GL1
GL2
GL3
IL1
IL2
IL3
Rpull
RGATE
VAREF
S
CVAREF
D
G
GLM2
GLM3
GND_REF
W
D
VDDEXT
CVDD_EXT1
Rpull
S
VDDEXT
P1.4
RGATE
CVDD_EXT2
G
SH1
SH2
RX
TX
RX
Rpull
S
LIN
(TLE8457)
Isolator
TX
SLM
P0.1
SH3
SL
RShunt
DH
GND_LIN
MON
RESET
P1.0
PGND
ROPAFILT
ROPAFILT
OP2
OP1
CSA
CSA
P1.3
P2.0
P2.2
TMS
P0.0
COPAFILT COP2
COP1
D1
D2
VDDEXT
T
Debug
Connector
SWD_EN
P0.2
P2.1
RTMS
GND
PGND
Figure 24
TLE9140EQW is driven by the MOTIX™ MCU (TLE987x) device supply concept: isolated 12 V
supply for the MOTIX™ MCU device with diodes
Datasheet
92
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
10 Application figure
LPFILT1
CPFILT1
VBAT_24V
CPFILT2
TLE4267
(LDO)
CCP2
CVCP2
CP1P
CP1N
CP1
CCP1
VDD
EN
TLE9351SJ
(CAN transceiver)
CVCP1
RVSM
DH
VSM
CVSM
RVDH
CVDH
RGATE
DH
RIN
CELKOx
GPIO
D6
D
S
G
GHM1
SHM1
SDI
SCLK
SDO
CSN
SDO
CH1
SCLK
CEMCP1
RGATE
SDI
D
G
GHM2
SHM2
CSN
CH2
CEMCP2
RGATE
S
IH1 TLE9140EQW
GPIO
GPIO
D
G
GHM3
IH2
IH3
CH3
SHM3
GLM1
MCU
U
D
CEMCP3
RGATE
S
GPIO
G
V
GPIO
GPIO
GPIO
IL1
IL2
IL3
Rpull
RGATE
S
D
G
GLM2
GLM3
W
D
Rpull
S
RGATE
G
Rpull
S
SLM
RShunt
PGND
OP2
OP1
CSA
CSA
GPIO
GND
PGND
Figure 25
TLE9140EQW is driven by the general MCU for 24 V applications
Datasheet
93
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
10 Application figure
LPFILT1
CPFILT2
VBAT_24V
CPFILT1
TLE4274
(LDO)
CVCP_E
CCP1_E
CCP2_E
CCP2
CVCP2
CP1P
CP1N
CP1
CCP1
(12V Power supply)
VS
VDDP
VDDC
VDD
EN
CVS1
CVS2
CVDDP1
CVDDP2
CVCP1
RVSM
DH
VDH
VSD
VSM
RVSD
CVSD
CVDDC1
RIN
CVDDC2
CVSM
RVDH
CVDH
RGATE
DH
CELKOx
P1.2
D6
D
S
G
GHM1
SHM1
SDI
SCLK
SDO
CSN
P0.2
P0.3
CH1
CEMCP1
RGATE
P0.4
P1.1
D
G
GHM2
SHM2
IH1TLE9140EQW
CH2
LIN
CEMCP2
RGATE
S
CLIN
GH1
GH2
D
GND_LIN
G
GHM3
IH2
IH3
CH3
SHM3
GLM1
U
D
CEMCP3
RGATE
S
GH3
G
TLE987x
(MOTIXTM MCU)
V
GL1
GL2
GL3
IL1
IL2
IL3
Rpull
VAREF
S
CVAREF
D
RGATE
G
GLM2
GLM3
GND_REF
VDDEXT
W
D
VDDEXT
CVDD_EXT1
Rpull
S
RGATE
CVDD_EXT2
G
SH1
SH2
Rpull
S
SLM
SH3
SL
RShunt
DH
MON
RESET
P1.0
PGND
ROPAFILT
ROPAFILT
OP2
OP1
CSA
CSA
P1.3
P2.0
P2.2
TMS
P0.0
COPAFILT
COP2
COP1
D1
D2
VDDEXT
T
Debug
Connector
SWD_EN
P0.2
P2.1
RTMS
GND
PGND
Figure 26
TLE9140EQW is driven by the MOTIX™ MCU (TLE987x) device for 24 V applications
Datasheet
94
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
11 Package outline
11
Package outline
Figure 27
TSDSO-32
To meet the world-wide customer requirements for environmental friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (this
means lead-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Datasheet
95
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
12 Revision history
12
Revision history
Revision number
Date of release
Description of changes
Rev. 0.05
2022-10-04
•
•
•
•
•
•
•
•
•
Update the logic supply currents IDD1 and IDD2
Update the SHMx high threshold voltage VSHMH
Update the SHMx low threshold voltage VSHML
Update the undervoltage threshold of CP2 VCP2UV
Update the BEMF hysteresis VBEMF_HYS
Update the BEMF accuracy VBEMF_ACC
Update the symbol of the on resistance of gate current source
Update the description in features and potential applications
Add application figure of TLE9140EQW controlled by general
microcontroller
•
•
•
Replace Embedded power with MOTIXTM MCU
Update the cover page of the datasheet
Split current accuracy for the normal and boosted current for high
current range.
Rev. 0.04
2022-04-20
•
•
•
•
•
•
•
•
•
•
Update the GHMx vs. SHMx voltage VGSHMx
Update the GLMx vs. SLMx voltage VGSLMx
Update the logic supply currents ISM_NOR1, ISM_NOR2 and ISM_NOR3
Add BEMF accuracy and BEMF hysteresis
Update the pull-up diagnosis current IPUDiag
Update the max. rating of VGHMx and VSHMx
Update the BEMF polarity in Global Status Register 4
Update Drain-source overvoltage threshold
Update the typ. values of all charge/discharge currents in registers
Update the on resistance of the gate current source RONGH
Datasheet
96
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
12 Revision history
Revision number
Date of release
2021-12-06
Description of changes
Rev. 0.03
•
•
•
•
•
•
•
Update the max. rating of the supply voltage VSM
Update the max. rating of charge pump pins
Update thermal resistance: RthJC and RthJA
Update quiescent current in chapter 4.4
Update the sleep mode delay tDSLEEP
Update the supply current ISM_NOR2
Update the hard overvoltage switch on/off
voltages: VSMOV_ON and VSMOV_OFF
•
•
•
•
•
•
•
•
Update the enable hysteresis VENHY
Update the values and conditions of charge pump outputs in Table 8
Update charge pump 1 undervoltage threshold VCP1UV
Update charge pump 2 undervoltage threshold VCP2UV
Update Drain-source overvoltage threshold
Update the pull-up diagnosis current IPUDiag
Update the pull-down diagnosis current IPDDiag
Update the values and conditions of the output voltage in chapter
6.2
•
•
•
•
•
•
•
•
•
•
•
Update the charge/discharge current accuracy
Update the Discharge_ST current accuracy
Update the SHMx high/low threshold
Add an on resistance of gate current source
Update the description of the BEMF feature in chapter 7
Update the typ. values of all charge/discharge currents in registers
Update the HS/LS delay on/off time
Update the gate driver current turn-on/turn-off rise time
Update the rise time of CP1
Update the rise time of CP2
Update the turn-on time of CP2
Datasheet
97
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
12 Revision history
Revision number
Date of release
2021-04-15
Description of changes
Rev. 0.02
•
Update the values and the conditions of off-state open load
diagnosis: IPUDiag, IPDDiag, IPDDiag/IPUDiag
•
•
•
•
Update the typ. and max. values of ISM_NOR1
Update the max. values of tVASDO and tENSDO
Update the min. value of VGSHM
Update the description and figures of "Resume normal
operation from VSM overvoltage event": "tGD_filt" is replaced with
"tBLK_VCPX and tGD_filt
"
•
•
Update the description of gate driver control in chapter 6.1
Add an additional description "low-side MOSFET latched on" in
chapter 5.8.2
•
•
•
•
•
•
•
•
•
•
•
Update the condition of VIL2_IN
Remove the conditions of RPD_SDI, RPD_SCLK, RPD_ILx and RPD_IHx
Change max. operation voltage to 72V
Correct a typo in table 43
.
Correct a typo in chapter 8.3
Add an additional description in chapter 6.1
Update the figures of gate driver control in chapter 6.1
Correct typos in chapter 6
Update the conditions of ISM_NOR1 and ISM_NOR2
Replace the PRQ numbers with P numbers
Remove the footnote "Not subject to production test, specified by
design."
•
•
•
•
Modify global status register 4
Add general control register 14 for BEMF processing
Update the BEMF description in chapter 7
Smaller capitalization and standardization updates through the
document
Rev. 0.01.3
2020-11-06
•
•
•
•
Update min. value of GHM, GLM and SHM
Update voltage range at CP1
Update ASIL level of EN Low filter time
Update high input voltage threshold, low input voltage threshold
and hysteresis of ILx and IHx
•
•
•
•
•
•
Update general control register 1, 4, 5, 6, 7, 8, 9, 10 and 11
Footnotes are updated
Add a simplified application figure for in product description folder
Add a title to the figure "In - frame response"
Add a marking for the package
Delete the redundant "Status" in "Configurable turn-on of the low-
side MOSFET"
Datasheet
98
Rev. 0.05
2022-10-04
TLE9140EQW
Preliminary datasheet
12 Revision history
Revision number
Date of release
Description of changes
Rev. 0.01.2
2020-05-18
•
•
Update application figures
Add additional description for LSAFW, delay time, rising/failing time,
exit stop mode, deglitch feature and cross current protection
•
•
Correct typos
Update following specs: FHTI, sleep mode delay, EN low filter time
and pull-up/down diagnosis current.
Rev. 0.01.1
2020-03-11
first release
Datasheet
99
Rev. 0.05
2022-10-04
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2022-10-04
Published by
Infineon Technologies AG
81726 Munich, Germany
Important notice
Warnings
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event be regarded as a guarantee of conditions or
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With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
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Document reference
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