TLE82094SACUMA1 [INFINEON]
Half Bridge Based Peripheral Driver,;
| 型号： | TLE82094SACUMA1 |
| 厂家： | 
Infineon |
| 描述： | Half Bridge Based Peripheral Driver, 驱动 接口集成电路 |
| 文件： | 总38页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.1, Oct. 2012
TLE8209-4SA
SPI Programmable H-Bridge
Automotive Power
TLE8209-4SA
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
4.2
4.3
5
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Basic Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VDD Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VDDIO - Digital Output Supply and Diagnostic Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics Power Supply and VDD-Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
5.2
5.3
5.4
6
Logic Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Parallel or SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
H-Bridge or Single Switch Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
7.2
7.3
8
Protection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Diagnosis in Status Flag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Temperature Dependent Current Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Short Circuit to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Short Circuit to Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Short Circuit across the Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Undervoltage Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Open Load Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
9
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
General SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Electrical Characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1
9.2
9.3
10
11
12
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Outlines TLE8209-4SA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Sheet
2
Rev. 1.1, 2012-10-15
SPI Programmable H-Bridge
TLE8209-4SA
1
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Programmable current limitation from 1.8 to 10.6 A typ.
Full path RDSon of 240 mΩ (typ. at Tj=25°C)
Operating battery supply voltage 4.5 V to 28 V
Operating logic supply voltage 4.4 to 5.25 V
Low standby current (8 µA typ.)
Logic inputs TTL/CMOS-compatible
All I/O pins overvoltage tolerant up to 18 V
Enable and disable input
Short circuit and overtemperature protection
VS undervoltage protection
PG-DSO-20-65
V
DD over and undervoltage protection
Open load detection in off condition
Temperature dependent current reduction
Extensive diagnosis capabilities via SPI interface
Status Flag for basic diagnosis without SPI
Configurable as H-bridge or two independent half bridges
Control of power stages by parallel inputs or via SPI
Output switching frequency up to 11 kHz
Slewrate programmable through SPI
Excellent EMC performance
AEC qualified
Green product (RoHS compliant)
Functional Description
The TLE8209-4SA is a SPI programmable H-bridge, designed for the control of DC motors in safety critical
automotive applications. It features four selectable current ranges, two selectable slew rate settings and extensive
diagnosis via SPI. The device monitors the digital supply voltage VDD and shuts down the output stages in case of
VDD over- or undervoltage, thus providing a safe switch off path in case of malfunction of the digital control circuitry.
In order to reduce power dissipation in extreme thermal conditions the current limitation threshold is reduced
linearly for junction temperatures over 165°C. A thermal warning bit is set in the SPI.
The two half bridges can also be used independently to drive two separate loads like solenoids or unidirectional
DC motors.
Type
Package
Body Width
Marking
TLE8209-4SA
PG-DSO-20-65
430 mil
TLE8209-4SA
Data Sheet
3
Rev. 1.1, 2012-10-15
TLE8209-4SA
Pin Configuration
2
Pin Configuration
2.1
Pin Assignment
GND
SO
1
20
19
18
17
16
15
14
13
12
11
GND
GNDABE
VDD
SCK
SI
2
VDDIO
SS/SF
CP
3
4
5
6
VS
VS
IN1
7
IN2
OUT1
DIS
8
OUT2
ABE
GND
21
GND
9
GND
10
Figure 1
Pinout TLE8209-4SA
2.2
Pin Definitions and Functions
Pin
1
Symbol
Function in SPI Mode
Ground
Function in Status Flag Mode
Ground
GND
SO
2
SPI Serial Data Out
no function - connect to GND
Switches to SF-mode if connected to GND
Status Flag (low active)
3
Supply Voltage for Logic Output Buffer
Slave Select (low active)
VDDIO
SS/SF
CP
4
5
Pin for external Charge Pump Capacitor
Pin for external Charge Pump Capacitor
6
Battery Supply Voltage, has to be connected to Battery Supply Voltage, has to be
VS
pin 15
connected to pin 15
7
IN1
Input 1
Input 1
8
OUT1
DIS
Output 1
Disable
Output 1
9
Disable
10
11
12
13
14
15
GND
GND
ABE
OUT2
IN2
Ground
Ground
Ground
Ground
Bidirectional Enable Pin
Output 2
Input 2
Bidirectional Enable Pin
Output 2
Input 2
Input battery supply voltage, has to be
connected to pin 6
Input battery supply voltage, has to be
connected to pin 6
VS
16
SI
SPI Serial Data Input
no function - connect to GND
Data Sheet
4
Rev. 1.1, 2012-10-15
TLE8209-4SA
Pin Configuration
Pin
17
18
19
20
21
Symbol
SCK
Function in SPI Mode
Function in Status Flag Mode
no function - connect to GND
VDD supply
SPI Clock
V
DD supply
VDD
GNDABE
GND
Sense ground for VDD monitoring
Ground
Sense ground for VDD monitoring
Ground
GND
Heatslug - connect to GND
Heatslug - connect to GND
2.3
Terms
ICP
IS
VCP
IDD
CP
VS
VDD
VS
IGNDABE
VGNDABE
VDD
GNDABE
I
IN 1
IN1
IN2
DIS
I
IN 2
VIN1
IDIS
IOUT1
OUT1
OUT2
VIN2
IABE
VABE
VDIS
ABE
VOUT1
IOUT2
VOUT2
ISO
ISI
SO
SI
SCK
SS/SF
VDDIO
ISCK
ISS / SF
IDDIO
VSO
VSI
VSCK
VSS /SF VDDIO
GND
Figure 2
Terms TLE8209-4SA
Data Sheet
5
Rev. 1.1, 2012-10-15
TLE8209-4SA
Block Diagram
3
Block Diagram
VS
CP
VDD
VDD-
Monitoring
internal
Supply
GNDABE
VS
IN1
Undervoltage
Logic
IN2
DIS
Gate Control
Diagnostics
ABE
OUT1
OUT2
SO
SI
SCK
SPI/Flag
SS/SF
VDDIO
GND
Figure 3
Block Diagram TLE8209-4SA
Data Sheet
6
Rev. 1.1, 2012-10-15
TLE8209-4SA
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 ⋅C to 150 ⋅C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions / Comment
Min.
Max.
4.1.1
Junction temperature
Tj
-40
150
150
175
°C
–
100h cumulative
4.1.2
4.1.3
4.1.4
Storage temperature
Ambient temperature
Battery supply voltage
Ts
Ta
VS
-55
-40
-0.5
-2
150
125
40
°C
°C
V
–
–
Static destruction proof
40
V
Dynamic destruction proof
t < 0.5 s (single pulse,
T
–
–
–
jstart < 85 °C)
4.1.5
4.1.6
4.1.7
Logic supply voltage
Supply for logic out
VDD
VDDIO
VIN
-0.5
-0.5
-0.5
18
18
18
V
V
V
Voltage at logic pins
ABE, IN1, IN2, DIS, SCK,
SS/SF, SI
4.1.8
4.1.9
Voltage at SO
VSO
-0.5
VDDIO
+0.3
V
V
–
Voltage at CP
VCP
VS-0.3
VS+5.0
0V < VS < 40V
4.1.10 Voltage at GNDABE
VGNDABE VGND-0.3 VGND+0.3 V
ESD Susceptibility
4.1.11 ESD Resistivity to GND
VESD
-2
2
kV
kV
V
HBM2)
4.1.12
4.1.13
4.1.14
-8
8
HBM2), Pins OUT1 and OUT2
CDM3)
CDM3), Pins 1, 10, 11, 20
-500
-750
500
750
V
1) Not subject to production test, specified by design.
2) ESD susceptibility HBM according to EIA/JESD22-A114-B (1.5kΩ, 100pF)
3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101
Note:Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note:Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
7
Rev. 1.1, 2012-10-15
TLE8209-4SA
General Product Characteristics
4.2
Operating Range
Pos.
Parameter
Symbol
Limit Values
Unit Remark
Min.
Max.
28
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
VS supply voltage range
VS
4.5
4.4
0
V
–
–
–
–
–
V
V
DD supply voltage
DDIO supply voltage
VDD
VDDIO
f
5.25
5.5
V
V
PWM frequency
–
11
kHz
°C
Junction temperature
TJ
-40
150
Note:Within the operating range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Pos.
Parameter
Symbol
Limit Values
Min. Typ. Max.
1.6
Unit Remark
4.3.6
4.3.7
Junction to Case1)
Junction to Ambient1)
RthJC
RthJA
–
–
–
K/W
K/W
–
2)
17
–
1) Not subject to production test, specified by design.
2) Simulation according to Jedec JESD51-2,-5,-7; natural convection; FR4 2s2p board 76.2 x 114.3 x 1.5 mm (2 x 70µm Cu,
2 x 35µm Cu)
Data Sheet
8
Rev. 1.1, 2012-10-15
TLE8209-4SA
Power Supply
5
Power Supply
5.1
Basic Supply Characteristics
The TLE8209-4SA has three different supply pins: VDD, VS and VDDIO. VDD is used to supply the internal logic
circuitry. VS connects to battery voltage and supplies the output stages. The voltage at pin VDDIO defines the high
level output voltage at the pin SO of the SPI interface. VDDIO is also used as a mode select pin. If VDDIO is
connected to ground, the device is set to status flag mode (SPI inactive).
On power up the device will enter a functional state when VDD rises above the functional reset threshold VDD_RES
In this state all output stages are inactive and internal registers are cleared. When VDD rises further above the
power on reset threshold VDD_POR the device starts operation with a delay time of tPOR
.
.
5.2
VDD Monitoring
The logic supply voltage level at the pin VDD is monitored. If the voltage at pin VDD is out of the permissible range
of VDD_L … VDD_H the power stages of TLE8209-4SA are switched off and pin ABE is pulled to ground. To suppress
glitches in the VDD monitoring, a glitch filter is implemented.VDD is measured with reference to pin GNDABE. The
state of VDD monitoring is stored in STATCON_REG and can be read out via SPI.
The output stages can also be turned off by pulling the ABE pin to ground externally.
In case of VDD failure, the output stages are switched off, even if the pin ABE should be connected to a high level
signal because of external short circuit to VDD or battery voltage (up to 18V). OUT1 and OUT2 cannot be switched
on in over- or undervoltage condition, switching off is always possible. A power on reset (VDD < VDD_POR) switches
off all stages without delay.
Control of VDD-monitoring is possible in SPI mode only. Detailed information (differentiation of over and under-
voltage detection) is only possible by SPI interface.
Behavior of VDD monitoring in SF mode:
- monitoring is present with the specified values for over- and undervoltage
- any test of over- and undervoltage threshold is not possible
- the latch for overvoltage is disabled
VDD Undervoltage
If the VDD voltage is lower than the supply voltage supervisory lower threshold (VDD_THL), output stages are shut
off after a filtering time (tFIL_OFF) and the bi-directional pin ABE is pulled low. At the transition from undervoltage to
normal voltage the signal at pin ABE goes high and the output stages will return to normal operation after a filtering
time (tFIL_ON) has expired. For output control via SPI the bits MUX and SINx in the config register have to be re-
programmed. New failures are not stored to diagnostic registers during undervoltage, register content remains
valid, writing new information to configuration registers is possible as far as they are not reset by ABE. If VDD falls
below the power-on-reset supply voltage (VDD_POR) all stages are shut off and ABE is switched active low. When
VDD is rising above the power-on-reset supply voltage threshold (VDD_POR) a power-on-reset is generated (tPOR),
setting all registers to its default state.
VDD Overvoltage
If the VDD voltage is higher than the supply voltage supervisory upper threshold (VDD_THH), all output stages are
shut off after a filtering time (tFIL_OFF) and the bi-directional pin ABE is pulled low. The behavior of the ABE level
and output stages on the return of VDD from overvoltage to the correct range is configured in STATCON_REG,
bit CONFIG0)
CONFIG0=’1’: ABE is latched and outputs remain off after overvoltage. Return to normal operation is only possible
with power-on reset or by changing this bit via SPI.
Data Sheet
9
Rev. 1.1, 2012-10-15
TLE8209-4SA
Power Supply
CONFIG0=’0’: ABE is inactive after VDD returned to normal operating voltage and filtering time has expired.
At the transition from overvoltage to normal condition, the output stages will return to normal operation. For output
control via SPI the bits MUX and SINx in the config register have to be re-programmed. New failures are not stored
to diagnostic registers during overvoltage, register content remains valid, writing new information to configure
registers is possible as far as they are not reset by ABE.
VDD Monitoring Test Mode
Testing of VDD monitoring is possible in SPI mode only. The latch function for over voltage at VDD has to be
switched of (CONFIG0=0 in STATCON_REG)
Testing upper threshold:
By writing 00xxxxxxb into STATCON_REG, the overvoltage threshold is reduced to VDD_TEST_H.
STATCON_REG bit 2 and 0 have to be LOW then. After writing 1xxxxxxxb to STATCON_REG, bit 2 and 0 in
STATCON_REG must be HIGH again
Testing lower threshold:
By writing 01xxxxxxb into STATCON_REG, the undervoltage threshold is increased to VDD_TEST_L.
STATCON_REG bit 2 and 1 have to be LOW then. After writing 1xxxxxxxb to STATCON_REG, bit 2 and 1 in
STATCON_REG must be HIGH again.
5.3
VDDIO - Digital Output Supply and Diagnostic Mode Selection
The voltage at VDDIO is used to supply the output buffer at the SO pin (serial output of SPI-interface). The VDDIO
pin is also used to select SPI- or in status flag (SF) diagnostic mode. As soon as VDDIO is lower than VDDIO_L, the
device is put into status flag mode.
.
VDDIO
to internal logic
+
(SF-mode / SPI -mode)
-
SF/SPI - mode
threshold VDDIO_L
SO
from internal logic
Figure 4
VDDIO and SO-Pin
Data Sheet
10
Rev. 1.1, 2012-10-15
TLE8209-4SA
Power Supply
5.4
Electrical Characteristics Power Supply and VDD-Monitoring
Electrical Characteristics: Power Supply and VDD-Monitoring
VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
Typ.
Max.
Supply
5.4.1
Supply Current
IVS
–
–
8
20
4
µA
IOUT = 0 A, VDD = 0V,
VS < 18 V, Tj < 125°C
2.1
mA
bridge disabled,
I
OUT = 0 A,
5 V < VS < 18 V
–
–
–
2.5
4
5
mA
mA
mA
f = 2 kHz, IOUT = 0 A,
5 V < VS < 18 V
9
f = 10 kHz, IOUT = 0 A,
5 V < VS < 18 V
4.8
13
f = 10 kHz, IOUT = 0 A,
5 V < VS < 28 V
5.4.2
5.4.3
5.4.4
Functional Reset Threshold VDD_RES
Power On Reset Threshold VDD_POR
–
1.4
2.5
4.0
0.5
V
–
–
3.5
–
3.75
0.22
V
Power On Reset Delay
Time
tPOR
ms
VDD = on --> output
stage active, no load
5.4.5
5.4.6
VDD Input current
IDD
–
–
7
9
mA
µA
4.5V < VDD < 5.5V
VDDIO Input current
IDDIO
30
100
SPI-mode
no load at SO
no SPI communication
5.4.7
5.4.8
5.4.9
SF-mode Threshold
SPI-mode Threshold
VDDIO_L
VDDIO_H
–
–
1.0
–
V
V
V
–
–
–
2.0
0.2
–
Mode selection hysteresis VDDIO_HYS
0.5
1.0
VDD-Monitoring
5.4.10
5.4.11
5.4.12
Overvoltage threshold
VDD_THH
5.25
4.2
5.4
4.3
4.3
5.5
4.4
4.4
V
V
V
Voltage referred to
GNDABE
Undervoltage threshold
VDD_THL
Test mode reduced
VDD_TEST_H
4.2
Overvoltage threshold
5.4.13
5.4.14
5.4.15
Test mode increased
Undervoltage threshold
VDD_TEST_L
tFIL
5.25
60
–
5.4
100
–
5.5
135
0.5
V
Filter time for glitch
suppression
μs
–
–
Maximum Slew Rate on
VDD1)
VDD_slew
V/µs
1) Not subject to production test; specified by design
Data Sheet
11
Rev. 1.1, 2012-10-15
TLE8209-4SA
Logic Inputs and Outputs
6
Logic Inputs and Outputs
The threshold specifications for the logic inputs are compatible to both 5 and 3.3 V standard CMOS micro-
controller ports. All inputs (except ABE) feature internal pull-up current sources. The logic output SO is supplied
by VDDIO. VDDIO can be supplied with either 5 or 3.3 V, so the output thresholds of SO can be configured to the
required I/O voltage.
Electrical Characteristics: Control Inputs
VS = 5 V to 28 V; VDD = 5.0 V; Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Test Conditions
Min.
Typ.
Max.
IN1, IN2
6.0.1
Low level
High level
Hysteresis
VINx_L
-0.3
2.0
0.2
-30
0
–
1.0
V
–
6.0.2
VINx_H
–
VDD+0.3
1.0
V
–
6.0.3
VINx_HYS
–
V
–
6.0.4
Input Current (Pull Up) IINx
-20
2
-10
µA
µA
0 V < VINx < 2.1 V
6.0.5
5
V
INx > 3.0 V
2)
6.0.6
DIS
Input Capacity1)
CINx
–
–
20
pF
6.0.7
6.0.8
6.0.9
6.0.10
6.0.11
Low level
High level
Hysteresis
VDIS_L
VDIS_H
-0.3
2.0
–
1.0
V
–
–
–
–
VDD+0.3
1.0
V
VDIS_HYS 0.2
–
V
Input Current (Pull Up) IDIS
-200
0
-125
2
-50
µA
µA
0 V < VDIS< 2.1 V
5
V
DIS > 3.0 V
2)
6.0.12
6.0.13
ABE
Input Capacity1)
Minimum Pulse Width1) tDIS
CDIS
–
–
20
pF
µs
0.4
0.8
1.5
–
6.0.14
Output low-level voltage VABE_OUTL
–
–
–
–
1.2
1.0
V
V
VDD_THH < VDD < 18 V
ABE < 5 mA
2.5 V < VDD < VDD_THL
ABE < 1 mA
I
6.0.15
I
6.0.16
6.0.17
6.0.18
6.0.19
6.0.20
6.0.21
SI
Input threshold high
Input threshold low
Hysteresis
VABE_INH 0.7*VDD
VABE_INL
VABE_INHY 0.2
–
–
V
–
–
–
0.3*VDD
1.0
V
–
–
V
–
Minimum pulse width1) tABE
0.4
20
0
0.8
40
–
1.5
µs
μA
μA
–
ABE Input current (Pull -IABE_L
Down)
120
60
1.5 V < VABE < 18 V
0 V < VABE < 1.5 V
6.0.22
6.0.23
6.0.24
6.0.25
6.0.26
Low level
High level
Hysteresis
VSI_L
-0.3
2.0
0.2
-30
–
1.0
V
–
–
–
VSI_H
–
VDD+0.3
1.0
V
VSI_HYS
–
V
Input Current (Pull Up) ISI
Input Capacity1)
CSI
-20
-10
µA
pF
0 V < VSI < 2.1 V
2)
14
Data Sheet
12
Rev. 1.1, 2012-10-15
TLE8209-4SA
Logic Inputs and Outputs
Electrical Characteristics: Control Inputs (cont’d)
VS = 5 V to 28 V; VDD = 5.0 V; Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Test Conditions
Min.
Typ.
Max.
SCK
6.0.27
6.0.28
6.0.29
6.0.30
6.0.31
SS/SF
6.0.32
6.0.33
6.0.34
6.0.35
6.0.36
6.0.37
6.0.38
6.0.39
6.0.40
SO
Low level
High level
Hysteresis
VSCK_L
VSCK_H
-0.3
2.0
–
1.0
V
–
–
–
–
VDD+0.3
1.0
V
VSCK_HYS 0.2
–
V
Input Current (Pull Up) ISCK
Input Capacity1)
-30
–
-20
–
-10
µA
pF
0 V < VSCK < 2.1 V
2)
CSCK
14
Low level
High level
Hysteresis
VSS_L
VSS_H
VSS_HYS
ISS
-0.3
2.0
0.2
-30
-30
0
–
1.0
V
–
–
VDD+0.3
V
–
–
1.0
-10
5
V
–
Input Current in SPI
mode (Pull Up)
-20
–
µA
µA
µA
µA
µA
pF
0 V < VSS < 2.1 V
2.1 V < VSS < 3.0 V
2
5
V
V
SS > 3.0 V
Input Current in SF
mode (Open Drain)
ISF
0
2
5
SF = 5.0 V, SF inactive
SF = 1.0 V, SF active
300
–
–
–
V
2)
Input Capacity1)
CSS
–
15
6.0.41
6.0.42
Low level
High level
VSO_L
VSO_H
0.0
–
0.4
V
V
I
I
SO = 2 mA
SO = -2 mA
V
DDIO-0.75 –
VDDIO
2.9 V < VDDIO < 5.5 V
In tristate2)
6.0.43
6.0.44
Output capacitance1)
Leakage current
CSO
ISO
–
–
–
19
2
pF
-2
μA
In tristate
0 < VSO < VDDIO
1) Not subject to production test; specified by design
2) Vbias = 2 V; Vtest = 20 mVpp; f = 1 MHz
Data Sheet
13
Rev. 1.1, 2012-10-15
TLE8209-4SA
Power Stages
7
Power Stages
The TLE8209-4SA contains four n-channel power-DMOS transistors that can be used in an H-bridge or in dual
half bridge configuration.
Integrated circuits protect the outputs against overcurrent and over-temperature, in case of short-circuit to ground,
to the supply voltage or across the load. Positive and negative voltage spikes, which occur when switching
inductive loads, are limited by integrated freewheeling diodes (body diodes of power-DMOS).
7.1
Parallel or SPI Control
By default the setting of the power switches is controlled by the Inputs IN1, IN2 (parallel control). The outputs
OUT1 and OUT2 are set to High (high-side switch ON, low-side switch OFF) or Low (high-side switch OFF, low-
side switch ON) by the parallel inputs IN1 and IN2, respectively. In SPI mode there is also the option to control the
outputs via the SPI bits SIN1 and SIN2 of the SPI configuration register. To switch to SPI control the bit MUX has
to be set to ’0’.
In addition, the outputs can be disabled (set to tristate, high- and low-side switch OFF) by the disable input DIS
and the bidirectional reset pin ABE. Disabling sets the device to parallel control
Table 1 shows the different options for the output control.
7.2
H-Bridge or Single Switch Usage
The IC can be set to H-bridge mode or single-switch mode by SPI. This setting changes the behavior of the device
in the following features:
•
•
•
current limiting
overcurrent shut-down
open load diagnosis
Table 1
Pos.
Functional Truth Table
DIS
ABE
IN1
IN2
SPI
SPI
SPI
OUT1 OUT2
MUX
SIN1
SIN2
Forward, parallel ctrl.
Reverse, parallel ctrl.
L
L
H
H
H
H
H
H
H
H
X
L
H
L
L
1
1
1
1
0
0
0
0
X
X
X
X
X
X
1
X
X
X
X
0
H
L
L
H
L
H
L
Free-wheeling low, parallel ctrl. L
Free-wheeling high, parallel ctrl. L
L
L
H
X
X
X
X
X
X
H
X
X
X
X
X
X
H
H
L
H
L
Forward, SPI ctrl.
L
L
L
L
H
X
Reverse, SPI ctrl.
0
1
H
L
Free-wheeling low, SPI ctrl.
Free-wheeling high, SPI ctrl.
Disabled by DIS
0
0
L
1
1
H
Z
Z
H
Z
Z
X
X
X
X
Disabled by ABE
Table 2
OUT States
OUT
H
High-Side DMOS
Low-Side DMOS
ON
OFF
ON
L
OFF
OFF
Z
OFF
Data Sheet
14
Rev. 1.1, 2012-10-15
TLE8209-4SA
Power Stages
7.3
Electrical Characteristics Power Stages
Electrical Characteristics: Power Stage
VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
Typ.
Max.
Power Outputs OUT1, OUT2
7.3.1
7.3.2
ROUT1L
ROUT2L
–
125
215
115
200
–
–
mΩ
mΩ
I
I
I
I
OUTx = 3 A; Tj = 25°C
OUTx = 3 A; Tj = 150°C
OUTx = 3 A; Tj = 25°C
OUTx = 3 A; Tj = 150°C
Switch on resistance low
side
–
250
–
Switch on resistance high ROUT1H
–
side
ROUT2H
–
240
200
7.3.3
7.3.4
7.3.5
Leakage current
IOUT1(off)
IOUT2(off)
-200
μA
V
Output stage switched off
VS = 13 V
Free-wheel diode forward UD
–
–
0.9
–
1.1
ID = 3 A
voltage
Free-wheel diode reverse
recovery time1)
100
ns
–
trr
Output Switching Times - Fast Slew Rate
7.3.6
7.3.7
7.3.8
7.3.9
Rise time HS
Fall time HS
Rise time LS
Fall time LS
tr (HS)
tf (HS)
tr (LS)
tf (LS)
3.5
3.5
3.5
3.5
6.0
6.0
6.0
6.0
10
μs
μs
SPI bit SL=’0’
VS = 8..18 V; IOUT = 3 A
10
8.5
8.5
Output Switching Times - Slow Slew Rate
7.3.10
7.3.11
7.3.12
7.3.13
Rise time HS
Fall time HS
Rise time LS
Fall time LS
tr (HS)
tf (HS)
tr (LS)
tf (LS)
15
15
18
18
30
30
30
30
48
48
48
48
SPI bit SL=’1’
VS = 8..18 V; IOUT = 3 A
Output Delay - Parallel Control, Fast Slew Rate
7.3.14
7.3.15
Output on-delay
Output off-delay
tdon
tdoff
–
–
–
–
12
7
μs
μs
VS = 8..18 V; IOUT = 3 A
VS = 8..18 V; IOUT = 3 A
VS = 8..18 V; IOUT = 3 A
VS = 8..18 V; IOUT = 3 A
Output Delay - SPI Control, Fast Slew Rate
7.3.16
7.3.17
Output on-delay
Output off-delay
tdon
tdoff
–
–
–
–
13
12
μs
μs
μs
Output Delay - Parallel Control, Slow Slew Rate
7.3.18
7.3.19
Output on-delay
Output off-delay
tdon
tdoff
–
–
–
–
41
25
Output Delay - SPI Control, Slow Slew Rate
7.3.20
7.3.21
Output on-delay
Output off-delay
tdon
tdoff
–
–
–
–
42
26
Data Sheet
15
Rev. 1.1, 2012-10-15
TLE8209-4SA
Power Stages
Electrical Characteristics: Power Stage
VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
Typ.
Max.
Enable and Disable Delay Times
7.3.22
7.3.23
7.3.24
7.3.25
7.3.26
Disable delay time, fast
slew rate
tddis
tddis
tdel
–
–
–
–
–
8
20
75
20
75
0.4
μs
VS = 8..18 V; IOUT = 3 A
Disable delay time, slow
slew rate
38
8
Enable delay time, fast
slew rate
Enable delay time, slow
slew rate
tdel
38
0.1
Power on delay time
tdel
ms
VS = on --> output stage
active, no load
1) Not subject to production test - specified by design
tRISE
tFALL
90%
90%
OUTx
10%
10%
Figure 5
Output Switching Time
V
5
INx
30%
30%
0
90%
OUTx
10%
tdon
tdoff
Figure 6
Output Delay Time – Low-Side FETs
Data Sheet
16
Rev. 1.1, 2012-10-15
TLE8209-4SA
Power Stages
V
5
ABE
50%
50%
0
t
3A
90%
IOUT
10%
0
t
tddis
tden
Figure 7
ABE pin - Enable and Disable Delay Time
V
5
DIS
30%
30%
0
t
3A
90%
IOUT
10%
0
t
tddis
tden
Figure 8
DIS pin - Enable and Disable Delay Time
Data Sheet
17
Rev. 1.1, 2012-10-15
TLE8209-4SA
Protection and Monitoring
8
Protection and Monitoring
Both output stages of the TLE8209-4SA are equipped with fault diagnostic functions:
•
•
•
•
•
•
Short to battery voltage (SCB). Can be detected when low side-switches are turned on
Short to ground (SCG). Can be detected when high side-switches are turned on
Open load (OL). Can be detected in inactive mode
Over-temperature (OT). Can be detected in active and inactive mode
VDD over- and under voltage (Chapter 5.2)
Battery under voltage detection. Can be detected in active and inactive mode
Individual detection for each output in single switch operation mode (SCB, SCG, OL) is possible. The
corresponding diagnostics bits for each failure will be set in the SPI according to Table 8 “Failure Encoding” on
Page 29.
8.1
Diagnosis in Status Flag Mode
Instead of using the SPI interface for control and diagnosis of the TLE8209-4SA, the device can also be set into
status flag mode by connecting pin VDDIO to GND as described in Chapter 5.3.
In status flag mode the pin SF will be pulled low in the following cases:
•
•
•
•
•
undervoltage at VS
bridge disabled by ABE or DIS
bridge disabled by VDD monitoring
bridge disabled by short circuit detection
overtemperature shut down
SF will not be pulled low if VDD is below the power on reset threshold (VDD_POR).
8.2
Current Limitation
To limit the output current at low power loss, a chopper current limitation is integrated. Current measurement for
current limitation is done in the high side path. This requires high side freewheeling in case of active current
limitation.
ttrans
tb
IL
HS1
LS1
HS2
LS2
Ihys
time
Figure 9
Chopper Current Limitation
Figure 9 shows the behavior of the current limitation for over current detection in HS1. It applies accordingly also
for HS2:
When the current in high-side switch of OUT1 (HS1) exceeds the limit IL longer than the blanking time tb, OUT2 is
switched to high (e.g. LS2->OFF, HS2->ON), independent of the input signal at IN2. This leads to a slow-decay
current decrease in the load and in HS1. As soon as the current falls below IL-Ihys, OUT2 is switched back to normal
Data Sheet
18
Rev. 1.1, 2012-10-15
TLE8209-4SA
Protection and Monitoring
operation, i.e. the outputs follow the inputs according to the truth table. The current limit IL can be programmed to
four different values by setting the SPI bits CL1 and CL2 in the SPI configuration register. To avoid high chopper
frequencies the time between two transients ttrans is limited.
Current limitation is available in H-bridge operation mode, not in single switch operation mode. This means, that
the current limit, current limit hysteresis and blanking time has no effect in single switch operation mode.
8.3
Temperature Dependent Current Reduction
For TILR < Tj < TSD the current limit decreases from IL as set by the SPI to IL_TSD = 2.5 A typ. as shown in
Figure 10.
A
IL
range of over-
temperature shut-down
tolerance of temperature
dependent current
reduction
IL_TSD
(typ. 2.5A)
TILR
TSD
Tj
[°C]
(typ. 165°C) (min. 175°C)
Figure 10 Temperature Dependent Current Reduction
8.4
Short Circuit to Ground
short circuit detected
output off
current limitation active
IOUK
current tracking
IL
Ihys
tb
t<tb
tDF_H
tDF_OFF
IOUT
time
Short
IN1
OUT1
IN2
tristate
tristate
OUT2
Figure 11 Short to Ground Detection
Data Sheet
19
Rev. 1.1, 2012-10-15
TLE8209-4SA
Protection and Monitoring
The short circuit to ground detection is activated when the current through one of the high side switches rises over
the threshold IOUK and remains higher than IOUK for at least the filter time tDF_H within the blanking time tb.
The output stage in which the short circuit was detected will be switched off within tDF_OFF
.
In H-bridge mode also the other output will be switched off after a short delay of tDF_del
In single switch mode only the affected output will be switched off.
.
8.5
Short Circuit to Battery
A short circuit to battery is detected in the same way as a short circuit to ground, only in the low side switch instead
of the high side switch.
8.6
Short Circuit across the Load
Short circuit over load is indicated by two failures - short circuit to ground on one output and short circuit to battery
on the other output. Both failure bits will be set in the SPI diagnostics register. Both output stages will be turned off.
8.7
Overtemperature
In case of high DC-currents, insufficient cooling or high ambient temperature, the chip temperature may rise above
the thermal shut-down temperature TSD (see Figure 10). In that case, all output transistors are turned off.
8.8
Undervoltage Shut-Down
If the supply voltage at the VS pins falls below the undervoltage detection threshold VUV_OFF, the outputs switches
are turned off. As soon as VS rises above VUV_ON again, the device is returning to normal operation.
8.9
Open Load Diagnosis
Open load diagnosis is only possible if outputs are switched off by DIS or ABE. The diagnostic current sources are
deactivated in status flag mode. Diagnostic current sources are disconnected if outputs are active. That means
that the diagnostic current sources are also disconnected if the outputs are deactivated due to short circuit. The
open load detection in H-bridge mode is different from the open load detection in single switch mode.
Open Load Detection in H-Bridge mode
VDD
OUT1
OUT2
OUT2_L
Vref_L
OUT1_L
+
-
Vref_L
+
-
Figure 12 Open Load Detection in H-Bridge Mode
Data Sheet
20
Rev. 1.1, 2012-10-15
TLE8209-4SA
Protection and Monitoring
Table 3
Open Load Detection in H-Bridge Mode
VOUT1 OUT1_L VOUT2 OUT2_L Diagnostic
Comment
< Vref_L
< Vref_L
> Vref_L
> Vref_L
H
H
L
< Vref_L
> Vref_L
< Vref_L
> Vref_L
H
L
Load o.k.
Load o.k.
Open Load
Load o.k.
pull down current is stronger
transient area
H
L
L
transient area
Open Load Detection in Single Switch Mode
VDD
Vref_M
VDD
Vref_H
OUTx
Vref_M
OUTx_H
OUTx_L
+
-
Vref_H
Vref_L
-
+
Vref_L
+
-
Figure 13 Open Load Detection in Single Switch Mode
Table 4
Open Load Detection in Single Switch Mode
VOUTx (OFF State)
OUTx_H
OUTx_L
Diagnostic
o.k.
Comment
V
V
V
OUTx < Vref_L
L
L
H
H
L
L
Load to ground
Output open
Load to VS
ref_L <VOUTx < Vref_H
OUTx > Vref_H
Open Load
o.k.
Data Sheet
21
Rev. 1.1, 2012-10-15
TLE8209-4SA
Protection and Monitoring
8.10
Electrical Characteristics
Electrical Characteristics: Protection and Monitoring
VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Test Conditions
Min.
Typ.
Max.
Chopper Current Limitation
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
Current Limit
|IL1|
|IL2|
|IL3|
|IL4|
Ihys
1.0
3.3
6.0
9.0
0.0
1.8
4.8
7.8
10.6
0.3
2.7
5.7
9.2
12.3
0.4
A
-40 °C < Tj < TILR
Dependent on SPI
setting; Default = IL3
Current Limit Hysteresis
Blanking time
A
-40 °C < Tj < TILR
8.10.6
8.10.7
tb
8
11
–
15
μs
μs
–
–
Time between transients
ttrans
90
130
Temperature Dependent Current Limitation1)
8.10.8
8.10.9
Current Limit at TSD
IL_TSD
1.4
2.5
3.6
–
A
–
–
Start of current limit
reduction
TILR
150
165
°C
8.10.10 Thermal shut-down
TSD
175
20
–
–
°C
°C
–
–
8.10.11 Range of temperature
dependent current
reduction
T
SD - TILR
25
30
Short Circuit Detection to GND
8.10.12 Short circuit detection
current (HS)
8.10.13
|IOUKH1
|IOUKH2
|IOUKH3
|IOUKH4
|
|
|
|
2.5
6.3
9.0
11.7
14.2
4.4
4.2
3.9
3.7
7.5
A
A
-40 °C < Tj < TILR
Dependent on SPI-
setting for |IL|; Default =
IOUKH3
5.5
8.5
10.5
11.0
13.5
17.4
5.5
8.10.14
8.10.15
8.10.16 Current tracking
8.10.17
|IOUKH1| - |IL1| 1.5
|IOUKH2| - |IL2| 2.0
|IOUKH3| - |IL3| 2.0
|IOUKH4| - |IL4| 1.5
5.5
8.10.18
5.0
8.10.19
5.0
Short Circuit Detection to VS
8.10.20 Short circuit detection
current (LS)
8.10.21
|IOUKL1
|IOUKL2
|IOUKL3
|IOUKL4
|
|
|
|
2.5
4.6
8.1
10.0
14
6.5
A
A
-40 °C < Tj < TILR
Dependent on SPI-
setting for |IL|; Default =
IOUKL3
5.0
7.5
10.5
10.0
11.5
17.4
5.0
8.10.22
8.10.23
8.10.24 Current tracking
8.10.25
|IOUKL1| - |IL1| 1.0
|IOUKL2| - |IL2| 1.0
|IOUKL3| - |IL3| 0.5
|IOUKL4| - |IL4| 0.3
2.8
3.3
2.2
3.4
5.5
8.10.26
5.5
8.10.27
7.0
Data Sheet
22
Rev. 1.1, 2012-10-15
TLE8209-4SA
Protection and Monitoring
Electrical Characteristics: Protection and Monitoring
VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Test Conditions
Min.
Typ.
Max.
Short Circuit Detection Timing
8.10.28 Delay time for fault
detection
t
DF_H, tDF_L
1
–
5
2
5
µs
µs
µs
–
–
–
8.10.29 Time from detected fault to tDF_OFF
–
4
high impedance of output1)
tDF_del
8.10.30 Delay time between
switching off of the output
stages in short circuit
17
40
Open Load
8.10.31 Open Load Diagnostic
Filter Time1)
tOL_DIAG
60
–
135
µs
V
–
–
8.10.32 Low Diagnosis Threshold Vref_L
0.4 *
0.4 *
0.4 * VDD
VDD
-
VDD
+ 0.2
0.2
8.10.33 High Diagnosis Threshold Vref_H
0.8 *
0.8 *
VDD
0.8 * VDD
+ 0.2
V
V
–
VDD
-
0.2
8.10.34 Diagnosis Bias Voltage
Vref_M
0.6 *
0.6 *
0.6 * VDD
–
VDD
-
VDD
+ 0.2
0.2
8.10.35 Positive Diagnostic Current IDIA_P
(pull down current source)
300
270
-350
-350
2
620
610
-240
-210
2.9
980
980
-100
-80
4
µA
µA
µA
µA
–
VOUTx = 14 V
8.10.36
V
OUTx = Vref_H
8.10.37 Negative Diagnostic
Current
IDIA_N
VOUTx = 0 V
8.10.38
V
OUTx = Vref_L
8.10.39 Ratio of current sources
(Pos/Neg)
RatioI_DIA
–
Undervoltage
8.10.40 Undervoltage at VS
VUV OFF
VUV ON
VUV HY
3.1
3.3
100
–
3.7
3.9
200
–
4.4
4.6
400
1.5
V
V
Switch off threshold
Switch on threshold
mV Hysteresis
µs
8.10.41 VS Undervoltage Detection tUV
Filter Time1)
1) Not subject to production test; specified by design.
Data Sheet
23
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
9
SPI Interface
The serial SPI interface establishes a communication link between TLE8209-4SA and the systems
microcontroller. The TLE8209-4SA always operates in slave mode whereas the controller provides the master
function. The maximum baud rate is 2 MBaud.
By applying an active slave select signal at SS the TLE8209-4SA is selected by the SPI-master. SI is the data
input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI-clock is provided by the
master. In case of inactive slave select signal (High) the data output SO goes into tristate.
The first two bits of an instruction may be used to establish an extended device-addressing. This gives the
opportunity to operate up to 4 Slave-devices sharing one common SS signal from the Master-Unit (see Figure 16).
SS
SPI-Control:
SCK
-> state machine
-> clock counter
-> instruction recognition
SI
shift-register
8
SO
8
DIA_REG
Diagnostics
Reset
DIS
OR
ABE
Figure 14 SPI Block Diagram
9.1
General SPI Characteristics
1. During active reset conditions the SPI is driven into its default state. The output SO is set to high impedance
(tristate). When reset becomes inactive, the state machine enters into a wait state for the next instruction.
2. If the slave select signal at SS is inactive (high), the state machine is forced to wait for the following instruction.
3. During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used to
latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing of the
data according to the instruction (i.e. modification of internal registers) will be triggered by the rising edge of
the SS signal.
4. In order to establish the option of extended addressing the upper two bits of the instruction byte (i.e. the first
two SI bits of a frame) are reserved to send a chip address. To avoid a bus conflict the output SO will remain
tristate during the addressing phase of a frame (i.e. until the address bits are recognized as a valid chip
Data Sheet
24
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
address). If the chip address does not match, the according frame will be ignored and SO remains tristate for
the complete frame.
5. Verification byte: Simultaneously to the receipt of an SPI instruction the TLE8209-4SA transmits a verification
byte via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains
an initial bit pattern and a flag indicating an invalid instruction of the previous access.
6. On a read access the data bits at the SPI input SI are rejected. During a valid write access the SPI will transmit
the data byte "00hex" at the output SO after having sent the verification byte.
7. An instruction is invalid if one of the following conditions is fulfilled:
- an unused instruction code is detected (see tables with SPI instructions).
- the previous transmission is not completed in terms of internal data processing.
- the number of SPI clock pulses (falling edge) counted during active SS differs from exactly 16 clock pulses.
If an unused instruction code occurres, the data byte “FFhex” (no error) will be transmitted after having sent the
verification byte. This transmission takes place within the same SPI-frame that contained the unused
instruction byte.
If an invalid instruction is detected, bit TRANS_F in the following verification byte (next SPI-transmission) is set
to HIGH. The TRANS_F bit must not be cleared before it has been sent to the microcontroller.
9.2
SPI Communication
The 16 input bits consist of the SPI instruction byte and an input data byte. The 16 output bits consist of the
verification byte and the output data byte (see also Figure 15). The definition of these bytes is given in the
subsequent sections. The access mode of the registers is described in the column “Type” (r = read, w = write).
SS
7
6
5
4
3
2
1
SCK
SI
7
6
5
4
3
2
1
0
0
SPI Instruction
Verification byte
input data-byte
output data-byte
MSB
MSB
LSB
SO
LSB MSB
LSB
Figure 15 SPI Communication
9.2.1
Instruction Byte
The upper 2 bit of the instruction byte contain the chip address. The chip address of the TLE8209-4SA is ’00’.
During read access, the output data according to the register requested in the instruction byte are applied to SO
within the same SPI frame. That means, the output data corresponding to an instruction byte sent during one SPI
frame are transmitted to SO during the same SPI-frame
Data Sheet
25
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
Table 5
SPI Instruction Format
7
6
5
4
3
2
1
0
CPAD1
CPAD0
INSTR5
INSTR4
INSTR3
INSTR2
INSTR1
INSTR0
Field
Bits
Type
Description
CPAD1:0
INSTR5:0
7:6
5:0
w
w
Chip Address (00B)
SPI Instruction (encoding)
SO remains tristated
after SS active
Address sent by
master is "00B"
Correct addres is recognized,
data transmitted to SO
SS
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
5
4
4
3
2
2
1
1
0
7
7
6
6
5
5
4
3
3
2
2
1
0
0
SO
Z
3
0
4
1
Correct addres is not recognized, SO
remains tristated and SI data are ignored
SO remains tristated
after SS active
Address sent by master
is different from "00 B"
SS
SCK
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
5
4
3
1
0
6
5
3
2
1
0
SI
6
2
7
4
SO
Z
Figure 16 Bus Arbitration by Chip Address
Data Sheet
26
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
Table 6
SPI Instruction Set
SPI Instruction Byte Description
Command
RD_ID
0000 0000
0000 0011
0000 1001
0011 0000
0011 1100
0010 1000
0001 1000
00xx xxxx
xxxx xxxx
Read identifier
RD_REV
Read version
RD_DIA
Read diagnostics register
Read power stage configuration
Read VDD monitoring status
Write power stage configuration
Write VDD monitoring status
RD_CONFIG
RD_STATCON
WR_CONFIG
WR_STATCON
all other instructions
all other chip addr.
Unused - TRANS_F is set to high, ff_hex is sent as data bit.
Invalid address - SO remains tristate during entire SPI-frame.
9.2.2
Verification Byte
Table 7
Verification Byte Format
7
6
5
4
3
2
1
0
VER6
VER5
VER4
VER3
VER2
VER1
VER0
TRANS_F
Field
Bits
Type
Description
VER6
VER5
VER4
VER3
VER2
VER1
VER0
TRANS_F
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
Fixed to tristate (Z)
Fixed to tristate (Z)
Fixed to high (1)
Fixed to low (0)
Fixed to high (1)
Fixed to low (0)
Fixed to high (1)
Transfer failure:
1B
0B
Error detected during previous transfer
Previous transfer was recognized as valid
9.2.3
Device Identifier and Revision
The IC’s identifier (device ID) and revision number are used for production test purposes and features plug & play
functionality depending on the systems software release. The two numbers are read-only accessible via the SPI-
instructions RD_ID and RD_REV as described in Section 9.2.1. The device ID is defined to allow identification of
different IC-types by software and is fixed for the TLE8209-4SA.
The revision number may be utilized to distinguish different states of hardware and is updated with each redesign
of the TLE8209-4SA. It is divided into an upper 4 bit field reserved to define revisions (SWR) corresponding to
specific software releases and a lower 4 bit field utilized to identify the actual mask set revision (MSR).
Both (SWR and MSR) will start with 0000B and are increased by 1 every time an according modification of the
hardware is introduced.
Data Sheet
27
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
ID_REG
Device Identifier
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Field
Bits
7:0
Type
Description
Device-ID
ID7:0
r
TLE8209-4SA: DE hex
REV_REG
Device Revision
7
6
5
4
3
2
1
0
SWR3
SWR2
SWR1
SWR0
MSR3
MSR2
MSR1
MSR0
Field
Bits
Type
Description
SWR3:0
MSR3:0
7:4
3:0
r
r
Revision corresponding to software release
Revision corresponding to mask set
9.2.4
Diagnostics Register
DIA_REG
Diagnostics Register
Reset Value: x111 1111B
7
6
5
4
3
2
1
0
ABE/DIS
OT
CurrRed
CurrLim
DIA21
DIA20
DIA11
DIA10
Field
Bits
7
Type
Description
ABE/DIS
OT
r
r
r
r
r
r
r
r
Is set to “0” in case of ABE = L or DIS = H
Is set to “0” in case of over temperature
6
CurrRed
CurrLim
DIA21
DIA20
DIA11
DIA10
5
Is set to “0” in case of temperature dependent current limitation
Is set to “0” in case of current limitation
Diagnosis-Bit2 of OUT2
4
3
2
Diagnosis-Bit1 of OUT2
1
Diagnosis-Bit2 of OUT1
0
Diagnosis-Bit1 of OUT1
Data Sheet
28
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
Table 8
Failure Encoding
ABE/DIS DIA21 DIA20 DIA11 DIA10 Description
Comment
X
1
1
1
1
1
1
1
1
X
0
0
0
1
X
X
X
0
1
1
0
1
0
1
1
1
1
X
X
X
1
0
1
1
0
0
1
1
1
1
0
1
1
X
X
X
1
0
0
0
X
0
1
1
0
1
X
X
X
0
1
0
0
0
X
no failure
short circuit to battery at OUT1 (SCB1)
short circuit to ground at OUT1 (SCG1)
no error detected at OUT1
latched
latched
short circuit to battery at OUT2 (SCB2)
short circuit to ground at OUT2 (SCG2)
no error detected at OUT2
latched
latched
short circuit accross load (HS1+LS2 active)
short circuit accross load (HS2+LS1 active)
Undervoltage at pin VS
latched
latched
not latched
latched
latched
latched
open load (H-Bridge)
open load at OUT1 (single switch operation)
open load at OUT2 (single switch operation)
Note:
The bit ABE/DIS shows directly the status of inputs ABE and DIS. It is set to ‘0’ if the power stages are disabled
by ABE or DIS.
The bits OT, CurrRed and CurrLim are latched. They will be reset with each read access. If the failure condition is
still present the according bits are set again.
Undervoltage at VS is reported and the outputs are switched off as long as the undervoltage condition is present.
The previous setting of the DIAx bits is masked but not reset. Once the supply voltage is back in the operating
range the diagnostic bits DIAxx will return to their setting before VS undervoltage. The outputs will return to normal
operation.
Detection of short circuit will switch of the output stages. In single half bridge operation only the affected output is
switched off. In H-Bridge mode both outputs are shut down. The outputs remain off until the failure condition is
removed and the diagnosis register is reset.
A short across the load may also be reported as SCG at one output and SCB at the other.
The diagnostic information DIAxx in the SPI interface is reset in the following cases:
•
•
•
•
Read out of DIA_REG: only bit 4, 5 and 6 will be reset
Enabling or disabling of the bridge via ABE or DIS
Undervoltage at VDD
Reset command via SPI
Data Sheet
29
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
9.2.5
Configuration Register
CONFIG_REG
Configuration Register
Reset Value: 1111 1010B
7
6
5
4
3
2
1
0
MODE
MUX
SIN1
SIN2
CL1
CL2
RESET
SL
Field
Bits
Type
Description
MODE
7
wr
’1’: H-bridge mode
’0’: single output stages (for current levels 1 to 3 only)
MUX
6
wr
’1’: control by parallel inputs IN1 and IN2
’0’: control by SPI bits SIN1 and SIN2
SIN1
SIN2
CL1
5
4
3
2
1
0
wr
wr
wr
wr
wr
wr
control of OUT1 if MUX=’0’
control of OUT2 if MUX=’0’
current limitation level (see table below)
current limitation level (see table below)
’0’: reset of digital logic
CL2
RESET
SL
slew rate setting
’1’: slow
’0’: fast
Table 9
CL1
Current Limitation Levels
CL2
0
Current Level
Typical Current
0
0
1
1
1
2
1.5A
4.0A
6.6A
8.6A
1
0
3 (default)
1
4
9.2.6
STATCON Register
STATCON_REG
STATCON Register
Reset Value: 1101 1xxxB
7
6
5
4
3
2
1
0
CONFIG2
CONFIG1
CONFIG0
DIACLR2
DIACLR1
STATUS2
STATUS1
STATUS0
Field
Bits
Type
wr
Description
CONFIG2
7
VDD threshold test mode
’1’: VDD monitoring in normal operation
’0’: VDD thresholds are changed according to CONFIG1
Data Sheet
30
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
Field
Bits
Type
Description
CONFIG1
6
wr
changes thresholds in VDD threshold test mode (CONFIG2=’0’)
’1’: increase lower threshold of VDD monitoring to test switch off path
’0’: decrease upper threshold of VDD monitoring to test switch off path
CONFIG0
5
wr
latch function for overvoltage at VDD
’1’: overvoltage at VDD latched
’0’: overvoltage at VDD not latched
DIACLR2
DIACLR1
4
3
wr
wr
’0’: clears diagnosis of OUT2
always returns ’1’ at read access
’0’: clears diagnosis of OUT1
always returns ’1’ at read access
STATUS2
STATUS1
2
1
r
r
returns level at ABE
’0’: under voltage at VDD
’1’: VDD voltage above lower limit
STATUS0
0
r
0’: over voltage at VDD
’1’: VDD voltage below upper limit
Data Sheet
31
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
9.2.7
Contents of the SPI registers after a reset condition
Note:The registers for device identifier and revision (ID_REG and REV_REG) are not affected by reset.
DIA_REG
7
6
OT
1
5
4
3
2
1
0
ABEDIS
CurrRed
CurLim
DIA21
DIA20
DIA11
DIA10
POR
x
x
x
x
x
x
1
1
1
1
x
x
1
1
1
1
x
x
1
1
1
x
x
1
1
1
1
x
x
1
1
1
1
x
1
x
1
1
1
x
1
x
SPIR
1
ABEDISR
RDR
1
1
DIACLR1
DIACLR2
x
x
CONFIG_REG
7
6
5
4
3
CL1
1
2
CL2
0
1
0
SL
0
MODE
MUX
SIN1
SIN2
RESET
POR
1
1
x
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SPIR
1
0
0
DISR
x
x
x
SFMODE
1
0
0
STATCON_REG
7
6
5
4
3
2
1
0
CONFIG2 CONFIG1 CONFIG0 DIACLR2 DIACLR1 STATUS2 STATUS1 STATUS0
POR
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
x
x
x
x
x
x
x
x
x
SPIR
SFMODE
POR: Reset due to VDD power up
SPIR: Reset via SPI by writing 0 into the RESET of CONFIG_REG
ABEDISR: Reset due to enabling or disabling the power stages via DIS or ABE (edge triggered)
DISR: Reset due to a disabled power stage by DIS or ABE (level triggered)
RDR: Reset due to a read access to DIA_REG
DIACLR1: Reset via SPI by writing 0 into the DIACLR1 of STATCON_REG
DIACLR2: Reset via SPI by writing 0 into the DIACLR2 of STATCON_REG
SFMODE: Reset by setting the TLE8209-4SA into the Status Flag Mode (VDDIO = 0V)
x: No change
Note:If a reset condition is not listed for a particular register it has no effect on the contents of this register.
Data Sheet
32
Rev. 1.1, 2012-10-15
TLE8209-4SA
SPI Interface
9.3
Electrical Characteristics SPI
Electrical Characteristics: SPI Interface
VS = 5 V to 28 V; VDD = 5.0 V; VDDIO = 2.9 V to 5.5 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground,
positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min. Typ. Max.
SPI-Timing (see Figure 17)1)
9.3.1
9.3.2
9.3.3
9.3.4
Cycle-time (1)
tcyc
tlead
tlag
tv
490
50
–
–
–
–
–
–
ns
ns
ns
ns
referred to master
referred to master
referred to master
Enable Lead Time (2)
Enable Lag Time (3)
150
Data Valid (4)
–
–
–
–
150
230
CL = 200 pF
CL = 350 pF
referred to TLE8209-4
H->L: VSCK=2V -> VSO=0.2 VDDIO
L->H: VSCK=2V -> VSO=0.8 VDDIO
if VDDIO < 4.5V:
L->H: VSCK=2V -> VSO=0.7 VDDIO
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10
9.3.11
Data Setup Time (5)
Data Hold Time (6)
Disable Time (7)
tsu
th
40
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
μs
referred to master
referred to master
referred to TLE8209-4
referred to master
referred to master
referred to master
referred to master
40
–
tdis
tdt
–
100
–
Transfer Delay (8)
Disable Lead Time (9)
Disable Lag Time (10)
Access time (11)
250
250
250
8.35
tdld
tdlg
tacc
–
–
–
1) All timing parameters specified by design - not subject to production test
11
SS
8
3
9
2
1
10
SCK
SO
SI
7
4
tristate
Bit (n-4)…1
Bit (n-4)…1
Bit 0; LSB
Bit (n-3)
6
5
MSB IN
Bit (n-2)
Bit (n-3)
LSB IN
n=16
Figure 17 SPI Timing
Data Sheet
33
Rev. 1.1, 2012-10-15
TLE8209-4SA
Application Information
10
Application Information
Note:The following simplified application examples are given as a hint for the implementation of the device only
and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the
device. The function of the described circuits must be verified in the real application
10 nF
Vbat
Vs<
40V
100nF
100 uF
CP
VS
TLE8209-4SA
5V ECU supply
VDD
8.2k
Enable
input(s)
ABE
OUT1
OUT2
open -drain
output (s)
IN1
IN2
DIS
M
µC
SO
SI
<33 nF
<33 nF
SCK
SS/SF
3.3 or 5V port supply
VDDIO
GNDABE
GND
VDD voltage
regulator GND pin
Figure 18 Application Example H-Bridge with SPI-Interface
Data Sheet
34
Rev. 1.1, 2012-10-15
TLE8209-4SA
Application Information
10 nF
CP
Vbat
Vs<
40V
100 nF
100 uF
VS
TLE8209-4SA
5V ECU supply
VDD
3.3 or 5V port supply
8.2k
47k
Enable
input (s)
ABE
OUT1
OUT2
open -drain
output (s)
SS/SF
M
uC
IN1
IN2
DIS
<33 nF
<33 nF
SO
SI
SCK
VDDIO
GNDABE
GND
VDD voltage
regulator GND pin
Figure 19 Application Example with Status Flag
Reverse polarity protection via main relay
VS
main
relay
100µF
100 nF
ignition
switch
battery
Figure 20 Application Examples for Overvoltage and Reverse-Voltage Protection
Data Sheet 35
Rev. 1.1, 2012-10-15
TLE8209-4SA
Package Outlines TLE8209-4SA
11
Package Outlines TLE8209-4SA
1)
±0.15
11
B
2.8
±0.1
1.1
±0.1
15.74
6.3
(Heatslug)
Heatslug
1.27
0.1
(Mold)
±0.15
0.95
0.4 +0.13
M
0.25 A 20x
±0.3
14.2
0.25 B
Bottom View
11
11
20
20
Index Marking
1 x 45˚
Heatslug
1
1
10
10
13.7 -0.2
1)
(Metal)
±0.15
15.9
A
(Mold)
1) Does not include plastic or metal protrusion of 0.15 max. per side
GPS05791
Footprint:
0.68
1.27
9 x 1.27 = 11.43
hlg09550
Figure 21 PG-DSO-20-65 (
)
Plastic Dual Small Outline Package
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
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Dimensions in mm
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Data Sheet 36
Rev. 1.1, 2012-10-15
TLE8209-4SA
Revision History
12
Revision History
Revision
0.1
Date
Comments / Changes
2010-08-05
2012-09-13
Target Data Sheet based on TLE8209-2SA Data Sheet Rev. 1.0
1.0
Data Sheet
Current Limitation and Short Circuit Limits revised
1.1
2012-10-15
Parameter 8.10.1: Max. changed to 2.7A
Parameter 8.10.12: Max. changed to 7.5A
Data Sheet
37
Rev. 1.1, 2012-10-15
Edition 2012-10-15
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
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