TLD5542-1QV [INFINEON]
;型号: | TLD5542-1QV |
厂家: | Infineon |
描述: | |
文件: | 总81页 (文件大小:2708K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Infineon® LITIX™ Power Flex
Package
Marking
PG-VQFN-48
TLD55421QV
PG-TQFP-48
TLD55421QU
TLD5542-1QU
Sales Name TLD5542-1QV
1
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single inductor high power Buck-Boost controller
Wide LED forward voltage range (2 V up to 55 V)
Wide VIN range (IC 4.5 V to 40 V, power 4.5 V to 55 V)
Switching frequency range from 200 kHz to 700 kHz
SPI for diagnostics and control
Maximum efficiency in every condition (up to 96%)
Constant current (LED) and constant voltage regulation
Drives multiple loads with a single IC thanks to the Fast Output Discharge operation
Limp Home function (fail safe mode)
EMC optimized device: features an Auto Spread Spectrum
LED and input current sense with dedicated monitor outputs
Advanced protection features for device and load
Enhanced dimming features: Analog and PWM dimming
LED current accuracy +/- 3%
Available in a small thermally enhanced PG-VQFN-48 or PG-TQFP-48 package
Automotive AEC Qualified
VIN
CIN2
CIN1
CIVCC
IVCC_ext
VIN
IIN2
IVCC
VFB_VIN
D2
D1
IIN1
COUT2
COUT3
VDD
BST1
BST2
RFB
COUT1
CBST1 CBST2
VDD
M1
M2
M4
HSGD1
SWN1
EN/INUVLO
LOUT
I/O
I/O
CCOMP
M3
LSGD1
SWCS
RCOMP
CSOFT_START
COMP
VDD
SOFT_START
Micro
controller
RFREQ
FREQ
PWMI
High
Power
LED Load
SGND
PGND1
PGND2
LSGD2
SWN2
HSGD2
VFB
I/O
I/O
EOMFS
LEDCUR
VDD
VDD
RSPI1
CSN
SI
SO
FBH
RSPI2
RSPI3
SPI
FBL
RSPI4
SCLK
GND
IOUTMON
VSS AGND
FILT
CFILT2
CFILT1
Figure 1
Application Drawing - TLD5542-1 as current regulator
Datasheet
www.infineon.com
1
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Overview
Description
The TLD5542-1 is a synchronous MOSFET H-Bridge DC/DC controller with built in protection features and SPI
interface. This concept is beneficial for driving high power LEDs with maximum system efficiency and
minimum number of external components. The TLD5542-1 offers both analog and digital (PWM) dimming.The
switching frequency is adjustable in the range of 200 kHz to 700 kHz. It can be synchronized to an external
clock source. A built in programable Spread Spectrum switching frequency modulation and the forced
continuous current regulation mode improve the overall EMC behavior. Furthermore the current mode
regulation scheme provides a stable regulation loop maintained by small external compensation
components. The adjustable soft start feature limits the current peak as well as voltage overshoot at start-up.
The TLD5542-1 is suitable for use in the harsh automotive environment.
Table 1
Product Summary
Power Stage input voltage range
Device Input supply voltage range
VPOW
4.5 V … 55 V
4.5 V … 40 V
VVIN
Maximum output voltage (depending by the
application conditions)
VOUT(max)
55 V as LED Driver Boost Mode
50 V as LED Driver Buck Mode
50 V as Voltage regulator
Switching Frequency range
fSW
200 kHz... 700 kHz
Typical NMOS driver on-state resistance at
RDS(ON_PU)
2.3 Ω
Tj = 25°C (Gate Pull Up)
Typical NMOS driver on-state resistance at
Tj = 25°C (Gate Pull Down)
RDS(ON_PD)
fSCLK(MAX)
1.2 Ω
SPI clock frequency
5 MHz
Protective Functions
•
•
•
•
•
Over load protection of external MOSFETs
Shorted load, output overvoltage protection
Input undervoltage protection
Thermal shutdown of device with autorestart behavior
Electrostatic discharge protection (ESD)
Diagnostic Functions
•
•
•
Latched diagnostic information via SPI
Device Overtemperature shutdown and Temperature Prewarning
Smart monitoring and advanced functions provide ILED and IIN information
Limp Home Function
Limp Home activation via LHI pin
•
Applications
•
•
•
Especially designed for driving multiple high power LED functions (I.E. Low Beam, High Beam, DRL)
Automotive Exterior Lighting: full LED headlamp assemblies
General purpose DC/DC voltage regulator
Datasheet
2
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Block Diagram
2
Block Diagram
IVCC
Internal Supply
Power
On Reset
LDO
VIN
IVCC_EXT
GATE
DRIVER
SYNC
FREQ
Oscillator
BST1
Auto-Spread
Spectrum
Generator
HSGD1
SWN1
BUCK
LOGIC
Slope Comp.
IVCC_EXT
VIN
EN/INUVLO
Voltage
Protection
+ Enable
Thermal Protection
+ Prewarning
LSGD1
PGND1
PWM
Generator
Diagnosis Overvoltage +
Short to GND
IVCC_EXT
Soft Start
SOFT_START
Limp Home Mode
Digital Dimming
LSGD2
PGND2
LHI
PWMI
BOOST
LOGIC
Analog Dimming Pin
SET
SWN2
HSGD2
BST2
Fast Output
Discharge
Operation
Mode
Output
current
accuracy
calibration
EOMFS
FILT
SWCS
Switch Current
Error Amplifier
VDD
SGND
VFB
8 Bit DAC
Analog
Dimming
CSN
SCLK
SI
SPI
SO
FBH
FBL
Input
Current
Monitor
LED
Current
Monitor
Feedback Error Amplifier
+ Short to GND
Input/diagnosis
register
IIN1 IIN2
VSS
AGND
COMP
DIM_HALF
VFB_VIN
Figure 2
Block Diagram - TLD5542-1
Datasheet
3
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
LHI
SOFT_START
IINMON
AGND
EN/INUVLO
IIN1
37
38
39
40
41
42
43
44
45
46
47
48
24 PWMI
23 FILT
22 SET
21 VFB_VIN
20 VFB
19 COMP
18 SGND
17 SWCS
16 IOUTMON
15 n.c.
EP
IIN2
VIN
n.c.
IVCC
IVCC_EXT
n.c.
14 FBL
13 FBH
Figure 3
Pin Configuration - TLD5542-1
Datasheet
4
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Pin Configuration
3.2
Pin Definitions and Functions
Table 2
Pin
Pin Definitions and Functions
1)
Symbol
I/O
Function
Power Supply
1, 12,
15, 45,
48
n.c.
-
Not connected, tie to AGND on the Layout;
44
31
47
VIN
-
-
I
Power Supply Voltage;
Supply for internal biasing.
VDD
Digital GPIO Supply Voltage;
Connect to reverse voltage protected 5 V or 3.3 V supply.
IVCC_EXT
PD External LDO input;
Input to alternatively supply internal Gate Drivers via an external LDO.
Connect to IVCC pin to use internal LDO to supply gate drivers. Must not
be left open.
5, 8
26
40
-
PGND1, 2
VSS
-
-
-
-
Power Ground;
Ground for power potential. Connect externally close to the chip.
Digital GPIO Ground;
Ground for GPIO pins.
AGND
EP
Analog Ground;
Ground Reference
Exposed Pad;
Connect to external heatspreading Cu area (e.g. inner GND layer of
multilayer PCB with thermal vias).
Gate Driver Stages
2
HSGD1
O
O
Highside Gate Driver Output 1;
Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT
superimposed on the switch node voltage SWN1. Connect to gate of
external switching MOSFET.
11
HSGD2
Highside Gate Driver Output 2;
Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT
superimposed on the switch node voltage SWN2. Connect to gate of
external switching MOSFET.
6
7
LSGD1
LSGD2
O
O
Lowside Gate Driver Output 1;
Drives the lowside n-channel MOSFET between GND and VIVCC_EXT
Connect to gate of external switching MOSFET.
.
.
Lowside Gate Driver Output 2;
Drives the lowside n-channel MOSFET between GND and VIVCC_EXT
Connect to gate of external switching MOSFET.
4
9
SWN1
SWN2
IO
IO
Switch Node 1;
SWN1 pin swings from a diode voltage drop below ground up to VIN.
Switch Node 2;
SWN2 pin swings from ground up to a diode voltage drop above VOUT
.
Datasheet
5
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Pin Configuration
Table 2
Pin
Pin Definitions and Functions
1)
Symbol
IVCC
I/O
Function
46
O
Internal LDO output;
Used for internal biasing and gate driver supply. Bypass with external
capacitor close to the pin. Pin must not be left open.
Inputs and Outputs
37
23
25
41
LHI
I
-
-
I
PD Limp Home Input Pin;
Used to enter in Limp Home state during Fail Safe condition.
FILT
MFS Filter;
Connect with a 220pF capacitor to GND to filter MFS reference Voltage.
TEST2
EN/INUVLO
Test Pin;
Used for Infineon end of line test, connect to GND in application.
PD Enable/Input Under Voltage Lock Out;
Used to put the device in a low current consumption mode, with
additional capability to fix an undervoltage threshold via external
components. Pin must not be left open.
35
34
FREQ
SYNC
I
I
Frequency Select Input;
Connect external resistor to GND to set frequency.
PD Synchronization Input;
Apply external clock signal for synchronization.
24
13
PWMI
FBH
I
I
PD Control Input; Digital input 5 V or 3.3 V.
Output current Feedback Positive;
Non inverting Input (+).
14
3
FBL
I
Output current Feedback Negative;
Inverting Input (-).
BST1
IO
Bootstrap capacitor;
Used for internal biasing and to drive the Highside Switch HSGD1.
Bypass to SWN1 with external capacitor close to the pin. Pin must not be
left open.
10
BST2
IO
Bootstrap capacitor;
Used for internal biasing and to drive the Highside Switch HSGD2.
Bypass to SWN2 with external capacitor close to the pin. Pin must not be
left open.
17
18
SWCS
SGND
I
I
Current Sense Input;
Inductor current measurement - Non Inverting Input (+).
Current Sense Ground;
Inductor current sense - Inverting Input (-).
Route as Differential net with SWCS on the Layout.
42
IIN1
I
Input Current Monitor Positive;
Non Inverting Input (+), connect to VIN if input current monitor is not
needed.
43
19
IIN2
I
Input Current Monitor Negative;
Inverting Input (-), connect to VIN if input current monitor is not needed.
COMP
O
Compensation Network Pin;
Connect R and C network to pin for stability phase margin adjustment.
Datasheet
6
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Pin Configuration
Table 2
Pin
Pin Definitions and Functions
1)
Symbol
I/O
Function
38
SOFT_START
O
Softstart configuration Pin;
Connect a capacitor CSOFT_START to GND to fix a soft start ramp default
time.
21
36
20
VFB_VIN
DIM_HALF
VFB
I
I
I
Input Voltage Feedback for analog dimming compensation;
Connect with a Resistor divider to Vin. If not used , short to IVCC
Dual Range Output Current;
Double the analog dimming compensation when High.
Voltage Loop Feedback Pin;
VFB is intended to set output overvoltage protection and F.D. output
voltage sensing.
22
39
SET
I
Analog current sense adjustment Pin;
IINMON
O
Input current monitor output;
Monitor pin that produces a voltage proportional to VIN1-IN2. Typical
IINMON will be equal 1 V when VIIN1-VIIN2 = 50 mV.
16
33
32
IOUTMON
LEDCUR
EOMFS
O
O
O
Output current monitor output;
Monitor pin that produces a voltage proportional to VFBH-FBL plus an
offset. Connect with a bypass capacitor to ground
LED current Flag;
An open drain output used to detect the presence of load current on
MFS topologies
End of MFS routine Flag;
An open drain output which is pulled to LOW when MFS routine is
ongoing, released to high when complete.
SPI
30
29
28
27
SI
I
PD Serial data in; Digital input 5 V or 3.3 V.
PD Serial clock; Digital input 5 V or 3.3 V.
SCLK
CSN
SO
I
I
PU SPI chip select; Digital input 5 V or 3.3 V. Active LOW.
O
Serial data out; Digital output, referenced to VDD.
1) O: Output, I: Input,
PD: pull-down circuit integrated,
PU: pull-up circuit integrated
Datasheet
7
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 3
Absolute Maximum Ratings1)
TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Supply Voltages
VIN
Supply Input
VVIN
-0.3
-0.3
-0.3
–
–
–
60
6
V
V
V
–
P_4.1.1
P_4.1.2
P_4.1.3
VDD
VVDD
VIVCC
–
–
Digital supply voltage
IVCC
6
Internal Linear Voltage Regulator
Output voltage
IVCC_EXT
VIVCC_EXT -0.3
–
6
V
–
P_4.1.4
External Linear Voltage Regulator Input
voltage
Gate Driver Stages
LSGD1,2 - PGND1,2
Lowside Gatedriver voltage
VLSGD1,2- -0.3
–
–
–
–
–
–
–
–
5.5
5.5
60
6
V
V
V
V
V
V
V
V
–
P_4.1.54
P_4.1.55
P_4.1.6
P_4.1.7
P_4.1.8
P_4.1.9
P_4.1.10
P_4.1.11
PGND1,2
2)
HSGD1,2 - SWN1,2
Highside Gatedriver voltage
VHSGD1,2- -0.3
SWN1,2
SWN1, SWN2
switching node voltage
VSWN1, 2
-1
–
2)
(BST1-SWN1), (BST2-SWN2)
Boostrap voltage
VBST1,2-
-0.3
-0.3
-0.3
-0.3
-0.5
SWN1,2
BST1, BST2
Boostrap voltage related to GND
VBST1, 2
65
0.3
0.3
0.5
–
–
–
–
SWCS
VSWCS
VSGND
Switch Current Sense Input voltage
SGND
Switch Current Sense GND voltage
SWCS-SGND
VSWCS-
Switch Current Sense differential
voltage
SGND
PGND1,2
Power GND voltage
VPGND1,2
-0.3
–
–
0.3
60
V
V
–
–
P_4.1.28
P_4.1.12
High voltage Pins
IIN1, IIN2
VIIN1, 2
-0.3
Input Current monitor voltage
Datasheet
8
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
General Product Characteristics
Table 3
Absolute Maximum Ratings1) (cont’d)
TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
2)
IIN1-IIN2
VIIN1-IIN2
-0.5
–
0.5
V
P_4.1.13
Input Current monitor differential
voltage
FBH, FBL
Feedback Error Amplifier voltage
VFBH, FBL -0.3
VFBH-FBL -0.5
–
–
60
V
V
–
P_4.1.14
P_4.1.15
2)
FBH-FBL
0.5
Feedback Error Amplifier differential
voltage
EN/INUVLO
VEN/INUVLO -0.3
–
60
V
–
P_4.1.16
Device enable/input undervoltage
lockout
Digital (I/O) Pins
PWMI
Digital Input voltage
VPWMI
VCSN
VSCLK
VSI
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
–
–
5.5
5.5
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
V
V
–
–
–
–
–
–
–
P_4.1.17
P_4.1.18
P_4.1.19
P_4.1.20
P_4.1.21
P_4.1.22
P_4.1.58
CSN
Voltage at Chip Select pin
SCLK
Voltage at Serial Clock pin
SI
Voltage at Serial Input pin
SO
VSO
Voltage at Serial Output pin
SYNC
VSYNC
VLHI
Synchronization Input voltage
LHI
Limp Home Input Voltage
Analog Pins
VFB, VFB_VIN
Output and Input Voltage feedback pins VVFB_VIN
VVFB
,
-0.3
–
–
–
–
–
–
5.5
5.5
3
V
V
V
V
V
V
–
–
–
–
–
–
P_4.1.25
P_4.1.26
P_4.1.62
P_4.1.61
P_4.1.29
P_4.1.30
DIM_HALF
Dual Range Output Current
VDIM_HALF -0.3
FILT
VFILT
-0.3
-0.3
-0.3
-0.3
MFS Filter pin voltage
EOMFS, LEDCUR
Flags output voltage
VFLAGS
VSET
5.5
5.5
3.6
SET
Analog dimming Input voltage
COMP
VCOMP
Compensation Input voltage
Datasheet
9
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
General Product Characteristics
Table 3
Absolute Maximum Ratings1) (cont’d)
TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
SOFT_START
Softstart Voltage
VSOFT_STAR -0.3
–
–
–
–
3.6
3.6
3.6
5.5
V
V
V
V
–
P_4.1.31
P_4.1.32
P_4.1.33
P_4.1.34
T
FREQ
VFREQ
-0.3
-0.3
–
–
–
Voltage at frequency selection pin
IINMON
Voltage at input monitor pin
VIINMON
IOUTMON
VIOUTMON -0.3
Voltage at output monitor pin
Temperatures
Junction Temperature
Storage Temperature
ESD Susceptibility
Tj
-40
-55
–
–
150
150
°C
°C
–
–
P_4.1.35
P_4.1.36
Tstg
ESD Resistivity of all Pins
ESD Resistivity to GND
ESD Resistivity of corner Pins to GND
VESD,HBM -2
VESD,CDM -500
VESD,CDM_c -750
orner
–
–
–
2
kV HBM3)
P_4.1.37
P_4.1.38
P_4.1.39
500
750
V
V
CDM4)
CDM4)
1) Not subject to production test, specified by design.
2) Does not refer to GND
3) ESD susceptibility, Human Body Model “HBM” according to AEC Q100-002
4) ESD susceptibility, Charged Device Model “CDM” AECQ100-011 Rev. D
Note:
Stresses above the ones listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the datasheet. Fault conditions are considered as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation.
4.2
Functional Range
Table 4
Functional Range
Parameter
Symbo
l
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
1)
Device Extended Supply Voltage
Range
VVIN
4.5
–
40
V
P_4.2.1
(parameter
deviations possible)
Device Nominal Supply Voltage
Range
VVIN
8
–
–
36
55
V
V
–
P_4.2.2
P_4.2.5
1)
Power Stage Voltage Range
VPOW
4.5
Datasheet
10
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
General Product Characteristics
Table 4
Functional Range (cont’d)
Symbo
Parameter
Values
Unit Note or
Test Condition
Number
l
Min.
3
Typ. Max.
Digital Supply Voltage
Junction Temperature
VDD
Tj
–
–
5.5
V
–
P_4.2.3
P_4.2.4
-40
150
°C
–
1) Not subject to production test, specified by design.
Note:
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
4.3
Thermal Resistance
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
Table 5
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
1) 2)
Junction to Case
RthJC
RthJA
–
–
0.9
25
–
–
K/W
K/W 3) 2s2p
P_4.3.1
P_4.3.2
Junction to Ambient
1) Not subject to production test, specified by design.
2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed pad are fixed
to ambient temperature). Ta = 25°C; The IC is dissipating 1 W.
3) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area
at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5 mm board. The 2s2p board has
2 outer copper layers (2 x 70 µm Cu) and 2 inner copper layers (2 x 35 µm Cu). A thermal via (diameter = 0.3 mm and
25 µm plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner
layer and second outer layer (bottom) of the JEDEC PCB. Ta = 25°C; The IC is dissipating 1 W.
Datasheet
11
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
5
Power Supply
The TLD5542-1 is supplied by the following pins:
•
•
•
VIN (main supply voltage)
VDD (digital supply voltage)
IVCC_EXT (supply for internal gate driver stages)
The VIN supply, in combination with the VDD supply, provides internal supply voltages for the analog and
digital blocks. In situations where VIN voltage drops below VDD voltage, an increased current consumption
may be observed at the VDD pin.
The SPI and IO interfaces are supplied by the VDD pin.
IVCC_EXT is the supply for the low side driver stages, which is also used to charge, by means of external
Schottky diodes, the bootstrap capacitors. These capacitors provide power to the high side driver stages. If no
external voltage is available, IVCC_EXT pin must be shorted to IVCC, which is the output of an internal 5 V LDO.
The supply pins VIN, VDD and IVCC_EXT have undervoltage detections.
Undervoltage on VDD prevents the activation of the gate driver stages and any SPI communication (the SPI
registers are reset). Undervoltage on IVCC_EXT or IVCC pins forces a deactivation of the driver stages, thus
stopping the switching activity, but has no effect on the SPI register settings.
Moreover the double function pin EN/INUVLO can be used as an input undervoltage protection by placing a
resistor divider from VIN to GND (refer to Chapter 10.3).
If EN/INUVLO undervoltage is detected, it will turn-off the IVCC voltage regulator, stop switching, stop
communications and reset all the registers.
Figure 4 shows a basic concept drawing of the supply domains and interactions among pins VIN, VDD and
IVCC/IVCC_EXT.
VIN
VREG (5V)
R1
IVCC
Internal pre-regulated
EN/INUVLO
voltage Supply
Undervoltage
detection
R2
IVCC_EXT
VREG
digital
VREG
analog
LS - Drivers
HS - Drivers
PGNDx
BSTx
Undervoltage
detection
Bandgap
Reference
Register
Banks
VDD
SPI & I/O
LOGIC
SWNx
Figure 4
Power Supply Concept Drawing
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
Usage of EN/INUVLO pin in different applications
The pin EN/INUVLO is a double function pin and can be used to put the device into a low current consumption
mode. An undervoltage threshold is fixed by placing an external resistor divider (A) in order to avoid low
voltage operating conditions. This pin can be driven by a µC-port as shown in (B) (C).
A
C
B
D
Vin
Vin
Vin
Vin
VIN
VIN
VIN
VIN
R1
R2
R1
R2
µC Port
EN/INUVLO
GND
EN/INUVLO
GND
EN/INUVLO
GND
EN/INUVLO
GND
µC Port
Figure 5
Usage of EN/INUVLO pin in different applications
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
5.1
Different Power States
TLD5542-1 has the following power states:
•
•
•
•
SLEEP state
IDLE state
LIMP HOME state
ACTIVE state
The transition between the power states is determined according to these variables after a filter time of max.
3 clock cycles:
•
•
•
•
•
•
•
VIN level
EN/INUVLO level
IVCC level
IVCC_EXT level
VDD level
LHI level
DVCCTRL.IDLEbit state
The state diagram including the possible transitions is shown in Figure 6.
The Power-up condition is entered when the supply voltage VVIN exceed its minimum supply voltage threshold
VVIN(ON)
.
SLEEP
When the device is powered it enters the SLEEP state, all outputs are OFF and the SPI registers are reset,
independently from the supply voltages at the pins VIN , VDD, IVCC, and IVCC_EXT. The current consumption
is low. Refer to parameters: IVDD(SLEEP), and IVIN(SLEEP)
.
The transition from SLEEP to ACTIVE state requires a specified time: tACTIVE
.
IDLE
In IDLE state, the current consumption of the device can reach the limits given by parameter IVDD (P_5.3.4). The
internal voltage regulator and IVCC linear regulator are working. Not all diagnosis functions are available
(refer to Chapter 10 for additional informations). In this state there is no switching activity, independently
from the supply voltages VIN, VDD, IVCC and IVCC_EXT. When VDD is available, the SPI registers are working and
SPI communication is possible.
Limp Home
The Limp Home state is beneficial to fulfill system safety requirements and provides the possibility to
maintain a defined current/voltage level on the output via a backup control circuitry. The backup control
circuitry turns on required loads during a malfunction of the µC. For detailed info, refer to Chapter 8.
When Limp Home state is entered, SPI registers are reset to their default values and SPI communication is
possible but only in read mode (SPI registers can be read but cannot be written). In order to regulate the
output current/voltage, it is necessary that VIN and IVCC_EXT are present and above their undervoltage
threshold.
ACTIVE
In active state the device will start switching activity to provide power at the output only when PWMI = HIGH.
To start the Highside gate drivers HSGD1,2 the voltage level VBST1,2 - VSWN1,2 needs to be above the threshold
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
VBST1,2 - VSWN1,2_UVth. In ACTIVE state the device current consumption via VIN and VDD is dependent on the
external MOSFET used and the switching frequency fSW
.
Power-up
LHI = LOW
EN/INUVLO = LOW
& EN/INUVLO = HIGH
SLEEP
EN/INUVLO = LOW
LHI = HIGH
& EN/INUVLO = HIGH
EN/INUVLO = LOW
LHI = HIGH
IDLE
LIMP HOME
VIN = LOW
or IVCC = LOW
VIN = HIGH
& IVCC = HIGH
EN/INUVLO = LOW
or IVCC_EXT = LOW
or VDD = LOW
& IVCC_EXT = HIGH
& VDD = HIGH
or DVCCTRL.IDLE = HIGH
& DVCCTRL.IDLE = LOW
LHI = LOW
LHI = HIGH
ACTIVE
Figure 6
Simplified State Diagram
5.2
Different Possibilities to RESET the device
There are several reset triggers implemented in the device.
After any kind of reset, the Transmission Error Flag (TER) is set to HIGH.
Under Voltage Reset:
EN/INUVLO: When EN/INUVLO is below VEN/INUVLOth (P_5.3.7), the SPI interface is not working and all the
registers are reset to their default values. In addition, the device enters SLEEP mode and the current
consumption is minimized.
VDD: When VVDD is below VVDD(UV) (P_5.3.6), the SPI interface is not working and all the registers are reset to their
default values.
Reset via SPI command:
There is a command (DVCCTRL.SWRST= HIGH) available to RESET all writeable registers with the exception
of MUXCTRL, to their default values. Note that the result coming from the Calibration routine, which is
readable by the SPI when DVCCTRL.ENCAL= HIGH, is not reset by the SWRST.
Reset via Limp Home:
When Limp Home state is detected the registers are reset to the default values.
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
5.3
Electrical Characteristics
Table 6
EC Power Supply
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Power Supply VIN
Input Voltage Startup
VVIN(ON)
–
–
–
–
–
–
5
–
4.7
4.5
7
V
V
VIN increasing;
P_5.3.1
V
V
EN/INUVLO = HIGH;
DD = 5 V;
IVCC = IVCC_EXT =
10 mA;
Input Undervoltage switch OFF VVIN(OFF)
VIN decreasing;
P_5.3.14
P_5.3.2
P_5.3.3
V
V
EN/INUVLO = HIGH;
DD = 5 V;
IVCC = IVCC_EXT =
10 mA;
Device operating current
IVIN(ACTIVE)
mA 1)ACTIVE mode;
VPWMI = 0 V;
VVFB_VIN
1/(51+1)*VVIN
VFB=0.7V
VEN/INUVLO = 0 V;
CSN = VDD = 5 V;
=
;
V
VIN Sleep mode supply current IVIN(SLEEP)
Digital Power Supply VDD
1.5
µA
V
VIN = 13.5 V;
VIVCC = VIVCC_EXT= 0 V;
Digital supply current
IVDD
–
–
–
–
0.5
1.5
mA VIN = 13.5 V;
SCLK = 0 Hz;
VPWMI = 0 V;
EN =VCSN = VDD = 5 V;
VEN/INUVLO = 0 V;
CSN = VDD = 5 V;
VIN = 13.5 V;
IVCC = VIVCC_EXT = 0 V;
P_5.3.4
P_5.3.5
f
V
Digital Supply Sleep mode
current
IVDD(SLEEP)
µA
V
V
V
Undervoltage shutdown
threshold voltage
VVDD(UV)
1
–
3
VCSN = VDD
;
P_5.3.6
P_5.3.7
VSI = VSCLK = 0 V;
SO from LOW to HIGH
impedance;
EN/INUVLO Pin characteristics
Input Undervoltage falling
Threshold
VEN/INUVLOth 1.6
1.75 1.9
V
–
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
Table 6
EC Power Supply (cont’d)
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
1)
EN/INUVLO Rising Hysteresis
VEN/INUVLO(hy
–
90
–
mV
P_5.3.8
P_5.3.9
P_5.3.10
st)
EN/INUVLO input Current LOW IEN/INUVLO(LO 0.45 0.89 1.34 µA
VEN/INUVLO = 0.8 V;
VEN/INUVLO = 2 V;
W)
EN/INUVLO input Current HIGH IEN/INUVLO(HI 1.1
2.2
3.3
µA
GH)
LHI Pin characteristics
LOW level
VLHI(L)
VLHI(H)
ILHI(L)
ILHI(H)
0
-
0.8
5.5
18
V
–
P_5.3.16
P_5.3.17
P_5.3.18
P_5.3.19
HIGH level
2.0
6
-
V
–
L-Input pull-down current
H-Input pull-down current
Timings
12
30
μA
μA
VLHI = 0.8 V;
VLHI = 2.0 V;
15
45
1)
SLEEP mode to ACTIVE time
tACTIVE
–
–
0.7
ms
P_5.3.11
VIVCC = VIVCC_EXT
IVCC = 10 µF;
;
C
VIN = 13.5 V;
VDD = 5 V;
1) Not subject to production test, specified by design.
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6
Regulator Description
The TLD5542-1 includes all of the functions necessary to provide constant current to the output as usually
required to drive LEDs. A voltage mode regulation can also be implemented (Refer to Chapter 6.6).
It is designed to control 4 gate driver outputs in a H-Bridge topology by using only one inductor and 4 external
MOSFETs. This topology is able to operate in high power Boost, Buck-Boost and Buck mode applications with
maximum efficiency.
The transition between the different regulation modes is done automatically by the device itself, with respect
to the application boundary conditions.
The Buck-Boost to Boost transition can be smoothed by mean of BB_BST_CMP bitfield.
A SPI flag provides mode feedback to the µC (refer to SPI bits REGUSETMON.REGUMODFB).
6.1
Regulator Diagram Description
The analog current control loop (A5, A6 with complessive gain = IFBxgm) connected to the sensing pins FBL,
FBH regulates the output current.
The regulator function is implemented by a pulse width modulated (PWM) current mode controller. The error
in the output current loop is used to determine the appropriate duty cycle to get a constant output current.
An external compensation network (RCOMP, CCOMP) is used to adjust the control loop to various application
boundary conditions.
The inductor current for the current mode loop is sensed by the RSWCS resistor.
RSWCS is used also to limit the maximum external switches / inductor current.
If the Voltage across RSWCS exceeds its overcurrent threshold (VSWCS_buck or VSWCS_boost for buck or boost
operation respectively) the device reduces the duty cycle in order to bring the switches current below the
imposed limit.
The current mode controller has a built-in slope compensation as well to prevent sub-harmonic oscillations.
The control loop logic block (LOGIC) provides a PWM signal to four internal gate drivers. The gate drivers
(HSGD1,2 and LSGD1,2) are used to drive external MOSFETs in an H-Bridge setup . Once the soft start expires
a forced CCM regulation mode is performed.
The control loop block diagram displayed in Figure 7 shows a typical constant current application. The
voltage across RFB sets the output current.
The output current is adjusted via the SPI register LEDCURRADIM.ADIMVALplus an offset trimming on
LEDCURRCAL.CALIBVALregister. Refer to Chapter 8.1 for more details.
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
RFB
IIN
IOUT
VIN
COUT
M4
M3
M1
M2
HSGD2
LSGD2
HSGD1
LSGD1
FBH
FBL
VOUT
LOUT
+
-
A5
ISWCSx
SWCS
SGND
BOOST
A2
A8
A9
HSGD1
HSGD2
RSWCS
SLOPE SELECTION
& Compensation
GATE
DRIVER
LOGIC
LSGD1
LSGD2
A3
BUCK
CLK
VFEEDBACK
-
I
Soft_Start_PU
RVFBH2
RVFBH1
VFB_VIN
10k
VFB
SOFT
START
LOGIC
Correction
Unit
RVFBL2
A6
RVFBL1
VREF_INT
GAIN
I
Soft_Start_PD
SOFT
START
COMP
RCOMP
CCOMP
8 bit resolution
4 bit calibration
DAC
0
1
VCOMP
VSST
CSOFT_START
MIN
SET
DAC_OFF OR
LHI
Figure 7
Regulator Block Diagram - TLD5542-1
An Infineon proprietary correction unit (see Figure 7) ensures optimum performance on MFS architecture,
minimizing dependency of comp voltage by the analog dimming value, and reduces overshoots during load
jump up.
The correction unit provides an input voltage feedback to the regulator loop, proportional to Vout/Vin through
the VFB/VFB_VIN signals. Therefore, the 2 voltage dividers at VFB and VIN_VFB are related to each other, and
their ratio is setting the feedback amount. Correction unit feedback can be disabled by setting
SWTMOD.VFB_VIN_OFF bitfield.
The negative feedback applied to VCOMP is also proportional to the analog dimming value. The smaller the
analog dimming value, the larger is the feedback voltage:
ꢀꢀꢁꢄ
(6.1)
ꢊ
[ ]ꢌ
ꢀꢁꢂꢂꢃꢄꢅꢆꢇ ≈ 0.05 ∙
∙ 100% − ꢅꢃꢈꢋ %
[ꢀ]
ꢀꢀꢁꢄ
ꢀꢈꢉ
In order to ensure good accuracy on VFB_VIN reading, the total resistance on the divider should be less than
100kΩ. It is recommended to have VFB_VIN / VFB voltage dividers ratio equal to 1 / 1.5 (I.E.
RVFBH2=RVFBH1=51kΩ , RVFBL2=1kΩ , RVFBL1 =1.5kΩ).
If the input voltage feedback is too high (I.E. RVFBL2 is too low), VCOMP may saturate toward the operating range
limit ( 2V ) and the output current regulation would be affected. Minimum temperature, maximum Vout/Vin
ratio and minimum ADIM value shall be considered as worst case condition when checking for VCOMP dynamic
operating range.
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6.2
Adjustable Soft Start Ramp
The soft start routine has 2 functionalities:
•
•
Fault management: fault mask and wait-before-retry time (Figure 8 and chapter Chapter 10.2)
Limit input inrush current and output overshoots by limiting Vcomp (Figure 7) in boost mode
The soft start routine is applied in two cases:
•
•
At startup (first PWM rise after IDLE to ACTIVE transition)
After output short to GND detection
The soft start routine is active during the rising and falling edges of the VSST. The soft start timing is defined
by a capacitor placed at the SOFT_START pin and the pull-up and pull down current sources (ISoft_Start_PU
ISoft_Start_PD).
,
Minimum value for soft start capacitor has to be designed such that, at startup, the output voltage exceeds the
short to ground threshold (VFBH_S2G_inc), before the soft start voltage reaches VSOFT_START_LOFF . Minimum
temperature and minimum input voltage shall be considered as worst case condition for previously
mentioned dimensioning.
tACTIVE
VIN
VIN(ON)
EN/INUVLO
VIVCC_EXT
VIVCC_EXT_RTH,d
+
VIVCCX_HYST
t
PWMI
FBH
8 clock cycles
V
VFFBBHH__SS22GG__idnecc
SWN
SHORT
DETECTION
I
SOFT_START_PU
ISOFT_START
I
SOFT_START_PD
V
soft_Start_reg
V
soft_Start_LOFF
VSOFT_START
Vsoft_Start_RESET
Normal
Operation
Normal
Operation
Application
Status
Startup
Vout shorted to GND
WAIT_BEFORE_RETRY
FAULT_MASK
t
SOFT_START
Figure 8
Soft Start timing diagram on a short to ground detected by the FBH pin
Soft Start rising edge time is aproximately:
ꢆ
ꢎꢒꢓꢍ _ꢎꢍꢔꢕꢍ
(6.2)
ꢍꢎꢏꢁꢐ_ꢎꢐꢅꢑꢐ =VSoft_Start_LOFF
∙
ꢈ
ꢎꢒꢓꢍ _ꢎꢍꢔꢕꢍ _ꢖꢗ
The Soft Start routine limits the inrush current during boost mode by clamping the COMP pin through a buffer
as in Figure 7. Therefore this functionality is effective only when Soft Start capacitor is sufficiently larger than
the comp capacitor.
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
If the inductor current is low during the soft start rising edge, DCM is enabled and MOSFET M4 is disabled. If
the inductor current increases then M4 may get enabled.
After the soft start has been completed (VSOFT_START > VSOFT_START_LOFF) CCM is forced and M4 is permanently
enabled, independently from the inductor current level.
To avoid overshoot at startup on voltage regulators, may be useful to keep CCM forced also during soft start
by setting CCM_4EVER bitfield.
If a short circuit on the output is detected, a pull-down current source ISOFT_START_PD (P_6.4.20) is activated. This
current brings down the VSOFT_START until VSOFT_START_RESET (P_6.4.22) is reached. Afterwards the pull-up current
source ISOFT_START_PU (P_6.4.19) turns on again. If the fault condition hasn’t been removed until VSOFT_START_LOFF
(P_6.4.21) is reached, the pull-down current source turns back on again, initiating a new cycle. This will
continue until the fault is removed.
If a low duty cycle PWMI is applied at startup, the output voltage may be still below the short to ground
threshold once the soft start fault mask is expired. Therefore the TLD5542-1 has a special feature in order to
prevent short to ground in case of startup with low duty cycle PWM.
At first PWMI rise after IDLE to ACTIVE transition, the internal PWM signal is extended if the following
conditions are met:
•
•
•
A capacitor is connected to the IOUTMON pin (suggested 220pF)
IDLE mode is kept for less than 10ms
PWMI rise is provided within 10ms from IDLE to ACTIVE transition
The PWMI extension last until one of the two following conditions is reached:
•
•
Until VSOFT_START exceeds VSoft_Start_LOFF
Until VFBH-FBL exceeds VFBH_FBL_IN
6.3
Switching Frequency setup
The switching frequency can be set from 200 kHz to 700 kHz by an external resistor connected from the FREQ
pin to GND or by supplying a sync signal as specified in chapter Chapter 11.2. Select the switching frequency
with an external resistor according to the graph in Figure 9 or the following approximate formulas.
fSW [kHz] = 5375*(RFREQ[kΩ])−0.8
RFREQ[kΩ]= 46023*(fSW[kHz])−1.25
(6.3)
(6.4)
Figure 9
Switching Frequency fSW versus Frequency Select Resistor to GND RFREQ
Datasheet
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Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6.4
Operation of 4 switches H-Bridge architecture
Inductor LOUT connects in an H-Bridge configuration with 4 external N channel MOSFETs (M1, M2, M3 & M4)
BOOST
BUCK-BOOST
BUCK
MODE
MODE
MODE
M1
M2
M3
M4
ON
PWM
PWM
PWM
PWM
PWM
PWM
OFF
ON
OFF
PWM
PWM
Figure 10 4 switches H-Bridge architecture Transistor Status summary
VIN
VOUT
M1
M4
HSGD2
LSGD2
HSGD1
LSGD1
LOUT
SWN1
SWN2
M2
M3
RSWCS
Figure 11 4 switches H-Bridge architecture overview
6.4.1
Boost mode (VIN < VOUT)
•
•
•
•
•
M1 is always ON, M2 is always OFF
Every cycle M3 turns ON first and inductor current is sensed (peak current control)
M3 stays ON until the upper reference threshold is reached across RSWCS (Energizing)
M3 turns OFF, M4 turns ON until the end of the cycle (Recirculation)
Switches M3 and M4 alternate, behaving like a typical synchronous boost Regulator (see Figure 12)
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
VIN
VOUT
ON
M1
M4
(2) Recirculation
ILOUT
HSGD2
LSGD2
HSGD1
LSGD1
LOUT
SWN1
SWN2
(1) Energizing
OFF
M2
M3
t
M1
+
M4
M1
+
M4
M1
+
M4
M1+M3
M1+M3
M1+M3
RSWCS
Figure 12 4 switches H-Bridge architecture in BOOST mode
Simplified comparison of 4 switches H-Bridge architecture to traditional asynchronous Boost approach.
•
•
•
M2 is always OFF in this mode (open)
M1 is always ON in this mode (closed connection of inductor to VIN)
M4 acts as a synchronous diode, with significantly lower conduction power losses (I2 x RDSON vs. 0.7 V x I)
Note:
Diode is source of losses and lower system efficiency!
LOUT
LOUT
D1
M1 (ON)
M4
VIN
VOUT
VOUT
VIN
M2
(OFF)
HSGD2
LSGD2
HSGD1
M3
M3
LSGD1
RSWCS
RSWCS
b) standard asynchronous BOOSTER
a) 4 switch architecture BOOSTER
Figure 13 4 switches H-Bridge architecture in BOOST mode compared to standard async Booster
6.4.2
Buck mode (VIN > VOUT)
•
•
•
•
•
M4 is always ON, M3 is always OFF
Every cycle M2 turns ON and inductor current is sensed (valley current control)
M2 stays ON until the lower reference threshold is reached across RSWCS (Recirculation)
M2 turns OFF, M1 turns ON until the end of the cycle (Energizing)
Switches M1 and M2 alternate, behaving like a typical synchronous BUCK Regulator (see Figure 14)
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
VIN
VOUT
ILOUT
ON
M1
M4
(3) Energizing
HSGD2
LSGD2
HSGD1
LSGD1
LOUT
SWN1
SWN2
(4) Recirculation
t
OFF
M1
+
M4
M1
+
M4
M1
+
M4
M2
M3
M2+M4
M2+M4
M2+M4
RSWCS
Figure 14 4 switches H-Bridge architecture in BUCK mode
Simplified comparison of 4 switches architecture to traditional asynchronous Buck approach.
•
•
•
M3 is always OFF in this mode (open).
M4 is always ON in this mode (closed connection inductor to VOUT).
M2 acts as a synchronous diode, with significantly lower conduction losses (I2 x RDSON vs. 0.7 V x I)
LOUT
M4
(ON)
LOUT
M1
M1
VIN
VOUT
VIN
VOUT
HSGD1
LSGD1
M3
(OFF)
HSGD1
HSGD2
M2
LSGD2
D1
RSWCS
b) standard asynchronous BUCK
a) 4 switch architecture BUCK
Figure 15 4 switches H-Bridge architecture in BUCK mode compared to standard async BUCK
6.4.3
Buck-Boost mode (VIN ~ VOUT)
•
•
When VIN is close to VOUT the controller is in Buck-Boost operation
All switches are switching in buck-boost operation. The direct energy transfer from the Input to the output
(M1+M4 = ON) is beneficial to reduce ripple current and improves the energy efficiency of the Buck-Boost
control scheme
•
The two buck boost waveforms and switching behaviors are displayed in Figure 16 below
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
VIN ≤ VOUT
ILOUT
VIN
VOUT
M1
M4
(2) Direct Transfer
HSGD2
LSGD2
HSGD1
LSGD1
(4) Direct Transfer
M1
+
M3
M1
+
M4
M1
+
M4
M1
+
M3
M1
+
M4
M1
+
M4
M1
+
M3
M1
+
M4
M1
+
M4
t
SWN1
SWN2
LOUT
(3) Recirculation
(1) Energizing
VIN ≥ VOUT
ILOUT
M2
M3
RSWCS
M2
+
M1
+
M1
+
M2
+
M1
+
M1
+
M2
+
M1
+
M1
+
t
M4
M4
M4
M4
M4
M4
M4
M4
M4
Figure 16 4 switches H-Bridge architecture in BUCK-BOOST mode
6.5
Fast Output Discharge Operation Mode - Multi Floating Switches Topology
Multiple light functions can be driven by a single DC/DC converter adopting a Multi Floating Switch (MFS)
topology. In a MFS topology, each LED Function is connected in series and can be independently turned off via
a bypass switch. Because of the series connections, all the functions are driven with the same current (except
for Loads with complementary duty cycle I.E. DRL, LB ). Different brightness can be achieved with individual
PWM duty cycles.
In order to drive different LED functions in this topology, a Buck Boost converter is probably needed. A single
stage buck boost topology has high efficiency buts requires several µF of output capacitance (COUT). The extra
voltage present on this capacitor, when shorting one function to turn it off, may create a current spike in the
LEDs that have to remain on.
The TLD5542-1 has a dedicated state machine which controls a fast discharge of the output cap to a desired
fraction of the initial output voltage. This Fast Output Discharge feature (F.D.), if carefully configured, limits
the current spike during load jump events preventing LED damage.
An Example of the Multi Floating Switch topology architecture and operation are shown in Figure 17
INITIAL CONDITION
FAST DISCHARGE
FINAL CONDITION
Vout
Disharging
Vout
Initial
Vout
Final
COUT
CIN
COUT
C
I
Disch
OUT
VBAT
DC/DC
LITIX FLEX
DC/DC
LITIX FLEX
DC/DC
LITIX FLEX
F1
OFF
F1
OFF
To VFB
To VFB
To VFB
F1
ON
External MOSFET
Control via µC
External MOSFET
Control via µC
External MOSFET
Control via µC
(A)
(B)
(C)
F2
OFF
F2
ON
F2
ON
External MOSFET
Control via µC
External MOSFET
Control via µC
External MOSFET
Control via µC
Figure 17 Multi Floating Switch topology: operation sequence on 2 Functions: (F1+F2) to (F2)
Datasheet
25
Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
The F.D. operation consists of discharging the capacitor COUT to the final load voltage (Figure 17-B) before the
bypass switch closure. The external Microcontroller Software has to take care of the synchronization between
the TLD5542-1 F.D. operation and the bypass Switches activation.
The discharged energy from COUT is recovered back to the Input capacitor CIN which could cause a small
overshoot on the CIN itself. This feature allows high efficiency designs also when PWM operation with repetitive
Load Jumps is needed.
The F.D. feature is needed when a negative VOUT step is performed, so when one or more LED functions are
switched off. If additional LED functions are turned on, increasing the output voltage, the F.D. does not have
to be used.
In case analog dimming is performed during a load Jump (I.E. from 1A LB to 300mA DRL), even with a positive
VOUT step, a discharge of the COMP capacitor could be necessary.
In MFS topologies, a short interruption of the current is observed during the Load Transitions (either positive
or negative) in all the functions, until VOUT is stable and the device control loop is able to provide the target
output current.
We will refer to any Voltage-Current or Load configuration just before the Load Jump as "Initial" (Figure 17-
A), while we will refer to any value after the system is in the new Load configuration as "Final" (Figure 17-C).
Set the Target COUT discharge voltage
The Target output voltage (VOUTFinal) of an F.D. operation is communicated to the TLD5542-1 as a fraction of the
VOUT at the beginning of the Jump (VOUTInitial), and not as an absolute Value.
In order to F.D. the output Capacitor to a desired Ratio of the initial voltage, two SPI commands have to be sent
to the TLD5542-1 register MFSSETUP1.
•
•
The first is to write in the MFSSETUP1.LEDCHAIN the Ratio Denominator
The second is to write in the MFSSETUP1 register the Ratio Numerator and the Start Of Multi Floating
Switch, respectively in the LEDCHAIN and SOMFS bitfields
The time interval between the Ratio Denominator and Numerator SPI commands, needs to be long enough to
sample the Initial Voltage of the F.D. in the FILT capacitor.
After the second command, as soon as the Chip select is raised the F.D. begins. The final output voltage of the
F.D. operation, after a MFS routine is correctly performed, will be approximately:
RatioNumerator
(6.5)
VOUTFinal
=
VOUTInitial
RatioDenominator
If RatioNumerator is bigger than RatioDenominator, the output voltage remains constant, but the COMP
capacitor is discharged during all the TPREP
F.D. operation will exit if the output voltage reaches VFBH_S2G_dec
.
Example:
In order to jump from 6LED (18 V) to 2LEDs (6 V), the Ratio is 1/3 of initial voltage.
So the 2 SPI commands that have to be sent are:
Spi command 1: set MFSSETUP1 to 0x06 (Ratio Denominator = 6)
Spi command 2: set MFSSETUP1 to 0x22 (Ratio Numerator+SOMFS = 0x02+0x20)
Preparation Time tprep
:
The TLD5542-1 enables the user to set a period tprep on the load jump, where CCOMP is discharged continuously
with a constant current (IEA_neg).
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
The Preparation Time has to be sufficient for the capacitor CCOMP to be discharged the desired value.
(6.6)
ꢆꢆꢏꢋꢖ
ꢍꢃꢘꢙꢚℎꢆꢒꢛꢜ = ꢃꢝꢚꢒꢛꢜ
= ꢍꢜꢕꢟꢜ
ꢈꢂꢅ_ꢞꢟꢠ
In order to set a preparation time on the TLD5542-1, a SPI command has to be sent to the register
MFSSETUP2.MFSDLY).
The Equation (6.7) below describes the relationship between the switching frequency fSW and the
MFSSETUP2.MFSDLY register value.
1
(6.7)
tprep
=
[2 + (MFSDLY )dec
]
fSW
For SPI command details refer to Chapter 12.6.
The F.D. procedure is automatically extended until Cout capacitor is discharged to the target value, and Tprep
is expired. If there is the need to do not discharge the CCOMP, but Discharge only the Vout , is possible to set
MFSSETUP2.MFSDLY to 0 on a F.D. routine, Cout will be anyway discharged to the target voltage.
Fast Discharge Phase
After programming the desired output voltage Ratio via SPI , the right Preparation Time and activating the
state machine (MFSSETUP1.SOMFS= HIGH) the TLD5542-1 inverts the inductor current IL and keeps its
negative peak at a reduced switch current limit ISwLim until the VOUT reaches the desired target.
ꢀ
2
3
ꢎꢣꢆꢎ_ꢤꢒꢒꢙꢍ
ꢈꢎꢡꢢꢘꢛ
≈
∙
(6.8)
ꢑꢎꢣꢆꢎ
Figure 18 displays the relation of inductor current IL and the output voltage VOUT during a fast output
discharge operation mode.
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
External
Mosfet
Closure
I F1
I F2
No current at the Load
during F.O.D.
EOMFS
LED N. FINAL
+ SOMF
LED N. INITIAL
TPREP
SPI CSN
IL
TPREP
TDISCHARGE_COUT
1CLK
ISwLim
VCOMP
VOUT_INITIAL
VOUT_FINAL
Normal Switching activity
F1 on
Current
Recovery
Break
Low
Fast Output Discharge
Normal Switching activity
F1+F2 on
Figure 18 Fast Output Discharge timing diagram
If the discharge current limit ISwLim needs to be reduced further , the MFSSETUP1.ILIM_HALF_MFSbit can
be used to reduce it to the Equation (6.9) (only during the F.D. phase and not in normal operation), see SPI
Chapter for further details Chapter 12.6.
ꢀ
1
2
ꢎꢣꢆꢎ_ꢤꢒꢒꢙꢍ
(6.9)
ꢈꢎꢡꢢꢘꢛ
≈
∙
ꢑꢎꢣꢆꢎ
Setting the EA_IOUT_MFS bit will reduce (only during the F.D. phase) the saturation current of the error
amplifier A6 (IEA_neg) that discharges the Comp capacitor.
Once VOUT reaches the desired target, the current recovery phase brings IL from a negative value back to 0 A
and the device stays in “Brake-Low condition” (both Lowside gatedrivers = ON) until the programmed
preparation time (MFSSETUP2.MFSDLY) expires.
Only when both the current recovery phase has ended and tprep is expired an SPI flag( STD bit EOMFS) and the
pin EOMFS are set to HIGH. One clock cycle after EOMFS is asserted, the TLD5542-1 starts automatically
switching again.
Figure 18 displays one Fast Output Discharge cycle.
Sequence of operations to perform a Fast Output Discharge
In order to perform a F.D .operation, the user has to :
•
•
•
Send via SPI to MFSSETUP1.LEDCHAINthe Ratio Denominator.
Set via SPI an adequate Preparation Time
Send via SPI to MFSSETUP1.LEDCHAINthe Ration Numerator + SOMFS
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
•
•
Wait until preparation time is expired and Vout has reached the target value (EOMFS is asserted)
Adjust the Floating switches to the new configuration
In case of short to GND the routine is not executed or it is aborted.
At startup (after EN = High), if PWM has never been set to HIGH, F.D. routine can not be executed.
If a F.D. is needed just after device enable (for instance to lower the output voltage after a low battery reset),
PWMI has to be set to 1 before the SOMFS command, and the F.D. procedure will be executed only once the SS
is expired.
Other than for the 2 above exceptions, it is always possible to perform F.D. independently from PWM signal
and output overvoltage condition.
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6.6
Programming Output Voltage (Constant Voltage Regulation)
For a voltage regulator, the output voltage can be set by selecting the values RFB1, RFB2 according to the
following Equation (6.10):
ꢑꢁꢄ1 + ꢑꢁꢄ2
(6.10)
ꢀꢏꢗꢐ
=
∙ ꢀꢁꢄꢥ−ꢁꢄꢢ
ꢑꢁꢄ1
Refer to the voltage regulator application drawing on Figure 45.
After the output voltage is fixed via the resistor divider, the value can be changed via the Analog Dimming bits
ADIMVAL.
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6.7
Electrical Characteristics
Table 7
EC Regulator
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Regulator:
V
FBH-FBL_REF reference voltage
VFBH-
145.5 150
154.5 mV ADIMVAL= 240;
P_6.4.1
P_6.4.5
FBL_REF
VFBH-FBL_REF reference voltage
VFBH-
12
15
18
mV ADIMVAL=24;
Calibration
Procedure not
performed
1)
FBL_REF
FBH Bias current @ highside
sensing setup
IFBH_HSS
IFBL_HSS
IEA_pos
65
17
25
110
30
155
43
µA
µA
µA
V
= 7 V;
P_6.4.8
P_6.4.9
P_6.10.2
FBL
VFBH - FBL = 150 mV;
1)
FBL Bias current @ highside
sensing setup
V
= 7 V;
FBL
VFBH - FBL = 150 mV;
A6 sense Amp +sat current
29
33
1)VCOMP = 1V;
ADIMVAL = 240;
VFBH - FBL = 0 mV
A6 sense Amp -sat current
IEA_neg
-63
–
-56
-49
µA
1)VCOMP = 1V;
ADIMVAL = 240;
P_6.10.3
VFBH - FBL = 500 mV
A5A6 sense Amp gm
IFBxgm
890
1.4
91
–
µS
V
1)EA_GM=0
P_6.4.10
P_6.4.11
P_6.4.12
Output Monitor Voltage
Maximum BOOST Duty Cycle
VIOUTMON 1.33
1.47
93
VFBH - FBL = 150 mV;
1)
DBOOST_MA 89
%
f = 300 kHZ;
sw
X
1)
Input current Monitor Voltage VIINMON
0.95
1
1.05
82
V
V
= 50 mV;
P_6.4.15
IIN1 - IIN2
VIIN1 = VVIN(ON) to 55 V;
1)
Switch Peak Over Current
Threshold - BOOST
VSWCS_boost 70
VSWCS_buck -60
76
-50
mV
mV
P_10.8.1
5
1)
Switch Peak Over Current
Threshold - BUCK
-40
P_10.8.1
6
Soft Start
Soft Start pull up current
ISoft_Start_P 22
26
32
µA
µA
V
VSoft_Start = 1 V;
P_6.4.19
P_6.4.20
P_6.4.21
P_6.4.22
U
Soft Start pull down current
ISoft_Start_P 2.2
2.6
1.75
0.2
3.2
1.85
0.3
VSoft_Start = 1 V;
D
Soft Start Latch-OFF Threshold VSoft_Start_L 1.65
–
–
OFF
Soft Start Reset Threshold
VSoft_Start_R 0.1
V
ESET
Datasheet
31
Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
Table 7
EC Regulator (cont’d)
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Soft Start Voltage during
regulation
VSoft_Start_r 1.9
2
2.1
24
-
V
1)No Faults
P_6.9.3
eg
Output Current init reference
Voltage VFBH-FBL
VFBH_FBL_IN 11
17.5
120
mV VFB = 1.4 V;
P_10.8.1
0
1)
Output Current EA_GM boost
reference Voltage VFBH-FBL
VFBH_FBL_E
–
mV
V
= 1.4 V;
P_6.10.4
FB
ADIMVAL=240;
A
Oscillator
Switching Frequency
fSW
285
300
315
kHz Tj = 25°C;
P_6.4.23
RFREQ= 37.4 kΩ;
SYNC Frequency
fSYNC
200
2
–
–
700
–
kHz
V
–
–
P_6.4.24
P_6.4.25
SYNC
VSYNC,ON
Turn On Threshold
SYNC
Turn Off Threshold
VSYNC,OFF
ISYNC,H
–
–
0.8
45
18
V
–
P_6.4.26
P_6.4.62
P_6.4.63
SYNC
High Input Current
15
6
30
12
µA
µA
VSYNC = 2.0 V;
VSYNC = 0.8 V;
SYNC
ISYNC,L
Low Input Current
Gate Driver for external Switch
Gate Driver undervoltage
threshold VBST1,2-
VSWN1,2_UVth
VBST1,2
VSWN1,2_UVt
-
3.4
–
4
V
VBST1,2 - VSWN1,2
decreasing;
P_6.4.64
h
HSGD1,2 NMOS driver on-state RDS(ON_PU) 1.4
2.3
1.2
2.3
1.2
–
3.7
2.2
3.7
1.8
–
Ω
VBST1,2 - VSWN1,2 = 5 V; P_6.4.28
source = 100 mA;
VBST1,2 - VSWN1,2 = 5 V; P_6.4.29
Isink = 100 mA;
resistance (Gate Pull Up)
I
HS
HSGD1,2 NMOS driver on-state RDS(ON_PD) 0.6
Ω
resistance (Gate Pull Down)
HS
LSGD1,2 NMOS driver on-state RDS(ON_PU) 1.4
Ω
VIVCC_EXT = 5 V;
Isource = 100 mA;
P_6.4.30
P_6.4.31
P_6.4.32
resistance (Gate Pull Up)
LS
LSGD1,2 NMOS driver on-state RDS(ON_PD)L 0.4
Ω
VIVCC_EXT = 5 V;
Isink = 100 mA;
1)
resistance (Gate Pull Down)
S
HSGD1,2 Gate Driver peak
sourcing current
IHSGD1,2_SR 380
mA
VHSGD1,2 - VSWN1,2 = 1 V
C
to 4 V;
V
BST1,2 - VSWN1,2 = 5 V
1)
HSGD1,2 Gate Driver peak
sinking current
IHSGD1,2_SN 410
–
–
mA
P_6.4.33
VHSGD1,2 - VSWN1,2 = 4 V
K
to 1 V;
VBST1,2 - VSWN1,2 = 5 V
Datasheet
32
Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
Table 7
EC Regulator (cont’d)
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
1)
LSGD1,2 Gate Driver peak
sourcing current
ILSGD1,2_SRC 370
–
–
mA
P_6.4.34
VLSGD1,2 = 1 V to 4 V;
V
IVCC_EXT = 5 V;
1)
LSGD1,2 Gate Driver peak
sinking current
ILSGD1,2_SN 550
–
–
mA
P_6.4.35
VLSGD1,2 = 4 V to 1 V;
K
V
IVCC_EXT = 5 V;
1)
LSGD1,2 OFF to HSGD1,2 ON
delay
tLSOFF-
15
35
30
60
40
75
ns
ns
P_6.4.36
P_6.4.37
HSON_delay
1)
HSGD1,2 OFF to LSGD1,2 ON
delay
tHSOFF-
LSON_delay
1) Not subject to production test, specified by design
Datasheet
33
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Digital Dimming Function
7
Digital Dimming Function
PWM dimming is adopted to vary LEDs brightness with greatly reduced chromaticity shift. PWM dimming
achieves brightness reduction by varying the duty cycle of a constant current in the LED string.
7.1
Description
A PWM signal can be transmitted to the TLD5542-1 as described below.
PWM via direct interface
The PWMI pin can be fed with a pulse width modulated (PWM) signals, this enables when HIGH and disables
when LOW the gate drivers of the main switches.
µC
PWM
Digital dimming
PWMI
+3.3V or +5V
VDD
CSN
SI
SPI
SO
SCLK
VSS AGND
Figure 19 Digital Dimming Overview
Note:
In Register REGUSETMON.REGUMODFB the regulation mode can be read. During PWMI = LOW the
SPI will always deliver the Regulation mode which was present at PWMI = HIGH as actual regulation
mode, instead of “no Regulation”.
To avoid unwanted output overshoots due to not soft start assisted startups, PWM dimming in LOW state
should not be used to suspend the output current for long time intervals. To stop in a safe manner
DVCCTRL.IDLE=HIGH or EN/INUVLO=LOW can be used.
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Digital Dimming Function
tACTIVE
VEN/INUVLO
VEN/INUVLOth
t
t
VIVCC_EXT
VIVCC_EXT_RTH,d
+VIVCCX_HYST
tPWMI,H
TPWMI
VPWMI
VPWMI,ON
VPWMI,OFF
t
t
Switching
activity
VCOMP
t
t
VOUT
ILED
t
t
VIOUTMON
200mV
Normal
Dim
Normal
Gate ON
Diag ON
Dim
Normal
Gate ON
Diag ON
Dim
Power ON
Gate ON
Gate OFF
Diag OFF
Gate OFF
Diag OFF
Gate OFF
Diag OFF
Diagnosis ON
Figure 20 Timing Diagram LED Dimming and Start up behavior example ( VVDD and VVIN stable in the
functional range and not during startup)
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Digital Dimming Function
7.2
Electrical Characteristics
Table 8
EC Digital Dimming
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note or Test Condition Number
Min. Typ. Max.
PWMI Input:
PWMI
Turn On Threshold
VPWMI,ON
VPWMI,OFF
IPWMI,H
2
–
–
V
–
P_7.2.1
P_7.2.2
P_7.2.4
P_7.2.5
PWMI
Turn Off Threshold
–
–
0.8
45
18
V
–
PWMI
High Input Current
15
6
30
12
µA
µA
VPWMI = 2.0 V;
VPWMI = 0.8 V;
PWMI
IPWMI,L
Low Input Current
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Analog Dimming and Limp Home
8
Analog Dimming and Limp Home
If the TLD5542-1 is used as current regulator, the analog dimming feature allows control of the LED peak
current level from the default maximum value. If the device is used as voltage regulator, then the analog
dimming can be used to reduce the output voltage. In this chapter the assumption is to have it as a current
regulator.
8.1
Description
For the calculation of the output current IOUT the following Equation (8.1) is used:
VFBH − VFBL
IOUT
=
(8.1)
RFB
The analog dimming feature is adjusting the average LED current level via the control of the feedback error
amplifier reference voltage VFBH-FBL_REF
.
In the default state (DAC_OFF=0 and LHI=LOW), the current adjustment is done via a 8BIT SPI parameter
(LEDCURRADIM.ADIMVAL) as shown on Figure 21 .
If DAC_OFF = 1 then the error amplifier reference voltage is the minimum between SET pin and DAC value.
Therefore, in order to have a full scale dimming via SET pin , ADIMVAL has to be set to 240.
V
FBH-FBL_REF [mV]
150
0
240
8 bit ADIMVAL
Figure 21 Analog Dimming Overview
Analog dimming adjustment during Limp Home state:
To enter in Limp Home state the LHI pin must be HIGH.
Note:
If the PWMI and the EN/INUVLO are not set to HIGH, it is not possible to enable switching, even during
Limp Home state.
In Limp Home state, or if DAC_OFF=1, the analog dimming control is done via the SET pin. A resistor divider
between IVCC/IVCC_EXT, SET and GND can be used to fix a load current/voltage value (refer to below).
When Limp Home is entered, the device will discharge the output capacitor with a F.D. Routine down
to VFBH_S2G_dec (MFSDLY set to the default Value). At the end of the F.D. routine, if the PWMI is kept HIGH, the
device will start regulating with the analog dimming level provided by the SET pin.
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Analog Dimming and Limp Home
CIN
> VIN(PO)
> VIVCC_EXT_RTH,d
IVCC
CIVCC
IVCC_ext
IVCC
VIN
EN/INUVLO
Current
Regulation
RFB
D2
D1
IOUT
default output
current/voltage
adjustment
BST1
BST2
SET
COUT
CBST1 CBST2
M1
M2
M4
HSGD1
SWN1
LOUT
LIMPHOME
FAIL SAFE Circuit
M3
LHI
HIGH
LSGD1
SWCS
Load
PWMI_LH
FAIL SAFE Circuit
SGND
PGND1
PGND2
Set HIGH to
activate output
PWMI
LSGD2
SWN2
HSGD2
VFB
CSN
SI
SO
SPI Writing
disabled during
Limp Home state
FBH
FBL
SCLK
VSS AGND
Figure 22 Limp Home state schematic overview
Using the SET pin to adjust the output current:
During Limp Home state or if DAC_OFF = 1, the average IOUT can be adjusted by controlling the voltage at the
SET pin (VSET) between 0.2 V and 1.4 V. The typical IOUT behaviour is described by Equation (8.2) below:
V SET − 200 mV
I OUT
=
(8.2)
R FB
8
If VSET is 200 mV (typ.) the LED current is only determined by the internal offset voltages of the comparators.
To assure the switching activity is stopped and IOUT = 0, VSET has to be < 100 mV, see Figure 23.
VFBH-FBL
150mV
100mV
0mV
VSET
200mV
1.4V 1.5V
Analog Dimming
Disabled
Analog Dimming Enabled
Figure 23 Analog Dimming Overview
8.2
LED current calibration procedure
The LED current calibration procedure improves the accuracy during analog dimming. In order to be most
effective, this routine has to be performed in the application, when the TLD5542-1 temperature and the output
Datasheet
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Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Analog Dimming and Limp Home
voltage are the ones in which the driver has to be accurate. The output current must be 0 during the procedure
run. The optimum should be to re-calibrate the output periodically every time the application has PWMI=LOW
for a sufficent long time .
Current calibration procedure:
•
•
Power the load with a low analog dimming value (for example 10%)
Set PWMI = LOW and disconnect the Load at the same time (to avoid Vout drifts from operating conditions
and bring the output current to 0)
•
•
•
•
•
•
Quickly (to avoid Vout drifts) µC enables the calibration routine: DVCCTRL.ENCAL= HIGH
Quickly (to avoid Vout drifts) µC starts the calibration: LEDCURRCAL.SOCAL= HIGH
Waiting time (needed to internally perform the calibration routine) → aprox. 200 µs
TLD5542-1 will set the FLAG: LEDCURRCAL.EOCAL= HIGH, when calibration routine has finished
Reconnect the load
The output current is automatically adjusted to a low offset and more accurate analog dimming value
Once the calibration routine is correctly performed, the output current accuracy with analog dimming = 10%
(LEDCURRADIM.ADIMVAL= 24) is 10%.
The Calibration routine is not affecting the accuracy at 100% analog dimming.
The ENCAL Bits affect both device operation and CALIBVAL reading result:
•
ENCAL = HIGH: the calibration result coming from the routine is used by internal circuitry and can be read
back from CALIBVAL
•
ENCAL = LOW: SPI value written in CALIBVAL is used by internal circuitry and can be read back; calibration
routine start is inhibited
As a result, μC can use a stored result from a previously performed calibration to directly impose the desired
value without waiting for a new routine to finish.
OUT H-Bridge
Vint_supply
FBH
+
V_sense_in
RFB
VFBH-FBL
IOUT_sense
FBL
V_sense_out
-
+
Latch
IDC_offset
ADC out
-
to LED
Load
IIN_feedback
ADC CLK
-
EA
ADC Latch
8 bit resolution
4 bit calibration
DAC
COMP
+
2Bit Monitoring
Logic
ADC CLK
Figure 24 LED current accuracy calibration overview
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Analog Dimming and Limp Home
8.3
Electrical Characteristics
Table 9
EC Analog Dimming
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
1)
Source current on SET Pin
ISET_source
–
–
1
µA
V
= 0.2 V to 1.4 V; P_8.3.4
SET
1) Specified by design: not subject to production test.
Datasheet
40
Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Linear Regulator
9
Linear Regulator
The TLD5542-1 features an integrated voltage regulator for the supply of the internal gate driver stages.
Furthermore an external voltage regulator can be connected to the IVCC_EXT pin to achieve an alternative
gate driver supply if required.
9.1
IVCC Description
When the IVCC pin is connected to the IVCC_EXT pin, the internal linear voltage regulator supplies the internal
gate drivers with a typical voltage of 5 V and current up to ILIM (P_9.2.2). An external output capacitor with low
ESR is required on pin IVCC for stability and buffering transient load currents. During normal operation the
external MOSFET switches will draw transient currents from the linear regulator and its output capacitor
(Figure 25, drawing A). Proper sizing of the output capacitor must be considered to supply sufficient peak
current to the gate of the external MOSFET switches. A minimum capacitance value is given in parameter CIVCC
(P_9.2.4).
Alternative IVCC_EXT Supply Concept:
The IVCC_EXT pin can be used for an external voltage supply to alternatively supply the MOSFET Gate drivers.
This concept is beneficial in the high input voltage range to avoid power losses in the IC (Figure 25, drawing B).
Integrated undervoltage protection for the external switching MOSFET:
An integrated undervoltage reset threshold circuit monitors the linear regulator output voltage. This
undervoltage reset threshold circuit will turn OFF the gate drivers in case the IVCC or IVCC_EXT voltage falls
below their undervoltage Reset switch OFF Thresholds VIVCC_RTH,d (P_9.2.9) and VIVCC_EXT_RTH,d (P_9.2.5).
In Limp Home state the Undervoltage Reset switch OFF threshold for the IVCC has no impact on the switching
activity.
The Undervoltage Reset threshold for the IVCC and the IVCC_EXT pins help to protect the external switches
from excessive power dissipation by ensuring the gate drive voltage is sufficient to enhance the gate of the
external logic level N-channel MOSFETs.
A
B
IVCC
Power
IVCC
Internal
VREG
Internal
VREG
VIN
VIN
Power
On Reset
On Reset
EN/
INUVLO
EN/
INUVLO
VIN
VIN
External
VREG
Voltage
Protection
+ Enable
Voltage
Protection
+ Enable
IVCC_EXT
IVCC_EXT
Gate Drivers
Gate Drivers
Figure 25 Voltage Regulator Configurations
Datasheet
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Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Linear Regulator
9.2
Electrical Characteristics
Table 10 EC Line Regulator
IN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
V
Parameter
Symbol
Values
Typ.
Unit
Note or
Test Condition
Number
Min.
Max.
IVCC
Output Voltage
VIVCC
ILIM
4.8
70
–
5
5.2
V
VIN= 13.5 V;
0.1 mA ≤ IIVCC ≤ 50 mA;
1)
P_9.2.1
P_9.2.2
P_9.2.3
Output Current
Limitation
90
200
110
350
mA
mV
VIVCC = 4 V;
VIN = 5 V;
Drop out Voltage (VIN -
VDR
VIVCC
)
IIVCC = 10 mA;
1) 2)
IVCC Buffer Capacitor
CIVCC
10
–
–
µF
V
P_9.2.4
P_9.2.5
3)
IVCC_EXT Undervoltage VIVCC_EXT_R 3.6
3.8
4.0
Reset switch OFF
VIVCC_EXT decreasing;
TH,d
Threshold
3)
IVCC Undervoltage Reset VIVCC_RTH,d 3.6
switch OFF Threshold
3.8
4.0
V
V
P_9.2.9
P_9.2.6
VIVCC decreasing;
VIVCC increasing;
IVCC and IVCC_EXT
VIVCCX_HYST 0.315
0.365
0.395
Undervoltage Hysterisis
VIVCC_EXT increasing;
1) Not subject to production test, specified by design
2) Minimum value given is needed for regulator stability; application might need higher capacitance than the minimum.
Use capacitors with LOW ESR.
3) Selection of external switching MOSFET is crucial. VIVCC_EXT_RTH,d and VIVCC_RTH,d min. as worst case VGS must be
considered.
Datasheet
42
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
10
Protection and Diagnostic Functions
10.1
Description
The TLD5542-1 has integrated circuits to diagnose and protect against overvoltage, short circuits of the load
and overtemperature faults. Furthermore, the device provides a 2 Bit information of ILED, IIN by the SPI to the
µC.
In IDLE state, only the overtemperature Shut Down, overtemperature warning, IVCC or IVCC_EXT
undervoltage monitor, VDD or VEN/INUVLO undervoltage monitor are reported according to specifications.
In a summary of the protection, diagnostic and monitor functions is displayed.
Protection and Diagnostic
SPI
SPI STD
Diagnosis
Overvoltage
SPI
Stop gate drivers
OR
Short at the Load
SPI
SPI
Linear Regulators
OFF
(only IVCC disabled
Device
Overtemperature
OR
in case of
Input
overtemperature)
Undervoltage
Monitoring
COMPARATOR
LEDCUR pin
2BIT data
2BIT data
2BIT data
FBH - FBL
Read-back via
SPI
IIN1- IIN2
Mode Indication
IOUTMON pin
IINMON pin
GAIN , OFFSET
GAIN
Figure 26 Protection, Diagnostic and Monitoring Overview - TLD5542-1
Note:
A device Overtemperature event overrules all other fault events!
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
10.2
Output Overvoltage, Short circuit protection
The VFB pin measures the voltage on the application output and in accordance with the populated resistor
divider overvoltage thresholds is set.
The Short to GND at the output is detected by a fixed threshold on the FBH pin
VIN
CIVCC
VFBH_S2G
IVCC
D2
D1
VOUT
RFB
BST1
BST2
CBST1 CBST2
M1
M2
M4
RVFBH
COUT
HSGD1
SWN1
VVFB_OVTH
LOUT
M3
LSGD1
SWCS
RVFBL
RSWCS
SGND
PGND
LSGD2
SWN2
HSGD2
VFB
FBH
FBL
Figure 27 Over Voltage and Short to grond Protection Pins - Overview
10.2.1
Short Circuit protection
The device detects a short circuit at the output if this condition is verified:
The pin FBH falls below the threshold voltage VFBH_S2G_dec for at least 8 clock cycles
•
It is possible to disable short circuit protection by setting SWTMOD.S2G_OFF to 1, this could be useful for high
output voltage swing applications (like MFS topology) . In case of short to GND, the device will simply regulate
the pre-fixed current to GND, without endangering the application.
During the rising edge of the Soft Start the short circuit detection is ignored until VSOFT_START_LOFF (see Figure 8).
After a short circuit detection, the SPI flag (SHRTLED) in the STD diagnosis register is set to HIGH and the gate
drivers stop delivering output current (Brake-Low condition, both LS MOSFETs ON). The Device will auto
restart with the soft start routine described in Chapter 6.2. The dedicated diagnosis flag (SHRTLED) will be
cleared after the next reading cycle of the STD diagnosis.
To prevent false S2G tripping after startup, a large enough soft-start capacitor must be used to allow the
output voltage to get above the S2G condition.
Note:
If the short circuit condition disappears, the device will re-start with the soft start routine as
described in Chapter 6.2.
Datasheet
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Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
10.2.2
Overvoltage Protection
A voltage divider between VOUT, VFB pin and AGND is used to adjust VOUT overvoltage protection threshold
(VOUT_OV), refer to Figure 27 and Equation (10.1):
ꢑꢀꢁꢄꢥ + ꢑꢀꢁꢄꢢ
ꢀꢏꢗꢐ_ꢏꢀ = ꢀ
∙
(10.1)
ꢀꢁꢄ_ꢏꢀꢐꢥ
ꢑꢀꢁꢄꢢ
If VVFB gets higher than its overvoltage threshold VVFB_OVTH , the SPI flag (OUTOV) in the STD diagnosis set to
HIGH and the gate drivers stop switching for output regulation (Brake-Low condition both LS MOSFETs ON).
When VVFB_OVTH- VVFB_OVTH,HYS threshold is reached the device will auto restart. The dedicated diagnosis flag
(OUTOV) will be cleared after the next reading cycle of the STD diagnosis.
If the overvoltage threshold VOUT_OV is set below the maximum VIN application operating range, then attention
needs to be paid to the overvoltage behavior.
If load current persists during overvoltage event, repetitive overvoltage triggering may occur with a high
frequency. This prevents inductor current regulation and the output current may even increase. To avoid this
condition, proper sizing of the external components is needed (i.e. increase the output capacitance or the
overvoltage threshold in order to delay the overvoltage trigger).
10.3
Input voltage monitoring, protection
Input undervoltage shutdown level can be defined through an external resistor divider, as shown in .
EN/INUVLO pin voltages are internally compared to their respective thresholds by means of hysteretic
comparators.
Neglecting the hysteresis, the following equations hold:
ꢑ1 + ꢑ2
(10.2)
ꢗꢀ =
∙ ꢂꢉ/ꢈꢉꢗꢀꢢꢏꢍℎ
ꢍℎ
ꢑ2
RIN
VIN
IN2
IN1
R1
R2
EN/INUVLO
Figure 28 Input Voltage Protection
10.4
Input current Monitoring
The two inputs (IIN1, IIN2) can be used to monitor the Input current.
The input current, measured via IIN1 and IIN2 pins, can be monitored through an analog output pin and an SPI
routine.
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
The IINMON pin provides a linear indication of the current flowing through the input. The following
Equation (10.3) is applicable:
VIINMON = I IN RIN 20
(10.3)
Purpose of the input current monitoring routine is to verify if the input current level is in the range of the Input
Current Sense threshold VIIN1-IIN2
.
•
•
The output of the Input Current Sense is compared to the internal precise reference voltage
The comparator works like a 2 bit window ADC referred to the internal precise reference voltage
To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready
when CURRMON.EOMON is read HIGH.
The result of the input monitor routine is reported on the CURRMON.INCURR bit.
RIN
VIN
2Bit Monitoring
ADC out
Vint_supply
11b
10b
00b
01b
IN2
IN1
feedback
-
Logic
VIN1-IN2
IIN_sense
1
+
ADC CLK
Latch
2
3
+
-
ADC out
Vref_int
ADC in
ADC CLK
ADC Latch
IINMON
1
2
3
Figure 29 Input Current Monitoring General Overview
10.5
Output current Monitoring
The output current can be monitored through an analog output pin, an open drain flag, an SPI routine and a
STD diagnosis bit.
LEDCUR is an open drain output, signaling LED current detected in MFS topologies.
The corresponding detection threshold is defined by kLEDC_INC and kLEDC_DEC
.
LEDCUR pin voltage raises to HIGH when VFBH-FBL/VFBH-FBL_REF > kLEDC_INC, and is pulled LOW when VFBH-FBL/VFBH-
FBL_REF < kLEDC_DEC. Both kLEDC_INC and kLEDC_DEC are depending on analog dimming value, as shown on .
The same information is also present on the STD diagosis via SPI , in the LEDCUR bit.
For a less immediate, but more detailed information about the output current, the SPI current monitor routine
can be used:
•
•
The output of the Led Current Sense is compared to the output of the Analog Dimming DAC
The comparator works like a 2 bit window ADC around 8 bit DAC output
To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready
when CURRMON.EOMON is read HIGH.
When CURRMON.SOMON bit is set to HIGH both input and output current monitor routines are executed in
parallel.
The result of the monitor routine is reported on the CURRMON.LEDCURR bit.
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
The IOUTMON pin provides a linear indication of the current flowing through the LEDs. The typical IOUTMON
behaviour follows Equation (10.4) :
(10.4)
VIOUTMON = 200 mV + IOUT RFB
8
The typical output impedance of the IOUTMON is 24k Ohm.
ADC out
OUT H-Bridge
2Bit Monitoring
IOUTMON
Vint_supply
11b
10b
00b 01b
FBH
feedback
Logic
+
V_sense_in
FBL
VFBH-FBL
RFB
IOUT_sense
-
ADC CLK
V_sense_out
+
Latch
IDC_offset
ADC in
ADC out
-
to LED
Load
-
LEDCUR
ADC CLK
+
-
ADC Latch
EA
+
8 bit dim
4 bit cal
DAC
COMP
Vref_int
Figure 30 Output Current Monitoring General Overview
Datasheet
47
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
10.6
Device Temperature Monitoring
A temperature sensor is integrated on the chip. The temperature monitoring circuit compares the measured
temperature to the warning and shutdown thresholds. If the internal temperature sensor reaches the warning
temperature, the temperature warning bit TWis set to HIGH. This bit is not latched (i.e. if the temperature falls
below the warning threshold (with hysteresis), the TWbit is reset to LOW again).
If the internal temperature sensor reaches the shut-down temperature, the Gate Drivers plus the IVCC
regulator are shut down as described in Figure 31 and the temperature shut-down bit: TSDis set to HIGH. The
TSDbit is latched while the Gate Drivers plus the IVCC regulator have an auto restart behavior.
Note:
The Device will start up with a soft start routine after a TSD condition disappear.
Tj
TjSD,hyst
TjSD
TjW
TjSD_exit
TjW_exit
TjW,Hyst
t
xSGDx
Gate Drivers
autorestart
Operating
OFF
t
IVCC
5V
IVCC
autorestart
OFF
t
TW bit
1
NO ERROR
NO ERROR
TW bit is reset automatically
0
t
t
TSD error bit
1
0
TSD error bit latched until next reset or CLRLAT
Figure 31 Device Overtemperature Protection Behavior
Datasheet
48
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
10.7
Electrical Characteristics
Table 11 EC Protection and Diagnosis
IN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
V
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition Number
Min.
Max.
Short Circuit Protection
1)
Short to GND exit
threshold
VFBH_S2G_i 1.95
2.05
1.75
70
2.15
1.85
80
V
V
V
increasing;
decreasing;
P_6.9.1
FBH
FBH
nc
1)
Short to GND entry
threshold
VFBH_S2G_d 1.65
V
P_6.9.2
ec
LEDCUR detect
threshold increasing
kLEDC_INC 60
%
%
%
%
%
1)ADIMVAL = 240
FBH-FBL increasing;
1)ADIMVAL = 48
FBH-FBL increasing;
1)ADIMVAL = 240
FBH-FBL decreasing;
1)ADIMVAL = 48
FBH-FBL decreasing;
P_10.7.1
P_10.7.2
P_10.7.3
P_10.7.4
P_10.7.5
V
LEDCUR detect
threshold increasing
kLEDC_INC 45
kLEDC_DEC 50
kLEDC_DEC 30
55
65
V
LEDCUR detect
threshold decreasing
60
70
V
LEDCUR detect
threshold decreasing
40
50
V
LEDCUR detect
hysteresys
kLEDCUR_HY
-
12
-
1)ADIMVAL = 48 to 240
S
Temperature Protection:
1)
1)
1)
1)
Thermal Warning
Tj,W
125
–
140
10
155
–
°C
°C
°C
°C
P_10.8.2
P_10.8.3
P_10.8.4
P_10.8.5
junction temperature
Temperature warning Tj,W,hyst
Hysteresis
Over Temperature
Shutdown
Tj,SD
160
–
175
10
190
–
Over Temperature
Tj,SD,hyst
Shutdown Hysteresis
Overvoltage Protection:
VFB Over Voltage
Feedback Threshold
VVFB_OVTH 1.42
1.46
40
1.50
58
V
P_10.8.6
P_10.8.7
Output Over Voltage
Feedback Hysteresis
VVFB_OVTH, 25
mV
Output Voltage
decreasing;
HYS
Flags
LEDCUR, EOMFS Pin
Output Impedance
RF12
–
2.1
–
kΩ
1)When Pull Down is
active I=100uA
P_10.8.14
1) Specified by design; not subject to production test.
Note:
Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the datasheet. Fault conditions are considered as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation.
Datasheet
49
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Infineon FLAT SPECTRUM Feature set
11
Infineon FLAT SPECTRUM Feature set
11.1
Description
The Infineon FLAT SPECTRUM feature set has the target to minimize external additional filter circuits. The goal
is to provide several beneficial concepts to provide easy adjustments for EMC improvements after the layout
is already done and the HW designed.
11.2
Synchronization Function
The TLD5542-1 features a SYNC input pin which can be used by a µC pin to define an oscillator switching
frequency. The µC is responsible to synchronize with various devices by applying appropriate SYNC signals to
the dedicated DC/DC devices in the system. Refer to Figure 32
Note:
The Synchronization function can not be used when the Spread Spectrum is active.
H-Bridge DCDC
MASTER
BUCK-
BOOST
SYNC
GATE
LOGIC
CONTROL
e.g. 400kHz
Phaseshift A
H-Bridge DCDC
Slave
BUCK-
BOOST
GATE
SYNC1
SYNC2
defined phase shift between
Outputs of different devices
SYNC
µC
LOGIC
INPUT
e.g. 400kHz
Phaseshift B
CONTROL
Figure 32 Synchronization Overview
Datasheet
50
Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Infineon FLAT SPECTRUM Feature set
11.3
Spread Spectrum
The Spread Spectrum modulation technique significantly improves the lower frequency range of the
spectrum (f < 30 MHz).
By using the spread spectrum technique, it is possible to optimize the input filter only for the peak limits, and
also pass the average limits (average emission limits are -20dB lower than the peak emission limits). By using
spread spectrum, the need for low ESR input capacitors is relaxed because the input capacitor series resistor
is important for the low frequency filter characteristic. This can be an economic benefit if there is a strong
requirement for average limits.
The TLD5542-1 features a built in Spread Spectrum function which can be enabled (SWTMOD.ENSPREAD)
and adjusted via the SPI interface. Dedicated SPI-Bits are used to adjust the modulation frequency fFM
,
(P_11.6.3) and (P_11.6.4) (SWTMOD.FMSPREAD) and the deviation frequency fdev, (P_11.6.1) and (P_11.6.2)
(SWTMOD.FDEVSPREAD) accordingly to specific application needs. Refer to Figure 33 for more details.
The following adjustments can be programmed when SWTMOD.ENSPREAD= HIGH:
SWTMOD.FMSPREAD= LOW: 12 kHz
SWTMOD.FMSPREAD= HIGH: 18 kHz
SWTMOD.FDEVSPREAD= HIGH: ±8% of fSW
SWTMOD.FDEVSPREAD= LOW: ±16% of fSW
Note:
The Spread Spectrum function can not be used when the synchronization pin is used.
fSW
fdev
t
1
f
FM
Figure 33 Spread Spectrum Overview
Datasheet
51
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Infineon FLAT SPECTRUM Feature set
11.4
EMC optimized schematic
Figure 34 below displays the Application circuit with additional external components for improved EMC
behavior.
LPI
CIN2
VIN
RIIN
CPI1 CPI2
CPI3 CPI4
CIVCC
VIN
IIN2
IVCC_EXT
IVCC
CIN1
D1
D2
LPO
RFB
Rfilter
Cfilter
RM4
BST1
BST2
COUT
DHSG1
RM1
CBST2
R1
R2
M4
IIN1
EN/INUVLO
M1
RVFBH
CBST1
HSGD1
SWN1
CM1
RM2
CM4
RM3
CM3
RHSG1
CPO1 CPO2
CPO3 CPO4
LOUT
RHSG2
M3
RVFBL
DLSG1
M2
CCOMP
RCOMP
LSGD1
SWCS
CM2
COMP
RLSG1
CSOFT_START
RFREQ
DLSG2
RLSG2
DHSG2
SOFT_START
FREQ
RSWCS
4LED in
series /
1A
SGND
PGND1
PGND2
LSGD2
SWN2
HSGD2
VFB
Digital dimminig
PWMI
IINMON
IOUTMON
Advanced monitoring via µC
+3.3V or +5V
VDD
CSN
SI
SO
SCLK
FBH
FBL
CFBH-FBL
CFBH
Spread Spectrum ON/OFF via SPI
VSS AGND
CFBL
RSPI
Figure 34 Application Drawing Including Additional Components for an Improved EMC Behavior
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
Datasheet
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Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Infineon FLAT SPECTRUM Feature set
11.5
Electrical Characteristics
Table 12 EC Spread Spectrum
IN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
V
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Spread Spectrum Parameters
1)
Frequency Deviation
fdev
fdev
fFM
fFM
–
±8
–
%
P_11.6.1
P_11.6.2
P_11.6.3
P_11.6.4
SWTMOD.FDEV
SPREAD= HIGH;
1)
Frequency Deviation
Frequency Modulation
Frequency Modulation
–
–
–
±16
12
–
–
–
%
SWTMOD.FDEV
SPREAD= LOW;
1)
kHz
kHz
SWTMOD.FMSP
READ= LOW;
1)
18
SWTMOD.FMSP
READ= HIGH;
1) Specified by design; not subject to production test.
Datasheet
53
Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines:
SO, SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of
CSN indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted
out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo
8/16 counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits.
Otherwise, a TER (i.e. Transmission Error) bit is asserted. In this way the interface provides daisy chain
capability with 16 bit as well as with 8 bit SPI devices.
MSB
MSB
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
SO
SI
CSN
SCLK
time
SPI_16bit.emf
Figure 35 Serial Peripheral Interface
12.1
SPI Signal Description
CSN - Chip Select
The system microcontroller selects the TLD5542-1 by means of the CSN pin. Whenever the pin is in LOW state,
data transfer can take place. When CSN is in HIGH state, any signals at the SCLK and SI pins are ignored and
SO is forced into a high impedance state.
CSN HIGH to LOW Transition
•
•
•
The requested information is transferred into the shift register.
SO changes from high impedance state to HIGH or LOW state depending on the signal level at pin SI.
If the device is in SLEEP mode, the SO pin remains in high impedance state and no SPI transmission will
occur.
•
TERFlag will set the Bit number 10 in the STD diagnosis Frame. This Bit is set to HIGH after an undervoltage
contition, reset via SPI command, on Limp Home state entering or after an incorrect SPI transmission. TER
Flag can be read also direcly on the SO line between the falling edge of the CSN and the first rising edge of
the SCLK according to the Figure 36.
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
STDDIAG.TER
SI
SO
OR
1
0
SO
S
SI
SPI
CSN
SCLK
S
SPI_16bitTER .emf
Figure 36 Combinatorial Logic for TER bit
CSN LOW to HIGH Transition
•
Command decoding is only done, when after the falling edge of CSN exactly a multiple (0,1, 2, 3, …) of eight
SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the
transmission error bit (TER) is set and the command is ignored.
•
Data from shift register is transferred into the addressed register.
SCLK - Serial Clock
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the
falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the
serial clock. It is essential that the SCLK pin is in LOW state whenever chip select CSN makes any transition,
otherwise the command may be not accepted.
SI - Serial Input
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling
edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to
Chapter 12.5 for further information.
SO Serial Output
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN
pin goes to LOW state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Chapter 12.5 for further information.
12.2
Daisy Chain Capability
The SPI of the TLD5542-1 provides daisy chain capability. In this configuration several devices are activated by
the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see
Figure 37), in order to build a chain. The end of the chain is connected to the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
device 1
device 2
SPI
device 3
SPI
SI
SO SI
SO SI
SO
MO
SPI
MI
MCSN
MCLK
SPI_DaisyChain_1.emf
Figure 37 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where each bit from the SI line is shifted in with each
SCLK. The bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is
finished. In single chip configuration, the CSN line must turn HIGH to make the device acknowledge the
transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2.
When using three devices in daisy chain, several multiples of 8 bits have to be shifted through the devices
(depending on how many devices with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must
turn HIGH (see Figure 38).
SO device 3
SI device 3
SO device 2
SI device 2
SO device 1
SI device 1
MI
MO
MCSN
MCLK
SPI_DaisyChain_2.emf
Figure 38 Data Transfer in Daisy Chain Configuration
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.3
Timing Diagrams
tCS(lead)
tCS(lag)
tCS(td)
tSCLK(P )
0.7VDD
0.2VDD
CSN
tSCLK (H)
tSCLK (L)
0.7VDD
0.2VDD
SCLK
SI
tSI (s u)
tSI (h)
0.7VDD
0.2VDD
tSO(en)
tSO(v )
tSO (dis)
0.7V
cc
SO
0.2V
cc
SPI_Timings.emf
Figure 39 Timing Diagram SPI Access
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.4
Electrical Characteristics
VIN = 8 V to 36 V, TJ = -40°C to +150°C, VDD= 3 V to 5.5 V, all voltages with respect to ground; (unless otherwise
specified)
Table 13 EC Serial Peripheral Interface (SPI)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Input Characteristics (CSN, SCLK, SI) - LOW level of pin
CSN
SCLK
SI
VCSN(L)
VSCLK(L)
VSI(L)
0
0
0
–
–
–
0.8
0.8
0.8
V
V
V
–
P_12.4.1
P_12.4.2
P_12.4.3
–
–
Input Characteristics (CSN, SCLK, SI) - HIGH level of pin
CSN
SCLK
SI
VCSN(H)
VSCLK(H)
VSI(H)
2
–
VDD
VDD
VDD
94
V
–
–
–
P_12.4.4
P_12.4.5
P_12.4.6
P_12.4.7
2
–
V
2
–
V
L-input pull-up current at CSN pin -ICSN(L)
H-input pull-up current at CSN pin -ICSN(H)
L-Input Pull-Down Current at Pin
31
63
μA
VDD = 5 V;
VCSN = 0.8 V;
22
45
67
μA
VDD = 5 V;
VCSN = 2 V;
P_12.4.8
SCLK
ISCLK(L)
ISI(L)
6
6
12
12
18
18
μA
μA
VSCLK = 0.8 V;
VSI = 0.8 V;
P_12.4.9
SI
P_12.4.10
H-Input Pull-Down Current at Pin
SCLK
ISCLK(H)
ISI(H)
15
15
30
30
45
45
μA
μA
VSCLK = 2 V;
VSI = 2 V;
P_12.4.11
P_12.4.12
SI
Output Characteristics (SO)
L level output voltage
H level output voltage
VSO(L)
VSO(H)
0
–
–
0.4
V
V
ISO = -2 mA;
ISO = 2 mA;
P_12.4.13
P_12.4.14
VDD
-
VDD
0.4 V
V
DD = 5 V;
VCSN = VDD
SO = 0 V or
Output tristate leakage current
ISO(OFF)
-1
–
1
μA
;
P_12.4.15
V
VSO = VDD
;
Timings
1)
1)
1)
1)
Enable lead time (falling CSN to tCSN(lead) 200
rising SCLK)
–
–
–
–
–
ns
ns
ns
ns
P_12.4.17
P_12.4.18
P_12.4.19
P_12.4.20
Enable lag time (falling SCLK to
rising CSN)
tCSN(lag)
200
250
–
–
Transfer delay time (rising CSN to tCSN(td)
falling CSN)
–
Output enable time (falling CSN to tSO(en)
200
SO valid)
CL = 20 pF at SO
pin;
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Table 13 EC Serial Peripheral Interface (SPI) (cont’d)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
1)
Output disable time (rising CSN to tSO(dis)
–
200
ns
P_12.4.21
SO tristate)
CL = 20 pF at SO
pin;
1)
Serial clock frequency
Serial clock period
fSCLK
–
–
–
–
–
–
5
–
–
–
–
MHz
ns
P_12.4.22
P_12.4.24
P_12.4.25
P_12.4.26
P_12.4.27
1)
1)
1)
1)
tSCLK(P)
tSCLK(H)
tSCLK(L)
200
75
75
20
Serial clock HIGH time
Serial clock LOW time
ns
ns
Data setup time (required time SI tSI(su)
ns
to falling SCLK)
1)
Data hold time (falling SCLK to SI) tSI(h)
20
–
–
–
–
ns
ns
P_12.4.28
P_12.4.29
1)
Output data valid time with
capacitive load
tSO(v)
100
CL = 20 pF;
1) Not subject to production test, specified by design
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.5
SPI Protocol
The relationship between SI and SO content during SPI communication is shown in Figure 40. The SI line
represents the frame sent from the µC and the SO line is the answer provided by the TLD5542-1. The first SO
response is the response from the previous command.
SI
frame A
frame B
frame C
(previous
response)
response to
frame A
response to
frame B
SO
SPI_SI2SO.emf
Figure 40 Relationship between SI and SO during SPI communication
The SPI protocol will provide the answer to a command frame only with the next transmission triggered by the
µC. Although the biggest majority of commands and frames implemented in TLD5542-1 can be decoded
without the knowledge of what happened before, it is advisable to consider what the µC sent in the previous
transmission to decode TLD5542-1 response frame completely.
More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows:
SI
write register A
read register A
(new command)
(previous
response)
Standard
diagnostic
register A
content
SO
SPI_RWseq.emf
Figure 41 Register content sent back to µC
There are 3 special situations where the frame sent back to the µC doesn't depend on the previously received
frame:
•
•
•
in case an error in transmission happened during the previous frame (for instance, the clock pulses were
not multiple of 8 with a minimum of 16 bits), shown in Figure 42
when TLD5542-1 logic supply comes out of an Undervoltage reset condition (VDD < VDD(UV) as shown in
Figure 43 or EN/INUVLO < VEN/INUVLOth
)
in case of a read or write command for a “not used” or “reserved” register (in this case TLD5542-1 answers
with Standard Diagnosis at the next SPI transmission)
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
frame A
SI
(new
command)
(error in trans .)
(previous
response)
Standard diag +
TER
SO
SPI_SO_TER.emf
Figure 42 TLD5542-1 response after an error in transmission
V
DD ≥ VDD(UV)
SI
frame A
frame B
frame C
Standard diag + TER
SO
(SO = „Z“)
response to frame B
Figure 43 TLD5542-1 response after coming out of Power-On reset at VDD
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.6
SPI Registers Overview
15 14
Frame W/R RB ADDR
Write Register in bank 0
ADDR
Read Register in bank 0
ADDR
Read Standard Diagnosis
13
12 11 10
9
8
7
6
5
4
3
2
1
0
Data
SI
SI
SI
1
0
Data
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
0
x
x
x
x
x
x
x
x
Reading a register needs two SPI frames. In the first frame the read command is sent. In the second frame the
output at SPI signal SO will contain the requested information. The MSB will be HIGH (while in case of standard
diagnosis is LOW). A new command can be executed in the second frame.
12.6.1
Standard Diagnosis
The Standard Diagnosis reports several diagnostic informations and the status of the device and the utility
routines.
The bits UVLORST, TER, OUTOV, IVCCUVLO and SHRTLED are latched and automatically cleared after a STD
diagnosis reading.
A CLRLAT command resets the diagnostic Latched Flag TSD bit.
The TSD bit is always latched and clearable only via explicit CLRLAT command.
The STD bits which are real time status monitors or mirror of internal registers are not cleared after a STD
diagnosis reading or via explicit CLRLAT command:
•
•
•
The STATE bits and TW are real time status flags
The bits EOMON, EOMFS and EOCAL are mirror of internal register
The SWRST_BSTUV bit is the logic OR of:
•
•
latched SWRST flag after a DVCSTRL.SWRST command (clearable via STD Diagnosis reading )
real time monitor of gate driver undervolage (VBSTx-VSWNx_UVth)
15
14
13
12 11 10
9
8
7
6
5
4
3
2
1
0
0
SWRST_ UVLO STATE TER EO
BSTUV RST
EOM EOC
AL
0
OUTOV IVCCU LED SHRT TSD TW
VLO CUR LED
MON FS
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
SWRST_BSTUV
14
r
SWRST OR VBSTx-VSWNx_UVth Monitor
0B , no SWRST or undervoltage on the Gate Drivers occured
1B , there was at least one SWRST since last readout OR an
undervoltage condition at the gate drivers is occurring
UVLORST
STATE
13
r
r
VDD OR VEN/INUVLO Undervoltage Monitor
0B , there was no VDD OR VEN/INUVLO undervoltage since last readout
1B , there was at least one VDD undervoltage OR VEN/INUVLO
undervoltage condition since last readout
12:11
Operative State Monitor
00B , (reserved)
01B , Limp Home Mode
10B , Active Mode
11B , Idle Mode
TER
10
9
r
r
Transmission Error
0B , Previous transmission was successful
(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)
1B , Previous transmission failed or first transmission after reset
EOMON
End of LED/Input Current Monitor Routine Bit
0B , Current monitoring routine not completed, not successfully
performed or never run.
1B , Current Monitor routine successfully performed (is reset to 0B
when SOMON is set to 1B)
EOMFS
EOCAL
8
7
r
r
End of MFS Routine Bit
0B , MFS routine not completed, not successfully performed or
never run.
1B , MFS routine successfully performed (is reset to 0B when
SOMOFS is set to 1B)
End of Calibration Routine
0B , Calibration routine not completed, not successfully
performed or never run.
1B , Calibration routine successfully performed (is reset to 0B
when SOCAL is set to 1B)
OUTOV
5
4
r
r
Output overvoltage Monitor
0B , Output overvoltage not detected since last readout
1B , Output overvoltage was detected since last readout
IVCCUVLO
IVCC or IVCC_EXT Undervoltage Lockout Monitor
0B , IVCC and IVCC_EXT above VIVCC_RTH,d or VIVCC_EXT_RTH,d threshold
since last readout
1B , Undervoltage on IVCC or IVCC_EXT occurred since last
readout
LEDCUR
3
r
LED Current Flag (see LEDCUR pin description Chapter 10.5)
0B , LED current not detected
1B , LED current detected
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
SHRTLED
2
r
Shorted LED Diagnosis
0B , Short circuit condition not detected since last readout
1B , Short circuit condition detected since last readout
TSD
TW
1
0
r
r
Over Temperature Shutdown
0B , Tj below temperature shutdown threshold
1B , Overtemperature condition detected since last readout
Over Temperature Warning
0B , Tj below temperature warning threshold
1B , Tj exceeds temperature warning threshold
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.6.2
Register structure
Table 15 describes in detail the available registers with their bit-fields function, size and position
Table 14 shows register addresses and summarize bit-field position inside each register
Table 14 Register Bank 0
Bit
15 14 13 12 11
1
0
9 8
7
6
5
4
3
2
1
0
Name
W/ R ADDR
Data
R
B
LEDCURR W/ 0
ADIM
LEDCURR W/ 0
CAL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0 0 ADIMVAL
1 1 x
R
0
1
1
0
DAC_ SOCAL EOCAL CALIBVAL
OFF
R
SWTMOD W/ 0
R
0 1 x
DCM_ CCM4E VFB_VI S2G_O ENSP FMSP FDEVSP
EN VER N_OFF FF READ READ READ
1 0 EA_IO EA_G SLOPE ENCAL CLRLA SWRS IDLE
UT
DVCCTRL W/ 0
R
M
T
T
MFSSETU W/ 0
0 1 EA_IO ILIM_ SOMFS EOMFS LEDCHAIN
UT_MF HALF
P1
R
S
_MFS
MFSSETU W/ 0
P2
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
1
1 0 MFSDLY
R
CURRMON W/ 0
R
0 0 x
1 1 x
x
x
SOMO EOMON INCURR
N
LEDCURR
REGUSET W/ 0
x
REGUMODFB BB_BST_CMP
MON
R
MUXCTRL W/ 1
R
1 0 MFS_R AMUX SO_MUX_SEL
EF _EN
A write to a non existing address is ignored, a read to a non existing register is ignored and the STD Diagnosis
Frame is send out.
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Table 15 Register description
Register name Field
Bits Type Purpose
LEDCURRADIM ADIMVAL
7:0 r/w LED Current Configuration Register
00000000B, analog dimming @ 0% of LED current fixed via
RFB
11110000B, (default) analog dimming @ 100% of LED
current fixed via RFB
LEDCURRCAL
CALIBVAL
3:0 r/w LED Current Accuracy Trimming Configuration
Register
LED current calibration value definition, the first bit is the
calibration sign:
0000B, (default) Initial state in the middle of the range
0111B, maximum calibration value positive
1111B, maximum calibration value negative
EOCAL
4
r
End of calibration routine signalling bit:
0B , (default) calibration routine not completed, not
successfully performed or never run.
1B , calibration successfully performed (is reset to 0B
when SOCALis set to 1B)
SOCAL
5
6
r/w Start of calibration routine signalling bit:
0B , (default) no calibration routine started
1B , calibration routine start (autoclear)
DAC_OFF
r/w Switch OFF internal analog dimming DAC bit:
0B , (default) internal DAC active
1B , internal DAC inactive and analog dimming error
amplifier mapped to SET pin
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Table 15 Register description (cont’d)
Register name Field
Bits Type Purpose
SWTMOD
FDEVSPREAD
0
r/w Switching Mode Configuration Register
Deviation Frequency fDEV definition:
0B , (default) ±16% of fSW
1B , ±8% of fSW
FMSPREAD
ENSPREAD
S2G_OFF
1
2
3
4
5
6
r/w Frequency Modulation Frequency fFM definition:
0B , (default) 12 kHz
1B , 18 kHz
r/w Enable Spread Spectrum feature:
0B , (default) Spread Spectrum modulation disabled
1B , Spread Spectrum modulation enabled
r/w Short to GND protection enable Bit
0B , (default) Short to ground protection enabled
1B , Short to ground protection disabled
VFB_VIN_OFF
CCM_4EVER
DCM_EN
r/w Vin Feedback Enable on VFB_VIN pin
0B , (default) Enable Vin Feedback
1B , Disable Vin Feedback
r/w Forced Continuous Conduction Mode
0B , (default) Forced CCM after soft start finish
1B , Forced CCM even during soft start ramp up
r/w Enable Bit to allow DCM regulation (MOSFET M4 control)
0B , (default) DCM is disabled (M4 alternately
switching),
1B , DCM is enabled (M4 is permanently OFF)
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Table 15 Register description (cont’d)
Register name Field
Bits Type Purpose
DVCCTRL
IDLE
0
r/w Device Control Register
IDLE mode configuration bit:
0B , ACTIVE mode (default)
1B , IDLE mode
SWRST
CLRLAT
ENCAL
1
2
3
r/w Software reset bit:
0B , (default) normal operation
1B , execute reset command
r/w Clear Latch bit:
0B , (default) normal operation
1B , execute CLRLAT command
r/w Enable automatic output current calibration bit:
0B , (default) DAC takes CALIBVAL from SPI registers
1B , DAC takes CALIBVAL from last completed automatic
calibration procedure; SOCAL Bit can be set.
SLOPE
5:4 r/w slope compensation strenght:
00B , (default) Nominal
01B , +25%
10B , -50%
11B , -25%
EA_GM
6
7
r/w Increase the gain of the error amplifier, active only when
output current is below 80% of target (i.e. < VFBH_FBL_EA
):
0B , (default) inactive
1B , IFBxgm boosted to 1420µS
EA_IOUT
r/w Bit to decrease the saturation current of the error
amplifier in current mode control loop:
0B , (default) inactive
1B , active: error amplifier saturation current reduced to
10uA
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Table 15 Register description (cont’d)
Register name Field
Bits Type Purpose
MFSSETUP1
LEDCHAIN
3:0 r/w Multifloat Switch configuration Register
MFS ratio bits: set MFS jump ratio
0001B, smallest Value 1 Step
0010B, 2 Steps
1000B, (default) 8 Steps
1111B, 15 Steps
0000B, largest Value 16 Steps
EOMFS
4
r
End of MFS routine bit:
0B , (default) MFS routine not completed, not
successfully performed or never run.
1B , MFS routine successfully performed (is reset to 0B
when SOMFSis set to 1B).
SOMFS
5
6
r/w Start of MFS routine bit:
0B , (default) MFS routine not activated
1B , MFS routine activated
ILIM_HALF
r/w Bit to decrease the Switch Current Limit (ISwLim) during F.D.
operation:
0B , (default)inactive ISwLim = 2/3of default value
1B , ISwLim reduced to 1/2of default value
EA_IOUT_MFS
MFSDLY
7
r/w Bit to decrease the saturation current of the error
amplifier (A6) in current mode control loop only during
MFS routine:
0B , (default) inactive
1B , active: error amplifier current reduced to 20%
MFSSETUP2
7:0 r/w Multifloatswitch configuration register 2 (delay time
programming)
00000000B, smallest delay time in respect to fSW
11111111B, largest delay time in respect to fSW
10000000B, (default) delay time in respect to fSW
Datasheet
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Table 15 Register description (cont’d)
Register name Field
Bits Type Purpose
CURRMON
LEDCURR
1:0
3:2
4
r
r
r
Current Monitor Register
Status of the LED Current bits:
00B , (default) LED current between Target and +25%
01B , LED current above +25% of Target
10B , LED current between Target and -25%
11B , LED current below -25% of Target
INCURR
EOMON
Status of the Input Current bits:
00B , (default) Input current between 75% and 90% of
Limit
01B , Input current between 90% and the Limit
10B , Input current between 60% and 75% of Limit
11B , Input current below 60% of Limit
End of LED/Input Current Monitoring bit:
0B , (default) Current monitoring routine not
completed, not successfully performed or never run.
1B , Current Monitor routine successfully performed (is
reset to 0B when SOMONis set to 1B)
SOMON
5
r/w Start of LED/Input Current Monitoring bit:
0B , (default) Current monitor routine not started
1B , Start of the current monitor routine
REGUSETMON
REGUMODFB
3:2
r
Regulation Setup And Monitor Register
Feedback of Regulation Mode bits:
01B , (default) Buck
10B , Boost
11B , Buck-Boost
BB_BST_CMP
SO_MUX_SEL
1:0 r/w Buck boost to Boost transition compensation level:
00B , (default) Min compensation: useful when low
switching frequencies are selected
01B , Low compensation: I.E. adopted @fSW=250kHz
10B , Mid compensation: I.E. adopted @fSW=400kHz
11B , Max compensation: useful when high switching
frequencies are selected I.E. @fSW=500kHz
MUXCTRL
5:0 r/w Internal Muxes Configuration Register
Digital Multiplexer selector, output on SO pin:
000000B, (default) SO pin configured as normal SPI output
000100B, as default with in addition internal oscillator
clock available when CS_N is high
AMUX_EN
MFS_REF
6
r/w Analog Mux enable, output on FILT pin:
0B , (default) Analog Mux disabled
1B , Analog Mux enabled
7
r/w MFS reference to FILT pin Path Enable:
0B , (default) path disabled
1B , Path Enabled
Datasheet
70
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
13
Application Information
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
VIN
CIN2
CIN1
CIVCC
VIN
IIN2
IVCC_ext
IVCC
VIN
D2
D1
IIN1
VOUT
VDD
BST1
BST2
RFB
VFB_VIN
COUT1
CBST1 CBST2
VDD
M1
M2
M4
ADC
HSGD1
SWN1
EN/INUVLO
DIM_HALF
M6
M7
LOUT
I/O
CCOMP
M3
ADC
LSGD1
SWCS
RCOMP
CSOFT_START
COMP
VDD
SOFT_START
Micro
controller
RFREQ
FREQ
PWMI
Low
Beam
SGND
PGND1
PGND2
LSGD2
SWN2
HSGD2
VFB
I/O
I/O
I/O
EOMFS
LEDCUR
VDD
VDD
DRL
RSPI1
CSN
SI
SO
FBH
RSPI2
RSPI3
SPI
FBL
RSPI4
SCLK
High
Beam
IOUTMON
AGND
FILT
CFILT2
VOUT
CFILT1
M5
ADC
I/Os
GND
Figure 44 Application Drawing - TLD5542-1 on a 3 functions LED Driver Module
Table 16 BOM - TLD5542-1 as current regulator (IOUT = 1 A, fSW = 300 kHz)
Reference Designator Value
Manufacturer
--
Part Number
BAT46WJ
X7R
Type
D1 , D2
CIN1
BAT46WJ
Diode
10 µF, 50 V
4.7 µF, 50 V
220 pF, 10 V
15 nF, 16 V
15 nF, 16 V
3x3.3 µF, 100 V
10 µF, 16 V
100 nF, 16 V
--
TDK
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
IC
CIN2
TDK
X7R
CFILT1,2
CCOMP
CSOFT_START
COUT1
CIVCC
TDK
X7R
TDK
X7R
TDK
X7R
TDK
X7R
TDK
X7R
CBST1 , CBST2
IC1
TDK
X7R
Infineon
TDK
TLD5542-1
LOUT
10 µH
SPM10065VT-100M Inductor
RFB
0.100 Ω, 1%
Panasonic
Panasonic
--
--
Resistor
Resistor
R1 , R2 , R3 , RPD , REN , RPWMI xx kΩ, 1%
, RSense1 , RSense2 , RSYNC
RSCLK , RSI , RSO , RCSN
,
R
VFBL , RVFBH
1k5Ω, 51kΩ, 1%
1kΩ, 51kΩ, 1%
Panasonic
Panasonic
--
--
Resistor
Resistor
RVFBL2 , RVFBH2
Datasheet
71
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
Table 16 BOM - TLD5542-1 as current regulator (IOUT = 1 A, fSW = 300 kHz)
Reference Designator Value
Manufacturer
Panasonic
Panasonic
Panasonic
Infineon
Part Number
Type
RCOMP
RFREQ
RSWCS
1k Ω, 1%
--
Resistor
Resistor
Resistor
Transistor
24 kΩ, 1%
--
0.007 Ω, 1%
ERJB1CFR05U
IPG20N10S4L-26
M1 , M2 , M3 , M4, M5, M6, M7 Dual MOSFET:
60V / 26 mΩ N-ch
VBAT
DTVS
MRP
Rgate
Voltage Regulator
CVREG_OUT
CIN2
RIIN
OUT
VS
Alternative external
VREG supply
GND
CIN1
CIVCC
IVCC_ext
VIN
IIN2
IVCC
VFB_VIN
D2
D1
COUT2
IIN1
SET
COUT3
BST1
BST2
COUT1
CBST1 CBST2
VDD
M1
M2
M4
VOUT
HSGD1
SWN1
EN/INUVLO
LOUT
I/O
I/O
CCOMP
M3
LSGD1
SWCS
RCOMP
CSOFT_START
COMP
SOFT_START
Micro
controller
RFREQ
FREQ
PWMI
SGND
PGND1
PGND2
RPWMI
RSENSE
CFF
A/D
IINMON
IOUTMON
LSGD2
I/O
SWN2
HSGD2
VFB
VDD
VDD
RCSN
CSN
SI
SO
FBH
RSI
SPI
RSO
FBL
RSCLK
SCLK
GND
Figure 45 Application Drawing - TLD5542-1 as adjustable voltage regulator
Table 17 BOM - TLD5542-1 as voltage regulator
Reference Designator Value
Manufacturer
--
Part Number
BAT46WJ
X7R
Type
D1 , D2
CIN1
BAT46WJ
Diode
1 µF, 100 V
4.7 µF, 100 V
22 nF, 16 V
10 nF, 50 V
22 nF, 16 V
3x4.7 µF, 100 V
100 nF, 100 V
10 µF, 16 V
100 nF, 16 V
--
TDK
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
IC
CIN2
TDK
X7R
CCOMP
CFF
TDK
X7R
TDK
X7R
CSOFT_START
COUT1
COUT2 , COUT3
CIVCC
BST1 , CBST2
TDK
X7R
TDK
X7R
TDK
X7R
TDK
X7R
C
TDK
X7R
IC1
Infineon
TLD5542-1
Datasheet
72
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
Table 17 BOM - TLD5542-1 as voltage regulator
Reference Designator Value
Manufacturer
Part Number
Type
LOUT
RFF
10 µH
Coilcraft
XAL1010-103MEC
Inductor
Resistor
Resistor
Resistor
Resistor
1.5 kΩ, 1%
150Ω, 20.5kΩ, 1%
0.005 Ω, 1%
xx kΩ, 1%
Panasonic
Panasonic
Panasonic
Panasonic
--
--
--
--
RFB1 , RFB2
RIN
R
PWMI , RSense1 , RSense2
,
RSYNC , RSCLK , RSI , RSO
,
RCSN
RVFBL , RVFBH
RCOMP
1.5 kΩ, 24 kΩ, 1%
0 Ω, 1%
Panasonic
Panasonic
Panasonic
--
--
Resistor
Resistor
Resistor
Resistor
Transistor
--
RFREQ
37.4 kΩ, 1%
0.007 Ω, 2%
--
RSWCS
--
M1 , M2 , M3 , M4
Dual MOSFET:
Infineon
IPG20N10S4L-35
100 V / 35 mΩ N-ch
Datasheet
73
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
13.1
Further Application Information
Typical Performance Characteristics of Device
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ꢁ5ꢂ
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ꢁ5ꢀꢁ
ꢁ
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ꢅ5ꢉꢁ
ꢅ5ꢉ
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ꢃꢀ
ꢄꢀ
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!"R !ꢄZꢏꢐ ꢇꢌ.ꢈVꢋ.QCꢎꢇ0ꢋꢇꢌVI]
ꢁꢆꢑꢌ(ꢆꢂꢇꢀQCꢉ:$Vꢇ0ꢋꢇꢌVI]
ꢂ5ꢅꢅ
ꢂ5ꢅꢄ
ꢂ5ꢅꢃ
ꢂ5ꢅꢂ
ꢂ5ꢅ
ꢂꢁꢅ
ꢂꢁꢄ
ꢂꢁꢃ
ꢂꢁꢂ
ꢂꢁꢀ
ꢂꢅꢊ
ꢂꢅꢉ
ꢂꢅꢏ
ꢂꢅꢋ
ꢎJ:CQ$ꢐꢑ1I8Yꢂꢀꢀꢒ5ꢐ"#ꢓYꢀ5ꢂꢁꢍ
ꢎJ:CQ$ꢐꢑ1I8Yꢂꢀꢀꢒ5ꢐ"#ꢓYꢂꢃꢍ
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ꢍ^"#ꢓR"#%_ YꢐꢐꢂꢁꢀIꢍ
ꢂ5ꢄꢊ
ꢂ5ꢄꢉ
ꢂ5ꢄꢏ
ꢂ5ꢄꢋ
Rꢅꢀ
ꢂꢀ
ꢋꢀ
ꢂꢂꢀ
Rꢅꢀ
ꢂꢀ
ꢋꢀ
ꢂꢂꢀ
ꢌVI]Vꢈ:ꢉ%ꢈVꢇ`ꢍꢃa
ꢌVI]Vꢈ:ꢉ%ꢈVꢇ`ꢍꢃa
Figure 46 Characterization Diagrams 1
Datasheet
74
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
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ꢀ
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!"
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ꢃꢀꢀ
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Figure 47 Characterization Diagrams 2
For further information you may contact http://www.infineon.com/
•
Datasheet
75
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Package Outlines
14
Package Outlines
0ꢀ9 MAXꢀ
(0ꢀ65)
11 x 0ꢀ5 = 5ꢀ5
0ꢀ1
7
A
0ꢀ5
0ꢀ26
0ꢀ03
6ꢀ8
0ꢀ1
+0ꢀ031)
2)
37
B
0ꢀ05
36
25
0ꢀ13
24
48x
0ꢀ08
48
13
1
12
Index Marking
48x
0ꢀ1
0ꢀ4 x 45°
0ꢀ05
Index Marking
0ꢀ23
(0ꢀ35)
M
A B C
(0ꢀ2)
0ꢀ05 MAXꢀ
(5ꢀ2)
(6)
C
1) Vertical burr 0ꢀ03 maxꢀ, all sides
2) These four metal areas have exposed diepad potential
PG-VQFN-48-29, -31-PO V05
Figure 48 PG-VQFN-48 (with LTI)
Datasheet
76
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Package Outlines
H
C
0.6±0.15
SEATING
PLANE
0.08
48x
C
COPLANARITY
9
7 1)
0.2 A-B D
48x
BOTTOMVIEW
2)
0.2 A-B D H
4x
5
EXPOSEDDIEPAD
D
A
B
48
1
48
1
INDEXMARKING
0.5
0.22±0.05
0.08
A-B D C
48x
1)DOESNOTINCLUDEPLASTICORMETALPROTRUSIONO0F.25MAX.PERSIDE
2)EXPOSEDPADFORSOLDERINGPURPOSE
Figure 49 PG-TQFP-48
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Dimensions in mm
Datasheet
77
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Revision History
15
Revision History
Table 18 Revision History
Revision
Rev. 1.0
Date
Changes
2019-11-21
2019-12-11
2019-12-11
Released datasheet
Rev. 1.10
Rev. 1.10
changed ESD in to “CDM” AECQ100-011 including revision : Rev. D
Updated Vout Overvoltage description Chapter 10.2
Datasheet
78
Rev. 1.10
2019-12-11
TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
Table of Content
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
5
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Different Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Different Possibilities to RESET the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
5.2
5.3
6
6.1
6.2
6.3
Regulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Regulator Diagram Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Adjustable Soft Start Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Switching Frequency setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operation of 4 switches H-Bridge architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Boost mode (VIN < VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Buck mode (VIN > VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Buck-Boost mode (VIN ~ VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fast Output Discharge Operation Mode - Multi Floating Switches Topology . . . . . . . . . . . . . . . . . . . . 25
Programming Output Voltage (Constant Voltage Regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4
6.4.1
6.4.2
6.4.3
6.5
6.6
6.7
7
7.1
7.2
Digital Dimming Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8
Analog Dimming and Limp Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LED current calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1
8.2
8.3
9
9.1
9.2
Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IVCC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10
Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Output Overvoltage, Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Short Circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Input voltage monitoring, protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Input current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Output current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Device Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1
10.2
10.2.1
10.2.2
10.3
10.4
10.5
10.6
10.7
11
Infineon FLAT SPECTRUM Feature set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Datasheet
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Rev. 1.10
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TLD5542-1
H-Bridge DC/DC Controller with SPI Interface
11.1
11.2
11.3
11.4
11.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Synchronization Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EMC optimized schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SPI Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.1
12.2
12.3
12.4
12.5
12.6
12.6.1
12.6.2
13
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.1
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14
15
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table of Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Datasheet
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Edition 2019-12-11
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Document reference
TLD5542-1
相关型号:
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