TDM3885 [INFINEON]

IPOL 3 A 采用集成电感的单输出高效率降压稳压器模块;


型号：	TDM3885
厂家：	Infineon
描述：	IPOL 3 A 采用集成电感的单输出高效率降压稳压器模块稳压器
文件：	总38页 (文件大小：1473K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDM3885

TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Features

•

Optimized Module with inductor included

Micro Sized 3.1mm x 3.8mm x 2.3mm

Continuous 4A Load Capability

Single Input Voltage Range (4.7V to 14V)

600kHz Switching Frequency

10uA Supply Current at Shutdown

Enhanced Stability IPOL Engine Stable with Ceramic Capacitors and no External Compensation

Enhanced Light Load Efficiency with Reduced Switching Frequency and Diode Emulation

Forced Continuous Conduction Mode Option

Thermally Compensated Internal Over-Current Protection

Internal Soft-Start, Enable Input , PreBias Start Up, Thermal Shut Down, Power Good Output

Precision Reference Voltage (0.5V+/-1.0%)

Lead-free, Halogen-free and RoHS6 Compliant

Potential applications

•

Server and Computing

Storage and Applications

Communications Infrastructure

General DC-DC Converters.

Distributed Point of Load Power Architectures.

Product validation

Qualified for Industrial Applications

Description

The TDM3885 4A Point of Load Module is an easy-to-use, fully integrated and highly efficient DC/DC module.

The module’s PWM controller, MOSFETs and inductor make TDMꢀꢁꢁꢂ a space-efficient solution, providing

accurate power delivery. The TDM3885 employs an Enhanced Stability Engine that makes it stable with ceramic

capacitors without compensation.

TDM3885 can operate in Forced Continuous Conduction Mode (FCCM) or can enter Diode Emulation Mode

(DEM) during light loads to save power. With ultra-light loads, TDM3885 can enter a low quiescent current mode

making it ideal for Standby power supplies. The switching frequency is 600kHz for an optimum solution.

It also features important protection functions, such as Pre-Bias startup, internal Soft-start, hiccup over-current

protection and thermal shutdown to give required system level security in the event of fault conditions.

Final Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Table of contents

Features ........................................................................................................................................ 1

Potential applications..................................................................................................................... 1

Product validation.......................................................................................................................... 1

Description .................................................................................................................................... 1

Table of contents............................................................................................................................ 2

Ordering Information ............................................................................................................. 3

2.1

2.2

Description............................................................................................................................ 4

PinOut......................................................................................................................................................4

Block Diagram .........................................................................................................................................5

Electrical Specifications.......................................................................................................... 6

Absolute Maximum Ratings ....................................................................................................................6

Maximum Operating Conditions.............................................................................................................6

Electrical Characteristics ........................................................................................................................7

Typical Operating Characteristics ..........................................................................................................8

Typical Efficiency Curves.......................................................................................................................11

3.1

3.2

3.3

3.4

3.5

Theory of Operation ..............................................................................................................12

Description ............................................................................................................................................12

Enhanced Stability IPOL Engine ...........................................................................................................12

Pseudo-Constant Switching Frequency ...............................................................................................12

Soft-Start ...............................................................................................................................................12

En/FCCM ................................................................................................................................................13

Pre-Bias Start-Up...................................................................................................................................15

Over-Current Protection .......................................................................................................................15

Minimum On-Time and Off-Time..........................................................................................................16

Over-Voltage Protection .......................................................................................................................16

PGood ....................................................................................................................................................17

Over-Temperature Protection ..............................................................................................................18

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

Application...........................................................................................................................19

Application Information........................................................................................................................19

Typical Application Diagrams ...............................................................................................................21

Recommended configurations .............................................................................................................23

Typical Operating Waveforms...............................................................................................................24

5.1

5.2

5.3

5.4

Marking Information .............................................................................................................28

Tape and Reel Information .....................................................................................................29

Mechanical Pad Drawing ........................................................................................................30

9.1

PCB Metal and Component Placement .....................................................................................31

Reflow guideline....................................................................................................................................31

Stencil Design .......................................................................................................................32

Layout Recommendations......................................................................................................33

Environmental Qualifications .................................................................................................35

Evaluation Board and Support Documentation.........................................................................36

Final Datasheet

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Ordering Information

Table 1

Ordering Information

Base Part and Number Package Type

Standard Pack Form and Qty

Tape and Reel 2500

Orderable Part Number

TDM3885

PG-LGA-15-2

TDM3885XUMA1

3.1 mm x 3.8 mm

Figure 1

Picture of the Product

Figure 2

TDM3885 Part Number Configuration

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Description

2.1

PinOut

Figure 3

Table 2

Pinout, Numbering and Name of Pins (transparent top view)

Pin Descriptions

Pin #

Pin Name Pin Type Pin Description

Input supply for the power stage.

PV_in

AGND

Signal ground for the internal reference and control circuitry.

Input bias for the internal control circuitry and driver. Generated by internal LDO via

Vcc

PV_in. A 2.2 µF ceramic capacitor is recommended between Vcc and the Power ground

(PGND).

Over-Current Protection (OCP) limit set point. Three user selectable OCP limits are

available by floating this pin, connecting it to Vcc or connecting it to PGND.

Power Good status pin. Output is an open Drain. Connect a pull up resistor from this pin

to Vcc or an external bias voltage.

OCSET

Power Ground. These pins serve as a separate ground for the MOSFET drivers and

should be connected to the system’s power ground plane.

Output voltage. Connect this pin to the load and decoupling capacitors.

6, 8, 14, 15

PGND

V_out

Output voltage feedback pin. Connect this pin to the output of the regulator via a

resistor divider to set the output voltage.

Vo sense pin. Connect this pin directly to the output of the regulator to set the on-time.

Multifunction pin: (1) Enable pin to turn the IC on and off. (2) Enable Diode Emulation

(DEM) Mode operation or Forced Continuous Conduction (FCCM) Mode operation.

Supply voltage for the high side driver. Connect this pin to the SW node of the regulator

through a bootstrap capacitor.

En/FCCM

BOOST

Switch Node. This pin is connected to the integrated output inductor.

Note:

I = Input, O = Output, S = Signal

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Description

2.2

Block Diagram

VCC

AGND

PVin

LDO

VCC

Enable

LDrVin

BOOST

PVIN

VREF

INTERNAL REFERENCE

Fault PVin

SOFT

START

PWM

COMP

Fault

ADAPTIVE

ON-TIME

GENERATOR

PWM

HDrVin

HDrv

SET

INTERNAL RAMP

GATE

DRIVE

LOGIC

Vcc

HDrVin

VOUT

VCC

Fault

DETECTION

POR

LDrVin

LDrv

POR

Fault

EN/

Zcross

THERMAL SHUT-

DOWN

PGND

FCCM

CONTROL

LOGIC

FCCM_EN

Zero Cross

DETECTION

PGND

FCCM

LDrVin

Current Limit

Control

POR

OCSet

The Integrated inductor is 0.68 uH

Figure 4

TDM3885 Block Diagram

Final Datasheet

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Electrical Specifications

3.1

Absolute Maximum Ratings

Stresses beyond these listed under ꢃAbsolute Maximum Ratingsꢄ may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these or any other conditions beyond

those indicated in the operational sections of the specifications are not implied.

Table 3

TDM3885 Absolute Maximum Ratings

-0.3 V to 14 V (dc), 16 V (ac, 2 µs)

-0.3 V to 6 V

PV_in, En/FCCM to PGND (Note 2, Note 3)

Vcc to PGND (Note 2)

Boost to PGND (Note 2)

-0.3 V to 22 V(dc), 24 V (ac, 10 ns)

-0.3 V to 16 V (dc), -4 V to 18 V (ac, 10 ns)

-0.3 V to Vcc+0.3 V (Note 1)

-0.3 V to 6 V(dc), 6.5 V (ac, 10 µs)

-0.3 V to 6 V

SW to PGND (Note 2)

Boost to SW

Vo, Fb to AGND (Note 2)

OCSet, PG to AGND (Note 2)

PGND to AGND

-0.3 V to +0.3 V

Thermal Information

Junction to Ambient Thermal Resistance Ɵ_JA

Junction-to-top Thermal characterization parameter ꢅ_JT

Junction-to-board Thermal characterization parameter ꢅ_JB

Storage Temperature Range

Junction Temperature Range

40.5 °C/W (Note 12)

8.0 °C/W (Note 12)

12.0 °C/W (Note 12)

-ꢂꢂ °C ≤Ta ≤ ꢆꢇꢂ °C

-ꢈꢉ °C ≤ Tj ≤ ꢆꢇꢂ °C

Note:

1. Must not exceed 6 V.

2. PGND pin and AGND pin are connected together.

3. SW node voltage should not exceed the max voltage defined in Table 3

3.2

Maximum Operating Conditions

Table 4

Maximum Operating Conditions

Definitions

Symbol

Min

4.7

4.4

0.5

Max

Units

Input Voltage Range (Note 4, Note 5)

PV_in

Vcc

Supply Voltage Range (Note 5)

5.5

3.3

5.0

Output Voltage Range (PV_in=4.7 to 8V, I_out=0 to 3A)

Output Voltage Range (PV_in=8 to 14V, I_out=0 to 4A)

Continuous Output Current Range (PV_in=4.7 to 8V)

Continuous Output Current Range (PV_in=8 to 14V)

Operating Junction Temperature

T_j

-40

125

°C

Note:

4. External Vcc supply voltage is not supported to bypass the internal LDO.

5. Maximum SW node voltage should not exceed the max voltage defined in Table 3.

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Electrical Specifications

3.3

Electrical Characteristics

Unless otherwise specified, these specifications apply over, 5.5 V < PV_in< 14 V, 0 °C < Tj < 125 °C. Typical values

are specified at Ta = 25 °C.

Table 5

Electrical Characteristics

Symbol

Parameter

Power Stage

Top Switch

Conditions

Min

Typ

Max Unit

R_{ds (on)_Top}

R_{ds (on)_Bot}

V_Boot–V_sw= 5.2 V, T_j= 25 C

V_cc= 5.2 V, T_j= 25 C

I_Boot=10 mA

106.4

mꢊ

Bottom Switch

33.9

Boot Diode Forward Voltage

Supply Current

200

300

PV_inSupply Current (Standby)

PV_inSupply Current (Static)

I_{in (Standby)}

I_{in (Static)}

Enable low

0.22

0.7

µA

En = 2 V, No switching

0.5

Enable high, PV_in= 12 V,

Fs = 600 kHz

PV_inSupply Current (Dyn)

I_{in (Dyn)}

Soft Start

Soft Start Ramp Rate

V_FBVoltage

SS_rate

V_FB

0.16

0.2

0.5

0.24

mV/µs

Feedback Voltage

0^°C < T_j< 85 ^°C

-40 ^°C < T_j< 125 ^°C (Note 6)

-0.6

-1

+0.6

Accuracy

V_FBInput Current

On-Time Timer Control

On Time

I_VFB

V_FB= 0.5 V, T_j= 25 C

-0.4

+0.4



T_on

PV_in= 12 V, V_out= 1.05 V

Note 7, PV_in= 12 V, V_out= 0 V

T_j= 25 C, V_FB= 0 V

146

Minimum On-Time

Minimum Off-Time

Thermal Shutdown

Hysteresis

T_on(Min)

T_off(Min)

240

300

Note 7

145

°C

Under Voltage Lockout

V_cc-Start-Threshold

V_CC-Stop-Threshold

V_CC_UVLO_Start

V_CC_UVLO_Stop

Enable_High

Enable_Low

R_EN

Vcc Rising Trip Level

Vcc Falling Trip Level

Ramping up

4.2

3.8

1.2

4.4

4.1

3.6

1.14

0.9

500

2.6

1.36

1.06

1500

Enable Threshold

k

Ramping down

Input Impedance

FCCM Start Threshold

FCCM Stop Threshold

Current Limit

1000

V_{FCCM_start}

V_{FCCM_stop}

2.3

0 °C<Tj< 125 °C, OCSet = PGND

4.4

6.5

6.9

Current Limit Threshold

Hiccup Blanking Time

Ioc

0 °C <Tj< 125 °C, OCSet = Floating

0 °C <Tj< 125 °C, OCSet = Vcc

Note 7

3.4

2.4

5.4

4.3

5.7

4.6

Tblk_Hiccup

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Electrical Specifications

OV Protection

Output OV Protection Threshold

V_ovp

OVP detect

115

120

125

Output OV Protection Delay

PGood

T_OVPDEL

S

Power Good Upper Threshold

Power Good Lower Threshold

Power Good Sink Current

V_PG(upper)

V_PG(lower)

I_PG

Fb Rising

Fb Falling

PG = 0.5 V, En = 2 V

2.5

Power Good Voltage Low when

no supply

PV_in= Vcc = 0 V,

R_pull-up=ꢂꢉ kΩ to ꢀ.ꢀ V

V_PG(low)

0.3

0.5

Note:

6. Cold & hot temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.

7. Guaranteed by design but not tested in production.

3.4

Typical Operating Characteristics

Unless otherwise specified, typical curves are generated at room temperature.

FSW vs. PVIN, FCCM, Io=0A

700

690

680

670

660

650

640

Vout=3.3V

PVin (V)

Figure 5

Switching Frequency vs. Input Voltage in FCCM, V_out= 3.3 V

Final Datasheet

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Electrical Specifications

FSW vs. IOUT, FCCM, PVin=12V

800

760

720

680

640

600

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Iout (A)

Vout=3.3V

Figure 6

Switching Frequency vs. Output Current in FCCM, V_out= 3.3 V

Load Regulation, FCCM

3.350

3.325

3.300

3.275

3.250

0.5

1.5

2.5

3.5

Iout (A)

Vin=12V, Vout=3.3V

Figure 7

Load Regulation for Vo = 3.3 V

Final Datasheet

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Electrical Specifications

THERMAL DERATING, PVIN = 12V

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Ambient Temperature (°C)

12V-3.3V 12V-1.8V

105

12V-5V

12V-1.0V

Figure 8

TDM3885 Thermal Derating, Tested at 0LFM, Climate chamber, the Case Temperature was

monitored with a 125C limit.

Final Datasheet

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Electrical Specifications

3.5

Typical Efficiency Curves

PV_in= 12 V [Io = 0 A – 4 A] and PV_in= 5 V [Io = 0 A – 3 A], Room Temperature, No Air Flow. Note that the efficiency

curves include the losses of TDM3885 and the inductor losses.

TDM3885 EFFICIENCY @PVin=5V

100

Vout=1.0V - FCCM

Vout=1.2V - FCCM

Vout=1.8V - FCCM

Vout=3.3V - FCCM

Vout=1.0V - DEM

Vout=1.2V - DEM

Vout=1.8V - DEM

Vout=3.3V - DEM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Load Current (A)

Figure 9

Efficiency Curves for PV_in= 5 V

TDM3885 EFFICIENCY @PVin=12V

Vout=1.0V - FCCM

Vout=1.2V - FCCM

Vout=1.8V - FCCM

Vout=3.3V - FCCM

Vout=5.0V - FCCM

Vout=1.0V - DEM

Vout=1.2V - DEM

Vout=1.8V - DEM

Vout=3.3V - DEM

Vout=5.0V - DEM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Load Current (A)

Figure 10

Efficiency Curves for PV_in= 12 V

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Theory of Operation

4.1

Description

The TDM3885 is an easy-to-use, fully integrated and highly efficient monolithic dc-dc regulator. The on-chip

PWM controller, MOSFETs and integrated inductor make TDM3885 a space-efficient solution, providing

accurate power delivery.

The TDM3885 offers two different operation modes: Forced Continuous Conduction Mode (FCCM) and Diode

Emulation Mode (DEM). With FCCM, the device always operates as a synchronous buck converter with a

pseudo- constant switching frequency of 600 kHz and small output voltage ripples. In DEM, the synchronous

FET is turned off when the inductor current drops to zero, which provides better efficiency at light load.

4.2

Enhanced Stability IPOL Engine

The TDM3885 uses the Enhanced Stability IPOL engine that comprises Constant On-Time (COT) control with

proprietary internal ramp compensation to offer stability across a wide range of conditions.

Unlike conventional COT devices, which usually require a certain amount of output ripple voltage to ensure

stability, the TDM3885 includes proprietary internal ramp compensation, facilitating the use of low ESR ceramic

output capacitors.

In addition, the internal ramp implements the input voltage feed-forward feature, which helps to preserve the

same loop response with a wide input voltage range.

The operation of TDM3885 is described as follows. The output voltage of the regulator is fed to the FB pin

through a resistor divider. Combined with the proprietary internal ramp, the FB voltage is then compared to an

internal reference voltage. If the combined voltage is lower than the reference voltage, the control FET is turned

on for a fixed duration to charge the output capacitor. When the on-time of the control FET is finished, the

synchronous FET is turned on. In FCCM, synchronous FET stays on until the combination of FB voltage and the

internal ramp drops below the reference voltage and a new PWM pulse is initiated. In DEM, synchronous FET

will be turned off when the inductor current drops to zero.

4.3

Pseudo-Constant Switching Frequency

The TDM3885 operates with a pseudo-constant frequency of 600 kHz within the recommended operation

range. To achieve constant switching frequency, the on-time of the control FET is automatically adjusted for

different input and output voltages.

The on-time is determined by the ratio of the voltages at the V₀pin and the PV_inpin, and can be calculated as

follows:

ꢄ

ꢂ

T_ꢀꢁ=

6ꢅꢅ kHz

iꢃ

4.4

Soft-Start

The TDM3885 has an internal digital soft-start circuit to control the output voltage rise time, and to limit the

current surge at start-up. To ensure correct start-up, the soft-start sequence initiates when Enable and Vcc

voltages rise above their UVLO thresholds and the internal Power On Ready (POR) signal is asserted. The

internal soft-start signal linearly rises at the rate of 0.2 mV/µs. The normal V_outstart-up time is fixed, as shown

below.

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Theory of Operation

ꢋ.ꢌ ꢍ

ꢆ_{ꢇꢈꢉꢊꢈ}

= ꢎ. ꢌ ꢏꢇ

ꢋ.ꢎ ꢏꢍ/ ꢐꢇ

The over-current protection (OCP) and over-voltage protection (OVP) are enabled during soft-start to protect

the device against any short circuit or over-voltage condition. Figure 11 illustrates the theoretical operation

waveforms during the start-up.

POR

PGood

0.5V

Internal SS

0.9* Vref

Figure 11

Theoretical operation waveforms during soft-start

4.5

En/FCCM

En/FCCM is a multi-function pin. It can be used to:

•

Turn the TDM3885 on and off

Select the operation mode: FCCM or DEM

Implement Under-Voltage Lockout of the Input Voltage

When En/FCCM voltage is higher than the Enable_high threshold (1.2 V typical), the TDM3885 is turned on with

DEM. In order to operate in FCCM, the En/FCCM voltage needs to be above 2.6 V. The Enable/FCCM thresholds

are designed to be compatible with 3.3 V logic.

The TDM3885 has a precise Enable_high threshold voltage, which is internally monitored by the Under-Voltage

Lockout (UVLO) circuit. As shown in Figure 12, the input of the Enable pin can be derived from the PV_involtage

by a resistor divider, R_EN1and R_EN2. By selecting different divider ratios, users can program the UVLO threshold

voltage. The bus voltage UVLO is a very useful feature. It prevents the TDM3885 from operating when PV_inis

lower than the desired voltage level.

For some space-constrained designs, the En/FCCM pin can be directly connected to PV_inwithout using an

external resistor divider.

The En/FCCM pin should not be left floating. A pull-down resistor in the range of tens of kilohms is

recommended.

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Theory of Operation

Figure 13 shows the connections of En/FCCM without using the external resistor divider. Figure 14 and Figure

15 illustrate the theoretical start-up waveforms.

PVin

Vcc

R_EN1

En/FCCM

TDM3885

R_EN2

Figure 12

Single supply configuration with adjustable PV_inUVLO and optional FCCM or DEM

PVin

Vcc

En/FCCM

TDM3885

Figure 13

Single supply configuration with FCCM operation

PVin=Enable=12 V

Vcc

En Threshold

Vcc_UVLO

90% of Vref

PGood

PGood stays at logic low

Figure 14

Start-up with PV_inand Enable tied together. PGood is pulled up to an external supply

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Theory of Operation

PVin=12 V

Vcc

Vcc_UVLO

Enable > 1.2 V

90% of Vref

PGood

PGood stays at logic low

Figure 15

Start-up with Enable up after PV_in. PGood is pulled up to an external supply

4.6

Pre-Bias Start-Up

The TDM3885 is able to start up into a pre-charged output without causing oscillation and disturbances of the

output voltage. When TDM3885 starts up with a pre-biased output voltage, both control FET and Synch FET are

kept off until the internal soft-start signal exceeds the FB voltage.

During pre-bias start-up, the PGood signal is held low until the first gate signal for the control FET is generated.

4.7

Over-Current Protection

TDM3885 has three selectable Over-Current Protection (OCP) thresholds determined by the voltage level of the

OCSet pin. The OCP is performed by sensing the current through the R_DS(on)of the Sync MOSFET. This method

enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and mitigates layout-

related noise issues. The current limit is pre-set internally and is thermally compensated to minimize OCP limit

variation.

The OCP circuit senses the current of the Sync MOSFET 100 ns after the Control FET is turned off. If the current

exceeds the OCP limit, PGood and soft start signals will be pulled low. The Sync FET remains on until the

current is decreased to zero. The TDM3885 then enters hiccup mode. Both Control FET and Sync FET remain off

during the hiccup blanking time. After the hiccup blanking time expires, the TDM3885 will try to restart. If the

over-current fault is still detected, the preceding actions will be repeated. The TDM3885 stays in hiccup mode

until the over-current fault is removed. Figure 16 illustrates the operation of OCP.

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Theory of Operation

100ns

Current Limit

Inductor

Current

Hiccup

Blanking time

HDrv

LDrv

PGood

Figure 16

Illustration of OCP with hiccup Mode

4.8

Minimum On-Time and Off-Time

The minimum on-time refers to the shortest time for control FET to be reliably turned on. Typically, it is 20 ns.

In both DEM and FCCM, the Sync FET stays on for at least 240 ns, which is referred to as the minimum off-time.

The minimum off-time is needed to charge the bootstrap capacitor and to monitor the current of the Sync FET

for OCP.

4.9

Over-Voltage Protection

The TDM3885 senses voltage at the FB pin for Over-Voltage Protection (OVP). When FB voltage exceeds the OVP

threshold for longer than the output OV protection delay ꢋtypical value is ꢂ μsꢌ, the OVP circuitry is tripped. The

Control FET is turned off immediately and PGood is pulled low. The Sync FET is turned on to discharge the

output capacitor until the FB voltage drops below the OVP threshold.

Once OVP is tripped, the Control FET remains latched off until a reset is performed by cycling either P_Vinvoltage

or the Enable signal. Figure 17 illustrates the operation of over-voltage protection.

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Theory of Operation

HDrv

LDrv

120%V_ref

115%V_ref

V_ref

90%V_ref

PGood

OVP delay =5us

Figure 17

Operation of Over-Voltage Protection

4.10

PGood

The PGood pin is the open drain of an internal NFET and needs to be externally pulled high through a pull-up

resistor, e.g., ꢈꢍ.ꢍ kΩ.

The PGood signal is high when three criteria are satisfied:

1. Enable and VCC UVLO voltage are above their respective thresholds;

2. No fault occurs including over-current, over-voltage and over-temperature;

3. Output voltage (V_out) is in regulation.

In order to detect if V_outis in regulation, the PGood comparator continuously monitors the FB pin voltage. When

FB voltage ramps up above the upper threshold (90% of Vref), the PGood signal is pulled high. When FB voltage

ramps down below the lower threshold (85% of Vref), the PGood signal is pulled low. Figure 18 illustrates the

PGood upper and lower thresholds.

For pre-biased start-up, PGood is not active until the first gate signal of the control FET is initiated.

TDM3885 also integrates a PFET in parallel with the PGood NFET, as shown in Figure 4. This PFET allows the

PGood signal to stay at logic low when the bias voltage of TDM3885 is low, and/or if the En is low. Please refer

to Figure 14 and Figure 15.

Final Datasheet

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Theory of Operation

90%V_ref

V_ref

85%V_ref

PGood

Figure 18

Power Good Thresholds

4.11

Over-Temperature Protection

Temperature sensing is provided by the TDM3885. The Over-Temperature Protection (OTP) threshold is

typically set to 145 °C. When the OTP threshold is exceeded, both MOSFETs are turned off and the internal soft

start is reset. The internal LDO is still in operation when OTP is tripped.

Automatic restart is initiated when the sensed temperature drops below the OTP threshold. The hysteresis of

the OTP threshold is 25 °C.

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Application

5.1

Application Information

The following example is a typical application for TDM3885. The application circuit is shown in Figure 19.

•

PV_in=12 V

V₀= 3.3 V

I₀= 4 A

V₀Ripple voltage = ± 1% of V₀

Transient response = ± 3% of V₀for 30% Load transient

ENABLE TDM3885

To enable TDM3885 in Diode Emulation Mode (DEM), the voltage at the EN/FCCM pin should be higher than the

Enable threshold, but lower than FCCM stop threshold. If a resistor divider is used to generate the Enable

voltage from PV_inas shown in Figure 12, the resistor divider can be selected as follows.

R_{EN 2}

PV_in(min)



1.36

R_EN1+ R_{EN 2}

R_{EN 2}

PV_in(max)



 2.3

R_EN1+ R_{EN 2}

Where PV_{in (min)}and PV_{in (max)}are the minimum and maximum input voltages respectively.

To enable TDM3885 in FCCM, the voltage at EN/FCCM pin should be no less than the FCCM start threshold. The

EN/FCCM pin can be connected directly to PV_inas shown in Figure 13, or a resistor divider can be used, Figure

12. The following criterion should be satisfied when selecting the resistor divider for FCCM.

R_{EN 2}

PV_in(min)



 2.6

R_EN1+ R_{EN 2}

INPUT CAPACITOR SELECTION

Without input capacitors, the pulse current of the control FET is provided directly from the input power supply.

Due to the impedance on the input power supply cabling, the pulse current can disturb the input voltage and

potential EMI issues can result. The input capacitors filter the pulse current of the control FET, reducing these

risks and resulting in almost constant current from the input supply.

The input capacitors should be selected to tolerate the input pulse current, and to reduce input voltage ripple.

The RMS value of the input ripple current can be expressed as:

I_RMS= I₀ D(1− D)

V₀

D =

V_in

Where I_RMSis the RMS value of the input capacitor current. I₀is the output current. D is the duty ratio.

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Application

To meet the requirement of the input ripple voltage, the minimum input capacitance can be calculated as

follows.

I₀ D(1− D)

C_in(min)



f_sw V

in(max)

Where ΔV_in(max)is the maximum allowable peak-to-peak input ripple voltage.

Ceramic capacitors are recommended as input capacitors due to low ESR, ESL and high RMS current capability.

In addition, a bulk capacitor is recommended if the input supply is not located close to the voltage regulator.

OUTPUT CAPACITOR SELECTION

To ensure loop stability, a minimum of one 22 µF output capacitor is suggested. The voltage ripple and

transient requirements determine the output capacitor selection.

The following formula calculates the peak-to-peak output voltage ripple due to the inductor ripple current

charging the output capacitor.

i_{L max}

V₀=

8C₀ f_sw

Therefore,

i_{L max}

C₀

8 V_0min f_sw

Where ΔV_0minis the minimum allowable peak-peak output ripple voltage. Δi_Lmaxis the maximum inductor ripple

current.

The ESR and ESL of the output capacitors, as well as the parasitic resistance or inductance due to PCB layout,

can also contribute to the output voltage ripple. For most applications, it is suggested to use Multi-Layer

Ceramic Capacitors (MLCC) for their low ESR, ESL and small size.

To meet the transient response requirements, the output capacitors should also meet the following criterion.

L I₀²_max

C₀

2 V_{0L _ max}V₀

Where ΔV_{0L_max}is the max allowable Vo deviation during the load transient. ΔI_0maxis the maximum step load

current. Please note that the impact of ESL, ESR, control loop response, transient load slew rate, and PWM

latency is not considered in the calculation shown above. Extra capacitance is usually needed to meet transient

response requirements.

OUTPUT VOLTAGE PROGRAMMING

Output voltage can be programmed with an external voltage divider. The FB voltage is compared to an internal

reference voltage of 0.5 V. The divider ratio is set to provide 0.5 V at the FB pin when the output is at its desired

value. The calculation of the feedback resistor divider is shown below.

R₁

V₀= V_ref (1+

)

R₂

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Application

The bottom feedback resistor is recommended not to exceed 20 kꢊ, in order to avoid interference with the

internal circuitry.

FEEDFORWARD CAPACITOR

A small MLCC capacitor C_ff, can be placed in parallel with the top feedback resistor to improve transient

response. As a general rule of thumb, for a fixed top feedback resistor of 39.2 kꢊ, 100 pF can be used for C_ff.

BOOTSTRAP CAPACITOR

For most applications, a 0.1 µF ceramic capacitor is recommended for the bootstrap capacitor placed between

the SW node and the Boot pin.

VCC BYPASS CAPACITOR

A 2.2 µF ceramic capacitor should be placed between VCC and PGND.

5.2

Typical Application Diagrams

BOOST

0.1µF

PVin

12V

PVin

49.9k

EN/FCCM

2x 22µF

16.7k

VOUT

TDM3885

100pF

47µF 47µF 47µF

VCC

2.2µF

39.2k

49.9k

OCSET1

6.98k

OCSET

OCSET2

OCSET3

Vout = 3.3V

Iout = 4A

Fsw = 600kHz

Op. Mode = FCCM

PGND

AGND

Figure 19

Application Diagram PV_in= 12 V, V_out= 3.3 V, I_out= 4 A, FCCM

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Application

BOOST

0.1µF

PVin

12V

PVin

49.9k

EN/FCCM

2x 22µF

10k

VOUT

TDM3885

100pF

47µF 47µF 47µF

VCC

2.2µF

39.2k

6.98k

49.9k

OCSET1

OCSET

OCSET2

OCSET3

Vout = 3.3V

Iout = 0A

Fsw = 600kHz

Op. Mode = DEM

PGND

AGND

Figure 20

Application Diagram PV_in= 12 V, V_out= 3.3 V, I_out= 0 A, DEM

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Application

5.3

Recommended configurations

Table 6 lists recommended configurations for a few commonly used output voltages.

Table 6

PV_in(V)

Recommended configurations

V_out(V)

Upper FB

Lower FB

Cff (pF)

Minimum Co Maximum Co

Resistor kΩ

ꢀμFꢁ

Note 9

5.0

3.3

2.5

1.8

1.2

1.0

3.3

2.5

1.8

1.2

1.0

39.2

16.5

39.2

16.5

4.32

6.98

9.76

15.0

11.8

16.5

6.98

9.76

15.0

11.8

16.5

100

3 x 47µF

14 x 47µF

12 x 47µF

10 x 47µF

14 x 47µF

12 x 47µF

10 x 47µF

Note:

8. All resistors are 0402, E96 series, 1% standard

9. The output capacitors are selected to meet ±1% output ripple voltage and ±3% undershoot/overshoot at 30% of max load transient

with 2.5A/µs slew rate. Please note that 47µF is rated capacitance at 0V DC bias voltage.

10. Application should not exceed the max operating conditions defined in Table 4.

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Application

5.4

Typical Operating Waveforms

PVin = 12.0V, Vo=3.3V, Io=0A - 4A, No airflow, room temperature

Figure 21 Start-up, PV_in=12V, V_out= 3.3V, I_out= 0A, FCCM. C_H1= V_out, C_H2= PV_in, C_H3= P_GOOD, C_H4= V_CC,C_H5=

Enable, C_H6= V_FEEDBACK

Figure 22 Start-up, PV_in=12V, V_out= 3.3V, I_out= 4A, FCCM. C_H1= V_out, C_H2= PV_in, C_H3= P_GOOD, C_H4= V_CC, C_H5=

Enable, C_H6= V_FEEDBACK

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Application

Figure 23 Start-up Prebias [1V], PV_in=12V, V_out= 3.3V, I_out= 0A, FCCM. C_H1= V_out, C_H2= PV_in, C_H3= P_GOOD, C_H4=

V_CC, C_H5= Enable, C_H6= V_FEEDBACK

Figure 24

OVP, PV_in=12V, V_out= 3.3V, I_out= 0A, FCCM. C_H1= V_out, C_H2= PV_in, C_H3= P_GOOD, C_H4= V_CC, C_H5=

Enable, C_H6= V_FEEDBACK

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Application

Figure 25 Short Circuit, PV_in=12V, V_out= 3.3V, I_out= 4A, FCCM. C_H1= V_out, C_H2= PV_in, C_H3= P_GOOD, C_H4= V_CC, C_H5

= Enable, C_H6= V_FEEDBACK

Figure 26 V_outripple, PV_in=12V, V_out= 3.3V, I_out= 4A, FCCM. C_H1= V_out

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Application

Figure 27 SW node, PV_in=12V, V_out= 3.3V, I_out= 0A, FCCM. C_H1= SW

Figure 28 Transient Response, PV_in=12V, V_out= 3.3V, I_out= 0A to 4A, FCCM. C_H1= V_out, C_H2= I_out.Slew rate =

5A/µS.

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Marking Information

Figure 29

Package Marking, Left (Front side), Right (Rear side)

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Tape and Reel Information

Figure 30

Pin 1 orientation in the tape

Final Datasheet

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Mechanical Pad Drawing

Figure 31

Mechanical Pad Drawing (all dimensions in mm), Tolerances are as per ISO 2768-mK.

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

PCB Metal and Component Placement

Figure 32

PCB Metal Pad Sizing and Spacing (all dimensions in mm)

9.1

Reflow guideline

Infineon does not recommend specific reflow profiles for our products. Multiple factors influence the reflow

profile: PCB size, thermal mass of the board, layers, copper thickness, etc. The optimum reflow profile should

be generated initially by referring to the solder paste manufacturer’s technical datasheet, and then should be

further optimized for the assembly.

For Maximum reflow temperature and time according to J-STD-020 standard, please refer to the reflow

soldering section in the following application note.

For further information, please refer to ꢃRecommendations for Board Assembly of Infineon Packages with Land

Grid Array Configurationꢄ application note.

Final Datasheet

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TDM3885 IPOL

4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Stencil Design

Figure 33

Stencil Pad Spacing (all dimensions in mm)

Note:

11. Contact Infineon Technologies to receive an electronic PCB Library file in your preferred format.

12. This evaluation board is not according to the JEDEC standard. Evaluation Board Description: DB310 REV5B - The PCB is a six-layer

board (40 x 40 mm) using FR4 material. Top and bottom layers use 0.5 oz. base copper plus 1.5 oz. plating. Inner layers use 2 oz. copper.

The PCB thickness is 1.57 mm. Layer stack-up is top – GND1 – GND2 – signal – GND3 – bottom.

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Layout Recommendations

The pinout of TDM3885 makes it easy to route the PCB layout. General PCB design guidelines should be

followed to achieve the best performance.

•

Bypass capacitors, including input/output capacitors and Vcc bypass capacitor, should be placed as close as

possible to the corresponding pins.

•

SW node area should be minimized and be limited to the top layer only.

Output voltage should be sensed with a separate trace directly from the output capacitor. The sensing trace

should be away from the inductor and SW node to avoid interference from switching noise.

•

The exposed pad can be connected to the power ground plane through via holes to aid thermal dissipation.

Wide copper polygons are best practice for input and output power connections. This provides power loss

reduction and improved thermal performance. Sufficient via holes should be used to connect the power

traces between different layers.

Figure 34

Demo Board Layout – Top layer

Figure 35

Demo Board Layout – PGND pads

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Layout Recommendations

Figure 36

Demo Board Layout – Signal layer

Figure 37

Demo Board Layout – Bottom layer

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Environmental Qualifications

Table 7

Environmental Qualifications

Qualification Level

Industrial

Moisture Sensitivity Level

3.1 mm x 3.8 mm

PG-LGA-15-2

JEDEC Level 3 @ 260 °C

ESD

[HBM] Human Body Model

[CDM] Charge Device Model

RoHS6 Compliant

ANSI/ESDA/JEDEC JS-001, Class 2, (2000V to <4000V)

ANSI/ESDA/JEDEC JS-002, Class C2A (500 to <750)

Yes

† Qualification standards can be found at Infineon Technologies web site: www.infineon.com

Final Datasheet

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4 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor

Evaluation Board and Support Documentation

Table 8

TDM3883 Evaluation Boards and User Guides

Evaluation board

Specifications

Website Address

www.infineon.com/eval-tdm3885-3.3vout

12 V±10%, 3.3 V, 4 A

EVAL_TDM3883_3.3Vout

Final Datasheet

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IMPORTANT NOTICE

The information given in this document shall in no For further information on the product, technology,

Edition 2022-07-11

event be regarded as a guarantee of conditions or delivery terms and conditions and prices please

Published by

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contact your nearest Infineon Technologies office

(www.infineon.com).

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With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement

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contain dangerous substances. For information on

the types in question please contact your nearest

Infineon Technologies office.

Do you have a question about this

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Document reference

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The data contained in this document is exclusively

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to evaluate the suitability of the product for the

intended application and the completeness of the

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respect to such application.

4ꢀAꢀIPOLꢀSynchronousꢀBuckꢀVoltageꢀRegulatorꢀwithꢀIntegratedꢀInductor

TDM3885

RevisionꢀHistory

TDM3885

Revision:ꢀ2022-07-20,ꢀRev.ꢀ2.3

Previous Revision

Revision Date

Subjects (major changes since last revision)

Initial release

2.0

2.1

2022-03-09

(1) Table 3, update Rth_JA = 40.5 °C/W, Psi_JT = 8.0°C/W, Psi_JB = 12.0°C/W. (2)

Update section 5.3 title, and table 6: Cff, Cout_min and Cout_max. (3) Add section 9.1,

Reflow guideline.

2022-04-29

2.2

2.3

Ordering information update. Tape & reel qty = 2500 units.

Fix page footer typo.

2022-07-06

2022-07-20

Trademarks

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aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare

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Rev.ꢀ2.3,ꢀꢀ2022-07-20

TDM3885 [INFINEON]

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TDN1-1210WI

TDN1-1210WISM

TDN1-1211WI

TDN1-1211WISM

TDN1-1212WI