TDA5240 [INFINEON]
看似矛盾的组合正是接收器设计所面临的日益严苛的要求：远距离、低能耗、灵活适应客户要求。您认为这需要投入大量开发精力，在设计中额外增加昂贵的器件？全新高灵敏度、低功率接收器系列 SmartLEWIS RX+ 帮您解决这一难题。SmartLEWIS RX+ 系列产品包括 TDA5240、TDA5235 和 TDA5225，需要极少外部器件即可满足所有要求。;
| 型号： | TDA5240 |
| 厂家： | 
Infineon |
| 描述： | 看似矛盾的组合正是接收器设计所面临的日益严苛的要求：远距离、低能耗、灵活适应客户要求。您认为这需要投入大量开发精力，在设计中额外增加昂贵的器件？全新高灵敏度、低功率接收器系列 SmartLEWIS RX+ 帮您解决这一难题。SmartLEWIS RX+ 系列产品包括 TDA5240、TDA5235 和 TDA5225，需要极少外部器件即可满足所有要求。 |
| 文件： | 总284页 (文件大小：13341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V4.0, February 2010
SmartLEWISTM RX+
TDA5240
Enhanced Sensitivity Multi-Channel
Quad-Configuration Receiver
with Digital Baseband Processing
Wireless Control
N e v e r s t o p t h i n k i n g .
Edition February 19, 2010
Published by Infineon Technologies AG,
Am Campeon 1 - 12
85579 Neubiberg, Germany
© Infineon Technologies AG February 19, 2010.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon Technologies
Representatives worldwide (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V4.0, February 2010
SmartLEWISTM RX+
TDA5240
Enhanced Sensitivity Multi-Channel
Quad-Configuration Receiver
with Digital Baseband Processing
Wireless Control
N e v e r s t o p t h i n k i n g .
TDA5240
Revision Number:
Revision History:
010
2010-02-19
V4.0
Previous Version:
Page
TDA5240_V3.4
Subjects (major changes since last revision)
Update of Figure 9
Page 27
Page 29
Update of Figure 10
Page 31
AFC limitation added
Page 33
AGC setting proposal added
Page 34
New Section 2.4.6.5 ADC added
Additional information on RSSIPRX register inserted
Signal and Noise Detector Procedure adapted
x_CDRRI register recommendation changed
Data Slicer Modes adapted; limitation added
Update of Figure 41
Page 36
Page 41
Page 45
Page 49, 52, 56
Page 69
Page 70
Update of Figure 42
Page 78
Additional hint on clock and data recovery algorithm of the user
software inserted
Page 84
PLDLEN limitation added
Page 86
Limitation for ISx readout and Burst-read function added
Limitation for Burst-read function added
Description of “Parallel Wake-up Search” adapted
Additional hints added
Page 88
Page 107
Page 125
Page 127
Page 130
Page 138 f
Page 138
Page 141 ff
Page 147
Adaption of Section 4.1
New item C7 added
Comments added for items I6, I7, I8, I9, J11, J12
Item J1 updated
General test conditions noted for parameters K, L and M
BOM components C7, C8, L1, R2 and R3 updated
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
Wirelesscontrol@infineon.com
TDA5240
Page
Table of Contents
1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
1.2
1.3
2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definition and Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RF/IF Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Crystal Oscillator and Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sigma-Delta Fractional-N PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PLL Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Digital Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ASK and FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ASK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Automatic Frequency Control Unit (AFC) . . . . . . . . . . . . . . . . . . . . . 28
Digital Automatic Gain Control Unit (AGC) . . . . . . . . . . . . . . . . . . . . 30
Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
RSSI Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Digital Baseband (DBB) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Filter and Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Encoding Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Slicer and Line Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Wake-Up Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Message ID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RUNIN, Synchronization Search Time and Inter-Frame Time . . . . . . 66
Power Supply Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chip Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Interfacing to the TDA5240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Digital Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Interrupt Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.6
2.4.6.1
2.4.6.2
2.4.6.3
2.4.6.4
2.4.6.5
2.4.7
2.4.8
2.4.8.1
2.4.8.2
2.4.8.3
2.4.8.4
2.4.8.5
2.4.8.6
2.4.8.7
2.4.8.8
2.4.9
2.4.9.1
2.4.9.2
2.5
2.5.1
2.5.1.1
2.5.1.2
2.5.2
2.5.3
2.5.4
Data Sheet
5
V4.0, 2010-02-19
TDA5240
Page
Table of Contents
2.5.5
2.5.5.1
2.5.6
2.6
2.6.1
Digital Control (4-wire SPI Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chip Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
System Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Master Control Unit (MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Run Mode Slave (RMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
HOLD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Self Polling Mode (SPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Automatic Modulation Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Multi-Channel in Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . 104
Run Mode Self Polling (RMSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Polling Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Self Polling Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Constant On-Off Time (COO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Fast Fall Back to SLEEP (FFB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Mixed Mode (MM, Const On-Off & Fast Fall Back to SLEEP) . . . . . 120
Permanent Wake-Up Search (PWUS) . . . . . . . . . . . . . . . . . . . . . . . 121
Active Idle Period Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition of Bit Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition of Manchester Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition of Power Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Symbols of SFR Registers and Control Bits . . . . . . . . . . . . . . . . . . . . 126
Digital Control (SFR Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SFR Address Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SFR Register List and Detailed SFR Description . . . . . . . . . . . . . . . . 127
2.6.1.1
2.6.1.2
2.6.1.3
2.6.1.4
2.6.1.5
2.6.1.6
2.6.1.7
2.6.1.8
2.6.2
2.6.2.1
2.6.2.2
2.6.2.3
2.6.2.4
2.6.2.5
2.6.2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.8.1
2.8.2
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.1
Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4
4.1
4.1.1
4.1.2
4.1.3
4.2
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Test Circuit - Evaluation Board v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Test Board Layout, Evaluation Board v1.0 . . . . . . . . . . . . . . . . . . . . . . . 155
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
4.3
4.4
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Appendix - Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Data Sheet
6
V4.0, 2010-02-19
TDA5240
Product Description
1
Product Description
1.1
Overview
The IC is a low power ASK/FSK Receiver for the frequency bands 300-320, 425-450,
863-870 and 902-928 MHz. Bi-phase modulation schemes, like Manchester, bi-phase
mark, bi-phase space and differential Manchester are supported.
The chip offers best-in-class sensitivity performance at a very high level of integration
and needs only a few external components.
The device is qualified to automotive quality standards and operates between -40 and
+105°C at supply voltage ranges of 3.0-3.6 Volts or 4.5-5.5 Volts.
The receiver is realized as a double down conversion super-heterodyne/low-IF
architecture each with image rejection supplemented by digital signal processing in the
baseband. A fully integrated Sigma-Delta Fractional-N PLL Synthesizer allows for high-
resolution frequency generation and uses a crystal oscillator as the reference. The on-
chip temperature sensor may be utilized for temperature drift compensation via the
crystal oscillator.
The digital baseband processing unit together with the high performance down converter
is the key element for the exceptional sensitivity performance of the device which take it
close to the theoretical top-performance limits. It comprises signal and noise detectors,
matched data filter, clock and data recovery, data slicer and a format decoder. It
demodulates the received ASK or FSK data stream independently and recovers the data
clock out of the received data stream with very fast synchronization times which can then
be either accessed via separate pins or used for further processing like frame
synchronization and intermediate storage in the on-chip FIFO. The RSSI output signal is
converted to the digital domain with an ADC. All these signals are accessible via the 4-
wire SPI interface bus. Up to 4 pre-configured telegram formats can be stored into the
device offering independent pre-processing of the received data to an extent not
available till now. The down converter can be also configured in single-conversion mode
at moderately reduced selectivity performance but at the advantage of omitting the IF
ceramic filter.
Data Sheet
7
V4.0, 2010-02-19
TDA5240
Product Description
1.2
Features
• Enhanced sensitivity receiver
• Multi-band/Multi-Channel (300-320, 425-450, 863-870 and 902-928 MHz)
• One crystal frequency for all supported frequency bands
• 21-bit Sigma-Delta Fractional-N PLL synthesizer with high resolution of 10.5 Hz
• Up to 4 parallel parameter sets for autonomous scanning and receiving from different
sources reduces significantly host processor power consumption and system
standby power consumption
• Up to 12 different frequency channels are supported with 10.5 Hz resolution each
• Autonomous receive mode leads to reduced noise of host processor and improved
system performance
• Ultrafast Wake-up on RSSI
• Fast synchronization on incoming data stream typically within first 4 bits of a telegram
• Selectable IF filter bandwidth and optional external filters possible
• Double down conversion image reject mixer
• ASK and FSK capability
• Automatic Frequency Control (AFC) for carrier frequency offset compensation
• Supports bi-phase line codes like Manchester, bi-phase mark/space and differential
Manchester
• NRZ data pre-processing capability
• Digital base band receiver with clock synch, frame synch, format decoding and FIFO
• Separate outputs for recovered data and clock
• RSSI peak detectors
• Wake-up generator and polling timer unit
• Message ID scanning
• Unique 32-bit serial number
• On-chip temperature sensor
• Integrated timer usable for external watch unit
• Integrated 4-wire SPI interface bus
• Supply voltage range 3.0 Volts to 3.6 Volts or 4.5 Volts to 5.5 Volts
• Operating temperature range -40 to +105°C
• ESD protection +/- 2 kV on all pins
• Package PG-TSSOP-28
1.3
Applications
• Remote keyless entry systems
• Remote start applications
• Tire pressure monitoring
• Short range radio data transmission
• Remote control units
• Cordless alarm systems
• Remote metering
Data Sheet
8
V4.0, 2010-02-19
TDA5240
Functional Description
2
Functional Description
2.1
Pin Configuration
IFBUF_IN
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IF_OUT
VDDA
RSSI
PP3
IFBUF_OUT
GNDA
3
IFMIX_INP
IFMIX_INN
VDD5V
VDDD
4
5
GNDRF
LNA_INP
LNA_INN
T2
6
7
TDA5240
VDDD1V5
GNDD
8
9
T1
PP0
10
11
12
13
14
SDO
PP1
SDI
PP2
SCK
P_ON
NCS
XTAL2
XTAL1
Figure 1
Pin-out
Data Sheet
9
V4.0, 2010-02-19
TDA5240
Functional Description
2.2
Pin Definition and Pin Functionality
Pin Definition and Function
Table 1
Pin Pad name
No.
Equivalent I/O Schematic
Function
1
2
IFBUF_IN
Analog input
IF Buffer input
VDDA
VDDA
330Ω
IFBUF
IFBUF_IN
IFMIX_INN
Note: Input is
biased at VDDA/2
VDDA
330Ω
MIX2BUF
IFBUF_OUT
Analog output
IF Buffer output
VDDA
VDDA
330Ω
IFBUF_OUT
IFBUF
GNDA
GNDA
3
4
GNDA
Analog ground
IFMIX_INP
Analog input
+ IF mixer input
VDDA
VDDA
Note: Input is
biased at VDDA/2
330Ω
IFMIX_INP
IFMIX_INN
MIX2BUF
5
6
IFMIX_INN
VDD5V
see schematic of Pin 1 and 4
Analog input.
- IF mixer input
Analog input
5 Volt supply input
Data Sheet
10
V4.0, 2010-02-19
TDA5240
Functional Description
Function
Pin Pad name
No.
Equivalent I/O Schematic
7
VDDD
Analog input
digital supply input
VDD5V
+
VReg
-
=
VDDD
VDDD
GNDD
8
VDDD1V5
Analog output
1.5 Volt voltage
regulator
+
VReg
-
=
VDD1V5
GNDD
9
GNDD
Digital ground
10 PP0
Digital output
CLK_OUT,
RX_RUN,
VDD5V
VDD5V
NINT, LOW, HIGH,
DATA,
PPx
SDO
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR (Special
Function Register),
default = CLK_OUT
GNDD
GNDD
Data Sheet
11
V4.0, 2010-02-19
TDA5240
Functional Description
Function
Pin Pad name
No.
Equivalent I/O Schematic
11 PP1
12 PP2
13 P_ON
see schematic of Pin 10
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR,
default = DATA
see schematic of Pin 10
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR,
default = NINT
Digital input
power-on reset
VDD5V
VDDD
P_ON
NCS
SCK
SDI
GNDD
GNDD
Data Sheet
12
V4.0, 2010-02-19
TDA5240
Functional Description
Function
Pin Pad name
No.
Equivalent I/O Schematic
14 XTAL1
Analog input
crystal oscillator
input
VDDD
VDDD
XTAL1
....
GNDD
GNDD
GNDD
15 XTAL2
Analog output
crystal oscillator
output
VDDD
VDDD
XTAL2
....
GNDD
GNDD
GNDD
16 NCS
17 SCK
18 SDI
19 SDO
20 T1
see schematic of Pin 13
see schematic of Pin 13
see schematic of Pin 13
see schematic of Pin 10
Digital input
SPI enable
Digital input
SPI clock
Digital input
SPI data in
Digital output
SPI data out
Digital input,
connect to Digital
Ground
21 T2
Digital input,
connect to Digital
Ground
Data Sheet
13
V4.0, 2010-02-19
TDA5240
Functional Description
Function
Pin Pad name
No.
Equivalent I/O Schematic
22 LNA_INN
Analog input
- RF input
LNA_INN
LNA
LNA
GNDRF
23 LNA_INP
Analog input
+ RF input
LNA_INP
GNDRF
24 GNDRF
25 PP3
RF analog ground
see schematic of Pin 10
Digital output
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR,
default = RX_RUN
26 RSSI
Analog output
analog RSSI output/
analog test pin
ANA_TST
VDDA
VDDA
500Ω
RSSI
GNDA
GNDA
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
Function
Pin Pad name
No.
Equivalent I/O Schematic
27 VDDA
Analog input
Analog supply
VDD5V
+
VReg
-
=
VDDA
GNDA
28 IF_OUT
Analog output
IF output
VDDA
VDDA
330Ω
IF_OUT
PPFBUF
GNDA
GNDA
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
2.3
Functional Block Diagram
IFMIX_INN (5)
)
E L S F E R C (
IFMIX_INP (4)
IFBUF_OUT (2)
IFBUF_IN (1)
IF_OUT (28)
GNDA (3)
Figure 2
TDA5240 Block Diagram1)
1) The function on each PPx port pin can be programmed via SFR (see also Table 1). Default values are given
in squared brackets in Figure 2.
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
2.4
Functional Block Description
Architecture Overview
2.4.1
A fully integrated Sigma-Delta Fractional-N PLL Synthesizer covers the frequency bands
300-320 MHz, 425-450 MHz, 863-870 MHz, 902-928 MHz with a high frequency
resolution, using only one VCO running at around 3.6 GHz. This makes the IC most
suitable for Multi-Band/Multi-Channel applications.
For Multi-Channel applications a very good channel separation is essential. To achieve
the necessary high sensitivity and selectivity a double down conversion super-
heterodyne architecture is used. The first IF frequency is located around 10.7 MHz and
the second IF frequency around 274 kHz. For both IF frequencies an adjustment-free
image frequency rejection feature is realized. In the second IF domain the filtering is
done with an on-chip third order bandpass polyphase filter. A multi-stage bandpass
limiter completes the RF/IF path of the receiver. For Single-Channel applications with
relaxed requirements to selectivity, a single down conversion low-IF scheme can be
selected.
For Multi-Channel systems where even higher channel separation is required, up to two
(switchable) external ceramic (CER) filters can be used to improve the selectivity.
An RSSI generator delivers a DC signal proportional to the applied input power and is
also used as an ASK demodulator. Via an anti-aliasing filter this signal feeds an ADC
with 10 bits resolution.
The harmonic suppressed limiter output signal feeds a digital FSK demodulator. This
block demodulates the FSK data and delivers an AFC signal which controls the divider
factor of the PLL synthesizer.
A digital receiver, which comprises RSSI peak detectors, a matched data filter, a clock
and data recovery, a data slicer, a frame synchronization and a data FIFO, decodes the
received ASK or FSK data stream. The recovered data and clock signals are accessible
via 2 separate pins. The FIFO data buffer is accessible via the SPI bus interface.
The crystal oscillator serves as the reference frequency for the PLL phase detector, the
clock signal of the Sigma-Delta modulator and divided by two as the 2nd local oscillator
signal. To accelerate the start up time of the crystal oscillator two modes are selectable:
a Low Power Mode (with lower precision) and a High Precision Mode.
Data Sheet
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TDA5240
Functional Description
2.4.2
Block Overview
The TDA5240 is separated into the following main blocks:
•
•
•
•
•
•
•
•
•
RF / IF Receiver
Crystal Oscillator and Clock Divider
Sigma-Delta Fractional-N PLL Synthesizer
ASK / FSK Demodulator incl. AFC, AGC and ADC
RSSI Peak Detector
Digital Baseband Receiver
Power Supply Circuitry
System Interface
System Management Unit
2.4.3
RF/IF Receiver
The receiver path uses a double down conversion super-heterodyne/low-IF architecture,
where the first IF frequency is located around 10.7 MHz and the second IF frequency
around 274 kHz. For the first IF frequency an adjustment-free image frequency rejection
is realized by means of two low-side injected I/Q-mixers followed by a second order
passive polyphase filter centered at 10.7 MHz (PPF). The I/Q-oscillator signals for the
first down conversion are delivered from the PLL synthesizer. The frequency selection
in the first IF domain is done by an external CER filter (optionally by two, decoupled by
a buffer amplifier). For moderate or low cost applications, this ceramic filter can be
substituted by a simple LC Pi-filter or completely by-passed using the receiver as a
single down conversion low-IF scheme with 274 kHz IF frequency. The down conversion
to the second IF frequency is done by means of two high-side injected I/Q-mixers
together with an on-chip third order bandpass polyphase filter (PPF2 + BPF). The I/Q-
oscillator signals for the second down conversion are directly derived by division of two
from the crystal oscillator frequency. The bandwidth of the bandpass filter (BPF) can be
selected from 50 kHz to 300 kHz in 5 steps. For a frequency offset of -150 kHz to -120
kHz, the AFC (Automatic Frequency Control) function is mandatory. Activated AFC
option might require a longer preamble sequence in the receive data stream.
The receiver enable signal (RX_RUN) can be offered at each of the port pins to control
external components. Whenever the receiver is active, the RX_RUN output signal is
active. Active high or active low is configurable via PPCFG2 register.
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
The frequency relations are calculated with the following formulas:
fIF1 = 10.7MHz
fIF1
fIF2 = --------
39
fcrystal = fIF2 × 80
fcrystal
fLO2 = ----------------
2
fLO1 = fcrystal × NFdivider
RX
FSK Data
I-Mix
I-
Mix2
LP
harm sup
digital
FSK Demod
CER-
Filter
IF1
CER-
RX
Input
Filter IF1
10.7 MHz
optional
LNA
RX
ASK Data
ASK /
RSSI
ADC
10.7 MHz
LP
alias sup
Q-
Mix2
RSSI Generator
Q-Mix
Divider
: N
IF
IQ :2
Attenuation
adjust
Channel Filter
Bandwidth select
AFC
Filter
N
ΣΔ Modulator
Channel select
Crystal
oscil-
lator
Band select
Multi Modulos
Divider : N_FN
VCO
:1/:2/:3
IQ Divider : 4
PD
Channel select
LF select
Front end
control unit
Channel Filter select
IF Attenuation adjust
RSSI Gain/Offset adjust
Band select
Loop
Filter
LF select
Figure 3
Block Diagram RF Section
The front end of the receiver comprises an LNA, an image reject mixer and a digitally
gain controlled buffer amplifier. This buffer amplifier allows the production spread of the
on-chip signal strip, of external matching circuitry and RF SAW and ceramic IF filters to
be trimmed. The second image reject mixer down converts the first IF to the second IF.
Data Sheet
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TDA5240
Functional Description
The bandpass filter follows the subsequent formula:
fcenter
=
fcorner, low × fcorner, high
Therefore asymmetric corner frequencies can be observed. The use of AFC results in
more symmetry.
A multi-stage bandpass limiter at a center frequency of 274 kHz completes the receiver
chain. The -3dB corner frequencies of the bandpass limiter are typically at 75 kHz and
at 520 kHz.
An RSSI generator delivers a DC signal proportional to the applied input power and is
also used as an ASK demodulator. Via a programmable anti-aliasing filter this signal is
converted to the digital domain by means of a 10-bit ADC.
The limiter output signal is connected to a digital FSK demodulator.
The immunity against strong interference frequencies (so called blockers) is determined
by the available filter bandwidth, the filter order and the 3rd order intercept point of the
front end stages. For Single-Channel applications with moderate requirements to the
selectivity the performance of the on-chip 3rd order bandpass polyphase filter might be
sufficient. In this case no external filters are necessary and a single down conversion
architecture can be used, which converts the input signal frequency directly to the 2nd IF
frequency of 274 kHz.
RX
I-Mix
FSK Data
I-
LP
harm sup
digital
FSK Demod
Mix2
RX
Input
LNA
RX
ASK Data
ASK /
RSSI
ADC
LP
alias sup
Q-
Mix2
RSSI Generator
Q-Mix
IF
Divider
: N
Attenuation
adjust
Channel Filter
Bandwidth select
1st LO
2
nd LO
Figure 4
Single Down Conversion (SDC, no external filters required)
For Multi-Channel applications or systems which demand higher selectivity the double
down conversion scheme together with one or two external CER filters can be selected.
The order of such ceramic filters is in a range of 3, so the selectivity is further improved
and a better channel separation is guaranteed.
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
RX
I-Mix
FSK Data
I-
LP
harm sup
digital
FSK Demod
Mix2
CER-
Filter
RX
Input
LNA
IF1
10.7 MHz
RX
ASK Data
ASK /
RSSI
ADC
LP
alias sup
Q-
Mix2
RSSI Generator
Q-Mix
IF
Divider
: N
Attenuation
adjust
Channel Filter
Bandwidth select
1st LO
2nd LO
Figure 5
Double Down Conversion (DDC) with one external filter
For applications which demand very high selectivity and/or channel separation even two
CER filters may be used. Also in applications where one channel requires a wider
bandwidth than the other (e.g. TPMS and RKE) the second filter can be by-passed.
RX
FSK Data
I-Mix
I-
LP
harm sup
digital
FSK Demod
Mix2
CER-
Filter
CER-
RX
Input
Filter IF1
10.7 MHz
optional
LNA
IF1
10.7 MHz
RX
ASK Data
ASK /
RSSI
ADC
LP
alias sup
Q-
Mix2
RSSI Generator
Q-Mix
Divider
: N
IF
Attenuation
adjust
Channel Filter
Bandwidth select
1st LO
2nd LO
Figure 6
Double Down Conversion (DDC) with two external filters
Data Sheet
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TDA5240
Functional Description
2.4.4
Crystal Oscillator and Clock Divider
The crystal oscillator is a Pierce type oscillator which operates together with the crystal
in parallel resonance mode. An automatic amplitude regulation circuitry allows the
oscillator to operate with minimum current consumption. In SLEEP Mode, where the
current consumption should be as low as possible, the load capacitor must be small and
the frequency is slightly detuned, therefore all internal trim capacitors are disconnected.
The internal capacitors are controlled by the crystal oscillator calibration registers
XTALCALx. With a binary weighted capacitor array the necessary load capacitor can be
selected.
Whenever a XTALCALx register value is updated, the selected trim capacitors are
automatically connected to the crystal so that the frequency is precise at the desired
value. The SFR control bit XTALHPMS can be used to activate the High Precision Mode
also during SLEEP Mode.
fsys
Setting
automatically
controlled
XTALCAL0
XTALCAL1
9
( ≤ 1pF steps )
(DGND)
XTALHPMS
Oscillator-Core
XTAL1
XTAL2
Figure 7
Crystal Oscillator
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
Recommended Trimming Procedure
• Set the registers XTALCAL0 and XTALCAL1 to the expected nominal values
• Set the TDA5240 to Run Mode Slave
• Wait for 0.5ms minimum
• Trim the oscillator by increasing and decreasing the values of XTALCAL0/1
• Register changes larger than 1 pF are automatically handled by the TDA5240 in 1pF
steps
• After the Oscillator is trimmed, the TDA5240 can be set to SLEEP mode and keeps
these values during SLEEP mode
• Add the settings of XTALCAL0/1 to the configuration. It must be set after every power
up or brownout!
Using the High Precision Mode
As discussed earlier, the TDA5240 allows the crystal oscillator to be trimmed by the use
of internal trim capacitors. It is also possible to use the trim functionality to compensate
temperature drift of crystals.
During Run Mode (always when the receiver is active) the capacitors are automatically
connected and the oscillator is working in the High Precision Mode.
On entering SLEEP Mode, the capacitors are automatically disconnected to save
power.
If the High Precision Mode is also required for SLEEP Mode, the automatic disconnec-
tion of trim capacitors can be avoided by setting XTALHPMS to 1 (enable XTAL High
Precision Mode during SLEEP Mode).
External Clock Generation Unit
A built in programmable frequency divider can be used to generate an external clock
source out of the crystal reference. The 20 bit wide division factor is stored in the
registers CLKOUT0, CLKOUT1 and CLKOUT2. The minimum value of the
programmable frequency divider is 2. This programmable divider is followed by an
additional divider by 2, which generates a 50% duty cycle of the CLK_OUT signal. So
the maximum frequency at the CLK_OUT signal is the crystal frequency divided by 4.
The minimum CLK_OUT frequency is the crystal frequency divided by 221.
To save power, this programmable clock signal can be disabled by the SFR control bit
CLKOUTEN. In this case the external clock signal is set to low.
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
The resulting CLK_OUT frequency can be calculated by:
fsys
fCLKOUT = --------------------------------------------
2 ⋅ divisionfactor
Enable
Enable
fsys
2 x fCLK_OUT
fCLK_OUT
Divide
by 2
20 Bit Counter
Figure 8
External Clock Generation Unit
The maximum CLK_OUT frequency is limited by the driver capability of the PPx pin and
depends on the external load connected to this pin. Please be aware that large loads
and/or high clock frequencies at this pin may interfere with the receiver and reduce
performance.
After Reset the PPx pin is activated and the division factor is initialized to 11 (equals
fCLK_OUT = 998 kHz).
A clock output frequency higher than 1 MHz is not supported.
For high sensitivity applications, the use of the external clock generation unit is not
recommended.
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
2.4.5
Sigma-Delta Fractional-N PLL Block
The Sigma-Delta Fractional-N PLL is fully integrated on chip. The Voltage Controlled
Oscillator (VCO) with on-chip LC-tank runs at approximately 3.6 GHz and is first divided
with a band select divider by 1, 2 or 3 and then with an I/Q-divider by 4 which provides
an orthogonal local oscillator signal for the first image reject mixer with the necessary
high accuracy.
The multi-modulus divider determines the channel selection and is controlled by a
3rd order Sigma-Delta Modulator (SDM). A type IV phase detector, a charge pump with
programmable current and an on-chip loop filter closes the phase locked loop.
To 1st mixer
3.6 GHz VCO Loop Filter
CP
IQ Divider
÷ 4
Band Select
÷1/÷2/÷3
Multi-
modulus
Divider
PFD
ΣΔ Modulator
Channel FN
QOSC
22MHz
AFC filter
AFC-data
Figure 9
Synthesizer Block Diagram
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
When defining a Multi-Channel system, the correct selection of channel spacing
is extremely important. A general rule is not possible, but following must be con-
sidered:
• If an additional SAW filter is used, all channels including their tolerances have to be
inside the SAW filter bandwidth.
• The distance between channels must be high enough, that no overlapping can occur.
Strong input signals may still appear as recognizable input signal in the neighboring
channel because of the limited suppression of IF Filters. Example: a typical 330kHz IF
filter has at 10.3 MHz ( 10.7 MHz - 0.4 MHz ) only 30 dB suppression. A -70 dBm input
signal appears like a -100 dBm signal, which is inside the receiver sensitivity. In critical
cases the use of two IF filters must be considered. See also Chapter 2.4.3 RF/IF
Receiver.
2.4.5.1 PLL Dividers
The divider chain consists of a band select divider 1/2/3, an I/Q-divider by 4 which
provides an orthogonal 1st local oscillator signal for the first image reject mixer with the
necessary high accuracy and a multi-modulus divider controlled by the Sigma-Delta
Modulator. With the band select divider, the wanted frequency band is selected. Divide
by 1 selects the 915 MHz and 868 MHz band, divide by 2 selects the 434 MHz band and
divide by 3 selects the 315 MHz band. The ISM band selection is done via bit group
BANDSEL in x_PLLINTC1 register.
2.4.5.2 Digital Modulator
The 3rd order Sigma-Delta Modulator (SDM) has a 22 bit wide input word, however the
LSB is always high, and is clocked by the XTAL oscillator. This determines the
achievable frequency resolution.
The Automatic Frequency Control Unit filters the actual frequency offset from the FSK
demodulator data and calculates the necessary correction of the divider factor to achieve
the nominal IF center frequency.
Data Sheet
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TDA5240
Functional Description
2.4.6
ASK and FSK Demodulator
AFC track/freeze
AFC
RF PLL ctrl
loop filter
B = 50..300kHz
image suppression /
band limitation (noise)
FSK/ASK
Rate adapter
channel filter FM limiter
FSK
Demodulated
Data
PPF2
BP
Bypass
Rate doubler
Decimation
33 / 46 / 65 / 93 / 132 /
190 / 239 / 282 kHz
(2sided PDF BW)
2nd
conversion
RSSI
8 … 16 samples/chip
(data rate dependent )
Temp
VDDD/2
delog
AGC
RSSI Slope
RSSI Offset
Dig. Gain
Control
Peak Memory
Mux
ADC
Filter
ASK
Div
Analog Gain Control
buffer
RSSI Peak
Detector
register
fSystem
RSSIPMF
register
RSSIPWU
register
RSSI
End of config/
channel
RSSIPWU
(internal
signal)
>
WU event
Begin of config/
channel ,
TH, BL, BH
x*WULOT
Figure 10
Functional Block Diagram ASK/FSK Demodulator
The IC comprises two separate demodulators for ASK and FSK.
After combining FSK and ASK data path, a sampling rate adaptation follows to meet an
output oversampling between 8 and 16 samples per chip. Finally, an oversampling of 8
samples per chip can be achieved using a fractional sample rate converter (SRC) with
linear interpolation (for further details see Figure 15).
2.4.6.1 ASK Demodulator
The RSSI generator delivers a DC signal proportional to the applied input power at a
logarithmic scale (dBm) and is also used as an ASK demodulator. Via a programmable
anti-aliasing filter this signal is converted to the digital domain by means of a 10-bit ADC.
For the AM demodulation a signal proportional to the linear power is required. Therefore
a conversion from logarithmic scale to linear scale is necessary. This is done in the digital
domain by a nonlinear filter together with an exponential function. The analog RSSI
signal after the anti-aliasing filter is available at the RSSI pin via a buffer amplifier. To
enable this buffer the SFR control bit RSSIMONEN must be set. The anti-aliasing filter
can be by-passed for visualization on the RSSI pin (see AAFBYP control bit).
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
2.4.6.2 FSK Demodulator
The limiter output signal, which has a constant amplitude over a wide range of the input
signal, feeds the FSK demodulator. There is a configurable lowpass filter in front of the
FSK demodulation to suppress the down conversion image and noise/limiter harmonics
(FSK Pre-Demodulation Filter, PDF). This is realized as a 3rd order digital filter. The
sampling rate after FSK demodulation is fixed and independent from the target data rate.
2.4.6.3 Automatic Frequency Control Unit (AFC)
In front of the image suppression filter a second FSK demodulator is used to derive the
control signal for the Automatic Frequency Control Unit, which is actually the DC
value of the FSK demodulated signal. This makes the AFC loop independent from signal
path filtering and allow so a wider frequency capture range of the AFC. The derivation of
the AFC control signal is preferably done during the DC free preamble and is then frozen
for the rest of the datagram.
Since the digital FSK demodulator determines the exact frequency offset between the
received input frequency and the programmed input center frequency of the receiver,
this offset can be corrected through the sigma delta control of the PLL. As shown in
Figure 10, for AFC purposes a parallel demodulation path is implemented. This path
does not contain the digital low pass filter (PDF, Pre-Demodulation Filter). The entire IF
bandwidth, filtered by the analog bandpass filter only, is processed by the AFC
demodulator.
There are two options for the active time of the AFC loop:
• 1. always on
• 2. active for a programmable time relative to a signal identification event (several
options can be programmed in SFR).
In the latter case the AFC can either be started or frozen relative to the signal
identification. After the active time the offset for the sigma-delta PLL (SD PLL) is frozen.
The programming of the active time is especially necessary in case the expected frame
structure contains a gap (noise) between wake-up and payload in order to avoid the AFC
from drifting.
AFC works both for FSK and ASK. In the latter case the AFC loop only regulates during
ASK data = high.
The maximum frequency offset generated by the AFC can be limited by means of the
x_AFCLIMIT register. This limit can be used to avoid the AFC from drifting in the
presence of interferers or when no RF input signal is available (AFC wander). A
maximum AFC limit of 42 kHz is recommended. AFC wandering needs to be kept in mind
especially when using Run Mode Slave.
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
K1 = integrator1 gain
x_AFCLIMIT
x_AFCK1CFG0/1
integrator 1
SDPLL
scaling &
limiting
FreqOffset
AFC Demod out
limit
K1
x16
HOLD
integrator2
hold
limit
hold
K2
x4
Freeze* / Track
Delay
x_AFCK2CFG0/1
x_AFCAGCD
K2 = integrator 2 gain
Figure 11
AFC Loop Filter (I-PI Filtering and Mapping)
The bandwidth (and thus settling time) of the loop is programmed by means of the
integrator gain coefficients K1 and K2 (x_AFCK1CFG and x_AFCK2CFG register).
K1 mainly determines the bandwidth. K2 influences the dynamics/damping (overshoot)
- smaller K2 means smaller overshoot, but slower dynamics. The bandwidth of the AFC
loop is approximately 1.3*K1.
To avoid residual FM, limiting the AFC BW to 1/20 ~ 1/40 of the bit rate is suggested,
therefore K1 must be set to approximately 1/50 ~ 1/100 of the bit rate. For most
applications K2 can be set equal to K1 (overshoot is then <25%).
When very fast settling is necessary K1 and K2 can be increased up to bit rate/10,
however, in this case approximately 1dB sensitivity loss is to be expected due to the AFC
counteracting the input FSK signal.
AFC limitation at Local Oscillator (LO) frequencies at multiples of reference frequency
(f_xtal). When AFC is activated and AFC drives the wanted LO frequency over the
integer limit of Sigma Delta (SD) modulator, the SD modulator stucks at frac=1.0 or
frac=0.0 due to saturation. So when AFC can change the integer value for the LO
(register x_PLLINTCy) within the frequency range LO-frequency +/- AFC-limit, a change
of the LO injection side or a smaller AFC-limit is recommended.
The frequency offset found by AFC (AFC loop filter output) can be readout via register
AFCOFFSET, when AFC is activated. The value is in signed representation and has a
frequency resolution of 2.68 kHz/digit. The output can be limited by the x_AFCLIMIT
register.
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
2.4.6.4 Digital Automatic Gain Control Unit (AGC)
Automatic Gain Control (AGC) is necessary mainly because of the limited dynamic range
of the on-chip bandpass filter (BPF). The dynamic range reduces to less than 60dB in
case of minimum BPF bandwidth.
AGC is used to cover the following cases:
1. ASK demodulation at large input signals
2. RSSI reading at large input signals
3. Improve IIP3 performance in either FSK or ASK mode
The 1st IF buffer (PPFBUF, see Figure 3) can be fine tuned "manually" by means of 4
bits thus optimizing the overall gain to the application (attenuation of 0dB to -12dB by
means of IFATT0 to IFATT15 in DDC mode; SDC mode has lower IFATT range). This
buffer allows the production spread of external components to be trimmed.
The gain of the 2nd IF path is set to three different values by means of an AGC algorithm.
Depending on whether the receiver is used in single down conversion or in double down
conversion mode the gain control in the 2nd IF path is either after the 2nd poly-phase
network or in front of the 2nd mixer.
The AGC action is illustrated in the RSSI curve below:
Analog (blue) &
digital (black )
RSSI output
Mixer2
saturation
BPF bypassed
AGC OFF
Max. B W
BPF
saturation
Min. B W
AGC ON
margin
Analog AGC
attack point
hysteresis
Analog AGC
decay point
Max. B W
Max. FE gain
(IFATT 0)
Front-end
Min. B W
noise x gain
Min. FE gain
(IFATT 15)
Limiter
noise floor
Input power
Figure 12
Analog RSSI output curve with AGC action ON (blue) vs. OFF (black)
Data Sheet
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V4.0, 2010-02-19
TDA5240
Functional Description
Digital RSSI, AGC and Delog:
In order to match the analog RSSI signal to the digital RSSI output a correction is
necessary. It adds an offset (RSSIOFFS) and modifies the slope (RSSISLOPE) such
that standardized AGC levels and an appropriate DELOG table can be applied.
Upon entering the AGC unit the digital RSSI signal is passed through a Peak Memory
Filter (PMF). This filter has programmable up and down integration time constants
(PMFUP, PMFDN) to set attack respectively decay time. The integration time for decay
time must be significantly longer than the attack time in order to avoid the AGC interfering
with the ASK modulation.
The integrator is followed by two digital Schmitt triggers with programmable thresholds
(AGCTLO; AGCTUP) - one Schmitt trigger for each of the two attack thresholds (two
digital AGC switching points). The hysteresis of the Schmitt triggers is programmable
(AGCHYS) and sets the decay threshold. The Schmitt triggers control both the analog
gain as well as the corresponding (programmable) digital gain correction (DGC).
The difference ("error") signal in the PMF is actually a normalized version of the
modulation. This signal is then used as input for the DELOG table.
AGC threshold programming
The SFR description for the AGC thresholds are in dBs. The first value to set is the AGC
threshold offset in AGCTHOFFS.
This value is the offset relative to 0 input (no noise, no signal), which for the default
setting of gain, and assuming typical insertion loss of matching network and ceramic
filter, can be extrapolated to be approximately -143dBm.
In this case the default setting of the AGCTHOFFS of 63.9dB corresponds to an input
power of approximately -79dBm (= -143dBm + 63.9dB).
The low (digital) AGC threshold is then -79 + 12.8dB (default AGCTLO) = -66dBm and
the upper (digital) AGC threshold is -79 + 25.6 (default AGCTUP) = -53dBm.
Therefore a margin of about 6dB is indicated before a degradation of the linearity of the
2nd IF can be observed when using the 50kHz BPF or even about 16dB when using the
300kHz BPF.
The input power level at which the AGC switches back to maximum gain is -66dBm -
21.3dB (default AGCHYS) = -87dBm. This provides enough margin against the minimum
sensitivity.
Data Sheet
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Functional Description
When AGC is activated, RSSI is untrimmed, IFATT <= 5.6dB and the same RSSI offset
should be applied for all bandpass filter settings, then the settings in Table 2 can be
applied, where a small reduction of the RSSI input range can be observed.
Table 2
AGC Settings 1
AGC Threshold Hysteresis = 21.3 dB
AGC Digital RSSI Gain Correction = 15.5 dB
BPF
RSSI Offset
AGC
AGC
AGC
RSSI Input
Range
Reduction
Compensation Threshold Threshold Threshold
(untrimmed) 1)
Offset
63.9 dB
63.9 dB
63.9 dB
51.1 dB
51.1 dB
Low
Up
300 kHz
200 kHz
125 kHz
80 kHz
32
32
32
32
32
8
4
5 dB
5 dB
6
2
5
0
5 dB
11
9
6
2.8 dB
0 dB
50 kHz
5
1) Note: This value needs to be used for calculating the register value
For the full RSSI input range, the values in Table 3 can be applied.
Table 3
AGC Settings 2
AGC Threshold Hysteresis = 21.3 dB
AGC Digital RSSI Gain Correction = 15.5 dB
BPF
RSSI Offset
AGC
AGC
AGC
Compensation Threshold Threshold Threshold
(untrimmed) 1)
Offset
63.9 dB
51.1 dB
51.1 dB
51.1 dB
51.1 dB
Low
Up
300 kHz
200 kHz
125 kHz
80 kHz
-18
-18
-18
4
5
1
11
10
9
7
5
5
50 kHz
32
9
5
1) Note: This value needs to be used for calculating the register value
Data Sheet
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Functional Description
Attack and Decay coefficients PMF-UP & PMF-DOWN:
The settling time of the loop is determined by means of the integrator gain coefficients
PMFUP and PMFDN, which need to be calculated from the wanted attack and decay
times.
The ADC is running at a fixed sampling frequency of 274kHz. Therefore the integrator is
integrating with PMFUP*274k per second, i.e. time constant is 1/(PMFUP*274k). The
attack times are typically 16 times faster than the decay times.
Typical calculation of the coefficients by means of an example:
• PMFUP = 2^-round( ln(AttTime / BitRate * 274kHz) / ln(2) )
• PMFDN = 2^-round( ln(DecTime / BitRate * 274kHz) / ln(2) ) / PMFUP
where AttTime, DecTime = attack, decay time in number of bits
Note: PMFDN = overall_PMFDN / PMFUP
Example:
BitRate = 2kbps
AttTime = 0.1 bits
=> PMFUP = 2^-round(ln(0.1bit/2kbps*274kHz)/ln(2)) = 2^-round(3.8) = 2^-4
DecTime = 2 bits
=> PMFDN = 2^-round(ln(2bit/2kbps*274kHz)/ln(2))/PMFUP = 2^-round(8.1)/2^-4 = 2^-4
Note: In case of ASK with large modulation index the attack time (PMFUP) can be up to
a factor 2 slower due to the fact that the ASK signal has a duty cycle of 50% - during the
ASK low duration the integrator is actually slightly discharged due to the decay set by
PMFDN.
The AGC start and freeze times are programmable. The same conditions can be used
as in the corresponding AFC section above. They will however, be programmed in
separate SFR registers.
Data Sheet
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Functional Description
2.4.6.5 Analog to Digital Converter (ADC)
In front of the AD converter there is a multiplexer so that also temperature and VDDD
can be measured (see Figure 10).
The default value of the ADC-MUX is RSSI (register ADCINSEL: 000 for RSSI; 001 for
Temperature; 010 for VDDD/2).
After switching ADC-MUX to a value other than RSSI in SLEEP Mode, the internal
references are activated and this ADC start-up lasts 100µs. So after this ADC start-up
time the readout measurements may begin. The chip stays in this mode until
reconfiguration of register ADCINSEL to setting RSSI. However, it is recommended to
measure temperature during SLEEP mode (This is also valid for VDDD).
Readout of the 10-bit ADC has to be done via ADCRESH register (the lower 2 bits in
ADCRESL register can be inconsistent and should not be used).
Typical the ADC refresh rate is 3.7 µs. Time duration between two ADC readouts has to
be at least 3.7 µs, so this is already achieved due to the maximum SPI rate (16 bit for
SPI command and address last 8µs at an SPI rate of 2MBit/s). The EOC bit (end of
conversion) indicates a successful conversion additionally. Repetition of the readout
measurement for several times is for averaging purpose.
The input voltage of the ADC is in the range of 1 .. 2 V. Therefore VDDD/2 (= 1.65 V
typical) is used to monitor VDDD.
Further details on the measurement and calibration procedure for temperature and
VDDD can be taken from the corresponding application note.
Data Sheet
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Functional Description
2.4.7
RSSI Peak Detector
The IC possesses several digital RSSI peak level detectors. The RSSI level is averaged
over 4 samples before it is fed to any of the peak detectors. This prevents the evaluated
peak values to be dominated by single noise peaks.
fsys
EOM
Compare
Update
Update
Peak
Value
Peak Value
Register
Peak Detector
Payload
RSSIPPL
ADC Sampling
Clock Generation
Load
FSYNC
Divide
by 4
Peak
Detector
Track
fADC
fADC/4
Control
Bit
position
Integrate
Dump
A
RSSI Slope
RSSI Offset
RSSI
I&D Averaging Filter
Compare
Update
D
from
RSSI
Generator
Peak-
Value
RSSIPRX
Peak Detector
Load
to
ASK path
RX_RUN
from
FSM
&
from
SPI Controller
Read Access to
Register RSSIPRX
RSSIRX
Figure 13
Peak Detector Unit
Peak Detector Payload is used to measure the input signal power of a received and
accepted data telegram. It is read via SFR RSSIPPL.
Observation of the RSSI signal starts at the detection of a TSI (FSYNC) and ends with
the detection of EOM. The internal RSSIPPL value is cleared after FSYNC. The
evaluated RSSI peak level RSSIPPL is transferred to the RSSIPPL register at EOM.
Starting the observation of the RSSI level can be delayed by a selectable number of data
bits and is controlled by the register x_PKBITPOS. A latency in the generation of FSYNC
and EOM of approx. 2..3 bits in relation to the contents of the Peak Detector must be
considered. Within the boundaries described, the register RSSIPPL always contains the
peak value of the last completely received data telegram. The register RSSIPPL is reset
to 0 at power up reset only.
Peak Detector is used to measure RSSI independent of a data transfer and to digitally
trim RSSI. It is read via SFR RSSIPRX.
Observation of the RSSI signal is active whenever the RX_RUN signal is high. The
RSSIPRX register is refreshed and the Peak Detector is reset after every read access to
RSSIPRX.
It may be required to read RSSIPRX twice to obtain the required result. This is because,
for example, during a trim procedure in which the input signal power is reduced, after
Data Sheet
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Functional Description
reading RSSIPRX, the peak detector will still hold the higher RSSI level. After reading
RSSIPRX the lower RSSI level is loaded into the Peak Detector and can be read by
reading RSSIPRX again.
Register RSSIPRX should not be read-out faster than 41µs in case AGC is ON (as
register value would not represent the actual, but a lower value).
When the RX_RUN signal is inactive, a read access has no influence to the peak
detector value. The register RSSIPRX is reset to 0 at power up reset.
Peak Detector Wake-Up RSSIPWU (see Figure 10) is used to measure the input signal
power during Wake-Up search. The internal signal RSSIPWU gets initialized to 0 at start
of the first observation time window at the beginning of each configuration/channel. The
peak value of this signal is tracked during Wake-Up search.
In case of a Wake-Up, the actual peak value is written in the RSSIPWU register. Even
in case no Wake-Up occurred, actual peak value is written in the RSSIPWU register at
the end of the actual configuration/channel of the Self Polling period. So if no Wake-Up
occurred, then the RSSIPWU register contains the peak value of the last
configuration/channel of the Self Polling period, even in a Multi-Configuration/Multi-
Channel setup. This functionality can be used to track RSSI during unsuccessful Wake-
Up search due to no input signal or due to blocking RSSI detection.
For further details please refer to Chapter 2.4.8.5 Wake-Up Generator and
Chapter 2.6.2 Polling Timer Unit.
Input
Data Pattern
Dn
-1
Dn Dn Dn
+1 +2 +3
Run-In
Run-In
TSI D0 D1
Noise
TSI D0 D1
Dn
EOM
Noise
....
....
....
SPI read out
RSSIPPL&RSSIPRX
internal RSSIPPL
RSSIPPL Register
internal RSSI
FSYNC clears the
internal RSSIPPL
internal RSSIPRX =
RSSIPRX Register
internal RSSI
*1
*1
*1
*1
SPI
Reset
FSync
n = PKBITPOS
EOM
FSync
*1 Computation Delay due to filtering and signal calculation.
Figure 14
Peak Detector Behavior
Data Sheet
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Functional Description
Recommended Digital Trimming Procedure
• Download configuration file (Run Mode Slave; RSSISLOPE, RSSIOFFS set to
default, i.e. RSSISLOPE=1, RSSIOFFS=0)
• Turn off AGC (AGCSTART=0) and set gain to AGCGAIN=0
• Apply PIN1 = -85 dBm RF input signal
• Read RSSIRX eleven times (minimum 10 ms in-between readings), use average of
last ten readings (always), store as RSSIM1
• Apply PIN2 = -65 dBm RF input signal
• Read RSSIRX eleven times (minimum 10 ms in-between readings), use average of
last ten readings (always), store as RSSIM2
• Calculate measured RSSI slope SLOPEM=(RSSIM2-RSSIM1)/(PIN2-PIN1)
• Adjust RSSISLOPE for required RSSI slope SLOPER as follows:
RSSISLOPE=SLOPER/SLOPEM
• Adjust RSSIOFFS for required value RSSIR2 at PIN2 as follows:
RSSIOFFS=(RSSIR2-RSSIM2)+(SLOPEM-SLOPER)*PIN2
• The new values for RSSISLOPE and RSSIOFFS have to be added to the
configuration!
Notes:
1. The upper RF input level must stay well below the saturation level of the receiver (see
Chapter 2.4.6.4 Digital Automatic Gain Control Unit (AGC))
2. The lower RF input level must stay well above the noise level of the receiver
3. If IF Attenuation is trimmed, this has to be done before trimming of RSSI
4. If RSSI needs to be trimmed in a higher input power range the AGCGAIN must be set
accordingly
Data Sheet
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Functional Description
2.4.8
Digital Baseband (DBB) Receiver
Blind Sync
Initial Phase & Data rate
CDR PLL
FSK
detector
CR PLL
Slicer
sync
chip_data_clock
CH_STR
adjust_length
SRC
bypass
8 to 16
samples
per chip
Matched Filter
Chip
Data
Invert
chip_data
Signal
Detector
Data
Slicer
Chip Data
Decoder
CH_DATA
fractional SRC
From ASK/
FSK
fsout / fsin = 0.5 … 1.0
Demodulator
CHIPDINV
Decoder
MUX
RAW Data Slicer
for external
processing
data_clk
data
SIGN
Data
eom
FIFO
Framer
(TSI Detector)
fsync
wakeup
WU Unit
Data
Invert
DINVEXT
Invert
RXSTR RXD
DATA
(Sliced RAW Data for
external processing)
DATA_MATCHFIL
(Matched Filtered Data
for external processing )
Figure 15
Functional Block Diagram Digital Baseband Receiver
The digital baseband receiver comprises a matched data filter, a clock and data
recovery, a data slicer, a line decoder, a wake-up generator, a frame synchronization
and a data FIFO. The recovered data and clock signals are accessible via 2 separate
pins. The FIFO data buffer is accessible via the SPI bus interface.
2.4.8.1 Data Filter and Signal Detection
The data filter is a matched filter (MF). The frequency response of a matched filter has
ideally the same shape as the power spectral density (PSD) of the originally transmitted
signal, therefore the signal-to-noise ratio (SNR) at the output of the matched filter
becomes maximum. The input sampling rate of the baseband receiver has to be
between 8 and 16 samples per chip. The oversampling factor within this range is
depending on the data rate (see Figure 10). The MF has to be adjusted accordingly to
this oversampling. After the MF a fractional sample rate converter (SRC) is applied using
linear interpolation. Depending on the data rate decimation is adjusted within the range
1...2. Finally, at the output of the fractional SRC the sampling rate is adjusted to 8
samples per chip for further processing.
To distinguish whether the incoming signal is really a signal or only noise adequate
detectors for ASK and FSK are built in.
Data Sheet
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Functional Description
Signal and Noise Detector
The Signal Detector decides between acceptable and unacceptable data (e.g. noise).
This decision is taken by comparing the signal power of the actually received data
(register SPWR) with a configurable threshold level (registers x_SIGDET0/1), which
must be evaluated. In case the actual signal power is above the threshold, acceptable
data has been detected.
To decide in case of FSK whether there is a data signal or simply noise at the output of
the rate adapter, there is a Noise Detector implemented. The principle is based on a
power measurement of the demodulated signal. The current noise power is stored in the
NPWR register and is updated at every SPI controller access. The Noise Detector is
useful if data signal is transmitted with small FSK deviations. In case the current noise
power (register NPWR) is below the configurable threshold (register x_NDTHRES), a
data signal has been detected.
The Signal Recognition mode must be configured based on whether ASK or FSK
modulation is used. Signal Recognition can be a combination of Signal Detector and
Noise Detector:
• Signal Detector (=Squelch) only (related registers: x_SIGDET0, x_SIGDET1 and
SPWR). This mode is generally used for ASK and recommended for FSK.
• Noise Detector only (related registers: x_NDTHRES and NPWR).
• Signal and Noise Detector simultaneously.
• Signal and Noise Detector simultaneously, but the FSK noise detect signal is valid
only if the x_SIGDETLO threshold is exceeded. This is the recommended FSK mode,
if minimum FSK deviation is not sufficient to use Signal Detector only.
Signal Recognition can also be used as Wake-up on Level criterion (see
Chapter 2.4.8.5).
Figure 16 shows the system characteristics to consider in choosing the best Signal
Detector level. On the one hand, a higher SIGDET threshold level must be set for
achieving good FAR (False Alarm Rate) performance, but then the MER/BER (Message
Error Rate/Bit Error Rate) performance will decrease. On the other hand, the MER/BER
performance can be increased by setting smaller SIGDET threshold levels but then the
FAR performance will worsen.
Data Sheet
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TDA5240
Functional Description
input data
telegram
signal power
better FAR
performance
SDTHR level area
better
MER/BER
performance
high SDTHR level
low SDTHR level
Figure 16
Signal Detector Threshold Level
Quick Procedure to Determine Signal and Noise Detector Thresholds
Preparation
A setup is required with original RF hardware as in the final application. The values of
SPWR and NPWR can be read via the final application.
A complete configuration file using right modulation, data rate and Run Mode Slave,
must be prepared and downloaded to the TDA5240.
Signal Detector Threshold for ASK
Take 500 readings of SPWR (50 are also possible, but this leads to less accurate results)
with no RF input signal applied (=noise only). Calculate average and Standard Deviation.
Signal Detector Threshold is average plus 2 times the Standard Deviation. To load the
x_SIGDET0/1 register the calculated value must be rounded and converted to
hexadecimals. For a final application, the Signal Detector Threshold should be varied to
optimize the false alarm rate and the sensitivity.
Signal and Noise Detector Thresholds for FSK
Signal Detector Threshold
Do 500 (50) readings of SPWR with no RF input signal applied (=noise only). Calculate
average and Standard Deviation. Signal Detector Threshold is average plus 2 times the
Standard Deviation. Of course this value has to be rounded and converted to
Data Sheet
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TDA5240
Functional Description
hexadecimals. For a final application the Signal Detector Threshold should be varied to
optimize the false alarm rate and the sensitivity.
Verification if Squelch only is possible
Apply a bit pattern (e.g. PRBS9) with correct data rate at about -80 dBm input signal
power and minimum FSK deviation to the RF input. Do 500 (50) readings of SPWR,
calculate average minus three times the Standard Deviation. This value should be higher
than the calculated Signal Detector Threshold calculated above. If this is not the case,
Signal Detector AND Noise Detector must be used.
Noise Detector Threshold
Do 500 (50) readings of NPWR with no RF input signal applied (=noise only). Calculate
average and Standard Deviation. Noise Detector Threshold is average minus the
Standard Deviation. Round this value and convert it to hexadecimals. For a final
application, the Noise Detector Threshold should be varied to optimize false alarm rate
and sensitivity.
Signal Detector Low Threshold
The Signal Detector Low Threshold is always required in combination with the Noise
Detector.
Set register bit SDLORE to 1 and set bit group SDLORSEL to 00. Apply a bit pattern (e.g.
PRBS9) at correct data rate at about -80 dBm input signal power and minimum FSK
deviation to the RF input. Do 500 (50) readings of SPWR, calculate average. If average
is larger than 200 dec (=0xC8), SDLORSEL has to be increased to the next larger value
until average is smaller than 200 dec. x_SIGDETLO = 0.8 * (average - 3 * Standard
Deviation). Set register SDLORE back to 0. The last setting of bit group SDLORSEL
must also be used for configuration!
Verification
Threshold settings should be verified by testing receiver sensitivity over the input
frequency range, with a step size of 100Hz, at minimum FSK deviation with all
combinations of minimum and maximum data rate and duty cycle.
Further detailed information can be taken from the corresponding Application Note.
Data Sheet
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Functional Description
2.4.8.2 Encoding Modes
The IC supports the following Bi-phase encodings:
• Manchester code
• Differential Manchester code
• Bi-phase space code
• Bi-phase mark code
The encoding mode is set and enabled by bit group CODE in x_DIGRXC configuration
register.
Data
1 0 1 0 0 1 1 0
Clock
Manchester
Differential Manchester
Biphase Space
Biphase Mark
Figure 17
Coding Schemes
The encoding modes Inverted Manchester and Inverted Differential Manchester can also
be decoded internally by usage of CHIPDINV bit in x_DIGRXC register (see Figure 15).
All the Manchester symbol combinations including Code Violations are shown in
Figure 18. Digital 0 and 1 are coded with the change of the amplitude in the middle of
the symbol period. The Code Violations (CV) M (mark) and S (space), are coded as
low/high signal levels.
0
1
S
M
1st 2nd
Chip Chip
1st 2nd
Chip Chip
1st 2nd
Chip Chip
1st 2nd
Chip Chip
Figure 18
Manchester Symbols including Code Violations
Data Sheet
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Functional Description
2.4.8.3 Clock and Data Recovery
An all-digital PLL (ADPLL) recovers the data clock from the incoming data stream. The
second main function is the generation of a signal indicating symbol synchronization.
Synchronization on the incoming data stream generally occurs within the first 4 bits of a
telegram.
Tnom / 16
EOM
from Clock
Recovery Slicer
Symbol
Timing Extrapolation
Sync found
Digital
Controlled
Oscillator
Phase
Detector
PI
Recovered
Clock
Loop Filter
Tnom / 2
T
nom / 2
Figure 19
Clock Recovery (ADPLL)
Clock Recovery is implemented as standard ADPLL PI regulator with Timing
Extrapolation Unit for fast settling.
In the unlocked state, the Timing Extrapolation Unit calculates the frequency offset for
the incoming data stream. If the defined number of Bi-phase encoded bits are detected
(the RUNIN length can be set in the x_CDRRI register), the I-part and the PLL oscillator
will be set and the PLL will be locked.
When x_CDRRI.RUNLEN is set to small values, then the I-part is less accurate (residual
error) and can lead to a longer needed PLL settling time and worse performance in the
Data Sheet
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Functional Description
first following bits. Therefore the selected default value is a good compromise between
fast symbol synchronization and accuracy/performance.
Duty cycle and data rate acceptance limits are adjustable via registers. After locking, the
clock must be stable and must follow the reference input. Therefore, a rapid settling
procedure (Timing Extrapolation Unit) and a slow PLL are implemented.
If the PLL is locked, the reference signal from the Clock Recovery Slicer is used in the
phase detector block to compute the actual error. The error is used in the PI loop filter to
set the digital controlled oscillator running frequency. For the P, I and Timing
Extrapolation Unit settings, the default values for the x_CDRP and x_CDRI control
registers are recommended.
The PLL will be unlocked, if a code violation of more than the defined length is detected,
which is set in the x_TVWIN control register. Another criterion for PLL resynchronization
is an End Of Message (EOM) signalled by the Framer block.
The PLL oscillator generates the chip clock (2 * fdata).
The internal PLL lock signal used by the Framer is generated up to 1 bit before RUNIN
ends. The Timing Extrapolation Unit counts the incoming edges and interprets the delay
between two edges as a bit or a chip. Due to the fact that the first edge of a “Low” bit,
coded as ’0’ and ’1’, rises one chip later than a “High” bit, the PLL locks later in this case
(see Figure 20). The real needed RUNIN time can be shorter than the configured
RUNIN length in the x_CDRRI register by up to two chips. This should be considered
when setting the TSI pattern and/or TSI length. See also Chapter 2.4.8.6 Frame
Synchronization.
first edge
RUNIN
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
4 bits detected
first edge
0
RUNIN
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
4 bits detected
Figure 20
RUNIN Generation Principle
Data Sheet
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Functional Description
Number of Required RUNIN Bits
The number of RUNIN bits specified in x_CDRRI register should always be 3.0. This
setting defines the duration of the internal synchronization. Because of internal
processing delays, the pattern length that must be reserved for RUNIN is longer.
The ideal RUNIN pattern is a series of either Manchester 1’s or Manchester 0’s. This
pattern includes the highest number of edges that can be used for synchronization. In
this case, the number of physically sent RUNIN bits is 4.
For any other RUNIN pattern, 5.5 bits should be reserved for RUNIN.
TVWIN (Timing Violation WINdow length)
The PLL unlocks if the reference signal is lost for more than the time defined in the
x_TVWIN register. During the TSI Gap (see TSI Gap Mode in Chapter 2.4.8.6 Frame
Synchronization), the PLL and the TVWIN are frozen.
TVWIN time is the time during which the Digital Baseband Receiver should stay locked
without any incoming signal edges detected. The time resolution is T/16.
Calculation of TVWIN can be seen at the end of subsection TSI Gap Mode in
Chapter 2.4.8.6 Frame Synchronization.
Data Sheet
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Functional Description
Duty Cycle Variation
Ideally, the input signal to the Clock and Data Recovery (CDR) would have a chip width
of 8 samples and a bit width of 16 samples and the CDR would not lock onto any input
that violates this. However, due to variations in the duty cycle this stringent assumption
for the pulse widths will in general not be true. Therefore it is necessary to loosen this
requirement by using tolerance windows.
TOLCHIPH
TOLBITH
TOLCHIPL
TOLBITL
1
t
lim_chip_low = 8 - TOLCHIPL
lim_bit_low = 16 - TOLBITL
lim_chip_high = 8 + TOLCHIPH
lim_bit_high = 16 + TOLBITH
Figure 21
Definition of Tolerance Windows for the CDR
There exist now two registers - x_CDRTOLC for the chip width tolerance and
x_CDRTOLB for the bit width tolerance - that can be used to tighten or loosen the
windows around the ideal pulse widths. As it can easily be seen from Figure 21, tighter
windows will result in more stringent requirements for the input data to have a 50% duty
cycle and bigger windows will allow the duty cycle to vary more. Figure 21 also depicts
the meaning of the bits in the registers x_CDRTOLC and x_CDRTOLB.
Data Sheet
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Functional Description
Data Rate Acceptance Limitation
The Clock and Data Recovery is able to accept data rate errors of more than +/-15% with
a certain loss of performance. There exist Multi-Configuration applications where the
data rate of both configurations are within this range. So the adjacent data rates of these
configurations are disturbing each other. The limitation of the data rate acceptance can
be activated in this case.
clock recovery
slicer
CLOCK RECOVERY
symbol synchronization
Data Rate
&
Acceptance
Limitation
preset value correlator
cdr_lock
cdr_clock
Clock Recovery PLL
Figure 22
Data Rate Acceptance Limitation
The clock and data recovery (CDR) regenerates the clock based on the input data
delivered from the clock recovery (CR) slicer. Symbol synchronization (cdr_lock) is
achieved when a specified number of chips (can be set via register x_CDRRI.RUNLEN)
has a valid pulse width. In parallel the preset value correlator estimates a preset value
for the clock recovery PLL so that a shorter settling time is achieved. This preset value
is also proportional to the data rate and is therefore used in the data rate acceptance
limitation block. If the preset value is outside a certain range (positive and negative
threshold configurable via registers CDRDRTHRP and CDRDRTHRN), the CDR does
not go into lock and no symbol synchronization is generated.
For each configuration there exists one bit (register x_CDRRI.DRLIMEN) to switch the
data rate acceptance limitation functionality on or off. Data rate acceptance limitation is
disabled by default. All configurations share the same threshold registers, the default
Data Sheet
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Functional Description
thresholds are set so that almost all packets with a data rate error of +/-10% and larger
are rejected.
The following statements summarize some important aspects that need to be kept in
mind when using the described functionality:
• The output of the estimator must be described on statistical terms - this means that
it can not be guaranteed that all packets with a certain data rate outside the allowed
range will be rejected
• The quality of the estimated data rate value is mainly influenced by the setting of the
signal and noise detectors
• Reducing the RUNIN length in register x_CDRRI reduces the quality of the data rate
estimation, resulting in a degradation of the performance of the data rate acceptance
limitation block
• The same threshold can be used for FSK and ASK
• If the thresholds are too small it may happen that also packets with a valid data rate
are rejected
2.4.8.4 Data Slicer and Line Decoding
The output signal of the matched filter within the internal data processing path is in the
range of +x to -x (x is the maximum value of the internal bit width). If Code Violations
within a Manchester encoded bitstream have to be detected, the data slicer has to
recover the underlying chipstream instead of the bitstream. In this case zero values at
the matched filter output lead to an additional slicing threshold and an implicit sensitivity
loss. To provide the full reachable sensitivity for applications which do not need the
symbols S (space) and M (mark), the data slicer has two different operating modes:
• Chip mode (Code Violations are allowed)
• Bit mode (without Code Violations)
The chip mode introduces an implicit sensitivity loss compared to the bit mode, because
a zero-crossing in the 2-chip matched filter signal must be detectable. This is only
possible when an additional slicing level is introduced in the data slicer.
The data slicer internally maps a positive value to a 1 and a negative value to a -1.
Everything inside the zero thresholds (zero-tube) becomes a 0. After that, the decoding
to the chip-level representation is done by mapping the -1 to a "0" chip and the 1 to a "1"
chip. A zero out of the data slicer is decoded to chip-level by referencing to the previous
chip value.
Data Sheet
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Functional Description
In bit mode the data slicer has only one threshold (zero) to distinguish between the two
levels of the matched filter output. The data slicer internally maps a positive value to a 1
and a negative value to a -1. After that, the selected line decoding is applied.
Summary of data slicer modes in the TDA5240:
Data Slicer Chip mode:
• Code violations detectable (TSI, or EOM)
• Performance loss compared to bit mode
• Activation via setting register x_SLCCFG to a value of
+ 0x90 (Chip Mode EOM-CV: For patterns with code violations in data packet and
optimized for activated EOM code violation criterion (and optional EOM data
length criterion))
+ 0x94 (Chip Mode EOM-Data length: For patterns with code violations in data
packet and optimized for activated EOM data length criterion only)
+ 0x95 (Chip Mode Transparent: When Framer is not used, but CH_DATA /
CH_STR are used for data processing)
Data Slicer Bit mode:
• No code violations detectable
• Full performance
• In case of Bi-phase mark and Bi-phase space an additional bit must be sent to ensure
correct decoding of the last bit
• Activation via setting register x_SLCCFG to a value of 0x75
In Data Slicer Bit mode an even number of TSI chips needs to be used.
When Data Slicer Bit mode is selected, then the the last chip of RUNIN must be different
from first chip of TSI (e.g. Runin-bit sequence 000000 and TSI bit sequence 0xx...xxx is
OK). Otherwise the TSI will not be detected correctly.
On using Data Slicer Bit Mode, the Wake-up criteria Equal Bits Detection and Pattern
Detection cannot be applied.
A line decoder decodes the incoming data chips according to the encoding scheme (see
Chapter 2.4.8.2).
Data Sheet
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Functional Description
2.4.8.5 Wake-Up Generator
A wake-up generation unit is used only in the Self Polling Mode for the detection of a
predefined wake-up criterion in the received pattern.
There are two groups of configurable wake-up criteria:
• Wake-up on Level criteria
• Wake-up on Data criteria
The search for the wake-up data criterion is started if data chip synchronization has
occurred within the predefined number of symbols, otherwise the wake-up search is
aborted. Several different wake-up patterns, like random bit, equal bit, bit pattern or bit
synchronization, are programmable.
Additional level criterion fulfilment for RSSI or Signal Recognition can lead to a fast
wake-up and to a change to Run Mode Self Polling. Whenever one of these Wake-up
Level criteria is enabled and exceeds a programmable threshold, a wake-up has been
detected.
The Wake-up Level criterion can be used very effectively in combination with the
Ultrafast Fall Back to SLEEP Mode (see Chapter 2.6.2.3) for further decreasing the
needed active time of the autonomous receive mode. A configurable observation time
for Wake-up on Level can be set in the x_WULOT register. The Wake-up on Level
criterion can be handled very quickly for FSK modulation, while in case of ASK the nature
of this modulation type has to be kept in mind.
Data Sheet
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Functional Description
RSSI Level
x_WURSSIBHy
Exceeding Threshold
Compare
x_WURSSIBLy
x_WURSSITHy
Data
WU Level
Criterion
x_NDCONFIG
x_SIGDET1
Exceeding Threshold(s)
Wake-up on Signal
Recognition
x_NDTHRES
x_SIGDETLO
Sync Search Time Elapsed
Sync
WU
x_WUBCNT
WUW Chip Counter
Elapsed
Wake-up Window
Chip Counter
Wake-up
Generation
FSM
No WU
Code Violation Detected
Bit Change Detected
Code Violation Detector
Bit Change Detector
3
Chip Data Clock
Chip Data
16-chips Shift Register
0
2
15
16
x_WUPAT0
x_WUPAT1
Pattern Detected
Pattern Detector
RSSI
WU on Level Criteria
Signal
Recognition
Sync
Random Bits
Equal Bits
Pattern
Selection
WU on Data Criteria
x_WUC
Figure 23
Wake-Up Generation Unit
Wake-Up on RSSI
The threshold x_WURSSITHy is used to decide whether the actual signal is a wanted
signal or just noise. Any kind of interfering RSSI level can be blocked by using an RSSI
blocking window. This window is determined by the thresholds x_WURSSIBLy and
Data Sheet
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Functional Description
x_WURSSIBHy, where y represents the actual RF channel. These two thresholds can
be evaluated during normal operation of the application to handle the actual interferer
environment.
The blocking window can be disabled by setting x_WURSSIBHy to the minimum value
and x_WURSSIBLy to the maximum value.
wanted signal
x_WURSSIBHy
interferer
x_WURSSIBLy
wanted signal
x_WURSSITHy
noise floor
Figure 24
RSSI Blocking Thresholds
Threshold evaluation procedure
A statistical noise floor evaluation using read register RSSIPMF (RMS operation) leads
to the threshold x_WURSSITHy. The interferer thresholds x_WURSSIBLy and
x_WURSSIBHy are disabled when they are set to their default values.
For evaluation of the interferer thresholds, either use register RSSIPMF for RMS
operation or during SPM and WU (Wake-Up) on RSSI use register RSSIPWU to
statistically evaluate the interferer band. Finally the thresholds x_WURSSIBLy and
x_WURSSIBHy can be set.
Wake-Up on RSSI can also be applied as additional criterion when already using a
Wake-Up on Data criterion in Constant On-Off (COO) Mode.
Further details can be seen in Figure 10, Chapter 2.4.7 RSSI Peak Detector,
Chapter 2.6.2.2 Constant On-Off Time (COO) and Chapter 2.6.2.3 Fast Fall Back to
SLEEP (FFB).
NOTE: If e.g. an interferer ends/starts too close after/to the beginning/end of the
observation time, then a decision level error can arise. This is due to the filter dynamics
(settling time). Further, for interferer thresholds evaluation in SPM this changes interferer
statistics. Several interferer measurements are recommended to suppress this, what
makes sense anyway for a better distribution.
Data Sheet
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Functional Description
Wake-Up on Signal Recognition
Instead of the previously mentioned RSSI criterion, the Signal Recognition criterion (see
Chapter 2.4.8.1) can be applied for Wake-Up search. So the x_SIGDET1, x_SIGDETLO
and x_NDTHRES threshold registers can be used.
The observation time has to be specified in the register x_WULOT. This observation time
has to contain the delay in the signal path (12.5 µs + 2.25*Tbit) and the duration for the
comparison of the Signal Recognition criterion.
The number of consecutive valid Signal Recognition samples/levels is compared vs. a
threshold defined in x_WURSSIBHy register. Please note that x_WURSSIBHy register
is used for both Wake-Up on RSSI and Wake-Up on Signal Recognition function. This
threshold has an influence on the false alarm rate. So x_WURSSIBHy defines the
minimum needed consecutive T/16 samples of the Signal Recognition output to be at
high level for a positive Wake-Up event generation.
Wake-Up on Data Criterion
All SFRs configuring the Wake-up Generation Unit support the Multi-Configuration
capability. The search for a wake-up data criterion is started if symbol synchronization is
given within a certain duration (see Chapter 2.4.8.8 RUNIN, Synchronization Search
Time and Inter-Frame Time); otherwise the wake-up search is aborted. During the
observation period, the wake-up data search is aborted immediately if symbol
synchronization is lost. If this is not the case, the wake-up search will last for the number
of chips/bits defined in the register x_WUBCNT.
The Wake-up Window (WUW) Chip/Bit Counter counts the number of received chips/bits
and compares this number vs. the number of chips/bits defined in the register
x_WUBCNT.
The Code Violation Detector checks the incoming chip data stream for being Bi-Phase
coded. A Code Violation is given if three consecutive chips are ’One’ or ’Zero’.
The Bit Change Detector checks the incoming Bi-phase coded bit data stream for
changes from 'Zero' to 'One' or 'One' to 'Zero'.
The Pattern Detector searches for a pattern with 16 chips/bits length within the Wake-up
Window. The pattern is configurable via the registers x_WUPAT0 and x_WUPAT1.
On using Data Slicer Bit Mode, the Wake-up criteria Equal Bits Detection and Pattern
Detection cannot be applied. Further details can be seen at the end of Chapter 2.4.8.4.
The selection of 1 out of 4 wake-up data criteria is done via the x_WUC register.
Data Sheet
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Functional Description
Details on the four wake-up data criteria
Pattern Detection
The incoming signal must match a dedicated pattern of up to 8 bits or 16 chips in Wake-
Up Pattern Chip Mode. When the WUW chip counter elapses, the search is stopped. The
higher the setting of WUBCNT the longer it is possible to search for the wake-up pattern.
The minimum for the WUBCNT is 0x11!
The pattern detection is stopped either when WUW elapses, or when symbol
synchronization is lost.
The Wake-Up pattern can be extended from 16 chips to 16 bits on activation of
WUPMSEL bit (Wake-Up Pattern Bit Mode). In this Bit Mode no Code Violations (CV)
are allowed and thus Pattern Detection is aborted, when a CV is detected.
Equal Bits Detection
Wake-up condition is fulfilled if all received bits inside of WUW are either 0 or 1.
WUBCNT holds the number of required equal bits. The higher the setting of WUBCNT
the lower the number of wrong wake-ups.
Equal bits detection is stopped if a bit change or a CV has been detected, or symbol
synchronization is lost.
Random Bits Detection
Wake-up condition is fulfilled if there is no code violation inside of WUW. WUBCNT holds
the number of required Bi-phase coded bits. The higher the setting of WUBCNT, the
lower the number of wrong wake-ups.
Random bits detection is stopped if a code violation has been detected, or symbol
synchronization is lost.
Valid Data Rate Detection
Wake-up condition is fulfilled if symbol synchronization is possible inside of Sync Search
Time out (see Chapter 2.4.8.8 RUNIN, Synchronization Search Time and Inter-
Frame Time). WUBCNT is not used.
This is the weakest wake-up data criterion, and should be avoided.
Data Sheet
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Functional Description
SSync Search Time Elapsed =1
SSync=0
Reset
Init Wakeup Unit
Idle
WU=0
No WU=0
SSync=1
Wakeup Criteria=Pattern Detection
SSync=1
SSync=1
SSync=1
Wakeup Criteria=Valid Data Rate
Detection
Wakeup Criteria=Random Bits Detection
Wakeup Criteria=Equal Bits Detection
WUW Chip Counter<
WUBCNT
WUW Chip Counter<
WUBCNT
Equal Bits
Detection
SSync=0
Pattern Detection
Random Bits Detection
SSync=0
CV=1
WUW Chip
Counter<WUBCNT
WU=0
No WU=0
WU=0
No WU=0
WU=0
No WU=0
Bit Change Detected=1
SSync=0
CV=1
WUW Chip Counter elapsed
(WUW Chip Counter=
WUBCNT)
WUW Chip Counter elapsed
(WUW Chip Counter = WUBCNT)
WUW Chip Counter elapsed
(WUW Chip Counter= WUBCNT)
Pattern Match=1
Wake-Up
WU=1
No WU=0
No Wake-Up
WU=0
No WU=1
Figure 25
Wake-Up Data Criteria Search
2.4.8.6 Frame Synchronization
The Frame Synchronization Unit (Framer) synchronizes to a specific pattern to identify
the exact start of a payload data frame within the data stream. This pattern is called
Telegram Start Identifier (TSI).
There are different TSI modes selectable via the configuration:
• 16-Bit TSI Mode, supporting a TSI length of up to 16 bits or 32 chips
• 8-Bit Parallel TSI Mode, supporting two independent TSI pattern of up to 8 bits length
each. Different payload length is possible for these two TSI pattern.
• 8-Bit Extended TSI Mode, identical to 8-Bit Parallel TSI Mode, but identifies which
pattern matches by adding a single bit at the beginning of the data frame
• 8-Bit TSI Gap Mode, supporting two independent TSI pattern separated by a
discontinuity
All SFRs configuring the Frame Synchronization Unit support the Multi-Configuration
capability (Config A, B, C and D). The Framer starts working in Run Mode Slave after
Symbol Sync found and in Self Polling Mode after wake-up found and searches for a
frame until TSI is found or synchronization is lost. The input of the Framer is a sequence
Data Sheet
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TDA5240
Functional Description
of Bi-phase encoded data (chips). Basically the Framer consists of two identical
correlators of 16 chips in length. It allows a Telegram Start Identifier (TSI) to be
composed of Bi-phase encoded “Zeros” and “Ones”. The active length of each of the 16
chips correlators is defined independently in the x_TSILENA and x_TSILENB registers.
The pattern to match is defined as a sequence of chips in the x_TSIPTA0, x_TSIPTA1,
x_TSIPTB0 and x_TSIPTB1 registers.
Note that the RUNIN length shown in the figures below is the maximum needed RUNIN
with the length of 8 chips. Further details on the needed RUNIN time of the receiver can
be seen in Chapter 2.4.8.3 Clock and Data Recovery.
Bi-phase- /
Data
Manchester -
Decoder
Data
Data Clock
CV
Data Clock
EOMCV
EOMSYLO
EOMDATLEN
Code-Violation
Detector
EOM-Detector
EOM
x_EOMDLEN
x_EOMDLENP
Sync
FSync
TSI wild card
x_TSIMODE(6:3)
Delay-Line 16-bit
Chip-Data Clock
Chip-Data
from CR
from
Data-
Slicer
MRB
LRB
x_TSILENA
Correlator A
Controller
Correlator A 16-bit
MSB LSB
CorrAMatch
Frame
Synchron-
ization
TSI Data-Pattern
TSI Data-Pattern
LSB
MSB
Controller
x_TSIMODE
x_TSIGAP
Delay-Line 16-bit
Correlator B 16-bit
MUX
MRB
LRB
Correlator B
Controller
x_TSILENB
TSI Data-Pattern
TSI Data-Pattern
LSB
MSB LSB
MSB
Figure 26
Frame Synchronization Unit
Data Sheet
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Functional Description
Please note that for Data Slicer Bit Mode a special constellation of RUNIN bits and TSI
bits has to be ensured. Further details can be seen at the end of Chapter 2.4.8.4.
The two independent correlators can be configured in the x_TSIMODE register to work
in one of the following four TSI modes:
16-Bit Mode: As a single correlator of up to 32 chips
The length of the x_TSILENA register must be set to 16d whenever x_TSILENB is higher
than 0.
x_TSILENA = 16d, x_TSILENB = 6d
RunIn
0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 1 0
Incoming Pattern
0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1
Manchester Coded
x_TSIPTB x_TSIPTA
4 3 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0
5
TSI Pattern Match
FSYNC
0110011001010110101010
Data into FIFO
1 0 1 0 0 1 0
Figure 27
16-Bit TSI Mode
8-Bit Parallel Mode: As two correlators of up to 16 chips length each
working simultaneously in parallel
In the following example, TSI Pattern B matches first and generates an FSYNC. The
lengths of both TSI Patterns are now independent from each other. The payload length
for these two TSI Pattern may be different.
x_TSILENA = 16d, x_TSILENB = 6d
RunIn
Incoming Pattern
0 0 0 0 0 1 0 1 0 1 0 0 1 0
Manchester Coded
TSI Pattern B Match
0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1
x_TSIPTB
5 4 3 2 1 0
011001
FSYNC
Data into FIFO
1 0 1 0 0 1 0
Figure 28
8-Bit Parallel TSI Mode
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Functional Description
8-Bit Extended Mode: As two correlators of up to 16 chips length each
working simultaneously in parallel, with matching information insertion
This bit is inserted at the beginning of the payload. “0” is inserted, when correlator A has
matched and “1” when correlator B has matched. The payload length for these two TSI
Pattern may be different.
x_TSILENA = 16d, x_TSILENB = 6d
RunIn
0 0 0 0 0 1 0 1 0 1 0 0 1 0
Incoming Pattern
Manchester Coded
0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1
x_TSIPTB
5 4 3 2 1 0
TSI Pattern B Match
FSYNC
011001
1 1 0 1 0 0 1 0
Data into FIFO
Matching Information inserted
Figure 29
8-Bit Extended TSI Mode
8-Bit Gap Mode: As two sequentially working correlators of up to 16 chips
length each
This mode is only used in combination with the TSI Gap Mode shown below!
This mode is used to define a gap between the two patterns which is preset in the
x_TSIGAP register. To identify exactly the beginning of the gap it would be helpful on
occasion to place the first CV of the gap into the TSI Pattern A. In this case, the gap
length needed for the x_TSIGAP register must be shortened and the x_TVWIN length
must be extended.
x_TSILENA = 8d, x_TSILENB = 12d
TSIGRSYN = 1
RunIn
Gap
RunIn
0
0
0
0
0
1
0 S
0 0 0 0 1 0 0 0 1 1 1 1 1 0 1
Incoming Pattern
Manchester Coded
0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0
x_TSIPTA
2
x_TSIPTB
1110 9 8 7 6 5 4 3 2 1 0
7
6
5
4
3
1
0
TSI Pattern Match
FSYNC
01100100
100101011010
1
1 1 0 1
Data into FIFO
Figure 30
8-Bit Gap TSI Mode
Data Sheet
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Functional Description
Selection of a TSI Pattern
TSI patterns must be different to the wake-up bit stream and the RUNIN to clearly mark
the start of the following payload data frame. It should be considered that the
synchronization has a tolerance of about one bit. In addition, synchronization is related
to data chips, and may occur in the middle of a data bit. This all must be tolerated by the
data framer. Further details can be seen in Chapter 2.4.8.3 Clock and Data Recovery.
Ideal TSI patterns have a unique bit combination at their end, which may also contain a
number of code violations (CVs), when possible (see Chapter 2.4.8.4 Data Slicer and
Line Decoding).
Some examples of TSI patterns:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
When CVs are used:
0 0 0 0 0 0 0 0 0 0 0 0 0 M 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 M 0
Note: CVs in a TSI are practical for better differentiation to the real data, especially if
repetition of data frames is used for wake-up.
End of Message (EOM) Detection
An End Of Message (EOM) detection feature is provided by the EOM detector. Three
criteria can be selected to indicate EOM.
The first is based on the number of received bits since frame synchronization. The
number of expected bits is preset in the x_EOMDLEN register. Sending fewer bits as
defined in the register will result in no EOM. The EOM counter will be reset after new
frame synchronization.
In 8-Bit Parallel TSI Mode and 8-Bit Extended TSI Mode, the payload length for the two
independent TSI pattern may be different. Therefore the payload length for TSI B pattern
can be preset in the x_EOMDLENP register, while payload length for TSI A pattern can
be preset in the x_EOMDLEN register.
The second criterion is the detection of a Code Violation. This EOM criterion is not
applicable for Data Slicer Bit mode.
Data Sheet
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Functional Description
The third criterion is the loss of symbol synchronization. Depending on the x_TVWIN
register, the Sync signal persists for a certain amount of time after the end of the pattern
has been reached. Therefore, more bits could be written into the FIFO than sent. The
three EOM criteria can be combined with each other. If one of the selected EOM criteria
is fulfilled, an EOM signal will be generated.
TSI Gap Mode
The TSI Gap Mode is only used if TSI patterns contain a gap that is not synchronous to
the data rate, e.g. if a gap is 7.7 data bits, or if a gap is longer than 10 data bits. In all
other cases, gaps should be included in the TSI pattern as code violations.
Because of its complexity in configuration, TSI Gap Mode should be only used in
applications as noted above!
For these special protocols, it is possible to lock the actual data frequency during a long
Code Violation period inside a TSI (x_TSIGAP must have a minimum of 8 chips).
TSIGAP is used to lock the PLL after TSI A was found. After the lock period, two different
resynchronization modes are available (TSI Gap ReSYNchronization, TSIGRSYN):
• Frequency readjustment (PLL starts from the beginning), TSIGRSYN = 1. In this
mode the T/2 gap resolution can be set in the 5 MSB x_TSIGAP register bits. The
value in GAPVAL (3 LSB in x_TSIGAP register) is not used. This is the preferred
mode in TSI Gap Mode.
clock recovery reset
start point
valid data
all space or all mark
valid data
GAPSync
RUNIN
TSI A
TSI GAP
PLL sync
TSI B
< 1bit
< 1bit
internal PLL sync
Figure 31
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 1
• Phase readjustment only, TSIGRSYN = 0. In this mode, the value in GAPVAL is used
to correct the phase after the gap phase. Overall gap time can be defined in T/16
Data Sheet
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Functional Description
steps. The 5 MSB bits (TSIGAP) define the real gap time and the 3 LSB bits
(GAPVAL) the DCO (digital controlled oscillator) phase correction value.
clock recovery phase
readjustment start point
valid data
all space or all mark
valid data
RUNIN
TSI A
TSI GAP
PLL sync
GAPSync
TSI B
< 1bit
Figure 32
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 0
When the time TSI GAP in the start sequence of the transmitted telegram has elapsed,
the receiver needs a certain time (GAPSync = 5...6 chips) to readjust the PLL settings.
Behavior of the system at the starting position of the TSI B:
The starting position (TSI B start) for the TSI B comparison is independent from the
RUNIN settings (x_CDRRI register) and the resynchronization mode (x_TSIMODE
register):
TSIBstart[chips] = TSIGAP[chips] + 6…8
The incoming chips at TSI B start and the following incoming chips are compared with
the contents of the register TSI B. Please notice that the receiver’s PLL runs at the data
rate determined before the gap. Therefore, the receiver calculates the gap based on this
data rate.
Behavior of the system at the ending position of TSI B:
The system checks for the TSI B to match within a limited time. If there is no match within
this time, then the receiver starts again to search for the TSI A pattern at the following
incoming chips:
TSIBstop[chips] = TSIGAP[chips] + TSILENB[chips] + 11
For a successful TSI B pattern match, the defined TSI B pattern must be between “Start
of TSI B” and “Stop of TSI B”. In the example below, the earliest possible start position
would be the 18th chip and the latest possible start position would be the 22nd chip.
Data Sheet
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Functional Description
Please note that after a gap, the internal TSI comparison register is cleared (all chips set
to ’0’). In this case, a TSI B criteria of “0000” would always match at the beginning. To
avoid such an unwanted matching, set the highest TSI B match chip to ’1’.
GapSync
RunIn
TSIA
TSIGAP=10 chips
TSIB
Incoming Pattern[bits] ... 0 0 1 0 S _ _ _ _ _ 0 0 0 0 1 0 0 0 1 1 1 1 1
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6
TSIBstart
Start of TSIB
comparison
Stop of TSIB
comparison
Figure 33
TSIGap TSIB Timing
The TVWIN (Timing Violation WINdow) and TSIGAP dependency is shown in Figure 34.
TVWIN
TVWIN
CV
TVWIN
GAP
int.
delay
TSIA
RUNIN/
TSIGRSYN = 1
TVWIN without GAP
TVWIN with GAP
Figure 34
TVWIN and TSIGAP dependency example
TVWIN calculation for pattern without Gap time:
TVWIN = round((8 + 16 ⋅ CV + 8) ⋅ 1.25)
The entire TVWIN time is made up of the CV1) number itself, the half bit before CV and
the half bit after the CV. To reach all frequency and duty cycle errors, 25% of the overall
sum must be added.
TVWIN calculation with Gap time:
TVWIN = round(max{((8 + 16 ⋅ CV + 8) ⋅ 1.25), (8 + 16 ⋅ TSIACV + 16 ⋅ 1 + 8) ⋅ 1.25})
1) CV...number of bits containing manchester code violations
Data Sheet
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Functional Description
2.4.8.7 Message ID Scanning
This unit is used to define an ID or special combination of bits in the payload data stream,
which identifies the pattern. All SFRs configuring the Message ID Scanning Unit feature
the Multi-Configuration capability. Furthermore, it is available in the Slave and Self
Polling Mode. The MID Unit can be mainly configured in two modes: 4-Byte and 2-Byte
organized Message ID. For each configuration there are 20 8-bit registers designed for
ID storage. SFRs are used to configure the MID Unit: Enabling of the MID scanning,
setting of the ID storage organization, the starting position of the comparison and
number of bytes to scan.
When the Message ID Scanning Unit is activated, the incoming data stream is compared
bit-wise serially with all stored IDs. If the Scan End Position is reached and all received
data have matched the observed part of at least one MID the Message ID Scanning Unit
indicates a successful MID scanning to the Master FSM, which generates an MID
interrupt.
Please note that the default register value of the MID registers is set to 0x00. All MID
registers must be set to a pattern value to avoid matching to default value 0x00.
If the MID Unit finishes ID matching without success, the data receiving is stopped and
the FSM waits again for a Frame Start criterion. The received bits are still stored in the
FIFO.
Data Sheet
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Functional Description
4-Byte Organized Message ID:
In this mode four bytes are merged to define an ID-Pattern. This does not mean that the
ID must be exact four bytes long. The number of bytes used is defined in register
x_MIDC1. Up to 5 ID Patterns are available.
8
x_MID0
MID0:MID3
32
32
32
32
32
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
x_MID1
x_MID2
x_MID3
x_MID4
x_MID5
x_MID6
x_MID7
x_MID8
x_MID9
x_MID10
x_MID11
x_MID12
x_MID13
x_MID14
x_MID15
x_MID16
x_MID17
x_MID18
x_MID19
MID4:MID7
MID8:MID11
MID12:MID15
MID16:MID19
Combiner
Scan Start Position
Reached
MID found
Control-
FSM
MID Scanning finished
Scan End Position
Reached
Bit Counter
Interface to
Master FSM
Organization
Init MID Scanner
Enable MID Scanning
from
Digital-Receiver
Figure 35
4-Byte Message ID Scanning
Data Sheet
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TDA5240
Functional Description
2-Byte Organized Message ID:
In this mode two bytes are merged to define an ID Pattern. Up to 10 patterns are
possible.
8
x_MID0
MID0:MID1
16
16
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
x_MID1
x_MID2
x_MID3
x_MID4
x_MID5
x_MID6
x_MID7
x_MID8
x_MID9
x_MID10
x_MID11
x_MID12
x_MID13
x_MID14
x_MID15
x_MID16
x_MID17
x_MID18
x_MID19
MID2:MID3
MID4:MID5
MID6:MID7
MID8:MID9
MID10:MID11
MID12:MID13
MID14:MID15
MID16:MID17
MID18:MID19
Combiner
Scan Start Position
Reached
MID found
Control-
FSM
MID Scanning finished
Scan End Position
Reached
Bit Counter
Interface to
Master FSM
Organization
Init MID Scanner
Enable MID Scanning
from
Digital-Receiver
Figure 36
2-Byte Message ID Scanning
ID Position Configuration:
It is possible to choose which part of the incoming data stream is compared against the
stored MIDs. The register x_MIDC0 contains the Scan Start Position. If the Bit Counter
detects the Scan Start Position, the Control FSM enables the Scanner. The register
x_MIDC1 contains the number of bytes to scan. During the observation period, the
Data Sheet
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TDA5240
Functional Description
Message ID Scanning is aborted immediately by the Master FSM, if symbol
synchronization is lost or an EOM (End Of Message) is detected.
Example:
Start Selection: 00010001b
Number to scan: 00b, 01b, 10b, 11b
FSYNC
Bit
0
1
2
17 18
23 24 25 26
31 32 33 34
39 40 41 42
47 48 49
Byte0
Byte0
Byte0
Byte0
Number To Scan =00b
Number To Scan =01b
Number To Scan =10b
Byte1
Byte1
Byte1
Byte2
Byte2
Byte3
Number To Scan =11b
Start MID Scan
Figure 37
MID Scanning
The starting position in this case is Bit 17. Depending on the number to scan, the
corresponding number of bytes is compared with the stored MIDs.
2.4.8.8 RUNIN, Synchronization Search Time and Inter-Frame Time
The functionality of the Digital Baseband Receiver is divided into four consecutive data
processing stages; the data filter, clock and data recovery, data slicer and frame
synchronization unit. The architecture of the Digital Baseband Receiver is optimized for
processing bi-phase coded data streams.
The basic structure of a payload frame is shown in Figure 38. The protocol starts with a
so called RUNIN. The RUNIN with the minimum length of four bi-phase coded symbols
is used for internal filter settling and frequency adjustment. The TSI (Telegram Start
Identifier), which is used as framing word, follows the RUNIN sequence. The payload
contains the effective data. The length of the valid payload data is defined as the length
itself or additional criteria (e.g. loss of Sync).
Please note that almost all transmitted protocols send a wake-up sequence before the
payload frame (see also Figure 72). This wake-up sequence allows a very fast decision,
whether there is a suitable message available or not. Further details on this topic can be
gained from Chapter 2.6.1.5 and Chapter 2.4.8.5.
Data Sheet
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TDA5240
Functional Description
RUNIN
TSI
PAYLOAD
Figure 38
Structure of Payload Frame
Two important system parameters are described in this section: the Synchronization
Search Time Out (SYSRCTO) and the Inter-Frame Time. The processing sequence of
a payload frame is shown in Figure 39.
input data
RUNIN
TSI
RUNIN
CDR input
RUNIN
TSI
RUNIN
PLL re-synchronization
chip data available
data available
TSI
RUNIN
T4
T2
T1
T2 T2
T3
symbol sync found
Figure 39
Data Latency
The overall system latency time is calculated in two steps: T1 is the delay between ADC
input (ASK) / limiter output (FSK) and the CDR input, and T2 is the time between Symbol
Sync Found and the Framer output (decoded data available).
T4 is the time between Symbol Sync Found and Chip Data output (RX mode TMCDS).
T4 = 1 T. T is the nominal duration of one data bit.
T1 latency time include: (T1 = 12.5µs + 2 T)
• digital frontend processing delay
• matched filter computation time
• signal detector delay
T2 latency time include: (T2 = 1.5 T + 0.5 T1) )
• Data Slicer computation time
• Framer computation time.
1) The 0.5 T have to be added in case of activation of Bi-phase mark / space decoding mode and Data Slicer Bit
mode without Code Violation (see register x_SLCCFG)
Data Sheet
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TDA5240
Functional Description
The synchronization search time T3 is the time the receiver requires to search for a
pattern in an incoming data stream and needs to be considered in the receivers start-up
phase. The minimum value of the search time out length is the consequence of the
system latency time T1, the RUNIN length and the time of asynchronism between
transmitter and receiver.
This means, that for the minimum length of register value for SYSRCTO, the value 2 bits
plus 12.5 µs plus the RUNIN length, which is set in the x_CDRRI register, plus 2 bits (to
consider worst case RUNIN patterns and TX-RX asynchronism) have to be used. To
reach data rate and duty cycle errors, 10% of the overall sum must be added.
12.5μs
Tbit
⎛⎛⎛
⎞
⎞
⎞
SYSRCT0 = roundup ---------------- + 2 + RUNLEN + 2 ⋅ 16 ⋅ 1.1
⎝⎝⎝
⎠
⎠
⎠
A second important system parameter that must be considered, is the minimal Inter-
Frame Time (time between two data frames). This time is equal to the time T2 and has a
length of 1.5 or 2 bits1). The EOM to PLL resynchronization time is negligible in case
INITDRXES is disabled. Otherwise T1 has to be added.2)
Note that the described Inter-Frame Time is based on the input pattern with equal signal
power in the following data frame; in other cases, the Inter-Frame Time can vary from
the calculated value.
1)
2)
⎛
⎜
⎝
⎞
⎛
⎜
⎝
⎞
0.5Tbit
T1
0
TInter – Frame = 1.5Tbit
+
+
⎟
⎟
⎠
⎠
0
1) see previous footnote
2) in case INITDRXES is enabled
Data Sheet
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TDA5240
Functional Description
2.4.9
Power Supply Circuitry
The chip may be operated within a 5 Volts or a 3.3 Volts environment.
VDD5V
IN
IN
Voltage Regulator
Voltage Regulator
RX_RUN
5 → 3.3 V
5 → 3.3 V
OUT
OUT
VDDA
VDDD
IN
Analog
Section
RF
Section
Voltage Regulator
3.3 → 1.5 V
Digital-I/O
OUT
GNDA
VDDD1V5
GNDRF
Power-Up
Reset- Internal
Circuit Reset
Digital-Core
P_ON
Brownout
Detector
GNDD
Figure 40
Power Supply
For operation within a 5 Volts environment (supply voltage range 1), the chip is supplied
via the VDD5V pin. In this configuration the digital I/O pads are supplied via VDD5V and
a 5 V to 3.3 V voltage regulator supplies the analog/RF section (only active in Run
Modes).
When operating within a 3.3 Volts environment (supply voltage range 2), the VDD5V,
VDDA and VDDD pins must be supplied. The 5 V to 3.3 V voltage regulators are inactive
in this configuration.
The internal digital core is supplied by an additional 3.3 V to 1.5 V regulator.
The regulators for the digital section are controlled by the signal at P_ON (Power On)
pin. A low signal at P_ON disables all regulators and set the IC in Power Down Mode. A
low to high transition at P_ON enables the regulators for the digital section and initiates
a power on reset. The regulator for the analog section is controlled by the Master Control
Unit and is active only when the RF section is active.
To provide data integrity within the digital units, a brownout detector monitors the digital
supply. In case a voltage drop of VDDD below approximately 2.45 V is detected a
RESET will be initiated.
Data Sheet
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TDA5240
Functional Description
A typical power supply application for a 3.3 Volts and a 5 Volts environment is shown in
the figure below.
*) 22Ω
4.7Ω
4.7Ω
10Ω
TDA5240
TDA5240
VDD5V
VDD5V
VDDA
VDDD
VDDA
VDDD
100n
100n
5V
3.3V
100n
100n
*) 1μ
VDDD1V5
100n
VDDD1V5
100n
100n
100n
GNDA
GNDA
GNDRF
GNDD
GNDRF
GNDD
Supply-Application in 3.3V environment
Supply-Application in 5V environment
*) When operating in a 5V environment, the voltage-drop across the voltage
regulators 5 Æ 3.3V has to be limited, to keep the regulators in a safe
operating range. Resistive or capacitive loads (in excess to the scheme
shown above) on pins VDDA and VDDD are not recommended.
Figure 41
3.3 Volts and 5 Volts Applications
Data Sheet
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TDA5240
Functional Description
2.4.9.1 Supply Current
In SLEEP Mode, the Master Control Unit switches the crystal oscillator into Low Power
Mode (all internal load capacitors are disconnected) to minimize power consumption.
This is also valid for Self Polling Mode during Off time (SPM_OFF).
Whenever the chip leaves the SLEEP Mode/SPM_OFF (t1), the crystal oscillator
resumes operation in High Precision Mode and requires tCOSCsettle to settle at the trimmed
frequency. At t2 the analog signal path (RF and IF section) and the RF PLL are activated.
At t3 the chip is ready to receive data. The chip requires tRXstartup when leaving SLEEP
Mode/SPM_OFF until the receiver is ready to receive data.
A transient supply current peak may occur at t1, depending on the selected trimming
capacitance. The average supply current drawn during tRFstartdelay is IRF-FE-startup,BPFcal
.
Run Mode*)
SLEEP Mode**)
SPM OFF Time
RX_RUN Signal
Supply
Current
IRun
IRF-FE-startup ,BPFcal
Isleep_low
t1
t2
t3
t
tRFstartdelay
tCOSCsettle
tRXstartup
(Toff)
Ton
(Toff)
*) Run Mode covers the global chip state:sRun Mode Slave/ Receiver active in Self Polling Mode/ Run Mode Self Polling
**) Isleep_low is valid in the chip states: SLEEP / Off time duringSelf Polling Mode
Figure 42
Supply Current Ramp Up/Down
If the IF buffer amplifier or the clock generation feature (PPx pin active) are enabled, the
respective currents must be added.
Data Sheet
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TDA5240
Functional Description
2.4.9.2 Chip Reset
Power down and power on are controlled by the P_ON pin. A LOW at this pin keeps the
IC in Power Down Mode. All voltage regulators and the internal biasing are switched off.
A high transition at P_ON pin activates the appropriate voltage regulators and the
internal biasing of the chip. A power up reset is generated at the same time.
Supply Voltage
at VDDD Pin
3V
Reset- / Brownout-
Threshold (typ. 2.45V)
Functional-
Threshold (typ. 2V)
t
tReset
Internal Reset
Voltage at PP2 Pin
(NINT Signal)
3V
Reset- / Brownout-
Threshold (typ. 2.45V)
Functional-
Threshold (typ. 2V)
A ‚LOW’ is
generated at
PP2 pin
(NINT signal)
Level on
NINT signal
is undefined
t
µC reads
Interrupt-
A ‚HIGH’ is
generated at
PP2 pin
Supply voltage
falls below
Functional-Threshold
Status-Register
Supplyvoltage falls below
Reset- / Brownout-Threshold
(NINT signal)
A ‚LOW’ is
generated at
PP2 pin
Supplyvoltage
rises above
Functional-Threshold
A ‚LOW’ is generated
at NINT signal
(NINTsignal)
Figure 43
Reset Behavior
A second source that can trigger a reset is a brownout event. Whenever the integrated
brownout detector measures a voltage drop below the brownout threshold on the digital
Data Sheet
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TDA5240
Functional Description
supply, the integrity of the stored data and configuration can no longer be guaranteed;
thus a reset is generated. While the supply voltage stays between the brownout and the
functional threshold of the chip, the NINT signal is forced to low. When the supply voltage
drops below the functional threshold, the levels of all digital output pins are undefined.
When the supply voltage raises above the brownout threshold, the IC generates a high
pulse at NINT and remains in the reset state for the duration of the reset time. When the
IC leaves the reset state, the Interrupt Status registers (IS0 and IS1) are set to 0xFF and
the NINT signal is forced to low. Now, the IC starts operation in the SLEEP Mode, ready
to receive commands via the SPI interface. The NINT signal will go high, when one of
the Interrupt Status registers is read for the first time.
Data Sheet
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TDA5240
Functional Description
2.5
System Interface
In most applications, the TDA5240 receiver IC is attached to an external microcontroller.
This so-called Application Controller executes a firmware which governs the TDA5240
by reading data from the receiver when data has been received on the RF channel and
by configuring the receiver device. The TDA5240 features an easy to use System
Interface, which is described in this chapter.
Transparent Mode
The TDA5240 supports two levels of integration. In the most elementary fashion, it
provides a rather rudimentary interface by which the incoming RF signal is demodulated
and the corresponding data is made available to the Application Controller. Optionally, a
chip clock is generated by the TDA5240. Since the data signal is always directly the
baseband representation of the RF signal, we call this mode the Transparent Mode. The
usage of the Transparent Mode will be described in Chapter 2.5.1.2.
Packet Oriented Mode
Alternatively, the TDA5240 features the so-called Packet Oriented Mode which supports
the autonomous reception of data telegrams. The Packet Oriented Mode provides a
high-level System Interface which greatly simplifies the integration of the receiver in
data-centric applications. In Packet Oriented Mode, the data interface is based on
chunks of synchronous data which are received in packets. In the easiest way, the
Application Controller only reacts on the synchronous data it receives. The receiver
autonomously handles the line decoding and the deframing of these data, and supports
the timed reception of packets. Data is buffered in a receive FIFO and can be read out
via the data interface. Further, the receiver provides support for the identification of
wake-up signals. Details on the usage of the Packet Oriented Mode of the receiver are
given in Chapter 2.5.1.2.
2.5.1
Interfacing to the TDA5240
The TDA5240 is interfacing with an application by three logical interfaces, see
Figure 44. The RF/IF interface handles the reception of RF signals and is responsible
for the demodulation. Its physical implementation has been described in Chapter 2.4.3
and Chapter 2.4.8, respectively. The other two logical interfaces establish the
connection to the Application Controller. Note that due to the high level of integration of
the receiver, these interfaces impose minor requirements on the Application Controller,
which can be as simple as an 8-bit microcontroller operated at low clock rate. As will be
shown later, the physical implementation of the data interface depends on whether the
receiver is operated in Packet Oriented or in Transparent Mode.
For the sake of clarity, the communication between the TDA5240 and the Application
Controller is split into control flow and data flow. This separation leads to an
independent definition of the data interface and the control interface, respectively.
Data Sheet
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TDA5240
Functional Description
data interface
RX data
Application
Controller
(µC)
TDA5240
configuration
RF interface
status & alerts
control interface
Figure 44
Logical and electrical System Interfaces of the TDA5240
2.5.1.1 Control Interface
The control interface is used in order to configure the TDA5240 after start-up or to re-
configure it during run-time, as well as to properly react on changes in the status of the
receiver in the Application Controller’s firmware. The control interface offers a bi-
directional communication link by which
•
configuration data is sent from the Application Controller to the TDA5240,
• the receiver provides status information (e.g. the status of a data reception) as
response to a request it has received from the Application Controller, and
• the TDA5240 autonomously alerts the Application Controller that a certain,
configurable event has occurred (e.g. that a packet has been received successfully).
Configuration and status information are sent via the 4-wire SPI interface as described
in Chapter 2.5.5. The configuration data determines the behavior of the receiver, which
comprises
• scheduling the inactive power-saving phases as well as the active receive phases,
• selecting the properties of the RF/IF interface configuration (e.g. carrier frequency
selection, filter settings),
• configuring the properties of the frames (e.g. wake-up patterns, Telegram Start
Identifier (TSI), and optionally specifying the position, format and content of patterns
within packets that stimulate a certain, configurable alerting behavior (Message ID)).
Note that the TDA5240 receiver IC supports reception of multiple configuration sets on
multiple channels in a time-based manner without reconfiguration. Thus, the RF/IF
interface as well as the frame format properties support alternative settings, which can
be activated autonomously by the receiver as part of the scheduling process.
In contrast to the high-level interface used for communicating configuration instructions
and status information, alerts are emitted by the receiver on a digital output pin that may
trigger external interrupts in the Application Controller. Note that the alerting conditions
as well as the polarity of the output pin are configurable, see Chapter 2.5.4.
Data Sheet
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TDA5240
Functional Description
2.5.1.2 Data Interface
The data interface between the Application Controller and the TDA5240 receiver IC is
used for the transport of the received data, see Figure 44. The physical implementation
as well as the features of the data interface depend on the selected mode of operation.
There are 5 possible receive modes:
• Packet Oriented FIFO Mode (POF)
• Packet Oriented Transparent Payload Mode (POTP)
• Transparent Mode - Chip Data and Strobe (TMCDS)
• Transparent Mode - Matched Filter (TMMF)
• Transparent Mode - Raw Data Slicer (TMRDS)
Access points for these receive modes can be seen in Figure 15.
The possible combinations of receive modes and polling mode setup is noted in
Figure 45.
Figure 45
Receive Modes
Packet Oriented FIFO Mode (POF)
In Packet Oriented FIFO Mode, data is transferred via the 4-wire SPI bus. During receive
operation, the incoming RF signal is demodulated in the RF/IF interface, the line
decoding is performed and the data, of which wake-up frames, data frame headers and
optional footers have been stripped off, is stored in the RX FIFO. Then, the received data
can be read from the RX FIFO using the “read FIFO” command described in
Data Sheet
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TDA5240
Functional Description
Chapter 2.5.2 and Chapter 2.5.5. The data which is read from the RX FIFO is
accompanied by information which contains the status of the respective receive
operation. Note that the availability of received data packets is communicated via alerts
in the control interface.
TDA5240
data
interface
RX FIFO
RX data
line decoder
framer
bit
synchronizer
scheduler
Figure 46
Data interface for the Packet Oriented FIFO Mode
Packet Oriented Transparent Payload Mode (POTP)
This mode is very similar to POF Mode as data which is going into FIFO is also available
via RXD and RXSTR signals (see Chapter 2.5.3 Digital Output Pins).
TDA5240
RX FIFO
line decoder
framer
data
interface
bit
RX data
Strobe
synchronizer
scheduler
Figure 47
Data interface for the Packet Oriented Transparent Payload Mode
In the TDA5240, there are specific digital output lines (PPx pin) for the Bi-phase decoded
data and an appropriate Strobe signal. During inactivity of the receiver, the line is in
default mode switched to low.
Data Sheet
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TDA5240
Functional Description
In default mode the Strobe signal is active high and has a delay of TBIT/16 relative to the
data bit and a duration of TBIT/2. The polarity of the Strobe signal is programmable, this
can be done via PPCFG2 register.
RXD
Dn
Dn+1
RXSTR
TBIT/16
TBIT/2
Figure 48
Timing of the Packet Oriented Transparent Payload Mode
Transparent Mode - Chip Data and Strobe (TMCDS)
The receiver’s simple plain data interface in this Transparent Mode is shown in
Figure 49. In this mode, the demodulated data signal is made directly available on the
data output pin of the data interface. Concurrently, an estimate of the chip clock is
optionally provided on the respective clock output line. Note that a sensible chip clock
can only be generated if the selected line encoding exhibits a constant chip rate. The
chip clock generation can be significantly improved by using a run-in signal of alternating
one-zero chips (maximum number of transitions within a data stream).
data
interface
TDA5240
RX data
RX chip strobe
bit
synchronizer
scheduler
Figure 49
Data interface for the Transparent Mode - Chip Data and Strobe
In the TDA5240, there is a specific digital output line for the chip clock estimate as well
as for the data output line, which delivers the encoded chip data. During inactivity of the
receiver, the line is in default mode switched to low.
The PPx pin provides the estimated chip clock, if CH_STR is selected. Further details
are given in Chapter 2.5.3.
Data Sheet
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TDA5240
Functional Description
In default mode the CH_STR signal is active high and has a delay of TCHIP/8 relative to
the data chip and a duration of TCHIP/2. The polarity of the CH_STR signal is
programmable, this can be done via PPCFG2 register.
CH_DATA
CH_STR
Dn
Dn+1
TCHIP/8
TCHIP/2
Figure 50
Timing of the Transparent Mode - Chip Data and Strobe
Transparent Mode - Matched Filter (TMMF)
The received data after the Matched Filter (Two-Chip Matched Filter) with an additional
SIGN function is provided via the DATA_MATCHFIL signal (PPx pin). In this mode
sensitivity measurements with ideal data clock can be performed very simple. For further
details see the block diagram in Figure 15.
Sensitivity in this transparent mode is significantly depending on the implemented clock
and data recovery algorithm of the user software in the application controller.
data
interface
TDA5240
RX data
scheduler
Figure 51
Data interface for the Transparent Modes TMMF / TMRDS
Transparent Mode - Raw Data Slicer (TMRDS)
This mode supports processing of data even without bi-phase encoding (e.g. NRZ
coding) by providing the received data via the One-Chip Matched Filter on the DATA
signal (PPx pin). See more details in the block diagram in Figure 15.
Data Sheet
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TDA5240
Functional Description
Sensitivity in this transparent mode is significantly depending on the implemented clock
and data recovery algorithm of the user software in the application controller.
The data interface can be seen from Figure 51.
Self Polling capabilities are possible as well, but only Constant On-Off Mode and Wake-
up on RSSI makes sense. Assume one of the TDA5240 configurations (e.g.
Configuration B) is set for external data processing mode. See also example in
Figure 52. The needed On time (latency through TDA5240) is configured in the
corresponding On time registers of the chip. The interrupt for Wake-Up Config B (WUB)
is enabled and suitable RSSI thresholds are set.
If the RSSI signal is in a valid threshold area, the TDA5240 changes to Run Mode Self
Polling and an interrupt can be signaled to the Application Controller.
In case the RSSI signal is outside the valid threshold area, the chip stays in Self Polling
Mode and the external controller gets no interrupt (as the desired RSSI level is not
reached).
It should be mentioned that all Timeout Timers (TOTIMs) should be disabled in the
configuration set of the external processing mode as the microcontroller takes over the
control (see SFR bit group EXTPROC in the x_CHCFG register).
It is recommended to put this external configuration at the end of the On time within the
polling cycle (so right before the Off time). This is helpful when using the "EXTTOTIM"
command (goto Self Polling Mode, next programmed channel or Configuration A; see
Figure 77). When the external configuration is the last configuration before the Off time,
then the next programmed channel within the polling cycle would be the sequence of the
Off time.
When data is available and the RSSI is within a valid threshold area, an interrupt is
generated (NINT). So the Application Controller can process the data and decide about
valid data.
In case the controller decides that wrong data was sent, the microcontroller can send the
register command "EXTTOTIM" (see Figure 77 and EXTPCMD register).
When the microcontroller detects valid data, then the controller can send the register
command "EXTEOM found" (see Figure 77 and EXTPCMD register) after completing
the data reception.
The functionality described above can also be used for other receive modes (mainly
TMMF, TMCDS), where the external microcontroller takes on responsibility for further
data processing.
Data Sheet
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TDA5240
Functional Description
SelfPolling Mode
SelfPolling scenario
ConfigA
ConfigB
OFF-time
Sleep Mode
RSSI level too low Î
Chip stays in Self Polling Mode
and sends no interrupt
Interrupt signal
for RSSI
RunMode SelfPolling
SelfPolling / Sleep
Interrupt signal
for RSSI
RunMode SelfPolling
SelfPolling / Sleep
µC detects invalid data and sends
„EXTTOTIM“Î goto SPM
Interrupt signal
for RSSI
µC finished data reception,
sends „EXTEOM found“
RunMode SelfPolling
SelfPolling / Sleep
Figure 52
External Data Processing
The SFR bit group EXTPROC in the x_CHCFG register can be activated for each
configuration set for an easier handling of external data processing by the Application
Controller. Depending on the intended transparent receive mode an activation of this
function means:
• Data path in front of Framer Unit is no longer closed (so that no data is going into
Framer Unit accidentally)
• Interrupts for FSync, MID and EOM are deactivated internally
• Some/all TOTIM counters are deactivated
• Some/all Wake-up on Data Criteria are disabled
• Wake-up on Signal Recognition is/is not disabled
Data Sheet
81
V4.0, 2010-02-19
TDA5240
Functional Description
2.5.2
Receive FIFO
The Receive FIFO is the storage of the received data frames and is only used in the POF
Mode. It is written during data reception. The host microcontroller is able to start reading
via SPI right after frame sync (interrupt) or in the most common case right after detection
of EOM (interrupt). The FIFO can store up to 256 received data bits. If the expected data
transmission contains more bits (note that in TSI 8-bit Extended Mode one bit is added
in front of the real payload to indicate which of the two TSI pattern has matched), reading
from FIFO must start a certain time after frame sync to prevent an overrun.
Architecture
The 256-bit receive FIFO is based on a bit-addressable 2-port memory architecture.
Data
from
Digital-
Receiver
Write-Port
Write Address
Pointer
(Up-Counter)
Bit-Address
In
1 of 16 Decoder
Data Clock
ENABLE
RESET
byte
byte
byte
byte
byte
byte
byte
byte
byte
0
1
2
3
4
5
6
7
8
byte 16
byte 17
byte 18
byte 19
byte 20
byte 21
byte 22
byte 23
byte 24
256-bit
Memory-Array
byte
9
byte 25
byte 26
byte 27
byte 28
byte 29
byte 30
byte 31
byte 10
byte 11
byte 12
byte 13
byte 14
byte 15
from FSM
INITFIFO
Read Address
Pointer
(Up-Counter)
FSINITFIFO
InitFIFO
16 to 1 MUX
Out
Bit-Address
Read-Port
SCLK
RESET
ENABLE
to
SPI-Bus
FIFO-Overflow
# of Valid Bits
from FSync
Digital-
FIFO-
Controller
EOM
SDO
Receiver
SDO-Frame
Generator
FIFOLK
fifolk
to FSM
Figure 53
Receive FIFO
The write port is controlled by the Digital Receiver using the Write Address Pointer.
Writing data into the FIFO starts with the detection of a TSI. The Write Address Pointer
is incremented with each data clock signal generated by the Digital Receiver. The read
port is controlled by the SPI controller using the Read Address Pointer. Each bit read
from the SPI controller increments the Read Address Pointer. The Read and Write
Address Pointers jump from their maximum value (255d) to address zero. Writing to the
FIFO stops at EOM or after Sync loss.
Data Sheet
82
V4.0, 2010-02-19
TDA5240
Functional Description
FIFO Lock Behavior
The FIFO possesses a lock mechanism that is enabled via the SFR control bit FIFOLK
in the CMC1 register. If this mechanism is enabled, the FIFO will enter a FIFO Lock state
at the detection of the EOM criterion. During the time that the FIFO is locked, it is not
possible to receive additional data in Run Mode Self Polling. This means that it is only
possible to detect another wake-up in the Self Polling Mode, but no more data in the Run
Mode Self Polling. This will guarantee that only the first complete data packet is stored
in the FIFO. Enabling FIFOLK also locks the digital receive chain at EOM until release
from FIFO lock state.
The FIFO will remain locked unless one of three conditions occurs:
1.) The remaining contents of the FIFO are completely read out via the SPI
2.) The SFR control bit FIFOLK is cleared
3.) INITFIFO at Cycle Start is set in the CMC1 register and
a) FSM is switched to Run Mode Slave or
b) FSM switches from Self Polling Mode to Run Mode Self Polling
INITFIFO (Init Fifo@ Cycle Start) = 1
Accept Data
EOM=0
Write Data into FIFO
EOM=1
EOM=1
FIFOLK=0
FIFOLK=1
FIFO Lock
FIFO Empty = 0
FIFOLK=1
Wait till FIFO is empty
FIFOLK=0
FIFO Empty=1
Figure 54
FIFO Lock Behavior
Data Sheet
83
V4.0, 2010-02-19
TDA5240
Functional Description
FIFO Status Word
The FIFO Status Word is attached at the end of a FIFO SPI transmission, and shows if
there was an overflow, and how many valid data bits were transmitted. The number of
valid FIFO bits is indicated at bit positions S0 to S5. S6 of the Status Word is always
undefined.
SDI
I7 I6
I1 I0
32 FIFO Bits
Status Word
high impedance Z
D0
D1
D30 D31 S7
S6
S1
S0
SDO
Figure 55
SPI Data FIFO Read
If the Write Address Pointer outruns the Read Address Pointer, an overflow is indicated
in the FIFO Overflow Status bit in the FIFO Read Status Word at position S7. All 32 FIFO
bits and the bits S5 to S0 of the Status Word are undefined while the Overflow Status bit
is set.
If a TSI is detected after an overflow, the FIFO Overflow Status bit is cleared and the
entire receive FIFO is initialized.
Initialization
Additionally, there are two possibilities to initialize the receive FIFO.
• If the INITFIFO bit is set in the CMC1 register (“Init FIFO at Cycle Start”) the entire
receive FIFO is always initialized
a.) after switching to Run Mode Slave or
b.) switching from Self Polling Mode to Run Mode Self Polling.
• If the FSINITFIFO bit in CMC1 register is set, the entire receive FIFO is initialized
when a TSI is detected and the receive FIFO is not locked (“Init FIFO at Frame
Start”).
Last received message length
For application protocols with several payload frames and only a short pause in-
between, the microcontroller would have to read out the FIFO very fast after detection of
an EOM. Thus even slow or overloaded Application Controllers have the possibility now
to determine the end of the last message, when reading out the FIFO, while the next
payload frame gets already received and payload data is further stored in the FIFO.
Data Sheet
84
V4.0, 2010-02-19
TDA5240
Functional Description
Therefore the last received message length (e.g. after an EOM event) is stored in
register PLDLEN and the upper two bits of register RFPLLACC at TSI detection of the
next message. The upper two bits of register RFPLLACC hold the MSBs, thus a
message length of 256 up to 1023 payload bits can be depicted. A saturation of the
message length at the maximum value of 1023 is realized. Storage at TSI of the next
message ensures that even wrong payload data (e.g. if MID is not matching, no EOM
will be generated, but payload is kept in FIFO. Or EOM data length criterion is selected
only and a sync loss prevents from generating an EOM event) can be identified.
On initialization of the FIFO, the register PLDLEN and the upper two bits of register
RFPLLACC are cleared. The corresponding internal counter is cleared with every TSI
detection and initialization of the FIFO.
PLDLEN will work correctly in case:
(INITDRXES = 0) AND ( (Data rate > 22kBit/s) OR (EOM2SPM = 0) )
If the condition above is not fulfilled, then the chip internal state machine can set
PLDLEN to 0 and a correct function of PLDLEN cannot be guaranteed.
2.5.3
Digital Output Pins
As long as the P_ON pin is high, all digital output pins operate as described. If the P_ON
pin is low, all digital output pins are switched to high impedance mode.
The digital outputs PP0, PP1, PP2 and PP3 are configurable, where each of the signals
CLK_OUT, RX_RUN, NINT, a LOW level (GND) and a HIGH level, DATA,
DATA_MATCHFIL, CH_DATA, CH_STR, RXD and RXSTR can be routed to any of the
four output pins. There is only one exception, CLK_OUT is not available on PP3. The
default configuration for these four output pins can be seen in Table 1.
Each port pin can be inverted by usage of PPCFG2 register.
The RX_RUN signal is active high for all Configurations by default. It can be deactivated
for every Configuration separately. Every PPx can be configured with an individual
RX_RUN setup. This can be set in RXRUNCFG0 and RXRUNCFG1 registers.
Interfacing to 3.3V Logic:
The TDA5240 is able to interface directly to a 3.3V logic, when chip is operated in 3.3V
environment.
Interfacing to 5V Logic:
The TDA5240 is able to interface directly to a 5V logic, when chip is operated in 5V
environment.
Data Sheet
85
V4.0, 2010-02-19
TDA5240
Functional Description
EMC Reduction of Digital I/Os:
Because electromagnetic distortion generated by digital I/Os may interfere with the high
sensitivity radio receiver, it is recommended that all inputs are filtered by adding an RC
low pass circuit.
2.5.4
Interrupt Generation Unit
The TDA5240 is able to signal interrupts (NINT signal) to the external Application
Controller on one of the PPx port pins (for further details see Chapter 2.5.3 Digital
Output Pins). The Interrupt Generation Unit receives all possible interrupts and sets the
NINT signal based on the configuration of the Interrupt Mask registers (IM0 and IM1).
The Interrupt Status registers (IS0 and IS1) are set from the Interrupt Generation Unit,
depending on which interrupt occurred. The polarity of the interrupt can be changed in
the PPCFG2 register. Please note that during power up and brownout reset, the polarity
of NINT signal is always as described in Chapter 2.4.9.2 Chip Reset.
A Reset event has the highest priority. It sets all bits in the Status registers to “1” and
sets the interrupt signal to “0”. The first interrupt after the Reset event will clear the Status
registers and will set the interrupt signal to “1”, even if this interrupt is masked.
A Wake-up interrupt clears the FsyncA, FsyncB, FsyncC, FsyncD and the
complementary Wake-up flag. An Fsync interrupt clears the EOMA, EOMB, EOMC,
EOMD, MIDA, MIDB, MIDC, MIDD and the complementary Fsync flags.
The Interrupt Status register is always cleared after read out via SPI.
It is not possible to disable the Power On Reset Indicator Interrupt using the Interrupt
Mask registers.
Some interrupts are not usable depending on the selected receive mode, which is
described in Chapter 2.5.1.2 Data Interface.
Interrupts for WU can be used in all receive modes.
Interrupts for FSync, MID and EOM can only be used in the receive modes POTP and
POF.
Data Sheet
86
V4.0, 2010-02-19
TDA5240
Functional Description
IS1 + IS0
IM1 + IM0
Reset
Interrupt-Mask
NINT
Interrupt-Signalling
NINT signal
Figure 56
Interrupt Generation Unit
RESET
PP2_select=NINT
PP2INV
SPI READ IS0
IS0
X
FF
01
03
07
0F
1C
30
70
F0
00
PP2(NINT)
WU(A,B)
FSYNC(A,B)
MID(A,B)
EOM(A,B)
ConfigA
ConfigB
Figure 57
Interrupt Generation Waveform (Example for Configuration A+B)
Data Sheet
87
V4.0, 2010-02-19
TDA5240
Functional Description
The following handling mechanism for read-clear registers was chosen due to
implementation of the Burst Read command:
• the current Interrupt Status (ISx) register 8-bit content is latched into the SPI shift
register after the last address bit is clocked-in (point A in Figure 58)
• the IS register is then cleared after last IS register bit is clocked out of the SPI
interface (point B in Figure 58)
Consequence: any interrupt event occurring in the window-time between points A and B
is cleared at point B and not stored/shown in an later readout of ISx.
(However: NINT signal is toggling in any case, if occurring interrupt is not masked in IMx
register)
A
B
8-bit @2MHz = 4us
irq1 (masked?)
irq2 (masked?)
nint
ncs
read/readb data = IS(t+0)
SPI IF
inst
addr
read/capture IS*
content
SFR IS* read clear
@end of data frame
SFR IS* IS(t-1)
IS(t+0)
IS(t+1) 0x00
NOTE:
SFR IS(j) status flag is cleared
before it can be read if an IRQ
occurs during SPI data frame
Figure 58
ISx Readout Set Clear Collision
Please see also the IMPORTANT NOTE in the Burst Read section !
Data Sheet
88
V4.0, 2010-02-19
TDA5240
Functional Description
2.5.5
Digital Control (4-wire SPI Bus)
The control interface used for device control and data transmission is a 4-wire SPI
interface.
•
•
•
NCS - select input, active low
SDI - data input
SDO - data output
• SCK - clock input: Data bits on SDI are read in at rising SCK edges and written out
on SDO at falling SCK edges.
Level definition:
logic 0 = low voltage level
logic 1 = high voltage level
Note for non-Burst modes: It is possible to send multiple frames while the device is
selected. It is also possible to change the access mode while the device is selected by
sending a different instruction.
Note: In all bus transfers MSB is sent first, except for the received data read from the
FIFO. There the bit order is given as first bit received is first bit transferred via the bus.
To read from the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
data byte at this address is then shifted out on SDO. After completing the read operation,
the master sets the NCS line to high.
NCS
Frame
Frame
1
8
1
8
1
8
1
8
1
8
1
8
SCK
SDI
Instruction
Register Address
Instruction
Register Address
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
Data Out
high impedance Z
SDO
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 59
Read Register
Data Sheet
89
V4.0, 2010-02-19
TDA5240
Functional Description
To read from the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first), the slave unit
will respond by transferring the register contents beginning from the given start address
(MSB first). Driving the NCS line to high will end the Burst frame.
NCS
1
8
1
8
1
8
1
8
1
8
SCK
SDI
Instruction
Register Start Address
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out(i)
Data Out (i+1)
Data Out (i+x)
high impedance Z
SDO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7
D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 60
Burst Read Registers
IMPORTANT NOTE - for being upwards compatible with further versions of the
product, we give following strong recommendation:
For read-clear registers at address (N), no read-burst access stopping at address
(N-1) is allowed, because read-clear register will be cleared without being read out.
Use single read command to read out the register at address (N-1) or extend the
burst read to include the read-clear register at address (N).
To write to the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
following data byte is then stored at this address.
After completing the writing operation, the master sets the NCS line to high.
Additionally the received address byte is stored into the register SPIAT and the received
data byte is stored into the register SPIDT. These two trace registers are readable.
Therefore, an external controller is able to check the correct address and data
transmission by reading out these two registers after each write instruction. The trace
registers are updated at every write instruction, so only the last transmission can be
checked by a read out of these two registers.
Data Sheet
90
V4.0, 2010-02-19
TDA5240
Functional Description
NCS
Frame
Frame
1
8
1
8
1
8
1
8
1
8
1
8
SCK
SDI
Instruction
Register Address
Data Byte
Instruction
Register Address
Data Byte
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
high impedance Z
SDO
Figure 61
Write Register
To write to the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first) the successive
data bytes will be stored into the automatically addressed registers.
To verify the SPI Burst Write transfer, the current address (start address, start address
+ 1, etc.) is stored in register SPIAT and the current data field of the frame is stored in
register SPIDT. At the end of the Burst Write frame the latest address as well as the
latest data field can be read out to verify the transfer. Note that some error in one of the
intermediate data bytes can not be detected by reading SPIDT.
Driving the NCS line to high will end the Burst frame.
A single SPI Burst Write command can be applied very efficiently for data transfer either
within a register block of configuration dependent registers or within the block of
configuration independent registers.
NCS
1
8
1
8
1
8
1
8
1
8
SCK
SDI
Instruction
Register Start Address
Data Byte (i)
Data Byte (i+1)
Data Byte (i+x)
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
high impedance Z
SDO
Figure 62
Burst Write Registers
Data Sheet
91
V4.0, 2010-02-19
TDA5240
Functional Description
The SPI also includes a safety feature by which the checksum is calculated with an
XOR operation from the address and the data when writing SFR registers. The
checksum is in fact an XOR of the data 8-bitwise after every 8 bits of the SPI write
command. The calculated checksum value is automatically written in the SPICHKSUM
register and can be compared with the expected value. After the SPICHKSUM register
is read, its value is cleared.
In case of an SPI Burst Write frame, a checksum is calculated from the SPI start address
and consecutive data fields.
enable every 8 bit
read/clear
SPI shift register
XOR
Checksum SFR
Figure 63
SPI Checksum Generation
To read the FIFO, the SPI master has to select the SPI slave unit first. Therefore, the
master must set the NCS line to low. After this, the instruction byte is shifted in on SDI
and stored in the internal instruction register. The data bits of the FIFO are then shifted
out on SDO. The following byte is a status word that contains the number of valid bits in
the data packet. After completing the read operation, the master sets the NCS line to
high.
NCS
Frame
Frame
1
8
1
32
1
8
1
8
1
32
1
8
SCK
SDI
Instruction
Instruction
I7 I6
I1 I0
I7 I6
I1 I0
32 FIFO Bits
Status Word
32 FIFO Bits
Status Word
high impedance Z
D0
D1
D30 D31 S7
S6
S1
S0
D0
D1
D30 D31 S7
S6
S1
S0
SDO
Figure 64
Read FIFO
Table 4
Instruction
WR
Instruction Set
Description
Instruction Format
0000 0010
Write to chip
RD
Read from chip
Read FIFO from chip
Write to chip in Burst mode
0000 0011
RDF
0000 0100
WRB
0000 0001
RDB
Read from chip in Burst mode 0000 0101
Data Sheet
92
V4.0, 2010-02-19
TDA5240
Functional Description
2.5.5.1 Timing Diagrams
tDeselect
NCS
tnot_hold
tSetup
tCL K_H
thold
tnot_setup
SCK
tSDI_setup
tSDI_hold
tCLK_L
SDI
high impedance Z
SDO
Figure 65
Serial Input Timing
NCS
SCK
SDO
tCLK_H
tSDO_disable
tCLK_SDO
tCLK_SDO
tCLK_L
tSDO_r
tSDO_f
Z
Z
SDI
ADDR LSB
Figure 66
Serial Output Timing
Data Sheet
93
V4.0, 2010-02-19
TDA5240
Functional Description
Table 5
Symbol
fclock
SPI Bus Timing Parameter
Parameter
Clock frequency
Clock High time
Clock Low time
tCLK_H
tCLK_L
tsetup
Active setup time
Not active setup time
Active hold time
Not active hold time
Deselect time
tnot_setup
thold
tnot_hold
tDeselect
tSDI_setup
tSDI_hold
tCLK_SDO
tSDO_r
SDI setup time
SDI hold time
Clock low to SDO valid
SDO rise time
tSDO_f
SDO fall time
tSDO_disable
SDO disable time
2.5.6
Chip Serial Number
Every device contains a unique, preprogrammed 32-bit wide serial number. This number
can be read out from SN3, SN2, SN1 and SN0 registers via the SPI interface. The
TDA5240 always has SN0.6 set to 1 and SN0.5 set to 1.
Fuses
SN0
SN1
SN2
SN3
Fuse-
Readout-
Interface
Figure 67
Chip Serial Number
Data Sheet
94
V4.0, 2010-02-19
TDA5240
Functional Description
2.6
System Management Unit (SMU)
The System Management Unit consists of two main units:
•
•
Master Control Unit, where the various operating modes can be configured.
Polling Timer Unit, where the receiver’s On and Off times and modes are defined.
The Polling Timer Unit is only working in the Self Polling Mode.
2.6.1
Master Control Unit (MCU)
2.6.1.1 Overview
The Master Control Unit controls the operation modes, the global states, and is generally
responsible for automating data reception, verification, identification, extraction, and
storage into the FIFO. The payload data without RUNIN, TSI and optional EOM can be
read from the FIFO via SPI by the external microcontroller.
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
The following operation modes and the behavior of the Master Control Unit are fully
automatic and only influenced by SFR settings and by incoming RF data streams.
The TDA5240 has two major operation modes, which are switched by SFR bit MSEL.
In Slave Mode the device is controlled via SPI by the external microcontroller. This mode
supports:
•
•
Run Mode Slave (RMS), where the receiver is continuously active
SLEEP Mode, where the receiver is switched off for power saving. This mode can
also be used to change register settings
•
HOLD Mode, allows register settings to be changed. The change to HOLD Mode and
back to RMS is faster than changing to SLEEP Mode and back to RMS.
In Slave Mode, switching between configurations and channels, as well as between Run
and SLEEP Mode must be initiated by the microcontroller.
In Self Polling Mode, TDA5240 autonomously polls for incoming RF signals. The
receiver switches automatically between up to four configurations (Configuration A, B, C
and D) and up to 3 channels per configuration (Further information can be found in
Chapter 2.6.2).
Between the RF signal scans, the receiver is automatically switched to Low Power Mode
for reducing the average power consumption. If an incoming signal fulfills the selected
wake-up criterion an interrupt can be generated and Run Mode Self Polling will be
entered. If the following received data matches to the TSI pattern, and passes the
optional message ID screening, the payload is loaded into the FIFO, and, if not masked,
an interrupt is generated. Then the payload data can be read via SPI.
Data Sheet
95
V4.0, 2010-02-19
TDA5240
Functional Description
Init
Reset
Initialize RX-Part
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == 0
or
Run Mode
Slave
Bit:MSEL == 1
Sleep Mode
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == 0
Bit:MSEL == 0
Chip is permanently
active
Chip is idle
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
Init
Initialize RX-Part
Bit:SLRXEN == X
Bit:MSEL == 0
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
ToTim Timeout== X
Self Polling
Mode
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 0
Chip is periodically active
and searching for
WU criteria
Bit:SLRXEN == X
Bit:MSEL == 1
EOM2SPM == 1
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 1
ToTim Timeout == 1
Run Mode
Self Polling
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 0
Chip is permanently
active
Figure 68
Global State Diagram
2.6.1.2 Run Mode Slave (RMS)
In Run Mode Slave, the receiver is able to continuously scan for incoming data streams.
Detection and validation of a wake-up criterion are not performed, but RUNIN and TSI
are required.
Recognition of TSI and validation of the optional MID (Message IDentification) are done
automatically. The data payload is extracted from the data stream, and moved to the
FIFO.
The various recognition steps are communicated by interrupts. Interrupts can be
generated at frame-start (when a valid TSI has been detected), when a valid MID has
been found and at EOM (End of Message).
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
Run Mode Slave is entered by setting SFR CMC0 bits MSEL to 0 and SLRXEN to 1.
Data Sheet
96
V4.0, 2010-02-19
TDA5240
Functional Description
Configurations are switched via SFR bit group MCS in the CMC0 register. The RF
channel in use can be selected in the x_CHCFG register, the frequency selection is
defined by SFRs x_PLLINTCy, x_PLLFRAC0Cy, x_PLLFRAC1Cy, x_PLLFRAC2Cy,
where x = A, B, C or D and y = 1, 2 or 3.
The configuration may be changed only in SLEEP or in HOLD Mode before returning to
the previously selected operation mode. This is necessary to restart the state machine
with defined settings at a defined state. Otherwise the state machine may hang up.
Reconfigurations in HOLD Mode are faster, because there is no Start-Up sequence.
The following flowchart and explanation show and help to understand the internal
behavior of the Finite State Machine (FSM) in Run Mode Slave.
Data Sheet
97
V4.0, 2010-02-19
TDA5240
Functional Description
0
1
Wait
Startup Finished == 0
Wait Till Startup
Has Finished
Startup Finished == 1
4
INIT
FIFO locked
fifolk == 1
Init FIFO=Init FIFO@Cyc.
EXTPROC==00
Wait Till FIFO Read Out
Symbol Sync ==0
INITDRXES==1
fifolk == 0
2
fifolk == 1
INIT
fifolk == 0
INITDRXES==1
Init Digital Receiver
Symbol Sync ==0
INITDRXES==0
3
fifolk == 0
Wait
Symbol Sync == 0
INITDRXES==0
Wait Till Symbol
Synchronization
Is Found
Generating A Frame Start
Interrupt If Not Masked
Symbol Sync == 1
EXTPROC<>10
Hold == 0
12
5
Wait
Hold
Frame Sync == 0
Hold == 1
Wait Till Frame Start
Is Found
Ready for
reconfiguration
Frame Sync == 1
EXTPROC==00
6
7
INIT FIFO
Init FIFO=
Init FIFO@FSYNC
Check
MID Screening enable == 0
MID Setup
Check The MID Setup
Register
MID Screening enable == 1
8
9
Init MID
Scanning Unit
Initialize The MID
Scanning Unit
MID Scanning Finished == 0
Wait
Store RX Data Into FIFO
Wait For Scan Finish
Generating A MID Found
Interrupt If Not Masked
MID Scanning Finished == 1
10
Checking ID
Scanning Result
Store RX Data Into FIFO
Analyze The Scanning
Result
MID Found== 0
Generating A EOM Interrupt If
Not Masked
MID Found=1
11
EOM Check
EOM Found == 1
Store RX Data Into FIFO
Check For EOM
EOM Found == 0
Figure 69
Run Mode Slave
Data Sheet
98
V4.0, 2010-02-19
TDA5240
Functional Description
2.6.1.3 HOLD Mode
This state (item 12 in Figure 69) is used for fast reconfiguration of the chip in Run Mode
Slave. This state can be reached after the Start-Up Sequencer and Initialization of the
chip have been completed from any state from 3 to 11. To reconfigure the chip the SFR
control bit HOLD must be set. After reconfiguration in this state the SFR control bit HOLD
must be cleared again. After leaving the HOLD state, the INIT state is entered and the
receiver can work with the new settings. Be aware that the time between changing the
configuration and reinitialization of the chip has to be at least 40us. Take note that one
SPI command for clearing the SFR control bit HOLD needs 24 bits or 12μs at an SPI
data rate of 2.0Mbit/s. The remaining 28μs must be guaranteed by the application.
Wait till
SSync
EOM-Check
HOLD
INIT
FSM State
Instruction Address
Data
HOLD=1
Instruction Address
Write
0x02
Data
x_CHCFG/ (sel. other
x_PLL.. channel)
Instruction Address
Data
HOLD=0
Write
0x02
CMC0
Write
0x02
CMC0
SPI Command
12us @ 2.0MHz
40us
Figure 70
HOLD State Behavior (INITPLLHOLD disabled)
In case of large frequency steps, an additional VAC routine (VCO Automatic Calibration)
has to be activated when recovering from HOLD Mode (INITPLLHOLD bit). The
maximum allowed frequency step in HOLD Mode without activation of VAC routine is
depending on the selected frequency band. The limits are +/- 1 MHz for the 315 MHz
band, +/- 1.5 MHz for the 434 MHz band and +/- 3 MHz for the 868/915 MHz band.
When this additional VAC routine is enabled, the TDA5240 starts initialization of the
Digital Receiver block after release from HOLD and an additional Channel Hop time.
Wait till
SSync
EOM-Check
HOLD
VAC
VAC
INIT
FSM State
Instruction Address
Data
HOLD=1
Instruction Address
Write
0x02
Data
x_CHCFG/ (sel. other
x_PLL.. channel)
Instruction Address
Data
HOLD=0
Write
0x02
CMC0
Write
0x02
CMC0
SPI Command
tC_Hop
12us @ 2.0MHz
40us
Figure 71
HOLD State Behavior (INITPLLHOLD enabled)
HOLD Mode is only available in Run Mode Slave. Configuration changes in Self Polling
Mode have to be done by switching to SLEEP Mode and returning to Self Polling Mode
after reconfiguration.
Data Sheet
99
V4.0, 2010-02-19
TDA5240
Functional Description
2.6.1.4 SLEEP Mode
The SLEEP Mode is a power save mode. The complete RF part is switched off and the
oscillator is in Low Power Mode. As in HOLD Mode, the chip can be reconfigured. When
switching from SLEEP to Run Mode Slave, the state machine starts with the internal
Start-Up Sequence.
2.6.1.5 Self Polling Mode (SPM)
In Self Polling Mode TDA5240 autonomously polls for incoming RF wake-up data
streams. There is no processing load on the host microcontroller. When a wake-up
criterion has been found, an interrupt can be generated and the TDA5240 mode is
changed to Run Mode Self Polling for automatic verification of TSI, optional MIDs and
for transfer of payload data into the FIFO.
A general overview on a typically transmitted protocol and the behaviour of the TDA5240
is given in Figure 72.
TX - RX interaction in RX - Self Polling Mode
TX Telegram:
1)
Wake-up Frame
Wake-up Frame continued or Gap
Data Frame
PAYLOAD
RUNIN + Wake-up sequence
(RUNIN)
TSI
EOM
RX Mode:
On time 2)
Self Polling Mode
On time 2)
Self Polling Mode
a
b
Run Mode Self Polling
Legend:
1) There can either be a Wake -up Frame directly followed by a Data Frame or the Wake -up Frame is separated from the Data Frame by a Gap in -between.
2) The position of the On time can vary (a, b, ...) as there is no synchronization between transmitted telegram and start of the receiver’s On time.
Figure 72
SPM - TX-RX Interaction
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
Self Polling Mode is entered by setting the MSEL register bit to 1.
Configuration changes are allowed only by switching to SLEEP Mode, and returning to
Self Polling Mode after reconfiguration.
Data Sheet
100
V4.0, 2010-02-19
TDA5240
Functional Description
The Polling Timer Unit controls the timing for scanning (On time) and sleeping (Off
time, SPM_OFF). Up to four independent configuration sets (A, B, C and D) can
automatically be processed, thus enabling scanning from different transmit sources.
Additionally, up to 3 different frequency channels within each configuration may be
scanned to support Multi-Channel applications. See also Chapter 2.6.2 Polling Timer
Unit. So a total number of up to 12 different frequency channels is supported.
The Wake-Up Generation Unit identifies, whether an incoming data stream matches
the configurable wake-up criterion.
After fulfillment of the wake-up criterion, modulation can be switched automatically.
See also Chapter 2.6.1.6 Automatic Modulation Switching, Chapter 2.4.8.5 Wake-
Up Generator and Chapter 2.5.1.2 Data Interface (in Subsection TMRDS).
The following state diagrams and explanations help to illustrate the behavior during Self
Polling Mode. First there is a search for a wake-up criterion according to Configuration
A on up to three different channels. Then, there is an optional search for a wake-up
criterion according to Configuration B, C and D, again including up to 3 channels.
In applications using only Single-Configuration, settings are always taken from
Configuration A.
Data Sheet
101
V4.0, 2010-02-19
TDA5240
Functional Description
RX_RUN=0
RX_RUN == 0
1
IDLE
Permanent WU Search Mode Enable== 0
Chip is idle
RX_RUN == 1
2
Wait
Startup Finished == 0
Wait Till Startup
Has Finished
From Run Mode Self Polling
Startup Finished == 1
Init
3
4
5
Loop Counter
CfgLoopCounter,
Loop Counter
is Initialized
Permanent WU Search Mode Enable== 1
Modulation
Switching CFG A
Modulation Selection
Depending On Register
Setting
WU Search With
Configuration A
Init With
CFG A
Initialize RX-Part
Configuration A
Loop Counter== 10
Loop Counter == 11
Load
Channel 1
Load
Channel 2
Load
Channel 3
6
11
11
Initialize RX-Part
Multi Channel A
Initialize RX-Part
Multi Channel A
Initialize RX-Part
Multi Channel A
Permanent WU Search Mode Enable== 0
Permanent WU Search Mode Enable== 1
Const On Time
Fast Fall Back To Sleep
7
7
WU Search
CFG A FFTS
Search For A Configurated
Wake Up Criteria
WU Search
CFG A COOT
Search For A Configurated
Wake Up Criteria
WU Search Finished == 0
ON Time elapsed == 0
WU Found== 0
Fast Fall Back
Const On Off
ON Time elapsed == 1
WU Found == 0
WU Search Finished == 1
WU Found == 1
WU Search Finished == 1
WU Found== 0
ON Time elapsed == X
WU Found == 1
9
10
Increment
Loop Counter
Compare
Loop Counter <> ANOC
Compare Loop Counter
Against Number Of
Channels
Incrementation Of
The Loop Counter
Loop Counter Equal ANOC == 1
CfgLoopCounter <> CfgNr
Loop Counter == ANOC
CfgLoopCounter== CfgNr
8
Store
Channel
Store The Current Channel
Configuration Into Actual
Channel Register
Generating WU CFG A
Interrupt If Not Masked
12
Run Mode
Self Polling
Chip is permanently
active
To Init Loop Counter
of Config B
From Compare of
Config B, C, D
Figure 73
Wake-up Search with Configuration A
Data Sheet
102
V4.0, 2010-02-19
TDA5240
Functional Description
To Init Loop
Counter / Idle of
Config A
From Compare of
Config A, B, C
WU Search With
Configuration B, C, D
3
4
Init
Loop Counter
Loop Counter Is
Initialized
Modulation
Switching CFG B,C,D
Modulation Selection
Depending On Register
Setting
5
Init With
CFG B,C,D
Initialize RX-Part
Configuration B,C,D
Loop Counter== 10
Loop Counter== 11
6
11
11
Load
Load
Load
Channel 1
Channel 2
Channel 3
Initialize RX-Part
Initialize RX-Part
Initialize RX-Part
Multi Channel B,C,D
Multi Channel B,C,D
Multi Channel B,C,D
Permanent WU Search Mode Enable == 0
Permanent WU Search Mode Enable== 1
Const On Time
Fast Fall Back To Sleep
7
7
WU Search
WU Search
ON Time elapsed == 0
WU Found == 0
CFG B,C,D COOT
Search For A Configurated
Wake Up Criteria
CFG B,C,D FFTS
Search For A Configurated
Wake Up Criteria
WU Search Finished == 0
Const On Off
Fast Fall Back
ON Time elapsed == X
WU Found== 1
ON Time elapsed == 1
WU Found == 0
WU Search Finished == 1 WU Search Finished == 1
WU Found == 1
WU Found == 0
9
10
Increment
Loop Counter
Compare
Loop Counter <> (B,C,D)NOC
Compare Loop Counter
Against Number Of
Channels
Incrementation Of
The Loop Counter
Loop Counter Equal(B,C,D)NOC == 1
CfgLoopCounter<> CfgNr
Loop Counter== (B,C,D)NOC
CfgLoopCounter == CfgNr
8
Store
Channel
Store The Current Channel
Configuration Into Actual
Channel Register
Generating WU CFG B ,C,D
Interrupt If Not Masked
12
Run Mode
Self Polling
Chip is permanently
active
To Init Loop Counter
of Config C,D
Figure 74
Wake-up Search with Configuration B, C, D
Data Sheet
103
V4.0, 2010-02-19
TDA5240
Functional Description
2.6.1.6 Automatic Modulation Switching
In Self Polling Mode, the chip is able to automatically change the type of modulation
after a wake-up criterion was fulfilled in a received data stream. The type of modulation
used in the different operational modes is selected by the SFR control bit MT.
2.6.1.7 Multi-Channel in Self Polling Mode
As previously mentioned, in Self Polling Mode the TDA5240 allows RF scans on up to
three RF channels per configuration, this can be defined in the x_CHCFG register.
Channel frequencies are defined in registers x_PLLINTCy, x_PLLFRAC0Cy,
x_PLLFRAC1Cy, x_PLLFRAC2Cy, where x = A, B, C or D and y = 1, 2 or 3.
The channel number at which a wake-up criterion has been found is available in register
RFPLLACC. See also Chapter 2.4.5 Sigma-Delta Fractional-N PLL Block.
2.6.1.8 Run Mode Self Polling (RMSP)
The chip enters Run Mode Self Polling after a successful fulfillment of a wake-up
criterion in Self Polling Mode.
When Wake-Up criterion for RSSI or Signal Recognition (see Chapter 2.4.8.1) is
selected and fulfilled, this leads to a change to Run Mode Self Polling. This will be
interesting especially in case of a transparent data stream being processed externally by
the Application Controller (see Chapter 2.5.1.2 Data Interface).
The following steps are performed automatically, depending on register settings:
• Modulation switching (see Chapter 2.6.1.6 Automatic Modulation Switching)
• Wait for valid TSI (see Chapter 2.4.8.6 Frame Synchronization)
• Initialize FIFO (see Chapter 2.5.2 Receive FIFO) and write data to FIFO
• Scan for MIDs (see Chapter 2.4.8.7 Message ID Scanning)
Depending on interrupt masking, the host microcontroller is alerted when
• a data frame has started,
• an MID has been found, (if enabled) or
• EOM (End of Message) has been detected.
See also Chapter 2.5.4 Interrupt Generation Unit
Run Mode Self Polling is left, when synchronization is lost and the timeout timer for loss
of synchronization (TOTIM_SYNC) has elapsed, or when one of the other timeout timers
(TOTIM_TSI, TOTIM_EOM) for each configuration (A, B, C, D) has elapsed, or when an
EOM occurred and the SFR bit EOM2SPM is activated, or when the operating mode is
switched to SLEEP or Run Mode Slave by the host microcontroller.
Data Sheet
104
V4.0, 2010-02-19
TDA5240
Functional Description
Timeout timers for getting no TSI or getting no EOM within a certain time period can be
used to avoid a deadlock situation, e.g. TOTIM_TSI can be used in case an interfering
transmit signal fulfilled the wake-up criterion and keeps on transmitting, but no TSI can
be found in this data stream within a certain programmable time period. TOTIM_EOM
might be used in case EOM criterion “EOM by payload data length” cannot be applied.
The timeout timer functionality in the absence/presence of an interfering signal is shown
in Figure 75 and Figure 76.
Without interfering signal:
WU frame and Payload frame have the same modulation type
e.g. TOTIM_TSI is set to 15ms
TX signal
RX_RUN
RI TSI Payload1
RI TSI Payload2
Wake-up
WU-data Interrupt
RunMode SelfPolling
SelfPolling / Sleep
Init TOTIMs
TOTIM_SYNC
counter activity
TOTIM_TSI
counter activity
9.5ms
5ms
5ms
TOTIM_EOM
counter activity
Figure 75
TOTIM Behavior without Presence of Interferer
Data Sheet
105
V4.0, 2010-02-19
TDA5240
Functional Description
With interfering signal (interferer signal has same data rate as wanted wake-up signal):
WU frame and Payload frame have the same modulation type
e.g. TOTIM_TSI is set to 15ms
TX interferer
TX signal
RI TSI Payload2
RI TSI Payload1
Wake-up
RX_RUN
WU-data Interrupt
RunMode SelfPolling
SelfPolling / Sleep
*)
Init TOTIMs
TOTIM_SYNC
counter activity
TOTIM_TSI
counter activity
TOTIM_EOM
counter activity
*) Chip proceeds with Self Polling Mode
Figure 76
TOTIM Behavior in Presence of Interferer
On expiring of one of the timeout timers, the receiver proceeds with Self Polling Mode
and with searching for a suitable wake-up criterion on the next programmed channel
(either next RF channel or next configuration, depending on the selected mode - Multi-
Configuration or Multi-Channel or a mix of both) or a search for a wake-up criterion in
Configuration A is initiated.
As long as the chip is in Run Mode Self Polling, incoming data frames (including a
RUNIN sequence and TSI, but without necessity of additional wake-up patterns) can be
received and stored.
The data FIFO can be initialized and cleared either at
• Cycle Start, that means whenever Run Mode Self Polling is entered or
• Frame Start, when a TSI has been successfully identified (and Receive FIFO is not
locked).
Further information about the Receive FIFO can be found in the Chapter 2.5.2 Receive
FIFO.
Data Sheet
106
V4.0, 2010-02-19
TDA5240
Functional Description
After an EOM was found, the information about the RF channel and the configuration of
the actual payload data is saved in the RFPLLACC register.
After detection of EOM the TDA5240 can either proceed with a search for a wake-up
criterion in the next configuration or a search for wake-up in Configuration A can follow
or the TOTIMs of the current configuration are reloaded for being prepared to receive
another (redundant) payload data frame within the same configuration.
Alternatively, a transparent data stream can also be processed externally by the
Application Controller. Therefore the external controller needs the possibility to send
following commands, which would normally be generated by the TDA5240 itself (see
Figure 77 and EXTPCMD register as well):
• EXTTOTIM: So the TDA5240 can proceed with Self Polling Mode (either with the
next programmed channel or with Configuration A).
• EXTEOM found: In this case the TDA5240 can either proceed with Self Polling Mode
(either with the next configuration or with Configuration A) or stay in Run Mode Self
Polling.
EXTTOTIM and EXTEOM are only available, when the external processing mode is
deactivating functional blocks (see bit group x_CHCFG.EXTPROC).
When the actual processed configuration is right before the Off time and the Application
Controller sends one of the above mentioned commands, then the TDA5240 can
proceed with the Off time (in case next configuration is selected).
If the autonomous Wake-up Search with Configuration A follows a TOTIM or EOM event,
then also the Polling Timer is initialized, this means a new On period is started. In case
the Wake-up Search is started with Next Programmed Channel (after a TOTIM event) or
Wake-up Search gets started with Next Configuration (after an EOM event), then the
Polling Timer is not initialized. This means that the On time counter proceeds with the
old value from leaving the previous Wake-up search period successfully. This is the case
for Fast Fall Back to SLEEP Mode.
In Constant On-Off Time Mode the Polling Timer is always initialized after a TOTIM or
EOM event.
Data Sheet
107
V4.0, 2010-02-19
TDA5240
Functional Description
0
1
Modulation
Switching
All Operations Are Done With
The Wake Up Configuration
Modulation Selection
Depending On Register
Setting
INIT
If PWUF == 0 then
{ Init FIFO=
Init FIFO@Cycle Start }
PWUF = 0
To Self Polling Mode
(WU Search With Next
Programmed Channel)
To Self Polling Mode
(WU Search With
Configuration A )
TOTIM2nCh == 1
15
1.1
INIT
17
TOTIM2nCh == 0
Goto SP Next
Programmed
Channel
INIT
If INITFRCS== 1 then
Init Framer
Generating WU
CFG X Interrupt
If Not Masked
Init Digital Receiver
EXTTOTIM
(from external controller)
INITDRXES==1
INITDRXES==0
3
2
Init TOTIMs
ToTim Timeout == 1
EXTPROC==00
fifolk == 1
FIFO locked
Symbol Sync==0 Initialize TOTIM timers
ToTim Timeout SYNC== 1
Symbol Sync == X
Wait Till FIFO Read Out
INITDRXES==0
16
3.1
fifolk == 0
INIT
Symbol Sync ==0
fifolk == 0
Init
INITDRXES==1
Parallel Wake-Up
Found
Digital Receiver
4
Wait
ToTim Timeout SYNC== 1
Symbol Sync == X
EXTPROC <> 10
WU Found == 1
PWUF == 1
Start ToTim Timer SYNC
(If Enabled)
WU Found == 1
ToTim Timeout SYNC== 0
Symbol Sync == 0
It Is Possible To Disable
The Timeout Feature
To Self Polling Mode PWUF == 1
(WU Search With
Configuration A)
ToTim Timeout SYNC== 0
Symbol Sync == 1
EXTPROC <> 10
ToTim Timeout TSI == 0
Frame Sync == 0
To Self Polling Mode
(WU Search With
Next Configuration)
5
Wait
ToTim Timeout TSI== 1
Frame Sync== X
EXTPROC == 00
EOM2nCfg == 0
Start ToTim TSI(If Enabl.)
Wait Till Frame Start
Is Found
EOM2nCfg == 1
ToTim Timeout TSI== 0
Generating A Frame Start
Interrupt If Not Masked
Frame Sync== 1
EXTPROC==00
14
Goto Next
Config After EOM
INIT FIFO
6
Start ToTimEOM(If Enab.)
Init FIFO=
InitFIFO@FSYNC
EOM2SPM == 1
Check
MID Setup
7
EOM2SPM == 0
MID Screening
enable == 0
Check The MID Setup
Register
13
MID Screening
Goto SelfPolling
After EOM
enable == 1
Init MID
Scanning Unit
8
ToTim Timeout
EOM == 1
Initialize The MID
Scanning Unit
9
Wait
Store RX Data Into FIFO
Wait For Scan Finish
Generating A MID Found
Interrupt If Not Masked
MID Scanning
Finished == 1
MID Scanning
Finished == 0
12
10
Save
Checking ID
Channel and
Configuration
Information
Scanning Result
Store RX Data Into FIFO
Analyze The Scanning
Result
MID Found == 0
MID Found == 1
Generating A EOM
Interrupt If Not Masked
11
EOM Check
Store RX Data Into FIFO
Check For EOM
ToTim Timeout EOM == 1
EOM Found == X
EOM Found == 1
PWUF = PWUEN bit
EXTEOM found
ToTim Timeout EOM == 0
EOM Found == 0
(from external controller)
Figure 77
Run Mode Self Polling
Data Sheet
108
V4.0, 2010-02-19
TDA5240
Functional Description
While the TDA5240 is in Run Mode Self Polling, further Wake-ups would normally not be
detected by the receiver. If the functionality of a parallel Wake-up search during the
search for a TSI is desired, this can be activated by the PWUEN bit. In this case the
Wake-up search is not active during a recognized payload and is only active after the
first received payload frame, as can be seen from Figure 77. This feature can only be
used, when modulation type is the same for SPM and RMSP.
So after a reception of the EOM from the current payload, the parallel WU search can
take place in this mode. The WU search will be active after Symbol Sync has been
detected. The WU search will be active until the Synchronization gets lost or wake-up is
generated. After the Synchronization gets lost the WU search will be finished and wake-
up can not be detected any more (the TSI search continues as usual).
Following procedure can be applied with help of 3 SPI Write command sequences.
The idea is to generate external EOM every time the Symbol Sync goes to inactive state
and no interrupt (TSI or WU) has been detected. This will bring the MCU to the cycle start
and reinitialize the WU search.
Configuration:
Write x_WUC.PWUEN = 1
// Enable Parallel Wake-up search
Write x_WURSSITHx 0xFF
// Set RSSI threshold to max value (avoid WU during the reinitialization procedure)
Write x_WULOT 0xFF
// Set WULOT to max value (avoid WU during the reinitialization procedure)
Data Sheet
109
V4.0, 2010-02-19
TDA5240
Functional Description
Wait for Wake-up interrupt
WU IRQ
TIMEOUT -> SLEEP -> SPM
or (dependent on application )
EXT_TOTIM:
* Select external processing (for ext. TOTIM)
(Write x_CHCFG.EXTROC = 0x2)
* Generate external TOTIM
(Write EXTPCMD 0x02)
* Disable external processing
(Write x_CHCFG.EXTROC = 0x0)
WU IRQ
TSI IRQ
Wait for TSI interrupt
TSI IRQ
Wait for EOM interrupt
EOM IRQ
Only necessary if other PPx signals needed during self -polling
otherwise configure PPx once at the beginning
Activate Symbol Sync on PPx
Deactivate Symbol Sync on PPx
(example for PP0 = RX_RUN)
Write PPCFG0.PP0CFG = 0x1
(example for PP 0;
for other PPx see notes below )
Write 0xF4 0x07
Write PPCFG0.PP0CFG = 0xE
1. Force Symbol Sync for MCU to 0
Write 0xED 0x40
2. Select external processing (for ext. EOM)
Write x_CHCFG.EXTPROC = 0x2
3. Generate external EOM
Wait for Symbol Sync
(on PPx)
(if no ISR impl.)
Write EXTPCMD 0x01
Symbol Sync = 1
4. Disable external processing
Write x_CHCFG.EXTPROC = 0x0
5. Unforce Symbol Sync
Write 0xED 0x00
Interrupt
Wait for interrupt
Wait for SW Timeout
EOM generation
- must be faster than
RUNIN duration
Symbol Sync = 0
SW Timeout
Figure 78
Parallel Wake-up Search
Notes:
- Symbol Sync can be activated on any PPx port
PP0: Write 0xF4 0x07 & Write PPCFG0 0x0E
PP1: Write 0xF4 0x70 & Write PPCFG0 0xE0
PP2: Write 0xF5 0x01 & Write PPCFG1 0x0E
PP3: Write 0xF5 0x10 & Write PPCFG1 0xE0
- Symbol Sync monitoring necessary only in run mode between frames and WU pattern
or till software timeout generated
Data Sheet
110
V4.0, 2010-02-19
TDA5240
Functional Description
- generation of external EOM will reinitialize also the TOTIM timers
- external EOM generation period should be smaller than the RUNIN length
(7 chips RUNIN = ~62 us @ 112 kchip/s , 5 SPI write commands = ~ 60 us @ 2 Mbit)
- minimal Symbol Sync active period = TVWIN, minimal Symbol Sync inactive period =
RUNIN
For protocols where no ASK/FSK switching is required between the Wake-up and
payload frame, the Wake-up and TSI pattern can share the same bits (e.g. Wake-up
pattern = ..00000, TSI = 000001, all bits Manchester encoded). This function can be
activated by the INITFRCS bit, so then there is no reset of the framer compare shift
register after a Wake-up event, which can shorten the required processing time.
Data Sheet
111
V4.0, 2010-02-19
TDA5240
Functional Description
2.6.2
Polling Timer Unit
SPM
Reference-Timer
(8 Bit)
SPM
On-Off-Timer
(14 Bit)
SPM
fsys / 64
fRT
fOnOff
Active-Idle Period Timer
(5 / 8 Bit)
Self-Polling-Mode (SPM)
FSM
No WU
Polling Mode
to
Master-Control-Unit
Figure 79
Polling Timer Unit
The Polling Timer Unit consists of a Counter Stage and a Control FSM (Finite State
Machine).
The Counter Stage is divided into three sub-modules.
The Reference Timer is used to divide the state machine clock (fsys/64) into the slower
clock required for the SPM timers.
The On-Off Timer and the Active Idle Period Timer are used to generate the polling
signal. The entire unit is controlled by the SPM FSM.
The TDA5240 is able to handle up to four different sets of configurations automatically.
However, the examples and figures in this subsection only show up to two configuration
sets for the sake of clarity.
Data Sheet
112
V4.0, 2010-02-19
TDA5240
Functional Description
2.6.2.1 Self Polling Modes
Four polling modes are available to fit the polling behavior to the expected wake-up
patterns and to optimize power consumption in Self Polling Mode.
The following 4 Polling Modes are available and can be configured via 2 bits in the
configuration register SPMC:
• Constant On-Off (COO)
• Fast Fall Back to SLEEP (FFB)
• Mixed Mode (MM)
• Permanent Wake-Up Search (PWUS)
A detected wake-up data sequence or an actual value for RSSI or Signal Recognition (a
combination of Signal Detector and Noise Detector, see Chapter 2.4.8.1) exceeding a
certain adjustable threshold forces the TDA5240 into Run Mode Self Polling.
In all modes the timing resolution is defined by the Reference Timer, which scales the
incoming frequency (fsys/64) corresponding to the value, which is defined in the Self
Polling Mode Reference Timer (SPMRT) register. Changing values of SPMRT helps to
fit the final On-Off timing to the calculated ideal timing.
2.6.2.2 Constant On-Off Time (COO)
In this mode there is a constant On and a constant Off time. Therefore also the resulting
master period time is constant. The On and Off time are set in the SPMONTA0,
SPMONTA1, SPMONTB0, SPMONTB1, SPMONTC0, SPMONTC1, SPMONTD0,
SPMONTD1, SPMOFFT0 and SPMOFFT1 registers. The On time configuration is done
separately for Configuration A, B, C and D.
When Single-Configuration is selected then only Configuration A is used. The number
of RF channels is defined in the A_CHCFG register (Single-Channel or Multi-Channel
Mode).
Multi-Configuration Mode allows reception of up to 4 different transmit sources. The
corresponding RF channels can be defined in the A_CHCFG, B_CHCFG, C_CHCFG
and D_CHCFG registers. In the case of Multi-Channel or combination of Multi-Channel
and Multi-Configuration Mode, the configured On time is used for each RF channel in a
configuration. The diagram below shows possible scenarios.
All receive modes described in Chapter 2.5.1.2 Data Interface can be used.
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Functional Description
Single Channel, Single Config
run mode
A
1
RX polling
Channels = 1
sleep mode
TAON
TOFF
T
MasterPeriod = TAON + TOFF
TMasterPeriod
Multi Channel, Single Config
run mode
RX polling
sleep mode
A
1
A
2
A
3
Channels = m
T
T
AON
T
AON
T
AON
T
OFF
T
MasterPeriod = m*TAON + TOFF
T
MasterPeriod
Multi Channel, Multi Config
run mode
A
1
A
2
A
3
B
1
B
2
RX polling
Channels Config A = m
Channels Config B = n
sleep mode
AON
T
AON
T
AON
TBON
T
BON
T
OFF
T
MasterPeriod = m*TAON + n*TBON+ TOFF
TMasterPeriod
Figure 80
Constant On-Off Time
Calculation of the On time:
The On time for each channel must be long enough to ensure proper detection of a
specified wake-up criterion. Therefore the On time depends on the wake-up pattern, and
the wake-up criterion. It has to include transmitter data rate tolerances.
A widely used wake-up pattern is a sequence of equal Bi-phase encoded bits or a certain
Bi-phase encoded bit pattern.
TON also must include the relevant start-up times. In case of the first channel after TOFF
,
this is the Receiver Start-Up Time. In case of following channels (RF Receiver is already
on, there is only a change of the channel or the configuration), e.g. if Configuration B is
used, this is the Channel Hop Latency Time. In addition, it has to be considered that
some data bits are required for synchronization and internal latency, see
Chapter 2.4.8.8 RUNIN, Synchronization Search Time and Inter-Frame Time.
There are other wake-up patterns in use as well, which have several (up to 10 and more)
short wake-up sequences (a few byte each) that are separated by a certain pause (again
a few byte each). In this case the On time has to be set, so that a possible wake-up can
be found within two wake-up sequences including the pause in-between.
Calculation of the Off time:
The longer the Off time, the lower the average power consumption in Self Polling Mode.
On the other hand, the Off time has to be short enough that no transmitted wake-up
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Functional Description
pattern is missed. Therefore the Off time depends mainly on the duration of the expected
wake-up pattern.
If there are further channels scanned, TOFF has to be reduced by the related additional
On times.
For basic timing of WU on RSSI in COO mode, please see Figure 81.
RF signal
e.g . ASK
t
RX ON
SLEEP
t
tWULOT
last observation time
window is forced to end by
end of tON
tWULOT
2
tWULOT
t WULOT_part
tStartup
n-1 npartially
1
latest decision here !
tON
Figure 81
COO Polling in WU on RSSI Mode
Always check at the end of the current observation time window, if there is a WU (Wake-
Up) event or NOT. This means, in algorithmic description (see also Figure 10,
Chapter 2.4.7 RSSI Peak Detector and Chapter 2.4.8.5 Wake-Up Generator):
if (RSSIPWU_value > x_WURSSITHy) and (RSSIPWU_value > x_WURSSIBHy)
then WU
else NOT
Here, ‘NOT‘ means to keep on evaluating and move on to the next observation time
window, also keep on peak value tracking of RSSIPWU signal. Keep on walking through
the observation time windows until there is a WU event from the algorithm above or
finally decide at the end of the On time with the following algorithm:
if (RSSIPWU_value > x_WURSSITHy) and (RSSIPWU_value < x_WURSSIBLy or
RSSIPWU_value > x_WURSSIBHy)
then WU
else NOT
If there is a WU event at the end of an observation time window while walking through
the observation time windows, freeze/hold this decision/peak value in register RSSIPWU
for optional read out and switch to run mode self polling.
Instead of the single RSSI criterion also the Signal Recognition criterion can be
activated.
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Functional Description
Combined Level and Data criterion in COO mode
On using the Wake-Up on Data criterion in COO mode, the RSSI criterion (including the
RSSI blocking window) can be applied additionally by setting the bit
x_WUC.UFFBLCOO. This means that a Wake-Up interrupt will not be generated, when
a blocking RSSI level (e.g. an interfering signal) is detected even when the Data criterion
is fulfilled.
The behavior of the additional RSSI criterion is similar to the behavior in Ultrafast Fall
Back Mode.
After the level observation time the receiver checks, if the RSSI level is within a valid
range. If RSSI is within a valid range, the state machine will go on to check the Data
criterion. If the RSSI is within a forbidden range, a new level observation time is started
(Note that no parts of the Wake-Up pattern are lost in this case, when the RSSI criterion
succeeds within the following observation time).
This will be done as long as the RSSI value is within a forbidden range and the On time
is not elapsed.
If the receiver loses synchronization within the search for the Data criterion (e.g. pattern
detection), the WU unit will be initialized and checks again for the RSSI criterion.
Instead of the additional RSSI criterion also Signal Recognition criterion can be applied.
When the Signal Recognition threshold (x_WURSSIBHy) is not exceeded at
Observation Time, the Wake-Up on Level FSM (finite state machine) and Wake-Up on
Data FSM are initialized.
If the threshold is exceeded, then the Wake-Up on Level FSM enters the READY state
and has no further impact on Wake-up search until the Wake-up unit is initialized again.
When afterwards a Data Criterion is found to be OK (e.g. pattern matches, number of
equal bits or random bits is reached), the Wake-up search is completed positively.
When a Data Criterion is found to be not OK, the Wake-up search is terminated
independent of the state of the Wake-Up on Level FSM. Therefore both FSMs are
initialized.
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Functional Description
2.6.2.3 Fast Fall Back to SLEEP (FFB)
This mode is used to switch off the receiver, if there is no RF signal, as quickly as
possible to reduce power consumption.
During the search for wake-up data, there is a check for a bit stream, to which the system
can be synchronized. If there is no synchronization to a bit stream within the so-called
Sync Search Time Out (SYSRCTO), the wake-up search for this channel is stopped. If
synchronization to a bit stream is possible (and not lost again), the TDA5240 waits if the
wake-up criterion is fulfilled. If the wake-up criterion is not fulfilled (in worst case, if the
last bit of an expected wake-up data pattern is wrong), the wake-up procedure for this
channel is stopped, and the TDA5240 tries to synchronize on the next channel, or falls
back to sleep. That means that the effective search time and, consequently, the receiver
active time is significantly shorter, and power consumption is reduced, when no input
signal is present. Calculation of Sync Search Time Out can be found in Chapter 2.4.8.8
RUNIN, Synchronization Search Time and Inter-Frame Time.
The needed time for detecting that no relevant transmission took place can be further
reduced by using Ultrafast Fall Back to SLEEP (UFFB). When there was no Wake-up on
Level criterion fulfilled in UFFB Mode during the Observation Time (TWULOT, see
Chapter 2.4.8.5), then the system goes back to SLEEP (or to next config/channel). This
can further reduce the receiver active time, when no data is available. When Wake-up
on Level criterion was fulfilled, then the system proceeds with normal FFB functionality
(SYSRCTO, optional Wake-up data criterion).
Note: UFFB and FFB start working at the same time!
Ultrafast Fall Back to SLEEP is working, when a Wake-up on Data criterion is selected,
the UFFBLCOO bit is enabled and FFB or PWUS mode is selected. The UFFB level
criterion can be selected in the x_WUC register.
RF signal
e.g. ASK
t
RX ON
SLEEP
UFFB
FFB
FFB
t
tWULOT
tStartup
tSYSRCTO
tWU-data-pattern
tON
Figure 82
Ultrafast Fall Back to SLEEP
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Functional Description
At the end of the observation time the RSSI peak tracking value of RSSIPWU signal is
compared to the 3 thresholds. Then the decision is made. The algorithmic description is
as follows (see also Figure 10, Chapter 2.4.7 RSSI Peak Detector and
Chapter 2.4.8.5 Wake-Up Generator):
if (RSSIPWU_value > x_WURSSITHy) and (RSSIPWU_value < x_WURSSIBLy or
RSSIPWU_value > x_WURSSIBHy)
then WU
else NOT
Instead of the RSSI criterion also Signal Recognition criterion can be applied. When the
Signal Recognition threshold (x_WURSSIBHy) is not exceeded at Observation Time,
then the system goes back to SLEEP or the Wake-Up on Level FSM (finite state
machine) is initialized and a Wake-up search is performed on the next specified
channel/configuration.
WULCUFFB
0
UFFB criterion
&
1
RSSI
4
WU on Level Criterion
Signal
5
3
1
2
0
Recognition
Sync
WU criterion
Random Bits
Equal Bits
Pattern
WU on Data Criterion
Wake-up
Generation
FSM
WUCRT
WUCRT (2)
WUCRT (1)
WUCRT (0)
&
&
UFFBLCOO
FFB is selected
Figure 83
UFFB activation
The On and Off time setting is different from the Constant On-Off Time Mode. The entire
On time is defined in the SPMONTA0 and SPMONTA1 registers. Regardless of the
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Functional Description
numbers of RF channels and whether or not Multi- or Single-Configuration is used, the
On time is defined with the Configuration A On-Timer. The deactivation of the receiver
can happen at different times, but this event does not influence the timer stage, because
the On time is still the same. So the master period is constant. The following scenarios
are the same as before, but with Fast Fall Back to SLEEP.
Only the following receive modes (see Chapter 2.5.1.2 Data Interface) can be used:
• Packet Oriented FIFO Mode (POF)
• Packet Oriented Transparent Payload Mode (POTP)
• Transparent Mode - Chip Data and Strobe (TMCDS)
Single Channel, Single Config
run mode
A
RX polling
1
Channels = 1
TMasterPeriod = TAON + TOFF
sleep mode
TAON
T
OFF
TMasterPeriod
Multi Channel, Single Config
run mode
Channels = m
TMasterPeriod = TAON + TOFF
A
2
A
3
A
1
RX polling
sleep mode
TAON
TOFF
TMasterPeriod
Multi Channel, Multi Config
run mode
Channels Config A = m
Channels Config B = n
TMasterPeriod = TAON+ TOFF
B
1
B
2
A
1
A
2
A
3
RX polling
sleep mode
T
AON
TOFF
TMasterPeriod
Figure 84
Fast Fall Back to SLEEP
Calculation of the On time:
The On time, which is now a sum for all of the channels and configurations used, must
include enough time to ensure proper detection of the specified wake-up pattern on all
channels. To cover the worst case scenario, the maximum time is required on all
channels as in Constant On-Off.
TON must also include the relevant start-up times. In case of the first channel after TOFF
,
this is the Receiver Start-Up Time. In case of following channels (RF Receiver is already
on, there is only a change of the channel or the configuration), e.g. if Configuration B is
used, this is the Channel Hop Latency Time.
In addition, it has to be considered that some data bits are required for synchronization
and internal latency (see Chapter 2.4.8.8 RUNIN, Synchronization Search Time and
Inter-Frame Time).
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Functional Description
Calculation of the Off time:
The same general rules apply as for Constant On-Off Time. The Off time has to be short
enough that no wake-up pattern reception is missed.
2.6.2.4 Mixed Mode (MM, Const On-Off & Fast Fall Back to SLEEP)
This mode combines Constant-On Time and Fast Fall Back to SLEEP within different
configuration sets: Cfg.A: COO; Cfg.B: FFB; Cfg.C: FFB; Cfg.D: FFB
T
ON for Configuration A is always calculated according to Const On-Off rules.
TON for Configuration B, C and D is always calculated according to Fast Fall Back to
SLEEP rules.
In Mixed Mode the On time of the first configuration within the FFB group is used. Below
there are shown the same scenarios as before, but now for Mixed Mode. Note that
Single-Configuration can be set, but is not recommended in Mixed Mode.
Only the following receive modes (see Chapter 2.5.1.2 Data Interface) can be used:
• Packet Oriented FIFO Mode (POF)
• Packet Oriented Transparent Payload Mode (POTP)
• Transparent Mode - Chip Data and Strobe (TMCDS)
Single Channel, Single Config
run mode
A
1
RX polling
Channels = 1
TMasterPeriod = TAON + TBON + TOFF
sleep mode
TAON
TOFF
T
BON
TMasterPeriod
Multi Channel, Single Config
run mode
RX polling
sleep mode
A
1
A
2
A
3
Channels = m
MasterPeriod = m*TAON + TBON + TOFF
T
T
AON
T
AON
T
AON
T
BON
TOFF
T
T
MasterPeriod
Multi Channel, Multi Config
run mode
RX polling
sleep mode
A
1
A
2
A
3
B
1
B
2
Channels Config A = m
Channels Config B = n
TMasterPeriod = m*TAON + TBON+ TOFF
AON
T
AON
T
AON
T
BON
MasterPeriod
T
OFF
T
Figure 85
Mixed Mode
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Functional Description
2.6.2.5 Permanent Wake-Up Search (PWUS)
In this mode the receiver will work in Fast Fall Back Mode, but it will not go back to the
SLEEP state after the last channel has been searched. Instead, it will start again from
the beginning (Configuration A, RF Channel 1) until the On time has elapsed. The timing
calculation can be seen in Figure 86. Ultrafast Fall Back to SLEEP functionality can be
used as well.
Only the following receive modes (see Chapter 2.5.1.2 Data Interface) can be used:
• Packet Oriented FIFO Mode (POF)
• Packet Oriented Transparent Payload Mode (POTP)
• Transparent Mode - Chip Data and Strobe (TMCDS)
Single Channel , Single Config
run mode
A
1
A
1
A A AA
1 1
RX polling
1
1
Channels = 1
sleep mode
T
AON
T
OFF
T
MasterPeriod = TAON + TOFF
T
MasterPeriod
Multi Channel , Single Config
run mode
A A A AA A A
1 2 3 1 2 3 1
Channels = m
RX polling
sleep mode
TMasterPeriod = TAON + TOFF
T
AON
T
OFF
T
MasterPeriod
Multi Channel , Multi Config
run mode
AA A B B A A
1 2 3 1 2 1 2
Channels Config A = m
Channels Config B = n
RX polling
sleep mode
T
AON
T
OFF
TMasterPeriod = TAON+ TOFF
T
MasterPeriod
Figure 86
Permanent Wake-Up Search
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Functional Description
2.6.2.6 Active Idle Period Selection
This mode is used to deactivate some polling periods and can additionally be applied to
each of the above mentioned Polling Modes.
Normally, polling starts again after the TMasterPeriod. With this Active Idle Period selection
some of the polling periods can be deactivated, independent from the Polling Mode. The
active and the idle sequence is set with the SPMAP and the SPMIP registers. The values
of these registers determine the factor M and N.
run mode
RX polling
sleep mode
TOn
TOff
TMasterPeriod
M*TMasterPeriod
N*TMasterPeriod
Active
Idle
Figure 87
Active Idle Period
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Functional Description
2.7
Definitions
2.7.1
Definition of Bit Rate
The definition for the bit rate in the following description is:
symbols
bitrate = ---------------------
s
If a symbol contains n chips (for Manchester n=2; for NRZ n=1) the chip rate is n times
the bit rate:
chiprate = n × bitrate
2.7.2
Definition of Manchester Duty Cycle
Several different definitions for the Manchester duty cycle (MDC) are in place. To avoid
wrong interpretation some of the definitions are given below.
Level-based Definition
MDC = Duration of H-level / Symbol period
bit = 1
1
0
0
1
1. chip
2. chip
Tbit
T
chip
MDC < 50%
0
1
1
0
1
ΔT
TH
TH
T
Tbit
Tbit
chip
MDC > 50%
ΔT
TH
TH
T
Tbit
Tbit
chip
Figure 88
Definition A: Level-based definition
This definition determinates the duty cycle to be the ratio of the high pulse width and the
ideal symbol period. The DC content is constant and directly proportional to the specified
duty cycle.
For ΔT > 0 the high period is longer than the chip-period and for ΔT < 0 the high period
is shorter than the chip-period.
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Functional Description
Depending on the bit content, the same type of edge (e.g. rising edge) is sometimes
shifted and sometimes not.
With this definition the Manchester duty cycle is calculated to
TH Tchip + ΔT
MDCA = -------- = --------------------------
Tbit Tbit
Chip-based Definition
MDC = Duration of the first chip / Symbol period
bit = 1
1
0
0
1
1. chip
2. chip
Tbit
T
c hip
MDC < 50%
0
1
1
0
1
ΔT
T1.chip
T1.chip
T
Tbit
Tbit
c hip
MDC > 50%
ΔT
T1.chip
Tbit
T
1.chip
T
Tbit
c hip
Figure 89
Definition B: Chip-based definition
This definition determinates the duty cycle to be the ratio of the first symbol chip and the
ideal symbol period independently of the information bit content. The DC content
depends on the information bit and it is balanced only if the message itself is balanced.
For ΔT > 0 the first chip-period is longer than the ideal chip-period and for ΔT < 0 the first
chip-period is shorter than the ideal chip-period.
Depending on the bit content, the same type of edge (e.g. rising edge) is sometimes
shifted and sometimes not.
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Functional Description
With this definition the Manchester duty cycle is calculated to
T1.chip chip + ΔT
T
MDCB = ---------------- = --------------------------
Tbit
Tbit
Edge delay Definition
MDC = Duration delayed edge / Symbol period
bit = 1
1
0
0
1
1. chip
2. chip
Tbit
T
chip
MDC < 50% T = 0
f
1
1
0
0
1
Tr
TH
Tr
TH
ΔT
T
Tbit
Tbit
Tbit
chip
MDC > 50% T = 0
r
1
1
0
0
1
Tf
Tf
ΔT
TH
TH
T
Tbit
Tbit
Tbit
chip
Figure 90
Definition C: Edge delay definition
This definition determinates the duty cycle to be the ratio of the duration of the delayed
high-chip and the ideal symbol period independently of the information bit content. The
position of the high-chip is determined by the delayed rising edge and/or the delayed
falling edge. For ΔT = Tfall -Trise the Manchester duty cycle is calculated to
TdelayedHighchip
MDCC = ---------------------------------------- = -------------------------- = -----------------------------------------------
Tbit Tbit Tbit
T
chip + ΔT
Tchip + Tfall – Trise
Independent on the bit content, the same type of edge (rising edge and/or falling edge)
is shifted.
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Functional Description
2.7.3
Definition of Power Level
The reference plane for the power level is the input of the receiver board. This means,
the power level at this point (Pr) is corrected for all offsets in the signal path (e.g.
attenuation of cables, power combiners etc.).
The specification value of power levels in terms of sensitivity is related to the peak power
of Pr in case of On-Off Keying (OOK). This is noted by the unit dBm peak.
Specification value of power levels is related to a Manchester encoded signal with a
Manchester duty cycle of 50% in case of ASK modulation.
An RF signal generator usually displays the level of the unmodulated carrier (Pcarrier).
This has following consequences for the different modulation types:
Table 6
Power Level
Realization with RF signal
Modulation
scheme
Power level specification
value
generator
ASK
ASK
AM 100%
Pr = Pcarrier + 6dB
Pr = Pcarrier
Pulse modulation (=OOK)
FM with deviation Δf:
f1 = fcarrier - Δf
FSK
Pr = Pcarrier
f2 = fcarrier + Δf
For power levels in sensitivity parameters given as average power, this is noted by the
unit dBm. Peak power can be calculated by adding 3 dB to the average power level in
case of ASK modulation and a Manchester duty cycle of 50%.
2.7.4
Symbols of SFR Registers and Control Bits
Symbolizes unique SFR registers or SFR control bit(s),
which are common for all configuration sets .
CONTROL
CONTROL
Symbolizes SFR registers or SFR control bit(s) with
Multi-Configuration capability (protocol specific).
In case of SFR register, the name starts with A _, B_, C_
or D_, depending on the selected configuration. This is
generally noted by the prefix „x_“.
Figure 91
SFR Symbols
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Functional Description
2.8
Digital Control (SFR Registers)
SFR Address Paging
2.8.1
An SPI instruction allows a maximum address space of 8 bit. The address space for
supporting more than one configuration set is exceeding this 8 bit address room.
Therefore a page switch is introduced, which can be applied via register SFRPAGE (see
Figure 92).
logical address space
physical address space
0x000
0
d
Configuration A1) - Page 0
Configuration A 1) - Page 0
Reserved 2)
Reserved 2)
0x080
128d
Common Registers3)
Common Registers3)
Reserved 4)
Reserved 4)
0x0FF
0x100
255d
256d
Configuration B1) - Page 1
Configuration B 1) - Page 1
Reserved 2)
Reserved 2)
0x180
384d
Common Registers3)
Reserved 4)
0x1FF
0x200
511d
512d
Configuration C 1) - Page 2
Configuration C 1) - Page 2
Reserved 2)
Reserved 2)
0x280
640d
Common Registers3)
Reserved 4)
0x2FF
0x300
767d
768d
Configuration D 1) - Page 3
Configuration D 1) - Page 3
Reserved 2)
Reserved 2)
0x380
896d
Common Registers3)
Reserved 4)
0x3FF
1)
1023d
Configuration dependent register block (4 protocol specific sets)
page switch via SFRPAGE register
Reserved – Forbidden area
2), 4)
3)
Configuration independent registers (common for all configurations )
map (“mirror“) to the same physical address space
Figure 92
2.8.2
SFR Address Paging
SFR Register List and Detailed SFR Description
The register list is attached in the Appendix at the end of the document.
Registers for Configurations B, C and D are equivalent and not shown in detail.
All registers with prefix “A_” are related to Configuration A. All these registers are also
available for Configuration B, C and D having the prefix “B_”, “C_” and “D_”.
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Functional Description
Data Sheet
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TDA5240
Applications
3
Applications
RF in
SAW
filter
to µC
SPI Bus
VS
TDA5240
IF CER
filter
to/from µC
(opt.)
Figure 93
Typical Application Schematic
Note: As a good practice in any RF design, shielding around sensitive nodes can
improve the EMC performance of the application.
For achieving the best sensitivity results the following has to be kept in mind. Every
digital system generates certain frequencies (fSRC, e.g. the crystal frequency or a
microcontroller clock) and harmonics (N * fSRC) of it, which can act as interferer (EMI
source) and therefore sensitivity can be reduced.
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Applications
There are two different cases, which need to be checked for the desired receive
channel(s):
Elimination of in-band EMI mixing with (2*M + 1) * fLO, where M > 0:
A square wave is used as LO (Local Oscillator) for the switching-type mixer, which also
has odd harmonics. When the harmonics of the EMI source are exactly the IF frequency
away from the harmonics of the LO, these spurs will be down-converted to the IF
frequency and act as a co-channel interferer within the receiver’s channel bandwidth
mainly in the 315 MHz band.
In this case a change of the LO injection side (high side or low side injection) can be
applied.
Example (Low Side LO-injection):
Wanted channel fRF = 314.233MHz ==> fLO = 303.533MHz ==> 3*fLO = 910.599MHz
fXOSC = 21.948717 MHz ==> 41 * fXOSC = 899.8974 MHz
Resulting IF = 910.599 - 899.8974 MHz = 10.702 MHz ==> co-channel interferer
within the receiver’s channel bandwidth ==> change LO injection side
Example (High Side LO-injection):
Wanted channel fRF = 314.233 MHz ==> fLO = 324.933 MHz ==> 3*fLO = 974.799 MHz
fXOSC = 21.948717 MHz ==> 44 * fXOSC = 965.744 MHz; 45 * fXOSC = 987.692 MHz
==> both XOSC harmonics are not generating a co-channel interferer at 10.7 MHz
A final sensitivity measurement on the application hardware is recommended.
Elimination of in-band EMI mixing with 1 * fLO:
Assuming a harmonic (N * fSRC) is falling within the BW of the wanted channel and has
an impact on the sensitivity there. In this case another XTAL frequency shall be selected,
e.g. 10 kHz away
| N * fSRC - fLocalOscillator | < BWChannel
Example (e.g. EMI source TDA5240 XOSC):
fXOSC = 21.948717 MHz ==> 42 * fXOSC = 921.846114 MHz
For further details please refer to the corresponding application note or to the latest
configuration software.
3.1
Configuration Example
Please see configuration files supplied with the Explorer tool.
Data Sheet
130
V4.0, 2010-02-19
TDA5240
Reference
4
Reference
4.1
Electrical Data
4.1.1
Absolute Maximum Ratings
Attention: The maximum ratings must not be exceeded under any circumstances,
not even momentarily and individually, as permanent damage to the IC
may result.
Table 7
Absolute Maximum Ratings
#
Parameter
Symbol
Limit Values
Unit Remarks
min.
max.
+6
A1
A2
Supply Voltage at VDD5V pin Vsmax
-0.3
-0.3
V
V
Supply Voltage at VDDD,
VDDA pin
Vsmax
+4
A3
Voltage between VDD5V vs
VDDD and VDD5V vs VDDA
Vsmax
-0.3
+4
V
A4
A5
A6
Junction Temperature
Storage Temperature
Tj
-40
-40
+125
+150
140
°C
Ts
°C
Thermal resistance junction to Rth(ja)
air
K/W
A7
A8
Total power dissipation at
amb = 105°C
Ptot
100
2
mW
T
ESD HBM integrity
VHBMRF
-2
KV
According to ESD
Standard JEDEC EIA /
JESD22-A114-B
A9
ESD SDM integrity (All pins
except corner pins)
VSDM
-500
-750
100
500
750
V
A10 ESD SDM integrity (All corner VSDM
pins)
V
A11 Latch up
ILU
mA
V
AEC-Q100 (transient
current)
A12 Maximum input voltage at
digital input pins
Vinmax
IIOmax
-0.3
VDD5V+0.5
or 6.0
whichever is lower
A13 Maximum current into digital
input and output pins
4
mA
Data Sheet
131
V4.0, 2010-02-19
TDA5240
Reference
4.1.2
Operating Range
Table 8
Supply Operating Range and Ambient Temperature
#
Parameter
Symbol
Limit Values
Unit Remarks
min.
max.
5.5
B1
B2
Supply voltage at pin VDD5V VDD5V
4.5
3.0
V
V
Supply voltage range 1
Supply voltage range 2
Supply voltage at pin
VDD5V=VDDD=VDDA
VDD3V3
3.6
B3
Ambient temperature
Tamb
-40
105
°C
Data Sheet
132
V4.0, 2010-02-19
TDA5240
Reference
4.1.3
AC/DC Characteristics
Supply voltage VDD5V = 4.5 to 5.5 Volt or VDD5V = VDDA = VDDD = 3.0 to 3.6 Volt
Ambient temperature Tamb = -40...105oC; Tamb = +25oC and VDD5V = 5.0V or VDD5V =
VDDA = VDDD = 3.3V for typical parameters, unless otherwise specified.
■ not subject to production test - verified by characterization/design
Table 9
AC/DC Characteristics
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
General DC Characteristics
C1.1
C1.2
C2
Supply Current
in Run Mode and
Double Down
IRun, Double
IRun, Single
Isleep_low
12
15
14
mA
mA
ASK or FSK mode
Pin < -50dBm
Conversion Mode
Supply Current
in Run Mode and
Single Down
10.5
ASK or FSK mode
Pin < -50dBm
Conversion Mode
Supply current
in Sleep Mode
crystal oscillator in Low
Power Mode;
clock generator off;
valid for SLEEP Mode
and during SPM Off time
T
amb = 25 °C
40
50
µA
µA
µA
µA
Tamb = 85 °C
Tamb = 105 °C
60
110
160
350
■
■
90
C3
C4
Supply current
in Sleep Mode
Isleep_high
115
crystal oscillator in High
Precision Mode
C
load = 25 pF;
clock generator off;
valid for SLEEP Mode
and during SPM Off time
Supply current
IPDN
in Power Down Mode
Tamb = 25 °C
Tamb = 85 °C
Tamb = 105 °C
0.8
3.7
9.0
23
1.5
13
27
27
µA
µA
µA
µA
■
■
■
C5
C6
Supply current
clock generator
Iclock
fclockout = 1 kHz
C
load = 10 pF
Supply current
IF-Buffer
IBuffer
0.5
0.7
mA
fIF_1 = 10.7 MHz
■
R
load = 330 Ω
no AC signal
Data Sheet
133
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
C7
Supply current
IRF-FE-
2.2
2.9
mA
■
during RF-FE startup
/ BPF calibration
startup,BPFcal
C8
C9
Brownout detector
threshold
VBOR
tReset
2.3
1.0
2.45
2.6
3.0
V
Receiver reset time
ms
Note: No SPI
communication is allowed
before XOSC start-up is
finished and chip reset is
already finished
C10
C11
Receiver startup
time
tRXstartup
455
111
455
111
455
111
350
µs
µs
Time to startup RF
frontend (comprises time
required to switch crystal
oscillator from Low Power
Mode to High Precision
Mode
■
■
RF Channel Hop
Latency Time and
Configuration (Hop)
Change Latency
Time (e.g. Cfg A to
Cfg B)
tC_Hop
Time to switch RF PLL
between different RF
Channels (does not
include settling of Data
Clock Recovery) and time
to change Configuration
C12
C13
RF Frontend startup tRFstartdelay
delay
350
15
350
12
µs
µs
µs
Delay of startup of RF
frontend
■
■
■
P_ON pulse width
tP_ON
Minimal pulse width to
reset the chip
C14
C15
NINT pulse length
tNINT_Pulse
Pulse width of interrupt
Accuracy of Temperature Sensor
Valid for temperature
range -40°C .. +105°C;
using upper 8 ADC bits
(ADCRESH)
C15.1 uncalibrated
C15.2 calibrated
TError, uncal
TError, cal
+/- 23
°C
uncalibrated (3 sigma)
value
■
■
+/- 4.5 °C
after 1-point calibration at
room temperature (3
sigma)
C16
Accuracy of VDDD readout
Valid for temperature
range -40°C .. +105°C;
using upper 8 ADC bits
(ADCRESH)
C16.1 uncalibrated
C16.2 calibrated
VDDD, Error,
+/- 200 mV
+/- 25 mV
uncalibrated (3 sigma)
value
■
■
uncal
VDDD, Error,
after 1-point calibration at
room temperature (3
sigma)
cal
Data Sheet
134
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
General RF Characteristics (overall)
D1
Frequency
Range 1
Range 2
Range 3
Range 4
fband_1
fband_2
fband_3
fband_4
fstep
300
425
863
902
10.5
320
450
870
928
MHz
MHz
MHz
MHz
Hz
1st Local Oscillator
Low Side LO-injection
and High Side LO-
injection allowed;
See also Chapter 3
D2
D3
Frequency step of
Sigma-Delta PLL
fstep = fXTAL / 221
■
ASK Demodulation
Data Rate
Rdata
0.5
-10
50
40
kchip/s
■
■
■
■
Data rate tol.
Rdata_tol
mASK
+10
100
100
%
%
%
Modulation index
ASK
mOOK
99
ON-OFF keying
D4
FSK Demodulation
Data Rate
Rdata
0.5
-10
1
112
+10
64
kchip/s including tolerance
%
■
■
■
Data rate tol.
Rdata_tol
Frequency deviation Δf
kHz
frequency deviation
zero-peak
Modulation index
mFSK
1.0
m = frequency_
■
deviationzero-peak
/
maximum_occuring_data
_frequency;
m >= 1.25 is
recommended at small
frequency deviation
D5
Decoding schemes
Manchester, differential Manchester,
Bi-phase Mark / Bi-phase Space
Duty cycle ASK
Duty cycle FSK
Tchip
Tdata
/
35
55
%
see Chapter 2.7.2
Definition C
■
■
Tchip
/
45
55
%
see Chapter 2.7.2
Tdata
Definition B
D6
Overall noise figure
Noise figure
RF input matched to 50 Ω
@ Tamb = 25 °C
NF
6
8
dB
■
Data Sheet
135
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
D7
BER Sensitivity (FSK)
BER = 2*10-3
RF input matched to 50 Ω
Manchester coding;
for additional test conditions see right after this
table
@ Tamb = 25 °C;
Single-Ended Matching
without SAW;
Insertion loss of input
matching network = 1dB;
Receive Mode = TMMF
(sampled with ideal data
clock);
Double Down Conversion
D7.1
D7.2
D7.3
D7.4
D7.5
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK1BER
-119
-114
-112
-105
-110
-116
-111
-109
-102
-107
dBm
dBm
dBm
dBm
dBm
2nd IF BW = 50 kHz
PDF = 33 kHz, AFC off,
IFATT=0
■
■
■
■
■
Data Rate 10 kBit/s; SFSK2BER
Δf = 14 kHz
2nd IF BW = 50 kHz
PDF = 65 kHz, AFC off,
IFATT=0
Data Rate 10 kBit/s; SFSK3BER
Δf = 50 kHz
2nd IF BW = 125 kHz
PDF = 132 kHz, AFC off,
IFATT=0
Data Rate 50 kBit/s; SFSK4BER
Δf = 50 kHz
2nd IF BW = 300 kHz
PDF = 239 kHz, AFC off,
IFATT=0
Data Rate 2 kBit/s;
SFSK5BER
2nd IF BW = 300 kHz
Δf = 10 kHz
PDF = 282 kHz, IFATT=7
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
D7.6
D7.7
Data Rate 10 kBit/s; SFSK6BER
Δf = 14 kHz
-106
-110
-103
-107
dBm
dBm
2nd IF BW = 300 kHz
PDF = 282 kHz, IFATT=7
Note: 3dB sensitivity loss
■
■
@ foffset=+/-90kHz @ AFC on
Data Rate 10 kBit/s; SFSK7BER
2nd IF BW = 300 kHz
Δf = 50 kHz
PDF = 282 kHz, IFATT=7
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
Data Sheet
136
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
D8
BER Sensitivity (OOK)
BER = 2*10-3
RF input matched to 50 Ω
Manchester coding;
for additional test conditions see right after this
table
@ Tamb = 25 °C,
peak power level (see
Chapter 2.7.3);
Single-Ended Matching
without SAW;
Insertion loss of input
matching network = 1dB;
Receive Mode = TMMF
(sampled with ideal data
clock);
Double Down Conversion
D8.1
D8.2
D8.3
D8.4
D8.5
Data Rate 0.5 kBit/s SASK1BER
-120
-116
-111
-109
-115
-117
-113
-108
-106
-112
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
■
■
■
■
Data Rate 2 kBit/s
Data Rate 10 kBit/s
Data Rate 16 kBit/s
SASK2BER
SASK3BER
SASK4BER
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 80 kHz
Data Rate 0.5 kBit/s SASK5BER
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
D8.6
D8.7
D8.8
Data Rate 2 kBit/s
Data Rate 10 kBit/s
Data Rate 16 kBit/s
SASK6BER
SASK7BER
SASK8BER
ΔSSDC
-112
-106
-104
-109
-103
-101
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
■
■
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
D9.1
D9.2
Sensitivity increase
for Single Down
Conversion mode
0
0.5
1
1
2
dB
dB
■
■
Double Down
ΔSDDC,
IFATT7
Conversion sensitivity
decrease for higher
blocking performance
(IFATT=0 => IFATT=7)
Data Sheet
137
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
SingleDownConversion
sensitivity decrease for
higher blocking
D9.3
ΔSSDC,
IFATT7
0.5
1
dB
■
performance
(IFATT=4 => IFATT=7)
D10.1 Sensitivity variation
due to temperature
(-40...+105°C)
ΔPin
ΔPin
ΔPin
2
3
3
dB
dB
dB
relative to Tamb = 25 °C;
temperature drift of crystal
not considered
■
■
■
D10.2 Sensitivity variation
due to frequency
offset 1)
AFC inactive;
For Sensitivity Bandwidth
see Table 11
D10.3 Sensitivity variation
due to frequency
offset
AFC active, slow AFC;
For Sensitivity Bandwidth
see Table 11 and applied
AFCLIMIT
D10.4 Sensitivity loss when ΔPin
AFC active at center
frequency
1
dB
AFC active;
■
■
center frequency - no
AFC wander (see
Chapter 2.4.6.3)
D11
D12
3rd order intercept
IIP3
PIIP3
-16
-27
-14
-25
dBm
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB;
IFATT = 7;
valid for Single and
Double Down Conversion
Mode
1 dB compression
point CP1dB
PCP1dB
dBm
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB;
IFATT = 7;
■
valid for Single and
Double Down Conversion
Mode
D13
D14
1st IF image rejection dimage1
30
30
40
34
dB
dB
1st IF = 10.7 MHz
without front end SAW
filter;
valid for Double Down
Conversion Mode
2nd IF image
rejection
dimage2
2nd IF = 274 kHz
without 1st IF CER filter;
valid for Single and
Double Down Conversion
Mode
Data Sheet
138
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
RF Front End Characteristics
(Unless otherwise noted, all values apply for the specified frequency ranges)
E1
LNA input impedance
fRF = 315 MHz
E1.1
Rin_p,diff
Cin_p,diff
Rin_p,diff
Cin_p,diff
Rin_p,diff
Cin_p,diff
Rin_p,diff
Cin_p,diff
Rin_p, SE
Cin_p, SE
Rin_p, SE
Cin_p, SE
Rin_p, SE
Cin_p, SE
Rin_p, SE
Cin_p, SE
Rout_IF
680
1.05
570
0.87
550
0.63
540
0.63
500
1.87
400
1.63
322
1.59
312
1.56
330
Ω
differential parallel
equivalent input between
LNA_INP and LNA_INN
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
pF
Ω
E1.2
E1.3
E1.4
E1.5
E1.6
E1.7
E1.8
fRF = 434MHz
fRF = 868MHz
fRF = 915MHz
fRF = 315 MHz
fRF = 434MHz
fRF = 868MHz
fRF = 915MHz
pF
Ω
pF
Ω
pF
Ω
single-ended parallel
equivalent input between
LNA_INP and GNDRF /
LNA_INN and GNDRF
pF
Ω
pF
Ω
pF
Ω
pF
Ω
E2
E3
FE output
impedance
290
34
380
38
fIF = 10.7 MHz
FE voltage
conversion gain
AVFE, max
36
dB
min. IF attenuation
(IFATT = 0);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
R
load_IF = 330 Ω;
tested at 434 MHz
E4
FE voltage
AVFE_7
29
31
33
dB
IF attenuation
conversion gain
(IFATT = 7);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
R
load_IF = 330 Ω;
tested at 434 MHz
Data Sheet
139
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
E5
FE voltage
conversion gain
AVFE, min
22
24
26
dB
max. IF attenuation
(IFATT = 15);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
R
load_IF = 330 Ω;
tested at 434 MHz
E6
FE voltage
0.8
dB
12dB / 15 = 0.8dB/step
■
conversion gain step
Double Down
Conversion: 16 gain
settings (4 bit)
Single Down Conversion:
7 gain settings
E7
1st Local Oscillator SSB Noise
PLL loop Bandwidth BW
closed loop
E7.1
E7.2
100
150
-81
200
-76
kHz
BW and its tolerances
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
fin_R1 = 315MHz
fin_R2 = 434MHz
fin_R3 = 868MHz
fin_R4 = 915MHz
dSSB_LO
dSSB_LO
dSSB_LO
dSSB_LO
dBc/Hz @ foffset = 1 kHz
@ foffset = 10 kHz
@ foffset = 100 kHz
@ foffset = 1 MHz
@ foffset => 10 MHz
dBc/Hz @ foffset = 1 kHz
@ foffset = 10 kHz
@ foffset = 100 kHz
@ foffset = 1 MHz
@ foffset => 10 MHz
dBc/Hz @ foffset = 1 kHz
@ foffset = 10 kHz
@ foffset = 100 kHz
@ foffset = 1 MHz
@ foffset => 10 MHz
dBc/Hz @ foffset = 1 kHz
@ foffset = 10 kHz
@ foffset = 100 kHz
@ foffset = 1 MHz
@ foffset => 10 MHz
dBm
-85
-80
-82
-77
-120
-130
-78
-115
-125
-73
E7.3
E7.4
E7.5
-83
-78
-82
-77
-117
-130
-75
-112
-125
-70
-79
-74
-77
-72
-114
-130
-71
-109
-125
-66
-79
-74
-77
-72
-116
-130
-111
-125
-57
E8.1
E8.2
Spurious emission < 1 GHz
Spurious emission > 1 GHz
-47
dBm
Data Sheet
140
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
E9
E10
Inband fractional spur
-40
dBc
kHz
■
■
3dB Overall Analog
Frontend Bandwidth
BWANA
230
LNA input to Limiter
output, excluding external
CER filter
1st IF Buffer Characteristics
F1
F2
F3
Input impedance
Output impedance
Voltage gain
Rin_IF
290
290
3
330
330
4
370
370
5
Ω
fIF = 10...12 MHz
fIF = 10...12 MHz
fIF = 10...12 MHz
■
■
Rout_IF
AVBuffer
Ω
dB
Z
Z
source = 330 Ω
load = 330 Ω
F4
Buffer switch
isolation (CERFSEL)
disolation
60
dB
fIF = 10...12 MHz
see Figure 6
■
■
2nd IF Mixer, RSSI and Filter Characteristics
G1
Mixer input
impedance
Rin_IF
290
330
390
Ω
fIF = 10...12 MHz
G2
RSSI
Related to RF input
matched to 50 Ω
G2.1 Dynamic range
(Linearity +/- 2 dB)
DRRSSI
-110
-115
-110
-1
-30
-60
-50
+1
dBm
dBm
dBm
dB
applies for digital RSSI;
AGC on
■
■
■
■
■
applies for analog RSSI
@ 50kHz BPF, AGC off
applies for analog RSSI
@ 300kHz BPF, AGC off
G2.2 Linearity
DRLIN
-95 dBm...-35 dBm;
applies for digital RSSI
G2.3 Temperature drift
within linear dynamic
range
DRTEMP
-2.5
+1.5
dB
-95 dBm...-35 dBm;
applies for digital RSSI
G2.4 Output dynamic
range
VRSSI+
0.8
2.0
+2
12
V
G2.5 analog RSSI error,
untrimmed
DRSSIana -4
dB
at RSSI pin
G2.6 analog RSSI slope,
untrimmed
dVRSSI
dVmix_in
/
8
10
mV/dB at RSSI pin;
typical 600 mV/60 dB =
10 mV/dB
G2.7 digital RSSI error,
untrimmed
DRSSIdig_u -4
+2
dB
RSSI register readout
Data Sheet
141
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
G2.8 digital RSSI error,
user trimmed via
DRSSIdig_t -1
+1
dB
RSSI register readout
■
SFRs RSSISLOPE
and RSSIOFFS
G2.9 digital RSSI slope,
untrimmed
dVRSSI
dVmix_in
/
2
2.5
2.5
3
LSB
/dB
RSSI register readout;
typical 600 mV/60 dB =
10 mV/dB,
1mV = 1 LSB (10-bit ADC)
8-bit readout: 4mV=1LSB
G2.10 digital RSSI slope,
user trimmed via
dVRSSI
dVmix_in
/
2.35
2.65
LSB
/dB
RSSI register readout;
typical 600 mV/60 dB =
10 mV/dB,
1mV = 1 LSB (10-bit ADC)
8-bit readout: 4mV=1LSB
■
SFRs RSSISLOPE
and RSSIOFFS
G2.11 Resistive load at
RSSI pin
RL,RSSImax 100
CL,RSSI
kΩ
■
■
G2.12 Capacitive load at
RSSI pin
20
pF
G3
2nd IF Filter (3rd order Bandpass Filter)
G3.1 Center frequency
fcenter
262
274
288
kHz
kHz
Asymmetric BPF corners:
f_center=sqrt(flow * fhigh);
Use AFC for more
symmetry
G3.2 -3 dB BW
BW-3dB
50
■
80
125
200
300
G3.3 -3 dB BW tolerance tol_BW-3dB -5
G3.4 -3 dB BW tolerance tol_BW-3dB -6
+5
+6
%
%
For BW = 125, 200, 300
kHz
■
■
For BW = 50, 80 kHz
Data Sheet
142
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
Crystal Oscillator Characteristics
21.948
717
H1
Frequency range
fXTAL
MHz
fF
H2
Crystal parameters
H2.1
Motional
C1
3
6
10
■
capacitance
H2.2
H2.3
H2.4
H2.5
Motional resistance
Shunt capacitance
Load capacitance
R1
18
2
80
4
Ω
■
■
■
■
C0
pF
pF
ppm
CLoad
fXTAL_Tol
12
nominal value
Initial frequency
tolerance
-30
-50
+30
oscillator untrimmed (trim
capacitor default settings,
usage of recommended
crystal);
not including crystal
tolerances
H2.6
H2.7
H3
Frequency trimming ΔfXTAL
range
+50
4
ppm
ppm
Hz
larger trimming range
possible via SD PLL
Trimming step
ΔfX_step
1
see also step size of
SD PLL
■
■
Clock output
frequency at PPx pin
fclock_out
11
5.5M
292
10pF load
H4
Crystal oscillator
settling time
tCOSCsettle
292
292
µs
(switching from Low
Power to High
Precision Mode)
H5
Start up time
tstart_up
0.45
1
ms
crystal type:
NDK NX5032SD;
See also BOM for ext.
load caps;
Note: No SPI
communication is allowed
before XOSC start-up is
finished and chip reset is
already finished
Data Sheet
143
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
Digital Inputs/Outputs Characteristics
I1
I2
I3
High level input
voltage
VIn_High
IIn_High
VIn_Low
0.7*
VDDD
VDD5V V
+0.1
High level input
leakage current
5
µA
Low level input
voltage (except
P_ON pin)
0
0.8
V
I4
Low level input
voltage (at P_ON
pin)
VIn_Low_PON
0
0.5
V
I5
I6
Low level input
leakage current
IIn_Low
-5
µA
VDD5V
-0.4
High level output
voltage 1
VOut_High1
VDD5V V
IOH=-500 µA, static driver
capability;
Normal Pad Mode
(see register PPCFG2
and CMC0)
I7
I8
I9
Low level output
voltage 1
VOut_Low1
VOut_High2
VOut_Low2
0
0.4
V
IOL=500 µA, static driver
capability;
Normal Pad Mode
(see register PPCFG2
and CMC0)
VDD5V
-0.8
High level output
voltage 2
VDD5V V
IOH=-4 mA, static driver
capability;
High Power Pad Mode
(see register PPCFG2
and CMC0)
Low level output
voltage 2
0
0.8
V
IOL=4 mA, static driver
capability;
High Power Pad Mode
(see register PPCFG2
and CMC0)
Data Sheet
144
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
Timing SPI-Bus Characteristics
J1
Clock frequency
fclock
2.2
MHz
Note: A high SPI clock
rate during data reception
can reduce sensitivity
J2
Clock High time
Clock Low time
Active setup time
tCLK_H
tCLK_L
tsetup
200
200
200
200
200
200
200
100
100
145
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
■
■
■
■
■
■
■
■
■
■
J3
J4
J5
Not active setup time tnot_setup
Active hold time thold
Not active hold time tnot_hold
J6
J7
J8
Deselect time
SDI setup time
SDI hold time
tDeselect
tSDI_setup
tSDI_hold
tCLK_SDO
J9
J10
J11
Clock low to SDO
valid
@ Cload = 80 pF
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J12
Clock low to SDO
valid
tCLK_SDO
40
ns
@ Cload = 10 pF
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J13
J14
J15
J16
J17
SDO rise time
SDO fall time
SDO rise time
SDO fall time
SDO disable time
tSDO_r
90
90
15
15
25
ns
ns
ns
ns
ns
@ Cload = 80 pF
@ Cload = 80 pF
@ Cload = 10 pF
@ Cload = 10 pF
■
■
■
■
■
tSDO_f
tSDO_r
tSDO_f
tSDO_disable
1) Please note that the system bandwidth is smaller than the smallest bandwidth in the signal path.
Data Sheet
145
V4.0, 2010-02-19
TDA5240
Reference
Unless explicitly otherwise noted, the following test conditions apply to the given
specification values in Table 10 and items D7 and D8:
* Hardware: TDA5240 Platform Testboard V1.0
* Single-Ended Matching for 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz
* RF input matched to 50 Ω; Insertion loss of input matching network = 1dB
* Receive Frequency 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz; Lo-Side LO-Injection
* Reference Clock: XTAL=21.948717 MHz
* IF-Gain: Attenuation set to default value (IFATT = 7)
* Double Down Conversion
* 1 IF-Filter: Center=10.7MHz; BW=330kHz; Connected between IF_OUT and IFBUF_IN
* 2nd IF Filter BW: Depending on Data Rate and FSK Deviation
* Received Signal at zero Offset to IF Center Frequency
* RSSI trimmed
* FSK Pre-Demodulation Filter (PDF) BW: Depending on Data Rate and FSK Deviation
* No SPI-traffic during telegram reception, CLK_OUT disabled
* AFC and AGC are OFF, unless otherwise noted
* Specification values are in respect to Manchester-coded Infineon-Reference Pattern 1
(7 Bits '0', 1 Bit ’1', 1 Bits '0', 1 Bit ’1', 1 Bits '0', 1 Bit ’1', PRBS5 (31 Bit), 1 Bit 'M') according to Figure 18
However a Code Violation is not used as EOM criterion
BER sensitivity measurements use Receive Mode TMMF (sampled with ideal data clock)
MER sensitivity measurements use Receive Mode POF
* DRE ... Data Date Error of received telegram vs. adjusted Data Rate
* DC ... Duty Cycle
* MER ... Message Error Rate
[MER = 1 - (number_of_correctly_received_messages / number_of_transmitted messages)]
* FAR ... False Alarm Rate
[FAR = number_of_mistakenly_wake_ups / number_of_periods_searching_for_data_on_channel]
* MMR ... Missed Message Rate
[MMR = number_of_mistakenly_missed_wake_up_patterns /
number_of_periods_with_wake_up_pattern_transmitted_and_searching_for_wake_up_pattern]
* BER ... Bit Error Rate (using a PRBS9 Pseudo-Random Binary Sequence)
[BER = 1 - (number_of_correctly_received_bits / number_of_transmitted bits)]
Data Sheet
146
V4.0, 2010-02-19
TDA5240
Reference
Table 10
MER Characteristics (Receive Mode = POF)
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
Characteristics of Digital Data Filter and Data Clock Recovery
Acceptance Criterion is: MER <= 10%. For additional test conditions see right before this table.
Double Down Conversion Mode
K1
Data Rate Error of
received Telegram
Sensitivity loss < 1dB
Db
-10
10
%
at DC = 50%
■
■
K2
Duty Cycle Error of Manchester coding of received Telegram
K2.1
Sensitivity loss < 1dB
45
35
45
35
55
55
55
55
%
According to Definition B
in Chapter 2.7.2;
including
DRE of -10% to +10%;
Data Rate < 50 kBit/s
tolManch_DefB
tolManch_DefC
tolManch_DefB
tolManch_DefC
K2.2
K2.3
K2.4
Sensitivity loss <
3.5dB
%
%
%
According to Definition C
in Chapter 2.7.2
including
DRE of -10% to +10%;
Data Rate < 10 kBit/s
■
■
■
Sensitivity loss <
1.5dB
According to Definition B
in Chapter 2.7.2;
including
DRE of -10% to +10%;
Data Rate >= 50 kBit/s
Sensitivity loss < 4dB
According to Definition C
in Chapter 2.7.2
including
DRE of -10% to +10%;
Data Rate >= 10 kBit/s;
Note:
If BPF_BW / Bitrate < 12,
the selected data rate in
the configuration tool
needs to be set 5%
higher.
Data Sheet
147
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
Sensitivity of Receiver
Acceptance Criterion is: MER <= 10%. For additional test conditions see right before this table.
Double Down Conversion Mode
L1
Sensitivity Limit in ASK (OOK) Mode;
Manchester coding
At DC = 50% and
DRE = 0%.
T
amb = 25 °C,
peak power level (see
Chapter 2.7.3)
L1.1
Data Rate 0.5 kBit/s SASK1
-120
-117
dBm
peak
m = 100%
■
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode;
868/915MHz: <=1dB loss
L1.2
L1.3
L1.4
Data Rate 2 kBit/s
Data Rate 10 kBit/s
Data Rate 16 kBit/s
SASK2
SASK3
SASK4
-116
-111
-109
-113
-108
-106
dBm
peak
m = 100%
■
■
■
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
dBm
peak
m = 100%
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
dBm
peak
m = 100%
2nd IF BW = 80 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode;
868/915MHz: <=1dB loss
L1.5
L1.6
Data Rate 0.5 kBit/s SASK5
-115
-112
-112
-109
dBm
peak
m = 100%
■
■
2nd IF BW = 300 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
Data Rate 2 kBit/s
SASK6
SASK7
dBm
peak
m = 100%
2nd IF BW = 300 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
868/915MHz:<=1dBloss;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
L1.7
Data Rate 10 kBit/s
-106
-103
dBm
peak
m = 100%
■
2nd IF BW = 300 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
Data Sheet
148
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
L1.8
Data Rate 16 kBit/s
SASK8
-104
-101
dBm
peak
m = 100%
■
2nd IF BW = 300 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
L2
Sensitivity Limit in FSK Mode;
Manchester coding
At DC = 50% and
DRE = 0%.
T
amb = 25 °C
L2.1
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK1
-118
-113
-112
-115
-110
-109
dBm
dBm
dBm
2
nd IF BW = 50 kHz;
■
■
■
PDF = 33 kHz, AFC off;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
L2.2
L2.3
Data Rate 10 kBit/s; SFSK2
Δf = 14 kHz
2nd IF BW = 50 kHz;
PDF = 65 kHz, AFC off;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
Data Rate 10 kBit/s; SFSK3
2nd IF BW = 125 kHz;
Δf = 50 kHz
PDF = 132 kHz, AFC off;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode;
868/915MHz: <=1dB loss
L2.4
L2.5
Data Rate 50 kBit/s; SFSK4
Δf = 50 kHz
-106
-108
-103
-105
dBm
dBm
2nd IF BW = 300 kHz;
PDF = 239 kHz, AFC off;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
■
■
Data Rate 2 kBit/s;
SFSK5
2nd IF BW = 300 kHz;
PDF = 282 kHz;
Δf = 10 kHz
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
868/915MHz:<=1dBloss;
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
L2.6
L2.7
Data Rate 10 kBit/s; SFSK6
Δf = 14 kHz
-107
-109
-104
-106
dBm
dBm
2
nd IF BW = 300 kHz;
■
■
PDF = 282 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
Data Rate 10 kBit/s; SFSK7
Δf = 50 kHz
2nd IF BW = 300 kHz;
PDF = 282 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
Data Sheet
149
V4.0, 2010-02-19
TDA5240
Reference
#
Parameter
Symbol
Limit Values
Unit Test Conditions
Remarks
min. typ. max.
Dynamic Range of Receiver
Acceptance Criteria are: MER <= 1E-3, FAR < 1E-5, MMR < 1E-4 (Criterion: 8 Equal Bits), Manchester coding.
For additional test conditions see right before this table.
Double Down Conversion Mode
M1
Dynamic Range in ASK (OOK) Mode, AGC on
At DC = 50% and
DRE = 0%.
T
amb = 25 °C,
peak power level (see
Chapter 2.7.3)
DR2,OOK
M1.1 Data Rate 2 kBit/s
M1.2 Data Rate 10 kBit/s
M1.3 Data Rate 2 kBit/s
M1.4 Data Rate 10 kBit/s
-10
-10
-45
-60
-109
-105
-103
-99
dBm
peak
m = 100%
■
■
■
■
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
DR10,OOK
DR2,ASK50
DR10,ASK50
dBm
peak
m = 100%
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
dBm
peak
m = 50%
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
dBm
peak
m = 50%
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
M2
Dynamic Range in FSK Mode, AGC on
Data Rate 10 kBit/s & Δf = 50 kHz
At DC = 50% and
DRE = 0%.
T
amb = 25 °C
DR10,AM0
M2.1 0% AM Modulation
-10
-10
-106
-90
dBm
dBm
2nd IF BW = 125 kHz
PDF = 132 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
■
■
DR10,AM90
M2.2 90% AM Modulation,
100 Hz
2nd IF BW = 125 kHz
PDF = 132 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
Data Sheet
150
V4.0, 2010-02-19
TDA5240
Reference
Table 11
Typical Achievable Sensitivity Bandwidth [kHz]
Ceramic Filter BW = 330 kHz
Table is valid for DDC (Double Down Conversion) and SDC (Single Down Conversion)
Valid for AFC=off; For FSK & AFC=on the BW can be increased by 2*AFCLIMIT, where AFCLIMIT < 43 kHz
BPF/PDF
Filter [Hz]
Modulation FSKDeviation Sensitivity
Data Rate [bit/s], Manchester
[+/- Hz]
Loss
0.5 k
230
280
160
230
140
220
120
200
120
180
-
1 k
230
280
150
220
160
230
130
210
120
190
-
5
230
280
-
10 k
230
280
-
20 k
230
280
-
50 k
BPF = 300 k
PDF = 282 k
ASK
FSK
-
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
-
-
0.5 k
1 k
-
-
-
-
-
-
-
-
-
-
-
-
-
5 k
150
220
140
210
130
200
130
190
-
140
220
140
210
140
200
130
190
120
160
110
140
-
-
-
-
10 k
15 k
20 k
40 k
50 k
150
210
150
210
140
190
-
-
-
-
-
-
-
110
160
-
-
-
-
-
-
-
-
-
-
-
-
110
140
110
140
110
140
100
140
100
140
Data Sheet
151
V4.0, 2010-02-19
TDA5240
Reference
Table 11
Typical Achievable Sensitivity Bandwidth [kHz]
Ceramic Filter BW = 330 kHz
Table is valid for DDC (Double Down Conversion) and SDC (Single Down Conversion)
Valid for AFC=off; For FSK & AFC=on the BW can be increased by 2*AFCLIMIT, where AFCLIMIT < 43 kHz
BPF/PDF
Filter [Hz]
Modulation FSKDeviation Sensitivity
Data Rate [bit/s], Manchester
[+/- Hz]
Loss
0.5 k
180
220
140
190
130
180
100
160
100
140
-
1 k
180
220
140
190
130
190
120
170
100
150
-
5
180
220
-
10 k
180
220
-
20 k
50 k
BPF = 200 k
PDF = 239 k
ASK
FSK
-
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
180
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
220
0.5 k
1 k
-
-
-
-
-
-
-
-
-
-
-
5 k
130
180
120
170
110
150
100
140
-
130
180
120
170
110
150
100
150
90
-
10 k
15 k
20 k
40 k
50 k
140
170
120
160
110
150
-
-
-
90
-
130
-
-
-
-
-
-
120
-
-
-
-
-
-
-
-
-
-
-
Data Sheet
152
V4.0, 2010-02-19
TDA5240
Reference
Table 11
Typical Achievable Sensitivity Bandwidth [kHz]
Ceramic Filter BW = 330 kHz
Table is valid for DDC (Double Down Conversion) and SDC (Single Down Conversion)
Valid for AFC=off; For FSK & AFC=on the BW can be increased by 2*AFCLIMIT, where AFCLIMIT < 43 kHz
BPF/PDF
Filter [Hz]
Modulation FSKDeviation Sensitivity
Data Rate [bit/s], Manchester
[+/- Hz]
Loss
0.5 k
120
150
100
120
90
120
70
100
70
90
-
1 k
120
150
100
120
100
120
80
110
70
100
-
5
120
150
-
10 k
120
150
-
20 k
50 k
BPF = 125 k
PDF = 132 k
ASK
FSK
-
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
3 dB
6 dB
120
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
150
0.5 k
1 k
-
-
-
-
-
-
-
-
-
-
5 k
80
110
80
100
70
90
70
90
-
90
110
80
100
80
90
70
90
-
-
-
10 k
15 k
20 k
40 k
50 k
80
100
80
100
70
90
-
-
-
60
80
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Data Sheet
153
V4.0, 2010-02-19
TDA5240
Reference
4.2
Test Circuit - Evaluation Board v1.0
Figure 94
Test Circuit Schematic
Data Sheet
154
V4.0, 2010-02-19
TDA5240
Reference
4.3
Test Board Layout, Evaluation Board v1.0
Figure 95
Test Board Layout, Top View
Figure 96
Test Board Layout, Bottom View
Data Sheet
155
V4.0, 2010-02-19
TDA5240
Reference
Figure 97
Test Board Layout, Component View
Data Sheet
156
V4.0, 2010-02-19
TDA5240
Reference
4.4
Bill of Materials
Pos Part Value
Package
Device /
Type
Tolerance
Manufacturer
Remark/Options
(RF+supply variant)
1
2
3
4
5
6
IC1
C1
C2
C3
C4
C5
TDA5240 PG-TSSOP-28
Infineon
3.9 pF
3.9 pF
100 nF
100 nF
0603
0603
0603
0603
0603
C0G
C0G
X7R
X7R
+/- 0.1 pF
+/- 0.1 pF
+/- 10 %
+/- 10 %
+/- 10 %
crystal oscillator load
crystal oscillator load
100 nF /
( 1 µF )
X7R /
X5R
3.3V /
( 5 V environment)
7
8
C6
C7
100 nF
1 pF
0603
0603
0603
0603
0603
0603
0603
0603
0603
SMC-A
0603
0603
0603
0603
0603
0603
0603
X7R
C0G
C0G
C0G
C0G
C0G
C0G
C0G
C0G
Tantal
X7R
X7R
+/- 10 %
+/- 0.1 pF
+/- 0.1 pF
matching for 315MHz
matching for 434MHz
matching for 868MHz
matching for 915MHz
matching for 315MHz
matching for 434MHz
matching for 868MHz
matching for 915MHz
polarized capacitor
0.5 pF
open
1 pF
+/- 0.1 pF
9
C8
open
open
2.7 pF
5.1 pF
1 µF
+/- 0.1 pF
+/- 0.1 pF
+/- 10%
+/- 10%
+/- 10%
+/- 2%
10
11
12
13
C9
C10
C11
L1
100 nF
10 nF
68 nH
39 nH
22 nH
15 nH
matching for 315MHz
matching for 434MHz
matching for 868MHz
matching for 915MHz
+/- 2%
+/- 2%
+/- 2%
14
15
16
R1
R2
R3
10 Ohm /
(open)
+/- 5%
3.3 V /
( 5 V environment)
4.7 Ohm / 0603
(open)
+/- 5%
+/- 5%
3.3 V /
( 5 V environment)
4.7 Ohm / 0603
(22 Ohm)
3.3 V /
( 5 V environment)
17
18
R4
0 Ohm
0603
IF1
SFECF10
M7EA00
Murata
BW = 330 kHz
SMD crystal
19
Q1
21.948717 NX5032SD
MHz
C0=1.7 pF
C1=7 fF
CL=12 pF
NDK (Frischer
Electronic),
EXS00A-
CS01580
Data Sheet
157
V4.0, 2010-02-19
TDA5240
Reference
Pos Part Value
Interface / optional
Package
Device /
Type
Tolerance
Manufacturer
Remark/Options
(RF+supply variant)
20
IC2
AT24C32 SOIC8
C-SH-B or
AT24C512
EEPROM for board
detection
21
C12
open
0603
X7R
+/- 10%
RSSI measurement
low pass
22
23
24
C13
C14
C15
100 nF
1 µF
0603
X7R
+/- 10%
+/- 10%
+/- 10%
SMC-A
0603
Tantal
X7R
polarized capacitor
10 nF
filter network on
supply line
25
26
27
C16
L2
10 nF
0 Ohm
open
0603
0603
0603
X7R
+/- 10%
filter network on
supply line
no filter network on
supply line
R5
RSSI measurement
low pass
28
29
R6
R7
1 kOhm
0 Ohm
0603
0603
write protection for
EEPROM
30
31
32
D1
IF2
X1
LED
LS M676-
P251-1
status indication LED
open
Murata
2nd IF filter is
optional
SMA
RF input
socket
33
34
X2
X3
3 pins
2 pins
Board supply
Chip supply current
(jumper closed)
35
36
37
X4
X5
X6
50 pins
2 pins
SIB-QTS-025-
01-X-D-RA
Samtec
Connector to
PC/µC/Interface
RSSI measuring
point
12 pins
Interface line
measuring point
38
39
40
X7
X8
4 pins
4 pins
GND
GND
Jum- 2 pins
per 1
Jumper for X3
41
Jum- 2 pins
per 2
Jumper for X2 -
Supply by interface
Board material 1.5mm FR4 with 35µm copper on both sides
Data Sheet
158
V4.0, 2010-02-19
TDA5240
Package Outlines
5
Package Outlines
1)
±0.1
4.4
B
+0.075
-0.035
0.125
0.65
C
+0.08 2)
-0.03
0.1
0.22
+0.15
-0.1
0.6
M
0.1 A C 28x
6.4
28
15
28x
0.2 B
1
14
1)
±0.1
9.7
A
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion
Figure 98
Table 12
PG-TSSOP-28 Package Outline (green package)
Order Information
Type
Ordering Code
Package
PG-TSSOP-28
TDA5240
SP000550860
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”:http://www.infineon.com/products
Dimensions in mm
V4.0, 2010-02-19
SMD = Surface Mounted Device
Data Sheet
159
TDA5240
Page
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AGC Settings 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AGC Settings 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Power Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Supply Operating Range and Ambient Temperature. . . . . . . . . . . . . 132
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
MER Characteristics (Receive Mode = POF) . . . . . . . . . . . . . . . . . . 147
Typical Achievable Sensitivity Bandwidth [kHz]. . . . . . . . . . . . . . . . . 151
Order Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Data Sheet
160
V4.0, 2010-02-19
TDA5240
Page
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TDA5240 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Block Diagram RF Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Single Down Conversion (SDC, no external filters required) . . . . . . . . 20
Double Down Conversion (DDC) with one external filter . . . . . . . . . . . 21
Double Down Conversion (DDC) with two external filters . . . . . . . . . . 21
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
External Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Synthesizer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Functional Block Diagram ASK/FSK Demodulator . . . . . . . . . . . . . . . 27
AFC Loop Filter (I-PI Filtering and Mapping) . . . . . . . . . . . . . . . . . . . . 29
Analog RSSI output curve with AGC action ON (blue) vs. OFF (black) 30
Peak Detector Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Peak Detector Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Functional Block Diagram Digital Baseband Receiver. . . . . . . . . . . . . 38
Signal Detector Threshold Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Coding Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Manchester Symbols including Code Violations . . . . . . . . . . . . . . . . . 42
Clock Recovery (ADPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
RUNIN Generation Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Definition of Tolerance Windows for the CDR . . . . . . . . . . . . . . . . . . . 46
Data Rate Acceptance Limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Wake-Up Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
RSSI Blocking Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Wake-Up Data Criteria Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Frame Synchronization Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
16-Bit TSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8-Bit Parallel TSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8-Bit Extended TSI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8-Bit Gap TSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 1 . . . . . 60
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 0 . . . . . 61
TSIGap TSIB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TVWIN and TSIGAP dependency example . . . . . . . . . . . . . . . . . . . . . 62
4-Byte Message ID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2-Byte Message ID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Structure of Payload Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Data Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3 Volts and 5 Volts Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Supply Current Ramp Up/Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Data Sheet
161
V4.0, 2010-02-19
TDA5240
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Figure 83
Figure 84
Figure 85
Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Logical and electrical System Interfaces of the TDA5240 . . . . . . . . . . 75
Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Data interface for the Packet Oriented FIFO Mode . . . . . . . . . . . . . . . 77
Data interface for the Packet Oriented Transparent Payload Mode . . 77
Timing of the Packet Oriented Transparent Payload Mode . . . . . . . . . 78
Data interface for the Transparent Mode - Chip Data and Strobe . . . . 78
Timing of the Transparent Mode - Chip Data and Strobe . . . . . . . . . . 79
Data interface for the Transparent Modes TMMF / TMRDS . . . . . . . . 79
External Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Receive FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
FIFO Lock Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SPI Data FIFO Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Interrupt Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Interrupt Generation Waveform (Example for Configuration A+B). . . . 87
ISx Readout Set Clear Collision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Burst Read Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Burst Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SPI Checksum Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Read FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chip Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Global State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Run Mode Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
HOLD State Behavior (INITPLLHOLD disabled) . . . . . . . . . . . . . . . . . 99
HOLD State Behavior (INITPLLHOLD enabled) . . . . . . . . . . . . . . . . . 99
SPM - TX-RX Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Wake-up Search with Configuration A . . . . . . . . . . . . . . . . . . . . . . . . 102
Wake-up Search with Configuration B, C, D . . . . . . . . . . . . . . . . . . . 103
TOTIM Behavior without Presence of Interferer . . . . . . . . . . . . . . . . 105
TOTIM Behavior in Presence of Interferer. . . . . . . . . . . . . . . . . . . . . 106
Run Mode Self Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Parallel Wake-up Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Polling Timer Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Constant On-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
COO Polling in WU on RSSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Ultrafast Fall Back to SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
UFFB activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Fast Fall Back to SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Mixed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Data Sheet
162
V4.0, 2010-02-19
TDA5240
Figure 86
Figure 87
Figure 88
Figure 89
Figure 90
Figure 91
Figure 92
Figure 93
Figure 94
Figure 95
Figure 96
Figure 97
Figure 98
Permanent Wake-Up Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Active Idle Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Definition A: Level-based definition . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition B: Chip-based definition. . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Definition C: Edge delay definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SFR Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SFR Address Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Test Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Test Board Layout, Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Test Board Layout, Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Test Board Layout, Component View . . . . . . . . . . . . . . . . . . . . . . . . 156
PG-TSSOP-28 Package Outline (green package). . . . . . . . . . . . . . . 159
Data Sheet
163
V4.0, 2010-02-19
TDA5240
Data Sheet
164
V4.0, 2010-02-19
TDA5240
Appendix - Registers Chapter
Data Sheet
165
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Appendix - Registers Chapter
Register Overview
Table 1
Register Short Name
Appendix - Registers Chapter, Register Description
Register Overview
Register Long Name
Offset Address Page Number
A_MID0
Message ID Register 0
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
000H
001H
002H
003H
004H
005H
006H
007H
008H
009H
00AH
00BH
00CH
00DH
00EH
00FH
010H
011H
012H
013H
014H
015H
016H
017H
018H
019H
01AH
193
193
193
194
194
194
195
195
196
196
196
197
197
197
198
198
198
199
199
200
200
200
201
202
203
204
204
205
205
A_MID1
A_MID2
A_MID3
A_MID4
A_MID5
A_MID6
A_MID7
A_MID8
A_MID9
A_MID10
A_MID11
A_MID12
A_MID13
A_MID14
A_MID15
A_MID16
A_MID17
A_MID18
A_MID19
A_MIDC0
A_MIDC1
A_IF1
A_WUC
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
A_WUPAT0
A_WUPAT1
A_WUBCNT
A_WURSSITH1
A_WURSSIBL1
RSSI Wake-Up Threshold for Channel 1 Register 01BH
RSSI Wake-Up Blocking Level Low Channel 1
Register
01CH
A_WURSSIBH1
A_WURSSITH2
RSSI Wake-Up Blocking Level High Channel 1
Register
01DH
206
206
RSSI Wake-Up Threshold for Channel 2 Register 01EH
Data Sheet
166
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
A_WURSSIBL2
Register Long Name
Offset Address Page Number
RSSI Wake-Up Blocking Level Low Channel 2
Register
01FH
207
A_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
020H
207
A_WURSSITH3
A_WURSSIBL3
RSSI Wake-Up Threshold for Channel 3 Register 021H
208
208
RSSI Wake-Up Blocking Level Low Channel 3
Register
022H
A_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
023H
208
A_SIGDETSAT
A_WULOT
Signal Detector Saturation Threshold Register
Wake-up on Level Observation Time Register
Synchronization Search Time-Out Register
SYNC Timeout Timer Register
024H
025H
026H
027H
028H
029H
02AH
02BH
02CH
02DH
02EH
02FH
030H
031H
032H
033H
034H
035H
036H
037H
038H
039H
03AH
03BH
03CH
03DH
03EH
03FH
209
209
210
210
211
211
212
212
213
214
214
215
215
215
216
217
218
219
219
220
221
221
222
222
223
223
223
224
A_SYSRCTO
A_TOTIM_SYNC
A_TOTIM_TSI
A_TOTIM_EOM
A_AFCLIMIT
A_AFCAGCD
A_AFCSFCFG
A_AFCK1CFG0
A_AFCK1CFG1
A_AFCK2CFG0
A_AFCK2CFG1
A_PMFUDSF
A_AGCSFCFG
A_AGCCFG0
A_AGCCFG1
A_AGCTHR
TSI Timeout Timer Register
EOM Timeout Timer Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
A_DIGRXC
Digital Receiver Configuration Register
RSSI Peak Detector Bit Position Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
A_PKBITPOS
A_ISUPFCSEL
A_PDECF
A_PDECSCFSK
A_PDECSCASK
A_MFC
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
A_SRC
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
A_EXTSLC
A_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
A_SIGDET1
Signal Detector Threshold Level Register -
Wakeup
040H
224
Data Sheet
167
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
A_SIGDETLO
A_SIGDETSEL
A_SIGDETCFG
A_NDTHRES
Register Long Name
Offset Address Page Number
Signal Detector Threshold Low Level Register
Signal Detector Range Selection Register
Signal Detector Configuration Register
FSK Noise Detector Threshold Register
FSK Noise Detector Configuration Register
041H
042H
043H
044H
045H
046H
225
225
226
227
227
228
A_NDCONFIG
A_CDRP
Clock and Data Recovery P Configuration
Register
A_CDRI
Clock and Data Recovery Configuration Register 047H
229
230
A_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
048H
A_CDRTOLC
A_CDRTOLB
A_TVWIN
CDR DC Chip Tolerance Register
CDR DC Bit Tolerance Register
Timing Violation Window Register
Slicer Configuration Register
049H
04AH
04BH
04CH
04DH
04EH
04FH
050H
051H
052H
053H
054H
055H
056H
057H
058H
059H
231
232
232
233
233
234
235
235
236
236
237
237
237
238
238
239
240
241
241
242
242
243
243
244
244
244
245
245
246
A_SLCCFG
A_TSIMODE
A_TSILENA
TSI Detection Mode Register
TSI Length Register A
A_TSILENB
TSI Length Register B
A_TSIGAP
TSI Gap Length Register
A_TSIPTA0
TSI Pattern Data Reference A Register 0
TSI Pattern Data Reference A Register 1
TSI Pattern Data Reference B Register 0
TSI Pattern Data Reference B Register 1
End Of Message Control Register
EOM Data Length Limit Register
EOM Data Length Limit Parallel Mode Register
Channel Configuration Register
PLL MMD Integer Value Register Channel 1
A_TSIPTA1
A_TSIPTB0
A_TSIPTB1
A_EOMC
A_EOMDLEN
A_EOMDLENP
A_CHCFG
A_PLLINTC1
A_PLLFRAC0C1
A_PLLFRAC1C1
A_PLLFRAC2C1
A_PLLINTC2
A_PLLFRAC0C2
A_PLLFRAC1C2
A_PLLFRAC2C2
A_PLLINTC3
A_PLLFRAC0C3
A_PLLFRAC1C3
A_PLLFRAC2C3
SFRPAGE
PLL Fractional Division Ratio Register 0 Channel 1 05AH
PLL Fractional Division Ratio Register 1 Channel 1 05BH
PLL Fractional Division Ratio Register 2 Channel 1 05CH
PLL MMD Integer Value Register Channel 2
05DH
PLL Fractional Division Ratio Register 0 Channel 2 05EH
PLL Fractional Division Ratio Register 1 Channel 2 05FH
PLL Fractional Division Ratio Register 2 Channel 2 060H
PLL MMD Integer Value Register Channel 3
061H
PLL Fractional Division Ratio Register 0 Channel 3 062H
PLL Fractional Division Ratio Register 1 Channel 3 063H
PLL Fractional Division Ratio Register 2 Channel 3 064H
Special Function Register Page Register
080H
Data Sheet
168
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
PPCFG0
Register Long Name
Offset Address Page Number
PP0 and PP1 Configuration Register
PP2 and PP3 Configuration Register
PPx Port Configuration Register
RX RUN Configuration Register 0
RX RUN Configuration Register 1
Clock Divider Register 0
081H
082H
083H
084H
085H
086H
087H
088H
089H
08AH
08BH
08CH
08DH
08EH
08FH
090H
091H
092H
246
247
249
250
251
252
252
252
253
254
254
255
255
256
257
257
257
258
PPCFG1
PPCFG2
RXRUNCFG0
RXRUNCFG1
CLKOUT0
CLKOUT1
Clock Divider Register 1
CLKOUT2
Clock Divider Register 2
RFC
RF Control Register
BPFCALCFG0
BPFCALCFG1
XTALCAL0
XTALCAL1
RSSIMONC
ADCINSEL
RSSIOFFS
RSSISLOPE
CDRDRTHRP
BPF Calibration Configuration Register 0
BPF Calibration Configuration Register 1
XTAL Coarse Calibration Register
XTAL Fine Calibration Register
RSSI Monitor Configuration Register
ADC Input Selection Register
RSSI Offset Register
RSSI Slope Register
CDR Data Rate Acceptance Positive Threshold
Register
CDRDRTHRN
CDR Data Rate Acceptance Negative Threshold 093H
Register
258
IM0
Interrupt Mask Register 0
094H
095H
096H
097H
098H
099H
09AH
09BH
09CH
09DH
09EH
09FH
0A0H
0A1H
0A2H
0A3H
0A4H
0A5H
259
260
261
261
262
262
263
263
264
264
265
265
266
266
267
267
268
269
IM1
Interrupt Mask Register 1
SPMAP
Self Polling Mode Active Periods Register
Self Polling Mode Idle Periods Register
Self Polling Mode Control Register
SPMIP
SPMC
SPMRT
Self Polling Mode Reference Timer Register
Self Polling Mode Off Time Register 0
Self Polling Mode Off Time Register 1
Self Polling Mode On Time Config A Register 0
Self Polling Mode On Time Config A Register 1
Self Polling Mode On Time Config B Register 0
Self Polling Mode On Time Config B Register 1
Self Polling Mode On Time Config C Register 0
Self Polling Mode On Time Config C Register 1
Self Polling Mode On Time Config D Register 0
Self Polling Mode On Time Config D Register 1
External Processing Command Register
Chip Mode Control Register 1
SPMOFFT0
SPMOFFT1
SPMONTA0
SPMONTA1
SPMONTB0
SPMONTB1
SPMONTC0
SPMONTC1
SPMONTD0
SPMONTD1
EXTPCMD
CMC1
Data Sheet
169
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address Page Number
CMC0
Chip Mode Control Register 0
Wakeup Peak Detector Readout Register
Interrupt Status Register 0
0A6H
0A7H
0A8H
0A9H
0AAH
270
271
271
272
274
RSSIPWU
IS0
IS1
Interrupt Status Register 1
RFPLLACC
RF PLL Actual Channel and Configuration
Register
RSSIPRX
RSSIPPL
PLDLEN
ADCRESH
ADCRESL
VACRES
AFCOFFSET
AGCGAINR
SPIAT
RSSI Peak Detector Readout Register
RSSI Payload Peak Detector Readout Register
Payload Data Length Register
ADC Result High Byte Register
ADC Result Low Byte Register
VCO Autocalibration Result Readout Register
AFC Offset Read Register
AGC Gain Readout Register
SPI Address Tracer Register
SPI Data Tracer Register
SPI Checksum Register
0ABH
0ACH
0ADH
0AEH
0AFH
0B0H
0B1H
0B2H
0B3H
0B4H
0B5H
0B6H
0B7H
0B8H
0B9H
0BAH
0BBH
0BCH
0BDH
100H
101H
102H
103H
104H
105H
106H
107H
108H
109H
10AH
10BH
10CH
10DH
275
275
275
276
276
277
277
278
278
279
279
280
280
280
281
281
281
282
282
SPIDT
SPICHKSUM
SN0
Serial Number Register 0
Serial Number Register 1
Serial Number Register 2
Serial Number Register 3
RSSI Readout Register
SN1
SN2
SN3
RSSIRX
RSSIPMF
SPWR
RSSI Peak Memory Filter Readout Register
Signal Power Readout Register
Noise Power Readout Register
Message ID Register 0
NPWR
B_MID0
B_MID1
B_MID2
B_MID3
B_MID4
B_MID5
B_MID6
B_MID7
B_MID8
B_MID9
B_MID10
B_MID11
B_MID12
B_MID13
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Data Sheet
170
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
B_MID14
Register Long Name
Offset Address Page Number
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
10EH
10FH
110H
111H
112H
113H
114H
115H
116H
117H
118H
119H
11AH
B_MID15
B_MID16
B_MID17
B_MID18
B_MID19
B_MIDC0
B_MIDC1
B_IF1
B_WUC
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
B_WUPAT0
B_WUPAT1
B_WUBCNT
B_WURSSITH1
B_WURSSIBL1
RSSI Wake-Up Threshold for Channel 1 Register 11BH
RSSI Wake-Up Blocking Level Low Channel 1
Register
11CH
B_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
11DH
B_WURSSITH2
B_WURSSIBL2
RSSI Wake-Up Threshold for Channel 2 Register 11EH
RSSI Wake-Up Blocking Level Low Channel 2
Register
11FH
B_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
120H
B_WURSSITH3
B_WURSSIBL3
RSSI Wake-Up Threshold for Channel 3 Register 121H
RSSI Wake-Up Blocking Level Low Channel 3
Register
122H
B_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
123H
B_SIGDETSAT
B_WULOT
Signal Detector Saturation Threshold Register
Wake-Up on Level Observation Time Register
Synchronization Search Time-Out Register
SYNC Timeout Timer Register
124H
125H
126H
127H
128H
129H
12AH
12BH
12CH
12DH
12EH
12FH
B_SYSRCTO
B_TOTIM_SYNC
B_TOTIM_TSI
B_TOTIM_EOM
B_AFCLIMIT
TSI Timeout Timer Register
EOM Timeout Timer Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
B_AFCAGCD
B_AFCSFCFG
B_AFCK1CFG0
B_AFCK1CFG1
B_AFCK2CFG0
Data Sheet
171
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
B_AFCK2CFG1
B_PMFUDSF
B_AGCSFCFG
B_AGCCFG0
B_AGCCFG1
B_AGCTHR
B_DIGRXC
Register Long Name
Offset Address Page Number
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
130H
131H
132H
133H
134H
135H
136H
137H
138H
139H
13AH
13BH
13CH
13DH
13EH
13FH
AGC Configuration Register 1
AGC Threshold Register
Digital Receiver Configuration Register
RSSI Peak Detector Bit Position Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
B_PKBITPOS
B_ISUPFCSEL
B_PDECF
B_PDECSCFSK
B_PDECSCASK
B_MFC
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
B_SRC
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
B_EXTSLC
B_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
B_SIGDET1
Signal Detector Threshold Level Register -
Wakeup
140H
B_SIGDETLO
B_SIGDETSEL
B_SIGDETCFG
B_NDTHRES
B_NDCONFIG
B_CDRP
Signal Detector Threshold Low Level Register
Signal Detector Range Selection Register
Signal Detector Configuration Register
FSK Noise Detector Threshold Register
FSK Noise Detector Configuration Register
141H
142H
143H
144H
145H
146H
Clock and Data Recovery P Configuration
Register
B_CDRI
Clock and Data Recovery Configuration Register 147H
B_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
148H
B_CDRTOLC
B_CDRTOLB
B_TVWIN
CDR DC Chip Tolerance Register
CDR DC Bit Tolerance Register
Timing Violation Window Register
Slicer Configuration Register
TSI Detection Mode Register
TSI Length Register A
149H
14AH
14BH
14CH
14DH
14EH
14FH
150H
151H
152H
B_SLCCFG
B_TSIMODE
B_TSILENA
B_TSILENB
B_TSIGAP
B_TSIPTA0
B_TSIPTA1
TSI Length Register B
TSI Gap Length Register
TSI Pattern Data Reference A Register 0
TSI Pattern Data Reference A Register 1
Data Sheet
172
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
B_TSIPTB0
B_TSIPTB1
B_EOMC
Register Long Name
Offset Address Page Number
TSI Pattern Data Reference B Register 0
TSI Pattern Data Reference B Register 1
End Of Message Control Register
EOM Data Length Limit Register
153H
154H
155H
156H
157H
158H
159H
B_EOMDLEN
B_EOMDLENP
B_CHCFG
EOM Data Length Limit Parallel Mode Register
Channel Configuration Register
B_PLLINTC1
B_PLLFRAC0C1
B_PLLFRAC1C1
B_PLLFRAC2C1
B_PLLINTC2
B_PLLFRAC0C2
B_PLLFRAC1C2
B_PLLFRAC2C2
B_PLLINTC3
B_PLLFRAC0C3
B_PLLFRAC1C3
B_PLLFRAC2C3
C_MID0
PLL MMD Integer Value Register Channel 1
PLL Fractional Division Ratio Register 0 Channel 1 15AH
PLL Fractional Division Ratio Register 1 Channel 1 15BH
PLL Fractional Division Ratio Register 2 Channel 1 15CH
PLL MMD Integer Value Register Channel 2
15DH
PLL Fractional Division Ratio Register 0 Channel 2 15EH
PLL Fractional Division Ratio Register 1 Channel 2 15FH
PLL Fractional Division Ratio Register 2 Channel 2 160H
PLL MMD Integer Value Register Channel 3
161H
PLL Fractional Division Ratio Register 0 Channel 3 162H
PLL Fractional Division Ratio Register 1 Channel 3 163H
PLL Fractional Division Ratio Register 2 Channel 3 164H
Message ID Register 0
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
200H
201H
202H
203H
204H
205H
206H
207H
208H
209H
20AH
20BH
20CH
20DH
20EH
20FH
210H
211H
212H
213H
C_MID1
C_MID2
C_MID3
C_MID4
C_MID5
C_MID6
C_MID7
C_MID8
C_MID9
C_MID10
C_MID11
C_MID12
C_MID13
C_MID14
C_MID15
C_MID16
C_MID17
C_MID18
C_MID19
Data Sheet
173
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
C_MIDC0
Register Long Name
Offset Address Page Number
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
214H
215H
216H
217H
218H
219H
21AH
C_MIDC1
C_IF1
C_WUC
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
C_WUPAT0
C_WUPAT1
C_WUBCNT
C_WURSSITH1
C_WURSSIBL1
RSSI Wake-Up Threshold for Channel 1 Register 21BH
RSSI Wake-Up Blocking Level Low Channel 1
Register
21CH
C_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
21DH
C_WURSSITH2
C_WURSSIBL2
RSSI Wake-Up Threshold for Channel 2 Register 21EH
RSSI Wake-Up Blocking Level Low Channel 2
Register
21FH
C_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
220H
C_WURSSITH3
C_WURSSIBL3
RSSI Wake-Up Threshold for Channel 3 Register 221H
RSSI Wake-Up Blocking Level Low Channel 3
Register
222H
C_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
223H
C_SIGDETSAT
C_WULOT
Signal Detector Saturation Threshold Register
Wake-Up on Level Observation Time Register
Synchronization Search Time-Out Register
SYNC Timeout Timer Register
224H
225H
226H
227H
228H
229H
22AH
22BH
22CH
22DH
22EH
22FH
230H
231H
232H
233H
234H
235H
C_SYSRCTO
C_TOTIM_SYNC
C_TOTIM_TSI
C_TOTIM_EOM
C_AFCLIMIT
TSI Timeout Timer Register
EOM Timeout Timer Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
C_AFCAGCD
C_AFCSFCFG
C_AFCK1CFG0
C_AFCK1CFG1
C_AFCK2CFG0
C_AFCK2CFG1
C_PMFUDSF
C_AGCSFCFG
C_AGCCFG0
C_AGCCFG1
C_AGCTHR
AGC Configuration Register 1
AGC Threshold Register
Data Sheet
174
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
C_DIGRXC
Register Long Name
Offset Address Page Number
Digital Receiver Configuration Register
RSSI Peak Detector Bit Position Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
236H
237H
238H
239H
23AH
23BH
23CH
23DH
23EH
23FH
C_PKBITPOS
C_ISUPFCSEL
C_PDECF
C_PDECSCFSK
C_PDECSCASK
C_MFC
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
C_SRC
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
C_EXTSLC
C_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
C_SIGDET1
Signal Detector Threshold Level Register -
Wakeup
240H
C_SIGDETLO
C_SIGDETSEL
C_SIGDETCFG
C_NDTHRES
C_NDCONFIG
C_CDRP
Signal Detector Threshold Low Level Register
Signal Detector Range Selection Register
Signal Detector Configuration Register
FSK Noise Detector Threshold Register
FSK Noise Detector Configuration Register
241H
242H
243H
244H
245H
246H
Clock and Data Recovery P Configuration
Register
C_CDRI
Clock and Data Recovery Configuration Register 247H
C_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
248H
C_CDRTOLC
C_CDRTOLB
C_TVWIN
CDR DC Chip Tolerance Register
CDR DC Bit Tolerance Register
Timing Violation Window Register
Slicer Configuration Register
249H
24AH
24BH
24CH
24DH
24EH
24FH
250H
251H
252H
253H
254H
255H
256H
257H
258H
C_SLCCFG
C_TSIMODE
C_TSILENA
C_TSILENB
C_TSIGAP
TSI Detection Mode Register
TSI Length Register A
TSI Length Register B
TSI Gap Length Register
C_TSIPTA0
C_TSIPTA1
C_TSIPTB0
C_TSIPTB1
C_EOMC
TSI Pattern Data Reference A Register 0
TSI Pattern Data Reference A Register 1
TSI Pattern Data Reference B Register 0
TSI Pattern Data Reference B Register 1
End Of Message Control Register
EOM Data Length Limit Register
EOM Data Length Limit Parallel Mode Register
Channel Configuration Register
C_EOMDLEN
C_EOMDLENP
C_CHCFG
Data Sheet
175
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
C_PLLINTC1
C_PLLFRAC0C1
C_PLLFRAC1C1
C_PLLFRAC2C1
C_PLLINTC2
C_PLLFRAC0C2
C_PLLFRAC1C2
C_PLLFRAC2C2
C_PLLINTC3
C_PLLFRAC0C3
C_PLLFRAC1C3
C_PLLFRAC2C3
D_MID0
Register Long Name
Offset Address Page Number
PLL MMD Integer Value Register Channel 1
259H
PLL Fractional Division Ratio Register 0 Channel 1 25AH
PLL Fractional Division Ratio Register 1 Channel 1 25BH
PLL Fractional Division Ratio Register 2 Channel 1 25CH
PLL MMD Integer Value Register Channel 2
25DH
PLL Fractional Division Ratio Register 0 Channel 2 25EH
PLL Fractional Division Ratio Register 1 Channel 2 25FH
PLL Fractional Division Ratio Register 2 Channel 2 260H
PLL MMD Integer Value Register Channel 3
261H
PLL Fractional Division Ratio Register 0 Channel 3 262H
PLL Fractional Division Ratio Register 1 Channel 3 263H
PLL Fractional Division Ratio Register 2 Channel 3 264H
Message ID Register 0
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
300H
301H
302H
303H
304H
305H
306H
307H
308H
309H
30AH
30BH
30CH
30DH
30EH
30FH
310H
311H
312H
313H
314H
315H
316H
317H
318H
319H
D_MID1
D_MID2
D_MID3
D_MID4
D_MID5
D_MID6
D_MID7
D_MID8
D_MID9
D_MID10
D_MID11
D_MID12
D_MID13
D_MID14
D_MID15
D_MID16
D_MID17
D_MID18
D_MID19
D_MIDC0
D_MIDC1
D_IF1
D_WUC
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
D_WUPAT0
D_WUPAT1
Data Sheet
176
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
D_WUBCNT
Register Long Name
Offset Address Page Number
Wake-Up Bit or Chip Count Register
31AH
D_WURSSITH1
D_WURSSIBL1
RSSI Wake-Up Threshold for Channel 1 Register 31BH
RSSI Wake-Up Blocking Level Low Channel 1
Register
31CH
D_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
31DH
D_WURSSITH2
D_WURSSIBL2
RSSI Wake-Up Threshold for Channel 2 Register 31EH
RSSI Wake-Up Blocking Level Low Channel 2
Register
31FH
D_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
320H
D_WURSSITH3
D_WURSSIBL3
RSSI Wake-Up Threshold for Channel 3 Register 321H
RSSI Wake-Up Blocking Level Low Channel 3
Register
322H
D_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
323H
D_SIGDETSAT
D_WULOT
Signal Detector Saturation Threshold Register
Wake-Up on Level Observation Time Register
Synchronization Search Time-Out Register
SYNC Timeout Timer Register
324H
325H
326H
327H
328H
329H
32AH
32BH
32CH
32DH
32EH
32FH
330H
331H
332H
333H
334H
335H
336H
337H
338H
339H
33AH
33BH
D_SYSRCTO
D_TOTIM_SYNC
D_TOTIM_TSI
D_TOTIM_EOM
D_AFCLIMIT
D_AFCAGCD
D_AFCSFCFG
D_AFCK1CFG0
D_AFCK1CFG1
D_AFCK2CFG0
D_AFCK2CFG1
D_PMFUDSF
D_AGCSFCFG
D_AGCCFG0
D_AGCCFG1
D_AGCTHR
TSI Timeout Timer Register
EOM Timeout Timer Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
D_DIGRXC
Digital Receiver Configuration Register
RSSI Peak Detector Bit Position Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
D_PKBITPOS
D_ISUPFCSEL
D_PDECF
D_PDECSCFSK
D_PDECSCASK
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Data Sheet
177
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
D_MFC
Register Long Name
Offset Address Page Number
Matched Filter Control Register
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
33CH
33DH
33EH
33FH
D_SRC
D_EXTSLC
D_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
D_SIGDET1
Signal Detector Threshold Level Register -
Wakeup
340H
D_SIGDETLO
D_SIGDETSEL
D_SIGDETCFG
D_NDTHRES
D_NDCONFIG
D_CDRP
Signal Detector Threshold Low Level Register
Signal Detector Range Selection Register
Signal Detector Configuration Register
FSK Noise Detector Threshold Register
FSK Noise Detector Configuration Register
341H
342H
343H
344H
345H
346H
Clock and Data Recovery P Configuration
Register
D_CDRI
Clock and Data Recovery Configuration Register 347H
D_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
348H
D_CDRTOLC
D_CDRTOLB
D_TVWIN
CDR DC Chip Tolerance Register
CDR DC Bit Tolerance Register
Timing Violation Window Register
Slicer Configuration Register
349H
34AH
34BH
34CH
34DH
34EH
34FH
350H
351H
352H
353H
354H
355H
356H
357H
358H
359H
D_SLCCFG
D_TSIMODE
D_TSILENA
D_TSILENB
D_TSIGAP
TSI Detection Mode Register
TSI Length Register A
TSI Length Register B
TSI Gap Length Register
D_TSIPTA0
TSI Pattern Data Reference A Register 0
TSI Pattern Data Reference A Register 1
TSI Pattern Data Reference B Register 0
TSI Pattern Data Reference B Register 1
End Of Message Control Register
EOM Data Length Limit Register
EOM Data Length Limit Parallel Mode Register
Channel Configuration Register
PLL MMD Integer Value Register Channel 1
D_TSIPTA1
D_TSIPTB0
D_TSIPTB1
D_EOMC
D_EOMDLEN
D_EOMDLENP
D_CHCFG
D_PLLINTC1
D_PLLFRAC0C1
D_PLLFRAC1C1
D_PLLFRAC2C1
D_PLLINTC2
D_PLLFRAC0C2
PLL Fractional Division Ratio Register 0 Channel 1 35AH
PLL Fractional Division Ratio Register 1 Channel 1 35BH
PLL Fractional Division Ratio Register 2 Channel 1 35CH
PLL MMD Integer Value Register Channel 2
35DH
PLL Fractional Division Ratio Register 0 Channel 2 35EH
Data Sheet
178
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
D_PLLFRAC1C2
D_PLLFRAC2C2
D_PLLINTC3
Register Long Name
Offset Address Page Number
PLL Fractional Division Ratio Register 1 Channel 2 35FH
PLL Fractional Division Ratio Register 2 Channel 2 360H
PLL MMD Integer Value Register Channel 3
361H
D_PLLFRAC0C3
D_PLLFRAC1C3
D_PLLFRAC2C3
PLL Fractional Division Ratio Register 0 Channel 3 362H
PLL Fractional Division Ratio Register 1 Channel 3 363H
PLL Fractional Division Ratio Register 2 Channel 3 364H
Table 2
Register Overview and Reset Value
Register Short Name
Register Long Name
Offset Address Reset Value
Appendix - Registers Chapter, Register Description
A_MID0
Message ID Register 0
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
000H
001H
002H
003H
004H
005H
006H
007H
008H
009H
00AH
00BH
00CH
00DH
00EH
00FH
010H
011H
012H
013H
014H
015H
016H
017H
018H
019H
01AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
20H
04H
00H
00H
00H
00H
A_MID1
A_MID2
A_MID3
A_MID4
A_MID5
A_MID6
A_MID7
A_MID8
A_MID9
A_MID10
A_MID11
A_MID12
A_MID13
A_MID14
A_MID15
A_MID16
A_MID17
A_MID18
A_MID19
A_MIDC0
A_MIDC1
A_IF1
A_WUC
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
A_WUPAT0
A_WUPAT1
A_WUBCNT
A_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 01BH
Data Sheet
179
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
A_WURSSIBL1
Register Long Name
Offset Address Reset Value
RSSI Wake-Up Blocking Level Low Channel 1
Register
01CH
FFH
A_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
01DH
00H
A_WURSSITH2
A_WURSSIBL2
RSSI Wake-Up Threshold for Channel 2 Register 01EH
00H
FFH
RSSI Wake-Up Blocking Level Low Channel 2
Register
01FH
A_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
020H
00H
A_WURSSITH3
A_WURSSIBL3
RSSI Wake-Up Threshold for Channel 3 Register 021H
00H
FFH
RSSI Wake-Up Blocking Level Low Channel 3
Register
022H
A_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
023H
00H
A_SIGDETSAT
A_WULOT
Signal Detector Saturation Threshold Register
Wake-up on Level Observation Time Register
Synchronization Search Time-Out Register
SYNC Timeout Timer Register
024H
025H
026H
027H
028H
029H
02AH
02BH
02CH
02DH
02EH
02FH
030H
031H
032H
033H
034H
035H
036H
037H
038H
039H
03AH
03BH
03CH
03DH
10H
00H
87H
FFH
00H
00H
02H
00H
00H
00H
00H
00H
00H
42H
00H
2BH
03H
08H
40H
00H
07H
00H
00H
20H
07H
00H
A_SYSRCTO
A_TOTIM_SYNC
A_TOTIM_TSI
A_TOTIM_EOM
A_AFCLIMIT
A_AFCAGCD
A_AFCSFCFG
A_AFCK1CFG0
A_AFCK1CFG1
A_AFCK2CFG0
A_AFCK2CFG1
A_PMFUDSF
A_AGCSFCFG
A_AGCCFG0
A_AGCCFG1
A_AGCTHR
TSI Timeout Timer Register
EOM Timeout Timer Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
A_DIGRXC
Digital Receiver Configuration Register
RSSI Peak Detector Bit Position Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
A_PKBITPOS
A_ISUPFCSEL
A_PDECF
A_PDECSCFSK
A_PDECSCASK
A_MFC
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
A_SRC
Sampe Rate Converter NCO Tune
Data Sheet
180
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
A_EXTSLC
Register Long Name
Offset Address Reset Value
Externel Data Slicer Configuration
03EH
03FH
02H
00H
A_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
A_SIGDET1
Signal Detector Threshold Level Register -
Wakeup
040H
00H
A_SIGDETLO
A_SIGDETSEL
A_SIGDETCFG
A_NDTHRES
A_NDCONFIG
A_CDRP
Signal Detector Threshold Low Level Register
Signal Detector Range Selection Register
Signal Detector Configuration Register
FSK Noise Detector Threshold Register
FSK Noise Detector Configuration Register
041H
042H
043H
044H
045H
046H
00H
7FH
00H
00H
07H
E6H
Clock and Data Recovery P Configuration
Register
A_CDRI
Clock and Data Recovery Configuration Register 047H
65H
01H
A_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
048H
A_CDRTOLC
A_CDRTOLB
A_TVWIN
CDR DC Chip Tolerance Register
CDR DC Bit Tolerance Register
Timing Violation Window Register
Slicer Configuration Register
049H
04AH
04BH
04CH
04DH
04EH
04FH
050H
051H
052H
053H
054H
055H
056H
057H
058H
059H
0CH
1EH
28H
90H
80H
00H
00H
00H
00H
00H
00H
00H
05H
00H
00H
04H
93H
F3H
07H
09H
13H
F3H
07H
09H
A_SLCCFG
A_TSIMODE
A_TSILENA
TSI Detection Mode Register
TSI Length Register A
A_TSILENB
TSI Length Register B
A_TSIGAP
TSI Gap Length Register
A_TSIPTA0
TSI Pattern Data Reference A Register 0
TSI Pattern Data Reference A Register 1
TSI Pattern Data Reference B Register 0
TSI Pattern Data Reference B Register 1
End Of Message Control Register
EOM Data Length Limit Register
EOM Data Length Limit Parallel Mode Register
Channel Configuration Register
PLL MMD Integer Value Register Channel 1
A_TSIPTA1
A_TSIPTB0
A_TSIPTB1
A_EOMC
A_EOMDLEN
A_EOMDLENP
A_CHCFG
A_PLLINTC1
A_PLLFRAC0C1
A_PLLFRAC1C1
A_PLLFRAC2C1
A_PLLINTC2
A_PLLFRAC0C2
A_PLLFRAC1C2
A_PLLFRAC2C2
PLL Fractional Division Ratio Register 0 Channel 1 05AH
PLL Fractional Division Ratio Register 1 Channel 1 05BH
PLL Fractional Division Ratio Register 2 Channel 1 05CH
PLL MMD Integer Value Register Channel 2
05DH
PLL Fractional Division Ratio Register 0 Channel 2 05EH
PLL Fractional Division Ratio Register 1 Channel 2 05FH
PLL Fractional Division Ratio Register 2 Channel 2 060H
Data Sheet
181
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
A_PLLINTC3
A_PLLFRAC0C3
A_PLLFRAC1C3
A_PLLFRAC2C3
SFRPAGE
Register Long Name
Offset Address Reset Value
PLL MMD Integer Value Register Channel 3
061H
13H
F3H
07H
09H
00H
50H
12H
00H
FFH
FFH
0BH
00H
00H
07H
07H
04H
10H
00H
01H
00H
80H
80H
1EH
PLL Fractional Division Ratio Register 0 Channel 3 062H
PLL Fractional Division Ratio Register 1 Channel 3 063H
PLL Fractional Division Ratio Register 2 Channel 3 064H
Special Function Register Page Register
PP0 and PP1 Configuration Register
PP2 and PP3 Configuration Register
PPx Port Configuration Register
RX RUN Configuration Register 0
RX RUN Configuration Register 1
Clock Divider Register 0
080H
081H
082H
083H
084H
085H
086H
087H
088H
089H
08AH
08BH
08CH
08DH
08EH
08FH
090H
091H
092H
PPCFG0
PPCFG1
PPCFG2
RXRUNCFG0
RXRUNCFG1
CLKOUT0
CLKOUT1
Clock Divider Register 1
CLKOUT2
Clock Divider Register 2
RFC
RF Control Register
BPFCALCFG0
BPFCALCFG1
XTALCAL0
XTALCAL1
RSSIMONC
ADCINSEL
BPF Calibration Configuration Register 0
BPF Calibration Configuration Register 1
XTAL Coarse Calibration Register
XTAL Fine Calibration Register
RSSI Monitor Configuration Register
ADC Input Selection Register
RSSI Offset Register
RSSIOFFS
RSSISLOPE
CDRDRTHRP
RSSI Slope Register
CDR Data Rate Acceptance Positive Threshold
Register
CDRDRTHRN
CDR Data Rate Acceptance Negative Threshold 093H
Register
23H
IM0
Interrupt Mask Register 0
094H
095H
096H
097H
098H
099H
09AH
09BH
09CH
09DH
09EH
09FH
0A0H
00H
00H
01H
01H
00H
01H
01H
00H
01H
00H
01H
00H
01H
IM1
Interrupt Mask Register 1
SPMAP
Self Polling Mode Active Periods Register
Self Polling Mode Idle Periods Register
Self Polling Mode Control Register
SPMIP
SPMC
SPMRT
Self Polling Mode Reference Timer Register
Self Polling Mode Off Time Register 0
Self Polling Mode Off Time Register 1
Self Polling Mode On Time Config A Register 0
Self Polling Mode On Time Config A Register 1
Self Polling Mode On Time Config B Register 0
Self Polling Mode On Time Config B Register 1
Self Polling Mode On Time Config C Register 0
SPMOFFT0
SPMOFFT1
SPMONTA0
SPMONTA1
SPMONTB0
SPMONTB1
SPMONTC0
Data Sheet
182
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
SPMONTC1
SPMONTD0
SPMONTD1
EXTPCMD
CMC1
Register Long Name
Offset Address Reset Value
Self Polling Mode On Time Config C Register 1
Self Polling Mode On Time Config D Register 0
Self Polling Mode On Time Config D Register 1
External Processing Command Register
Chip Mode Control Register 1
0A1H
0A2H
0A3H
0A4H
0A5H
0A6H
0A7H
0A8H
0A9H
0AAH
00H
01H
00H
00H
04H
10H
00H
FFH
FFH
00H
CMC0
Chip Mode Control Register 0
RSSIPWU
IS0
Wakeup Peak Detector Readout Register
Interrupt Status Register 0
IS1
Interrupt Status Register 1
RFPLLACC
RF PLL Actual Channel and Configuration
Register
RSSIPRX
RSSIPPL
PLDLEN
ADCRESH
ADCRESL
VACRES
AFCOFFSET
AGCGAINR
SPIAT
RSSI Peak Detector Readout Register
RSSI Payload Peak Detector Readout Register
Payload Data Length Register
ADC Result High Byte Register
ADC Result Low Byte Register
VCO Autocalibration Result Readout Register
AFC Offset Read Register
AGC Gain Readout Register
SPI Address Tracer Register
SPI Data Tracer Register
0ABH
0ACH
0ADH
0AEH
0AFH
0B0H
0B1H
0B2H
0B3H
0B4H
0B5H
0B6H
0B7H
0B8H
0B9H
0BAH
0BBH
0BCH
0BDH
100H
101H
102H
103H
104H
105H
106H
107H
108H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
SPIDT
SPICHKSUM
SN0
SPI Checksum Register
Serial Number Register 0
SN1
Serial Number Register 1
SN2
Serial Number Register 2
SN3
Serial Number Register 3
RSSIRX
RSSIPMF
SPWR
RSSI Readout Register
RSSI Peak Memory Filter Readout Register
Signal Power Readout Register
Noise Power Readout Register
Message ID Register 0
NPWR
B_MID0
B_MID1
B_MID2
B_MID3
B_MID4
B_MID5
B_MID6
B_MID7
B_MID8
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Data Sheet
183
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
B_MID9
Register Long Name
Offset Address Reset Value
Message ID Register 9
109H
10AH
10BH
10CH
10DH
10EH
10FH
110H
111H
112H
113H
114H
115H
116H
117H
118H
119H
11AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
20H
04H
00H
00H
00H
00H
FFH
B_MID10
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
B_MID11
B_MID12
B_MID13
B_MID14
B_MID15
B_MID16
B_MID17
B_MID18
B_MID19
B_MIDC0
B_MIDC1
B_IF1
B_WUC
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
B_WUPAT0
B_WUPAT1
B_WUBCNT
B_WURSSITH1
B_WURSSIBL1
RSSI Wake-Up Threshold for Channel 1 Register 11BH
RSSI Wake-Up Blocking Level Low Channel 1
Register
11CH
B_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
11DH
00H
B_WURSSITH2
B_WURSSIBL2
RSSI Wake-Up Threshold for Channel 2 Register 11EH
00H
FFH
RSSI Wake-Up Blocking Level Low Channel 2
Register
11FH
B_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
120H
00H
B_WURSSITH3
B_WURSSIBL3
RSSI Wake-Up Threshold for Channel 3 Register 121H
00H
FFH
RSSI Wake-Up Blocking Level Low Channel 3
Register
122H
B_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
123H
00H
B_SIGDETSAT
B_WULOT
Signal Detector Saturation Threshold Register
Wake-Up on Level Observation Time Register
Synchronization Search Time-Out Register
SYNC Timeout Timer Register
124H
125H
126H
127H
128H
129H
12AH
10H
00H
87H
FFH
00H
00H
02H
B_SYSRCTO
B_TOTIM_SYNC
B_TOTIM_TSI
B_TOTIM_EOM
B_AFCLIMIT
TSI Timeout Timer Register
EOM Timeout Timer Register
AFC Limit Configuration Register
Data Sheet
184
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
B_AFCAGCD
B_AFCSFCFG
B_AFCK1CFG0
B_AFCK1CFG1
B_AFCK2CFG0
B_AFCK2CFG1
B_PMFUDSF
B_AGCSFCFG
B_AGCCFG0
B_AGCCFG1
B_AGCTHR
Register Long Name
Offset Address Reset Value
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
12BH
12CH
12DH
12EH
12FH
130H
131H
132H
133H
134H
135H
136H
137H
138H
139H
13AH
13BH
13CH
13DH
13EH
13FH
00H
00H
00H
00H
00H
00H
42H
00H
2BH
03H
08H
40H
00H
07H
00H
00H
20H
07H
00H
02H
00H
AGC Configuration Register 1
AGC Threshold Register
B_DIGRXC
Digital Receiver Configuration Register
RSSI Peak Detector Bit Position Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
B_PKBITPOS
B_ISUPFCSEL
B_PDECF
B_PDECSCFSK
B_PDECSCASK
B_MFC
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
B_SRC
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
B_EXTSLC
B_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
B_SIGDET1
Signal Detector Threshold Level Register -
Wakeup
140H
00H
B_SIGDETLO
B_SIGDETSEL
B_SIGDETCFG
B_NDTHRES
B_NDCONFIG
B_CDRP
Signal Detector Threshold Low Level Register
Signal Detector Range Selection Register
Signal Detector Configuration Register
FSK Noise Detector Threshold Register
FSK Noise Detector Configuration Register
141H
142H
143H
144H
145H
146H
00H
7FH
00H
00H
07H
E6H
Clock and Data Recovery P Configuration
Register
B_CDRI
Clock and Data Recovery Configuration Register 147H
65H
01H
B_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
148H
B_CDRTOLC
B_CDRTOLB
B_TVWIN
CDR DC Chip Tolerance Register
CDR DC Bit Tolerance Register
Timing Violation Window Register
Slicer Configuration Register
TSI Detection Mode Register
149H
14AH
14BH
14CH
14DH
0CH
1EH
28H
90H
80H
B_SLCCFG
B_TSIMODE
Data Sheet
185
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
B_TSILENA
B_TSILENB
B_TSIGAP
Register Long Name
Offset Address Reset Value
TSI Length Register A
14EH
14FH
150H
151H
152H
153H
154H
155H
156H
157H
158H
159H
00H
00H
00H
00H
00H
00H
00H
05H
00H
00H
04H
93H
F3H
07H
09H
13H
F3H
07H
09H
13H
F3H
07H
09H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
TSI Length Register B
TSI Gap Length Register
B_TSIPTA0
B_TSIPTA1
B_TSIPTB0
B_TSIPTB1
B_EOMC
TSI Pattern Data Reference A Register 0
TSI Pattern Data Reference A Register 1
TSI Pattern Data Reference B Register 0
TSI Pattern Data Reference B Register 1
End Of Message Control Register
EOM Data Length Limit Register
EOM Data Length Limit Parallel Mode Register
Channel Configuration Register
PLL MMD Integer Value Register Channel 1
B_EOMDLEN
B_EOMDLENP
B_CHCFG
B_PLLINTC1
B_PLLFRAC0C1
B_PLLFRAC1C1
B_PLLFRAC2C1
B_PLLINTC2
B_PLLFRAC0C2
B_PLLFRAC1C2
B_PLLFRAC2C2
B_PLLINTC3
B_PLLFRAC0C3
B_PLLFRAC1C3
B_PLLFRAC2C3
C_MID0
PLL Fractional Division Ratio Register 0 Channel 1 15AH
PLL Fractional Division Ratio Register 1 Channel 1 15BH
PLL Fractional Division Ratio Register 2 Channel 1 15CH
PLL MMD Integer Value Register Channel 2
15DH
PLL Fractional Division Ratio Register 0 Channel 2 15EH
PLL Fractional Division Ratio Register 1 Channel 2 15FH
PLL Fractional Division Ratio Register 2 Channel 2 160H
PLL MMD Integer Value Register Channel 3
161H
PLL Fractional Division Ratio Register 0 Channel 3 162H
PLL Fractional Division Ratio Register 1 Channel 3 163H
PLL Fractional Division Ratio Register 2 Channel 3 164H
Message ID Register 0
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
200H
201H
202H
203H
204H
205H
206H
207H
208H
209H
20AH
20BH
20CH
20DH
20EH
C_MID1
C_MID2
C_MID3
C_MID4
C_MID5
C_MID6
C_MID7
C_MID8
C_MID9
C_MID10
C_MID11
C_MID12
C_MID13
C_MID14
Data Sheet
186
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
C_MID15
Register Long Name
Offset Address Reset Value
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
20FH
210H
211H
212H
213H
214H
215H
216H
217H
218H
219H
21AH
00H
00H
00H
00H
00H
00H
00H
20H
04H
00H
00H
00H
00H
FFH
C_MID16
C_MID17
C_MID18
C_MID19
C_MIDC0
C_MIDC1
C_IF1
C_WUC
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
C_WUPAT0
C_WUPAT1
C_WUBCNT
C_WURSSITH1
C_WURSSIBL1
RSSI Wake-Up Threshold for Channel 1 Register 21BH
RSSI Wake-Up Blocking Level Low Channel 1
Register
21CH
C_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
21DH
00H
C_WURSSITH2
C_WURSSIBL2
RSSI Wake-Up Threshold for Channel 2 Register 21EH
00H
FFH
RSSI Wake-Up Blocking Level Low Channel 2
Register
21FH
C_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
220H
00H
C_WURSSITH3
C_WURSSIBL3
RSSI Wake-Up Threshold for Channel 3 Register 221H
00H
FFH
RSSI Wake-Up Blocking Level Low Channel 3
Register
222H
C_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
223H
00H
C_SIGDETSAT
C_WULOT
Signal Detector Saturation Threshold Register
Wake-Up on Level Observation Time Register
Synchronization Search Time-Out Register
SYNC Timeout Timer Register
224H
225H
226H
227H
228H
229H
22AH
22BH
22CH
22DH
22EH
22FH
230H
10H
00H
87H
FFH
00H
00H
02H
00H
00H
00H
00H
00H
00H
C_SYSRCTO
C_TOTIM_SYNC
C_TOTIM_TSI
C_TOTIM_EOM
C_AFCLIMIT
TSI Timeout Timer Register
EOM Timeout Timer Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
C_AFCAGCD
C_AFCSFCFG
C_AFCK1CFG0
C_AFCK1CFG1
C_AFCK2CFG0
C_AFCK2CFG1
Data Sheet
187
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
C_PMFUDSF
C_AGCSFCFG
C_AGCCFG0
C_AGCCFG1
C_AGCTHR
C_DIGRXC
Register Long Name
Offset Address Reset Value
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
231H
232H
233H
234H
235H
236H
237H
238H
239H
23AH
23BH
23CH
23DH
23EH
23FH
42H
00H
2BH
03H
08H
40H
00H
07H
00H
00H
20H
07H
00H
02H
00H
AGC Configuration Register 1
AGC Threshold Register
Digital Receiver Configuration Register
RSSI Peak Detector Bit Position Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
C_PKBITPOS
C_ISUPFCSEL
C_PDECF
C_PDECSCFSK
C_PDECSCASK
C_MFC
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
C_SRC
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
C_EXTSLC
C_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
C_SIGDET1
Signal Detector Threshold Level Register -
Wakeup
240H
00H
C_SIGDETLO
C_SIGDETSEL
C_SIGDETCFG
C_NDTHRES
C_NDCONFIG
C_CDRP
Signal Detector Threshold Low Level Register
Signal Detector Range Selection Register
Signal Detector Configuration Register
FSK Noise Detector Threshold Register
FSK Noise Detector Configuration Register
241H
242H
243H
244H
245H
246H
00H
7FH
00H
00H
07H
E6H
Clock and Data Recovery P Configuration
Register
C_CDRI
Clock and Data Recovery Configuration Register 247H
65H
01H
C_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
248H
C_CDRTOLC
C_CDRTOLB
C_TVWIN
CDR DC Chip Tolerance Register
CDR DC Bit Tolerance Register
Timing Violation Window Register
Slicer Configuration Register
249H
24AH
24BH
24CH
24DH
24EH
24FH
250H
251H
252H
253H
0CH
1EH
28H
90H
80H
00H
00H
00H
00H
00H
00H
C_SLCCFG
C_TSIMODE
C_TSILENA
C_TSILENB
C_TSIGAP
C_TSIPTA0
C_TSIPTA1
C_TSIPTB0
TSI Detection Mode Register
TSI Length Register A
TSI Length Register B
TSI Gap Length Register
TSI Pattern Data Reference A Register 0
TSI Pattern Data Reference A Register 1
TSI Pattern Data Reference B Register 0
Data Sheet
188
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
C_TSIPTB1
C_EOMC
Register Long Name
Offset Address Reset Value
TSI Pattern Data Reference B Register 1
End Of Message Control Register
EOM Data Length Limit Register
254H
255H
256H
257H
258H
259H
00H
05H
00H
00H
04H
93H
F3H
07H
09H
13H
F3H
07H
09H
13H
F3H
07H
09H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
C_EOMDLEN
C_EOMDLENP
C_CHCFG
EOM Data Length Limit Parallel Mode Register
Channel Configuration Register
C_PLLINTC1
C_PLLFRAC0C1
C_PLLFRAC1C1
C_PLLFRAC2C1
C_PLLINTC2
C_PLLFRAC0C2
C_PLLFRAC1C2
C_PLLFRAC2C2
C_PLLINTC3
C_PLLFRAC0C3
C_PLLFRAC1C3
C_PLLFRAC2C3
D_MID0
PLL MMD Integer Value Register Channel 1
PLL Fractional Division Ratio Register 0 Channel 1 25AH
PLL Fractional Division Ratio Register 1 Channel 1 25BH
PLL Fractional Division Ratio Register 2 Channel 1 25CH
PLL MMD Integer Value Register Channel 2
25DH
PLL Fractional Division Ratio Register 0 Channel 2 25EH
PLL Fractional Division Ratio Register 1 Channel 2 25FH
PLL Fractional Division Ratio Register 2 Channel 2 260H
PLL MMD Integer Value Register Channel 3
261H
PLL Fractional Division Ratio Register 0 Channel 3 262H
PLL Fractional Division Ratio Register 1 Channel 3 263H
PLL Fractional Division Ratio Register 2 Channel 3 264H
Message ID Register 0
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
300H
301H
302H
303H
304H
305H
306H
307H
308H
309H
30AH
30BH
30CH
30DH
30EH
30FH
310H
311H
312H
313H
314H
D_MID1
D_MID2
D_MID3
D_MID4
D_MID5
D_MID6
D_MID7
D_MID8
D_MID9
D_MID10
D_MID11
D_MID12
D_MID13
D_MID14
D_MID15
D_MID16
D_MID17
D_MID18
D_MID19
D_MIDC0
Data Sheet
189
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
D_MIDC1
Register Long Name
Offset Address Reset Value
Message ID Control Register 1
IF1 Register
315H
316H
317H
318H
319H
31AH
00H
20H
04H
00H
00H
00H
00H
FFH
D_IF1
D_WUC
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
D_WUPAT0
D_WUPAT1
D_WUBCNT
D_WURSSITH1
D_WURSSIBL1
RSSI Wake-Up Threshold for Channel 1 Register 31BH
RSSI Wake-Up Blocking Level Low Channel 1
Register
31CH
D_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
31DH
00H
D_WURSSITH2
D_WURSSIBL2
RSSI Wake-Up Threshold for Channel 2 Register 31EH
00H
FFH
RSSI Wake-Up Blocking Level Low Channel 2
Register
31FH
D_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
320H
00H
D_WURSSITH3
D_WURSSIBL3
RSSI Wake-Up Threshold for Channel 3 Register 321H
00H
FFH
RSSI Wake-Up Blocking Level Low Channel 3
Register
322H
D_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
323H
00H
D_SIGDETSAT
D_WULOT
Signal Detector Saturation Threshold Register
Wake-Up on Level Observation Time Register
Synchronization Search Time-Out Register
SYNC Timeout Timer Register
324H
325H
326H
327H
328H
329H
32AH
32BH
32CH
32DH
32EH
32FH
330H
331H
332H
333H
334H
335H
336H
10H
00H
87H
FFH
00H
00H
02H
00H
00H
00H
00H
00H
00H
42H
00H
2BH
03H
08H
40H
D_SYSRCTO
D_TOTIM_SYNC
D_TOTIM_TSI
D_TOTIM_EOM
D_AFCLIMIT
D_AFCAGCD
D_AFCSFCFG
D_AFCK1CFG0
D_AFCK1CFG1
D_AFCK2CFG0
D_AFCK2CFG1
D_PMFUDSF
D_AGCSFCFG
D_AGCCFG0
D_AGCCFG1
D_AGCTHR
TSI Timeout Timer Register
EOM Timeout Timer Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
D_DIGRXC
Digital Receiver Configuration Register
Data Sheet
190
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
D_PKBITPOS
D_ISUPFCSEL
D_PDECF
Register Long Name
Offset Address Reset Value
RSSI Peak Detector Bit Position Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
337H
338H
339H
33AH
33BH
33CH
33DH
33EH
33FH
00H
07H
00H
00H
20H
07H
00H
02H
00H
D_PDECSCFSK
D_PDECSCASK
D_MFC
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
D_SRC
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
D_EXTSLC
D_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
D_SIGDET1
Signal Detector Threshold Level Register -
Wakeup
340H
00H
D_SIGDETLO
D_SIGDETSEL
D_SIGDETCFG
D_NDTHRES
D_NDCONFIG
D_CDRP
Signal Detector Threshold Low Level Register
Signal Detector Range Selection Register
Signal Detector Configuration Register
FSK Noise Detector Threshold Register
FSK Noise Detector Configuration Register
341H
342H
343H
344H
345H
346H
00H
7FH
00H
00H
07H
E6H
Clock and Data Recovery P Configuration
Register
D_CDRI
Clock and Data Recovery Configuration Register 347H
65H
01H
D_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
348H
D_CDRTOLC
D_CDRTOLB
D_TVWIN
CDR DC Chip Tolerance Register
CDR DC Bit Tolerance Register
Timing Violation Window Register
Slicer Configuration Register
349H
34AH
34BH
34CH
34DH
34EH
34FH
350H
351H
352H
353H
354H
355H
356H
357H
358H
359H
0CH
1EH
28H
90H
80H
00H
00H
00H
00H
00H
00H
00H
05H
00H
00H
04H
93H
D_SLCCFG
D_TSIMODE
D_TSILENA
D_TSILENB
D_TSIGAP
TSI Detection Mode Register
TSI Length Register A
TSI Length Register B
TSI Gap Length Register
D_TSIPTA0
D_TSIPTA1
D_TSIPTB0
D_TSIPTB1
D_EOMC
TSI Pattern Data Reference A Register 0
TSI Pattern Data Reference A Register 1
TSI Pattern Data Reference B Register 0
TSI Pattern Data Reference B Register 1
End Of Message Control Register
EOM Data Length Limit Register
EOM Data Length Limit Parallel Mode Register
Channel Configuration Register
PLL MMD Integer Value Register Channel 1
D_EOMDLEN
D_EOMDLENP
D_CHCFG
D_PLLINTC1
Data Sheet
191
V4.0, 2010-02-19
TDA5240
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
D_PLLFRAC0C1
D_PLLFRAC1C1
D_PLLFRAC2C1
D_PLLINTC2
Register Long Name
Offset Address Reset Value
PLL Fractional Division Ratio Register 0 Channel 1 35AH
PLL Fractional Division Ratio Register 1 Channel 1 35BH
PLL Fractional Division Ratio Register 2 Channel 1 35CH
F3H
07H
09H
13H
F3H
07H
09H
13H
F3H
07H
09H
PLL MMD Integer Value Register Channel 2
35DH
D_PLLFRAC0C2
D_PLLFRAC1C2
D_PLLFRAC2C2
D_PLLINTC3
PLL Fractional Division Ratio Register 0 Channel 2 35EH
PLL Fractional Division Ratio Register 1 Channel 2 35FH
PLL Fractional Division Ratio Register 2 Channel 2 360H
PLL MMD Integer Value Register Channel 3
361H
D_PLLFRAC0C3
D_PLLFRAC1C3
D_PLLFRAC2C3
PLL Fractional Division Ratio Register 0 Channel 3 362H
PLL Fractional Division Ratio Register 1 Channel 3 363H
PLL Fractional Division Ratio Register 2 Channel 3 364H
Data Sheet
192
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Register Description
Message ID Register 0
A_MID0
Offset
000H
Reset Value
00H
Message ID Register 0
ꢀ
ꢁ
0,'ꢀ
Z
Field
Bits
Type
Description
MID0
7:0
w
Message ID Register 0
Reset: 00H
Message ID Register 1
A_MID1
Offset
001H
Reset Value
00H
Message ID Register 1
ꢀ
ꢁ
0,'ꢁ
Z
Field
Bits
Type
Description
MID1
7:0
w
Message ID Register 1
Reset: 00H
Message ID Register 2
A_MID2
Offset
002H
Reset Value
00H
Message ID Register 2
Data Sheet
193
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢁ
0,'ꢂ
Z
Field
Bits
Type
Description
MID2
7:0
w
Message ID Register 2
Reset: 00H
Message ID Register 3
A_MID3
Offset
003H
Reset Value
00H
Message ID Register 3
ꢀ
ꢁ
0,'ꢃ
Z
Field
Bits
Type
Description
MID3
7:0
w
Message ID Register 3
Reset: 00H
Message ID Register 4
A_MID4
Offset
004H
Reset Value
00H
Message ID Register 4
ꢀ
ꢁ
0,'ꢄ
Z
Field
Bits
Type
Description
MID4
7:0
w
Message ID Register 4
Reset: 00H
Message ID Register 5
Data Sheet
194
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
A_MID5
Offset
005H
Reset Value
00H
Message ID Register 5
ꢀ
ꢁ
0,'ꢅ
Z
Field
Bits
Type
Description
MID5
7:0
w
Message ID Register 5
Reset: 00H
Message ID Register 6
A_MID6
Offset
006H
Reset Value
00H
Message ID Register 6
ꢀ
ꢁ
0,'ꢆ
Z
Field
Bits
Type
Description
MID6
7:0
w
Message ID Register 6
Reset: 00H
Message ID Register 7
A_MID7
Offset
007H
Reset Value
00H
Message ID Register 7
ꢀ
ꢁ
0,'ꢇ
Z
Field
Bits
Type
Description
MID7
7:0
w
Message ID Register 7
Reset: 00H
Data Sheet
195
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Message ID Register 8
A_MID8
Offset
008H
Reset Value
00H
Message ID Register 8
ꢀ
ꢁ
0,'ꢈ
Z
Field
Bits
Type
Description
MID8
7:0
w
Message ID Register 8
Reset: 00H
Message ID Register 9
A_MID9
Offset
009H
Reset Value
00H
Message ID Register 9
ꢀ
ꢁ
0,'ꢉ
Z
Field
Bits
Type
Description
MID9
7:0
w
Message ID Register 9
Reset: 00H
Message ID Register 10
A_MID10
Offset
00AH
Reset Value
00H
Message ID Register 10
ꢀ
ꢁ
0,'ꢁꢀ
Z
Data Sheet
196
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
MID10
7:0
w
Message ID Register 10
Reset: 00H
Message ID Register 11
A_MID11
Offset
00BH
Reset Value
00H
Message ID Register 11
ꢀ
ꢁ
0,'ꢁꢁ
Z
Field
Bits
Type
Description
MID11
7:0
w
Message ID Register 11
Reset: 00H
Message ID Register 12
A_MID12
Offset
00CH
Reset Value
00H
Message ID Register 12
ꢀ
ꢁ
0,'ꢁꢂ
Z
Field
Bits
Type
Description
MID12
7:0
w
Message ID Register 12
Reset: 00H
Message ID Register 13
A_MID13
Offset
00DH
Reset Value
00H
Message ID Register 13
Data Sheet
197
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢁ
0,'ꢁꢃ
Z
Field
MID13
Bits
Type
Description
7:0
w
Message ID Register 13
Reset: 00H
Message ID Register 14
A_MID14
Offset
00EH
Reset Value
00H
Message ID Register 14
ꢀ
ꢁ
0,'ꢁꢄ
Z
Field
Bits
Type
Description
MID14
7:0
w
Message ID Register 14
Reset: 00H
Message ID Register 15
A_MID15
Offset
00FH
Reset Value
00H
Message ID Register 15
ꢀ
ꢁ
0,'ꢁꢅ
Z
Field
Bits
Type
Description
MID15
7:0
w
Message ID Register 15
Reset: 00H
Message ID Register 16
Data Sheet
198
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
A_MID16
Offset
010H
Reset Value
00H
Message ID Register 16
ꢀ
ꢁ
0,'ꢁꢆ
Z
Field
Bits
Type
Description
MID16
7:0
w
Message ID Register 16
Reset: 00H
Message ID Register 17
A_MID17
Offset
011H
Reset Value
00H
Message ID Register 17
ꢀ
ꢁ
0,'ꢁꢇ
Z
Field
Bits
Type
Description
MID17
7:0
w
Message ID Register 17
Reset: 00H
Message ID Register 18
A_MID18
Offset
012H
Reset Value
00H
Message ID Register 18
ꢀ
ꢁ
0,'ꢁꢈ
Z
Field
Bits
Type
Description
MID18
7:0
w
Message ID Register 18
Reset: 00H
Data Sheet
199
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Message ID Register 19
A_MID19
Offset
013H
Reset Value
00H
Message ID Register 19
ꢀ
ꢁ
0,'ꢁꢉ
Z
Field
Bits
Type
Description
MID19
7:0
w
Message ID Register 19
Reset: 00H
Message ID Control Register 0
A_MIDC0
Offset
014H
Reset Value
00H
Message ID Control Register 0
ꢀ
ꢃ
ꢁ
8186('
66326
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
SSPOS
6:0
w
Message ID Scan Start Position
Min: 00h = Comparision starts one Bit after FSYNC
Max: 7F = Comparision starts 128 Bits after FSYNC
Reset: 00H
Message ID Control Register 1
A_MIDC1
Offset
015H
Reset Value
00H
Message ID Control Register 1
Data Sheet
200
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢄ
ꢅ
0,'6(1
Z
ꢆ
0,'%2
Z
ꢇ
ꢁ
8186('
0,'176
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
MIDSEN
3
w
Enable Message ID Screening
0B
1B
Disabled
Enabled
Reset: 0H
MIDBO
2
w
w
Message ID Byte Organisation
0B
1B
2 Byte Mode
4 Byte Mode
Reset: 0H
MIDNTS
1:0
Message ID Number of Bytes To Scan (4 Byte Mode / 2 Byte Mode)
00B 1 Byte to scan / 1 Byte to scan
01B 2 Bytes to scan / 2 Bytes to scan
10B 3 Bytes to scan / 2 Bytes to scan
11B 4 Bytes to scan / 2 Bytes to scan
Reset: 0H
IF1 Register
A_IF1
Offset
016H
Reset Value
20H
IF1 Register
ꢀ
ꢃ
ꢈ
ꢅ
ꢆ
6'&6(/
Z
ꢇ
,)%8)(1
Z
ꢁ
&(5)6(/
Z
8186('
66%6(/
%3)%:6(/
ꢂ
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
SSBSEL
6
w
RXRF Receive Side Band Select
0B
1B
RF = LO + IF1 (Lo-side LO-injection)
RF = LO - IF1 (Hi-side LO-injection)
Reset: 0H
Data Sheet
201
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
BPFBWSEL
5:3
w
Band Pass Filter Bandwidth Selection
000B 50 kHz
001B 80 kHz
010B 125 kHz
011B 200 kHz
100B 300 kHz
101B not used
110B not used
111B not used
Reset: 4H
SDCSEL
IFBUFEN
CERFSEL
2
1
0
w
w
w
Single / Double Conversion Selection
0B
1B
Double Conversion (10.7 MHz/274 kHz)
Single Conversion (274 kHz)
Reset: 0H
IF Buffer Enable
0B
1B
Disabled
Enabled
Reset: 0H
Number of external Ceramic Filters
0B
1B
1 Ceramic Filter
2 Ceramic Filters
Reset: 0H
Wake-Up Control Register
A_WUC
Offset
017H
Reset Value
04H
Wake-Up Control Register
ꢀ
ꢃ
3:8(1
Z
ꢈ
ꢄ
ꢅ
ꢆ
ꢁ
:8/&8)) 8))%/&2
8186('
:8306(/
:8&57
%
2
ꢂ
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
PWUEN
6
w
Parallel Wake Up Mode Enable
This feature can only be used, when modulation type is the same for SPM
and RMSP
0B
1B
Disabled
Enabled
Reset: 0H
Data Sheet
202
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
WUPMSEL
5
w
Wake Up Pattern Mode Selection
0B
1B
Chip mode
Bit mode
Reset: 0H
WULCUFFB
UFFBLCOO
4
3
w
w
Select a "Wake Up on Level Criterion", when UFFBLCOO is enabled.
0B
1B
RSSI
automatically selected, when A_CHCFG.EXTPROC = "10"
Signal Recognition
Reset: 0H
Ultrafast Fall Back to SLEEP or additional Level criterion in
Constant On Off.
Enables additional parallel processing of "Level Criterion", when a "Data
Criterion" is selected in WUCRT.
In case of Fast Fall Back to SLEEP or Permanent Wake-Up Search, this
mode is called UFFB (Ultrafast Fall Back). Same Mode can be used in
Constant On-Off.
0B
1B
Disabled
Enabled
Reset: 0H
WUCRT
2:0
w
Select a "Wake Up Criterion"
000B Pattern Detection (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
001B Random Bits (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
010B Equal Bits (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
011B Wake Up on Symbol Sync, Valid Data Rate (Data Criterion); The
A_WUBCNT Register is
not used in this mode
100B RSSI (Level Criterion)
automatically selected, when A_CHCFG.EXTPROC = "10"
101B Signal Recognition (Level Criterion)
110B n.u.
111B n.u.
Reset: 4H
Wake-Up Pattern Register 0
A_WUPAT0
Offset
018H
Reset Value
00H
Wake-Up Pattern Register 0
ꢀ
ꢁ
:83$7ꢀ
Z
Data Sheet
203
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
WUPAT0
7:0
w
Wake Up Detection Pattern: Bit 7...Bit 0(LSB) (in Bits/Chips)
Reset: 00H
Wake-Up Pattern Register 1
A_WUPAT1
Offset
019H
Reset Value
00H
Wake-Up Pattern Register 1
ꢀ
ꢁ
:83$7ꢁ
Z
Field
Bits
Type
Description
WUPAT1
7:0
w
Wake Up Detection Pattern: (MSB) Bit 15...Bit 8 (in Bits/Chips)
Reset: 00H
Wake-Up Bit or Chip Count Register
A_WUBCNT
Offset
01AH
Reset Value
00H
Wake-Up Bit or Chip Count Register
ꢀ
ꢃ
ꢁ
8186('
:8%&17
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
Data Sheet
204
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
WUBCNT
6:0
w
Wake Up Bit/Chip Count Register (unit is bits; only exception is WU
Pattern Chip Mode, where unit is chips, see A_WUC.WUPMSEL)
Counter Register to define the maximum counts of bits/chips for Wake Up
detection.
Min: 00h = 0 Bits/Chips to count
In Random Bits or Equal Bits Mode this will cause a Wake Up
on Data Criterion immediately after Symbol Synchronization is found.
In Pattern Detection Mode this will cause no Wake Up on Data Criterion.
In this
Mode there is needed minimum 11h = 17 Bits/Chips to shift
one Pattern through the whole Pattern Detector. Because
comparision can only be started when at least the comparision
register is completely filled.
Max: 7Fh: 127 Bits/Chips to count after Symbol Sync found
Reset: 00H
RSSI Wake-Up Threshold for Channel 1 Register
A_WURSSITH1
Offset
01BH
Reset Value
00H
RSSI Wake-Up Threshold for Channel 1
Register
ꢀ
ꢁ
:8566,7+ꢁ
Z
Field
Bits
Type
Description
Wake Up on RSSI Threshold level for Channel 1
WURSSITH1 7:0
w
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00H
RSSI Wake-Up Blocking Level Low Channel 1 Register
A_WURSSIBL1
Offset
01CH
Reset Value
FFH
RSSI Wake-Up Blocking Level Low Channel 1
Register
Data Sheet
205
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢁ
:8566,%/ꢁ
Z
Field
WURSSIBL1
Bits
Type
Description
7:0
w
Wake Up on RSSI Blocking Level LOW for Channel 1
Reset: FFH
RSSI Wake-Up Blocking Level High Channel 1 Register
A_WURSSIBH1
Offset
01DH
Reset Value
00H
RSSI Wake-Up Blocking Level High Channel
1 Register
ꢀ
ꢁ
:8566,%+ꢁ
Z
Field
Bits
Type
Description
WURSSIBH1 7:0
w
Wake Up on RSSI Blocking Level HIGH for Channel 1, when RSSI is
selected as WU criterion or FFB criterion.
In case of Signal Recognition as WU criterion or FFB criterion, the
register defines the minimum consecutive T/16 samples of the Signal
Recognition output to be at high level for a positive wake up event
generation or FFB generation
Reset: 00H
RSSI Wake-Up Threshold for Channel 2 Register
A_WURSSITH2
Offset
01EH
Reset Value
00H
RSSI Wake-Up Threshold for Channel 2
Register
ꢀ
ꢁ
:8566,7+ꢂ
Z
Data Sheet
206
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
WURSSITH2 7:0
w
Wake Up on RSSI Threshold level for Channel 2
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00H
RSSI Wake-Up Blocking Level Low Channel 2 Register
A_WURSSIBL2
Offset
01FH
Reset Value
FFH
RSSI Wake-Up Blocking Level Low Channel 2
Register
ꢀ
ꢁ
:8566,%/ꢂ
Z
Field
Bits
Type
Description
WURSSIBL2
7:0
w
Wake Up on RSSI Blocking Level LOW for Channel 2
Reset: FFH
RSSI Wake-Up Blocking Level High Channel 2 Register
A_WURSSIBH2
Offset
020H
Reset Value
00H
RSSI Wake-Up Blocking Level High Channel
2 Register
ꢀ
ꢁ
:8566,%+ꢂ
Z
Field
Bits
Type
Description
WURSSIBH2 7:0
w
Wake Up on RSSI Blocking Level HIGH for Channel 2, when RSSI is
selected as WU criterion or FFB criterion.
In case of Signal Recognition as WU criterion or FFB criterion, the
register defines the minimum consecutive T/16 samples of the Signal
Recognition output to be at high level for a positive wake up event
generation or FFB generation
Reset: 00H
Data Sheet
207
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
RSSI Wake-Up Threshold for Channel 3 Register
A_WURSSITH3
Offset
021H
Reset Value
00H
RSSI Wake-Up Threshold for Channel 3
Register
ꢀ
ꢁ
:8566,7+ꢃ
Z
Field
Bits
Type
Description
Wake Up on RSSI Threshold level for Channel 3
WURSSITH3 7:0
w
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00H
RSSI Wake-Up Blocking Level Low Channel 3 Register
A_WURSSIBL3
Offset
022H
Reset Value
FFH
RSSI Wake-Up Blocking Level Low Channel 3
Register
ꢀ
ꢁ
:8566,%/ꢃ
Z
Field
Bits
Type
Description
WURSSIBL3
7:0
w
Wake Up on RSSI Blocking Level LOW for Channel 3
Reset: FFH
RSSI Wake-Up Blocking Level High Channel 3 Register
A_WURSSIBH3
Offset
023H
Reset Value
00H
RSSI Wake-Up Blocking Level High Channel
3 Register
Data Sheet
208
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢁ
:8566,%+ꢃ
Z
Field
Bits
Type
Description
WURSSIBH3 7:0
w
Wake Up on RSSI Blocking Level HIGH for Channel 3, when RSSI is
selected as WU criterion or FFB criterion.
In case of Signal Recognition as WU criterion or FFB criterion, the
register defines the minimum consecutive T/16 samples of the Signal
Recognition output to be at high level for a positive wake up event
generation or FFB generation
Reset: 00H
Signal Detector Saturation Threshold Register
A_SIGDETSAT
Offset
024H
Reset Value
10H
Signal Detector Saturation Threshold
Register
ꢀ
ꢁ
6,*'(76$7
Z
Field
Bits
Type
Description
SIGDETSAT
7:0
w
Saturation threshold of the Sigdet peak detector used for zero-tube
threshold calculation.
Reset: 10H
Wake-up on Level Observation Time Register
A_WULOT
Offset
025H
Reset Value
00H
Wake-up on Level Observation Time Register
ꢀ
ꢈ
ꢄ
ꢁ
:8/2736
:8/27
Z
Z
Data Sheet
209
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
WULOTPS
7:5
w
Wake-Up Level Observation Time PreScaler
000B
001B
4
8
010B 16
011B 32
100B 64
101B 128
110B 256
111B 512
Reset: 0H
WULOT
4:0
w
Wake-Up Level Observation Time
Min. 01h : Twulot = 1 * WULOTPS * 64 / Fsys
Max 1Fh : Twulot = 31 * WULOTPS * 64 / Fsys
Value 00h : Twulot = 32 * WULOTPS * 64 / Fsys
Reset: 00H
Synchronization Search Time-Out Register
A_SYSRCTO
Offset
026H
Reset Value
87H
Synchronization Search Time-Out Register
ꢀ
ꢁ
6<65&72
Z
Field
Bits
Type
Description
SYSRCTO
7:0
w
Synchronization search time out
FFh: 15 15/16 bit
00h: 0 bit
Reset: 87H
SYNC Timeout Timer Register
A_TOTIM_SYNC
Offset
027H
Reset Value
FFH
SYNC Timeout Timer Register
ꢀ
ꢁ
727,06<1&
Z
Data Sheet
210
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
TOTIMSYNC 7:0
w
Set value of Time-Out Timer (Symbol Synchronization)
Timer is used to get back from Run Mode Self Polling to the Self Polling
Mode whenever there is no Symbol Synchronization.
Timer is set back at new cycle start of Run Mode Self Polling.
TimeOut= (TOTIMSYNC * 64 * 512) / fsys
Min: 01h = (1 * 64 * 512)/ fsys
Max: FFh= (255 * 64 * 512) / fsys
00h: disabled
Reset: FFH
TSI Timeout Timer Register
A_TOTIM_TSI
Offset
028H
Reset Value
00H
TSI Timeout Timer Register
ꢀ
ꢁ
727,076,
Z
Field
Bits
Type
Description
Set value of Time-Out Timer (Telegram Start Identifier)
TOTIMTSI
7:0
w
Timer is used to get back from Run Mode Self Polling to the Self Polling
Mode whenever a Symbol Synchronisation is available but there is no TSI
detected.
Timer is set back at new cycle start of Run Mode Self Polling.
TimeOut= (TOTIMTSI * 64 * 512) / fsys
Min: 01h = (1 * 64 * 512)/ fsys
Max: FFh= (255 * 64 * 512) / fsys
00h: disabled
Reset: 00H
EOM Timeout Timer Register
A_TOTIM_EOM
Offset
029H
Reset Value
00H
EOM Timeout Timer Register
ꢀ
ꢁ
727,0(20
Z
Data Sheet
211
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
TOTIMEOM
7:0
w
Set value of Time-Out Timer (End of Message)
Timer is used to get back from Run Mode Self Polling to the Self Polling
Mode whenever a TSI has been detected but there is no EOM detected.
Timer is set back at new cycle start of Run Mode Self Polling.
TimeOut= (TOTIMEOM * 64 * 512 * 2) / fsys
Min: 01h = (1 * 64 * 512 * 2)/ fsys
Max: FFh= (255 * 64 * 512 * 2) / fsys
00h: disabled
Reset: 00H
AFC Limit Configuration Register
A_AFCLIMIT
Offset
02AH
Reset Value
02H
AFC Limit Configuration Register
ꢀ
ꢄ
ꢅ
ꢁ
8186('
$)&/,0,7
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCLIMIT
3:0
w
AFC Frequency Offset Saturation Limit ==> 1...15 x 21.4 kHz
Min: 1h = +/- Fsys / 2^(22-12) Hz
Max: Fh = +/- 15 * Fsys / 2^(22-12) Hz
Reg. value 0h = 0 Hz - no AFC correction
Reset: 2H
AFC/AGC Freeze Delay Register
A_AFCAGCD
Offset
02BH
Reset Value
00H
AFC/AGC Freeze Delay Register
ꢀ
ꢁ
$)&$*&'
Z
Data Sheet
212
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
AFCAGCD
7:0
w
AFC/AGC Freeze Delay Counter Division Ratio
The base period for the delay counter is the 8-16 samples/chip
(predecimation strobe) divided by 4
Reset: 00H
AFC Start/Freeze Configuration Register
A_AFCSFCFG
Offset
02CH
Reset Value
00H
AFC Start/Freeze Configuration Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢆ
ꢇ
ꢁ
$)&%/$6 $)&5(6$
8186('
$)&)5((=(
$)&67$57
.
7&&
ꢂ
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
AFCBLASK
6
w
AFC blocking during a low phase in the ASK signal
0B
1B
Disabled
Enabled
Reset: 0H
AFCRESATC
C
5
w
w
Enable AFC Restart at Channel Change and at the beginning of the
current configuration in Self Polling Mode
and at leaving the HOLD state (when bit CMC0.INITPLLHOLD is set) in
Run Mode Slave
0B
1B
Disabled
Enabled
Reset: 0H
AFCFREEZE 4:2
AFC Freeze Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
000B Stay ON
001B Freeze on RSSI Event + Delay (AFCAGCDEL)
010B Freeze on Signal Recognition Event + Delay (AFCAGCDEL)
011B Freeze on Symbol Synchronization + Delay (AFCAGCDEL)
100B SPI Command - write to EXTPCMD.AFCMANF bit
101B n.u.
110B n.u.
111B n.u.
Reset: 0H
Data Sheet
213
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
AFCSTART
1:0
w
AFC Start Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
00B OFF
01B Direct ON
10B Start on RSSI event
11B Start on Signal Recognition event
Reset: 0H
AFC Integrator 1 Gain Register 0
A_AFCK1CFG0
Offset
02DH
Reset Value
00H
AFC Integrator 1 Gain Register 0
ꢀ
ꢁ
$)&.ꢁBꢀ
Z
Field
Bits
Type
Description
AFCK1_0
7:0
w
AFC Filter coefficient K1, AFCK1(11:0) = AFCK1_1(MSB) &
AFCK1_0(LSB)
Reset: 00H
AFC Integrator 1 Gain Register 1
A_AFCK1CFG1
Offset
02EH
Reset Value
00H
AFC Integrator 1 Gain Register 1
ꢀ
ꢄ
ꢅ
ꢁ
8186('
$)&.ꢁBꢁ
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCK1_1
3:0
w
AFC Filter coefficient K1, AFCK1(11:0) = AFCK1_1(MSB) &
AFCK1_0(LSB)
Reset: 0H
Data Sheet
214
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
AFC Integrator 2 Gain Register 0
A_AFCK2CFG0
Offset
02FH
Reset Value
00H
AFC Integrator 2 Gain Register 0
ꢀ
ꢁ
$)&.ꢂBꢀ
Z
Field
Bits
Type
Description
AFCK2_0
7:0
w
AFC Filter coefficient K2, AFCK2(11:0) = AFCK2_1(MSB) &
AFCK2_0(LSB)
Reset: 00H
AFC Integrator 2 Gain Register 1
A_AFCK2CFG1
Offset
030H
Reset Value
00H
AFC Integrator 2 Gain Register 1
ꢀ
ꢄ
ꢅ
ꢁ
8186('
$)&.ꢂBꢁ
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCK2_1
3:0
w
AFC Filter coefficient K2, AFCK2(11:0) = AFCK2_1(MSB) &
AFCK2_0(LSB)
Reset: 0H
Peak Memory Filter Up-Down Factor Register
A_PMFUDSF
Offset
031H
Reset Value
42H
Peak Memory Filter Up-Down Factor Register
Data Sheet
215
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
8186('
30)83
8186('
30)'1
ꢂ
Z
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
PMFUP
6:4
w
Peak Memory Filter Attack (Up) Factor
000B 2^-1
001B 2^-2
010B 2^-3
011B 2^-4
100B 2^-5
101B 2^-6
110B 2^-7
111B 2^-8
Reset: 4H
UNUSED
PMFDN
3
-
UNUSED
Reset: 0H
2:0
w
Peak Memory Filter Decay (Down) Factor (additional to Attack
Factor)
000B 2^-2
001B 2^-3
010B 2^-4
011B 2^-5
100B 2^-6
101B 2^-7
110B 2^-8
111B 2^-9
Reset: 2H
AGC Start/Freeze Configuration Register
A_AGCSFCFG
Offset
032H
Reset Value
00H
AGC Start/Freeze Configuration Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢆ
ꢇ
ꢁ
$*&5(6$
7&&
8186('
$*&)5((=(
$*&67$57
ꢂ
Z
Z
Z
Data Sheet
216
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
AGCRESATC
C
5
w
Enable AGC Restart at Channel Change and at the beginning of the
current configuration in Self Polling Mode
and at leaving the HOLD state (when bit CMC0.INITPLLHOLD is set) in
Run Mode Slave
0B
1B
Disabled
Enabled
Reset: 0H
AGCFREEZE 4:2
w
AGC Freeze Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
000B Stay ON
001B Freeze on RSSI Event + Delay (AFCAGCDEL)
010B Freeze on Signal Recognition Event + Delay (AFCAGCDEL)
011B Freeze on Symbol Synchronization + Delay (AFCAGCDEL)
100B SPI Command - write to EXTPCMD.AGCMANF bit
101B n.u.
110B n.u.
111B n.u.
Reset: 0H
AGCSTART
1:0
w
AGC Start Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
00B OFF
01B Direct ON
10B Start on RSSI event
11B Start on Signal Recognition event
Reset: 0H
AGC Configuration Register 0
A_AGCCFG0
Offset
033H
Reset Value
2BH
AGC Configuration Register 0
ꢀ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
8186('
$*&'*&
$*&+<6
$*&*$,1
ꢂ
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
Data Sheet
217
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
AGCDGC
6:4
w
AGC Digital RSSI Gain Correction Tuning
000B 14.5 dB
001B 15.0 dB
010B 15.5 dB
011B 16.0 dB
100B 16.5 dB
101B 17.0 dB
110B 17.5 dB
111B 18.0 dB
Reset: 2H
AGCHYS
AGCGAIN
3:2
1:0
w
w
AGC Threshold Hysteresis
00B 12.8 dB
01B 17.1 dB
10B 21.3 dB
11B 25.6 dB
Reset: 2H
AGC Gain Control
00B 0 dB
01B -15 dB
10B -30 dB
11B Automatic
Reset: 3H
AGC Configuration Register 1
A_AGCCFG1
Offset
034H
Reset Value
03H
AGC Configuration Register 1
ꢀ
ꢆ
ꢇ
ꢁ
8186('
$*&7+2))6
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:2
-
UNUSED
Reset: 00H
AGCTHOFFS 1:0
w
AGC Threshold Offset
00B 25.5 dB
01B 38.3 dB
10B 51.1 dB
11B 63.9 dB
Reset: 3H
Data Sheet
218
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
AGC Threshold Register
A_AGCTHR
Offset
035H
Reset Value
08H
AGC Threshold Register
ꢀ
ꢄ
ꢅ
ꢁ
$*&783
$*&7/2
Z
Z
Field
Bits
Type
Description
AGCTUP
7:4
w
AGC Upper Attack Threshold [dB]
AGC Upper Threshold = A_AGCCFG1.AGCTHOFFS + 25.6 +
AGCTUP*1.6
Reset: 0H
AGCTLO
3:0
w
AGC Lower Attack Threshold [dB]
AGC Lower Threshold = A_AGCCFG1.AGCTHOFFS + AGCTLO*1.6
Reset: 8H
Digital Receiver Configuration Register
A_DIGRXC
Offset
036H
Reset Value
40H
Digital Receiver Configuration Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
',19(;7
Z
ꢇ
$$)%<3
Z
ꢁ
,1,7'5;
(6
,1,7)5&
6
&+,3',1
9
$$))&6(
/
&2'(
Z
Z
Z
Z
Z
Field
Bits
Type
Description
INITDRXES
7
w
Init the Digital Receiver at EOM or Loss of Symbol Sync (e.g. for
initialization of the Peak Memory Filter)
0B
1B
Disabled
Enabled
Reset: 0H
INITFRCS
6
w
Init the Framer at Cycle Start in RMSP.
If disabled, the WUP Data can be used as part of TSI as well in case the
modulation type is the same for SPM and RMSP
0B
1B
Disabled
Enabled
Reset: 1H
Data Sheet
219
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
CODE
5:4
w
Encoding Mode Selection
00B Manchester Code
01B Differential Manchester Code
10B Biphase Space
11B Biphase Mark
Reset: 0H
CHIPDINV
DINVEXT
3
2
w
w
Baseband Chip Data Inversion for CH_DATA and Decoder/Framer
input. Therefore Inverted Manchester and Inverted Differential
Manchester can be decoded internally.
0B
1B
Not inverted
Inverted
Reset: 0H
Data Inversion of signal DATA and DATA_MATCHFIL for External
Processing
0B
1B
Not inverted
Inverted
Reset: 0H
AAFBYP
1
0
w
w
Anti-Alliasing Filter Bypass for RSSI pin
0B
1B
Not bypassed
Bypassed
Reset: 0H
AAFFCSEL
Anti-Alliasing Filter Corner Frequency Select
0B
1B
40 kHz
80 kHz
Reset: 0H
RSSI Peak Detector Bit Position Register
A_PKBITPOS
Offset
037H
Reset Value
00H
RSSI Peak Detector Bit Position Register
ꢀ
ꢁ
566,'/<
Z
Field
Bits
Type
Description
RSSIDLY
7:0
w
RSSI Detector Start-up Delay for RSSIPPL register
Min: 00h: 0 bit delay (Start with first bit after FSYNC)
Max: FFh: 255 bit delay
Note: Due to filtering and signal computation, the latency T1 and T2 have
to be added
Reset: 00H
Data Sheet
220
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Image Supression Fc Selection Register
A_ISUPFCSEL
Offset
038H
Reset Value
07H
Image Supression Fc Selection Register
ꢀ
ꢄ
ꢅ
ꢆ
ꢁ
8186('
5HV
)&6(/
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
FCSEL
2:0
w
Image Supression Filter Corner Frequency Selection for FSK signal
path
000B 33 kHz
001B 46 kHz
010B 65 kHz
011B 93 kHz
100B 132 kHz
101B 190 kHz
110B 239 kHz
111B 282 kHz
Reset: 7H
Pre Decimation Factor Register
A_PDECF
Offset
039H
Reset Value
00H
Pre Decimation Factor Register
ꢀ
ꢃ
ꢁ
8186('
35('(&)
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
PREDECF
6:0
w
Predecimation Filter Decimation Factor
Predecimation Factor = PREDECF + 1
Reset: 00H
Data Sheet
221
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Pre Decimation Scaling Register FSK Mode
A_PDECSCFSK
Offset
03AH
Reset Value
00H
Pre Decimation Scaling Register FSK Mode
ꢀ
ꢃ
ꢈ
ꢄ
ꢁ
,1732/(
1)
5HV
3'6&$/()
Z
Z
Field
Bits
Type
Description
FSK Data Interpolation Enable
INTPOLENF
5
w
0B
1B
Disabled
Enabled
Reset: 0H
PDSCALEF
4:0
w
Predecimation Block Scaling Factor for FSK
Min 00h : 2^-10
Max 17h : 2^13
Reset: 00H
Pre Decimation Scaling Register ASK Mode
A_PDECSCASK
Offset
03BH
Reset Value
20H
Pre Decimation Scaling Register ASK Mode
ꢀ
ꢃ
ꢈ
ꢄ
ꢁ
,1732/(
1$
8186('
5HV
3'6&$/($
ꢂ
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
INTPOLENA
5
w
w
ASK Data Interpolation Enable
0B
1B
Disabled
Enabled
Reset: 1H
PDSCALEA
Data Sheet
4:0
Predecimation Block Scaling Factor for ASK
Min 00h : 2^-10
Max 17h : 2^13
Reset: 00H
222
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Matched Filter Control Register
A_MFC
Offset
03CH
Reset Value
07H
Matched Filter Control Register
ꢀ
ꢄ
ꢅ
ꢁ
8186('
0)/
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
MFL
3:0
w
Matched Filter Length
MF Length = MFL + 1
Reset: 7H
Sampe Rate Converter NCO Tune
A_SRC
Offset
03DH
Reset Value
00H
Sampe Rate Converter NCO Tune
ꢀ
ꢁ
65&1&2
Z
Field
Bits
Type
Description
SRCNCO
7:0
w
Sample Rate Converter NCO Tune
Min 00h : Fout = Fin
Max FFh : Fout = Fin / 2
Reset: 00H
Externel Data Slicer Configuration
A_EXTSLC
Offset
03EH
Reset Value
02H
Externel Data Slicer Configuration
Data Sheet
223
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢁ
8186('
5HV
(6/&6&$
(6/&%:
ꢂ
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
ESLCSCA
4:3
w
External Slicer BW Selection Scaling
00B 1/2
01B 1/4
10B 1/8
11B 1/16
Reset: 0H
ESLCBW
2:0
w
External Slicer Manual BW Selection
000B 1/8
001B 1/16
010B 1/24
011B 1/32
100B 1/40
101B 1/48
110B n.u.
111B n.u.
Reset: 2H
Signal Detector Threshold Level Register - Run Mode
A_SIGDET0
Offset
Reset Value
00H
Signal Detector Threshold Level Register -
Run Mode
03FH
ꢀ
ꢁ
6'7+5
Z
Field
Bits
Type
Description
SDTHR
7:0
w
Signal Detector Threshold Level for Run Mode
Reset: 00H
Signal Detector Threshold Level Register - Wakeup
Data Sheet
224
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
A_SIGDET1
Offset
040H
Reset Value
00H
Signal Detector Threshold Level Register -
Wakeup
ꢀ
ꢁ
6'7+5
Z
Field
Bits
Type
Description
SDTHR
7:0
w
Signal Detector Threshold Level for Wakeup
Reset: 00H
Signal Detector Threshold Low Level Register
A_SIGDETLO
Offset
041H
Reset Value
00H
Signal Detector Threshold Low Level
Register
ꢀ
ꢁ
6'/27+5
Z
Field
Bits
Type
Description
SDLOTHR
7:0
w
Signal Detector Threshold Low Level. This threshold level is
only valid, if the FSK Noise detector selection in the A_NDCONFIG
register is
set to 11b
Reset: 00H
Signal Detector Range Selection Register
A_SIGDETSEL
Offset
042H
Reset Value
7FH
Signal Detector Range Selection Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
5HV
6'56(/$6.
6'56(/)6.
6'/256(/
Z
Z
Z
Data Sheet
225
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
SDRSELASK 5:4
w
A_SIGDET0/1 range selection factor for ASK. The selected signal
detector value is multiplied by the 2^range selection factor. Use the
right setting to fit the measured SPWR value.
00B
01B
6
7
10B 7+6
11B
8
Reset: 3H
SDRSELFSK 3:2
w
A_SIGDET0/1 range selection factor for FSK. The selected signal
detector value is multiplied by the 2^range selection factor. Use the
right setting to fit the measured SPWR value.
00B
01B
10B
11B
2
4
6
8
Reset: 3H
SDLORSEL
1:0
w
SIGDETLO range selection factor. The selected signal detector
value is multiplied by the 2^range selection factor. Use the right
setting to fit the measured SPWR value.
00B
01B
10B
11B
2
4
6
8
Reset: 3H
Signal Detector Configuration Register
A_SIGDETCFG
Offset
043H
Reset Value
00H
Signal Detector Configuration Register
ꢀ
ꢄ
ꢅ
ꢆ
6'/25(
Z
ꢇ
6'&17ꢁ
Z
ꢁ
6'&17ꢀ
Z
8186('
5HV
ꢂ
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
SDLORE
2
w
Source selection of Signal Power Readout Register
0B
1B
Signal Power for A_SIGDET0/1
Signal for minimal usable FSK deviation, the sigdet low level can
be read out with SPWR register
Reset: 0H
Data Sheet
226
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
SDCNT1
1
w
Signal Detector Threshold Counter for Wakeup
0B
1B
Disabled
1/2 bit
Reset: 0H
SDCNT0
0
w
Signal Detector Threshold Counter for Run Mode
0B
1B
Disabled
1/2 bit
Reset: 0H
FSK Noise Detector Threshold Register
A_NDTHRES
Offset
044H
Reset Value
00H
FSK Noise Detector Threshold Register
ꢀ
ꢁ
1'7+5(6
Z
Field
Bits
Type
Description
NDTHRES
7:0
w
FSK Noise Detector Threshold
Reset: 00H
FSK Noise Detector Configuration Register
A_NDCONFIG
Offset
045H
Reset Value
07H
FSK Noise Detector Configuration Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
1'56(/
1'6(/
1'7/
1'3'65
Z
Z
Z
Z
Field
Bits
7:6
Type
Description
NDRSEL
w
FSK Noise Detector Range Selection
00B 2^7
01B 2^6
10B 2^5
11B 2^4
Reset: 0H
Data Sheet
227
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
NDSEL
5:4
w
Signal and Noise Detector Selection
00B Signal detection (=Squelch) only. This mode is recommended for
ASK.
01B Noise detection only
10B Signal and noise detection simultaneously
11B Signal and noise detection simultaneously, but the FSK noise
detect signal is valid only if the SIGDETLO threshold is exceeded.
This is the recommended mode for FSK.
Reset: 0H
NDTL
3:2
1:0
w
w
FSK Noise Detector Threshold Level
00B 1/2
01B 3/8
10B 1/4
11B 1/8
Reset: 1H
NDPDSR
FSK Noise Detector - Peak Detector Slew Rate
00B 1/256
01B 1/128
10B 1/64
11B 1/32
Reset: 3H
Clock and Data Recovery P Configuration Register
A_CDRP
Offset
046H
Reset Value
E6H
Clock and Data Recovery P Configuration
Register
ꢀ
ꢃ
ꢈ
3+'(1ꢁ
Z
ꢄ
3+'(1ꢀ
Z
ꢅ
ꢆ
ꢇ
ꢁ
3'65
39$/
36$7
Z
Z
Z
Field
Bits
7:6
Type
Description
PDSR
w
Peak-Detector slew rate. The slew rate of the Peak-Detector in the
clock-recovery path will be set with
PDSR. Actually, Peak-Detector part of Signal Detector Block
00B up/down = 1/64
01B up = 1/64; down = 1/128
10B up = 1/32; down = 1/128
11B up = 1/32; down = 1/256
Reset: 3H
Data Sheet
228
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
Phase detector error (PDE) outer tolerance range
PHDEN1
5
w
0B
1B
Disabled: PDEout = PDEin.
Enabled: If PDEin > abs(7/16) bit then PDEout = 0 else PDEout =
PDEin.
Reset: 1H
PHDEN0
PVAL
4
w
w
Phase detector error (PDE) inner tolerance range
0B
1B
Disabled: PDEout = PDEin.
Enabled: If PDEin < abs(1/16) bit then PDEout = 0 else PDEout =
PDEin.
Reset: 0H
3:2
P Value. The PVAL is the P value of the Clock-Recovery PI Loop-
Filter. The Phase-
Detector output error will be multiplied with the set value.
00B 1/1 phase detector error
01B 1/2 phase detector error
10B 1/4 phase detector error
11B 1/8 phase detector error
Reset: 1H
PSAT
1:0
w
P Value Saturation. The saturation of the P-Loop-Filter path will be
set according to the PSAT
value. Remark that the internal phase resolution of the phase detector is
1/16 bit.
00B saturation to 1/16 bit
01B saturation to 2/16 bit
10B saturation to 4/16 bit
11B saturation to 8/16 bit
Reset: 2H
Clock and Data Recovery Configuration Register
A_CDRI
Offset
047H
Reset Value
65H
Clock and Data Recovery Configuration
Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
&256$7
/)6$7
,9$/
,6$7
Z
Z
Z
Z
Data Sheet
229
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
CORSAT
7:6
w
Correlator output value (Timing extrapolation unit). The timing
extrapolation unit output value will be multiplied with the LFSAT
value. The timing extrapolation unit measures the data rate error during
the
RUNIN sequence and sets the I-Loop-Filter path when the RUNIN length
is
reached.
00B 1/4 calculated value
01B 1/8 calculated value
10B 1/16 calculated value
11B 1/32 calculated value
Reset: 1H
LFSAT
5:4
w
Loop Filter Saturation. The saturation of the I-Loop-Filter path will
be set according to the LFSAT
value.Remark that the internal phase resolution of the phase detector is
1/16 bit.
00B saturation to 1/32 bit
01B saturation to 1/16 bit
10B saturation to 2/16 bit
11B saturation to 4/16 bit
Reset: 2H
IVAL
3:2
w
I Value. The IVAL is the I value of the Clock-Recovery PI Loop-Filter.
The Phase-
Detector output error will be multiplied with this set value.
00B 1/32 phase detector error
01B 1/64 phase detector error
10B 1/128 phase detector error
11B 1/256 phase detector error
Reset: 1H
ISAT
1:0
w
I Value Saturation. The saturation of the I-Loop-Filter accumulator
will be set according to the
ISAT value. Remark that the internal phase resolution of the phase
detector is 1/16 bit.
00B saturation to 1/16 bit
01B saturation to 2/16 bit
10B saturation to 4/16 bit
11B saturation to 8/16 bit
Reset: 1H
Clock and Data Recovery RUNIN Configuration Register
A_CDRRI
Offset
048H
Reset Value
01H
Clock and Data Recovery RUNIN
Configuration Register
Data Sheet
230
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢅ
ꢆ
'5/,0(1
Z
ꢇ
ꢁ
8186('
581/(1
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
DRLIMEN
2
w
Enable data rate error acceptance limitation.
The limits are defined in CDRDRTHRP and CDRDRTHRN registers.
0B
1B
Disabled
Enabled
Reset: 0H
RUNLEN
1:0
w
RUNIN Length. The RUNIN length is equal to PLL-start-value
calculation time. This means
that the shorter RUNIN length decreases the data rate offset calculation
accuracy and symbol synchronization found signal generation stability.
Note that the RUNLEN have to be changed together with the TSI
configuration registers.
00B 8 chips
01B 7 chips
10B 6 chips
11B 5 chips
Reset: 1H
CDR DC Chip Tolerance Register
A_CDRTOLC
Offset
049H
Reset Value
0CH
CDR DC Chip Tolerance Register
ꢀ
ꢃ
ꢈ
ꢅ
ꢆ
ꢁ
8186('
72/&+,3+
72/&+,3/
ꢂ
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
TOLCHIPH
5:3
w
Duty Cycle Tolerance for Chip Border High Level. Represents the
number of 1/16 bit sample deviation from the ideal chip border
where an edge can occur in direction to the following chip border.
Reset: 1H
Data Sheet
231
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
TOLCHIPL
2:0
w
Duty Cycle Tolerance for Chip Border Low Level. Represents the
number of 1/16 bit sample deviation from the ideal chip border
where an edge can occur in direction to the previous chip border.
Reset: 4H
CDR DC Bit Tolerance Register
A_CDRTOLB
Offset
04AH
Reset Value
1EH
CDR DC Bit Tolerance Register
ꢀ
ꢃ
ꢈ
ꢅ
ꢆ
ꢁ
8186('
72/%,7+
72/%,7/
ꢂ
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
TOLBITH
5:3
w
Duty Cycle Tolerance for Bit Border High Level. Represents the
number of 1/16 bit sample deviation from the ideal bit border where
an edge can occur in direction to the following bit border.
Reset: 3H
TOLBITL
2:0
w
Duty Cycle Tolerance for Bit Border Low Level. Represents the
number of 1/16 bit sample deviation from the ideal bit border where
an edge can occur in direction to the previous bit border.
Reset: 6H
Timing Violation Window Register
A_TVWIN
Offset
04BH
Reset Value
28H
Timing Violation Window Register
ꢀ
ꢁ
79:,1
Z
Data Sheet
232
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
TVWIN
7:0
w
Timing Violation Window Length.
Defines the maximal number of 1/16 data samples without detected edge
which will be tolerated by CDR with no Loss of Symbol Synchronization
28h: 40/16 bit ((8 + 16 *CV + 8)*1.25)
FFh: 255/16 bit
Note: in TSIGAP mode the value must be higher.
Reset: 28H
Slicer Configuration Register
A_SLCCFG
Offset
04CH
Reset Value
90H
Slicer Configuration Register
ꢀ
ꢁ
6/&&)*
Z
Field
Bits
Type
Description
Data Slicer Configuration
SLCCFG
7:0
w
Value 90H : Chip Mode EOM-CV: For patterns with code violations in data
packet and optimized for activated EOM code violation criterion (and
optional EOM data length criterion)
Value 94H : Chip Mode EOM-Datalength: For patterns with code
violations in data packet and optimized for activated EOM data length
criterion only (EOMDATLEN)
Value 95H : Chip Mode Transparent: When Framer is not used, but
CH_DATA / CH_STR are used for data processing
Value 75H : Bit Mode: Only for patterns without Code Violations
Reset: 90H
TSI Detection Mode Register
A_TSIMODE
Offset
04DH
Reset Value
80H
TSI Detection Mode Register
ꢀ
ꢃ
ꢅ
ꢆ
&3+5$
Z
ꢇ
ꢁ
76,*56<
1
76,:&$
76,'(702'
Z
Z
Z
Data Sheet
233
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
TSI Gap Resync Mode (only for TSIDETMODE=2H)
TSIGRSYN
7
w
0B
Disabled - In this mode the GAPVAL and TSIGAP values are used,
so the overall GAP time can be
defined in T/16 steps.
1B
Enabled - PLL resync after TSI Gap
In this mode the T/2 GAP resolution can be set in the 5 MSB
TSIGAP register bits.
GAPVAL value is not used. Prefered in TSI Gap Mode.
Reset: 1H
TSIWCA
CPHRA
6:3
2
w
w
w
Wild Cards for 4 LSB chips of Correlator A
If all 4 chips are 0, the whole TSI pattern for Correlator A is valid
if a chip is 1, the corresponding chip from the TSI pattern is ignored
Reset: 0H
Code Phase Readjustment in Payload
0B
1B
disabled - code polarity is defined by the TSI pattern
enabled - code phase readjustment in payload
Reset: 0H
TSIDETMOD 1:0
TSI Detection Mode
00B 16 Bit TSI Mode - TSI configuration B AND A valid (sequentially),
B is valid if A_TSILENA=16 (=10H) and the A_TSILENB > 0
01B 8 Bit Parallel TSI Mode - TSI configurations A OR B (parallel)
10B 8 Bit TSI Gap Mode - TSI configurations A AND B with Gap
(sequentially with Gap between TSIA & TSIB)
11B 8 Bit Extended TSI Mode - TSI configurations A OR B (parallel with
matching information), dependent on found TSI A or B, 0 resp. 1 will
be sent as 1st received bit.
Reset: 0H
TSI Length Register A
A_TSILENA
Offset
04EH
Reset Value
00H
TSI Length Register A
ꢀ
ꢈ
ꢄ
ꢁ
8186('
76,/(1$
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
Data Sheet
234
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
TSILENA
4:0
w
TSI A Length (in chips):
(11H up to 1FH not used)
Min: 01 = 1 Chip; Be aware that such small values makes it
impossible to find the right phase of the pattern in the data stream and
therefore wrong data and code violations can be generated.
Max: 10h = 16 Chips = 8 Bit
Reset: 00H
TSI Length Register B
A_TSILENB
Offset
04FH
Reset Value
00H
TSI Length Register B
ꢀ
ꢈ
ꢄ
ꢁ
8186('
76,/(1%
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
TSILENB
4:0
w
TSI B Length (in chips):
(11H up to 1FH not used)
Min:
For 16 Bit TSI Mode:
Min: 00h = 0 Chip (see also A_TSILENA)
For all other TSI Modes:
Min: 01h = 1 Chip (see also A_TSILENA)
Max: 10h = 16 Chips = 8 Bit
Reset: 00H
TSI Gap Length Register
A_TSIGAP
Offset
050H
Reset Value
00H
TSI Gap Length Register
ꢀ
ꢅ
ꢆ
ꢁ
76,*$3
*$39$/
Z
Z
Data Sheet
235
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
TSIGAP
7:3
w
TSI Gap (T/2 bit resolution)
1Fh: 15 1/2 bit gap
00h: 0 bit gap
TSIGAP is used to lock the PLL after TSI A is found, if the TSI detection
mode 10b is selected.
Reset: 00H
GAPVAL
2:0
w
TSI Gap (T/16 bit resolution)
111b: 7/16 bit gap
000b: 0 bit gap
GAPVAL is used to correct the DCO phase after TSIGAP time, if
A_TSIMODE.TSIGRSYN is disabled
Reset: 0H
TSI Pattern Data Reference A Register 0
A_TSIPTA0
Offset
051H
Reset Value
00H
TSI Pattern Data Reference A Register 0
ꢀ
ꢁ
76,37$ꢀ
Z
Field
Bits
Type
Description
TSIPTA0
7:0
w
Data Pattern for TSI comparison: Bit 7...Bit 0(LSB) (in Chips)
Reset: 00H
TSI Pattern Data Reference A Register 1
A_TSIPTA1
Offset
052H
Reset Value
00H
TSI Pattern Data Reference A Register 1
ꢀ
ꢁ
76,37$ꢁ
Z
Field
Bits
Type
Description
TSIPTA1
7:0
w
Data Pattern for TSI comparison: Bit 15(MSB)...Bit 8 (in Chips)
Reset: 00H
Data Sheet
236
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
TSI Pattern Data Reference B Register 0
A_TSIPTB0
Offset
053H
Reset Value
00H
TSI Pattern Data Reference B Register 0
ꢀ
ꢁ
76,37%ꢀ
Z
Field
Bits
Type
Description
TSIPTB0
7:0
w
Data Pattern for TSI comparison: Bit 7...Bit 0(LSB) (in Chips)
Reset: 00H
TSI Pattern Data Reference B Register 1
A_TSIPTB1
Offset
054H
Reset Value
00H
TSI Pattern Data Reference B Register 1
ꢀ
ꢁ
76,37%ꢁ
Z
Field
Bits
Type
Description
TSIPTB1
7:0
w
Data Pattern for TSI comparison: Bit 15(MSB)...Bit 8 (in Chips)
Reset: 00H
End Of Message Control Register
A_EOMC
Offset
055H
Reset Value
05H
End Of Message Control Register
ꢀ
ꢄ
ꢅ
ꢆ
(206</2
Z
ꢇ
(20&9
Z
ꢁ
(20'$7/
(1
8186('
5HV
ꢂ
Z
Data Sheet
237
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
EOMSYLO
EOMCV
2
1
0
w
w
w
EOM by Sync Loss
0B
1B
Disabled
Enabled
Reset: 1H
EOM by Code Violation
0B
1B
Disabled
Enabled
Reset: 0H
EOMDATLEN
EOM by Data Length
0B
1B
Disabled
Enabled
Reset: 1H
EOM Data Length Limit Register
A_EOMDLEN
Offset
056H
Reset Value
00H
EOM Data Length Limit Register
ꢀ
ꢁ
'$7/(1
Z
Field
Bits
Type
Description
DATLEN
7:0
w
Length of Data Field in Telegram, only valid when EOM criterion is
EOMDATLEN
Counting of number of payload bits starts after the last TSI Bit. EOM will
be generated after the last payload bit.
In 8-bit extended TSI mode, the value must be the payload length + 1,
because of the additional bit inserted (matching information).
Min: 00h = 256 payload bits
Reg. value 01h = 1 payload bit
Max: FFh = 255 payload bits
Reset: 00H
EOM Data Length Limit Parallel Mode Register
Data Sheet
238
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
A_EOMDLENP
Offset
057H
Reset Value
00H
EOM Data Length Limit Parallel Mode
Register
ꢀ
ꢁ
'$7/(13
Z
Field
Bits
Type
Description
DATLENP
7:0
w
Length of Data Field in Telegram in Parallel Mode for TSI Pattern B,
only valid when EOM criterion is EOMDATLEN
Counting of number of payload bits starts after the last TSI Bit. EOM will
be generated after the last payload bit.
In 8-bit extended TSI mode, the value must be the payload length + 1,
because of the additional bit inserted (matching information).
Min: 00h = 256 payload bits
Reg. value 01h = 1 payload bit
Max: FFh = 255 payload bits
Reset: 00H
Channel Configuration Register
A_CHCFG
Offset
058H
Reset Value
04H
Channel Configuration Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
8186('
(;7352&
(20ꢂ630
12&
07
ꢂ
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
Data Sheet
239
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
EXTPROC
6:5
w
External Data Processing
00B No deactivation of functional blocks
01B Chip Data (RX Mode: TMCDS)
- no framing
- FSYNC, MID and EOM interrupts disabled
- only TOTIM_SYNC is active
- random, equal and pattern WU are disabled (mapped to sync)
10B Data + Data MF (RX Mode: TMMF, TMRDS)
- no framing
- FSYNC, MID and EOM interrupts disabled
- all TOTIMs are inactive
- only WU on RSSI (Level Criterion) possible
11B not used
Reset: 0H
EOM2SPM
4
w
w
Continue with Self Polling Mode after EOM detected in Run Mode
Self Polling
0B
Disabled - stay in Run Mode Self Polling (next Payload Frame is
expected)
1B
Enabled - leave Run Mode Self Polling after EOM
Reset: 0H
NOC
3:2
Number of Channels (Run Mode Slave / Self Polling Mode - Run
Mode Self Polling)
00B Channel 1 / Channel 1
01B Channel 1 / Channel 1
10B Channel 2 / Channel 1 + 2
11B Channel 3 / Channel 1 + 2 + 3
Reset: 1H
MT
1:0
w
Modulation Type (Run Mode Slave / Self Polling Mode - Run Mode
Self Polling)
00B ASK / ASK - ASK
01B FSK / FSK - FSK
10B ASK / FSK - ASK
11B FSK / ASK - FSK
Reset: 0H
PLL MMD Integer Value Register Channel 1
A_PLLINTC1
Offset
059H
Reset Value
93H
PLL MMD Integer Value Register Channel 1
ꢀ
ꢃ
ꢈ
ꢁ
%$1'6(/
3//,17&ꢁ
Z
Z
Data Sheet
240
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
BANDSEL
7:6
w
Frequency Band Selection
00B not used
01B 915MHz/868MHz
10B 434MHz
11B 315MHz
Reset: 2H
PLLINTC1
5:0
w
SDPLL Multi Modulus Divider Integer Offset value for Channel 1
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13H
PLL Fractional Division Ratio Register 0 Channel 1
A_PLLFRAC0C1
Offset
Reset Value
F3H
PLL Fractional Division Ratio Register 0
Channel 1
05AH
ꢀ
ꢁ
3//)5$&ꢀ&ꢁ
Z
Field
Bits
Type
Description
PLLFRAC0C1 7:0
w
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3H
PLL Fractional Division Ratio Register 1 Channel 1
A_PLLFRAC1C1
Offset
Reset Value
07H
PLL Fractional Division Ratio Register 1
Channel 1
05BH
ꢀ
ꢁ
3//)5$&ꢁ&ꢁ
Z
Data Sheet
241
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
PLLFRAC1C1 7:0
w
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07H
PLL Fractional Division Ratio Register 2 Channel 1
A_PLLFRAC2C1
Offset
05CH
Reset Value
09H
PLL Fractional Division Ratio Register 2
Channel 1
ꢀ
ꢃ
ꢈ
ꢄ
ꢁ
3//)&20
3&ꢁ
8186('
3//)5$&ꢂ&ꢁ
ꢂ
Z
Z
Field
UNUSED
Bits
7:6
Type
Description
-
UNUSED
Reset: 0H
PLLFCOMPC1 5
w
w
Fractional Spurii Compensation enable for Channel 1
0B
1B
Disabled
Enabled
Reset: 0H
PLLFRAC2C1 4:0
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09H
PLL MMD Integer Value Register Channel 2
A_PLLINTC2
Offset
05DH
Reset Value
13H
PLL MMD Integer Value Register Channel 2
ꢀ
ꢃ
ꢈ
ꢁ
8186('
3//,17&ꢂ
ꢂ
Z
Data Sheet
242
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
PLLINTC2
5:0
w
SDPLL Multi Modulus Divider Integer Offset value for Channel 2
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13H
PLL Fractional Division Ratio Register 0 Channel 2
A_PLLFRAC0C2
Offset
Reset Value
F3H
PLL Fractional Division Ratio Register 0
Channel 2
05EH
ꢀ
ꢁ
3//)5$&ꢀ&ꢂ
Z
Field
Bits
Type
Description
PLLFRAC0C2 7:0
w
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3H
PLL Fractional Division Ratio Register 1 Channel 2
A_PLLFRAC1C2
Offset
Reset Value
07H
PLL Fractional Division Ratio Register 1
Channel 2
05FH
ꢀ
ꢁ
3//)5$&ꢁ&ꢂ
Z
Field
Bits
Type
Description
PLLFRAC1C2 7:0
w
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07H
Data Sheet
243
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
PLL Fractional Division Ratio Register 2 Channel 2
A_PLLFRAC2C2
Offset
060H
Reset Value
09H
PLL Fractional Division Ratio Register 2
Channel 2
ꢀ
ꢃ
ꢈ
ꢄ
ꢁ
3//)&20
3&ꢂ
8186('
3//)5$&ꢂ&ꢂ
ꢂ
Z
Z
Field
UNUSED
Bits
7:6
Type
Description
-
UNUSED
Reset: 0H
PLLFCOMPC2 5
w
w
Fractional Spurii Compensation enable for Channel 2
0B
1B
Disabled
Enabled
Reset: 0H
PLLFRAC2C2 4:0
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09H
PLL MMD Integer Value Register Channel 3
A_PLLINTC3
Offset
061H
Reset Value
13H
PLL MMD Integer Value Register Channel 3
ꢀ
ꢃ
ꢈ
ꢁ
8186('
3//,17&ꢃ
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
PLLINTC3
5:0
w
SDPLL Multi Modulus Divider Integer Offset value for Channel 3
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13H
PLL Fractional Division Ratio Register 0 Channel 3
Data Sheet
244
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
A_PLLFRAC0C3
Offset
062H
Reset Value
F3H
PLL Fractional Division Ratio Register 0
Channel 3
ꢀ
ꢁ
3//)5$&ꢀ&ꢃ
Z
Field
Bits
Type
Description
PLLFRAC0C3 7:0
w
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3H
PLL Fractional Division Ratio Register 1 Channel 3
A_PLLFRAC1C3
Offset
Reset Value
07H
PLL Fractional Division Ratio Register 1
Channel 3
063H
ꢀ
ꢁ
3//)5$&ꢁ&ꢃ
Z
Field
Bits
Type
Description
PLLFRAC1C3 7:0
w
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07H
PLL Fractional Division Ratio Register 2 Channel 3
A_PLLFRAC2C3
Offset
Reset Value
09H
PLL Fractional Division Ratio Register 2
Channel 3
064H
Data Sheet
245
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢃ
ꢈ
ꢄ
ꢁ
3//)&20
3&ꢃ
8186('
3//)5$&ꢂ&ꢃ
ꢂ
Z
Z
Field
UNUSED
Bits
7:6
Type
Description
-
UNUSED
Reset: 0H
PLLFCOMPC3 5
w
w
Fractional Spurii Compensation enable for Channel 3
0B
1B
Disabled
Enabled
Reset: 0H
PLLFRAC2C3 4:0
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09H
Special Function Register Page Register
SFRPAGE
Offset
080H
Reset Value
00H
Special Function Register Page Register
ꢀ
ꢆ
ꢇ
ꢁ
8186('
6)53$*(
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:2
-
UNUSED
Reset: 00H
SFRPAGE
1:0
w
Selection of Register Page File (Configuration A..D) for SPI
communication
00B Page 0 (Config. A, start address: 000H)
01B Page 1 (Config. B, start address: 100H)
10B Page 2 (Config. C, start address: 200H)
11B Page 3 (Config. D, start address: 300H)
Reset: 0H
PP0 and PP1 Configuration Register
PPCFG0
Offset
081H
Reset Value
PP0 and PP1 Configuration Register
50H
Data Sheet
246
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢄ
ꢅ
ꢁ
33ꢁ&)*
33ꢀ&)*
Z
Z
Field
PP1CFG
Bits
Type
w
Description
7:4
Port Pin 1 Output Signal Selection
0000B CLK_OUT
0001B RX_RUN
0010B NINT
0011B LOW
0100B HIGH
0101B DATA
0110B DATA_MATCHFIL
0111B n.u.
1000B CH_DATA
1001B CH_STR
1010B RXD
1011B RXSTR
1100B n.u.
1101B n.u.
1110B n.u.
1111B n.u.
Reset: 5H
PP0CFG
3:0
w
Port Pin 0 Output Signal Selection
0000B CLK_OUT
0001B RX_RUN
0010B NINT
0011B LOW
0100B HIGH
0101B DATA
0110B DATA_MATCHFIL
0111B n.u.
1000B CH_DATA
1001B CH_STR
1010B RXD
1011B RXSTR
1100B n.u.
1101B n.u.
1110B n.u.
1111B n.u.
Reset: 0H
PP2 and PP3 Configuration Register
Data Sheet
247
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
PPCFG1
Offset
082H
Reset Value
12H
PP2 and PP3 Configuration Register
ꢀ
ꢄ
ꢅ
ꢁ
33ꢃ&)*
33ꢂ&)*
Z
Z
Field
Bits
Type
Description
PP3CFG
7:4
w
Port Pin 3 Output Signal Selection
0000B n.u.
0001B RX_RUN
0010B NINT
0011B LOW
0100B HIGH
0101B DATA
0110B DATA_MATCHFIL
0111B n.u.
1000B CH_DATA
1001B CH_STR
1010B RXD
1011B RXSTR
1100B n.u.
1101B n.u.
1110B n.u.
1111B n.u.
Reset: 1H
PP2CFG
3:0
w
Port Pin 2 Output Signal Selection
0000B CLK_OUT
0001B RX_RUN
0010B NINT
0011B LOW
0100B HIGH
0101B DATA
0110B DATA_MATCHFIL
0111B n.u.
1000B CH_DATA
1001B CH_STR
1010B RXD
1011B RXSTR
1100B n.u.
1101B n.u.
1110B n.u.
1111B n.u.
Reset: 2H
Data Sheet
248
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
PPx Port Configuration Register
PPCFG2
Offset
083H
Reset Value
00H
PPx Port Configuration Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
33ꢃ,19
Z
ꢆ
33ꢂ,19
Z
ꢇ
33ꢁ,19
Z
ꢁ
33ꢀ,19
Z
33ꢃ+33(
1
33ꢂ+33(
1
33ꢁ+33(
1
33ꢀ+33(
1
Z
Z
Z
Z
Field
Bits
Type
Description
PP3 High Power Pad Enable
PP3HPPEN
PP2HPPEN
PP1HPPEN
PP0HPPEN
PP3INV
7
w
0B
1B
Normal
High Power
Reset: 0H
6
5
4
3
2
1
0
w
w
w
w
w
w
w
PP2 High Power Pad Enable
0B
1B
Normal
High Power
Reset: 0H
PP1 High Power Pad Enable
0B
1B
Normal
High Power
Reset: 0H
PP0 High Power Pad Enable
0B
1B
Normal
High Power
Reset: 0H
PP3 Inversion Enable
0B
1B
Not Inverted
Inverted
Reset: 0H
PP2INV
PP2 Inversion Enable
0B
1B
Not Inverted
Inverted
Reset: 0H
PP1INV
PP1 Inversion Enable
0B
1B
Not Inverted
Inverted
Reset: 0H
PP0INV
PP0 Inversion Enable
0B
1B
Not Inverted
Inverted
Reset: 0H
Data Sheet
249
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
RX RUN Configuration Register 0
RXRUNCFG0
Offset
084H
Reset Value
FFH
RX RUN Configuration Register 0
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
5;58133 5;58133 5;58133 5;58133 5;58133 5;58133 5;58133 5;58133
ꢁ'
ꢁ&
ꢁ%
ꢁ$
ꢀ'
ꢀ&
ꢀ%
ꢀ$
Z
Z
Z
Z
Z
Z
Z
Z
Field
Bits
Type
Description
RXRUNPP1D
RXRUNPP1C
RXRUNPP1B
RXRUNPP1A
RXRUNPP0D
RXRUNPP0C
RXRUNPP0B
RXRUNPP0A
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
RXRUN Active Level on PP1 for Configuration D
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP1 for Configuration C
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP1 for Configuration B
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP1 for Configuration A
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP0 for Configuration D
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP0 for Configuration C
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP0 for Configuration B
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP0 for Configuration A
0B
1B
Active Low
Active High
Reset: 1H
Data Sheet
250
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
RX RUN Configuration Register 1
RXRUNCFG1
Offset
085H
Reset Value
FFH
RX RUN Configuration Register 1
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
5;58133 5;58133 5;58133 5;58133 5;58133 5;58133 5;58133 5;58133
ꢃ'
ꢃ&
ꢃ%
ꢃ$
ꢂ'
ꢂ&
ꢂ%
ꢂ$
Z
Z
Z
Z
Z
Z
Z
Z
Field
Bits
Type
Description
RXRUNPP3D
RXRUNPP3C
RXRUNPP3B
RXRUNPP3A
RXRUNPP2D
RXRUNPP2C
RXRUNPP2B
RXRUNPP2A
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
RXRUN Active Level on PP3 for Configuration D
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP3 for Configuration C
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP3 for Configuration B
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP3 for Configuration A
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP2 for Configuration D
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP2 for Configuration C
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP2 for Configuration B
0B
1B
Active Low
Active High
Reset: 1H
RXRUN Active Level on PP2 for Configuration A
0B
1B
Active Low
Active High
Reset: 1H
Data Sheet
251
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Clock Divider Register 0
CLKOUT0
Offset
086H
Reset Value
0BH
Clock Divider Register 0
ꢀ
ꢁ
&/.287ꢀ
Z
Field
Bits
Type
Description
CLKOUT0
7:0
w
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0BH
Clock Divider Register 1
CLKOUT1
Offset
087H
Reset Value
00H
Clock Divider Register 1
ꢀ
ꢁ
&/.287ꢁ
Z
Field
Bits
Type
Description
CLKOUT1
7:0
w
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 00H
Clock Divider Register 2
CLKOUT2
Offset
088H
Reset Value
00H
Clock Divider Register 2
Data Sheet
252
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢄ
ꢅ
ꢁ
8186('
&/.287ꢂ
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
CLKOUT2
3:0
w
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0H
RF Control Register
RFC
Offset
089H
Reset Value
07H
RF Control Register
ꢀ
ꢈ
ꢄ
5)2))
Z
ꢅ
ꢁ
8186('
,)$77
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
RFOFF
4
w
Switch off RF-path (for RSSI trimming)
0B
1B
RF path enabled
RF path disabled
Reset: 0H
Data Sheet
253
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
IFATT
3:0
w
Adjust IF attenuation from LNA_IN to IF_OUT (Double-Down
Conversion / Single-Down Conversion)
Used to trim out external component tolerances.
0000B 0 dB / n.u.
0001B 0.8 dB / n.u.
0010B 1.6 dB / n.u.
0011B 2.4 dB / n.u.
0100B 3.2 dB / 0 dB
0101B 4.0 dB / 0.8 dB
0110B 4.8 dB / 1.6 dB
0111B 5.6 dB / 2.4 dB
1000B 6.4 dB / 3.2 dB
1001B 7.2 dB / 4.0 dB
1010B 8.0 dB / 4.8 dB
1011B 8.8 dB / n.u.
1100B 9.6 dB / n.u.
1101B 10.4 dB / n.u.
1110B 11.2 dB / n.u.
1111B 12.0 dB / n.u.
Reset: 7H
BPF Calibration Configuration Register 0
BPFCALCFG0
Offset
08AH
Reset Value
07H
BPF Calibration Configuration Register 0
ꢀ
ꢈ
ꢄ
ꢅ
ꢁ
8186('
5HV
%3)&$/67
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
BPFCALST
3:0
w
BPF Calibration Time (use default = 07H)
Min: 0h= Txtal * 80 * 7 * (0 + 4)
Max: Fh= Txtal * 80 * 7 * (15 + 4)
Reset: 7H
BPF Calibration Configuration Register 1
BPFCALCFG1
Offset
08BH
Reset Value
04H
BPF Calibration Configuration Register 1
Data Sheet
254
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢃ
ꢈ
ꢁ
8186('
%3)&$/%:
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
BPFCALBW
5:0
w
Band Pass Filter Bandwidth Selection during Calibration
04H - 50 kHz (=default)
0DH - 80 kHz
16H - 125 kHz
1FH - 200 kHz
27H - 300 kHz
Reset: 04H
XTAL Coarse Calibration Register
XTALCAL0
Offset
08CH
Reset Value
10H
XTAL Coarse Calibration Register
ꢀ
ꢈ
ꢄ
ꢁ
8186('
;7$/6:&
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
XTALSWC
4:0
w
Xtal Trim Capacitor Value
Min 00h: 0pF
Value 01h: 1pF
Max 18h: 24pF
higher values than 18h are automatically mapped to 24pF
Reset: 10H
XTAL Fine Calibration Register
XTALCAL1
Offset
08DH
Reset Value
00H
XTAL Fine Calibration Register
Data Sheet
255
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
;7$/6:) ;7$/6:) ;7$/6:) ;7$/6:)
8186('
ꢃ
ꢂ
ꢁ
ꢀ
ꢂ
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
XTALSWF3
3
2
1
0
w
Connect 500 fF XTAL Trim capacitor
0B
1B
not connected
connected
Reset: 0H
XTALSWF2
XTALSWF1
XTALSWF0
w
w
w
Connect 250 fF XTAL Trim capacitor
0B
1B
not connected
connected
Reset: 0H
Connect 125 fF XTAL Trim capacitor
0B
1B
not connected
connected
Reset: 0H
Connect 62.5 fF XTAL Trim capacitor
0B
1B
not connected
connected
Reset: 0H
RSSI Monitor Configuration Register
RSSIMONC
Offset
08EH
Reset Value
01H
RSSI Monitor Configuration Register
ꢀ
ꢅ
ꢆ
ꢇ
ꢁ
566,021
(1
8186('
5HV
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
RSSIMONEN
0
w
Enable Buffer for RSSI pin
0B
1B
Disabled
Enabled
Reset: 1H
Data Sheet
256
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ADC Input Selection Register
ADCINSEL
Offset
08FH
Reset Value
00H
ADC Input Selection Register
ꢀ
ꢅ
ꢆ
ꢁ
8186('
$'&,16(/
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
ADCINSEL
2:0
w
ADC Input Selection
000B RSSI
001B Temperature
010B VDDD / 2
011B n.u.
100B n.u.
101B n.u.
110B n.u.
111B n.u.
Reset: 0H
RSSI Offset Register
RSSIOFFS
Offset
090H
Reset Value
80H
RSSI Offset Register
ꢀ
ꢁ
566,2))6
Z
Field
Bits
Type
Description
RSSIOFFS
7:0
w
RSSI Offset Compensation Value
Min: 00h= -256
Max: FFh= 254
Reset: 80H
RSSI Slope Register
Data Sheet
257
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
RSSISLOPE
Offset
091H
Reset Value
80H
RSSI Slope Register
ꢀ
ꢁ
566,6/23(
Z
Field
Bits
Type
Description
RSSISLOPE
7:0
w
RSSI Slope Compensation Value (Multiplication Value)
Multiplication Factor = RSSISLOPE * 2^-7
Min: 00h= 0.0
Max: FFh= 1.992
Reset: 80H
CDR Data Rate Acceptance Positive Threshold Register
CDRDRTHRP
Offset
092H
Reset Value
1EH
CDR Data Rate Acceptance Positive
Threshold Register
ꢀ
ꢁ
&'5'57+53
Z
Field
Bits
Type
Description
CDRDRTHRP 7:0
w
Data Rate Acceptance Positive Threshold Value
This feature can be turned on with *_CDRRI.DRLIMEN.
Higher the value, more percent of the datarate is tolerated.
Default => 10%
Reset: 1EH
CDR Data Rate Acceptance Negative Threshold Register
CDRDRTHRN
Offset
093H
Reset Value
23H
CDR Data Rate Acceptance Negative
Threshold Register
Data Sheet
258
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢁ
&'5'57+51
Z
Field
Bits
Type
Description
CDRDRTHRN 7:0
w
Data Rate Acceptance Negative Threshold Value
This feature can be turned on with *_CDRRI.DRLIMEN.
Higher the value, more percent of the datarate is tolerated.
Default => 10%
Reset: 23H
Interrupt Mask Register 0
IM0
Offset
094H
Reset Value
00H
Interrupt Mask Register 0
ꢀ
,0(20%
Z
ꢃ
,00,')%
Z
ꢈ
ꢄ
,0:8%
Z
ꢅ
,0(20$
Z
ꢆ
,00,')$
Z
ꢇ
ꢁ
,0:8$
Z
,0)6<1&
%
,0)6<1&
$
Z
Z
Field
Bits
Type
Description
Mask Interrupt on "End of Message" for Configuration B
IMEOMB
IMMIDFB
IMFSYNCB
IMWUB
7
w
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
6
5
4
3
w
w
w
w
Mask Interrupt on "Message ID Found" for Configuration B
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Mask Interrupt on "Frame Sync" for Configuration B
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Mask Interrupt on "Wake-up" for Configuration B
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
IMEOMA
Mask Interrupt on "End of Message" for Configuration A
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Data Sheet
259
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
Mask Interrupt on "Message ID Found" for Configuration A
IMMIDFA
2
w
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
IMFSYNCA
IMWUA
1
0
w
w
Mask Interrupt on "Frame Sync" for Configuration A
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Mask Interrupt on "Wake-up" for Configuration A
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Interrupt Mask Register 1
IM1
Offset
095H
Reset Value
00H
Interrupt Mask Register 1
ꢀ
,0(20'
Z
ꢃ
,00,')'
Z
ꢈ
ꢄ
,0:8'
Z
ꢅ
ꢆ
,00,')&
Z
ꢇ
ꢁ
,0:8&
Z
,0)6<1&
'
,0)6<1&
&
,0(20&
Z
Z
Z
Field
Bits
Type
Description
Mask Interrupt on "End of Message" for Configuration D
IMEOMD
IMMIDFD
IMFSYNCD
IMWUD
7
w
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
6
5
4
3
w
w
w
w
Mask Interrupt on "Message ID Found" for Configuration D
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Mask Interrupt on "Frame Sync" for Configuration D
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Mask Interrupt on "Wake-up" for Configuration D
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
IMEOMC
Mask Interrupt on "End of Message" for Configuration C
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Data Sheet
260
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
Mask Interrupt on "Message ID Found" for Configuration C
IMMIDFC
2
w
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
IMFSYNCC
IMWUC
1
0
w
w
Mask Interrupt on "Frame Sync" for Configuration C
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Mask Interrupt on "Wake-up" for Configuration C
0B
1B
Interrupt enabled
Interrupt disabled
Reset: 0H
Self Polling Mode Active Periods Register
SPMAP
Offset
096H
Reset Value
01H
Self Polling Mode Active Periods Register
ꢀ
ꢈ
ꢄ
ꢁ
8186('
630$3
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
SPMAP
4:0
w
Self Polling Mode Active Periods value
Min: 01h = 1 (Master) Period
Max: 1Fh = 31(Master) Periods
Reg. value 00h = 32 (Master) Periods
Reset: 01H
Self Polling Mode Idle Periods Register
SPMIP
Offset
097H
Reset Value
01H
Self Polling Mode Idle Periods Register
ꢀ
ꢁ
630,3
Z
Data Sheet
261
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
SPMIP
7:0
w
Self Polling Mode Idle Periods value
Min: 01h = 1 (Master) Period
Max: FFh = 255 (Master) Periods
Reg. value 00h = 256 (Master) Periods
Reset: 01H
Self Polling Mode Control Register
SPMC
Offset
098H
Reset Value
00H
Self Polling Mode Control Register
ꢀ
ꢅ
ꢆ
630$,(1
Z
ꢇ
ꢁ
8186('
6306(/
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
SPMAIEN
SPMSEL
2
w
Self Polling Mode Active Idle Enable
0B
1B
Disabled
Enabled
Reset: 0H
1:0
w
Self Polling Mode Selection
00B Constant On/Off (COO)
01B Fast Fall Back to Sleep (FFB)
10B Mixed Mode (MM, Combination of Const On/Off and Fast Fall Back
to Sleep for different Configurations: COO, FFB, FFB, FFB)
11B Permanent Wake Up Search (PWUS)
Reset: 0H
Self Polling Mode Reference Timer Register
SPMRT
Offset
099H
Reset Value
01H
Self Polling Mode Reference Timer Register
ꢀ
ꢁ
63057
Z
Data Sheet
262
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
SPMRT
7:0
w
Self Polling Mode Reference Timer value
The output of this timer is used as input for the On/Off Timer
Incoming Periodic Time = 64 / fsys
Output Periodic Time = TRT = (64 * SPMRT) / fsys
Min: 01h = (64*1) / fsys
Max: 00h = (64 * 256) / fsys
Reset: 01H
Self Polling Mode Off Time Register 0
SPMOFFT0
Offset
09AH
Reset Value
01H
Self Polling Mode Off Time Register 0
ꢀ
ꢁ
6302))7ꢀ
Z
Field
Bits
Type
Description
SPMOFFT0
7:0
w
Self Polling Mode Off Time value: SPMOFFT(13:0) =
SPMOFFT1(MSB) & SPMOFFT0(LSB)
Off -Time = TRT * SPMOFFT
Min: 0001h = 1 * TRT
Reg.Value 3FFFh = 16383 * TRT
Max: 0000h = 16384 * TRT
Reset: 01H
Self Polling Mode Off Time Register 1
SPMOFFT1
Offset
09BH
Reset Value
00H
Self Polling Mode Off Time Register 1
ꢀ
ꢃ
ꢈ
ꢁ
8186('
6302))7ꢁ
ꢂ
Z
Field
Bits
7:6
Type
Description
UNUSED
-
UNUSED
Reset: 0H
Data Sheet
263
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
SPMOFFT1
5:0
w
Self Polling Mode Off Time value: SPMOFFT(13:0) =
SPMOFFT1(MSB) & SPMOFFT0(LSB)
Off -Time = TRT * SPMOFFT
Min: 0001h = 1 * TRT
Reg.Value 3FFFh = 16383 * TRT
Max: 0000h = 16384 * TRT
Reset: 00H
Self Polling Mode On Time Config A Register 0
SPMONTA0
Offset
09CH
Reset Value
01H
Self Polling Mode On Time Config A Register
0
ꢀ
ꢁ
630217$ꢀ
Z
Field
Bits
Type
Description
SPMONTA0
7:0
w
Set Value Self Polling Mode On Time: SPMONTA(13:0) =
SPMONTA1(MSB) & SPMONTA0(LSB)
On-Time = TRT *SPMONTA
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config A Register 1
SPMONTA1
Offset
09DH
Reset Value
00H
Self Polling Mode On Time Config A Register
1
ꢀ
ꢃ
ꢈ
ꢁ
8186('
630217$ꢁ
ꢂ
Z
Data Sheet
264
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTA1
5:0
w
Set Value Self Polling Mode On Time: SPMONTA(13:0) =
SPMONTA1(MSB) & SPMONTA0(LSB)
On-Time = TRT *SPMONTA
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
Self Polling Mode On Time Config B Register 0
SPMONTB0
Offset
09EH
Reset Value
01H
Self Polling Mode On Time Config B Register
0
ꢀ
ꢁ
630217%ꢀ
Z
Field
Bits
Type
Description
SPMONTB0
7:0
w
Set Value Self Polling Mode On Time: SPMONTB(13:0) =
SPMONTB1(MSB) & SPMONTB0(LSB)
On-Time = TRT *SPMONTB
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config B Register 1
SPMONTB1
Offset
09FH
Reset Value
00H
Self Polling Mode On Time Config B Register
1
ꢀ
ꢃ
ꢈ
ꢁ
8186('
630217%ꢁ
ꢂ
Z
Data Sheet
265
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTB1
5:0
w
Set Value Self Polling Mode On Time: SPMONTB(13:0) =
SPMONTB1(MSB) & SPMONTB0(LSB)
On-Time = TRT *SPMONTB
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
Self Polling Mode On Time Config C Register 0
SPMONTC0
Offset
0A0H
Reset Value
01H
Self Polling Mode On Time Config C Register
0
ꢀ
ꢁ
630217&ꢀ
Z
Field
Bits
Type
Description
SPMONTC0
7:0
w
Set Value Self Polling Mode On Time: SPMONTC(13:0) =
SPMONTC1(MSB) & SPMONTC0(LSB)
On-Time = TRT *SPMONTC
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config C Register 1
SPMONTC1
Offset
0A1H
Reset Value
00H
Self Polling Mode On Time Config C Register
1
ꢀ
ꢃ
ꢈ
ꢁ
8186('
630217&ꢁ
ꢂ
Z
Data Sheet
266
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTC1
5:0
w
Set Value Self Polling Mode On Time: SPMONTC(13:0) =
SPMONTC1(MSB) & SPMONTC0(LSB)
On-Time = TRT *SPMONTC
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
Self Polling Mode On Time Config D Register 0
SPMONTD0
Offset
0A2H
Reset Value
01H
Self Polling Mode On Time Config D Register
0
ꢀ
ꢁ
630217'ꢀ
Z
Field
Bits
Type
Description
SPMONTD0
7:0
w
Set Value Self Polling Mode On Time: SPMONTD(13:0) =
SPMONTD1(MSB) & SPMONTD0(LSB)
On-Time = TRT *SPMONTD
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config D Register 1
SPMONTD1
Offset
0A3H
Reset Value
00H
Self Polling Mode On Time Config D Register
1
ꢀ
ꢃ
ꢈ
ꢁ
8186('
630217'ꢁ
ꢂ
Z
Data Sheet
267
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTD1
5:0
w
Set Value Self Polling Mode On Time: SPMONTD(13:0) =
SPMONTD1(MSB) & SPMONTD0(LSB)
On-Time = TRT *SPMONTD
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
External Processing Command Register
EXTPCMD
Offset
0A4H
Reset Value
00H
External Processing Command Register
ꢀ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
(;7(20
ZF
(;7727,
0
5HV
8186('
$*&0$1) $)&0$1)
ZF ZF
ꢂ
ZF
Field
Bits
Type
Description
UNUSED
6:4
-
UNUSED
Reset: 0H
AGCMANF
3
wc
AGC Manual Freeze
When *_AGCSFCFG.AGCFREEZE set to SPI Command, this bit sets the
AGC to freeze mode
0B
1B
Inactive
Active
Reset: 0H
AFCMANF
EXTTOTIM
2
1
wc
wc
AFC Manual Freeze
When *_AFCSFCFG.AFCFREEZE set to SPI Command, this bit sets the
AFC to freeze mode
0B
1B
Inactive
Active
Reset: 0H
Force TOTIM signal in external data processing mode
(*_CHCFG.EXTROC = 1H or 2H)
0B
1B
no external TOTIM signal forced
external TOTIM signal forced
Reset: 0H
Data Sheet
268
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
EXTEOM
0
wc
Force EOM signal in external data processing mode
(*_CHCFG.EXTROC = 1H or 2H)
0B
1B
no external EOM signal forced
external EOM signal forced
Reset: 0H
Chip Mode Control Register 1
CMC1
Offset
0A5H
Reset Value
04H
Chip Mode Control Register 1
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢇ
),)2/.
Z
ꢁ
(20ꢂ1&)
*
727,0ꢂ1
&+
,1,7),)
2
)6,1,7)
,)2
;7$/+30
6
8186('
ꢂ
Z
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
EOM2NCFG
5
w
Continue with next Configuration in Self Polling Mode after EOM
detected in Run Mode Self Polling
0B
1B
Continue with Configuration A in Self Polling Mode
Continue with next Configuration in Self Polling Mode
Reset: 0H
TOTIM2NCH
4
3
w
Continue with next RF channel in Self Polling Mode after TOTIM
detected in Run Mode Self Polling. In case of single RF channel
application this means "continue with next Configuration" instead
of "continue with next RF channel".
0B
1B
Continue with Configuration A in Self Polling Mode
Continue with next RF channel in Self Polling Mode
Reset: 0H
INITFIFO
w
Initialization of FIFO at Cycle Start
This Initialization of the FIFO can be configured in both Run Mode Slave
and Self Polling Mode. In Run Mode Slave this happens at the beginning.
In Self Polling Mode the initialization is done after Wake up found
(switching from Self Polling Mode to Run Mode Self Polling).
0B
1B
Initialization disabled
Initialization enabled
Reset: 0H
FSINITFIFO
Data Sheet
2
w
Initialization of FIFO at Frame Start
0B
1B
Initialization disabled
Initialization enabled
Reset: 1H
269
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
FIFOLK
1
w
Lock Data FIFO at EOM
0B
1B
FIFO lock is disabled
FIFO lock is enabled at EOM. This also locks the digital receive
chain at EOM until release from FIFO lock state.
Reset: 0H
XTALHPMS
0
w
XTAL High Precision Mode in Sleep Mode
0B
1B
Disabled
Enabled
Reset: 0H
Chip Mode Control Register 0
CMC0
Offset
0A6H
Reset Value
10H
Chip Mode Control Register 0
ꢀ
ꢃ
ꢈ
+2/'
Z
ꢄ
ꢅ
ꢆ
ꢇ
6/5;(1
Z
ꢁ
06(/
Z
6'2+33(
1
,1,73//
+2/'
&/.287(
1
0&6
Z
Z
Z
Z
Field
SDOHPPEN
Bits
Type
Description
7
w
SDO High Power Pad Enable
0B
1B
Normal
High Power
Reset: 0H
INITPLLHOLD 6
w
Init PLL after coming from HOLD (when new channel programmed).
This requires an additional Channel Hop Time before initialization of the
Digital Receiver.
0B
1B
No init of PLL
Init of PLL
Reset: 0H
HOLD
5
4
w
w
Holds the chip in the Register Configuration state (only in Run Mode
Slave)
0B
1B
Normal Operation
Jump into the Register Config state Hold
Reset: 0H
CLKOUTEN
CLK_OUT Enable
0B
1B
Disabled
Enable programmable clock output
Reset: 1H
Data Sheet
270
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
MCS
3:2
w
Multi Configuration Selection (Run Mode Slave / Self Polling Mode)
00B Config A / Config A
01B Config B / Config A + B
10B Config C / Config A + B + C
11B Config D / Config A + B + C + D
Reset: 0H
SLRXEN
MSEL
1
0
w
w
Slave Receiver Enable
This Bit is only used in Operating Mode Run Mode Slave / Sleep Mode
0B
1B
Receiver is in Sleep Mode
Receiver is in Run Mode Slave
Reset: 0H
Operating Mode Selection
0B
1B
Run Mode Slave / Sleep Mode
Self Polling Mode
Reset: 0H
Wakeup Peak Detector Readout Register
RSSIPWU
Offset
0A7H
Reset Value
00H
Wakeup Peak Detector Readout Register
ꢀ
ꢁ
566,3:8
U
Field
Bits
Type
Description
RSSIPWU
7:0
r
Peak Detector Level at Wakeup
Set at every WU event and also set at the end of every
configuration/channel cycle within a Self Polling period.
Cleared at Reset only.
Reset: 00H
Interrupt Status Register 0
IS0
Offset
0A8H
Reset Value
FFH
Interrupt Status Register 0
ꢀ
(20%
UF
ꢃ
0,')%
UF
ꢈ
ꢄ
:8%
UF
ꢅ
(20$
UF
ꢆ
0,')$
UF
ꢇ
)6<1&$
UF
ꢁ
:8$
UF
)6<1&%
UF
Data Sheet
271
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
EOMB
7
rc
Interrupt Request by "End of Message" from Configuration B (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
MIDFB
FSYNCB
WUB
6
5
4
3
2
1
0
rc
rc
rc
rc
rc
rc
rc
Interrupt Request by "Message ID Found" from Configuration B
(Reset event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Frame Sync" from Configuration B (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Wake Up" from Configuration B (Reset event
sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
EOMA
MIDFA
FSYNCA
WUA
Interrupt Request by "End of Message" from Configuration A (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Message ID Found" from Configuration A
(Reset event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Frame Sync" from Configuration A (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Wake Up" from Configuration A (Reset event
sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Status Register 1
Data Sheet
272
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
IS1
Offset
0A9H
Reset Value
FFH
Interrupt Status Register 1
ꢀ
(20'
UF
ꢃ
0,')'
UF
ꢈ
)6<1&'
UF
ꢄ
:8'
UF
ꢅ
(20&
UF
ꢆ
0,')&
UF
ꢇ
)6<1&&
UF
ꢁ
:8&
UF
Field
Bits
Type
Description
EOMD
MIDFD
FSYNCD
WUD
7
rc
Interrupt Request by "End of Message" from Configuration D (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
6
5
4
3
2
1
rc
rc
rc
rc
rc
rc
Interrupt Request by "Message ID Found" from Configuration D
(Reset event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Frame Sync" from Configuration D (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Wake Up" from Configuration D (Reset event
sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
EOMC
MIDFC
FSYNCC
Interrupt Request by "End of Message" from Configuration C (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Message ID Found" from Configuration C
(Reset event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Frame Sync" from Configuration C (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Data Sheet
273
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
WUC
0
rc
Interrupt Request by "Wake Up" from Configuration C (Reset event
sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
RF PLL Actual Channel and Configuration Register
RFPLLACC
Offset
0AAH
Reset Value
00H
RF PLL Actual Channel and Configuration
Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
3/'/(1
5063$&)*
5063$&
630$&
U
U
U
U
Field
Bits
Type
Description
PLDLEN
7:6
5:4
3:2
1:0
r
r
r
r
Payload Data Length stored at TSI detection of the next message,
PLDLEN(9:0) = RFPLLACC.PLDLEN(MSB) & PLDLEN(LSB).
Cleared with INIT FIFO
Min. 000h = 0 bits received
Max. 3FFh = 1023 bits received
Reset: 0H
RMSPACFG
RMSPAC
SPMAC
RF PLL Run Mode Self Polling Actual Configuration
00B Configuration A
01B Configuration B
10B Configuration C
11B Configuration D
Reset: 0H
RF PLL Run Mode Self Polling Actual Channel
00B No valid data in FIFO from any channel and configuration
01B Data in FIFO belong to Channel 1
10B Data in FIFO belong to Channel 2
11B Data in FIFO belong to Channel 3
Reset: 0H
RF PLL Self Polling Mode Actual Channel
00B No Wake Up from any Channel was actually found
01B Wake Up was found from Channel 1
10B Wake Up was found from Channel 2
11B Wake Up was found from Channel 3
Reset: 0H
Data Sheet
274
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
RSSI Peak Detector Readout Register
RSSIPRX
Offset
0ABH
Reset Value
00H
RSSI Peak Detector Readout Register
ꢀ
ꢁ
566,35;
UF
Field
Bits
Type
Description
RSSIPRX
7:0
rc
RSSI Peak Level during Receiving
Tracking is active when Digital Receiver is enabled
Set at higher peak levels than stored
Cleared at Reset and SPI read out
Reset: 00H
RSSI Payload Peak Detector Readout Register
RSSIPPL
Offset
0ACH
Reset Value
00H
RSSI Payload Peak Detector Readout
Register
ꢀ
ꢁ
566,33/
U
Field
Bits
Type
Description
RSSIPPL
7:0
r
RSSI Peak Level during Payload
Tracking starts after FSYNC + PKBITPOS
Set at every EOM
Cleared at the Reset only
Reset: 00H
Payload Data Length Register
PLDLEN
Offset
0ADH
Reset Value
00H
Payload Data Length Register
Data Sheet
275
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢁ
3/'/(1
U
Field
PLDLEN
Bits
Type
Description
7:0
r
Payload Data Length stored at TSI detection of the next message,
PLDLEN(9:0) = RFPLLACC.PLDLEN(MSB) & PLDLEN(LSB).
Cleared with INIT FIFO
Min. 000h = 0 bits received
Max. 3FFh = 1023 bits received
Reset: 00H
ADC Result High Byte Register
ADCRESH
Offset
0AEH
Reset Value
00H
ADC Result High Byte Register
ꢀ
ꢁ
$'&5(6+
UF
Field
Bits
Type
Description
ADCRESH
7:0
rc
ADC Result Value ADCRES(9:0) = ADCRESH(7:0) & ADCRESL(1:0)
Note: RC for control signal generation only, no clear
Reset: 00H
ADC Result Low Byte Register
ADCRESL
Offset
0AFH
Reset Value
00H
ADC Result Low Byte Register
ꢀ
ꢅ
ꢆ
ꢇ
ꢁ
8186('
$'&(2&
$'&5(6/
ꢂ
U
U
Data Sheet
276
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
ADCEOC
2
r
r
ADC End of Conversion detected
0B
1B
not detected
detected
Reset: 0H
ADCRESL
1:0
ADC Result Value ADCRES(9:0) = ADCRESH(7:0) & ADCRESL(1:0)
The 2 LSBs of the ADC result are captured when the SFR register
ADCRESH is readout.
Reset: 0H
VCO Autocalibration Result Readout Register
VACRES
Offset
0B0H
Reset Value
00H
VCO Autocalibration Result Readout
Register
ꢀ
ꢈ
ꢄ
ꢅ
ꢁ
8186('
5HV
9$&5(6
ꢂ
U
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
VACRES
3:0
r
VCO Autocalibration Result
Returns the VCO range selected by VCO Autocalibration
Reset: 0H
AFC Offset Read Register
AFCOFFSET
Offset
0B1H
Reset Value
00H
AFC Offset Read Register
ꢀ
ꢁ
$)&2))6
U
Data Sheet
277
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
AFCOFFS
7:0
r
Readout of the Frequency Offset found by AFC (AFC loop filter
output).
Value is in signed representation.
Frequency resolution is 2.68 kHz/digit
Output can be limited by x_AFCLIMIT register
Update rate is 548 kHz
Reset: 00H
AGC Gain Readout Register
AGCGAINR
Offset
0B2H
Reset Value
00H
AGC Gain Readout Register
ꢀ
ꢅ
ꢆ
ꢇ
ꢁ
0,;ꢂ*$,
1
8186('
,)ꢂ*$,1
ꢂ
U
U
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
IF2GAIN
2:1
r
AGC IF2 Gain Readout
00B 0 dB
01B -15 dB
10B -30 dB
11B n.u.
Reset: 0H
MIX2GAIN
0
r
AGC MIX2 Gain Readout
0B
1B
0 dB
-15 dB
Reset: 0H
SPI Address Tracer Register
SPIAT
Offset
0B3H
Reset Value
00H
SPI Address Tracer Register
Data Sheet
278
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢁ
63,$7
U
Field
SPIAT
Bits
Type
Description
7:0
r
SPI Address Tracer, Readout of the last address of a SFR Register
written by SPI
Reset: 00H
SPI Data Tracer Register
SPIDT
Offset
0B4H
Reset Value
00H
SPI Data Tracer Register
ꢀ
ꢁ
63,'7
U
Field
Bits
Type
Description
SPIDT
7:0
r
SPI Data Tracer, Readout of the last written data to a SFR Register
by SPI
Reset: 00H
SPI Checksum Register
SPICHKSUM
Offset
0B5H
Reset Value
00H
SPI Checksum Register
ꢀ
ꢁ
63,&+.680
UF
Field
Bits
Type
Description
SPICHKSUM 7:0
rc
SPI Checksum Readout
Reset: 00H
Data Sheet
279
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Serial Number Register 0
SN0
Offset
0B6H
Reset Value
00H
Serial Number Register 0
ꢀ
ꢁ
61ꢀ
U
Field
Bits
Type
Description
SN0
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
Serial Number Register 1
SN1
Offset
0B7H
Reset Value
00H
Serial Number Register 1
ꢀ
ꢁ
61ꢁ
U
Field
Bits
Type
Description
SN1
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
Serial Number Register 2
SN2
Offset
0B8H
Reset Value
00H
Serial Number Register 2
ꢀ
ꢁ
61ꢂ
U
Data Sheet
280
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
SN2
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
Serial Number Register 3
SN3
Offset
0B9H
Reset Value
00H
Serial Number Register 3
ꢀ
ꢁ
61ꢃ
U
Field
Bits
Type
Description
SN3
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
RSSI Readout Register
RSSIRX
Offset
0BAH
Reset Value
00H
RSSI Readout Register
ꢀ
ꢁ
566,5;
U
Field
Bits
Type
Description
RSSIRX
7:0
r
RSSI value after averaging over 4 samples
Reset: 00H
RSSI Peak Memory Filter Readout Register
RSSIPMF
Offset
0BBH
Reset Value
00H
RSSI Peak Memory Filter Readout Register
Data Sheet
281
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
ꢀ
ꢁ
566,30)
U
Field
RSSIPMF
Bits
Type
Description
7:0
r
RSSI Peak Memory Filter Level
Reset: 00H
Signal Power Readout Register
SPWR
Offset
0BCH
Reset Value
00H
Signal Power Readout Register
ꢀ
ꢁ
63:5
U
Field
Bits
Type
Description
SPWR
7:0
r
Signal Power
The register contains the actual signal power which should be used to
calculate the value of x_SIGDET0, x_SIGDET1 and x_SIGDETLO
registers
Reset: 00H
Noise Power Readout Register
NPWR
Offset
0BDH
Reset Value
00H
Noise Power Readout Register
ꢀ
ꢁ
13:5
U
Data Sheet
282
V4.0, 2010-02-19
TDA5240
Appendix
Register Description
Field
Bits
Type
Description
NPWR
7:0
r
FSK Noise Power
The register contains the actual noise power which should be used to
calculate the value for the x_NDTHRES register
Reset: 00H
Data Sheet
283
V4.0, 2010-02-19
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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