TDA38827 [INFINEON]

OptiMOS™ IPOL 25A 单输出高效降压稳压器;


型号：	TDA38827
厂家：	Infineon
描述：	OptiMOS™ IPOL 25A 单输出高效降压稳压器稳压器
文件：	总48页 (文件大小：2628K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA38827

TDAꢀꢁꢁꢂꢃ OptiMOS™ IPOL

25 A single-voltage synchronous Buck regulator

Features



Single 4.3 V to 17 V application or Wide Input Voltage Range from 2.0 V to 17 V with an External VCC

Precision Reference Voltage (0.6 V +/- 0.5%)

Enhanced Fast COT engine stable with Ceramic Output Capacitors and No External Compensation

Optional Forced Continuous Conduction Mode and Diode Emulation for Enhanced Light Load Efficiency

Programmable Switching Frequency from 600 kHz to 2 MHz

Monotonic Start-Up with Four Selectable Soft-Start Time & Enhanced Pre-Bias Start-Up

Thermally Compensated Internal Over Current Protection with Four Selectable Settings

Enable input with Voltage Monitoring Capability & Power Good Output

Thermal Shut Down

Operating Temp: -40 °C < T_j< 125 °C

Small Size: 6 mm x 5 mm PQFN

Halogen-free and RoHS2 Compliant with Exemption 7a

Potential applications



Server Applications

Storage Applications

Telecom & Datacom Applications

Distributed Point of Load Power Architectures

Product validation

Qualified for industrial applications according to the relevant tests of JEDEC47/20/22

Description

The TDA38827 is an easy-to-use, fully integrated dc - dc Buck regulator. The onboard PWM controller and

OptiMOS™ FETs with integrated bootstrap diode make TDA38827 a small footprint solution, providing high-

efficient power delivery. Furthermore, it uses a fast Constant On-Time (COT) control scheme, which simplifies the

design efforts and achieves fast control response.

The TDA38827 has an internal low dropout voltage regulator, allowing operations with a single supply. It can also

operate with an external bias supply, extending the operating input voltage (PVin) range.

The TDA38827 is a versatile regulator, offering programmable switching frequency from 600 kHz to 2 MHz, four

selectable current limits, four selectable soft-start time, Forced Continuous Conduction Mode (FCCM) and Diode

Emulation Mode (DEM) operation.

It also features important protection functions, such as pre-bias start-up, thermally compensated current limits,

over voltage and under voltage protection, and thermal shutdown to give required system level security in the

event of fault conditions.

Final Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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25 A single-voltage synchronous Buck regulator

Table of contents

Features ........................................................................................................................................ 1

Potential applications..................................................................................................................... 1

Product validation.......................................................................................................................... 1

Description .................................................................................................................................... 1

Table of contents............................................................................................................................ 2

Ordering information ............................................................................................................. 4

Functional block diagram........................................................................................................ 5

Typical application diagram .................................................................................................... 6

Pin descriptions ..................................................................................................................... 7

Absolute maximum ratings ..................................................................................................... 8

Thermal characteristics .......................................................................................................... 9

6.1

Thermal characteristics ..........................................................................................................................9

7.1

7.2

Electrical specifications .........................................................................................................10

Recommended operating conditions...................................................................................................10

Electrical characteristics.......................................................................................................................11

Typical efficiency and power loss curves..................................................................................14

PV_in= V_in= 12 V, F_sw= 600 kHz ................................................................................................................14

PV_in= V_in= 12 V, F_sw= 800 kHz ................................................................................................................15

PV_in= V_in= 12 V, F_sw= 1000 kHz...............................................................................................................16

PV_in= V_in= VCC = 5 V, F_sw= 600 kHz ........................................................................................................17

8.1

8.2

8.3

8.4

Thermal de-rating curves .......................................................................................................18

R_DS(ON)of MOSFET over temperature .........................................................................................19

Typical operating characteristics (-40 °C ≤ T_j≤ +125 °C)..............................................................20

Theory of operation...............................................................................................................23

Fast Constant On-Time control ............................................................................................................23

Enable ....................................................................................................................................................23

FCCM and DEM operation .....................................................................................................................24

Pseudo constant switching frequency .................................................................................................24

Soft-start................................................................................................................................................25

Pre-bias start-up....................................................................................................................................26

Internal Low – Dropout (LDO) regulator...............................................................................................26

Over Current Protection (OCP) .............................................................................................................27

Under Voltage Protection (UVP) ...........................................................................................................28

Over Voltage Protection (OVP)..............................................................................................................28

Over Temperature Protection (OTP) ....................................................................................................29

Power Good (Pgood) output.................................................................................................................29

Minimum on – time and minimum off – time.......................................................................................30

Selection of feedforward capacitor and feedback resistors................................................................30

Resistors for configuration pins............................................................................................................31

12.1

12.2

12.3

12.4

12.5

12.6

12.7

12.8

12.9

12.10

12.11

12.12

12.13

12.14

12.15

Design example.....................................................................................................................32

Enabling the TDA38827 .........................................................................................................................32

Programming the switching frequency and operation mode .............................................................32

Selecting input capacitors ....................................................................................................................32

Inductor selection .................................................................................................................................33

13.1

13.2

13.3

13.4

Final Datasheet

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25 A single-voltage synchronous Buck regulator

Table of contents

13.5

13.6

13.7

13.8

13.9

Output capacitor selection ...................................................................................................................33

Output voltage programming...............................................................................................................34

Feedforward capacitor..........................................................................................................................34

Bootstrap capacitor ..............................................................................................................................34

VIN and VCC/LDO bypass capacitor......................................................................................................34

14.1

14.2

Application information.........................................................................................................35

Application diagram..............................................................................................................................35

Typical operating waveforms ...............................................................................................................35

15.1

15.2

Layout recommendations ......................................................................................................38

Solder mask...........................................................................................................................................42

Stencil design ........................................................................................................................................43

Package ...............................................................................................................................44

Marking information .............................................................................................................................44

Dimensions............................................................................................................................................44

Tape and reel information ....................................................................................................................45

16.1

16.2

16.3

Environmental qualifications .................................................................................................46

Evaluation boards and support documentation ........................................................................47

Revision history.............................................................................................................................48

Final Datasheet

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25 A single-voltage synchronous Buck regulator

Ordering information

Ordering Information

Sales Product Name

TDA38827

Package Type

Standard Pack Form and Qty

Orderable Part Number

QFN 6 mm x 5 mm

Tape and Reel

5000

TDA38827AUMA1

TDA38827

Designator

Packing type

Tape & Reel

Dry

Moisture

protection packing

Packing size

330 mm

Halogen Free

RoHS compliant

Total lead free

Yes

PGND

PVIN

VCC/ LDO

BOOT

AGND

VIN

VSNS

Figure 1 Package Top View

Final Datasheet

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25 A single-voltage synchronous Buck regulator

Functional block diagram

VCC/LDO

AGND

PGood

Vin

AGND

POR

VREF

*70%

UVP OTP

OVP

VCC

LDO

Fault

AGND

LDrVin

BOOT

PVin

VREF

*120%

Hysteresis

=5%

Turn-on Delay

VSNS

Prebias

Fault

PGood

HDrVin

HDrv

Hysteresis

=5%

VREF

*90%

POR

VCC

4.0V

Hiccup

OVP

GATE

DRIVE

LOGIC

POR

VCC

OTP

Fault

1.2V

LDrVin

LDrv

PWM

COMP

SOFT

START

SS/Latch

ADAPTIVE

ON-TIME

GENERATOR

SET

PGND

Zero Cross

DETECTION

PGND

OCP

VREF

RAMP

GENERATOR

OVP

Latch Off

Floor

GENERATOR

Hiccup

UVP

AGND

Rt/MODE

ILIM

20ms

Delay

ILIM Ref

Figure 2 Block diagram

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25 A single-voltage synchronous Buck regulator

Typical application diagram

4.3V<Vin<17V

Enable

PVin

Vin

Boot

VCC/LDO

Cff

PGood

RFB1

RFB2

PGood

TDA38827

SS/Latch

Rt/MODE

ILIM

RFB1

RFB2

VSNS

AGnd

PGnd

Figure 3 TDA38827 basic application circuit

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25 A single-voltage synchronous Buck regulator

Pin descriptions

Note:

I = Input, O = Output

Pin#

Pin Name

I/O

Type

Pin Description

Output voltage feedback pin. Connect this pin to the output

of the regulator via a resistor divider to set the output voltage.

Multi-function pin. This pin sets the Soft-Start time to 1 of 4

options. This pin also selects latched-off Over Voltage

Protection (OVP) or non-latched OVP. Refer to Table 6.

Not connected internally. They can be left floating on PCB or

Analog

SS/Latch

Analog

Not

3, 16

connected connected to other signals as needed.

Signal ground for the internal circuitry except the internal

reference voltage. AGND and PGND are not internally

connected. AGND and PGND must be connected on PCB with a

single ground connection.

4, 17

AGND

Ground

Multi-function pin. This pin sets the switching frequency to 1

of 8 settings and sets the mode of operation to FCCM or DEM.

Refer to Table 5.

Connecting a resistor to ground sets the Over Current

Protection (OCP) limit. Four user selectable OCP limits are

available.

Power Good status output pin is open drain. Connect a pull up

resistor from this pin to VCC or to an external bias voltage, e.g.

3.3 V.

Sense pin for over voltage protection and Pgood. Tie this pin

to Vout using a resistor divider. Alternatively, tie this pin to FB

pin directly.

Rt/MODE

ILIM

Analog

PGood

VSNS

Input voltage for an Internal LDO. A 4.7 µF capacitor should be

connected between this pin and PGnd. If an external supply is

connected to VCC/LDO pin, this pin should be shorted to

VCC/LDO pin and a 10 µF ceramic capacitor can be shared

with Vin and VCC/LDO pin.

Input bias for an external VCC voltage or output of the internal

LDO. A 2.2 µF – 10 µF ceramic capacitor is recommended to

use between VCC, and the Power ground (PGND).

Power Ground. Should be connected to the system’s power

ground plane.

Vin

Power

VCC/LDO

I/O

PGND

Ground

Power

Analog

Switch Node. Connect these pins to an output inductor.

Input supply for the power stage.

Pvin

Boot

Supply voltage for the high side driver. Connect this pin to the

SW pin through a bootstrap capacitor.

Enable pin to turn the IC on and off.

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25 A single-voltage synchronous Buck regulator

Absolute maximum ratings

5 Absolute maximum ratings

Absolute maximum ratings

Description

Min

Max

Unit

Conditions

-0.3

Pvin, Vin, En to PGND

Note 1

-0.3 V(dc) ,

below -5 V for 5 ns

-0.3

25 V(dc),

above 32 V for 2 ns

Pvin to SW

VCC to PGND

Note 1

-0.3 V(dc),

below -0.3 V for 5 ns

-0.3 (dc),

Boot to PGND

25 V(dc),

above 32 V for 2 ns

6 V(dc),

SW to PGND

Boot to SW

Note 1

below -5 V for 5 ns

-0.3

7 V for 5 ns

ILIM, Fb, Pgood, Rt/MODE, VSNS

and SS/Latch to GND

PGnd to AGND

-0.3

Note 1

0.3

150

°C

Storage Temperature Range

Junction Temperature Range

-55

-40

Note:

1. PGND, and AGND pin are connected together

Attention:

Stresses beyond these listed under ꢀAbsolute Maximum Ratingsꢁ may cause permanent

damage to the device. These are stress ratings only and functional operation of the device at

these or any other conditions beyond those indicated in the operational sections of the

specifications are not implied.wing2865

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25 A single-voltage synchronous Buck regulator

Thermal characteristics

6.1

Thermal characteristics

Description

Symbol

Values

17 °C/W

3.5 °C/W

34 °C/W

Test Conditions

Note 2

Junction to Ambient Thermal Resistance

Junction to PCB Thermal Resistance

Junction to Case Top Thermal Resistance

θ_JA

θ_JC-PCB

θ_JC

Note 3

Note:

2. Thermal resistance is measured with components mounted on a standard EVAL_38827_1Vout demo board in

free air.

3. Thermal resistance is based on the board temperature near the Pvin pin.

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25 A single-voltage synchronous Buck regulator

Electrical specifications

7.1

Recommended operating conditions

Description

Min

Max

Unit

Note

Note 4, Note 5

Note 5, Note 6 & 10

Note 4, Note 7

Note 8, Note 9

Note 9

PV_inVoltage Range with External VCC

PV_inVoltage Range with Internal LDO

VCC Supply Voltage Range

4.5

4.3

0.6

5.5

Typical Output Voltage Range

Continuous Output Current Range

Typical Switching Frequency

600

-40

2000

125

kHz

°C

Note 10

Operating Junction Temperature

Note:

4. V_inis shorted to VCC and use an external bias voltage.

5. A common practice is to have 20% margin on the maximum SW node voltage in the design. For applications

requiring PV_inequal to or above 14 V, a small resistor in series with the Boot pin might be needed to ensure the

maximum SW node spike voltage does not exceed 20 V. Alternatively, a snubber can be used at the SW node to

reduce the SW node spike.

6. V_inis connected to PV_inand the internal LDO is used. For single-rail applications with the internal LDO, and PV_in

=V_in= 4.3 V-5.4 V, the internal LDO may enter dropout mode. OCP limits can be reduced due to the lower VCC

voltage. Please refer to Section 12.7 for more detailed design guidelines.

7. The TDA38827 is designed to function with VCC down to 4.2 V, however, electrical specifications such as OCP

limits may be degraded.

8. The maximum output voltage is also limited by the minimum off-time. Please refer to Section 12.13 for details.

Also note that OCP limit may be degraded when off-time is close to the minimum off-time.

9. Refer to Section 9 for maximum output current rating at different ambient temperatures.

10. The maximum LDO output current must be limited within 50 mA for operations requiring full operating

temperature range of -40 °C ꢀ T_Jꢀ 125 °C. Figure 6 shows the maximum LDO output current capability over

junction temperature. Thermal de-rating may be needed at an elevated ambient temperature to ensure the

junction temperature within the recommended operating range.

Final Datasheet

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25 A single-voltage synchronous Buck regulator

Electrical specifications

7.2

Electrical characteristics

Note:

Unless otherwise specified, the specifications apply over, 4.5 V ≤ Vin = Pvin ≤ ꢀ7 V, in ꢁ °C < T_J< 125

°C. Typical values are specified at Ta = 25 °C.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Power Stage

Top Switch

R_{ds(on)_Top}

R_{ds(on)_Bot}

V_Boot– V_sw= 5.0 V, I_O= 25 A, T_j=25 °C

VCC = 5.0 V, Io = 25 A, T_j=25 °C

I(Boot) = 25 mA

3.3

2.1

370

mΩ

Bottom Switch

Bootstrap Forward Voltage

600

300

En = 0 V

SW float voltage

V_SW

En = high, No Switching

SW node falling edge, Io = 25 A,

Internal LDO, T_j= 25 °C, Note 11

Dead Band Time

T_db

SW node rising edge, Io = 25 A,

Internal LDO, T_j= 25 °C, Note 11

Supply Current

Vin Supply Current (standby)

Vin Supply Current (static)

I_in(Standby)

I_in(Static)

En = Low, No Switching

En=2 V, No Switching

µA

2.3

Soft Start

SS/Latch = 0 kΩ, 4.53 kΩ, 10.5 kΩ,

18.7 kΩ;

0.4

0.2

0.1

0.6

0.3

0.84

0.42

0.21

SS/Latch = 1.5 kΩ, 5.76 kΩ, 12.1 kΩ,

21.5 kΩ;

Soft Start Ramp Rate

SS rate

SS/Latch = 2.49 kΩ, 7.32 kΩ, 14 kΩ,

24.9 kΩ;

mV/s

0.15

SS/Latch = 3.48 kΩ, 8.87 kΩ, ꢀꢁ.ꢂ

kΩ, 28.7 kΩ;

0.05 0.075

0.105

0.21

SS/Latch = Floating, or VCC

0.1

0.15

Feedback Voltage

V_FB

0.6

-0.5

+0.5

0°C < T_j< 85 °C

Accuracy

-40 °C < T_j< 125 °C, Note 12

V_FB=0.6 V, T_j=25 C

-1

V_FBInput Current

IV_FB

-0.15

+0.15

A

On-Time Timer Control

Vin=12 V, Vo=1 V, Rt= ꢃ kΩ, 10.5 kΩ,

Note 13

Vin=12 V, Vo=1 V, Rt= 1.5 kΩ, 12.1

kΩ, Note 13

152

114

On Time

T_on

Vin=12 V, Vo=1 V, Rt= 2.49 kΩ, 14 kΩ,

Note 13;

Vin=12 V, Vo=1 V, Rt= 3.48 kΩ, 16.2

kΩ, Note 13

91.5

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25 A single-voltage synchronous Buck regulator

Electrical specifications

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Vin=12 V, Vo=1 V, Rt= ꢄ.ꢅꢆ kΩ, 18.7

kΩ, Note 13

66.5

Vin=12 V, Vo=1 V, Rt= 5.76 kΩ, 21.5

kΩ, Note 13

Vin=12 V, Vo=1 V, Rt= 7.32 kΩ, 24.9

kΩ, Note 13

58.5

Vin=12V , Vo=1 V, Rt= 8.87 kΩ, ꢂꢇ.ꢈ

kΩ, Note 13

Vin=12V, Vo=1 V, Rt = Floating,

Note 13

114

Minimum On-Time

Minimum Off-Time

VCC LDO Output

T_{on (Min)}

T_{off (Min)}

Vin=12 V, Vo=0 V

T_j=25 C, V_FB=0 V

270

360

5.5 V ꢉ Vin ꢉ 17 V, when Icc =50 mA,

Output Voltage

VCC

4.7

5.0

5.3

Cload = 2.2 µF

VCC Dropout

VCC_drop Vin = 4.3 V, Icc=50 mA, Cload=2.2 µF

300

Short Circuit Current

I_short

5.5 V ꢉ Vin ꢉ 17 V

Under Voltage Lockout

VCC-Start Threshold

VCC-Stop Threshold

Enable-Start-Threshold

Enable-Stop-Threshold

Input Impedance

Vcc_UVLO_Start

Vcc_UVLO_Stop

En_UVLO_Start

En_UVLO_Stop

VCC Rising Trip Level

VCC Falling Trip Level

ramping up

3.8

3.6

4.0

3.8

1.2

4.2

4.0

1.14

0.9

1.36

1.06

1500

ramping down

500

1000

R_EN

k

Over Current Limit

Tj = 25 °C, Int LDO, RILIM=24.9 kΩ

28.4

32.8

35.3

Or RILIM = VCC, Floating

Tj = 25 °C, Int LDO, RILIM=21.5 kΩ

Tj = 25 °C, Int LDO, RILIM=16.2 kΩ

23.6

18.9

13.9

27.3

21.8

16.4

29.4

23.5

17.6

Current Limit Threshold

(Valley current)

Ioc

Tj = 25 °C, Int LDO, RILIM=ꢀꢂ.ꢀ kΩ

Or RILIM = GND

Over Voltage Protection

VSNS Rising

115

110

121

115

125

120

OVP Trip Threshold

OVP_Vth

% Vref

VSNS Falling, OVP hysteresis

OVP Protection Delay

Hiccup Blanking Time

OVP_Tdly

µs

Tblk_Hiccup Unlatched OVP

Under Voltage Protection

UVP Trip Threshold

UVP_Vth

VSNS Falling

% Vref

µs

UVP Protection Delay

Hiccup Blanking Time

UVP_Tdly

Tblk_Hiccup

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25 A single-voltage synchronous Buck regulator

Electrical specifications

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Power Good

% Vref

Pgood Turn on Threshold

Pgood Turn off Threshold

Pgood Sink Current

Pgood Voltage Low

VPG(upper) VSNS Rising

VPG(lower)

I_PG

VSNS Falling

PG = 0.5 V, En = 2 V

2.5

V_PG(low)

Vin = VCC =0 V, Rpull-up = 50 kΩ to

0.3

2.5

0.5

3.3 V

µs

Pgood Turn on Delay

V_{PG(on)_Dly}

VSNS Rising, see VPG(upper)

Pgood Comparator Delay

V_{PG(comp)_Dly}

VSNS < VPG(lower) or

VSNS > VPG(upper)

3.5

Pgood Open Drain Leakage

Current

PG = 3.3 V

µA

Thermal Shutdown

Hysteresis

140

Note 11

°C

Note:

11. Guaranteed by construction and not tested in production

12. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in

production.

13. The Ton is trimmed so that the target switching frequency is achieved at around 10A load current using

EVAL_38827_1Vout demo board.

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25 A single-voltage synchronous Buck regulator

Typical efficiency and power loss curves

8.1

PV_in= V_in= ꢄꢂ V, F_sw= ꢅꢆꢆ kHz

PV_in= V_in= 12 V, VCC = Internal LDO, I_o= 0 A-25 A, F_sw= 600 kHz, Room Temperature, No Air Flow. Note that the

efficiency and power loss curves include the losses of TDA38827, the inductor losses, the losses of the input and

output capacitors, and PCB trace losses. The table below shows the inductors used for each of the output

voltages in the efficiency measurement.

Table 1

Inductors for PV_in=V_in=12 V, F_s= 600 kHz

Vout (V)

Lout (nH)

150

P/N

Size (mm)

12.4 x 8.3 x 8

10.8 x 8 x 8

DCR (m)

0.15

HCB138380D-151 (Delta)

FP1008R5-R220-R (Cooper)

HCBD101195-351(Delta)

HCBD101195-451(Delta)

1.0

1.2

1.8

2.5

3.3

220

0.17

220

0.17

10.8 x 8 x 8

350

0.35

10.1 x 11.4 x 9.5

350

0.35

450

0.35

Final Datasheet

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25 A single-voltage synchronous Buck regulator

Typical efficiency and power loss curves

8.2

PV_in= V_in= ꢄꢂ V, F_sw= ꢁꢆꢆ kHz

PV_in= V_in= 12 V, VCC = Internal LDO, Io = 0 A-25 A, F_sw= 800 kHz, Room Temperature, No Air Flow. Note that the

efficiency and power loss curves include the losses of TDA38827, the inductor losses, the losses of the input and

output capacitors, and PCB trace losses. The table below shows the inductors used for each of the output

voltages in the efficiency measurement.

Table 2

Inductors for PV_in=V_in=12 V, F_sw= 800 kHz

Vout (V)

Lout (nH)

150

P/N

Size (mm)

12.4 x 8.3 x 8

10.8 x 8 x 8

DCR (m)

0.15

1.0

1.2

1.8

2.5

3.3

HCB138380D-151 (Delta)

FP1008R5-R220-R (Cooper)

HCBD101195-351(Delta)

150

0.15

220

0.17

220

0.17

10.8 x 8 x 8

350

0.35

10.1 x 11.4 x 9.5

Final Datasheet

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25 A single-voltage synchronous Buck regulator

Typical efficiency and power loss curves

8.3

PV_in= V_in= ꢄꢂ V, F_sw= ꢄꢆꢆꢆ kHz

PV_in= V_in= 12 V, VCC = Internal LDO, Io = 0 A-25 A, F_sw= 1000 kHz, Room Temperature, No Air Flow. Note that the

efficiency and power loss curves include the losses of TDA38827, the inductor losses, the losses of the input and

output capacitors, and PCB trace losses. The table below shows the inductors used for each of the output

voltages in the efficiency measurement.

Table 3

Inductors for PV_in=V_in=12 V, F_sw= 1000 kHz

Vout (V)

Lout (nH)

100

P/N

Size (mm)

6.4 x 9.5 x 10

DCR (m)

0.145

1.0

1.2

1.8

AH3740A-100K (ITG)

AH3740A-150K (ITG)

100

0.145

150

0.145

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Typical efficiency and power loss curves

8.4

PV_in= V_in= VCC = ꢇ V, F_sw= ꢅꢆꢆ kHz

PV_in= V_in= VCC = 5.0 V, I_o= 0 A – 25 A, F_sw= 600 kHz, Room Temperature, No Air Flow. Note that the efficiency and

power loss curves include the losses of TDA38827, the inductor losses, the losses of the input and output

capacitors and and PCB trace losses. The table below shows the inductors used for each of the output voltages

in the efficiency measurement.

Table 4

Inductors for PV_in=V_in=VCC=5 V, F_sw= 600 kHz

Vout (V)

Lout (nH)

150

P/N

Size (mm)

6.4 x 9.5 x 10

DCR (m)

0.145

AH3740A-150K (ITG)

1.0

1.2

1.8

3.3

150

0.145

150

0.145

150

0.145

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25 A single-voltage synchronous Buck regulator

Thermal de-rating curves

Measurement is done on Evaluation board of EVAL_38827. PCB is a 6-layer board with 1.5 ounce Copper for top

and bottom layer and 2 ounce Copper for the inner layers, FR4 material, size ꢆ.ꢃ”xꢆ.75”.

Figure 4 Thermal de-rating curves, PV_in= 12 V, V_out=1.2 V/3.3 V/5 V, f_sw= 600 kHz, VCC = Internal LDO

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RDS(ON) of MOSFET over temperature

R_DSꢈONꢉof MOSFET over temperature

Figure 5 R_DS(on)of MOSFETs over Junction Temperature

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Typical operating characteristics (-ꢊꢆ C ≤ Tj ≤ +ꢄꢂꢇ Cꢉ

Typical operating characteristics ꢈ-ꢊꢆ °C ≤ T_j≤ +ꢄꢂꢇ °Cꢉ

Figure 6 Typical operating characteristics (set 1 of 3)

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Typical operating characteristics (-ꢊꢆ C ≤ Tj ≤ +ꢄꢂꢇ Cꢉ

Figure 7 Typical operating characteristics (set 2 of 3)

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Typical operating characteristics (-ꢊꢆ C ≤ Tj ≤ +ꢄꢂꢇ Cꢉ

Figure 8 Typical operating characteristics (set 3 of 3)

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Theory of operation

12.1

Fast Constant On-Time control

The TDA38827 features a proprietary Fast Constant On-Time (COT) Control, which can provide fast load transient

response, good output regulation and minimize the design effort. Fast COT control compares the output voltage,

V_o, to a floor voltage combined with an internal ramp signal. When V_outdrops below that signal, a PWM signal is

initiated to turn on the high-side FET for a fixed on-time. The floor voltage is generated from an internal

compensated error amplifier, which compares the Vout with a reference voltage. Compared to the traditional

COT control, Fast COT control significantly improves the Vout regulation.

12.2

Enable

En pin controls the on/off of the TDA38827. An internal Under Voltage Lock-Out (UVLO) circuit monitors the En

voltage. When the En voltage is above an internal threshold, the internal LDO starts to ramp up. When the

VCC/LDO voltage rises above the VCC_UVLO_Start threshold, the soft-start sequence starts. The En pin can be

configured in three ways, as shown in Figure 9. With configuration 2, the Enable signal is derived from the Pvin

voltage by a set of resistive divider, REN1 and REN2. By selecting different divider ratios, users can program a

UVLO threshold voltage for the bus voltage. This is a very desirable feature because it prevents the TDA38827

from operating until Pvin is higher than a desired voltage level. For some space constrained designs, En pin can

be directly connected to Pvin without using the external resistor dividers, as shown in Configuration 3. En pin

should not be left floating. A pull down resistor in the range of tens of kilohms is recommended. Figure 10

illustrates the corresponding start-up sequences with three En configurations.

PVin

Vin

PVin

R_EN1

Vcc

PVin

Vin

Vcc

TDA38827

R_EN2

ꢁ

ꢂꢃꢄ

En = an external logic signal

Configuration 1

En = _ꢁ

× ꢆ_ꢇꢈꢉ

ꢂꢃꢄ

Pvin = Vin = En

Configuration 3

+ꢁ

ꢂꢃꢅ

Configuration 2

Figure 9 Enable Configurations

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25 A single-voltage synchronous Buck regulator

Theory of operation

Pvin= Vin=12V

PVin=Vin=En=12V

Pvin = Vin = 12V

Vcc_ UVLO

Vcc

Vcc_UVLO

En Threshold

Vcc_ UVLO

En = REN2/(REN1+REN2)*PVin

En>1.2V

En Threshold

Pgood Turn-on

threshold

Pgood Turn-on

threshold

Pgood Turn-on

threshold

2.5ms

PGood

Pgood stays at logic low

ꢁ

ꢂꢃꢄ

En = an external logic signal

Configuration 1

En = _ꢁ

× ꢆ_ꢇꢈꢉ

ꢂꢃꢄ

Pvin = Vin = En

Configuration 3

+ꢁ

ꢂꢃꢅ

Configuration 2

Figure 10 Start-up sequence

12.3

FCCM and DEM operation

The TDA38827 offers two operation modes: Forced Continuous Conduction (FCCM) and Diode Emulation Mode

(DEM). With FCCM, the TDA38827 always operates as a synchronous buck converter with a pseudo constant

switching frequency and therefore achieves small output voltage ripples. In DEM, the synchronous FET is turned

off when the inductor current is close to zero, which reduces the switching frequency and improves the efficiency

at light load. At heavy load, both FCCM and DEM operate in the same way. The operation mode can be selected

with TON/MODE pin, as shown in Table 5. It should be noted that the selection of the operation mode cannot be

changed on the fly. To load a new TON/MODE configuration, En or VCC voltage needs to be cycled.

12.4

Pseudo constant switching frequency

The TDA38827 offers eight programmable switching frequencies, f_sw, from 600 kHz to 2 MHz, by connecting an

external resistor from TON/MODE pin to the ground. Based on the selected f_sw, the TDA38827 generates the

corresponding on-time of the Control FET for a given PV_inand V_o, as shown by the formula below.

ꢌ_ꢍ

ꢎ

ꢊ

ꢋꢉ

ꢆꢌ

ꢏ

ꢐꢑ

ꢈꢉ

Where f_swis the desired switching frequency. During the operation, the TDA38827 monitors PV_inand V_o, and can

automatically adjust the on-time to maintain the pre-selected f_sw. With the increase of the load, the switching

frequency can increase to compensate for the power losses. Therefore, the TDA38827 has a pseudo constant

switching frequency.

Table 5 lists the resistors for TON/MODE pin. In this table, E96 resistors with ±1% tolerance are used. If E12

resistor values are preferred, please refer to the Section 12.15. To load a new TON/MODE configuration, En or

VCC voltage needs to be cycled.

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Theory of operation

Table 5 Configuration Resistors for Rt/MODE Pin

Rt/MODE Resistor (kΩꢉ

Freq (kHz)

Mode

±1% Tolerance

600

800

1.5

2.49

1000

1200

1400

1600

1800

2000

600

3.48

FCCM

4.53

5.76

7.32

8.87

10.5

12.1

800

1000

1200

1400

1600

1800

2000

800

16.2

DEM

18.7

21.5

24.9

28.7

Rt/MODE = Floating

FCCM

12.5

Soft-start

The TDA38827 has an internal digital soft-start to control the output voltage rise and to limit the current surge at

the start-up. To ensure a correct start-up, the soft-start sequence initiates when the EN and VCC voltages rise

above their respective thresholds. The internal soft-start signal linearly rises from 0 V to 0.8 V in a defined time

duration. The soft-start time does not change with the output voltage. During the soft-start, the TDA38827

operates in DEM until 1ms after the output voltage ramps above the Pgood turn-on threshold. The TDA38827 has

four soft-start time options selected by placing a resistor from SS/Latch pin to the ground. Table 6 lists the

resistor values and its corresponding soft-start time. In this table, E96 resistors with ±1% tolerance are used. If

E12 resistor values are preferred, please refer to the Section 12.15. For each soft-start time, there are two resistor

options available. Please note that SS/Latch pin is a multi-function pin, which is also used to select different

responses for Over Voltage Protection (OVP). To load a new SS/Latch selection, En or VCC voltage needs to be

cycled.

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Theory of operation

Table 6 Configuration Resistor for SS/Latch Pin

SS/Latch Resistor ꢈkΩꢉ

Soft-start Time

(ms)

OVP

±1% Tolerance

4.53

1.5

5.76

Latch

2.49

7.32

3.48

8.87

10.5

18.7

12.1

21.5

No Latch

Latch

24.9

16.2

28.7

SS/Latch = Floating, VCC

12.6

Pre-bias start-up

The TDA38827 is able to start up into a pre-charged output without causing oscillations and disturbances of the

output voltage. When TDA38827 starts up with a pre-biased output voltage, both control FET and Synch FET are

kept off till the internal soft-start signal exceeds the FB voltage.

12.7

Internal Low – Dropout ꢈLDOꢉ regulator

The TDA38827 has an integrated low-dropout LDO regulator, providing the bias voltage for the internal circuitry.

To minimize the standby current, the internal LDO is disabled when the En voltage is pulled low. VIN pin is the

input of the LDO. When using the internal LDO for a single rail operation, VIN pin should be connected to PVIN

pin. To save the power losses on the LDO, an external bias voltage can be used by connecting VIN pin to the

VCC/LDO pin. Figure 11 illustrates the configuration of VCC/LDO, and VIN pin.

PVin

Ext Vcc

PVin

4.7uF

Vin

PVin

VCC/LDO

Vin

PVin

VCC/LDO

TDA38827

PGND

TDA38827

PGND

2.2uF ~10uF

10uF

Single rail operation with the internal LDO Use an external VCC

Figure 11 Configuration of Using the internal LDO or an external VCC.

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Theory of operation

Section 7.1 specified the recommended operating voltage range of V_inand VCC under different configurations.

Following design guidelines are recommended when configuring the VCC/LDO.



Place a bypass capacitor to minimize the disturbance on the VCC pin. For a single rail operation using the

internal LDO, a 4.7 µF low ESR ceramic capacitor must be used between VIN pin and PGND and a 2.2 µF~10 µF

low ESR ceramic capacitor is required to be placed close to the VCC/LDO with reference to PGND. 10 µF MLCC

is recommended for VCC bypass capacitor when VIN is below 5.5 V. When using an external VCC bias voltage,

a 10 µF ceramic capacitor can be shared with VIN, and VCC/LDO pin.



For applications using the internal LDO with 4.3 V ꢉ V_inꢉ ꢅ.ꢄ V, the LDO can be in the dropout mode. It is

important to ensure that the LDO voltage does not fall below the VCC UVLO threshold voltage. At V_in= 4.3 V,

I_CCmust not exceed 50 mA under all operating conditions such as during a step-up load transient, in which the

control loop may require the increase of f_sw. OCP limits can be reduced due to the lower VCC voltage.

12.8

Over Current Protection ꢈOCPꢉ

The TDA38827 offers cycle-by-cycle OCP response with four selectable current limits, which is set by the

resistance between ILIM pin and GND. The selected OCP limit bank is loaded to the IC during the power up and

cannot be changed on the fly. To change the OCP limit, users must cycle EN signal or VCC voltage. Cycle-by-cycle

OCP response allows the TDA38827 to fulfill a brief high current demand, such as a high inrush current during the

start-up. The detailed operation is explained as follows.

The OCP is activated when EN voltage is above its threshold. The OCP circuitry monitors the current of the

Synchronous MOSFET through its R_ds(on). When a new PWM pulse is requested by the control loop, if the current

of Synchronous MOSFET exceeds the selected OCP limit, the TDA38827 skips the PWM pulse and extends the on-

time of Synchronous MOSFET till the current drops below the OCP limit. The OCP operation is also illustrated in

Figure 12. During OCP events, the valley of the inductor current is regulated around the OCP limit. But during

the first switching cycle when the OCP is tripped, the valley of the inductor current can drop slightly below the

OCP limit. It should be noted that OCP events do not pull the Pgood signal low unless the V_odrops below the

Pgood turn-off threshold. If the OCP event persists, the output voltage can eventually drop below the Under

Voltage Protection (UVP) threshold and trigger UVP. Then the TDA38827 enters a hiccup mode.

The OCP limits are thermally compensated. Please refer to the typical performance of OCP limits in Figure 8. The

OCP limits specified in the Section 7.2 refer to the valley of the inductor current when OCP is tripped. Therefore,

the corresponding output DC current can be calculated as follows:

∆ꢜ_ꢘ

ꢒ_{ꢋꢓꢔ_ꢕꢖꢗ}= ꢒ_ꢘꢙꢚ

ꢛ

ꢝ

Where: I_{out_OCP}= Output DC current when OCP is tripped. I_LIM= OCP limit specified in the Section 7.2, which is the

valley of inductor current. ΔiL = Peak-peak inductor ripple current.

To avoid the inductor saturation during OCP events, the following criterion is recommended for the inductor

saturation current rating.

ꢒ_ꢐꢞꢔꢟ ꢒ_{ꢘꢙꢚ_ꢠꢞꢡ}ꢛ ∆ꢜ_ꢘ

Where: I_satis the inductor saturation current and I_{LIM_max}is the maximum spec of the OCP limit.

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Theory of operation

OCP Tripped

Current

Limit

UVP Hiccup

Blanking

time

Inductor

Pulse

Current

skipped

HDrv

LDrv

PGood

UVP

Threshold

PGood Turn-off

Threshold

Figure 12 Cycle-by-cycle OCP response

12.9

Under Voltage Protection ꢈUVPꢉ

Under Voltage Protection (UVP) provides additional protection during OCP fault or other faults. UVP is activated

when the soft-start voltage rises above 100 mV. UVP circuitry monitors the FB voltage. When it is below the UVP

threshold for 5 µs (typical), an under voltage trip signal asserts and both Control MOSFET and Synchronous

MOSFET are turned off. The TDA38827 enters a hiccup mode with a blanking time of 20 ms, during which Control

MOSFET and Synchronous MOSFET remain off. After the completion of blanking time, the TDA38827 attempts to

recover to the nominal output voltage with a soft-start, as shown in Figure 12. The TDA38827 will repeat hiccup

mode and attempt to recover until UVP condition is removed.

12.10

Over Voltage Protection ꢈOVPꢉ

Over Voltage Protection (OVP) is achieved by comparing the VSNS voltage to an OVP threshold voltage. When the

VSNS voltage exceeds the OVP threshold, an over voltage trip signal asserts after 7 µs (typical) delay. Control

MOSFET is latched off immediately and Pgood flags low. Synchronous MOSFET remains on to discharge the

output capacitor. When FB voltage drops below around 115% of the reference voltage, Synchronous MOSFET

turns off to prevent the complete depletion of the output capacitors. Figure 13 illustrates the OVP operation.

The OVP comparator becomes active when the EN signal is above the start threshold.

With SS/Latch pin, two OVP responses can be selected: Latch or No Latch, as shown in Table 6. With a latched

OVP response, Control FET remains latched off until either VCC voltage or EN signal is cycled. With an unlatched

OVP response, the TDA38827 enters a hiccup mode. Control FET remains off for a blanking time of 20ms. After

hiccup blanking time expires, the TDA38827 will try to restart with a soft-start. The TDA38827 can stay in the

hiccup mode infinitely if over voltage fault persists.

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25 A single-voltage synchronous Buck regulator

Theory of operation

HDrv

LDrv

120%V_ref

115%V_ref

V_ref

OVP

91%V_ref

84%V_ref

VSNS

PGood

Pgood turn-on

delay =2.5ms

Pgood turn-on

delay =2.5ms

OVP delay =7us

Figure 13 Over voltage protection response and Pgood behavior.

12.11

Over Temperature Protection ꢈOTPꢉ

Temperature of the controller is monitored internally. When the temperature exceeds the over temperature

threshold, OTP circuitry turns off both Control and Synchronous MOSFETs, and resets the internal soft start.

Automatic restart is initiated when the sensed temperature drops back into the operating range. The thermal

shutdown threshold has a hysteresis of 20 °C.

12.12

Power Good ꢈPgoodꢉ output

The Pgood pin is the open drain of an internal NFET, and needs to be externally pulled high through a pull-up

resistor. Pgood signal is high when three criteria are satisfied.

1. En signal and VCC voltage are above their respective thresholds.

2. No over voltage and over temperature faults occur.

3. V_ois within the regulation.

In order to detect if V_ois in regulation, Pgood comparator continuously monitors the VSNS voltage. When VSNS

voltage ramps up above the upper threshold, Pgood signal is pulled high after 2.5 ms. When VSNS voltage drops

below the lower threshold, Pgood signal is pulled low immediately. Figure 13 illustrates the Pgood response.

During the start-up with a pre-biased voltage, Pgood signal is held low before the first PWM is generated and is

then pulled high with 2.5 ms delay after VSNS voltage rises above the Pgood threshold. TDA38827 also integrates

an additional PFET in parallel to the Pgood NFET, as shown in Figure 2. This PFET allows Pgood signal to stay at

logic low when the VCC voltage is not present, and Pgood pin is pulled up by an external bias voltage. Please refer

to Figure 10. Since Pgood PFET has relatively higher on resistance, a 50 kΩ pull-up resistor is needed for a Pgood

bias voltage of 3.3 V to maintain the Pgood signal at logic low when Pgood PFET is on.

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Theory of operation

12.13

Minimum on – time and minimum off – time

The minimum on-time refers to the shortest time for Control MOSFET to be reliably turned on. The minimum off-

time refers to the minimum time duration in which Synchronous FET stays on before a new PWM pulse is

generated. The minimum off-time is needed for TDA38827 to charge the bootstrap capacitor, and to sense the

current of the Synchronous MOSFET for OCP.

For applications requiring a small duty cycle, it is important that the selected switching frequency results in an

on-time larger than the maximum spec of the minimum on-time in the Section 7.2. Otherwise the resulting

switching frequency may be lower than the desired target. Following formula could be used to check for the

minimum on-time requirement.

ꢌ_ꢍ

> max ꢣꢤꢥꢦ ꢧꢏ ꢊ_{ꢋꢉ ꢩiꢪ}

ꢨ

ꢫ

ꢢꢏ × ꢆꢌ

ꢐꢑ

ꢈꢉ

Where f_swis the desired switching frequency. k is the variation of the switching frequency. As a rule of thumb,

select k = 1.25 to ensure the design margin.

For applications requiring a high duty cycle, it is important to make sure a proper switching frequency is selected

so that the resulting off-time is longer than the maximum spec of the minimum off-time in the Section 7.2, which

can be calculated as shown below.

ꢆꢌ − ꢌ_ꢍ

ꢈꢉ

> max ꢣꢤꢥꢦ ꢧꢏ ꢊ_{ꢋꢬꢬ ꢩiꢪ}

ꢨ

ꢫ

ꢢꢏ × ꢆꢌ

ꢐꢑ

ꢈꢉ

Where f_swis the desired switching frequency. k is the variation of the switching frequency. As a rule of thumb,

select k = 1.25 to ensure the design margin.

Please note that with the increase of load current, f_swwill increase to maintain the ꢌ_ꢍregulation. Especially

during a load transient, a fast large load increase could increase f_swsignificantly for a short-period of time.

Therefore extra design margin needs to be considered to cover the worst case scenario. Also note that OCP

limit may be degraded when off-time is close to ꢊ_{ꢋꢬꢬ ꢩiꢪ}

ꢨ

ꢫ

The maximum duty cycle can be determined by the selected on-time and minimum off-time, as shown below.

ꢊ

ꢋꢉ

ꢭ_ꢠꢞꢡ

ꢊ

ꢋꢉ

ꢛ ꢊ_{ꢋꢬꢬꢨꢩiꢪꢫ}

12.14

Selection of feedforward capacitor and feedback resistors

A small MLCC capacitor, Cff, is preferred in parallel with the top feedback resistor, RFB1, to provide extra phase

boost and to improve the transient load response, as shown in Figure 14. Following formula can be used to

help select Cff and RFB1. The value of Cff is recommended to be 100 pF or higher to minimize the impact of

circuit parasitic capacitance. Cff and RFB1 may be further optimized based on the transient load tests. Where

Lo and Co are the output LC filter of the buck regulator.

ꢳ ꢲ

√

ꢍ

ꢮ_ꢯꢰꢱꢲ_ꢬꢬ

ꢴ × 4.ꢵ

Table 7 Selection of m

0.3

0.5

0.7

ꢆ V ꢉ Vo ꢉ 6 V

1.2 V < Vo < 3 V

Vo ꢉ ꢀ.ꢂ V

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Theory of operation

RFB1 Cff

RFB2

Figure 14 Configuration of feedforward capacitor, Cff.

12.15

Resistors for configuration pins

To properly configure SS/LATCH pin, TON/ MODE pin and ILIM pin, E96 resistors with ±1% tolerance must be

used per Table 5, Table 6 and Section 7.2. If E12 resistor values are preferred, the E96 resistors can be replaced

with two or three E12 resistors in series, as shown in Table 8. Note that the tolerance of E12 resistors must be

±0.1%.

Table 8 Replacement of E96 configuration resistors with E12 resistors in series

E96 ±1%

R ꢊkΩꢋ

4.53

1.50

5.76

2.49

7.32

3.45

8.87

10.5

12.1

21.5

E12 ±0.1% (R = R_S1+ R_S2or R_S1+ R_S2+ R_S3)

R_S1ꢊkΩꢋ

R_S2ꢊkΩꢋ

1.8

R_S3ꢊkΩꢋ

2.7

1.5

5.6

1.8

6.8

3.3

8.2

N/A

0.18

0.15

0.68

0.56

0.15

0.68

0.47

0.1

3.3

3.9

24.9

16.2

28.7

21.5

24.9

2.7

1.2

1.8

3.3

2.7

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Design example

In this section, an example is used to explain how to design a buck regulator with the TDA38827. The

application circuit is shown in Figure 15. The design specifications are given below.



PV_in= 12 V (±10%)

V_o= 1.0 V

I_o= 25 A

V_oripple voltage = ±1% of V_o

Load transient response = ± 3% of V_owith a step load current = 9 A and slew rate = 30 A/µs

13.1

Enabling the TDAꢀꢁꢁꢂꢃ

The TDA38827 has a precise Enable threshold voltage, which can be used to implement a UVLO of the input bus

voltage by connecting the EN pin to PV_inwith a resistor divider, as shown in Configuration 2 of Figure 9. The

Enable feedback resistor, R_EN1and R_EN2, can be calculated as follows.

ꢮ_ꢶꢷꢸ

ꢆꢌ

ꢟ ꢌ_{ꢶꢷꢨꢩꢹꢺꢫ}

ꢈꢉꢨꢩiꢪꢫ

ꢮ_ꢶꢷꢱꢛ ꢮ_ꢶꢷꢸ

ꢌ_{ꢶꢷꢨꢩꢹꢺꢫ}

ꢆꢌ_{ꢈꢉꢨꢩiꢪꢫ}− ꢌ_{ꢶꢷꢨꢩꢹꢺꢫ}

ꢮ_ꢶꢷꢸꢟ ꢮ_ꢶꢷꢱ

Where V_EN(max)is the maximum spec of the En-start-threshold as defined in Section 7.2. For PV_{in (min)}=10.8 V, select

R_EN1=49.9 kΩ and R_EN2=7.5 kΩ.

13.2

Programming the switching frequency and operation mode

The TDA38827 has very good efficiency performance and is suitable for high switching frequency operation. In

this case, 800 kHz is selected to achieve a good compromise between the efficiency, passive component size and

dynamic response. In addition, FCCM operation is selected to ensure a small output ripple voltage over the entire

load range. To select ꢇꢃꢃ kHz and FCCM operation, the TON/MODE pin can be left floating or connect a ꢀ.ꢅ kΩ

resistor to GND per Table 5.

13.3

Selecting input capacitors

Without input capacitors, the pulse current of Control MOSFET is directly from the input supply power. Due to

the impedance on the cable, the pulse current can cause disturbance on the input voltage and potential EMI

issues. The input capacitors filter the pulse current, resulting in almost constant current from the input supply.

The input capacitors should be selected to tolerate the input pulse current, and to reduce the input voltage

ripple. The RMS value of the input ripple current can be expressed by:

ꢒ_ꢁꢚꢻ= ꢒ × ꢭ × ꢨꢎ − ꢭꢫ

√

ꢋ

ꢌ

ꢋ

ꢭ =

ꢆꢌ

ꢈꢉ

Where I_RMSis the RMS value of the input capacitor current. I_ois the output current and D is the Duty Cycle. For I_o

= 25A and D_(max)= 0.09, the resulting RMS current flowing into the input capacitor is I_rms= 7.2 A.

Final Datasheet

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Design example

To meet the requirement of the input ripple voltage, the minimum input capacitance can be calculated as

follows.

ꢒ_ꢋ× ꢨꢎ − ꢭꢫ × ꢭ

ꢲ_{ꢈꢉꢨꢩiꢪꢫ}

ꢨ

ꢫ

ꢏ × ꢨ∆ꢆꢌ − ꢼꢽꢮ × ꢒ_ꢋ× ꢎ − ꢭ ꢫ

ꢐꢑ

ꢈꢉ

Where ∆PV_inis the maximum allowable peak-to-peak input ripple voltage, and ESR is the equivalent series

resistor of the input capacitors. Ceramic capacitors are recommended due to low ESR, ESL and high RMS current

capability. For I_o= 25 A, f_sw= ꢇꢃꢃ kHz, ESR = ꢆ mΩ, and ∆PV_in= 240 mV, C_in(min)> 15 µF. To account for the de-rating

of ceramic capacitors under a bias voltage, 10 x 22 µF/0805/25V MLCC are used for the input capacitors. In

addition, a bulk capacitor is recommended if the input supply is not located close to the voltage regulator.

13.4

Inductor selection

The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor

value results in a large ripple current, lower efficiency and high output noise, but helps with size reduction and

transient load response. Generally, the desired peak-to-peak ripple current in the inductor ꢊ∆iꢋ is found between

20% and 50% of the output current.

The inductor saturation current must be higher than the maximum spec of the OCP limit plus the peak-to-peak

inductor ripple current. For some core material, inductor saturation current may decrease as the increase of

temperature. So it is important to check the inductor saturation current at the maximum operating temperature.

The inductor value for the desired operating ripple current can be determined using the following relation:

ꢭ_ꢠꢈꢉ

ꢳ = ꢨꢆꢌ_{ꢈꢉꢨꢩꢹꢺꢫ}− ꢌ ꢫ ×

ꢋ

∆ꢜ_{ꢘꢨꢩꢹꢺꢫ}× ꢾ

ꢐꢑ

ꢌ

ꢋ

ꢭ_ꢠꢈꢉ

ꢆꢌ

ꢈꢉꢨꢩꢹꢺꢫ

ꢒ_ꢐꢞꢔꢟ ꢿꢲꢆ_ꢠꢞꢡꢛ ∆ꢜ_{ꢘꢨꢩꢹꢺꢫ}

Where: PV_in(max)= Maximum input voltage; ∆iL_max= Maximum peak-to-peak inductor ripple current; OCP_max

maximum spec of the OCP limit as defined in Section 7.2; and I_sat= inductor saturation current. In this case,

select inductor L =150 nH to achieve ∆iL_max= 30% of I_omax. The I_satshould be no less than 42 A.

13.5

Output capacitor selection

The output capacitor selection is mainly determined by the output voltage ripple and transient requirements.

To satisfy the V_oripple requirement, C_oshould satisfy the following criterion.

∆ꢜ_ꢘꢠꢞꢡ

ꢲ_ꢋ>

ꣀ × ∆ꢌ × ꢏ

ꢋꣁ

ꢐꢑ

Where ∆V_oris the desired peak-to-peak output ripple voltage. For ∆iL_max= 7.6 A, ∆V_or=20 mV, f_sw= 800 kHz, C_o

must be larger than 59 µF. The ESR and ESL of the output capacitors, as well as the parasitic resistance or

inductance due to PCB layout, can also contribute to the output voltage ripple. It is suggested to use Multi-

Layer Ceramic Capacitor (MLCC) for their low ESR, ESL and small size.

To meet the transient response requirements, the output capacitors should also meet the following criterion.

ꢳ × ∆ꢒ_ꢋ^ꢸ_{ꢨꢩꢹꢺꢫ}

ꢲ_ꢋ>

ꢝ × ∆ꢌ × ꢌ

ꢋꢘ

ꢋ

Final Datasheet

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Design example

Where ∆V_OLis the allowable V_odeviation during the load transient. ∆I_o(max)is the maximum step load current.

Please note that the impact of ESL, ESR, control loop response, transient load slew rate, and PWM latency is not

considered in the calculation shown above. Extra capacitance is usually needed to meet the transient

requirements. As a rule of thumb, we can triple the C_othat is calculated above as a starting point, and then

optimize the design based on the bench measurement. In this case, to meet the transient load requirement (i.e.

∆V_OL= 30 mV, ∆I_o(max)= 9 A), select C_o= ~800 µF. For more accurate estimation of C_o, simulation tool should be used

to aid the design.

13.6

Output voltage programming

Output voltage can be programmed with an external voltage divider. The FB voltage is compared to an internal

reference voltage of 0.6 V. The divider ratio is set to provide 0.6 V at the FB pin when the output is at its desired

value. The calculation of the feedback resistor divider is shown below.

ꢮ_ꢯꢰꢱ

ꢌ = ꢌ × ꢨꢎ ꢛ

ꢫ

ꢋ

ꣁꣂꢬ

ꢮ_ꢯꢰꢸ

Where R_FB1and R_FB2are the top and bottom feedback resistors. Select R_FB1= 7.5 kΩ and R_FB2= 11.3 kΩ, to achieve

V_o= 1 V. Same set of the resistor divider can be used at VSNS pin to achieve the same voltage scaling factor.

13.7

Feedforward capacitor

A small MLCC capacitor, C_ff, can be placed in parallel with the top feedback resistor, R_FB1, to improve the transient

response. Based on Section 12.14, C_ffcan be selected using the following formula.

ꢳ ꢲ

√

ꢍ

ꢮ_ꢯꢰꢱꢲ_ꢬꢬ

ꣃ.꣄ × 4.ꢵ

With Lo = 150 nH, Co = 800 µF and R_FB1= 7.5 kΩ, C_ff= 470 pF. C_ffcan be further optimized on the bench test based

on transient load response.

13.8

Bootstrap capacitor

For most applications, a 0.1 µF ceramic capacitor is recommended for bootstrap capacitor placed between SW

and BOOT Pin.

13.9

VIN and VCC/LDO bypass capacitor

Please see the recommendation in Section 12.7. A 10 µF MLCC is selected for VCC/LDO bypass capacitor and a

4.7 µF MLCC is selected for VIN bypass capacitor.

Final Datasheet

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Application information

14.1

Application diagram

Cin

10 x 22uF

CinHF

4.7uF

Vin = 12V 10%

Optional

REN1

49.9k ꢀ

REN2

7.5k ꢀ

Cvin

4.7uF

RBoot

0 ꢀ

PVin

Vin

Boot

CBoot

0.1uF

VCC/LDO

Vo=1V

RPG

49.9k ꢀ

Cvcc

10uF

150nH

PGood

CoHF

0.1uF

Co1 Co2

1x470uF 10x47uF

PGood

TDA38827

VSNS

SS/Latch

7.5k ꢀ

11.3k ꢀ

RSS

1.5k ꢀ

Rt/Mode

ILIM

Cff

470pF

RTon

1.5k ꢀ

AGnd

PGnd NC

RLIM

24.9k ꢀ

RFB1

7.5k ꢀ

RFB2

11.3k ꢀ

Figure 15 Application diagram of TDA38827. Pvin = 12 V, Vo = 1V, Io = 25 A, fsw = 800 kHz.

14.2

Typical operating waveforms

PV_in= V_in= 12.0 V, Vo = 1 V, I_o= 0 – 25 A, f_sw= 800 kHz, Room Temperature, no airflow

Figure 16

Start up at 25 A Load, (Ch₁: PV_in, Ch₂: Enable, Ch₃:Pgood,Ch₄: V_out)

Final Datasheet

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Application information

Figure 17

Pre-bias Start up at 0 A Load, (Ch₁: PV_in, Ch₂: Enable, Ch₃:Pgood, Ch₄: V_out)

Figure 18

Vout ripple at 25 A Load, fsw = 800 kHz, (Ch₃: V_o)

Figure 19

SW node, 25 A load, fsw = 800 kHz

Final Datasheet

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Application information

Figure 20

Short circuit and UVP (Hiccup), (Ch₁: V_o, Ch₃:Pgood)

Figure 21

Transient response at 9 A step load current @ 30 A/µs slew rate: Io= 16 A – 25 A, (Ch₁: V_o,

Ch₄: I_o), pk-pk: 52 mV, fsw = 800 kHz

Figure 22

Thermal image of the board at 25 A load TDA38827 = 92°C, L = 65.7°C, fsw = 800 kHz, room

temperature, natural convection

Final Datasheet

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Layout recommendations

PCB layout is very important when designing high frequency switching converters. Layout will affect noise pickup

and can cause a good design to perform with less than expected results. Following design guidelines are

recommended to achieve the best performance.



Bypass capacitors, including input/output capacitors, Vin and VCC bypass capacitors, should be placed near

the corresponding pins as close as possible.



Place bypass capacitors from TDA38827 power input (Drain of Control MOSFET) to PGND (Source of

Synchronous MOSFET) to reduce noise and ringing in the system. The output capacitors should be terminated

to a ground plane that is away from the input PGND to mitigate the switching spikes on the Vout. The Vin and

VCC bypass capacitor should be terminated to PGND.



Place a boot strap capacitor near the TDA38827 BOOT and SW pin as close as possible to minimize the loop

inductance.



SW node copper should only be routed on the top layer to minimize the impact of switching noises

Connect AGND pin to the PGND pad through a single point connection. On the TDA38827 demo board, AGND

pin is connected to the exposed AGND pad (Pin 23) and then connected to the internal PGND layer through the

thermal via holes.



Via holes can be placed on PVIN and PGND pads to aid thermal dissipation.

Wide copper polygons are desired for Pvin and PGND connections in favor of power losses reduction and

thermal dissipation. Sufficient via holes should be used to connect power traces between different layers.



To implement the V_osensing, following design guidelines should be followed, as illustrated in Figure 23.

The output voltage can be sensed from a high-frequency bypass capacitor of 0.1 µF or higher,

preferably through a 15 mil PCB trace.

Keep the Vout sense line away from any noise sources and shield the sense line with ground

planes.

The sense trace is connected to a feedback resistor divider with the lower resistor terminated at

AGND pin.



The En pin and configuration pins including SS/Latch, Rt/MODE, and ILIM should be terminated to a quiet

ground. On the TDA38827 standard demo board, they are terminated to the PGND copper plane away from

the power current flow. Alternatively, they can be terminated to a dedicated AGND PCB trace.

Final Datasheet

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Layout recommendations

4.3V<Vin<17V

Enable

PVin

Vin

Boot

VCC/LDO

PGood

0.1uF

PGood

TDA38827

VSNS

SS/Latch

Rt/Mode

ILIM

Cff

AGnd

PGnd NC

RFB2

RFB1

Figure 23

Single-ended V_osense configuration

Following figures illustrate the PCB layout design of the TDA38827 standard demo board.

Figure 24

TDA38827 Demo Board – Top Layer

Final Datasheet

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Layout recommendations

Figure 25

TDA38827 Demo Board – Bottom Layer

Figure 26

TDA38827 Demo Board – 2^ndLayer (Ground)

Figure 27

TDA38827 Demo Board – 3^rdLayer (Ground & Signal)

Final Datasheet

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Layout recommendations

Figure 28

TDA38827 Demo Board – 4^thLayer (Ground & Signal)

Figure 29

TDA38827 Demo Board – 5^thLayer (Ground)

Final Datasheet

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Layout recommendations

15.1

Solder mask

Evaluation has shown that the best overall performance is achieved using the substrate/PCB layout as shown in

the following figures. PQFN devices should be placed to an accuracy of 0.050 mm on both X and Y axes. Self-

centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the

limits of self-centering on specific processes.

Infineon recommends that larger Power or Land Area pads are Solder Mask Defined (SMD). This allows the

underlying copper traces to be as large as possible, which helps in terms of current carrying capability and device

cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05 mm larger (on

each edge) than the openings in the solder mask. This allows for layers to be misaligned by up to 0.1 mm on both

axes. Ensure that the solder resist in-between the smaller signal lead areas is at least 0.15 mm wide, due to the

high x/y aspect ratio of the solder mask strip.

Figure 30

Solder mask (all dimensions in mm)

Final Datasheet

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Layout recommendations

15.2

Stencil design

Stencils for PQFN packages can be used with thicknesses of 0.100-0.250 mm (0.004-ꢃ.ꢃꢀꢃ”ꢋ. Stencils thinner

than 0.100 mm are unsuitable because they deposit insufficient solder paste to make good solder joints with

the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125 mm-0.200

mm (0.005-ꢃ.ꢃꢃꢇ”ꢋ, with suitable reductions, give the best results. A recommended stencil design is shown

below. This design is for a stencil thickness of ꢃ.ꢀꢂꢈ mm ꢊꢃ.ꢃꢃꢅ”ꢋ. The reduction should be adjusted for stencils

of other thicknesses.

Figure 31

Stencil pad size and spacing (all dimensions in mm)

Final Datasheet

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Package

This section includes marking, mechanical and packaging information for the TDA38827.

16.1

Marking information

PART NUMBER

38827

DATE CODE

ASSEMBLY

SITE CODE

4YWWP

XXX

PIN 1, IDENTIFIER

LOT CODE

Figure 32

Package marking

16.2

Dimensions

Figure 33

Package Dimensions (all dimensions in mm)

Final Datasheet

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Package

16.3

Tape and reel information

Figure 34

Pin 1 orientation in the tape

Final Datasheet

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Environmental qualifications

Qualification Level

Industrial

Moisture Sensitivity

QFN Package

JEDEC Level 2 @ 260 °C

Human Body Model

Charged Device Model

ANSI/ESDA/JEDEC JS-001, 2 (2000 V to < 4000 V)

ESD

ANSI/ESDA/JEDEC JS-002, C3 (ꢌ1000 V)

RoHS2 Compliant

This product is in compliance with EU Directive 2015/863/EU

amending Annex II to EU Directive 2011/65/EU (RoHS) and

contains Pb according RoHS exemption 7a, Lead in high

melting temperature type solders.

Final Datasheet

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Evaluation boards and support documentation

Table 9 TDA38827 Evaluation Boards and User Guides

Evaluation board

Specifications

Website Address

EVAL_38827_1Vout

12 V±10%, 1 V, 25 A

www.infineon.com/EVAL_38827_1Vout

Table 10 TDA38827 Package Information

Device

Package Type

PG-IQFN-22-2

Website Address

TDA38827

https://www.infineon.com/cms/en/product/packages/PG-IQFN

Final Datasheet

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TDA38827

RevisionꢀHistory

TDA38827

Revision:ꢀ2021-07-27,ꢀRev.ꢀ2.3

Previous Revision

Revision Date

2.0

Subjects (major changes since last revision)

Release of final version, Change Pin numbering from 23 pins to 17 pins, to match with

IR3894/5, IR3824/5/6/6A

2020-09-24

2.1

2.2

2.3

(1) Update ordering info; (2) Correct UVP activation threshold in section 12.9; (3) Correct

test conditions of dead time in EC table

2021-03-02

2021-04-17

1) Add max Vout of 6V to the recommended operating conditions; (2) Update note 8; (3)

Correct typo in Table 7; (4) Add Fig 22.

(1). Change typ value of top switch Rds(on) from 3.8mohm to 3.3mohm (2). Change test

condition of OCP limit in EC table from VCC = 5.0V to int LDO (3). Update Fig 30, 31,

33, and 34 (4). Correct typo in Table 7

2021-07-27

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Rev.ꢀ2.3,ꢀꢀ2021-07-27

TDA38827 [INFINEON]

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TDA3LADBJFABFQ1

TDA3LADBJFABFRQ1

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