SAK-TC1798F-512F300EP AB [INFINEON]

TC1798 是 AUDO MAX 系列终极旗舰产品。;


型号：	SAK-TC1798F-512F300EP AB
厂家：	Infineon
描述：	TC1798 是 AUDO MAX 系列终极旗舰产品。
文件：	总200页 (文件大小：5172K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

32-Bit

Microcontroller

TC1798

32-Bit Single-Chip Microcontroller

Data Sheet

V 1.1 2014-05

Microcontrollers

Edition 2014-05

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

32-Bit

Microcontroller

TC1798

32-Bit Single-Chip Microcontroller

Data Sheet

V 1.1 2014-05

Microcontrollers

TC1798

Table of Contents

Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

System Overview of the TC1798 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.1

TC1798 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92

5.1

Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94

Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94

Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . 5-95

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96

Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100

Extended Range Operating Conditions . . . . . . . . . . . . . . . . . . . . 5-102

DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105

Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105

Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . 5-125

Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . 5-132

Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136

Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-137

Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-138

Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . 5-140

AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-142

Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-142

Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-143

Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-145

Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-147

ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . 5-150

JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-151

DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-153

Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-154

Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 5-157

SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-159

ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-161

EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-163

BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-163

EBU Asynchronous Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-163

EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-170

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.6.1

5.3

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

5.3.12

5.3.12.1

5.3.12.2

5.3.12.3

Data Sheet

I-1

V 1.1, 2014-05

TC1798

5.3.12.4

5.3.12.5

5.4

EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-173

EBU DDR Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-174

Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-181

Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-184

Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-184

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-185

Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-185

5.5

5.5.1

5.5.2

5.5.3

History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Data Sheet

I-2

V 1.1, 2014-05

TC1798

Data Sheet

V 1.1, 2014-05

TC1798

Data Sheet

V 1.1, 2014-05

TC1798

Summary of Features

The SAK-TC1798F-512F300EL / SAK-TC1798F-512F300EP has the following

features:

•

High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– 300 MHz operation at full temperature range

32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

– 200 MHz operation at full temperature range

Multiple on-chip memories

•

– 4 Mbyte Program Flash Memory (PFLASH) with ECC

– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 2 x 8 Kbyte Key Flash

– 128 Kbyte Data Scratch-Pad RAM (DSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Data Cache (DACHE)

– 128 Kbyte Memory (SRAM)

– 16 Kbyte BootROM (BROM)

•

16-Channel DMA Controller

8-Channel Safe DMA (SDMA) Controller

Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels

serviced by CPU or PCP2

•

High performing on-chip bus structure

– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

•

Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,

parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data

length and shift direction

– Four SSC Guardian (SSCG) modules, one for each SSC

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external

power devices

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor

communication

Data Sheet

V 1.1, 2014-05

TC1798

Summary of Features

– One External Bus Interface (EBU) supporting different memories: asynchronous

memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR

flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0

(limited frequency at 1.8 V I/O supply)

– One MultiCAN Module with 4 CAN nodes and 128 free assignable message

objects for high efficiency data handling via FIFO buffering and gateway data

transfer (one CAN node supports TTCAN functionality)

– One FlexRay^TMmodule with 2 channels (E-Ray).

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer

Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer

functionality to realize autonomous and complex Input/Output management

– Two Capture / Compare 6 modules

– Two General Purpose 12 Timer Units (GPT120 and GPT121)

64 analog input lines for ADC

– 4 independent kernels (ADC0, ADC1, ADC2, and ADC3)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

4 different FADC input channels

•

– channels with impedance control and overlaid with ADC1 inputs

– Extreme fast conversion, 21 cycles of f_FADCclock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of

consecutive conversions in digital data reduction filter)

8 digital input lines for SENT

•

– communication according to the SENT specification J2716 FEB2008

238 digital general purpose I/O lines (GPIO)

Digital I/O ports with 3.3 V capability

On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)

Dedicated Emulation Device chip available (TC1798ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

Power Management System

•

Clock Generation Unit with PLL and PLL_ERAY

Flexible CRC Engine (FCE)

– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)

– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)

The SAK-TC1798N-512F300EP has the following features:

•

High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– 300 MHz operation at full temperature range

Data Sheet

V 1.1, 2014-05

TC1798

Summary of Features

•

32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

– 200 MHz operation at full temperature range

Multiple on-chip memories

– 4 Mbyte Program Flash Memory (PFLASH) with ECC

– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 2 x 8 Kbyte Key Flash

– 128 Kbyte Data Scratch-Pad RAM (DSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Data Cache (DACHE)

– 128 Kbyte Memory (SRAM)

– 16 Kbyte BootROM (BROM)

•

16-Channel DMA Controller

8-Channel Safe DMA (SDMA) Controller

Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels

serviced by CPU or PCP2

•

High performing on-chip bus structure

– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

•

Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,

parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data

length and shift direction

– Four SSC Guardian (SSCG) modules, one for each SSC

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external

power devices

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor

communication

– One External Bus Interface (EBU) supporting different memories: asynchronous

memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR

flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0

(limited frequency at 1.8 V I/O supply)

– One MultiCAN Module with 4 CAN nodes and 128 free assignable message

objects for high efficiency data handling via FIFO buffering and gateway data

transfer (one CAN node supports TTCAN functionality)

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer

Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer

functionality to realize autonomous and complex Input/Output management

– Two Capture / Compare 6 modules

Data Sheet

V 1.1, 2014-05

TC1798

Summary of Features

– Two General Purpose 12 Timer Units (GPT120 and GPT121)

•

64 analog input lines for ADC

– 4 independent kernels (ADC0, ADC1, ADC2, and ADC3)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

4 different FADC input channels

– channels with impedance control and overlaid with ADC1 inputs

– Extreme fast conversion, 21 cycles of f_FADCclock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of

consecutive conversions in digital data reduction filter)

8 digital input lines for SENT

•

– communication according to the SENT specification J2716 FEB2008

238 digital general purpose I/O lines (GPIO)

Digital I/O ports with 3.3 V capability

On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)

Dedicated Emulation Device chip available (TC1798ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

Power Management System

•

Clock Generation Unit with PLL and PLL_ERAY

Flexible CRC Engine (FCE)

– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)

– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)

The SAK-TC1798S-512F300EP has the following features:

•

High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– 300 MHz operation at full temperature range

32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

– 200 MHz operation at full temperature range

Multiple on-chip memories

•

– 4 Mbyte Program Flash Memory (PFLASH) with ECC

– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 2 x 8 Kbyte Key Flash

– 128 Kbyte Data Scratch-Pad RAM (DSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Data Cache (DACHE)

Data Sheet

V 1.1, 2014-05

TC1798

Summary of Features

– 128 Kbyte Memory (SRAM)

– 16 Kbyte BootROM (BROM)

16-Channel DMA Controller

8-Channel Safe DMA (SDMA) Controller

Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels

serviced by CPU or PCP2

•

High performing on-chip bus structure

– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

•

Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,

parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data

length and shift direction

– Four SSC Guardian (SSCG) modules, one for each SSC

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external

power devices

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor

communication

– One External Bus Interface (EBU) supporting different memories: asynchronous

memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR

flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0

(limited frequency at 1.8 V I/O supply)

– One MultiCAN Module with 4 CAN nodes and 128 free assignable message

objects for high efficiency data handling via FIFO buffering and gateway data

transfer (one CAN node supports TTCAN functionality)

– One FlexRay^TMmodule with 2 channels (E-Ray).

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer

Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer

functionality to realize autonomous and complex Input/Output management

– Two Capture / Compare 6 modules

– Two General Purpose 12 Timer Units (GPT120 and GPT121)

64 analog input lines for ADC

– 4 independent kernels (ADC0, ADC1, ADC2, and ADC3)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

4 different FADC input channels

•

– channels with impedance control and overlaid with ADC1 inputs

– Extreme fast conversion, 21 cycles of f_FADCclock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of

consecutive conversions in digital data reduction filter)

8 digital input lines for SENT

•

– communication according to the SENT specification J2716 FEB2008

Data Sheet

V 1.1, 2014-05

TC1798

Summary of Features

•

238 digital general purpose I/O lines (GPIO)

Digital I/O ports with 3.3 V capability

On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)

Dedicated Emulation Device chip available (TC1798ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

Power Management System

•

Clock Generation Unit with PLL and PLL_ERAY

Flexible CRC Engine (FCE)

– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)

– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)

Secure Hardware Extension (SHE)

•

– For further information please contact your Infineon representative

Data Sheet

V 1.1, 2014-05

TC1798

Summary of Features

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the

required product. This ordering code identifies:

•

The derivative itself, i.e. its function set, the temperature range, and the supply

voltage

•

The package and the type of delivery.

For the available ordering codes for the TC1798 please refer to the “Product Catalog

Microcontrollers”, which summarizes all available microcontroller variants.

This document describes the derivatives of the device.The Table 1 enumerates these

derivatives and summarizes the differences.

Table 1

TC1798 Derivative Synopsis

Derivative

Ambient Temperature Range

T_A= -40^oC to +125^oC

SAK-TC1798F-512F300EL

SAK-TC1798F-512F300EP

SAK-TC1798N-512F300EP

SAK-TC1798S-512F300EP

Data Sheet

V 1.1, 2014-05

TC1798

System Overview of the TC1798

The TC1798 combines three powerful technologies within one silicon die, achieving new

levels of power, speed, and economy for embedded applications:

•

Reduced Instruction Set Computing (RISC) processor architecture

Digital Signal Processing (DSP) operations and addressing modes

On-chip memories and peripherals

DSP operations and addressing modes provide the computational power necessary to

efficiently analyze complex real-world signals. The RISC load/store architecture

provides high computational bandwidth with low system cost. On-chip memory and

peripherals are designed to support even the most demanding high-bandwidth real-time

embedded control-systems tasks.

Additional high-level features of the TC1798 include:

•

Efficient memory organization: instruction and data scratch memories, caches

Serial communication interfaces – flexible synchronous and asynchronous modes

Peripheral Control Processor – standalone data operations and interrupt servicing

DMA Controller – DMA operations and interrupt servicing

General-purpose timers

High-performance on-chip buses

On-chip debugging and emulation facilities

Flexible interconnections to external components

Flexible power-management

The TC1798 is a high-performance microcontroller with TriCore CPU, program and data

memories, buses, bus arbitration, an interrupt controller, a peripheral control processor

and a DMA controller and several on-chip peripherals. The TC1798 is designed to meet

the needs of the most demanding embedded control systems applications where the

competing issues of price/performance, real-time responsiveness, computational power,

data bandwidth, and power consumption are key design elements.

The TC1798 offers several versatile on-chip peripheral units such as serial controllers,

timer units, and Analog-to-Digital converters. Within the TC1798, all these peripheral

units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect

(FPI) Bus and the Cross Bar Interconnect (SRI). Several I/O lines on the TC1798 ports

are reserved for these peripheral units to communicate with the external world.

Data Sheet

V 1.1, 2014-05

TC1798

System Overview of the TC1798Block Diagram

2.1

Block Diagram

Figure 1 shows the block diagram of the SAK-TC1798S-512F300EP.

Abbreviations:

FPU

ICACHE:

DCACHE

PSPR:

Instruction Cache

Data Cache

Program Scratch-Pad RAM

Data Scratch-Padl Data RAM

Boot ROM

Program Flash

Data Flash

Parameter RAM in PCP

Code RAM in PCP

SRI Cross Bar (XBar_SRI)

On Chip Bus Slave Interface

On Chip Bus Master Interface

PMI

DMI

LMU

DSPR:

TriCore

CPU

128 KB DSPR

32 KB PSPR

16 KB ICACHE

LDRAM

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

XBAR:

16 KB DCACHE

128 KB

SRAM

DCACHE

M/S

EBU

Cross Bar Interconnect (SRI)

XBAR

M/S

OCDSL1 Debug

Interface/JTAG

PMU0

PMU1

DMA

16 channels

(MemCheck)

Bridge

(SFI)

2 MB PFlash

192 KB DFlash

16 KB BROM

KeyFlash

2 MB PFlash

MLI

M/S

16 KB PRAM

Interrupt

System

SDMA

8 channels

ASC

PCP2

SHE

STM

SBCU

Ports

SSC

Core

SSCG

BMU

SSC Guardian

32 KB CMEM

E-Ray

(2 Channels)

5V (3.3V su

pported as well)

Ext. ADC Su

pply

External

Request Unit

MultiCAN

(4 Nodes, 128 MO)

ADC0

ADC1

ADC2

ADC3

CCU6

(2xCCU6)

(5V max)

SENT

(8 channels )

FCE

GPT120

SCU

GPTA0

GPTA1

LTCA2

MSC

FM-PLL

(LVDS)

(3.3V max)

PLL E-RAY

FADC

System Peripheral Bus (SPB)

3.3V

Ext. FADC Supply

TC1798

Figure 1

Block Diagram

Data Sheet

V 1.1, 2014-05

TC1798

System Overview of the TC1798Block Diagram

Figure 1 shows the block diagram of the SAK-TC1798F-512F300EL / SAK-TC1798F-

512F300EP.

Abbreviations:

FPU

ICACHE:

DCACHE

PSPR:

Instruction Cache

Data Cache

Program Scratch-Pad RAM

Data Scratch-Padl Data RAM

Boot ROM

Program Flash

Data Flash

Parameter RAM in PCP

Code RAM in PCP

SRI Cross Bar (XBar_SRI)

On Chip Bus Slave Interface

On Chip Bus Master Interface

PMI

DMI

LMU

DSPR:

TriCore

CPU

128 KB DSPR

32 KB PSPR

16 KB ICACHE

LDRAM

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

XBAR:

16 KB DCACHE

128 KB

SRAM

DCACHE

M/S

EBU

Cross Bar Interconnect (SRI)

XBAR

M/S

OCDS L1 Debug

Interface/JTAG

PMU0

PMU1

DMA

16 channels

(MemCheck)

Bridge

(SFI)

2 MB PFlash

192 KB DFlash

16 KB BROM

KeyFlash

2 MB PFlash

MLI

M/S

16 KB PRAM

Interrupt

System

SDMA

8 channels

ASC

PCP2

STM

SBCU

Ports

SSC

Core

SSCG

BMU

SSC Guardian

32 KB CMEM

E-Ray

(2 Channels)

5V (3.3V su

pported as well)

Ext. ADC Su

pply

External

Request Unit

MultiCAN

(4 Nodes, 128 MO)

ADC0

ADC1

ADC2

ADC3

CCU6

(2xCCU6)

(5V max)

SENT

(8 channels )

FCE

GPT120

SCU

GPTA0

GPTA1

LTCA2

MSC

FM-PLL

(LVDS)

(3.3V max)

PLL E-RAY

FADC

System Peripheral Bus (SPB)

3.3V

Ext. FADC Supply

TC1798

Figure 2

Block Diagram

Figure 1 shows the block diagram of the SAK-TC1798N-512F300EP.

Data Sheet

V 1.1, 2014-05

TC1798

System Overview of the TC1798Block Diagram

Abbreviations:

FPU

ICACHE:

DCACHE

PSPR:

Instruction Cache

Data Cache

Program Scratch-Pad RAM

Data Scratch-Padl Data RAM

Boot ROM

Program Flash

Data Flash

Parameter RAM in PCP

Code RAM in PCP

SRI Cross Bar (XBar_SRI)

On Chip Bus Slave Interface

On Chip Bus Master Interface

PMI

DMI

LMU

DSPR:

TriCore

CPU

128 KB DSPR

32 KB PSPR

16 KB ICACHE

LDRAM

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

XBAR:

16 KB DCACHE

128 KB

SRAM

DCACHE

M/S

EBU

Cross Bar Interconnect (SRI)

XBAR

M/S

OCDS L1 Debug

Interface/JTAG

PMU0

PMU1

DMA

16 channels

(MemCheck)

Bridge

(SFI)

2 MB PFlash

192 KB DFlash

16 KB BROM

KeyFlash

2 MB PFlash

MLI

M/S

16 KB PRAM

Interrupt

System

SDMA

8 channels

ASC

PCP2

STM

SBCU

Ports

SSC

Core

SSCG

BMU

SSC Guardian

32 KB CMEM

5V (3.3V su

pported as well)

Ext. ADC Su

pply

External

Request Unit

MultiCAN

(4 Nodes, 128 MO)

ADC0

ADC1

ADC2

ADC3

CCU6

(2xCCU6)

(5V max)

SENT

(8 channels )

FCE

GPT120

SCU

GPTA0

GPTA1

LTCA2

MSC

FM-PLL

(LVDS)

(3.3V max)

PLL E-RAY

FADC

System Peripheral Bus (SPB)

3.3V

Ext. FADC Supply

TC1798

Figure 3

Block Diagram

Data Sheet

V 1.1, 2014-05

TC1798

Pinning

Figure 4 is showing the TC1798 Logic Symbol.

Alternate Functions :

GPTA / HWCFG / E-RAY /

GPT12

PORST

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

TESTMODE

GPTA / MLI0 / ERU / SSC1 /

SSC3 / CCU6 / GPT12

General Control

ESR0

GPTA / SSC0 / SSC1

ESR1

GPTA/ CCU6 / GPT12

GPTA / SSC2 / CCU6 / GPT12

TRST

TCK / DAP0

ASC0 / ASC1 / MSC0 / MSC1 /

LVDS / MLI0 / CCU6 / GPT12

TDI / BRKIN/

OCDS /

BRKOUT

JTAG Control

ASC0 / ASC1 / SSC1 / CAN /

TDO /BRKOUT/

DAP2 / BRKIN

E-RAY / CCU6 / GPT12

ERU / ADC-Mux / SSC3

TMS / DAP1

MLI1 / GPTA/ SENT /

CCU6 / GPT12

MSC0 / MSC1 / GPTA /

SENT / CCU6 / GPT12

XTAL1

XTAL2

V_DDOSC

SSC0

EBU

Port 10

Port 11

Port 12

Port 13

Port 14

Port 15

Port 16

V_DDOSC3

Oscillator

V_SSOSC

TC1798

V_SS

EBU

V_DDPF

V_DDPF3

GPTA / EBU

GPTA/ EBU / CCU6 / GPT12

EBU / CCU6 / GPT12

EBU

V_DDEBU

V_DDP

V_DD

V_DDFL3

Digital Circuitry

Power Supply

V_SS

SENT

Port 17

Port 18

(Overlay with Analog Inputs )

V_DDSB

(ED only, N.C. in PD)

SSC2

V_SSAF

ADC / FADC

Analog Inputs

V_SSMF

AN[71:0]

V_FAGND

V_FAREF

V_DDMF

V_DDAF

FADC Analog

Power Supply

V_AREFx

V_AGNDx

V_DDM

ADC0 /ADC1 / ADC2 /ADC3

Analog Power Supply

V_SSM

1) Only available for SAK -TC-

1798 S-512F300EP / SAK-TC-

1798 F-512 F300EP / SAK-TC-

1798 F-512 F300EL

N.C.

TC1798_LogSym_516

Figure 4

TC1798 Logic Symbol

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

3.1

TC1798 Pin Configuration

This chapter shows the pin configuration of the TC1798 package PG-LFBGA- 516.

27 26

23 22

19 18

17 16

AK VSS P15.13 P16.2 P16.8 P15.1 P15.8 P15.3 P16.4 VSS VDDE P15.12 P15.7 P15.5 P16.0 VSSP VDDP P4.15 NC

NC VSSMF

AN71 AN69 AN67 AN65 NC NC NC NC

GND3 GND1

VA VA

GND2 REF3

AJ VDD VSS P15.10 P15.9 P15.0 P15.2 P15.11 P16.5 VSS VDDE P16.3 P16.1 P15.6 P15.4 VSSP VDDP P4.13 P4.11 NC VSSMF

AN70 AN68 AN66 AN64 NC NC NC NC

AH P15.15 VDD

AG P15.14 P16.6

AF P14.15 P16.7

NC NC

AN62 AN63

AN60 AN61

VA AN39 AN37

AN34 AN1 NC

AE P14.13 P14.14

VSS P14.6 P14.8 VSS P10.5 P10.0 P10.3 P4.7 P4.3 VSSP VSSMFAN30 AN26

AN58 AN59

GND0 REF0 P17.11 P17.9

VA VA AN38 AN36

REF2 REF1 P17.10 P17.8

AD P14.11 P14.12

AC P14.9 P14.10

AB P14.7 P16.12

VDD VSS P14.4 VDDE P10.4 P10.1 P4.10 P4.6 P4.2 VDDP

AN29 AN25

AN33 AN2 AN3

AN4 AN44

AN56 AN57

AN54 AN55

AN52 AN53

AGND

P14.2 VDD

VDD VFA

MF REF

AN43 AN41

AN47 AN32

P17.15 P17.13

P14.0 P13.15

P13.14 P13.13

P13.12 P13.11

P13.9 P13.8

P13.5 P13.4

VDDE VDDE

VSS VSS

VSS P10.2 P4.14 P4.9 P4.5 P4.1

VDD VSS P4.12 P4.8 P4.4 P4.0

AN28 AN24

AN5 AN45

VDD

AN42 AN40

AN7 AN0

AA P14.5 P16.11

AN31 AN27 AN35

AN6 AN46

AN50 AN51

VSSM VSSM

AN48 AN49

NC NC

P17.14 P17.12

P13.1

VDD

AN8 AN9

P17.0 P17.1

P14.3 P16.10

P14.1 P16.9

P12.4 P12.5

VDDE VDDE

VSS VSS

VDDM VSSM

AN10 AN11

P17.2 P17.3

AN12 AN13

P17.4 P17.5

P13.7 P13.6

P13.3 P13.2

P13.1 P13.0

VDD VSS VSS VSS VSS VDD

VSS VSS VSS VSS

AN14 AN15

P17.6 P17.7

VDD

VSS VSS

VDD

AN16 AN17

AN18 AN19

VSS VSS

AN20 AN21

AN22 AN23

VDDP VSSP

P7.2 P7.1

P1.12 P1.0

P1.6 P1.7

P8.4 P8.0

P8.3 P6.15

P6.11 P6.14

P6.10 P6.13

NC NC

VDD VDD

PF3 FL3

VSS VSS VSS VSS VSS VSS VSS VSS

VDDP VDDP

VSSP VSSP

P7.6 P7.7

NC NC

VSS VSS

OSC OSC

VDD VDD

PF OSC3

VDD

FL3

XTAL1 XTAL2

P7.5

VSS VDD

OSC OSC

P12.2 P12.3

P12.0 P12.1

P11.14 P11.15

P11.12 P11.13

P11.10 P11.11

P11.8 P11.9

P11.6 P11.7

P11.4 P11.5

P11.2 P11.3

TDI TMS

TDO P9.14

VSS VSS

VDD

VSS VSS

VDD

P7.4 P7.3

P7.0 P1.1

P1.9 P8.6

P8.5 P8.7

TCK TRST

ESR1 ESR0

P9.10 PORST

P9.7 P9.8

P9.2 P9.1

P9.3 P9.4

VSS VSS VSS VSS

Test

P9.13

mode

VDD VSS VSS VSS VSS VDD

P1.2 P1.3

P1.8 P1.4

P1.10 P1.11

P1.5 P1.13

P1.14 P1.15

NC NC

P9.5 P9.6

P9.0 VSSP P5.5 P3.0 P3.4 P3.12 P0.1 P0.3 P0.5 P0.7 P2.6 P8.1 VSSP P8.2

VSSP P5.7 P5.2 P5.12 P3.10 P0.0 P0.2 P0.4 P0.6 P2.10 P2.5 P2.4 P6.7 VSSP

P5.6 VSSP VDDP P5.9 P5.8 P5.3 P5.13 P5.14 P0.10 P0.13 VDDP P0.9 P2.12 P2.7 P2.3 P6.8 P6.4 VDDP VSSP P6.12

VSSP VDDP P5.4 P5.11 P5.10 P5.0 P5.1 P5.15 P0.11 P0.12 VSSP P0.14 P2.14 P2.8 P2.2 P6.9 P6.6 P6.5 VDDP NC

NC NC

P11.0 P11.1

P12.6 P12.7

VDDE NC

NC NC

VSS VSSP VDDP P9.12 NC NC

VSSP VDDP P9.9 P9.11 NC NC

NC NC P3.1 P3.3 P3.6 P3.8 P3.11 NC VDDP VSSP NC P3.14 P0.8 P18.0 P18.2 P18.4 P18.6 P2.13 P2.9 NC NC VDDP VSSP NC

NC NC P3.2 P3.5 P3.7 P3.9 P3.13 NC VDDP VSSP NC P3.15 P0.15 P18.1 P18.3 P18.5 P18.7 P2.15 P2.11 NC NC NC VDDP NC

Figure 5

TC1798 Pinning for PG-LFBGA- 516 Package

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package)

Symbol

Ctrl. Type Function

Port 0

J17

P0.0

I/O

A1+/ Port 0 General Purpose I/O Line 0

HWCFG0

OUT56

OUT80

P0.1

Hardware Configuration Input 0

OUT56 Line of GPTA0

I/O

OUT56 Line of GPTA1

OUT80 Line of LTCA2

K16

J16

K15

A1/

Port 0 General Purpose I/O Line 1

Hardware Configuration Input 1

OUT57 Line of GPTA0

HWCFG1

OUT57

OUT81

P0.2

I/O

OUT57 Line of GPTA1

OUT81 Line of LTCA2

A2/

Port 0 General Purpose I/O Line 2

Hardware Configuration Input 2

OUT58 Line of GPTA0

HWCFG2

OUT58

OUT82

P0.3

I/O

OUT58 Line of GPTA1

OUT82 Line of LTCA2

A1/

Port 0 General Purpose I/O Line 3

Hardware Configuration Input 3

OUT59 Line of GPTA0

HWCFG3

OUT59

OUT83

OUT59 Line of GPTA1

OUT83 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

J15

P0.4

I/O

A1/

Port 0 General Purpose I/O Line 4

Hardware Configuration Input 4

OUT60 Line of GPTA0

OUT60 Line of GPTA1

MCDS Output Event 0¹⁾

Port 0 General Purpose I/O Line 5

Hardware Configuration Input 5

OUT61 Line of GPTA0

OUT61 Line of GPTA1

MCDS Output Event 1¹⁾

Port 0 General Purpose I/O Line 6

Hardware Configuration Input 6

OUT62 Line of GPTA0

OUT62 Line of GPTA1

MCDS Output Event 2¹⁾

Port 0 General Purpose I/O Line 7

Hardware Configuration Input 7

OUT63 Line of GPTA0

OUT63 Line of GPTA1

MCDS Output Event 3¹⁾

Port 0 General Purpose I/O Line 8

HWCFG4

OUT60

EVTO0

P0.5

I/O

K14

J14

K13

B12

A1/

HWCFG5

OUT61

EVTO1

P0.6

I/O

A2/

HWCFG6

OUT62

EVTO2

P0.7

I/O

A1/

HWCFG7

OUT63

EVTO3

P0.8

I/O

A1/

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

G14

P0.9

I/O

A1/

Port 0 General Purpose I/O Line 9

RXDA0

Reserved

P0.10

E-Ray Channel A Receive Data Input 0 ²⁾

I/O

G17

F17

A2/

Port 0 General Purpose I/O Line 10

TXENA

E-Ray Channel A transmit Data Output

enable ²⁾

Reserved

P0.11

I/O

A2/

Port 0 General Purpose I/O Line 11

T5INB

GPT120

GPT121

T5INA

TXENB

E-Ray Channel B transmit Data Output

enable ²⁾

Reserved

P0.12

I/O

F16

A2/

Port 0 General Purpose I/O Line 12

T5EUDA

T5EUDB

TXDB

GPT120

GPT121

E-Ray Channel B transmit Data Output ²⁾

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

G16

P0.13

I/O

A1/

Port 0 General Purpose I/O Line 13

RXDB0

T5EUDB

T5EUDA

Reserved

P0.14

E-Ray Channel B Receive Data Input 0 ²⁾

GPT120

GPT121

I/O

F14

A2/

Port 0 General Purpose I/O Line 14

T6INA

GPT120

T6INB

GPT121

TXDA

I/O

E-Ray Channel A transmit Data Output ²⁾

Reserved

P0.15

A12

A1/

Port 0 General Purpose I/O Line 15

Reserved

Port 1

P1.0

I/O

A2/

Port 1 General Purpose I/O Line 0

REQ0

External trigger Input 0

EXTCLK1

Reserved

External Clock Output 1

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P1.1

I/O

A1/

Port 1 General Purpose I/O Line 1

REQ1

External trigger Input 1

CC60INA

CC60INB

CC60

CCU60

CCU61

I/O

CCU60

Reserved

P1.2

A1/

Port 1 General Purpose I/O Line 2

REQ2

External trigger Input 2

Reserved

P1.3

I/O

A1/

Port 1 General Purpose I/O Line 3

REQ3

External trigger Input 3

TREADY0B

Reserved

P1.4

MLI0 transmit Channel ready Input B

I/O

A2/

Port 1 General Purpose I/O Line 4

TCLK0

MLI0 transmit Channel Clock Output

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P1.5

I/O

A1/

Port 1 General Purpose I/O Line 35

MLI0 transmit Channel ready Input A

TREADY0A

Reserved

P1.6

I/O

A2/

Port 1 General Purpose I/O Line 6

MLI0 transmit Channel valid Output A

SSC1 Slave Select Output Line 10

CCU60

TVALID0A

SLSO10

COUT60

P1.7

A2/

Port 1 General Purpose I/O Line 7

CCU60

CC61INB

CC61INA

TData0

CC61

CCU61

I/O

MLI0 transmit Channel Data Output

CCU61

T3OUT

P1.8

GPT120

A1/

Port 1 General Purpose I/O Line 8

MLI0 Receive Channel Clock Input A

OUT64 Line of GPTA0

OUT64 Line of GPTA1

OUT88 Line of LTCA2

Port 1 General Purpose I/O Line 9

MLI0 Receive Channel ready Output A

SSC 1Slave Select Output Line 11

OUT65 Line of GPTA0

RCLK0A

OUT64

OUT88

P1.9

I/O

M10

A2/

RREADY0A O1

SLSO11

OUT65

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P1.10

I/O

A1/

Port 1 General Purpose I/O Line 10

MLI0 Receive Channel valid Input A

OUT66 Line of GPTA0

RVALID0A

OUT66

OUT90

P1.11

I/O

OUT66 Line of GPTA1

OUT90 Line of LTCA2

A1/

Port 1 General Purpose I/O Line 11

MLI0 Receive Channel Data Input A

SSC3 Input

RDATA0A

SLSI3

OUT67

OUT91

P1.12

I/O

OUT67 Line of GPTA0

OUT67 Line of GPTA1

OUT91 Line of LTCA2

A2/

Port 1 General Purpose I/O Line 12

External Clock Output 0

OUT68 Line of GPTA0

EXTCLK0

OUT68

P1.13

OUT68 Line of GPTA1

A1/

Port 1 General Purpose I/O Line 13

MLI0 Receive Channel Clock Input B

OUT69 Line of GPTA0

RCLK0B

OUT69

OUT93

P1.14

I/O

OUT69 Line of GPTA1

OUT93 Line of LTCA2

A1/

Port 1 General Purpose I/O Line 14

MLI0 Receive Channel valid Input B

OUT70 Line of GPTA0

RVALID0B

OUT70

OUT94

OUT70 Line of GPTA1

OUT94 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P1.15

I/O

A1/

Port 1 General Purpose I/O Line 15

MLI0 Receive Channel Data Input B

OUT71 Line of GPTA0

RDATA0B

OUT71

OUT95

OUT71 Line of GPTA1

OUT95 Line of LTCA2

Port 2

F11

P2.2

I/O

A1+/ Port 2 General Purpose I/O Line 2

SLSO02

SLSO12

SSC0 Slave Select Output Line 2

SSC1 Slave Select Output Line 12

SLSO02

AND

SSC0 & SSC1 Slave Select Output Line 2

AND Slave Select Output Line 12

SLSO12

G11

P2.3

I/O

A1+/ Port 2 General Purpose I/O Line 3

SLSO03

SLSO13

SSC0 Slave Select Output Line 3

SSC1 Slave Select Output Line 13

SLSO03

AND

SSC0 & SSC1 Slave Select Output Line 3

AND Slave Select Output Line 13

SLSO13

J11

P2.4

I/O

A1+/ Port 2 General Purpose I/O Line 4

SLSO04

SLSO14

SSC0 Slave Select Output Line 4

SSC1 Slave Select Output Line 14

SLSO04

AND

SSC0 & SSC1 Slave Select Output Line 4

AND Slave Select Output Line 14

SLSO14

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

J12

P2.5

I/O

A1+/ Port 2 General Purpose I/O Line 5

SLSO05

SLSO15

SSC0 Slave Select Output Line 5

SSC1 Slave Select Output Line 15

SLSO05

AND

SSC0 & SSC1 Slave Select Output Line 5

AND Slave Select Output Line 15

SLSO15

K12

P2.6

I/O

A1+/ Port 2 General Purpose I/O Line 6

SLSO06

SLSO16

SSC0 Slave Select Output Line 6

SSC1 Slave Select Output Line 16

SLSO06

AND

SSC0 & SSC1 Slave Select Output Line 6

AND Slave Select Output Line 16

SLSO16

G12

P2.7

I/O

A1+/ Port 2 General Purpose I/O Line 7

SLSO07

SLSO17

SSC0 Slave Select Output Line 7

SSC0 Slave Select Output Line 17

SLSO07

AND

SSC0 & SSC1 Slave Select Output Line

7AND Slave Select Output Line 17

SLSO17

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

F12

P2.8

I/O

A1/

Port 2 General Purpose I/O Line 8

IN0 Line of GPTA0

IN0 Line of GPTA1

IN0 Line of LTCA2

CCU62

IN0

CCPOS0A

T12HRB

T3INB

T3INA

OUT0

P2.9

CCU63

GPT120

GPT121

I/O

OUT0 Line of GPTA0

OUT0 Line of GPTA1

OUT0 Line of LTCA2

Port 2 General Purpose I/O Line 9

IN1 Line of GPTA0

IN1 Line of GPTA1

IN1 Line of LTCA2

OUT1 Line of GPTA0

OUT1 Line of GPTA1

OUT1 Line of LTCA2

A1/

IN1

OUT1

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

J13

P2.10

IN2

I/O

A1/

Port 2 General Purpose I/O Line 10

IN2 Line of GPTA0

IN2 Line of GPTA1

IN2 Line of LTCA2

CCU60

IN2

T12HRE

CC61INC

CTRAPA

CC60INC

CTRAPB

OUT2

P2.11

IN3

CCU60

CCU61

CCU63

I/O

OUT2 Line of GPTA0

OUT2 Line of GPTA1

OUT2 Line of LTCA2

Port 2 General Purpose I/O Line 11

IN3 Line of GPTA0

IN3 Line of GPTA1

IN3 Line of LTCA2

OUT3 Line of GPTA0

OUT3 Line of GPTA1

OUT3 Line of LTCA2

A1/

IN3

OUT3

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

G13

P2.12

IN4

I/O

A1/

Port 2 General Purpose I/O Line 12

IN4 Line of GPTA0

IN4 Line of GPTA1

IN4 Line of LTCA2

CCU62

IN4

T12HRB

CCPOS0A

T2INB

T2INA

OUT4

P2.13

IN5

CCU63

GPT120

GPT121

I/O

OUT4 Line of GPTA0

OUT4 Line of GPTA1

OUT4 Line of LTCA2

Port 2 General Purpose I/O Line 13

IN5 Line of GPTA0

IN5 Line of GPTA1

IN5 Line of LTCA2

OUT5 Line of GPTA0

OUT5 Line of GPTA1

OUT5 Line of LTCA2

A1/

IN5

OUT5

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

F13

P2.14

IN6

I/O

A1/

Port 2 General Purpose I/O Line 14

IN6 Line of GPTA0

IN6 Line of GPTA1

IN6 Line of LTCA2

CCU60

IN6

CCPOS0A

T12HRB

T3INA

T3INB

OUT6

P2.15

IN7

CCU61

GPT120

GPT121

I/O

OUT6 Line of GPTA0

OUT6 Line of GPTA1

OUT6 Line of LTCA2

Port 2 General Purpose I/O Line 15

IN7 Line of GPTA0

IN7 Line of GPTA1

IN7 Line of LTCA2

OUT7 Line of GPTA0

OUT7 Line of GPTA1

OUT7 Line of LTCA2

A1/

IN7

OUT7

Port 3

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

K19

P3.0

I/O

A1/

Port 3 General Purpose I/O Line 0

IN8 Line of GPTA0

IN8 Line of GPTA1

IN8 Line of LTCA2

CCU62

IN8

CTRAPA

CTRPAB

CC60INC

T12HRE

CC61INC

T5INA

T5INB

OUT8

P3.1

CCU61

CCU63

GPT120

GPT121

I/O

OUT8 Line of GPTA0

OUT8 Line of GPTA1

OUT8 Line of LTCA2

Port 3 General Purpose I/O Line 1

IN9 Line of GPTA0

IN9 Line of GPTA1

IN9 Line of LTCA2

OUT9 Line of GPTA0

OUT9 Line of GPTA1

OUT9 Line of LTCA2

B22

A1/

IN9

OUT9

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

A22

P3.2

I/O

A1/

Port 3 General Purpose I/O Line 2

IN10 Line of GPTA0

IN10 Line of GPTA1

IN10 Line of LTCA2

IN10

T13HRE

OUT10

P3.3

CCU63

I/O

OUT10 Line of GPTA0

OUT10 Line of GPTA1

OUT10 Line of LTCA2

Port 3 General Purpose I/O Line 3

IN11 Line of GPTA0

IN11 Line of GPTA1

IN11 Line of LTCA2

B21

A1/

IN11

OUT11

OUT11 Line of GPTA0

OUT11 Line of GPTA1

OUT11 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

K18

P3.4

I/O

A1/

Port 3 General Purpose I/O Line 4

IN12 Line of GPTA0

IN12 Line of GPTA1

IN12 Line of LTCA2

CCU62

IN12

T12HRE

CC61INC

CTRAPA

CTRAPB

CC60INC

OUT12

P3.5

CCU62

CCU63

CCU60

CCU63

I/O

OUT12 Line of GPTA0

OUT12 Line of GPTA1

OUT12 Line of LTCA2

Port 3 General Purpose I/O Line 5

IN13 Line of GPTA0

IN13 Line of GPTA1

IN13 Line of LTCA2

OUT13 Line of GPTA0

OUT13 Line of GPTA1

OUT13 Line of LTCA2

A21

A1/

IN13

OUT13

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

B20

P3.6

I/O

A1/

Port 3 General Purpose I/O Line 6

IN14 Line of GPTA0

IN14 Line of GPTA1

IN14 Line of LTCA2

CCU62

IN14

T13HRE

T6EUDB

T6EUDA

OUT14

P3.7

GPT120

GPT121

I/O

OUT14 Line of GPTA0

OUT14 Line of GPTA1

OUT14 Line of LTCA2

Port 3 General Purpose I/O Line 7

IN15 Line of GPTA0

IN15 Line of GPTA1

IN15 Line of LTCA2

OUT15 Line of GPTA0

OUT15 Line of GPTA1

OUT15 Line of LTCA2

Port 3 General Purpose I/O Line 8

IN16 Line of GPTA0

IN16 Line of GPTA1

IN16 Line of LTCA2

CCU61

A20

A1/

IN15

OUT15

P3.8

I/O

B19

A1/

IN16

T13HRE

OUT16

OUT16 Line of GPTA0

OUT16 Line of GPTA1

OUT16 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

A19

P3.9

I/O

A1/

Port 3 General Purpose I/O Line 9

IN17 Line of GPTA0

IN17

IN17 Line of GPTA1

IN17

IN17 Line of LTCA2

OUT17

P3.10

IN18

I/O

OUT17 Line of GPTA0

OUT17 Line of GPTA1

OUT17 Line of LTCA2

J18

A1+/ Port 3 General Purpose I/O Line 10

IN18 Line of GPTA0

IN18

IN18 Line of GPTA1

IN18 Line of LTCA2

CCU62

IN18

CCPOS1A

T13HRB

T3EUDB

T3EUDA

OUT18

P3.11

IN19

CCU63

GPT120

GPT121

I/O

OUT18 Line of GPTA0

OUT18 Line of GPTA1

OUT18 Line of LTCA2

B18

A1/

Port 3 General Purpose I/O Line 11

IN19 Line of GPTA0

IN19

IN19 Line of GPTA1

IN19

IN19 Line of LTCA2

OUT19

OUT19 Line of GPTA0

OUT19 Line of GPTA1

OUT19 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

K17

P3.12

I/O

A1/

Port 3 General Purpose I/O Line 12

IN20 Line of GPTA0

IN20 Line of GPTA1

IN20 Line of LTCA2

CCU62

IN20

CCPOS2A

T12HRC

T13HRC

T4INB

T4INA

OUT20

P3.13

CCU63

GPT120

GPT121

I/O

OUT20 Line of GPTA0

OUT20 Line of GPTA1

OUT20 Line of LTCA2

Port 3 General Purpose I/O Line 13

IN21 Line of GPTA0

IN21 Line of GPTA1

IN21 Line of LTCA2

OUT21 Line of GPTA0

OUT21 Line of GPTA1

OUT21 Line of LTCA2

A18

A1/

IN21

OUT21

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

B13

P3.14

IN22

I/O

A1/

Port 3 General Purpose I/O Line 14

IN22 Line of GPTA0

IN22

IN22 Line of GPTA1

IN22

IN22 Line of LTCA2

T13HRE

OUT22

P3.15

IN23

CCU63

I/O

OUT22 Line of GPTA0

OUT22 Line of GPTA1

OUT22 Line of LTCA2

Port 3 General Purpose I/O Line 15

IN23 Line of GPTA0

A13

A1/

IN23

IN23 Line of GPTA1

IN23

IN23 Line of LTCA2

OUT23

OUT23 Line of GPTA0

OUT23 Line of GPTA1

OUT23 Line of LTCA2

Port 4

AA17 P4.0

IN24

I/O

A1+/ Port 4 General Purpose I/O Line 0

IN24 Line of GPTA0

IN24

IN24 Line of GPTA1

IN24

IN24 Line of LTCA2

MRST2A

SSC2 Master Receive Input A (Master Mode)

OUT24 Line of GPTA0

OUT24

MRST2

OUT24 Line of GPTA1

SSC2 Slave Transmit Output (Slave Mode)

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AB17 P4.1

IN25

I/O

A1+/ Port 4 General Purpose I/O Line 1

IN25 Line of GPTA0

IN25

IN25 Line of GPTA1

IN25

IN25 Line of LTCA2

MTSR2A

SSC2 Slave Receive Input A (Slave Mode)

MRSTG2A

SSC Guardian 2 Master Receive Input A

(Master Mode)

OUT25

MTSR2

OUT25 Line of GPTA0

OUT25 Line of GPTA1

SSC2 Master Transmit Output (Master

Mode)³⁾

AD17 P4.2

I/O

A1+/ Port 4 General Purpose I/O Line 2

IN26

IN26 Line of GPTA0

IN26

IN26 Line of GPTA1

IN26 Line of LTCA2

IN26

SCLK2

OUT26

SCLK2

SSC2 Input

I/O

OUT26 Line of GPTA0

OUT26 Line of GPTA1

SSC2 Output

AE17 P4.3

A1+/ Port 4 General Purpose I/O Line 3

IN27

IN27 Line of GPTA0

IN27

IN27 Line of GPTA1

IN27 Line of LTCA2

OUT27 Line of GPTA0

OUT27 Line of GPTA1

SSC2 Output

IN27

OUT27

SLSO20

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AA18 P4.4

IN28

I/O

A1+/ Port 4 General Purpose I/O Line 4

IN28 Line of GPTA0

IN28 Line of GPTA1

IN28 Line of LTCA2

OUT28 Line of GPTA0

OUT28 Line of GPTA1

SSC2 Output

IN28

OUT28

I/O

OUT28

SLSO21

AB18 P4.5

A1+/ Port 4 General Purpose I/O Line 5

IN29

IN29 Line of GPTA0

IN29

IN29 Line of GPTA1

IN29 Line of LTCA2

IN29

OUT29

SLSO22

I/O

OUT29 Line of GPTA0

OUT29 Line of GPTA1

SSC2 Output

AD18 P4.6

A1+/ Port 4 General Purpose I/O Line 6

IN30

IN30 Line of GPTA0

IN30

IN30 Line of GPTA1

IN30 Line of LTCA2

OUT30 Line of GPTA0

OUT30 Line of GPTA1

SSC2 Output

IN30

OUT30

SLSO23

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AE18 P4.7

IN31

I/O

A1+/ Port 4 General Purpose I/O Line 7

IN31 Line of GPTA0

IN31 Line of GPTA1

IN31Line of LTCA2

GPT120

IN31

T6INB

T6INA

GPT121

OUT31

SLSO24

I/O

OUT31 Line of GPTA0

OUT31 Line of GPTA1

SSC2 Output

AA19 P4.8

A1/

Port 4 General Purpose I/O Line 8

IN32 Line of GPTA0

IN32 Line of GPTA1

CCU60

IN32

CCPOS1A

T13HRB

T3EUDA

T3EUDB

OUT32

OUT0

CCU61

GPT120

GPT121

OUT32 Line of GPTA0

OUT32 Line of GPTA1

OUT0 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AB19 P4.9

IN33

I/O

A1/

Port 4 General Purpose I/O Line 9

IN33 Line of GPTA0

IN33 Line of GPTA1

CCU60

IN33

CCPOS2A

T12HRC

T13HRC

T4INA

CCU61

GPT120

T4INB

GPT121

SLSI2

SSC2

OUT33

OUT1

I/O

OUT33 Line of GPTA0

OUT33 Line of GPTA1

OUT1 Line of LTCA2

Port 4 General Purpose I/O Line 10

IN34 Line of GPTA0

IN34 Line of GPTA1

CCU60

AD19 P4.10

A1/

IN34

T12HRB

CCPOS0A

T2INA

T2INB

OUT34

OUT2

CCU61

GPT120

GPT121

OUT34 Line of GPTA0

OUT34 Line of GPTA1

OUT2 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AJ13

P4.11

IN35

I/O

A1/

Port 4 General Purpose I/O Line 11

IN35 Line of GPTA0

IN35 Line of GPTA1

OUT35 Line of GPTA0

OUT35 Line of GPTA1

OUT3 Line of LTCA2

Port 4 General Purpose I/O Line 12

IN36 Line of GPTA0

IN36 Line of GPTA1

CCU60

IN35

OUT35

OUT3

I/O

AA20 P4.12

IN36

A1/

IN36

T13HRB

CCPOS1A

T2EUDA

T2EUDB

OUT36

OUT4

CCU61

GPT120

GPT121

I/O

OUT36 Line of GPTA0

OUT36 Line of GPTA1

OUT4 Line of LTCA2

Port 4 General Purpose I/O Line 13

IN37 Line of GPTA0

IN37 Line of GPTA1

OUT37 Line of GPTA0

OUT37 Line of GPTA1

OUT5 Line of LTCA2

AJ14

P4.13

A1/

IN37

OUT37

OUT5

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AB20 P4.14

IN38

I/O

A1/

Port 4 General Purpose I/O Line 14

IN38 Line of GPTA0

IN38 Line of GPTA1

CCU60

IN38

T12HRC

T13HRC

CCPOS2A

T4EUDA

T4EUDB

OUT38

CCU60

CCU61

GPT120

GPT121

I/O

OUT38 Line of GPTA0

OUT38 Line of GPTA1

OUT6 Line of LTCA2

Port 4 General Purpose I/O Line 15

IN39 Line of GPTA0

IN39 Line of GPTA1

OUT39 Line of GPTA0

OUT39 Line of GPTA1

OUT7 Line of LTCA2

OUT38

OUT6

AK14 P4.15

A1/

IN39

OUT39

OUT7

Port 5

F20

P5.0

I/O

A1+/ Port 5 General Purpose I/O Line 0

RXD0A

T6EUDA

T6EUDB

RXD0A

OUT72

ASC0 Receiver Input/Output A

GPT120

GPT121

ASC0 Receiver Input/Output A

OUT72 Line of GPTA0

OUT72 Line of GPTA1

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

F19

P5.1

I/O

A1+/ Port 5 General Purpose I/O Line 1

TXD0

ASC0 Transmitter Output A

OUT73 Line of GPTA0

OUT73

P5.2

OUT73 Line of GPTA1

J20

A2/

Port 5 General Purpose I/O Line 2

ASC1 Receiver Input/Output A

OUT74 Line of GPTA0

RXD1A

OUT74

P5.3

I/O

OUT74 Line of GPTA1

G20

F23

A1+/ Port 5 General Purpose I/O Line 3

TXD1

ASC1 Transmitter Output A

OUT75

P5.4

OUT75 Line of GPTA0

OUT75 Line of GPTA1

A2/

Port 5 General Purpose I/O Line 4

T13HRB

CCPOS1A

T2EUDB

T2EUDA

EN00

CCU62

CCU63

GPT120

GPT121

MSC0 Device Select Output 0

MLI0 Receive Channel ready Output B

OUT76 Line of GPTA0

RREADY0B O2

OUT76 O3

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

K20

P5.5

I/O

A1+/ Port 5 General Purpose I/O Line 5

SDI0

MSC0 Serial Data Input

T12HRC

T13HRC

CCPOS2A

T4EUDB

T4EUDA

OUT77

OUT101

P5.6

CCU62

CCU63

GPT120

GPT121

I/O

OUT77 Line of GPTA0

OUT77 Line of GPTA1

OUT101 Line of LTCA2

Port 5 General Purpose I/O Line 6

CCU62

G25

A2/

CC60INA

CC60INB

EN10

CCU63

I/O

MSC1 Device Select Output 0

MLI0 transmit Channel valid Output B

CCU62

TVALID0B

CC60

J21

P5.7

A1+/ Port 5 General Purpose I/O Line 7

SDI1

MSC1 Serial Data Input

CC61INA

CC61INB

OUT79

CC61

CCU62

CCU63

OUT79 Line of GPTA0

OUT79 Line of GPTA1

CCU62

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

G21

P5.8

I/O

Port 5 General Purpose I/O Line 8

CC62INA

CC62INB

SON0

CCU62

CCU63

MSC0 Differential Driver Serial Data Output

Negative

OUT80

CC62

P5.9

I/O

OUT80 Line of GPTA0

CCU62

G22

F21

F22

J19

Port 5 General Purpose I/O Line 9

SOP0A

MSC0 Differential Driver Serial Data Output

Positive A

OUT81

COUT60

P5.10

I/O

OUT81 Line of GPTA0

CCU62

Port 5 General Purpose I/O Line 10

FCLN0

MSC0 Differential Driver Clock Output

Negative

OUT82

COUT61

P5.11

I/O

OUT82 Line of GPTA0

CCU62

Port 5 General Purpose I/O Line 11

FCLP0A

MSC0 Differential Driver Clock Output

Positive A

OUT83

COUT62

P5.12

I/O

OUT83 Line of GPTA0

CCU62

Port 5 General Purpose I/O Line 12

SON1

MSC1 Differential Driver Serial Data Output

Negative

OUT84

OUT84 Line of GPTA0

OUT84 Line of GPTA1

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

G19

P5.13

I/O

Port 5 General Purpose I/O Line 13

SOP1A

MSC1 Differential Driver Serial Data Output

Positive A

OUT85

P5.14

I/O

OUT85 Line of GPTA0

OUT85 Line of GPTA1

G18

F18

Port 5 General Purpose I/O Line 14

FCLN1

MSC1 Differential Driver Clock Output

Negative

OUT86

P5.15

I/O

OUT86 Line of GPTA0

OUT86 Line of GPTA1

Port 5 General Purpose I/O Line 15

FCLNP1A

MSC1 Differential Driver Clock Output

Positive A

OUT87

OUT87 Line of GPTA0

OUT87 Line of GPTA1

Port 6

P6.4

I/O

A1+/ Port 6 General Purpose I/O Line 4

MTSR1

MRSTG1

SSC1 Slave Receive Input (Slave Mode)

SSC Guardian 1 Master Receive Input

(Master Mode)

MTSR1

SSC1 Master Transmit Output (Master

Mode)³⁾

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P6.5

I/O

A1+/ Port 6 General Purpose I/O Line 5

MRST1

Reserved

P6.6

SSC1 Master Receive Input (Master Mode)

I/O

SSC1 Slave Transmit Output (Slave Mode)

A1+/ Port 6 General Purpose I/O Line 6

SCLK1

Reserved

P6.7

SSC1 Clock Input/Output

I/O

SSC1 Clock Input/Output

J10

A1+/ Port 6 General Purpose I/O Line 7

SLSI1

SSC1 slave Select Input

T6OFL

Reserved

P6.8

I/O

GPT120

G10

A2/

Port 6 General Purpose I/O Line 8

RXDCAN0

CAN Node 0 Receiver Input 0

CAN Node 3 Receiver Input 1

RXD0B

ASC0 Receiver Input/Output B

CAPINB

CAPINA

Reserved

RXD0B

GPT120

GPT121

ASC0 Receiver Input/Output B

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

F10

P6.9

I/O

A2/

Port 6 General Purpose I/O Line 9

CAN Node 0 Transmitter Output

ASC0 Transmitter Output B

GPT120

TXDCAN0

TXD0

T60FL

P6.10

A2/

Port 6 General Purpose I/O Line 10

RXDCAN1

CAN Node 1 Receiver Input 0

CAN Node 0 Receiver Input 1

RXD1B

Reserved

RXD1B

TXENA

ASC1 Receiver Input/Output B

E-Ray Channel A transmit Data Output

enable ²⁾

P6.11

I/O

A2/

Port 6 General Purpose I/O Line 11

CAN Node 1 Transmitter Output

ASC1 Transmitter Output B

TXDCAN1

TXD1

TXENB

E-Ray Channel B transmit Data Output

enable ²⁾

P6.12

I/O

A1/

Port 6 General Purpose I/O Line 12

RXDCAN2

CAN Node 2 Receiver Input 0

CAN Node 1 Receiver Input 1

RXDA1

E-Ray Channel A Receive Data Input 1 ²⁾

Reserved

COUT61

CCU60

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P6.13

I/O

A2/

Port 6 General Purpose I/O Line 13

CAN Node 2 Transmitter Output

E-Ray Channel A transmit Data Output ²⁾

CCU60

TXDCAN2

TXDA

COUT62

P6.14

A1/

Port 6 General Purpose I/O Line 14

RXDCAN3

CAN Node 3 Receiver Input 0

CAN Node 2 Receiver Input 1

RXDB1

E-Ray Channel B Receive Data Input 1 ²⁾

Reserved

COUT63

P6.15

I/O

CCU60

A2/

Port 6 General Purpose I/O Line 15

CC60INB

CC60INA

TXDCAN3

TXDB

CCU60

CCU61

CAN Node 3 Transmitter Output

E-Ray Channel B transmit Data Output ²⁾

CCU61

CC60

Port 7

N10

P7.0

I/O

A1+/ Port 7 General Purpose I/O Line 0

MRST3

REQ4

SSC3 Master Receive Input (Master Mode)

External trigger Input 4

AD2EMUX2 O1

ADC2 external multiplexer Control Output 2

SSC3 Slave Transmit Output (Slave Mode)

MRST3

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P7.1

I/O

A1+/ Port 7 General Purpose I/O Line 1

REQ5

External trigger Input 5

MTSR3

MRSTG3B

SSC3 Slave Receive Input (Master Mode)

SSC Guardian 3 Master Receive Input B

(Master Mode)

AD0EMUX2 O1

ADC0 external multiplexer Control Output 2

MTSR3

SSC3 Master Transmit Output (Master

Mode)³⁾

Reserved

P7.2

I/O

A1+/ Port 7 General Purpose I/O Line 2

SCLK3

SSC3 Input

AD0EMUX0 O1

ADC0 external multiplexer Control Output 0

SCLK3

Reserved

P7.3

I/O

SSC3 Output

A1+/ Port 7 General Purpose I/O Line 3

AD0EMUX1 O1

ADC0 external multiplexer Control Output 1

SLSO30

Reserved

P7.4

I/O

SSC3 Output

P10

A1+/ Port 7 General Purpose I/O Line 4

REQ6

External trigger Input 6

AD2EMUX0 O1

ADC2 external multiplexer Control Output 0

SLSO31

SSC3 Output

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P7.5

I/O

A1+/ Port 7 General Purpose I/O Line 5

REQ7

External trigger Input 7

AD2EMUX1 O1

ADC2 external multiplexer Control Output 1

SLSO32

Reserved

P7.6

I/O

SSC3 Output

A1+/ Port 7 General Purpose I/O Line 6

AD1EMUX0 O1

ADC1 external multiplexer Control Output 0

SLSO33

Reserved

P7.7

I/O

SSC3 Output

A1+/ Port 7 General Purpose I/O Line 7

AD1EMUX1 O1

ADC1 external multiplexer Control Output 1

SLSO34

SSC3 Output

Reserved

Port 8

P8.0

I/O

A2/

Port 8 General Purpose I/O Line 0

IN40 Line of GPTA0

IN40

IN40 Line of GPTA1

SENT0

OUT40

COUT62

TCLK1

SENT Digital Input

OUT40 Line of GPTA0

CCU61

MLI1 transmit Channel Clock Output

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

K11

P8.1

I/O

A1/

Port 8 General Purpose I/O Line 1

IN41 Line of GPTA0

IN41 Line of GPTA1

MLI1 transmit Channel ready Input A

SENT Digital Input

CCU60

IN41

TREADY1A

SENT1

CC61INA

CC61INB

OUT41

CC61

CCU61

I/O

OUT41 Line of GPTA0

CCU60

SENT1

P8.2

SENT Digital Output

Port 8 General Purpose I/O Line 2

IN42 Line of GPTA0

IN42 Line of GPTA1

SENT Digital Input

GPT120

A2/

IN42

SENT2

CAPINA

CAPINB

COUT63

OUT42

TVALID1A

GPT121

CCU61

OUT42 Line of GPTA1

MLI1 transmit Channel valid Output A

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P8.3

I/O

A2/

Port 8 General Purpose I/O Line 3

IN43 Line of GPTA0

IN43 Line of GPTA1

SENT Digital Input

CCU60

IN43

SENT3

CC62INA

CC62INB

OUT43

CC62

CCU61

I/O

OUT43 Line of GPTA0

CCU60

TDATA1

P8.4

MLI1 transmit Channel Data Output A

Port 8 General Purpose I/O Line 4

IN44 Line of GPTA0

IN44 Line of GPTA1

MLI1 Receive Channel Clock Input A

SENT Digital Input

CCU60

A1/

IN44

RCLK1A

SENT4

CC62INB

CC62INA

OUT44

CC62

CCU61

OUT44 Line of GPTA0

CCU61

T3OUT

GPT121

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

L10

P8.5

I/O

A2/

Port 8 General Purpose I/O Line 5

IN45 Line of GPTA0

IN45 Line of GPTA1

SENT Digital Input

CCU60

IN45

SENT5

CTRAPA

CTRAPB

CC60INC

T12HRE

CC61INC

OUT45

CCU62

CCU60

CCU61

OUT45 Line of GPTA0

OUT45 Line of GPTA1

MLI1 Receive Channel ready Output A

Port 8 General Purpose I/O Line 6

IN46 Line of GPTA0

IN46 Line of GPTA1

MLI1 Receive Channel valid Input A

SENT Digital Input

OUT46 Line of GPTA0

CCU61

RREADY1A O3

P8.6

I/O

A1/

IN46

RVALID1A

SENT6

OUT46

COUT60

T6OUT

GPT120

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P8.7

I/O

A1/

Port 8 General Purpose I/O Line 7

IN47 Line of GPTA0

IN47 Line of GPTA1

MLI1 Receive Channel Data Input A

SENT Digital Input

IN47

RDATA1A

SENT7

OUT47

COUT61

T6OUT

OUT47 Line of GPTA0

CCU61

GPT121

Port 9

K22

P9.0

I/O

A2/

Port 9 General Purpose I/O Line 0

IN48 Line of GPTA0

IN48 Line of GPTA1

CCU62

IN48

COUT63

OUT48

EN12

I/O

OUT48 Line of GPTA1

MSC1 Device Select Output 2

Port 9 General Purpose I/O Line 1

IN49 Line of GPTA0

IN49 Line of GPTA1

CCU62

J24

P9.1

A2/

IN49

CC60INB

CC60INA

CC60

OUT49

EN11

CCU63

OUT49 Line of GPTA1

MSC1 Device Select Output 1

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

J25

P9.2

I/O

A2/

Port 9 General Purpose I/O Line 2

IN50 Line of GPTA0

IN50 Line of GPTA1

CCU62

IN50

CC61INB

CC61INA

CC61

CCU63

I/O

CCU63

OUT50

SOP1B

P9.3

OUT50 Line of GPTA1

MSC1 serial Data Output

Port 9 General Purpose I/O Line 3

IN51 Line of GPTA0

IN51 Line of GPTA1

CCU62

H25

A2/

IN51

CC62INB

CC62INA

CC62

CCU63

I/O

CCU63

OUT51

FCLP1B

P9.4

OUT51 Line of GPTA1

MSC1 Clock Output

Port 9 General Purpose I/O Line 4

IN52 Line of GPTA0

IN52 Line of GPTA1

CCU63

H24

A2/

IN52

COUT60

OUT52

EN03

OUT52 Line of GPTA1

MSC0 Device Select Output 3

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

L22

P9.5

I/O

A2/

Port 9 General Purpose I/O Line 5

IN53 Line of GPTA0

IN53

IN53 Line of GPTA1

SENT1

COUT61

OUT53

EN02

SENT Digital Input

I/O

CCU63

OUT53 Line of GPTA1

MSC0 Device Select Output 2

Port 9 General Purpose I/O Line 6

IN54 Line of GPTA0

L21

K25

K24

P9.6

A2/

IN54

IN54 Line of GPTA1

SENT3

OUT54

SENT3

EN01

SENT Digital Input

I/O

OUT54 Line of GPTA0

SENT Digital Output

MSC0 Device Select Output 1

Port 9 General Purpose I/O Line 7

IN55 Line of GPTA0

P9.7

A2/

IN55

IN55 Line of GPTA1

SENT4

OUT55

SENT4

SOP0B

P9.8

SENT Digital Input

I/O

OUT55 Line of GPTA0

SENT Digital Output

MSC0 serial Data Output

Port 9 General Purpose I/O Line 8

SENT Digital Input

A2/

SENT6

COUT62

SENT6

FCLP0B

CCU63

SENT Digital Output

MSC0 Clock Output

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

A28

P9.9

I/O

A1/

Port 9 General Purpose I/O Line 9

SENT0

SENT Digital Input

Reserved

SENT0

I/O

SENT Digital Output

Reserved

P9.10

L25

A1/

Port 9 General Purpose I/O Line 10

EMGSTOP

SENT7

Emergency Stop

SENT Digital Input

COUT63

SENT7

I/O

CCU63

SENT Digital Output

Reserved

P9.11

A27

B27

A1/

Port 9 General Purpose I/O Line 11

SENT2

SENT Digital Input

Reserved

SENT2

I/O

SENT Digital Output

Reserved

P9.12

A1/

Port 9 General Purpose I/O Line 12

SENT5

SENT Digital Input

Reserved

SENT5

SENT Digital Output

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

M21

P9.13

I/O

A2/

Port 9 General Purpose I/O Line 13

BRKIN

OCDS Break Input

ECTT1

TTCAN Input

Reserved

BRKOUT

P9.14

OCDS Break Output

N21

I/O

A2/

Port 9 General Purpose I/O Line 14

BRKIN

OCDS Break Input

ECTT2

TTCAN Input

REQ15

External trigger Input 15

Reserved

BRKOUT

OCDS Break Output

Port 10

AE20 P10.0

MRST0

I/O

A2/

Port 10 General Purpose I/O Line 0

SSC0 Master Receive Input (Master Mode)

MRST0

SSC0 Slave Transmit Output (Slave Mode)

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AD20 P10.1

MTSR0

I/O

A2/

Port 10 General Purpose I/O Line 1

SSC0 Slave Receive Input (Slave Mode)

MRSTG0

SSC Guardian 0 Master Receive Input

(Master Mode)

MTSR0

SSC0 Master Transmit Output (Master

Mode)³⁾

Reserved

AB21 P10.2

SLSI0

I/O

A1/

Port 10 General Purpose I/O Line 2

SSC0 Slave Select Input

Reserved

AE19 P10.3

SCLK0

I/O

A2/

Port 10 General Purpose I/O Line 3

SSC0 Clock Input/Output

SCLK0

I/O

SSC0 Clock Input/Output

Reserved

AD21 P10.4

SLSO0

A1+/ Port 10 General Purpose I/O Line 4

SSC0 Slave Select Output Line 0

Reserved

AE21 P10.5

SLSO1

A1+/ Port 10 General Purpose I/O Line 5

SSC0 Slave Select Output Line 1

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

Port 11

E30

P11.0

I/O

Port 11 General Purpose I/O Line 0

Reserved

EBU Address Bus Line 0

E29

F30

F29

G30

P11.1

I/O

Port 11 General Purpose I/O Line 1

Reserved

EBU Address Bus Line 1

P11.2

I/O

Port 11 General Purpose I/O Line 2

Reserved

EBU Address Bus Line 2

P11.3

I/O

Port 11 General Purpose I/O Line 3

Reserved

EBU Address Bus Line 3

P11.4

I/O

Port 11 General Purpose I/O Line 4

Reserved

EBU Address Bus Line 4

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

G29

P11.5

I/O

Port 11 General Purpose I/O Line 5

Reserved

EBU Address Bus Line 5

H30

H29

J30

J29

P11.6

I/O

Port 11 General Purpose I/O Line 6

Reserved

EBU Address Bus Line 6

P11.7

I/O

Port 11 General Purpose I/O Line 7

Reserved

EBU Address Bus Line 7

P11.8

I/O

Port 11 General Purpose I/O Line 8

Reserved

EBU Address Bus Line 8

P11.9

I/O

Port 11 General Purpose I/O Line 9

Reserved

EBU Address Bus Line 9

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

K30

P11.10

I/O

Port 11 General Purpose I/O Line 10

Reserved

A10

EBU Address Bus Line 10

K29

L30

L29

M30

P11.11

I/O

Port 11 General Purpose I/O Line 11

Reserved

A11

EBU Address Bus Line 11

P11.12

I/O

Port 11 General Purpose I/O Line 12

Reserved

A12

EBU Address Bus Line 12

P11.13

I/O

Port 11 General Purpose I/O Line 13

Reserved

A13

EBU Address Bus Line 13

P11.14

I/O

Port 11 General Purpose I/O Line 14

Reserved

A14

EBU Address Bus Line 14

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

M29

P11.15

I/O

Port 11 General Purpose I/O Line 15

Reserved

A15

EBU Address Bus Line 15

Port 12

N30

P12.0

I/O

Port 12 General Purpose I/O Line 0

Reserved

A16

EBU Address Bus Line 16

N29

P30

P29

P12.1

I/O

Port 12 General Purpose I/O Line 1

Reserved

A17

EBU Address Bus Line 17

P12.2

I/O

Port 12 General Purpose I/O Line 2

Reserved

A18

EBU Address Bus Line 18

P12.3

I/O

Port 12 General Purpose I/O Line 3

Reserved

A19

EBU Address Bus Line 19

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

V30

P12.4

I/O

Port 12 General Purpose I/O Line 4

Reserved

A20

EBU Address Bus Line 20

V29

P12.5

I/O

Port 12 General Purpose I/O Line 5

Reserved

A21

EBU Address Bus Line 21

D30

P12.6

I/O

Port 12 General Purpose I/O Line 6

Reserved

A22

EBU Address Bus Line 22

D29

P12.7

I/O

Port 12 General Purpose I/O Line 7

Reserved

A23

EBU Address Bus Line 23

Port 13

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

U21

P13.0

AD0

I/O

Port 13 General Purpose I/O Line 0

EBU Address/Data Bus Line 0

OUT88 Line of GPTA0

OUT88

OUT80

AD0

OUT88 Line of GPTA1

OUT80 Line of LTCA2

EBU Address/Data Bus Line 0

Port 13 General Purpose I/O Line 1

EBU Address/Data Bus Line 1

OUT89 Line of GPTA0

U22

V21

V22

P13.1

AD1

I/O

OUT89

OUT81

AD1

OUT89 Line of GPTA1

OUT81 Line of LTCA2

EBU Address/Data Bus Line 1

Port 13 General Purpose I/O Line 2

EBU Address/Data Bus Line 2

OUT90 Line of GPTA0

P13.2

AD2

I/O

OUT90

OUT82

AD2

OUT90 Line of GPTA1

OUT82 Line of LTCA2

EBU Address/Data Bus Line 2

Port 13 General Purpose I/O Line 3

EBU Address/Data Bus Line 3

OUT91 Line of GPTA0

P13.3

AD3

I/O

OUT91

OUT83

AD3

OUT91 Line of GPTA1

OUT83 Line of LTCA2

EBU Address/Data Bus Line 3

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

V24

P13.4

AD4

I/O

Port 13 General Purpose I/O Line 4

EBU Address/Data Bus Line 4

OUT92 Line of GPTA0

OUT92

OUT84

AD4

OUT92 Line of GPTA1

OUT84 Line of LTCA2

EBU Address/Data Bus Line 4

Port 13 General Purpose I/O Line 5

EBU Address/Data Bus Line 5

OUT93 Line of GPTA0

V25

P13.5

AD5

I/O

OUT93

OUT85

AD5

OUT93 Line of GPTA1

OUT85 Line of LTCA2

EBU Address/Data Bus Line 5

Port 13 General Purpose I/O Line 6

EBU Address/Data Bus Line 6

OUT94 Line of GPTA0

W21

P13.6

AD6

I/O

OUT94

OUT86

AD6

OUT94 Line of GPTA1

OUT86 Line of LTCA2

EBU Address/Data Bus Line 6

Port 13 General Purpose I/O Line 7

EBU Address/Data Bus Line 7

OUT95 Line of GPTA0

W22

P13.7

AD7

I/O

OUT95

OUT87

AD7

OUT95 Line of GPTA1

OUT87 Line of LTCA2

EBU Address/Data Bus Line 7

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

W24

P13.8

AD8

I/O

Port 13 General Purpose I/O Line 8

EBU Address/Data Bus Line 8

OUT96 Line of GPTA0

OUT96

OUT88

AD8

OUT96 Line of GPTA1

OUT88 Line of LTCA2

EBU Address/Data Bus Line 8

Port 13 General Purpose I/O Line 9

EBU Address/Data Bus Line 9

OUT97 Line of GPTA0

W25

Y22

Y24

P13.9

AD9

I/O

OUT97

OUT89

AD9

OUT97 Line of GPTA1

OUT89 Line of LTCA2

EBU Address/Data Bus Line 9

Port 13 General Purpose I/O Line 10

EBU Address/Data Bus Line 10

OUT98 Line of GPTA0

P13.10

AD10

I/O

OUT98

OUT90

AD10

OUT98 Line of GPTA1

OUT90 Line of LTCA2

EBU Address/Data Bus Line 10

Port 13 General Purpose I/O Line 11

EBU Address/Data Bus Line 11

OUT99 Line of GPTA0

P13.11

AD11

I/O

OUT99

OUT91

AD11

OUT99 Line of GPTA1

OUT91 Line of LTCA2

EBU Address/Data Bus Line 11

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

Y25

P13.12

AD12

I/O

Port 13 General Purpose I/O Line 12

EBU Address/Data Bus Line 12

OUT100 Line of GPTA0

OUT100

OUT92

AD12

OUT100 Line of GPTA1

OUT92 Line of LTCA2

EBU Address/Data Bus Line 12

Port 13 General Purpose I/O Line 13

EBU Address/Data Bus Line 13

OUT101 Line of GPTA0

AA24 P13.13

AD13

I/O

OUT101

OUT93

OUT101 Line of GPTA1

OUT93 Line of LTCA2

AD13

EBU Address/Data Bus Line 13

Port 13 General Purpose I/O Line 14

EBU Address/Data Bus Line 14

OUT102 Line of GPTA0

AA25 P13.14

AD14

I/O

OUT102

OUT94

OUT102 Line of GPTA1

OUT94 Line of LTCA2

AD14

EBU Address/Data Bus Line 14

Port 13 General Purpose I/O Line 15

EBU Address/Data Bus Line 15

OUT103 Line of GPTA0

AB24 P13.15

AD15

I/O

OUT103

OUT95

OUT103 Line of GPTA1

OUT95 Line of LTCA2

AD15

EBU Address/Data Bus Line 15

Port 14

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AB25 P14.0

AD16

I/O

Port 14 General Purpose I/O Line 0

EBU Address/Data Bus Line 16

CCU60

CC60

OUT96

AD16

OUT96 Line of GPTA1

OUT96 Line of LTCA2

EBU Address/Data Bus Line 16

Port 14 General Purpose I/O Line 1

EBU Address/Data Bus Line 17

CCU60

W30

P14.1

AD17

I/O

CC61

OUT97

AD17

OUT97 Line of GPTA1

OUT97 Line of LTCA2

EBU Address/Data Bus Line 17

Port 14 General Purpose I/O Line 2

EBU Address/Data Bus Line 18

CCU60

AC25 P14.2

AD18

I/O

CC62

OUT98

AD18

OUT98 Line of GPTA1

OUT98 Line of LTCA2

EBU Address/Data Bus Line 18

Port 14 General Purpose I/O Line 3

EBU Address/Data Bus Line 19

CCU60

Y30

P14.3

I/O

AD19

COUT60

OUT99

AD19

OUT99 Line of GPTA1

OUT99 Line of LTCA2

EBU Address/Data Bus Line 19

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AD23 P14.4

AD20

I/O

Port 14 General Purpose I/O Line 4

EBU Address/Data Bus Line 20

CCU60

COUT61

OUT100

AD20

OUT100 Line of GPTA1

OUT100 Line of LTCA2

EBU Address/Data Bus Line 20

Port 14 General Purpose I/O Line 5

EBU Address/Data Bus Line 21

CCU60

AA30 P14.5

I/O

AD21

COUT62

OUT101

AD21

OUT101 Line of GPTA1

OUT101 Line of LTCA2

EBU Address/Data Bus Line 21

Port 14 General Purpose I/O Line 6

EBU Address/Data Bus Line 22

CCU60

AE24 P14.6

I/O

AD22

COUT63

OUT102

AD22

OUT102 Line of GPTA1

OUT102 Line of LTCA2

EBU Address/Data Bus Line 22

Port 14 General Purpose I/O Line 7

EBU Address/Data Bus Line 23

CCU61

AB30 P14.7

I/O

AD23

CC60

OUT103

AD23

OUT103 Line of GPTA1

OUT103 Line of LTCA2

EBU Address/Data Bus Line 23

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AE23 P14.8

AD24

I/O

Port 14 General Purpose I/O Line 8

EBU Address/Data Bus Line 24

CCU61

CC61

T3OUT

OUT104

AD24

GPT120

OUT104 Line of LTCA2

EBU Address/Data Bus Line 24

Port 14 General Purpose I/O Line 9

EBU Address/Data Bus Line 25

CCU61

AC30 P14.9

AD25

I/O

CC62

T3OUT

OUT105

AD25

GPT121

OUT105 Line of LTCA2

EBU Address/Data Bus Line 25

Port 14 General Purpose I/O Line 10

EBU Address/Data Bus Line 26

CCU61

AC29 P14.10

AD26

I/O

COUT60

T6OUT

OUT106

AD26

GPT120

OUT106 Line of LTCA2

EBU Address/Data Bus Line 26

Port 14 General Purpose I/O Line 11

EBU Address/Data Bus Line 27

CCU61

AD30 P14.11

AD27

I/O

COUT61

T6OUT

OUT107

AD27

GPT121

OUT107 Line of LTCA2

EBU Address/Data Bus Line 27

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AD29 P14.12

AD28

I/O

Port 14 General Purpose I/O Line 12

EBU Address/Data Bus Line 28

CCU61

COUT62

OUT108

AD28

OUT108 Line of GPTA1

OUT108 Line of LTCA2

EBU Address/Data Bus Line 28

Port 14 General Purpose I/O Line 13

EBU Address/Data Bus Line 29

CCU61

AE30 P14.13

AD29

I/O

COUT63

OUT109

AD29

OUT109 Line of GPTA1

OUT109 Line of LTCA2

EBU Address/Data Bus Line 29

Port 14 General Purpose I/O Line 14

EBU Address/Data Bus Line 30

GPT120

AE29 P14.14

AD30

I/O

T3INC

T3IND

GPT121

OUT110

AD30

OUT110 Line of GPTA0

OUT110 Line of GPTA1

OUT110 Line of LTCA2

EBU Address/Data Bus Line 30

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AF30 P14.15

AD31

I/O

Port 14 General Purpose I/O Line 15

EBU Address/Data Bus Line 31

GPT120

T3EUDC

T3EUDD

OUT111

AD31

GPT121

OUT111 Line of GPTA0

OUT111 Line of GPTA1

OUT111 Line of LTCA2

EBU Address/Data Bus Line 31

Port 15

AJ26

P15.0

I/O

Port 15 General Purpose I/O Line 0

T4INC

GPT120

T4IND

GPT121

CCPOS2B

Reserved

CS0

CCU60

Chip Select Output Line 0

AK26 P15.1

T4EUDC

I/O

Port 15 General Purpose I/O Line 1

GPT120

T4EUDD

CCPOS2B

Reserved

CS1

GPT121

CCU61

Chip Select Output Line 1

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AJ25

P15.2

I/O

Port 15 General Purpose I/O Line 2

Reserved

CS2

Chip Select Output Line 2

AK24 P15.3

Reserved

I/O

Port 15 General Purpose I/O Line 3

Reserved

CS3

Chip Select Output Line 3

AJ17

P15.4

I/O

Port 15 General Purpose I/O Line 4

Reserved

BC0

Byte Control Line 0

AK18 P15.5

Reserved

I/O

Port 15 General Purpose I/O Line 5

Reserved

BC1

Byte Control Line 1

AJ18

P15.6

I/O

Port 15 General Purpose I/O Line 6

Reserved

BC2

Byte Control Line 2

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AK19 P15.7

I/O

Port 15 General Purpose I/O Line 7

Reserved

BC3

Byte Control Line 3

AK25 P15.8

I/O

Port 15 General Purpose I/O Line 8

Reserved

Read Control Line

AJ27

AJ28

AJ24

P15.9

I/O

Port 15 General Purpose I/O Line 9

Reserved

RD/WR

P15.10

Write Control Line

I/O

Port 15 General Purpose I/O Line 10

Reserved

ADV

Address Valid Output

P15.11

I/O

Port 15 General Purpose I/O Line 11

WAIT

Wait Input for inserting Wait-States

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AK20 P15.12

I/O

Port 15 General Purpose I/O Line 12

Reserved

MR/W

Motorola-style Read/Write Control Signal

AK29 P15.13

I/O

Port 15 General Purpose I/O Line 13

Reserved

BAA

Burst Address Advance Output

AG30 P15.14

I/O

Port 15 General Purpose I/O Line 14

BFCLKI

Burst FLASH Clock Input (Clock Feedback).

Reserved

I/O

AH30 P15.15

Port 15 General Purpose I/O Line 15

Reserved

BFCLKO

Burst Mode Flash Clock Output (Non-

Differential)

Port 16

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AK17 P16.0

HOLD

I/O

Port 16 General Purpose I/O Line 0

Hold Request Input

Reserved

I/O

Reserved

P16.1

AJ19

Port 16 General Purpose I/O Line 1

HLDA

Hold Acknowledge Input

Reserved

HLDA

Hold Acknowledge Output

AK28 P16.2

Reserved

I/O

Port 16 General Purpose I/O Line 2

Reserved

BREQ

Bus Request Output

AJ20

P16.3

I/O

Port 16 General Purpose I/O Line 3

Reserved

CSCOMB

Combined Chip Select Output

AK23 P16.4

Reserved

I/O

Port 16 General Purpose I/O Line 4

Reserved

RAS

Row Address Select/Strobe

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AJ23

P16.5

I/O

Port 16 General Purpose I/O Line 5

Reserved

CAS

Column Address Select/Strobe

AG29 P16.6

Reserved

I/O

Port 16 General Purpose I/O Line 6

Reserved

DDRCLK

Double Data Rate Flash Clock

AF29 P16.7

I/O

Port 16 General Purpose I/O Line 7

Reserved

DDRCLKN

Inverted Double Data Rate Flash Clock

AK27 P16.8

I/O

Port 16 General Purpose I/O Line 8

Reserved

CKE

Inverted Double Data Rate Flash Clock

W29

P16.9

I/O

Port 16 General Purpose I/O Line 9

DQS0

Data Strobe Signal 0

Reserved

DQS0

Data Strobe Signal 0

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

Y29

P16.10

I/O

Port 16 General Purpose I/O Line 10

DQS1

Data Strobe Signal 1

Reserved

DQS1

Data Strobe Signal 1

AA29 P16.11

DQS2

I/O

Port 16 General Purpose I/O Line 11

Data Strobe Signal 2

Reserved

DQS2

Data Strobe Signal 2

AB29 P16.12

I/O

Port 16 General Purpose I/O Line 12

DQS3

Data Strobe Signal 3

Reserved

DQS3

Data Strobe Signal 3

Port 17

Y10

P17.0

SENT0

AN8

D / S Port 17 General Purpose I Line 0⁴⁾

SENT Digital Input 0

Analog Input : ADC0.CH8 ⁵⁾

D / S Port 17 General Purpose I Line 1⁴⁾

SENT Digital Input 1

P17.1

SENT1

AN9

Analog Input : ADC0.CH9 ⁵⁾

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

D / S Port 17 General Purpose I Line 2⁴⁾

W10

P17.2

SENT2

AN10

SENT Digital Input 2

Analog Input : ADC0.CH10 ⁵⁾

D / S Port 17 General Purpose I Line 3⁴⁾

SENT Digital Input 3

P17.3

SENT3

AN11

Analog Input : ADC0.CH11 ⁵⁾

D / S Port 17 General Purpose I Line 4⁴⁾

SENT Digital Input 4

P17.4

SENT4

AN12

Analog Input : ADC0.CH12 ⁵⁾

D / S Port 17 General Purpose I Line 5⁴⁾

SENT Digital Input 5

P17.5

SENT5

AN13

Analog Input : ADC0.CH13 ⁵⁾

D / S Port 17 General Purpose I Line 6⁴⁾

SENT Digital Input 6

P17.6

SENT6

AN14

Analog Input : ADC0.CH14 ⁵⁾

D / S Port 17 General Purpose I Line 7⁴⁾

SENT Digital Input 7

P17.7

SENT7

AN15

Analog Input : ADC0.CH15 ⁵⁾

D / S Port 17 General Purpose I Line 8⁴⁾

SENT Digital Input 0

AD9

AE9

P17.8

SENT0

AN36

Analog Input : ADC2.CH4 ⁵⁾

D / S Port 17 General Purpose I Line 9⁴⁾

SENT Digital Input 1

P17.9

SENT1

AN37

Analog Input : ADC2.CH5 ⁵⁾

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

D / S Port 17 General Purpose I Line 10⁴⁾

AD10 P17.10

SENT2

SENT Digital Input 2

Analog Input : ADC2.CH6 ⁵⁾

D / S Port 17 General Purpose I Line 11⁴⁾

SENT Digital Input 3

AN38

AE10 P17.11

SENT3

AN39

Analog Input : ADC2.CH7 ⁵⁾

D / S Port 17 General Purpose I Line 12⁴⁾

SENT Digital Input 4

AA11 P17.12

SENT4

AN40

Analog Input : ADC2.CH8 ⁵⁾

D / S Port 17 General Purpose I Line 13⁴⁾

SENT Digital Input 5

AB11 P17.13

SENT5

AN41

Analog Input : ADC2.CH9 ⁵⁾

D / S Port 17 General Purpose I Line 14⁴⁾

SENT Digital Input 6

AA12 P17.14

SENT6

AN42

Analog Input : ADC2.CH10 ⁵⁾

D / S Port 17 General Purpose I Line 15⁴⁾

SENT Digital Input 7

AB12 P17.15

SENT7

AN43

Analog Input : ADC2.CH11 ⁵⁾

Port 18

B11

P18.0

I/O

A1+/ Port 18 General Purpose I/O Line 0

MRST2B

MRST2

SSC2 Master Receive Input B (Slave Mode)

SSC2 Slave Transmit Output (Master Mode)

Reserved

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

A11

P18.1

I/O

A1+/ Port 18 General Purpose I/O Line 1

MTSR2B

MRSTG2B

SSC2 Slave Receive Input B (Slave Mode)

SSC Guardian 2 Master Receive Input B

(Master Mode)

MTSR2

SSC2 Master Transmit Output (Master

Mode)³⁾

Reserved

P18.2

I/O

B10

A1+/ Port 18 General Purpose I/O Line 2

SCLK2B

SCLK2

SSC2 Input

I/O

SSC2 Output

Reserved

P18.3

A10

A1+/ Port 18 General Purpose I/O Line 3

SLSO20

Reserved

P18.4

SSC2 Output

A1+/ Port 18 General Purpose I/O Line 4

SLSO21

Reserved

P18.5

SSC2 Output

A1+/ Port 18 General Purpose I/O Line 5

SLSO22

Reserved

SSC2 Output

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

P18.6

I/O

A1+/ Port 18 General Purpose I/O Line 6

SLSO23

Reserved

P18.7

SSC2 Output

A1+/ Port 18 General Purpose I/O Line 7

SLSO24

Reserved

SSC2 Output

Analog Input Port

AA9

AE7

AD7

AD6

AC7

AB7

AA7

AN0

AN1

AN2

AN3

AN4

AN5

AN6

Analog Input 0: ADC0.CH0 ⁵⁾

Analog Input 1: ADC0.CH1 ⁵⁾

Analog Input 2: ADC0.CH2 ⁵⁾

Analog Input 3: ADC0.CH3 ⁵⁾

Analog Input 4: ADC0.CH4 ⁵⁾

Analog Input 5: ADC0.CH5 ⁵⁾

Analog Input 6: ADC0.CH6 ⁵⁾

AA10 AN7

Analog Input 7: ADC0.CH7 ⁵⁾

Y10

AN8

Analog Input 8: ADC0.CH8, SENT0 ⁵⁾

Analog Input 9: ADC0.CH9, SENT1 ⁵⁾

Analog Input 10: ADC0.CH10, SENT2 ⁵⁾

Analog Input 11: ADC0.CH11, SENT3 ⁵⁾

Analog Input 12: ADC0.CH12, SENT4 ⁵⁾

Analog Input 13: ADC0.CH13, SENT5 ⁵⁾

Analog Input 14: ADC0.CH14, SENT6 ⁵⁾

Analog Input 15: ADC0.CH15, SENT7 ⁵⁾

Analog Input 16: ADC1.CH0 ⁵⁾

AN9

W10

AN10

AN11

AN12

AN13

AN14

AN15

AN16

V10

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AN17

AN18

AN19

AN20

AN21

AN22

AN23

Analog Input 17: ADC1.CH1 ⁵⁾

Analog Input 18: ADC1.CH2 ⁵⁾

Analog Input 19: ADC1.CH3 ⁵⁾

Analog Input 20: ADC1.CH4 ⁵⁾

Analog Input 21: ADC1.CH5 ⁵⁾

Analog Input 22: ADC1.CH6 ⁵⁾

Analog Input 23: ADC1.CH7 ⁵⁾

Analog Input 24: ADC1.CH8 ⁵⁾

Analog Input 25: ADC1.CH9 ⁵⁾

Analog Input 26: ADC1.CH10 ⁵⁾

Analog Input 27: ADC1.CH11 ⁵⁾

Analog Input 28: ADC1.CH12 ⁵⁾

Analog Input 29: ADC1.CH13 ⁵⁾

Analog Input 30: ADC1.CH14 ⁵⁾

Analog Input 31: ADC1.CH15 ⁵⁾

Analog Input 32: ADC2.CH0 ⁵⁾

Analog Input 33: ADC2.CH1 ⁵⁾

Analog Input 34: ADC2.CH2 ⁵⁾

Analog Input 35: ADC2.CH3 ⁵⁾

Analog Input 36: ADC2.CH4, SENT0 ⁵⁾

Analog Input 37: ADC2.CH5, SENT1 ⁵⁾

Analog Input 38: ADC2.CH6, SENT2 ⁵⁾

Analog Input 39: ADC2.CH7, SENT3 ⁵⁾

Analog Input 40: ADC2.CH8, SENT4 ⁵⁾

Analog Input 41: ADC2.CH9, SENT5 ⁵⁾

Analog Input 42: ADC2.CH10, SENT6 ⁵⁾

U10

AB13 AN24

AD13 AN25

AE13 AN26

AA14 AN27

AB14 AN28

AD14 AN29

AE14 AN30

AA15 AN31

AB9

AD8

AE8

AN32

AN33

AN34

AA13 AN35

AD9

AE9

AN36

AN37

AD10 AN38

AE10 AN39

AA11 AN40

AB11 AN41

AA12 AN42

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AB12 AN43

Analog Input 43: ADC2.CH11, SENT7 ⁵⁾

Analog Input 44: ADC2.CH12 ⁵⁾

Analog Input 45: ADC2.CH13 ⁵⁾

Analog Input 46: ADC2.CH14 ⁵⁾

Analog Input 47: ADC2.CH15 ⁵⁾

Analog Input 48: ADC3.CH0 ⁵⁾

Analog Input 49: ADC3.CH1 ⁵⁾

Analog Input 50: ADC3.CH2 ⁵⁾

Analog Input 51: ADC3.CH3 ⁵⁾

Analog Input 52: ADC3.CH4 ⁵⁾

Analog Input 53: ADC3.CH5 ⁵⁾

Analog Input 54: ADC3.CH6 ⁵⁾

Analog Input 55: ADC3.CH7 ⁵⁾

Analog Input 56: ADC3.CH8 ⁵⁾

Analog Input 57: ADC3.CH9 ⁵⁾

Analog Input 58: ADC3.CH10 ⁵⁾

Analog Input 59: ADC3.CH11 ⁵⁾

Analog Input 60: ADC3.CH12 ⁵⁾

Analog Input 61: ADC3.CH13 ⁵⁾

Analog Input 62: ADC3.CH14 ⁵⁾

Analog Input 63: ADC3.CH15 ⁵⁾

Analog Input 64: FADC_FADIN0P ⁶⁾

Analog Input 65: FADC_FADIN0N ⁶⁾

Analog Input 66: FADC_FADIN1P ⁶⁾

Analog Input 67: FADC_FADIN1N ⁶⁾

Analog Input 68: FADC_FADIN2P ⁶⁾

AC6

AB6

AA6

AN44

AN45

AN46

AB10 AN47

AN48

AN49

AN50

AN51

AN52

AN53

AN54

AN55

AN56

AN57

AN58

AN59

AN60

AN61

AN62

AN63

AN64

AN65

AN66

AN67

AN68

AA2

AA1

AB2

AB1

AC2

AC1

AD2

AD1

AE2

AE1

AF2

AF1

AG2

AG1

AJ5

AK5

AJ6

AK6

AJ7

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AK7

AN69

AN70

AN71

Analog Input 69: FADC_FADIN2N ⁶⁾

Analog Input 70: FADC_FADIN3P ⁶⁾

Analog Input 71: FADC_FADIN3N ⁶⁾

AJ8

AK8

System I/O

L24

PORST

Power-on Reset Input

M24

ESR0

I/O

External System Request Reset Input 0

Default configuration during and after reset is

open-drain driver. The driver drives low during

power-on reset.

M25

N25

ESR1

I/O

A2/

External System Request Reset Input 1

TCK

JTAG Module Clock Input

DAP0

Device Access Port Line 0

P22

TDI

A2/

JTAG Module Serial Data Input

OCDS Break Input (Alternate Output)

OCDS Break Output (Alternate Input)

Test Mode Select Input

BRKIN

BRKOUT

TESTMODE

TMS

M22

P21

A2/

JTAG Module State Machine Control Input

Device Access Port Line 1

DAP1

I/O

N24

R25

R24

N22

TRST

XTAL1

XTAL2

TDO

JTAG Module Reset/Enable Input

Main Oscillator/PLL/Clock Generator Input

Main Oscillator/PLL/Clock Generator Output

JTAG Module Serial Data Output

OCDS Break Input (Alternate Input)

OCDS Break Output (Alternate Output)

Device Access Port Line 2

A2/

BRKIN

BRKOUT

DAP2

Power Supply

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

V_DDM

V_SSM

ADC Analog Part Power Supply (3.3V - 5V)

ADC Analog Part Ground

Y1,

Y2, Y6

AE11 V_AREF0

AE12 V_AGND0

AD11 V_AREF1

ADC0 Reference Voltage

ADC0 Reference Ground

ADC1 Reference Voltage

ADC1 Reference Ground

ADC2 Reference Voltage

ADC2 Reference Ground

ADC3 Reference Voltage

ADC3 Reference Ground

FADC Reference Voltage

FADC Reference Ground

FADC Analog Part Power Supply (3.3V)

AK9

V_AGND1

AD12 V_AREF2

AJ10

AJ9

V_AGND2

V_AREF3

AK10 V_AGND3

AB15 V_FAREF

AD15 V_FAGND

AB16 V_DDMF

AA16 V_DDAF

FADC Analog Part Logic Power Supply

(1.3V)

AE15, V_SSMF

AJ11,

V_SSAF

AK11

FADC Analog Part Ground

FADC Analog Part Logic Ground

R10,

T21

V_DDFL3

Flash Power Supply (3.3V)

R30,

R29,

P25

V_SSOSC

V_SS

Main Oscillator Ground

Digital Ground

P24

R21

R22

T22

V_DDOSC

V_DDOSC3

V_DDPF

Main Oscillator Power Supply (1.3V)

Main Oscillator Power Supply (3.3V)

E-Ray PLL Power Supply (1.3V)

E-Ray PLL Power Supply (3.3V)

V_DDPF3

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

AJ30, V_DD

AH29,

Digital Core Power Supply (1.3V)

AD25,

AC24,

AA22,

Y21

W18, V_DD

W13,

V19,

Digital Core Power Supply (1.3V, center

balls)

V12,

N19,

N12,

M18,

M13

AK15, V_DDP

AJ15,

AD16,

T2,

Port Power Supply (3.3V)

T1,

R7,

G23,

G15,

G8,

F24,

F7,

B28,

A29,

B16,

A16,

B3, A2

AK21, V_DDEBU

AJ21,

EBU Port Power Supply (1.8 - 2.5V - 3.3V)

AD22,

U24,

U25,

U29,

U30,

C30

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

V_DDSB

Ctrl. Type Function

T9,

T10

Emulation Stand-by SRAM Power Supply

(1.3V) (Emulation device only)

Note: This pin is N.C. in a productive device.

AK16, V_SSP

AJ16,

AE16,

R6,

Digital Ground

R2,

R1,

F15,

K10,

K21,

J22,

J9,

G24,

G7,

F25,

B29,

B15,

B2,

A30,

A15

AK22, V_SS

AJ22,

AE22,

T30,

Digital Ground

T29,

T25,

T24,

B30

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

W17, V_SS

W16,

W15,

W14, ,

V17,

V16,

Digital Ground (center balls)

V15,

V14

N17,

N16,

N15,

N14, ,

M17,

M16,

M15,

M14

V_SS

Digital Ground (center balls cont’d)

U19,

U18,

U16,

U15,

U13,

U12,

P13,

P12,

P19,

P18,

P16,

P15,

V_SS

Digital Ground (center balls cont’d)

R19,

R18,

R17,

R16,

R15,

R14,

R13,

R12

V_SS

Digital Ground (center balls cont’d)

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

V_SS

Ctrl. Type Function

T19,

T18,

T17,

T16,

T15,

T14,

T13,

T12

Digital Ground (center balls cont’d)

AK30, V_SS

AJ29,

AE25,

AD24,

AB22,

Digital Ground (center balls cont’d)

AA21

A1,

N.C.

Not connected. These pins are reserved for

future extension and shall not be connected

externally.

A3,

A4,

A5,

A14,

A17,

A23,

A24,

A25,

A26

B1,

B4,

B5,

N.C.

Not connected. These pins are reserved for

future extension and shall not be connected

externally.

B14,

B17,

B23,

B24,

B25,

B26

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

Table 2

Pin Definitions and Functions (PG-LFBGA- 516 Package) (cont’d)

Symbol

Ctrl. Type Function

C1,

C2,

C29,

D1,

D2,

E1,

E2,

F1,

F2,

F6,

G1,

G2,

N1,

N.C.

Not connected. These pins are reserved for

future extension and shall not be connected

externally.

U1,

U2,

V1,

N.C.

Not connected. These pins are reserved for

future extension and shall not be connected

externally.

V2,

AE6,

AH1,

AH2,

AJ1,

AJ2,

AJ3

AJ4,

N.C.

Not connected. These pins are reserved for

future extension and shall not be connected

externally.

AJ12,

AK1,

AK2,

AK3,

AK4,

AK12,

AK13

1) Only applicable in TC1798ED. Reserved in TC1798PD.

2) Only available for SAK-TC1798F-512F300EL, SAK-TC1798F-512F300EP, and SAK-TC1798S-512F300EP.

3) The MTSR output of SSCx is overlayed with the MRSTG input of the related SSCGx

4) Analog Input overlayed with a SENT Digitial Input. The related port logic is used configure the input as either

analog input (default after reset) or digital input. The related port logic supports only the port input features as

the connected pads are input pads only.

Data Sheet

V 1.1, 2014-05

TC1798

PinningTC1798 Pin Configuration

5) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table.

6) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table.

Legend for Table 2

Column “Ctrl.”:

I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXX_B)

O = Output

O0 = Output with IOCR bit field selection PCx = 1X00_B

O1 = Output with IOCR bit field selection PCx = 1X01_B(ALT1)

O2 = Output with IOCR bit field selection PCx = 1X10_B(ALT2)

O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)

Column “Type”:

A1 = Pad class A1 (LVTTL)

A1+ = Pad class A1+ (LVTTL)

A2 = Pad class A2 (LVTTL)

B = Pad class B (LVTTL)

F = Pad class F (LVDS/CMOS)

D = Pad class D (ADC)

S = Pad class D (ADC) / Pad class S(SENT)

PU = with pull-up device connected during reset (PORST = 0)

PD = with pull-down device connected during reset (PORST = 0)

TR = tri-state during reset (PORST = 0)

Data Sheet

V 1.1, 2014-05

TC1798

Identification Registers

The Identification Registers uniquely identify the whole device.

Table 3

SAK-TC1798F-512F300EL Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

0700 9802_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Table 4

SAK-TC1798F-512F300EP Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

8700 9802_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Table 5

SAK-TC1798N-512F300EP Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

8700 B002_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Table 6

SAK-TC1798S-512F300EP Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

Value

Address

Stepping

0000 6350_H

1018 E083_H

8700 AC02_H

F000 0408_H

F000 0464_H

F000 0640_H

Data Sheet

V 1.1, 2014-05

TC1798

Identification Registers

Table 6

SAK-TC1798S-512F300EP Identification Registers (cont’d)

Short Name

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 1820_H

0000 0000_H

F000 0644_H

F000 0648_H

Data Sheet

V 1.1, 2014-05

TC1798

Electrical ParametersGeneral Parameters

Electrical Parameters

This specification provides all electrical parameters of the TC1798.

5.1

General Parameters

5.1.1

Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC1798

and partly its requirements on the system. To aid interpreting the parameters easily

when evaluating them for a design, they are marked with an two-letter abbreviation in

column “Symbol”:

•

Such parameters indicate Controller Characteristics which are a distinctive feature of

the TC1798 and must be regarded for a system design.

•

Such parameters indicate System Requirements which must provided by the

microcontroller system in which the TC1798 designed in.

Data Sheet

V 1.1, 2014-05

TC1798

Electrical ParametersGeneral Parameters

5.1.2

Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic

characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.

Table 7

Pad Driver and Pad Classes Overview

Class Power Type

Supply

Sub Class Speed Load Leakage Termination

Grade

150oC ¹⁾

3.3 V

LVTTL A1

6 MHz 100 pF 500 nA

I/O,

(e.g. GPIO)

LVTTL

outputs

A1+

(e.g. serial

I/Os)

MHz

50 pF 1 μA

50 pF 3 μA

Series

termination

recommended

Series

(e.g. serial

I/Os)

MHz

termination

recommended

3.3 V²⁾LVTTL

I/O

MHz

35 pF 6 μA

Series

termination

recommended

2.5 V

MHz

35 pF

1.8 V

3.3 V

LVDS

–

Parallel

MHz

termination,

100 Ω ± 10% ³⁾

CMOS

ADC

–

6 MHz 50 pF

–

5 V

–

3.3 V

LVTTL

(input

only)

1) These values show typical application configurations for the pad. Complete and detailed pad parameters are

available in the individual pad parameter table on the following pages.

2) Supplied via V_DDEBU

3) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or

properly terminated with the differential parallel termination of 100 Ω ± 10%.

Data Sheet

V 1.1, 2014-05

TC1798

Electrical ParametersGeneral Parameters

5.1.3

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Table 8

Absolute Maximum Rating Parameters

Symbol Values

Min. Typ. Max.

Parameter

Unit Note /

Test Con

dition

Storage temperature

T_ST

SR -65

–

150

2.0

°C

–

Voltage at 1.3 V power supply V_DDSR

pins with respect to V_SS

–

Voltage at 3.3 V power supply V_DDP

–

4.33

7.0

–

pins with respect to V_SS

Voltage at 5 V power supply V_DDMSR –

pins with respect to V_SS

Voltage on any Class A input V_IN

pin and dedicated input pins

with respect to V_SS

SR -0.7

V_DDP+ 0.5

Whatever

is lower

or max. 4.33

Voltage on any Class D

analog input pin with respect V_AREFx

to V_AGND

V_AIN

-0.6

–

7.0

–

Voltage on any shared Class V_AINF

D analog input pin with

V_FAREF

respect to V_SSAF, if the FADC

is switched through to the pin.

Voltage on any shared Class V_AINF

D analog input pin with

respect to V_SSAF, if the FADC

is switched through to the pin.

-0.5

-10

–

7.0

–

Input current on any pin

I_IN

+10

during overload condition¹⁾

Data Sheet

V 1.1, 2014-05

TC1798

Electrical ParametersGeneral Parameters

Table 8

Absolute Maximum Rating Parameters

Parameter

Symbol

Values

Unit Note /

Test Con

dition

Min. Typ. Max.

Absolute maximum sum of all I_IN

input circuit currents for one

port group during overload

condition³⁾

-25

–

+25

200

Absolute maximum sum of all ΣI_IN

input circuit currents during

overload condition

-200 –

1) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods

of time may damage the device.

2) Refers to possibility of current caused degradation, where the voltages in overload do not violate the normal

operating conditions. In case that the overvoltages violate the normal operating conditions, the reliability

considerations caused by overvoltage apply independently, as described in this document.

3) The port groups are defined in Table 13.

Data Sheet

V 1.1, 2014-05

TC1798

Electrical ParametersGeneral Parameters

5.1.4

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience

overload currents and voltages that go beyond their own IO power supplies specification.

Table 9 defines overload conditions that will not cause any negative reliability impact if

all the following conditions are met:

•

full operation life-time (24000 h) is not exceeded

Operating Conditions are met for

– pad supply levels (V_DDPor V_DDM

)

– temperature

If a pin current is out of the Operating Conditions but within the overload parameters,

then the parameters functionality of this pin as stated in the Operating Conditions can no

longer be guaranteed. Operation is still possible in most cases but with relaxed

parameters.

Note: An overload condition on one or more pins does not require a reset.

Table 9

Overload Parameters

Symbol

Parameter

Values

Unit Note /

Test Con

dition

Min. Typ. Max.

Input current on any digital pin I_IN

during overload condition

except LVDS pins

-5

–

Input current on LVDS pins

I_INLVDS

I_ING

-3

–

Absolute sum of all input

circuit currents for one port

group during overload

condition¹⁾

-20

+20

Input current on analog pins I_INANA

-3

–

Absolute sum of all analog

input currents for analog

inputs during overload

condition

I_INSA

-45

+45

Absolute sum of all input

circuit currents during

overload condition

ΣI_INS

-100 –

100

1) The port groups are defined in Table 13.

Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.

Data Sheet

V 1.1, 2014-05

TC1798

Electrical ParametersGeneral Parameters

Table 10

PN-Junction Characterisitics for positive Overload

_IN= 3 mA _IN= 5 mA

Pad Type

A1 / A1+ / F

U_IN= V_DDP+ 0.6 V

U_IN= V_DDP+ 0.5 V

U_IN= V_DDP+ 0.7 V

U_IN= V_DDM+ 0.6 V

_IN= V_DDP+ 0.7 V

LVDS

_IN= V_DDP+ 0.6 V

Table 11

PN-Junction Characterisitics for negative Overload

_IN= -3 mA _IN= -5 mA

Pad Type

A1 / A1+ / F

U_IN= V_SS- 0.6 V

U_IN= V_SS- 0.5 V

U_IN= V_SS- 0.7 V

U_IN= V_SSM- 0.6 V

_IN= V_SS- 0.7 V

LVDS

_IN= V_SS- 0.6 V

Note: A series resistor at the pin to limit the current to the maximum permitted overload

current is sufficient to handle failure situations like short to battery without having

any negative reliability impact on the operational life-time.

Data Sheet

V 1.1, 2014-05

TC1798

Electrical ParametersGeneral Parameters

5.1.5

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation and reliability of the TC1798. All parameters specified in the following tables

refer to these operating conditions, unless otherwise noticed.

Digital supply voltages applied to the TC1798 must be static regulated voltages which

allow a typical voltage swing of ± 5 %.

All parameters specified in the following tables (Table 14 and following) refer to these

operating conditions (Table 12), unless otherwise noticed in the Note / Test Condition

column.

The Extended Range Operating Conditions did not increase area of validity of the

parameters defined in table 10 and later.

Table 12

Operating Conditions Parameters

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Overload coupling factor K_OVAN

for analog inputs, negative CC

−

0.0001

I_OV≤ 0 mA;

I_OV≥ -2 mA;

analog

pad= 5.0 V

Overload coupling factor K_OVAP

for analog inputs, positive CC

−

0.0000

I_OV≤ 3 mA;

I_OV≥ 0 mA;

analog

pad= 5.0 V

CPU Frequency

_CPUSR

−

300

MHz

Modulated f_CPU

f_{CPU_mod}

_ulatedSR

300-

2*MA¹⁾

FPI bus frequency

_FPISR

−

100

MHz

Modulated f_FPI

f_{FPI_modul}

_atedSR

100-

2*MA¹⁾

FSI frequency

_FSISR

−

150

MHz

Modulated f_FSI

f_{FSI_modul}

_atedSR

150-

2*MA¹⁾

PCP Frequency

_PCPSR

−

200

MHz

Modulated f_PCP

f_{PCP_mod}

_ulatedSR

200-

2*MA¹⁾

SRI Frequency

Data Sheet

_SRISR

−

300

MHz

100

V 1.1, 2014-05

TC1798

Electrical ParametersGeneral Parameters

Table 12

Operating Conditions Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Modulated f_SRI

f_{SRI_modul}

_atedSR

−

300-

MHz

2*MA¹⁾

Inactive device pin current I_IDSR

-1

−

mA All power

supply voltages

V_DDx= 0

Short circuit current of

digital outputs²⁾

_SCSR -5

−

Absolute sum of short

circuit currents of the

device

ΣI_{SC_D}

−

100

Absolute sum of short

circuit currents per pin

group

ΣI_{SC_PG}

−

Ambient Temperature

Junction temperature

Core Supply Voltage

T_ASR

T_JSR

-40

−

125

°C

150

1.365³⁾

_DDSR 1.235 1.3

for duration

limitation see

Section 5.1.5.1

EBU supply voltage

V_DDEBU3.135 3.3

3.465⁵⁾

for duration

limitation see

Section 5.1.5.1

2.375 2.5

2.625

1.89

3.63⁵⁾

1.71

1.8

Flash supply voltage 3.3V V_DDFL3

3.135 3.3

for duration

limitation see

Section 5.1.5.1

ADC analog supply

voltage

V_DDM

3.135

5.5⁴⁾

Oscillator core supply

voltage

V_DDOSC1.235 1.3

1.43³⁾

for duration

limitation see

Section 5.1.5.1

Oscillator 3.3V supply

voltage

V_DDOSC33.135 3.3

3.63⁵⁾

for duration

limitation see

Section 5.1.5.1

Data Sheet

101

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TC1798

Electrical ParametersGeneral Parameters

Table 12

Operating Conditions Parameters (cont’d)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Min.

Max.

Digital supply voltage for

IO pads

_DDPSR 3.135 3.3

3.63 ⁵⁾

for duration

limitation see

Section 5.1.5.1

E-Ray PLL core voltage

supply

V_DDPF

1.235 1.3

1.43³⁾

3.63⁵⁾

−

for duration

limitation see

Section 5.1.5.1

E-Ray PLL 3.3V supply

V_DDPF33.135 3.3

for duration

limitation see

Section 5.1.5.1

VDDP voltage to ensure

defined pad states⁶⁾

V_DDPPA0.65

−

Digital ground voltage

_SSSR

−

Analog ground voltage for

_SSMSR -0.1

0.1

V_DDM

Analog core supply

V_DDAF

1.235 1.3

3.135 3.3

1.365³⁾

3.47⁵⁾

0.1

for duration

limitation see

Section 5.1.5.1

FADC / ADC analog

supply voltage

V_DDMF

for duration

limitation see

Section 5.1.5.1

Analog ground voltage for V_SSAF

V_DDMFSR

-0.1

1) MA equals the modulation amplitude in percentage times the configured PLL clock out frequency.

2) Applicable for digital outputs.

3) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less

than 100 μs and the cumulated sum of the pulses does not exceed 1 h.

4) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less

than 100 μs and the cumulated sum of the pulses does not exceed 1 h.

5) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less

than 100 μs and the cumulated sum of the pulses does not exceed 1 h.

6) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-

up/power-down of V_DDP

5.1.5.1 Extended Range Operating Conditions

The following extended operating conditions are defined:

•

1.3V + 5% < V_DD/ V_DDOSC/ V_DDPF/ V_DDAF< 1.3V + 7.5% (overvoltage condition):

Data Sheet

102

V 1.1, 2014-05

TC1798

Electrical ParametersGeneral Parameters

– limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction

of the chip caused by the overvoltage stress.

•

1.3V + 7.5% < V_DD/ V_DDOSC/ V_DDPF/ V_DDAF< 1.3V + 10% (overvoltage condition):

– limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction

of the chip caused by the overvoltage stress.

V_DDP/ V_DDOSC3/ V_DDPF3/ V_DDFL3/ V_DDMF/ V_DDEBU< 3.3 V ± 10%

– 3.3V + 5% < V_DDP/ V_DDOSC3/ V_DDPF3/ V_DDFL3/ V_DDMF/ V_DDEBU< 3.3V + 10%

(overvoltage condition):

limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction

of the chip caused by the overvoltage stress.

Table 13

Pin Groups for Overload / Short-Circuit Current Sum Parameter

Group

Pins

P2.[4:2], P6.[6:9]

P6.[5:4], P6.[11:10]

P6.[15:12]

P8.[5:0]

P8.[7:6], P1.[15:13]

P1.5, P1.[11:8]

P1.[4:2], P1.6, P1.12

P1.[1:0], P7.[2:0]

P7.[7:3]

P4.[6:0]

P4.[10:7]

P4.[15:11]

P10.[5:0]

P15.[7:4], P16.[1:0]

P15.3, P15.[12:11], P16.[5:3]

P15.[2:0], P15.[9:8], P16.2, P16.8

P15.10, P15.[15:13], P16.[7:6]

P14.[15:12]

P14.[11:8], P16.12

P14.[7:3], P16.11

P13.15, P14.[2:0]

Data Sheet

103

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TC1798

Electrical ParametersGeneral Parameters

Table 13

Pin Groups for Overload / Short-Circuit Current Sum Parameter

(cont’d)

Group

Pins

P13.[14:11]

P13.[10:8], P16.10

P13.[7:4], P16.9

P12.5, P13.[3:0]

P12.[4:0]

P11.[15:11]

P11.[10:6]

P11.[5:2]

P11.[1:0], P12.[7:6]

P9.10, P9.14

P9.7, P9.13

P9.[4:2], P9.6

P9.1, P9.5, P9.[9:8]

P9.0, P9.[12:11]

P5.[11:8]

P5.6, P5.[15:12]

P5.0, P5.[5:2], P5.7

P3.[5:0], P5.1

P3.[12:6]

P0.[3:0], P3.[15:13]

P0.[11:4]

P0.[14:12]

P0.15, P18.[5:0]

P2.[15:11], P18.[7:6]

P2.[10:5]

Data Sheet

104

V 1.1, 2014-05

TC1798

Electrical ParametersDC Parameters

5.2

DC Parameters

5.2.1

Input/Output Pins

Table 14

Standard_Pads Parameters

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Pin capacitance (digital

inputs/outputs)

C_IOCC

−

T_A= 25 °C;

f= 1 MHz

Pull-down current

|I_PDL

−

150

μA

V_i≥ 0.6 x V_DDPV

V_i≥ 0.36 x

−

_DDPV

Pull-Up current

|I_PUH

−

μA

V_i≤ 0.6 x V_DDPV

V_i≤ 0.36 x

−

100

_DDPV

Spike filter always blocked t_SF1CC

pulse duration

−

only PORST pin

Spike filter pass-through

pulse duration

_SF2CC 100

−

only PORST pin

Table 15

Standard_Pads Class_A1

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Input Hysteresis for A1

pads ¹⁾

HYSA1 0.1 x

−

V_DDP

Input Leakage Current

Class A1

I_OZA1

-500

−

500

V_i≥ 0 V;

V_i≤ V_DDPV

Ratio Vil/Vih, A1 pads

V_ILA1

V_IHA1

0.6

−

Data Sheet

105

V 1.1, 2014-05

TC1798

Electrical ParametersDC Parameters

Table 15

Standard_Pads Class_A1 (cont’d)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Min.

Max.

On-Resistance of the

R_DSONW

−

450

600

Ohm I_OH> -0.5 mA;

class A1 pad, weak driver CC

P_MOS

−

210

−

340

155

110

150

Ohm I_OL< 0.5 mA;

N_MOS

On-Resistance of the

class A1 pad, medium

driver

R_DSONM

Ohm I_OH> 2 mA;

P_MOS

−

Ohm I_OL< 2 mA;

N_MOS

Fall time,pad type A1

_FA1CC

−

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF; pin

out

driver= medium

140

550

C_L= 150 pF; pin

out

driver= medium

C_L= 150 pF; pin

out

driver= weak

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Data Sheet

106

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TC1798

Electrical ParametersDC Parameters

Table 15

Standard_Pads Class_A1 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Rise time, pad type A1

_RA1CC

−

150

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF; pin

out

driver= medium

140

550

C_L= 150 pF; pin

out

driver= medium

C_L= 150 pF; pin

out

driver= weak

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Input high voltage class

A1 pads

V_IHA1

0.6 x

V_DDP

min(V

DDP+

0.3,3.6

)

Input low voltage class A1 V_ILA1SR -0.3

−

0.36 x

pads

V_DDP

Data Sheet

107

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TC1798

Electrical ParametersDC Parameters

Table 15

Standard_Pads Class_A1 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Output voltage high class V_OHA1

A1 pads CC

V_DDP

0.4

−

I_OH≥ -1.4 mA;

pin out

driver= medium

2.4

−

I_OH≥ -2 mA; pin

out

driver= medium

V_DDP

0.4

−

I_OH≥ -400 μA;

pin out

driver= weak

2.4

−

I_OH≥ -500 μA;

pin out

driver= weak

Output voltage low class V_OLA1

A1 pads CC

0.4

I_OL≤ 2 mA; pin

out

driver= medium

−

I_OL≤ 500 μA;

pin out

driver= weak

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Table 16

Standard_Pads Class_A1+

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Input Hysteresis for A1+

pads ¹⁾

HYSA1 0.1 x

−

+ CC

V_DDP

Input Leakage Current

Class A1+

I_OZA1+

-1000

−

1000

600

On-Resistance of the

class A1+ pad, weak

driver

R_DSONW

−

450

210

Ohm I_OH> -0.5 mA;

P_MOS

340

Ohm I_OL< 0.5 mA;

N_MOS

Data Sheet

108

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TC1798

Electrical ParametersDC Parameters

Table 16

Standard_Pads Class_A1+ (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

On-Resistance of the

class A1+ pad, medium

driver

R_DSONM

−

155

Ohm I_OH> 2 mA;

P_MOS

−

110

100

Ohm I_OL< 2 mA;

N_MOS

On-Resistance of the

class A1+ pad, strong

driver

R_DSON1+

Ohm I_OH> 2 mA;

P_MOS

Ohm I_OL< 2 mA;

N_MOS

Fall time, pad type A1+

_FA1+CC −

150

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF;

edge= slow ;

pin out

driver= strong

C_L= 50 pF;

edge= soft ; pin

out

driver= strong

−

C_L= 50 pF; pin

out

driver= medium

140

550

C_L= 150 pF; pin

out

driver= medium

C_L= 150 pF; pin

out

driver= weak

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Data Sheet

109

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TC1798

Electrical ParametersDC Parameters

Table 16

Standard_Pads Class_A1+ (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

_RA1+CC −

Max.

Rise time, pad type A1+

150

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF;

edge= slow ;

pin out

driver= strong

C_L= 50 pF;

edge= soft ; pin

out

driver= strong

−

C_L= 50 pF; pin

out

driver= medium

140

550

C_L= 150 pF; pin

out

driver= medium

C_L= 150 pF; pin

out

driver= weak

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Input high voltage, Class V_IHA1+

0.6 x

V_DDP

min(V

DDP+

0.3,3.6

)

A1+ pads

Input low voltage Class

A1+ pads

V_ILA1+

-0.3

0.6

−

0.36 x

V_DDP

Ratio Vil/Vih, A1+ pads

V_ILA1+

V_IHA1+

−

Data Sheet

110

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TC1798

Electrical ParametersDC Parameters

Table 16

Standard_Pads Class_A1+ (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Output voltage high class V_OHA1+V_DDP

A1+ pads

−

I_OH≥ -1.4 mA;

pin out

driver= medium

0.4

V_DDP

0.4

−

I_OH≥ -1.4 mA;

pin out

driver= strong

2.4

−

I_OH≥ -2 mA; pin

out

driver= medium

−

I_OH≥ -2 mA; pin

out

driver= strong

V_DDP

0.4

−

I_OH≥ -400 μA;

pin out

driver= weak

2.4

−

I_OH≥ -500 μA;

pin out

driver= weak

Output voltage low class V_OLA1+

A1+ pads CC

0.4

I_OL≤ 2 mA; pin

out

driver= medium

−

I_OL≤ 2 mA; pin

out

driver= strong

−

I_OL≤ 500 μA;

pin out

driver= weak

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Data Sheet

111

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Electrical ParametersDC Parameters

Table 17

Standard_Pads Class_A2

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Input Hysteresis for A2

pads ¹⁾

HYSA2 0.1 x

−

V_DDP

Input Leakage current

Class A2

I_OZA2

-6000

−

6000

V_i< V_DDP/ 2 -

1 V; V_i> V_DDP/2

+ 1 V; V_i≥ 0 V;

V_i≤ V_DDPV

-3000

0.6

−

3000

V_i> V_DDP/ 2 -

1 V; V_i< V_DDP/2

+ 1 V

Ratio Vil/Vih, A2 pads

On-Resistance of the

V_ILA2

V_IHA2

−

R_DSONW

−

450

210

−

600

340

155

110

Ohm I_OH> -0.5 mA;

class A2 pad, weak driver CC

P_MOS

Ohm I_OL< 0.5 mA;

N_MOS

On-Resistance of the

class A2 pad, medium

driver

R_DSONM

Ohm I_OH> 2 mA;

P_MOS

−

Ohm I_OL< 2 mA;

N_MOS

On-Resistance of the

class A2 pad, strong driver CC

R_DSON2

−

Ohm I_OH> 2 mA;

P_MOS

−

Ohm I_OL< 2 mA;

N_MOS

Data Sheet

112

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Electrical ParametersDC Parameters

Table 17

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Fall time, pad type A2

_FA2CC

−

150

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF;

edge= medium

; pin out

driver= strong

3.7

C_L= 50 pF;

edge= medium-

minus ; pin out

driver= strong

C_L= 50 pF;

edge= sharp ;

pin out

driver= strong

C_L= 50 pF;

edge= sharp-

minus ; pin out

driver= strong

C_L= 50 pF;

edge= soft ; pin

out

driver= strong

−

C_L= 50 pF; pin

out

driver= medium

7.5

C_L= 100 pF;

edge= sharp ;

pin out

driver= strong

−

140

C_L= 150 pF; pin

out

driver= medium

Data Sheet

113

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Electrical ParametersDC Parameters

Table 17

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

−

550

C_L= 150 pF; pin

out

driver= weak

−

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Data Sheet

114

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Electrical ParametersDC Parameters

Table 17

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Rise time, pad type A2

_RA2CC

−

150

C_L= 20 pF; pin

out

driver= weak

−

7.0

3.7

C_L= 50 pF;

edge= medium

; pin out

driver= strong

C_L= 50 pF;

edge= medium-

minus ; pin out

driver= strong

C_L= 50 pF;

edge= sharp ;

pin out

driver= strong

C_L= 50 pF;

edge= sharp-

minus ; pin out

driver= strong

C_L= 50 pF;

edge= soft ; pin

out

driver= strong

−

C_L= 50 pF; pin

out

driver= medium

7.5

C_L= 100 pF;

edge= sharp ;

pin out

driver= strong

−

140

C_L= 150 pF; pin

out

driver= medium

Data Sheet

115

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Electrical ParametersDC Parameters

Table 17

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

−

550

C_L= 150 pF; pin

out

driver= weak

−

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Input high voltage, class

A2 pads

V_IHA2

0.6 x

V_DDP

min(V

DDP+

0.3,

3.6)

Input low voltage Class A2 V_ILA2SR -0.3

pads

−

0.36 x

V_DDP

Output voltage high class V_OHA2

V_DDP

−

I_OH≥ -1.4 mA;

pin out

driver= medium

A2 pads

0.4

V_DDP

0.4

−

I_OH≥ -1.4 mA;

pin out

driver= strong

2.4

I_OH≥ -2 mA; pin

out

driver= medium

I_OH≥ -2 mA; pin

out

driver= strong

V_DDP

0.4

I_OH≥ -400 μA;

pin out

driver= weak

2.4

I_OH≥ -500 μA;

pin out

driver= weak

Data Sheet

116

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Electrical ParametersDC Parameters

Table 17

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Output voltage low class V_OLA2

A2 pads CC

−

0.4

I_OL≤ 2 mA; pin

out

driver= medium

−

0.4

I_OL≤ 2 mA; pin

out

driver= strong

I_OL≤ 500 μA;

pin out

driver= weak

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Table 18

Standard_Pads Class_B

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Input Hysteresis, B class HYSB

0.05 x

V_DDEBU

−

_DDEBU= 1.8 V

_DDEBU= 2.5 V

_DDEBU= 3.3 V

_DDEBU= 1.8 V;

pads¹⁾

0.08 x

V_DDEBU

−

0.1 x

V_DDEBU

−

Input Leakage Current,

class B pads

_OZBCC -3000

3000

V_i> 0 V;

V_i< V_DDEBUV

-6000

−

6000

3000

V_i> 0 V;

V_i> V_DDEBU/2 +

0.6 V;

V_i≤ V_DDEBUV;

V_i≤ V_DDEBU/2 -

0.6 V

-3000

−

V_i> V_DDEBU/2 -

0.6 V;

V_i< V_DDEBU/2 +

0.6 V

Data Sheet

117

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Electrical ParametersDC Parameters

Table 18

Standard_Pads Class_B (cont’d)

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Ratio between low and

high input threshold

V_ILB

_IHBCC

R_DSONW

0.6

−

On-Resistance of the

class B pad, weak driver CC

−

450

210

−

600

340

155

110

Ohm I_OH> -0.5 mA;

P_MOS;

_DDEBU= 3.3 V

Ohm I_OL< 0.5 mA;

N_MOS;

_DDEBU= 3.3 V

On-Resistance of the

class B pad, medium

driver

R_DSONM

Ohm I_OH> -2 mA;

P_MOS;

_DDEBU= 3.3 V

−

Ohm I_OL< 2 mA;

N_MOS;

_DDEBU= 3.3 V

On-Resistance of the

class B pad, strong driver CC

R_DSON2

−

Ohm I_OH> -2 mA;

P_MOS;

_DDEBU= 3.3 V

−

Ohm I_OL< 2 mA;

N_MOS;

_DDEBU= 3.3 V

Data Sheet

118

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Electrical ParametersDC Parameters

Table 18

Standard_Pads Class_B (cont’d)

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Fall time, class B pads;

edge= sharp ; pin out

driver= strong ²⁾

_FBCC

−

3.3

C_L= 20 pF;

_DDEBU1.53 V;

V_DDEBU≤ 1.98 V

−

5.0

3.0

2.5

7.0

4.0

3.3

12.0

7.0

6.0

C_L= 35 pF;

_DDEBU1.53 V;

V_DDEBU≤ 1.98 V

C_L= 35 pF;

_DDEBU2.375 ;

V_DDEBU≤ 2.625

C_L= 35 pF;

_DDEBU3.13 ;

V_DDEBU≤ 3.47

C_L= 50 pF;

_DDEBU1.53 V;

V_DDEBU≤ 1.98 V

C_L= 50 pF;

_DDEBU2.375 ;

V_DDEBU≤ 2.625

C_L= 50 pF;

_DDEBU3.13 ;

V_DDEBU≤ 3.47

C_L= 100 pF;

_DDEBU1.53 V;

V_DDEBU≤ 1.98 V

C_L= 100 pF;

_DDEBU2.375 ;

V_DDEBU≤ 2.625

C_L= 100 pF;

_DDEBU3.13 ;

V_DDEBU≤ 3.47

Data Sheet

119

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Electrical ParametersDC Parameters

Table 18

Standard_Pads Class_B (cont’d)

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Rise time, class B pads;

edge= sharp ; pin out

driver= strong ²⁾

_RBCC

−

3.3

C_L= 20 pF;

_DDEBU1.53 V;

V_DDEBU≤ 1.98 V

−

5.0

C_L= 35 pF;

_DDEBU1.53 V;

V_DDEBU≤ 1.98 V

3.0

C_L= 35 pF;

_DDEBU2.375 ;

V_DDEBU≤ 2.625

3.0

C_L= 35 pF;

_DDEBU3.13 ;

V_DDEBU≤ 3.47

7.0

C_L= 50 pF;

_DDEBU1.53 V;

V_DDEBU≤ 1.98 V

4.0

C_L= 50 pF;

_DDEBU2.375 ;

V_DDEBU≤ 2.625

3.7

C_L= 50 pF;

_DDEBU3.13 ;

V_DDEBU≤ 3.47

12.0

7.0

C_L= 100 pF;

_DDEBU1.53 V;

V_DDEBU≤ 1.98 V

C_L= 100 pF;

_DDEBU2.375 ;

V_DDEBU≤ 2.625

6.0

C_L= 100 pF;

_DDEBU3.13 ;

V_DDEBU≤ 3.47

Input high voltage, class B V_IHBCC 0.6 x

max(V

pads

V_DDEBU

DDEBU

+ 0.3,

3.6)

Data Sheet

120

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Electrical ParametersDC Parameters

Table 18

Standard_Pads Class_B (cont’d)

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Input low voltage, Class B

pads

_ILBCC -0.3

−

0.36 x

V_DDEBU

Output voltage high, class V_OHB

B pads

V_DDEBU

- 0.4

−

_OH-2 mA;

_OL= 2 mA

Output voltage low, class

B pads

_OLBCC −

0.4

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

2) For non strong driver and sharp edge settings see the class A2 definitions.

Table 19

Standard_Pads Class_F

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Input Hysteresis F¹⁾

HYSF

0.05 x

V_DDP

−

Input Leakage Current

Class F

_OZFCC -6000

−

6000

3000

V_i< V_DDP/ 2 -

1 V; V_i> V_DDP/2

+ 1 V; V_i≥ 0 V;

V_i≤ V_DDPV

-3000

−

V_i> V_DDP/ 2 -

1 V; V_i< V_DDP/2

+ 1 V

Ratio Vil/ Vih, F pads

V_ILF

0.6

−

_IHFCC

On-Resistance of the

class F pad, medium

driver

R_DSONM

170

145

Ohm I_OH> -2 mA;

P_MOS

−

Ohm I_OL< 2 mA;

N_MOS

Fall time, pad type F,

CMOS mode

_FFCC

_RFCC

−

C_L= 50 pF

Rise time, pad type F,

CMOS mode

−

C_L= 50 pF

Data Sheet

121

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Electrical ParametersDC Parameters

Table 19

Standard_Pads Class_F (cont’d)

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Input high voltage, pad

class F, CMOS mode

_IHFSR 0.6 x

−

min(V

DDP+

0.3,

V_DDP

3.6)

Input low voltage, Class F

pads, CMOS mode

_ILFSR -0.3

−

0.36 x

V_DDP

Output high voltage, class V_OHF

F pads, CMOS mode

V_DDP-

0.4

−

I_OH≥ -1.4 mA

2.4

−

I_OH≥ -2 mA

I_OL≤ 2 mA

Output low voltage, class

F pads, CMOS mode

_OLFCC −

0.4

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Table 20

Standard_Pads Class_I

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Input Hysteresis Class I¹⁾HYSI

0.1 x

−

V_DDP

Input Leakage Current

_OZICC -1000

_ILI/ V_IHI0.6

−

1000

Ratio between low and

high input threshold

−

Input high voltage, class I

pins

_IHISR 0.6 x

−

min(V

DDP+

0.3,

V_DDP

3.6)

Input low voltage, Class I

pads

_ILISR -0.3

−

0.36 x

V_DDP

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Class S pad parameters are only valid for V_DDM= 4.75 V to 5.25 V.

Data Sheet

122

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Electrical ParametersDC Parameters

Table 21

Standard_Pads Class_S

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Input Hysteresis for class HYSS

0.3

−

S pads¹⁾

Input leakage current

Input voltage high

Input voltage low

_OZSCC -300

−

300

3.6

−

_IHSCC

−

_ILSCC 1.9

_ILSDelta ²⁾

V_ILSD

-50

mV Maximum input

low state

treshold

variation over

1ms

(V_DDP= consta

nt)

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

2) V_ILSDis implemented to ensure J2716 specification. It can’t be guaranteed that it suppresses switching due to

external noise.

Table 22

LVDS_Pads Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

R_OCC 40

Max.

Output impedance, pad

class F, LVDS mode

140

Ohm

Fall time, pad type LVDS

_FLCC

−

termination

100 Ω ± 1 %;

differential

capacitance = 1

0 pF; input

capacitance = 2

0 pF

Data Sheet

123

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Electrical ParametersDC Parameters

Table 22

LVDS_Pads Parameters (cont’d)

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Rise time, pad type LVDS t_RLCC

−

termination

100 Ω ± 1 %;

differential

capacitance = 1

0 pF; input

capacitance = 2

0 pF

Pad set-up time

t_{SET_LVD}

_SCC

−

μs

termination

100 Ω ± 1 %

Output Differential Voltage V_ODCC 150

400

1525

−

mV termination

100 Ω ± 1 %

Output voltage high, pad

class F, LVDS mode

_OHCC

−

mV termination

100 Ω ± 1 %

Output voltage low, pad

class F, LVDS mode

_OLCC 875

mV termination

100 Ω ± 1 %

Output Offset Voltage

_OSCC 1075

1325

mV termination

100 Ω ± 1 %

Data Sheet

124

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TC1798

Electrical ParametersDC Parameters

5.2.2

Analog to Digital Converters (ADCx)

ADC parameter are valid for V_{DD / DDAF}= 1.235 V to 1.365 V; V_DDM= 4.5 V to 5.5 V.

Table 23

ADC Parameters

Symbol

Parameter

Values

Typ.

Unit Note /

Test Condition

Min.

Max.

Switched capacitance at C_AINSW

−

the analog voltage inputs¹⁾CC

Total capacitance of an

analog input

C_AINTOT

−

Switched capacitance at C_AREFSW

the positive reference

voltage input²⁾³⁾

Total capacitance of the

C_AREFTO

−

voltage reference inputs²⁾_TCC

Differential Non-Linearity EA_DNL

-3

−

LSB ADC

Error^4)5)6)7)

resolution= 12-

bit ^{8) 9)}

LSB ADC

Gain Error^4)5)6)7)

EA_GAIN-3.5

−

3.5

resolution= 12-

bit ^{8) 9)}

Integral Non-

Linearity^4)5)7)7)

EA_INL

-3

LSB ADC

resolution= 12-

bit ^{8) 9)}

ADC = 0,1,2

LSB ADC

;

−

resolution= 12-

bit ^{8) 9)}

ADC3 and

_AIN≤ V_AREFx

0.15 V

LSB ADC

-15

resolution= 12-

bit ^{8) 9)}

ADC3 and

V_AREFx

0.15 V ≤ V_AIN

V_AREFx

Data Sheet

125

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Electrical ParametersDC Parameters

Table 23

ADC Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

-4

Max.

Offset Error^4)5)6)7)

EA_OFF

LSB ADC

resolution= 12-

bit ^{8) 9)}

_ADC= f_FPI

Converter clock

_ADCSR

−

100

MHz f

Internal ADC clock

_ADCICC 1

−

MHz ADC0

MHz ADC1

MHz ADC2

MHz ADC3

−

20¹⁰⁾

−

Charge consumption per Q_CONV

conversion CC

85¹¹⁾

100

chargeneedsto

be provided via

V_AREF0

Data Sheet

126

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Electrical ParametersDC Parameters

Table 23

ADC Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

_OZ1CC -100

Max.

Input leakage at analog

inputs¹²⁾

500

V_i≤ V_DDMV;

V_i≥ 0.97 x

_DDMV;

overlayed= No

-100

-500

-600

-100

−

600

100

200

V_i≥ 0.97 x

_DDMV;

V_i≤ V_DDMV;

overlayed= Yes

V_i≤ 0.03 x

_DDMV;

V_i≥ 0 V;

overlayed= No

V_i≤ 0.03 x

_DDMV;

V_i≥ 0 V;

overlayed= Yes

V_i> 0.03 x

_DDMV;

V_i< 0.97 x

_DDMV;

overlayed= No

-100

−

300

V_i< 0.97 x

_DDMV;

V_i> 0.03 x

_DDMV;

overlayed= Yes

Input leakage current at

V_AREFx

_OZ2CC -1

_OZ3CC -1

−

μA

V_AREFx≥ 0 V;

V_AREFx≤ V_DDMV

Input leakage current at

−

μA

V_AGNDx≥ 0 V;

V_AGNDx

V_AGNDx≤ V_DDMV

ON resistance of the

transmission gates in the

analog voltage path

_AINCC

−

900

1500

Ohm

ON resistance for the ADC R_AIN7T

180

550

900

Ohm

test (pull down for AIN7)

Data Sheet

127

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TC1798

Electrical ParametersDC Parameters

Table 23

ADC Parameters (cont’d)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Min.

Max.

Resistance of the

reference voltage input

path

R_AREF

−

500

1000

Ohm

Sample time

t_SCC

−

257

T_ADCI

Calibration time after bit

ADC_GLOBCFG.SUCAL

is set

_CALCC

−

4352

cycle

Total Unadjusted

Error^6)5)13)

TUE CC -4

−

4¹⁴⁾

LSB ADC

resolution= 12-

bit

ADC = 0,1,2

-4

4¹⁴⁾

LSB ADC

resolution= 12-

bit ^{8) 9)}

ADC3 and

_AIN≤ V_AREFx

0.15 V

LSB ADC

-14

−

14¹⁴⁾

resolution= 12-

bit ^{8) 9)}

ADC3 and

V_AREFx

0.15 V ≤ V_AIN

V_AREFx

Analog reference ground²⁾V_AGNDxV_SSM

SR 0.05

_AINSR V_AGNDx

Analog reference voltage²⁾V_AREFxV_AGNDx

−

V_AREFx

- 1

Analog input voltage

−

V_AREFx

_DDM+ V

+ 1

0.05¹⁵⁾

16)

Analog reference voltage V_AREFx

_DDM/2 −

0.05

_DDM+ V

range⁶⁾⁵⁾²⁾

V_AGNDx

1) The sampling capacity of the conversion C-network is pre-charged to V_AREFx/2 before the sampling moment.

Because of the parasitic elements the voltage measured at AINx can deviate from V_AREFx/2.

2) Applies to AINx, when used as auxiliary reference input.

Data Sheet

128

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Electrical ParametersDC Parameters

3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage

at once. Instead smaller capacitances are successively switched to the reference voltage.

4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.

5) If a reduced analog reference voltage between 1V and V_DDM/ 2 is used, then there are additional decrease in

the ADC speed and accuracy.

6) If the analog reference voltage range is below V_DDMbut still in the defined range of V_DDM/ 2 and V_DDMis used,

then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),

TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.

7) If the analog reference voltage is > V_DDM, then the ADC converter errors increase.

8) For 10-bit conversions the error value must be multiplied with a factor 0.25.

9) For 8-bit conversions the error value must be multiplied with a factor 0.0625.

10) For f_ADCIbetween 18MHz and 20MHz the TUE and Gain Error can increase beyond the given limits. For

STC < 2 INL, DNL , and Offset errors can also increase.

11) For a conversion time of 1 µs a rms value of 85µA result for I_AREFx.

12) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The

numerical values defined determine the characteristic points of the given continuous linear approximation -

they do not define step function.

13) Measured without noise.

14) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB

15) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).

16) If the reference voltage V_AREFxincrease or the V_DDMdecrease, so that V_AREF= (V_DDM+ 0.05V to V_DDM+ 0.07V),

then the accuracy of the ADC decrease by 4LSB12.

Table 24

Conversion Time (Operating Conditions apply)

Parameter

Symbol Values

Unit Note

Conversion

time with

t_CCC 2 × T_ADC+ (4 + STC + n) × T_ADCIμs

n = 8, 10, 12 for

n - bit conversion

post-calibration

_ADC= 1 / f_FPI

_ADCI= 1 / f_ADCI

Conversion

2 × T_ADC+ (2 + STC + n) × T_ADCI

time without

post-calibration

The power-up calibration of the ADC requires a maximum number of 4352 f_ADCIcycles.

Data Sheet

129

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Electrical ParametersDC Parameters

Analog Input Circuitry

R_{AIN, On}

R_EXT

ANx

V_AIN

C_EXT

C_AINSW

_AINTOT- C_AINSW

V_AGNDx

R_AIN7T

Reference Voltage Input Circuitry

R_{AREF, On}

V_AREFx

V_AREF

_AREFTOT- C_AREFSW

C_AREFSW

V_AGNDx

Analog_InpRefDiag

Figure 6

ADCx Input Circuits

Data Sheet

130

V 1.1, 2014-05

TC1798

Electrical ParametersDC Parameters

Ioz1

Single ADC Input

500nA

200nA

100nA

VIN[VDDM%]

-100nA

97%100%

-500nA

Ioz1

Overlayed ADC/FADC Input

600nA

300nA

100nA

VIN[VDDM%]

-100nA

97%100%

-600nA

Figure 7

ADCx Analog Inputs Leakage

Data Sheet

131

V 1.1, 2014-05

TC1798

Electrical ParametersDC Parameters

5.2.3

Fast Analog to Digital Converter (FADC)

FADC parameter are vaild for V_{DD / DDAF}= 1.235 V to 1.365 V; V_DDMF= 2.97 V to 3.6 V.

Table 25

FADC Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Input current at VFAREF I_FAREF

−

120

μA

Input leakage current at

VFAREF¹⁾

I_FOZ2

-500

-1

−

500

V_FAREF≤ V_DDMF

V; V_FAREF≥ 0 V

Input leakage current at

VFAGND

I_FOZ3

DNL error

EF_DNL

LSB

V_INmode=

differential;

Gain = 1 or 2

-2

-1

-2

−

LSB

V_INmode=

differential;

Gain = 4 or 8²⁾

_INmode=

single ended;

Gain = 1 or 2

_INmode=

single ended;

Gain = 4 or 8²⁾

GRADient error

EF_GRAD-5

V_INmode=

differential ;

Gain≤ 4

-5

-6

V_INmode=

single ended ;

Gain≤ 4

V_INmode=

differential ;

Gain= 8

V_INmode=

single ended ;

Gain= 8

Data Sheet

132

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Electrical ParametersDC Parameters

Table 25

FADC Parameters (cont’d)

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

INL error

EF_INL

-4

LSB

_INmode=

differential

_INmode=

single ended

_INmode=

-4

−

Offset error

EF_OFF

-90

differential ;

Calibration= No

-90

-20

−

V_INmode=

single ended ;

Calibration= No

_INmode=

differential ;

Calibration= Ye

s ³⁾⁴⁾

-20

−

V_INmode=

single ended ;

Calibration= Ye

s ³⁾⁴⁾

Error of commen mode

voltage V_FAREF/2

EF_REF

-60

−

Channel amplifier cutoff

frequency

f_COFF

MHz

1 /

Converter clock

f_FADC

100

200

_FADC= f_FPI

Conversion time

t_CCC

−

For 10-bit

f_FADCconversion

Input resistance of the

analog voltage path (Rn, CC

R_FAIN

100

kOh

Rp)

Settling time of a channel

amplifier after changing

ENN or ENP

_SETCC

−

μs

Analog input voltage

range

V_AINF

V_FAGND

V_DDMF

Data Sheet

133

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Electrical ParametersDC Parameters

Table 25

FADC Parameters (cont’d)

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Analog reference ground V_FAGNDV_SSAF

SR 0.05

V_SSAF

+ 0.05

Analog reference voltage V_FAREF2.97

−

3.63⁵⁾

1) This value applies in power-down mode.

2) No missing codes.

3) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed

minimium once per week.

4) The offser error voltage drifts over the whole temperature range maximum +-3LSB.

5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum

of the pulses does not exceed 1 h.

6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage

overshoots).

The calibration procedure should run after each power-up, when all power supply

voltages and the reference voltage have stabilized.

Data Sheet

134

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TC1798

Electrical ParametersDC Parameters

FADC Analog Input Stage

R_N

FAINxN

V_FAREF/2

V_FAGND

R_P

FAINxP

FADC Reference Voltage

Input Circuitry

V_FAREF

I_FAREF

V_FAREF

V_FAGND

FADC_InpRefDiag

Figure 8

FADC Input Circuits

Data Sheet

135

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TC1798

Electrical ParametersDC Parameters

5.2.4

Oscillator Pins

Table 26

OSC_XTAL Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

_IX1CC -25

Max.

Input current at XTAL1

Input frequency

μA

V_IN<V_DDOSC3

V_IN>0 V

;

_OSCSR

−

MHz Direct Input

Mode selected

MHz ExternalCrystal

Mode selected

Oscillator start-up time¹⁾

t_OSCS

Input high voltage at

XTAL1²⁾

_IHXSR 0.7 x

V_DDOS

0.5

Input low voltage at

XTAL1

_ILXSR -0.5

−

0.3 x

V_DDOS

Input Hysteresis for

XTAL1 pad ³⁾

HYSAX

−

200

t_OSCSis defined from the moment when V_DDOSC3= 3.13V until the oscillations reach an amplitude at XTAL1 of

0.3 * V_DDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative

resistance as recommended and specified by crystral suppliers.

2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * V_DDOSC3is

necessary.

3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Note: It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimal parameters

for the oscillator operation. Please refer to the limits specified by the crystal or

ceramic resonator supplier.

Data Sheet

136

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TC1798

Electrical ParametersDC Parameters

5.2.5

Temperature Sensor

Table 27

DTS Parameters

Symbol

Parameter

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

100

Measurement time

t_MCC

−

μs

Temperature sensor

range

_SRSR -40

150

°C

Sensor Accuracy

(calibrated)

_TSACC -6

−

°C

Start-up time after resets

inactive

_TSSTSR −

μs

The following formula calculates the temperature measured by the DTS in [^oC] from the

RESULT bit field of the DTSSTAT register.

(1)

DTSSTATRESULT – 596

Tj = ------------------------------------------------------------------

2, 03

Data Sheet

137

V 1.1, 2014-05

TC1798

Electrical ParametersDC Parameters

5.2.6

Power Supply Current

The total power supply current defined below consists of leakage and switching

component.

Application relevant values are typically lower than those given in the following two

tables and depend on the customer's system operating conditions (e.g. thermal

connection or used application configurations).

The operating conditions for the parameters in the following table are:

VDD / V_DDOSC/ V_DDAF/ V_DDPF=1.365 V, VDDP / V_DDOSC/ V_DDMF/ V_DDFL3/ V_DDPF=3.47 V,

fSRI / CPU=300 MHz, fPCP=200 MHz, fSRI=100 MHz, TJ=150 oC

The realisic power pattern defines the following conditions:

•

TJ=150 oC

_SRI= f_CPU= 300 MHz

_PCP= 200 MHz

_FPI= 100 MHz

_DD= V_DDOSC= V_DDAF= V_DDPF= 1.326 V

_DDP= V_DDOSC3= V_DDFL3V_DDPF3= V_DDMF= 3.366 V

_DDM= 5.1 V

The max power pattern defines the following conditions:

•

TJ=150 oC

_SRI= f_CPU= 300 MHz

_PCP= 200 MHz

_FPI= 100 MHz

_DD= V_DDOSC= V_DDAF= V_DDPF= 1.43 V

_DDP= V_DDOSC3= V_DDFL3V_DDPF3= V_DDMF= 3.63 V

_DDM= 5.5 V

Table 28

Power Supply Parameters

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

890³⁾

Core active mode supply

current¹⁾²⁾

_DDCC

−

mA power

pattern= max;

fCPU=300 MHz

mA power

−

656⁴⁾

pattern= realisti

fCPU=300 MHz

I_DDcurrent at PORST Low I_{DD_PORS}

−

298

249

mA TJ=150 oC

mA TJ=140 oC

_TCC

Data Sheet

138

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TC1798

Electrical ParametersDC Parameters

Table 28

Power Supply Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

E-Ray PLL core supply

current

I_DDPF

−

Oscillator core supply

current

I_DDOSC

−

FADC core supply current I_DDAF

689

Sum of all 1.3 V supply

currents

I_DDSUM

mA power

pattern= realisti

fCPU=300 MHz

E-Ray PLL 3.3V supply

I_DDPF3

−

Oscillator power supply

current, 3.3V

I_DDOSC3

FADC analog supply

current, 3.3V

I_DDMF

_DDEBUcurrent at PORST I_{DDEBU_P}

Low

_ORSTCC

_DDPcurrent at PORST

Low

_DDPcurrent no pad

activity, LVDS off ⁵⁾

I_{DDP_POR}

_STCC

_DDPCC

I_{DDP_P}mA including flash

read current

ORST

−

I_{DDP_P}mA including flash

programming

ORST

current ⁶⁾

I_{DDP_P}mA including flash

erase verify

ORST

40 ⁷⁾

current ⁶⁾

Data Sheet

139

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TC1798

Electrical ParametersDC Parameters

Table 28

Power Supply Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Flash memory current ⁵⁾

I_DDFL3

−

mA flash read

current

−

mA flash

programming

current ⁶⁾

−

mA flash erase

current ⁶⁾

Current Consumption of

LVDS Pad Pairs

I_LVDS

mA in total for all

LVDS pairs

Sum of all 3.3 V supply

currents, no pad activity, CC

I_DD3SUM

161 ⁸⁾mA including flash

read current

LVDS off

ADC 5V power supply

current

_DDMCC −

−

Maximum power

dissipation

PD CC

−

1808

mW power

pattern= max;

fCPU=300 MHz

mW power

−

1547

pattern= realisti

fCPU=300 MHz

1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer

application will most probably be lower than this value, but must be evaluated seperately.

2) This current includes the E-Ray module power consumption, including the PCP operation component.

3) The I_DDdecreases typically by 89mA if the f_CPUdecreases by 50MHz, at constant T_J

4) The I_DDdecreases typically by 70mA if the f_CPUdecreases by 50MHz, at constant T_J

5) For operations including the D-Flash the required currents are always lower than the currents for non D-Flash

operation.

6) Relevant for the power supply dimensioning, not for thermal considerations.

7) In case of erase of Program Flash PFx, internal flash array loading effects may generate transient current

spikes of up to 15 mA for maximum 5 ms per flash module.

8) For power supply dimensioning of V_DDP30 mA have to added for flash programming case.

5.2.6.1 Calculating the 1.3 V Current Consumption

The current consumption of the 1.3 V rail compose out of two parts:

•

Static current consumption

Data Sheet

140

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TC1798

Electrical ParametersDC Parameters

•

Dynamic current consumption

The static current consumption is related to the device temperature T_Jand the dynamic

current consumption depends of the configured clocking frequencies and the software

application executed. These two parts needs to be added in order to get the rail current

consumption.

(2)

0, 02041 × T

--------

= 3, 75

× e

[C]

(3)

--------

0, 01825 × T

= 18, 77

× e

[C]

Function 2 defines the typical static current consumption and Function 3 defines the

maximum static current consumption. Both functions are valid for V_DD= 1.326 V.

For the dynamic current consumption using the application pattern and f_SRI

= 2 * f_PCP= 3 * f_FPIthe function 4 applies:

(4)

------------

MHz

= 1, 19

× f

[MHz]

D m

CPU

and this finally results in

(5)

= I + I

DYM

Data Sheet

141

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TC1798

Electrical ParametersAC Parameters

5.3

AC Parameters

That means, keeping the pads constantly at maximum strength.

5.3.1

Testing Waveforms

V_DDP

90%

10%

V_SS

t_R

t_F

rise_fall

Figure 9

Rise/Fall Time Parameters

V_DDP

V_DDE/ 2

Test Points

V_DDE/ 2

V_SS

mct04881_a.vsd

Figure 10

Testing Waveform, Output Delay

V_Load+ 0.1 V

V_Load- 0.1 V

V_OH- 0.1 V

Timing

Reference

Points

V_OL- 0.1 V

MCT04880_new

Figure 11

Testing Waveform, Output High Impedance

Data Sheet

142

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TC1798

Electrical ParametersAC Parameters

5.3.2

Power Sequencing

5.25V

4.75V

3.47V

V_AREF

3.3V

1.3V

3.0V

-12%

1.365V

1.235V

0.5V

-12%

0.5V

V_DDP

PORST

power

down

power

fail

Power-Up 10.vsd

Figure 12

5 V / 3.3 V / 1.3 V Power-Up/Down Sequence

The following list of rules applies to the power-up/down sequence:

•

All ground pins V_SSmust be externally connected to one single star point in the

system. Regarding the DC current component, all ground pins are internally directly

connected.

At any moment in time to avoid increased latch-up risk,

each power supply must be higher then any lower_power_supply - 0.5 V, or:

VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.3 - 0.5 V;VDD3.3 > VDD1.3 - 0.5 V, see

Figure 12.

– The latch-up risk is minimized if the I/O currents are limited to:

– 20 mA for one pin group

– AND 100 mA for the completed device I/Os

– AND additionally before power-up / after power-down:

1 mA for one pin in inactive mode (0 V on all power supplies)

During power-up and power-down, the voltage difference between the power supply

pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example

VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than

•

Data Sheet

143

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TC1798

Electrical ParametersAC Parameters

100 mV. On the other hand, all power supply pins with the same name (for example

all VDDP), are internally directly connected. It is recommended that the power pins

of the same voltage are driven by a single power supply.

•

The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF

power-supplies and the oscillator have reached stable operation, within the normal

operating conditions.

At normal power down the PORST signal should be activated within the normal

operating range, and then the power supplies may be switched off. Care must be

taken that all Flash write or delete sequences have been completed.

At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V

power supply voltage falls 12% below the nominal level. If, under these conditions,

the PORST is activated during a Flash write, only the memory row that was the target

of the write at the moment of the power loss will contain unreliable content. In order

to ensure clean power-down behavior, the PORST signal should be activated as

close as possible to the normal operating voltage range.

•

In case of a power-loss at any power-supply, all power supplies must be powered-

down, conforming at the same time to the rules number 2 and 4.

Although not necessary, it is additionally recommended that all power supplies are

powered-up/down together in a controlled way, as tight to each other as possible.

Additionally, regarding the ADC reference voltage VAREF:

– VAREF must power-up at the same time or later then VDDM, and

– VAREF must power-down either earlier or at latest to satisfy the condition

VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF

filter capacitance through the ESD diodes through the VDDM power supply. In

case of discharging the reference capacitance through the ESD diodes, the

current must be lower than 5 mA.

Data Sheet

144

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TC1798

Electrical ParametersAC Parameters

5.3.3

Power, Pad and Reset Timing

Reset Timings Parameters

Table 29

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

Application Reset Boot

Time¹⁾²⁾

t_BCC

−

880

μs

f_CPU= 300 MHz

Power on Reset Boot

Time³⁾⁴⁾

_BPCC

−

2.5

−

HWCFG pins hold time

from ESR0 rising edge

_HDHSR 16 /

f_FPI

HWCFG pins setup time to t_HDSSR

ESR0 rising edge

−

Ports inactive after ESR0

reset active

_PICC

8/f_FPI

150

−

Ports inactive after

_PIPCC

PORST reset active⁵⁾

Minimum PORST active

time after power supplies

are stable at operating

levels

_POASR 10

TESTMODE / TRST hold

time from PORST rising

edge

_POHSR 100

−

PORST rise time

_PORSR

_POSSR

−

TESTMODE / TRST

setup time to PORST

rising edge

−

Application Reset inactive t_{POR_APP}

−

40 ⁶⁾

μs

after PORST deassertion SR

1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock

cycle when the first user instruction has entered the CPU pipeline and its processing starts.

2) The given time includes the time of the internal reset extension for

SCU_RSTCNTCON.RELSA = 0x05BE.

a configured value of

3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the

first user instruction has entered the CPU pipeline and its processing starts.

Data Sheet

145

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Electrical ParametersAC Parameters

4) The given time includes the internal reset extension time for the System and Application Reset which is visible

through ESR0.

5) This parameter includes the delay of the analog spike filter in the PORST pad.

6) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the

Application Reset is extended.

V_DDP-12%

V_DDPPA

VDDP

VDD

V_DD-12%

t_POA

PORST

t_POH

TRST

TESTMODE

t_hd

ESR0

t_HDH

HWCFG

t_PIP

t _PIP

t_PI

Pads

t_PI

t _PIP

Pad-state undefined

Tri-state or pull device active

As programmed

reset_beh2

Figure 13

Power, Pad and Reset Timing

Data Sheet

146

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TC1798

Electrical ParametersAC Parameters

5.3.4

Phase Locked Loop (PLL)

Table 30

PLL_SysClk Parameters

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Accumulated Jitter

Modulation frequency

PLL base frequency

D_PCC -7

_MODSR 50

−

200

320

kHz

MHz

f_PLLBASE50

200

VCO input frequency

VCO frequency range

_REFCC

−

MHz

_VCOCC 400

720

MHz with inactive

modulation

400

−

600

MHz with active

modulation

Modulation jitter

_MODCC −

−

2.5

Total long term jitter

Modulation Amplitude

PLL lock-in time

J_TOTCC

−

9.5

MA SR

t_LCC

2.5

−

200

400

0.01

μs

N > 32

N ≤ 32

System frequency

deviation

f_SYSD

with active

modulation

Phase Locked Loop Operation

When PLL operation is enabled and configured, the PLL clock f_VCO(and with it the SRI-

Bus clock f_SRI) is constantly adjusted to the selected frequency. The PLL is constantly

adjusting its output frequency to correspond to the input frequency (from crystal or clock

source), resulting in an accumulated jitter that is limited. This means that the relative

deviation for periods of more than one clock cycle is lower than for a single clock cycle.

This is especially important for bus cycles using wait states and for the operation of

timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train

generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter

is negligible.

Data Sheet

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Electrical ParametersAC Parameters

Two formulas are defined for the (absolute) approximate maximum value of jitter D_min

[ns] dependent on the K2 - factor, the SRI clock frequency f_SRIin [MHz], and the number

m of consecutive f_SRIclock periods.

for

(K2 ≤ 100)

and

(m ≤ (f_SRI[MHz]) ⁄ 2)

(6)

(7)

740

(1 – 0, 01 × K2) × (m – 1)

0, 5 × f_SRI[MHz] – 1

⎛

⎞

+ 5 ×

⎠

⎛

⎝

⎞

-----------------------------------------

----------------------------------------------------------------

Dm[ns] =

+ 0, 01 × K2

⎝

⎠

K2 × f_SRI[MHz]

740

-----------------------------------------

+ 5

else

Dm[ns] =

K2 × f_SRI[MHz]

With rising number m of clock cycles the maximum jitter increases linearly up to a value

of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum

accumulated jitter remains at a constant value. Further, a lower SRI-Bus clock frequency

_SRIresults in a higher absolute maximum jitter value.

Note: The specified PLL jitter values are valid if the capacitive load per pin does not

exceed C_L= 20 pF with the maximum driver and sharp edge.

Note: The maximum peak-to-peak noise on the pad supply voltage, measured between

_DDOSC3and V_SSOSC, is limited to a peak-to-peak voltage of V_PP= 100 mV for noise

frequencies below 300 KHz and V_PP= 40 mV for noise frequencies above

300 KHz.

The maximum peak-to peak noise on the pad supply voltage, measured between

_DDOSCand V_SSOSC, is limited to a peak-to-peak voltage of V_PP= 100 mV for noise

frequencies below 300 KHz and V_PP= 40 mV for noise frequencies above

300 KHz.

These conditions can be achieved by appropriate blocking of the supply voltage

as near as possible to the supply pins and using PCB supply and ground planes.

Oscillator Watchdog (OSC_WDT)

The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The

OSC_WDT checks for too low frequencies and for too high frequencies.

The frequency that is monitored is f_OSCREFwhich is derived for f_OSC

(8)

OSC

----------------------------------

OSCREF

OSCVAL + 1

The divider value SCU_OSCCON.OSCVAL has to be selected in a way that f_OSCREFis

2.5 MHz.

Data Sheet

148

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Electrical ParametersAC Parameters

Note: f_OSCREFhas to be within the range of 2 MHz to 3 MHz and should be as close as

possible to 2.5 MHz.

The monitored frequency is too low if it is below 1.25 MHz and too high if it is above

7.5 MHz. This leads to the following two conditions:

•

Too low: f_OSC< 1.25 MHz × (SCU_OSCCON.OSCVAL+1)

Too high: f_OSC> 7.5 MHz × (SCU_OSCCON.OSCVAL+1)

Note: The accuracy is 30% for these boundaries.

Frequency Modulation

Frequency modulation defines a slow and predictable variation of the clock speed. The

modulation configuration itself is controlled via register SCU_PLLCON2 where the two

bit fields define the modulation properties.

(9)

OSC MODFREQ × 31, 32

-------------- ----------------------------------------------------

MOD

MODAMP

(10)

MODAMP

N × 161

----------------------------

MA =

Data Sheet

149

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TC1798

Electrical ParametersAC Parameters

5.3.5

ERAY Phase Locked Loop (ERAY_PLL)

Table 31

PLL_ERAY Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

_PPCC -0.8

Max.

Accumulated jitter at

SYSCLK pin

0.8

Accumulated_Jitter

D_PCC -0.5

−

0.5

PLL Base Frequency of

the ERAY PLL

f_{PLLBASE_}50

_ERAYCC

250

360

MHz

VCO input frequency of

the ERAY PLL

_REFCC 20

−

MHz

μs

VCO frequency range of f_{VCO_ERA}450

the ERAY PLL

500

200

_YCC

PLL lock-in time

t_LCC

5.6

Note: The specified PLL jitter values are valid if the capacitive load per pin does not

exceed C_L= 20 pF with the maximum driver and sharp edge.

Note: The maximum peak-to-peak noise on the pad supply voltage, measured between

_DDPF3and V_SSPF, is limited to a peak-to-peak voltage of V_PP= 100 mV for noise

frequencies below 300 KHz and V_PP= 40 mV for noise frequencies above

300 KHz.

These conditions can be achieved by appropriate blocking of the supply voltage

as near as possible to the supply pins and using PCB supply and ground planes.

Data Sheet

150

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Electrical ParametersAC Parameters

5.3.6

JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug

interface. The JTAG module is fully compliant with IEEE1149.1-2000.

Note: These parameters are not subject to production test but verified by design and/or

characterization.

Table 32

JTAG Interface Timing Parameters

(Operating Conditions apply)

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

–

Typ.

Max.

TCK clock period

TCK high time

t1 SR

t2 SR

t₃SR

t₄SR

t₅SR

t6 SR

–

TCK low time

TCK clock rise time

TCK clock fall time

–

TDI/TMS setup

to TCK rising edge

TDI/TMS hold

t₇SR

–

after TCK rising edge

TDO valid after TCK falling t₈CC

–

C_L= 50 pF

C_L= 20 pF

edge¹⁾(propagation delay)

t₈CC

TDO hold after TCK falling t₁₈CC

–

edge¹⁾

TDO high imped. to valid t₉CC

–

C_L= 50 pF

from TCK falling edge¹⁾²⁾

TDO valid to high imped.

from TCK falling edge¹⁾

₁₀CC

13.5

1) The falling edge on TCK is used to generate the TDO timing.

2) The setup time for TDO is given implicitly by the TCK cycle time.

Data Sheet

151

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Electrical ParametersAC Parameters

t₁

0.9 V_DDP

0.1 V_DDP

0.5 V_DDP

t₅

t₄

t₂

t₃

MC_JTAG_TCK

Figure 14

Test Clock Timing (TCK)

TCK

t₆

t₇

TMS

t₆

t₇

TDI

t₉

t₈

t₁₀

TDO

t₁₈

MC_JTAG

Figure 15

JTAG Timing

Data Sheet

152

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TC1798

Electrical ParametersAC Parameters

5.3.7

DAP Interface Timing

The following parameters are applicable for communication through the DAP debug

interface.

Note: These parameters are not subject to production test but verified by design and/or

characterization.

Table 33

DAP Parameters

Symbol

Parameter

Values

Unit Note /

Test Condition

Min.

_TCKSR 12.5

Typ.

Max.

DAP0 clock period¹⁾

DAP0 high time

DAP0 low time¹⁾

−

₁₂SR

₁₃SR

₁₄SR

₁₅SR

₁₆SR

DAP0 clock rise time

DAP0 clock fall time

−

DAP1 setup to DAP0

rising edge

6.0

DAP1 hold after DAP0

rising edge

₁₇SR

₁₉CC

6.0

−

DAP1 valid per DAP0

clock period²⁾

C_L= 20 pF;

f= 80 MHz

C_L= 50 pF;

f= 40 MHz

1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.

2) The Host has to find a suitable sampling point by analyzing the sync telegram response.

t₁₁

0.9 V_DDP

0.1 V_DDP

0.5 V_DDP

t₁₅

t₁₄

t₁₂

t₁₃

MC_DAP0

Figure 16

Test Clock Timing (DAP0)

Data Sheet

153

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Electrical ParametersAC Parameters

DAP0

DAP1

t₁₆

t₁₇

MC_DAP1_RX

Figure 17

DAP Timing Host to Device

t₁₁

DAP1

t₁₉

MC_DAP1_TX

Figure 18

5.3.8

DAP Timing Device to Host

Micro Link Interface (MLI) Timing

Data Sheet

154

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TC1798

Electrical ParametersAC Parameters

MLI Transmitter Timing

t₁₃

t₁₄

t₁₀

t₁₂

TCLKx

t₁₁

t₁₅

TDATAx

TVALIDx

t₁₆

t₁₇

TREADYx

MLI Receiver Timing

t₂₃

t₂₄

t₂₀

t₂₂

RCLKx

t₂₁

t₂₅

t₂₆

RDATAx

RVALIDx

t₂₇

RREADYx

MLI_Tmg_2.vsd

Figure 19

MLI Interface Timing

Note: The generation of RREADYx is in the input clock domain of the receiver. The

reception of TREADYx is asynchronous to TCLKx.

The MLI parameters are vaild for C_L= 50 pF and strong driver medium edge.

Data Sheet

155

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Electrical ParametersAC Parameters

Table 34

MLI Receiver

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

1 / f_FPI

−

Max.

RCLK clock period

RCLK high time¹⁾²⁾

₂₀SR

₂₁SR

−

0.5 x

t₂₀

RCLK low time¹⁾²⁾

₂₂SR

−

0.5 x

−

t₂₀

RCLK rise time³⁾

RCLK fall time³⁾

₂₃SR

₂₄SR

₂₅SR

−

RDATA/RVALID setup

time before RCLK falling

edge

4.2

RDATA/RVALID hold time t₂₆SR

after RCLK falling edge

2.2

−

RREADY output delay

time

₂₇SR

1) The following formula is valid: t21 + t22 = t20.

2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver

timing parameters.

3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower

input signal rise/fall times can be used for longer RCLK clock periods.

Table 35

MLI Transmitter

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

TCLK clock period

TCLK high time¹⁾²⁾

TCLK low time¹⁾²⁾

TCLK rise time

₁₀CC

₁₁CC

₁₂CC

₁₃CC

₁₄CC

2 x 1 /

f_FPI

−

0.45 x 0.5 x

t₁₀t₁₀

0.45 x 0.5 x

0.55 x ns

t₁₀

0.55 x ns

t₁₀

−

0.3 x

t₁₀

TCLK fall time

−

0.3 x

t₁₀

Data Sheet

156

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Electrical ParametersAC Parameters

Table 35

MLI Transmitter (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

-3

Max.

TDATA/TVALID output

delay time

₁₅CC

₁₆SR

₁₇SR

4.4

TREADY setup time

before TCLK rising edge

-2

−

TREADY hold time after

TCLK rising edge

1) The following formula is valid: t11 + t12 = t10.

2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be

regarded additionally to t11 / t12.

3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended

for TCLK.

5.3.9

Micro Second Channel (MSC) Interface Timing

The MSC parameters are vaild for C_L= 50 pF.

Table 36

MSC Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

FCLP clock period¹⁾²⁾

₄₀CC

₄₅CC

2 x

T_MSC

−

SOP⁴⁾/ENx outputs delay

from FCLP⁴⁾rising edge

-2

−

ENx with strong

driver and

sharp (minus )

edge

−

ENx with strong

driver and

medium

(minus) edge

−

ENx with strong

driver and soft

edge

SDI bit time

Data Sheet

₄₆CC

8 x

T_MSC

−

157

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Electrical ParametersAC Parameters

Table 36

MSC Parameters (cont’d)

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

200

SDI rise time

SDI fall time

₄₈SR

₄₉SR

−

200

1) FCLP signal rise/fall times are only defined by the pad rise/fall times.

2) FCLP signal high and low can be minimum 1xT_MSC

3) TMSC = TSYS = 1 / fSYS.

4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge.

t₄₀

0.9 V_DDP

0.1 V_DDP

FCLP

t₄₅

SOP

t₄₈

t₄₉

0.9 V_DDP

0.1 V_DDP

SDI

t₄₆

MSC Interface Timing

t₄₆

MSC_Tmg_1.vsd

Figure 20

Note: The data at SOP should be sampled with the falling edge of FCLP in the target

device.

Data Sheet

158

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TC1798

Electrical ParametersAC Parameters

5.3.10

SSC Master/Slave Mode Timing

The SSC parameters are vaild for C_L= 50 pF and strong driver medium edge.

Table 37

SSC Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

SCLK clock period¹⁾²⁾³⁾

₅₀CC

₅₁CC

₅₂SR

₅₃SR

₅₄SR

2 x 1 /

f_FPI

−

MTSR/SLSOx delay form

SCLK rising edge

−

MRST setup to SCLK

latching edge³⁾

16.5

−

MRST hold from SCLK

latching edge³⁾

−

SCLK input clock

period¹⁾³⁾

4 x 1 /

f_FPI

−

SCLK input clock duty

cycle

t₅₅_t₅₄

−

MTSR setup to SCLK

latching edge³⁾⁴⁾

₅₆SR

₅₇SR

₅₈SR

₅₉SR

₆₀CC

₆₁CC

1 / f_FPI

MTSR hold from SCLK

latching edge

1 / f_FPI

+ 5

−

SLSI setup to first SCLK

latching edge

1 / f_FPI

+ 5

−

SLSI hold from last SCLK

latching edge⁵⁾

−

MRST delay from SCLK

shift edge

16.5

SLSI to valid data on

MRST

1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.

2) SCLK signal high and low times can be minimum 1xTSSC.

3) TSSCmin = TSYS = 1/fSYS.

4) Fractional divider switched off, SSC internal baud rate generation used.

Data Sheet

159

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Electrical ParametersAC Parameters

5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever

is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair

of shifting / latching edges.

t₅₀

SCLK¹⁾²⁾

t₅₁

MTSR¹⁾

t₅₂

t₅₃

Data

valid

MRST¹⁾

t₅₁

SLSOn²⁾

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0

and the first SCLK high pulse is in the first one of a transmission.

SSC_TmgMM

Figure 21

SSC Master Mode Timing

Data Sheet

160

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Electrical ParametersAC Parameters

t₅₄

First latching

SCLK edge

Last latching

SCLK edge

First shift

SCLK edge

SCLK¹⁾

t₅₅

t₅₆

t₅₇

Data

valid

Data

valid

MTSR¹⁾

MRST¹⁾

SLSI

t₆₀

t₆₁

t₅₉

t₅₈

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

SSC_TmgSM

Figure 22

SSC Slave Mode Timing

Data Sheet

161

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Electrical ParametersAC Parameters

5.3.11

ERAY Interface Timing

The timings of this section are valid for the strong driver and either sharp edge or medium

edge settings of the output drivers with C_L= 25 pF.

The ERAY interface is only available for the SAK-TC1798F-512F300EP / SAK-

TC1798F-512F300EL / SAK-TC1798S-512F300EP.

Table 38

ERAY Parameters

Symbol

Parameter

Values

Typ.

Unit Note /

Test Condition

Min.

Max.

Time span from last BSS

to FES without the

₆₀CC

997.75 −

1002.2 ns

influence of quartz

tolerancies (d10Bit_TX)¹⁾

TxD data valid from

fsample flip flop txd_reg

TxDA, TxDB

t₆₁-t₆₂

−

1.5

Asymmetrical

delay of rising

and falling edge

(TxDA, TxDB)

(dTxAsym)²⁾³⁾

Time span between last

BSS and FES without

influence of quartz

tolerancies

₆₃SR

966

1046.1 ns

(d10Bit_RX)¹⁾⁴⁾⁵⁾

RxD capture by fsample

(RxDA/RxDB sampling

flip-flop) (dRxAsym)⁶⁾

t₆₄-t₆₅

−

3.0

Asymmetrical

delay of rising

and falling edge

(RxDA, RxDB)

TxD data delay from

sampling flip-flop

dTxdly

−

10.0

15.0

10.0

Px_PDR.PDy =

000_B

Px_PDR.PDy =

001_B

RxD capture delay by

sampling flip-flop

dRxdly

1) This includes the PLL_ERAY accumulated jitter.

2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.

Quarz tolerance and PLL_ERAY accumulated jitter are not included.

3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |t_FA2- t_RA2| ≤ 1 ns.

4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * V_DDPFlexRay standard input thresholds. For input

thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.

Data Sheet

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Electrical ParametersAC Parameters

5) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * V_DDPto 80% * V_DDP, according to the

FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming

signal have to satisfy the following inequality: -1.6ns ≤ t_FA2- t_RA2≤ 1.3ns.

6) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * V_DDPto 80% * V_DDP, according to the

FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming

signal have to satisfy the following inequality: -1.6ns ≤ t_FA2- t_RA2≤ 1.3ns.

Last CRC Byte

BSS

FES

(Byte Start Sequence)

(Frame End Sequence)

0.7 V_DD

0.3 V_DD

TXD

t₆₀

t_sample

0.9 V_DD

0.1 V_DD

TXD

t₆₁

t₆₂

Last CRC Byte

BSS

FES

(Byte Start Sequence)

(Frame End Sequence)

0.7 V_DD

0.3 V_DD

RXD

t₆₃

t_sample

0.7 V_DD

0.3 V_DD

RXD

t₆₄

t₆₅

ERAY_TIMING

Figure 23

ERAY Timing

Data Sheet

163

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TC1798

Electrical ParametersAC Parameters

5.3.12

EBU Timings

5.3.12.1 BFCLKO Output Clock Timing

_SS= 0 V;V_DD= 1.3 V ± 5%; V_DDEBU= 2.5 V ± 5% and 3.3 V ± 5%,;

C_L= 35 pF

Table 39

BFCLK0 Output Clock Timing Parameters¹⁾

Parameter

Symbol

Values

Unit Note /

Test Con

Min.

_BFCLKOCC 13.33²⁾

Typ. Max.

dition

BFCLKO clock period

BFCLKO high time

BFCLKO low time

BFCLKO rise time

BFCLKO fall time

–

t₅

t₆

t₇

t₈

–

BFCLKO duty cycle t₅/(t₅+ t₆)³⁾DC

1) Not subject to production test, verified by design/characterization.

2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter

parameters.

3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to f_CPU, the K divider has to

be regarded.

t_BFCLKO

0.9 V_DD

0.5 V_DDP05

BFCLKO

0.1 V_DD

t₈

t₇

t₅

t₆

MCT04883_mod

Figure 24

BFCLKO Output Clock Timing

5.3.12.2 EBU Asynchronous Timings

_SS= 0 V;V_DD= 1.3 V ± 5%; V_DDEBU= 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;

C_L= 35 pF for address/data; C_L= 40pF for the control lines.

For each timing, the accumulated PLL jitter of the programed duration in number of clock

periods must be added separately. Operating conditions apply and C_L= 35 pF.

Data Sheet

164

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Electrical ParametersAC Parameters

Table 40

EBU Common Asynchronous Timings

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

-0.8

Typ.

Max.

0.8

Pulse wdih deviation from t_aCC

the ideal programmed

width due to B pad

−

edge= medium

edge= sharp

0.8

asymmetry, rise delay - fall

delay¹⁾

AD(31:0) output delay to

ADV# rising edge,

₁₃CC

₁₄CC

-5.5

-2

−

multiplexed read / write¹⁾

AD(31:0) output delay to

ADV# rising edge,

multiplexed read / write¹⁾

Address valid to CS falling t₁₅CC

edge (deviation from

programmed value)¹⁾

Address valid to ADV

falling edge (deviation

from programmed value)¹⁾

₁₆CC

₁₇CC

-2

ADV falling edge

-> CSfalling edge

(deviation from

-2

programmed value)¹⁾

1) Not subject to production test, verified by design/characterization.

Data Sheet

165

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Electrical ParametersAC Parameters

Table 41

EBU Asynchronous Read Timings

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

A(23:0) output delay to RD t₀CC

rising edge, deviation from

the ideal programmed

value¹⁾

-2.5

2.5

A(23:0) output delay to RD t₁CC

rising edge, deviation from

the ideal programmed

value¹⁾

-2.5

-2

−

2.5

4.5

2.5

−

CS rising edge to RD

rising edge, deviation from

the ideal programmed

value¹⁾

t₂CC

t₃CC

t₄CC

t₅SR

t₆SR

t₇SR

ADV rising edge to RD

rising edge, deviation from

the ideal programmed

value¹⁾

-1.5

-2.5

BC rising edge to RD

rising edge, deviation from

the ideal programmed

value¹⁾

WAIT input setup to RD

rising edge, deviation from

the ideal programmed

value¹⁾

WAIT input hold to RD

rising edge, deviation from

the ideal programmed

value¹⁾

−

Data input setup to RD

rising edge, deviation from

the ideal programmed

value¹⁾

−

Data Sheet

166

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Electrical ParametersAC Parameters

Table 41

EBU Asynchronous Read Timings (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Data input hold to RD

rising edge, deviation from

the ideal programmed

value¹⁾

t₈SR

-2

−

MR / W output delay to

RD# rising edge, deviation

from the ideal

t₉CC

-2.5

−

1.5

programmed value¹⁾

Data input hold from CS

rising edge¹⁾

₁₈CC

₁₉CC

-2

−

Data input setup to CS

rising edge¹⁾

1) Not subject to production test, verified by design/characterization.

Data Sheet

167

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Electrical ParametersAC Parameters

Address

Phase

Address Hold

Phase (opt.) Delay Phase

Command

Phase

Recovery

Phase (opt.)

New Addr.

Phase

EBU

STATE

Control Bitfield:

ADDRC

1...15

AHOLDC

0...15

CMDDELAY

0...7

RDWAIT

1...31

RDRECOVC

0...15

ADDRC

1...15

Duration Limits in

EBU_CLK Cycles

A[23:0]

Valid Address

Addr.

pv +

t₁

t₂

t₀

t_a

CS[3:0]

CSCOMB

pv +

t₃

t_a

ADV

pv +

t_a

pv +

t_a

t₄

t_a

BC[3:0]

pv +

t₅

t₆

WAIT

pv +

t₁₄

pv +

t₁₃

t₇

t₈

Address Out

AD[31:0]

MR/W

Data In

pv +

t₉

pv = programmed value,

new_MuxRD_Async_10.vsd

T_{EBU_CLK}* sum (correponding bitfield values)

Figure 25

Multiplexed Read Access

Data Sheet

168

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Electrical ParametersAC Parameters

Address

Phase

Address Hold

Phase (opt.)

Command

Phase

Recovery

Phase (opt.)

New Addr.

Phase

EBU

STATE

Control Bitfield:

ADDRC

1...15

AHOLDC

0...15

RDWAIT

1...31

RDRECOVC

0...15

ADDRC

1...15

Duration Limits in

EBU_CLK Cycles

A[23:0]

Valid Address

pv +

Addr.

pv +

t₂

t₀

t₁

pv +

t_a

CS[3:0]

CSCOMB

pv +

t₃

t_a

ADV

pv +

t_a

pv +

t_a

t₄

pv +

t_a

BC[3:0]

pv +

t₅

t₆

WAIT

t₇

t₈

AD[31:0]

MR/W

Data In

pv +

t₉

pv = programmed value,

_{EBU_CLK}* sum (correponding bitfield values)

new_DemuxRD_Async_10.vsd

Figure 26

Demultiplexed Read Access

Data Sheet

169

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Electrical ParametersAC Parameters

Table 42

EBU Asynchnronous Write Timings

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

A(23:0) output delay to

WR rising edge, deviation

from the ideal

₃₀CC

₃₁CC

₃₂CC

₃₃CC

₃₄CC

₃₅SR

₃₆SR

₃₇CC

-2.5

2.5

programmed value¹⁾

A(23:0) output delay to

WR rising edge, deviation

from the ideal

-2.5

-2

−

2.5

programmed value¹⁾

CS rising edge to WR

rising edge, deviation from

the ideal programmed

value¹⁾

ADV rising edge to WR

rising edge, deviation from

the ideal programmed

value¹⁾

-2.5

BC rising edge to WR

rising edge, deviation from

the ideal programmed

value¹⁾

WAIT input setup to WR

rising edge, deviation from

the ideal programmed

value¹⁾

−

WAIT input hold to WR

rising edge, deviation from

the ideal programmed

value¹⁾

−

Data output delay to WR

falling edge, deviation

from the ideal

-5.5

programmed value¹⁾

Data Sheet

170

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Electrical ParametersAC Parameters

Table 42

EBU Asynchnronous Write Timings (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Data output delay to WR

rising edge, deviation from

the ideal programmed

value¹⁾

₃₈CC

₃₉CC

-5.5

MR / W output delay to

WR rising edge, deviation

from the ideal

-2.5

−

1.5

programmed value¹⁾

1) Not subject to production test, verified by design/characterization.

5.3.12.3 EBU Burst Mode Access Timing

_SS= 0 V;V_DD= 1.3 V ± 5%; V_DDEBU= 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;

C_L= 35 pF;

Table 43

EBU Burst Read Timings

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

-2

Max.

Output delay from

₁₀CC

₁₂CC

BFCLKO rising edge¹⁾

RD and RD/WR

-2

−

active/inactive after

BFCLKO active edge¹⁾²⁾

CSx output delay from

BFCLKO active edge¹⁾²⁾

₂₁CC

₂₂CC

-2.5

-2

−

1.5

ADV active/inactive after

BFCLKO active edge¹⁾³⁾

BAA active/inactive after

BFCLKO active edge¹⁾³⁾

_22aCC -2.5

1.5

−

Data setup to BFCLKI

rising edge¹⁾

₂₃SR

₂₄SR

Data hold from BFCLKI

rising edge¹⁾

−

Data Sheet

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Electrical ParametersAC Parameters

Table 43

EBU Burst Read Timings (cont’d)

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

WAIT setup (low or high)

to BFCLKI rising edge ¹⁾

₂₅SR

₂₆SR

−

WAIT hold (low or high)

−

from BFCLKI rising edge¹⁾

1) Not subject to production test, verified by design/characterization.

2) An active edge can be rising or falling edge, depending on the settings of bits BFCON.EBSE / ECSE and clock

divider ratio. Negative minimum values for these parameters mean that the last data read during a burst may

be corrupted. However, with clock feedback enabled, this value is oversampling not required for the LMB

transaction and will be discarded. If the clock feedback is not enabled, the input signals are latched using the

internal clock in the same way as at asynchronous access. So t14, t15, t16, t17, t18 and t19 from the

asynchronous timings apply.

3) For BUSCONx.EBSE=1B and BUSAPx.EXLCLK=00B, ADV will change normally on the clock edge so this

parameter is used directly.

For BUSCONx.EBSE=1B and other values of BUSAPx.EXTCLK, ADV and BAA add the high pulse width of

EBUCLK to this parameter.

For BUSCONx.EBSE=0B and BUSAPx.EXTCLK=00B add the high pulse width of EBUCLK to this parameter.

For BUSCONx.EBSE=0B and BUSAPx.EXTCLK=11B add two EBUCLK periodsto this parameter to get the

hold time from BFCLKO rising edge to the ADV.

For BUSCONx.EBSE=0B and BUSAPx.EXTCLK=01B or 10B add 1 EBUCLK period.

Please note that the high pulse width of EBUCLK is defined by the high pulse width of fVCO of the used PLL.

Data Sheet

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Electrical ParametersAC Parameters

Address

Phase(s)

Command

Phase(s)

Burst

Phase(s)

Burst

Phase(s)

Recovery

Phase(s)

Next Addr.

Phase(s)

BFCLKI

BFCLKO

t₁₀

A[23:0]

ADV

Burst Start Address

Addr.

t₂₂

t₂₁

CS[3:0]

CSCOMB

t₁₂

t_22a

t₂₄

RD/WR

t_22a

BAA

t₂₄

t₂₃

D[31:0]

(32-Bit)

Data (Addr+0)

Data (Addr+4)

D[15:0]

(16-Bit)

Data (Addr+0)

Data (Addr+2)

t₂₆

t₂₅

WAIT

Output delays are always referenced to BCLKO. The reference clock for input

characteristics depends on bit EBU_BFCON.FDBKEN.

EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.

EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock

feedback enabled).

BurstRDWR_4.vsd

Figure 27

EBU Burst Mode Read / Write Access Timing

Data Sheet

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Electrical ParametersAC Parameters

5.3.12.4 EBU Arbitration Signal Timing

_SS= 0 V;V_DD= 1.5 V ± 5%; V_DDEBU= 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;

T_A= -40°C to +125 °C; C_L= 35 pF;

Table 44

EBU EBU Arbitration Timings

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Output delay from

₂₇CC

₂₈SR

₂₉SR

−

BFCLKO rising edge¹⁾

Data setup to BFCLKO

falling edge¹⁾

−

Data hold from BFCLKO

falling edge¹⁾

1) Not subject to production test, verified by design/characterization.

BFCLKO

t₂₇

HLDA Output

t₂₇

BREQ Output

BFCLKO

t₂₈

t₂₉

t₂₈

t₂₉

HOLD Input

HLDA Input

EBUArb_1

Figure 28

EBU Arbitration Signal Timing

Data Sheet

174

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Electrical ParametersAC Parameters

5.3.12.5 EBU DDR Timing Parameters

Parameters applicable when using the EBU to access DDR memories

Table 45 is valid under the following conditions: C_L≤ 20 pF; V_DDEBU= 1.8 ±5% V

Table 45

EBU DDR Timings

Symbol

Parameter

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

3.3

DDR Clock Signal fall time t_CFCC

−

DDR Clock Signal high

time

_CHCC 29

DDR Clock Signal period¹⁾

_CKCC 24.0

−

Skew between clock rising t_CKDQS

transition and DQS rising CC

edge or clock falling

-1.2

1.2

transition and DQS falling

edge²⁾

DDR Clock Signal low

time

_CLCC

_CRCC

−

3.3

DDR Clock Signal rise

time

Maximum time from falling t_CVACC

clock edge until DDR

−

Control signal is valid³⁾

Maximum time before

falling clock edge that

DDR control signal can

become invalid³⁾

_CVBCC

−

DLL Delay time for duty

cycle correction when

locked

_DCCCC t_EBU/ 2

−

_EBU/ 2 ns

- 0.3

+ 0.3

byte lane x signals valid

value hold time (DQ & DM)

after DQSx edge⁴⁾

_DH1CC -1.6⁵⁾

−

DLL Delay time for for DQ

and DM when locked with

DLLCON.WR_ADJ=0d

_DLLCC

_EBU/ 4

_EBU/ 4 ns

- 0.2

+ 0.2

Data Sheet

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Electrical ParametersAC Parameters

Table 45

EBU DDR Timings (cont’d)

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

_EBU/ 4 ns

+ 0.15

DLL Delay time for DQS

when locked with

_DLLRCC t_EBU/ 4

- 0.15

DLLCON.RD_ADJ=0d

DQ and DQS all signals

hold time after DDRCLK0 CC

edge, DDRCLK0

controlled read

t_DQCKH

1.0

1.2

−

DQ and DQS all signal

t_DQCKS

−

valid to DDRCLK0 edge, CC

DDRCLK0 controlled read

DQSx edge to byte lane x

signals valid (DQ & DM)⁴⁾

_DS1CC

−

1.0

Maximum Peak to Peak

jitter of the DDR clock

output

t_PKPK

DQ byte lane hold time

after DQSx edge,

minimum hold time to

guarantee read data

capture, DLL Controlled

read

_QHSR 1.0

−

DQ byte lane valid to

DQSx edge minimum

setup time to guarantee

read data capture, DLL

Controlled read⁶⁾⁴⁾

_QSSR 1.0

−

1) This is a configuration constraint and not a design limit. Application code must not configure the EBU to

generate a DDR clock with a period of less than 12ns.

2) To allow for the differential clock trigger point being different from the trigger point on each of the individual

signals, this parameter will be characterised separately for each of the clock signals OCLKO, DDRCLKO and

DDRCLKO with a limit of ±1 ns

3) To allow for the differential clock trigger point being different from the trigger point on each of the individual

signals, this parameter will be characterised separately for each of the clock signals DDRCLKO (SDCLKO)

and DDRCLKO with a limit of ±2.4 ns

4) x = 0 to 3

5) i.e. signal can become invalid at most tDH1 before the clock edge

6) falling or rising edge

Data Sheet

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Electrical ParametersAC Parameters

Timing for EBU DDR Clock Outputs

The EBU provides three possible DDR clock outputs depending on the type of device

being accessed. These are

•

Differential clock for accessing devices using a DDRAM type protocol on the

DDRCLKO and DDRCLKO pins.

Differential clock for accessing devices using a burst flash type protocol on the

BFCLKO and DDRCLKO pins.

A single-ended clock on OCLKO (MR/W) for interfacing to ONFI 2 compliant devices.

All these clocks operate with identical timing parameters and have a restricted load limit

of 10pF for DDR operation.

The rising edge on the differential clocks is defined as when a rising edge on DDRCLKO

or BFCLKO transitions past a falling edge on DDRCLKO.

Timings apply at VDD_EBU= 1.8 volts

t_CK

0.9 VDD_EBU

0.5 VDD_EBU

0.1 VDD_EBU

t_CF

t_CR

t_CH

t_CL

Figure 29

Timing Waveform for DDR Clock Signals

Timing for EBU DDR Control Outputs

The EBU control state machine will ensure that commands and signal transitions are

generated in the correct clock cycle to meet device requirements. This section also

applies when accessing SDRAM devices.

The EBU will generate address (A[15:0]) and control (CKE, RAS, CAS, WR) outputs on

the falling edge of the DDR clock to allow nominally symmetric setup and hold margins

around the rising edge of the clock. For SDRAM devices, the same address and control

signals are required but, in addition, the write data (AD[31:0]) and DQM signals (BC[3:0])

are required to meet the same timing requirements.

As these parameters apply to SDRAM as well as DDR devices, the load limit should be

taken to be 40pF.

Data Sheet

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Electrical ParametersAC Parameters

DDRCLKO

t_CVA

t_CVB

CKE

t_CVA

t_CVB

Command

VALID

NOP

t_CVA

t_CVB

ADDR

Don't Care

Figure 30

DDR command and Address Timing

Using the DDRNCON.AMODE field, the timing of the address can be changed so that

the address changes on the rising clock edge and is held for two clock cycles. This allows

a nominal setup and hold margin of a full clock cycle. This mode is not compatible with

burst length of two as commands needing a valid address output can then be generated

in consecutive clock cycles.

Timing of DDR Write Data

The EBU will generate the DQ (write data) DM and DQS signals in two different modes

depending on the ratio of the internal to external clocks.

If the ratio is 1:1, then the clock used to generate the DQ and DM outputs must be shifted

by the DLL by 25% of the external clock period (nominal value).

If the ratio is 1:2 or 1:4, then the DQ and DM signals will be generated using edges of

the internal clock and the DLL must not be used to further adjust the edge timing.

A ratio of 1:3 is not supported.

In all cases, the edges of the DQS signals are nominally aligned to the clock output and

the DQS waveform is in phase with, and the same frequency as, the memory device

clock input.

Data Sheet

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Electrical ParametersAC Parameters

The EBU is characterised with the DLL inactive, so the timing parameters are specified

for this case. For the 1:1 operating mode, the DLL shift time and its error margin has to

be added where appropriate. For the 1:2 or 1:4 cases, the signals will be generated by

the appropriate clock edge so will be delayed by the correct number of EBU clock periods

(t_EBU). In this case the clock jitter will need to be subtracted from the available setup and

hold margins.

DDRCLKO

t_CKDQS

t_CK

(nom)

DQS[3:0]

DQ[31:0]

DM[3:0]

t_DH1

t_DS1

Don't Care

Data Valid

WRITE command issued at T0

DQ and DM signals shown with DLL disabled. With

DLL enabled, DQ and DQM will be delayed by

0.25*t_CK(nominal)

Transitioning Data

Figure 31

Signal Relationship for DDR writes

1:1 internal to external clock ratio

If the external bus clock is running at the same frequency as the internal clock, then the

DLL is used to generate intermediate clock edges at the intervals necessary to correctly

position the transitions on DQ and DM

Using the defined parameters. In the case where the DDR memory clock is the same

frequency as the internal EBU clock and the DLL is enabled but the DLL’s internal duty

cycle correction is not in use:

•

t_DHfor the memory will be t_CK/2+t_DH1-tDLL

t_DSfor the memory will be t_CK/2-t_DS1-tDLL-t_JIT

If the duty cycle correction is in use (DLLCON.DCC_EN=1_B), then the equation for setup

becomes:

1) t_JITis the pk-pk clock jitter of the EBU internal clock

Data Sheet

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Electrical ParametersAC Parameters

•

t_DSfor the memory will be t_CK/2-t_DS1-tDLL-(2*t_JIT

t_DHfor the memory will be t_CK/2+t_DH1-tDLL

)

1:2 internal to external clock ratio

If the external bus clock is running at half the internal clock frequency, then the negative

phase clock is used to generate intermediate clock edges at the intervals necessary to

correctly position the transitions on DQ and DM

The negative phase clock is generated either by:

•

If the EBU internal clock is a pulse swallowed version of the system clock then the

negative phase clock is generated by swallowing alternate pulses. So if the main

clock is divide by 4 and generated by passing pulses 0..4..8.. etc, then the neagtive

phase clock will be generated by passing pulses 2..6..10..

– t_DHfor the memory will be t_EBU/2+t_DH1-(n¹⁾/2*t_JIT

)

– t_DSfor the memory will be t_EBU/4-t_DS1-(n/2*t_JIT

)

•

If the EBU internal clock is a buffered version of the system clock input then the

negative phase clock will be an inverted version of the system clock

– t_DHfor the memory will be t_CK/4+t_DH1-t_JIT2

– t_DSfor the memory will be t_CK/4-t_DS1-t_JIT2

If the duty cycle correction function of the DLL is enabled, then the negative phase

clock will be the main clock delayed by 0.5*t_CK

– t_DHfor the memory will be t_DCC+t_DH1

– t_DSfor the memory will be t_DCC-t_DS1

1:4 internal to external clock ratio

If the external bus clock is running at one quarter the internal clock frequency, then EBU

internal clock clock is used to generate intermediate clock edges at the intervals

necessary to correctly position the transitions on DQ and DM

The negative phase clock is generated either by:

•

_DHfor the memory will be t_EBU+t_DH1-t_JIT

t_DSfor the memory will be t_EBU-t_DS1-t_JIT

Timing of DDR Read Data

DDR read data can be captured in two modes. The first mode uses the DLL to shift the

DQS signals internally to provide setup and hold margins between the DQS and DQ

lines. The DQS signals are then used as a clock to latch the data into internal registers.

The second mode is suitable only for lower frequencies and uses the DDRCLKO signal

internally as a clock to latch both the DQ and DQS signals. The state of the latched DQS

1) where n is the divide ratio between the system clock input and the EBU internal clock

t_JITis the pk-pk clock jitter of the system clock source

3) t_JIT2is the rising to falling edge jitter of the system clock source

Data Sheet

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TC1798

Electrical ParametersAC Parameters

signal is used to determine whether DQ is valid at any given clock edge. The restriction

is that the DDRCLKO signal must propagate through the TC1798 output pad in both

directions in time for the DQ and DQS signals to be latched before the next rising edge

of DDRCLKO at the clock generating flip-flop inside the EBU, i.e.

(Pad Output Delay)+(Pad Input Delay)+(Latch CK->Q valid) = t_TIME< t_ck

In addition the clock to output valid delay of the attached memory device must be less

than 0.5 * t_CK

DLL Controlled Read

The EBU interface is characterised with the DLL disabled. The relative positioning of the

DQ and DQS edges are then adjusted to determine the setup and hold times. The

parameters in the following table are therefore specified with the DLL inactive

A standard DDR device will output the DQ and DQS signals with edges that are

nominally aligned and the DLL will delay the DQS inputs internally to re-establish the

setup and hold margins.

DDRCLKO

DQS[3:0]

t_QS

t_QH

DQ[31:0]

Don't Care

Data Valid

Transitioning Data

Figure 32

DLL Controlled Read

Once the DLL is enabled, to satisfy the setup time, the DQ output from the memory

device must be valid less than t_DLLR-t_QSns after the DQS edge.

To satisfy the hold time, the DQ output from the memory device must remain valid until

the time (t_CK/2)-t_JITn-t_DLLR-t_DHbefore the next DQS edge.

DDRCLKO Controlled Read

A standard DDR device will output the DQ and DQS signals with edges that are

nominally aligned. In this mode, the data will be latched on both edges of the feedback

clock. This clock is generated from DDRCLKO.

Data Sheet

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TC1798

Electrical ParametersFlash Memory Parameters

t_DQCKS

t_DQCKH

DDRCLKO

DQS[3:0]

t_DQCKS

t_DQCKH

DQ[31:0]

Don't Care

Data Valid

Transitioning Data

Figure 33

DDRCLKO Controlled Read

In order for the read data to be captured successfully, the maximum clock to DQS & DQ

valid limit for the attached memory device must be less than half an external bus clock

period by the setup margin, t_DQCKSand the hold time for the DQS and data after the clock

edge must be greater than t_DQCKH

Timing of SDRAM Read Data

For SDRAM read accesses, DDRCLKO (SDCLKO) must be connected to DDRCLKO

(SDCLKI) to establish a path for the feedback clock. Then tDQCKS and tDQCKH can be

used to calculate timing margins in the same ways as for a DDR read except that only

the rising edge of SDCLKI is used for capturing data.

In order for the read data to be captured successfully, the maximum clock to DQ valid

limit for the attached memory device must be less than an external bus clock period by

the setup margin, t_DQCKSand the hold time for the data after the clock edge must be

greater than t_DQCKH

5.4 Flash Memory Parameters

The data retention time of the TC1798’s Flash memory depends on the number of times

the Flash memory has been erased and programmed.

Table 46

FLASH32 Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

4.2¹⁾

Data Flash Erase Time

per Sector

_ERDCC

_ERPCC

−

Program Flash Erase

Time per 256 KByte

Sector

−

Data Sheet

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TC1798

Electrical ParametersFlash Memory Parameters

Table 46

FLASH32 Parameters (cont’d)

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Program time data flash

per page²⁾

_PRDCC

−

5.3

without

reprogramming

−

15.9

with two

reprogramming

cycles

Program time program

flash per page³⁾

_PRPCC

−

5.3

without

reprogramming

10.6

with one

reprogramming

cycle

Data Flash Endurance

Erase suspend delay

N_ECC 60000

−

cycle Min. data

retention time 5

years

t_{FL_ErSusp}

−

μs

Wait time after margin

change

t_{FL_Margin}10

_DelCC

Aborted logical sector

erase soft-programming

recovery

t_{FL_SPRE}

−

400

_CCC

Program Flash Retention

Time, Physical Sector⁵⁾⁶⁾

_RETCC 20

−

year Max. 1000

erase/program

cycles

year Max. 100

erase/program

cycles

year Max. 4

Program Flash Retention

Time, Logical Sector⁵⁾⁶⁾

_RETLCC 20

_RTUCC 20

UCB Retention Time⁵⁾⁶⁾

erase/program

cycles per UCB

Wake-Up time

_WUCC

−

270

μs

DFlash wait state

configuration

WS_DF

50 ns x

f_FSI

−

PFlash wait state

configuration

WS_PF

26 ns x

f_FSI

−

Data Sheet

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TC1798

Electrical ParametersFlash Memory Parameters

1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can

increase by up to 100%.

2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each

reprogramming takes additional 5 ms.

3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The

reprogramming takes additional 5 ms.

4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.

5) Storage and inactive time included.

6) At average weighted junction temperature T_j= 100°C, or the retention time at average weighted temperature

of T_j= 110°C is minimum 10 years, or the retention time at average weighted temperature of T_j= 150°C is

minimum 0.7 years.

Data Sheet

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Electrical ParametersPackage and Reliability

5.5

Package and Reliability

5.5.1

Package Parameters

Table 47

Device

Thermal Characteristics of the Package

Package

RΘJCT RΘJCB RΘJA Unit

Note

TC1798

PG-LFBGA- 516

3,5

6,1

14,7

K/W

1) The top and bottom thermal resistances between the case and the ambient (R_TCAT, R_TCAB) are to be combined

with the thermal resistances between the junction and the case given above (R_TJCT, R_TJCB), in order to calculate

the total thermal resistance between the junction and the ambient (R_TJA). The thermal resistances between

the case and the ambient (R_TCAT, R_TCAB) depend on the external system (PCB, case) characteristics, and are

under user responsibility.

The junction temperature can be calculated using the following equation: T_J= T_A+ R_TJA× P_D, where the R_TJA

is the total thermal resistance between the junction and the ambient. This total junction ambient resistance

R_TJAcan be obtained from the upper four partial thermal resistances.

Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).

Data Sheet

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Electrical ParametersPackage and Reliability

5.5.2

Package Outline

Figure 34

Package Outlines PG-LFBGA- 516

You can find all of our packages, sorts of packing and others in our Infineon Internet

Page “Products”: http://www.infineon.com/products.

5.5.3

Quality Declarations

Table 48

Quality Parameters

Symbol

Parameter

Values

Unit Note / Test Condition

Min. Typ. Max.

Operation

Lifetime¹⁾

t_OP

–

24000 hours

–

ESD susceptibility V_HBM

according to

Human Body

–

2000

500

Conforming to

JESD22-A114-B

Model (HBM)

ESD susceptibility V_HBM1

–

of the LVDS pins

Data Sheet

186

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Electrical ParametersPackage and Reliability

Table 48

Quality Parameters

Symbol

Parameter

Values

Unit Note / Test Condition

Min. Typ. Max.

ESD susceptibility V_CDM

according to

–

500

Conforming to

JESD22-C101-C

Charged Device

Model (CDM)

Moisture

Sensitivity Level

MSL

–

Conforming to Jedec

J-STD-020C for 240°C

1) This lifetime refers only to the time when the device is powered on.

2) For worst-case temperature profile equivalent to:

1200 hours at T_j= 125...150^oC

3600 hours at T_j= 110...125^oC

7200 hours at T_j= 100...110^oC

11000 hours at T_j= 25...110^oC

1000 hours at T_j= -40...25^oC

Data Sheet

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TC1798

History

The following changes where done between Version 0.6 and 0.62 of this document:

•

change wdith for port 2 in figure 2

change numbers of V_DDFL3and V_SSin figure 2

update figure 3 according to pinning changes

remove typo in Ctrl. line from I/O0 to I/O

change for port 2.8 the symbol from CTRAPB (CCU60) to CCPOS0A (CCU62)

change for port 2.8 the symbol from T13HRE (CCU61) to T12HRB (CCU63)

add for port 2.8 the symbol from T3INB (GPT120)

add for port 2.8 the symbol from T3INA (GPT121)

change for port 2.10 the symbol from CC60INC (CCU61) to CTRAPB (CCU63)

change for port 2.12 the symbol from CTRAPB (CCU61) to CCPOS0A (CCU63)

change for port 2.12 the symbol from T13HRE (CCU60) to T12HRB (CCU62)

add for port 2.12 the symbol from T2INB (GPT120)

add for port 2.12 the symbol from T2INA (GPT121)

add for port 3.0 the symbol CTRAPB (CCU61)

change for port 3.0 for symbol CC60INC from CCU62 to CCU61

move pin P3.1 from B20 to B22

move pin P3.2 from J19 to A22

move pin P3.3 from A20 to B21

move pin P3.4 from G19 to K18

move pin P3.5 from B19 to A21

move pin P3.6 from K18 to B19

move pin P3.7 from A19 to A20

move pin P3.8 from J18 to B19

move pin P3.9 from B18 to A19

move pin P3.10 from G18 to J18

move pin P3.11 from A18 to B18

move pin P3.12 from F18 to K17

move pin P3.13 from B13 to A18

move pin P3.14 from K17 to B13

removed for port 3.2 the symbol CTRAPB (CCU62)

add for port 3.4 the symbol CTRAPA (CCU63)

change for port 3.4 the symbol from CC61INC (CCU62) to CTRAPB (CCU60)

removed for port 3.6 the symbol CTRAPB (CCU63)

change for port 3.8 the symbol from T12HRB (CCU63) to T13HRE (CCU61)

removed for port 3.8 the symbol CCPOS0A (CCU62)

removed for port 3.8 the symbol T3INB (GPT120)

removed for port 3.8 the symbol T3INA (GPT121)

change for port 3.14 the symbol from T12HRB (CCU62) to T13HRE (CCU60)

removed for port 3.14 the symbol CCPOS0A (CCU63)

Data Sheet

V 1.1, 2014-05

TC1798

History

•

removed for port 3.14 the symbol T2INB (GPT120)

removed for port 3.14 the symbol T2INA (GPT121)

change function description for port 4.1 alternate output 3 MTSR2 from Slave to

Master Mode

•

add footnote to port 4.1 alternate output 3 MTSR2

change function description for port 4.1 alternate output 3 MTSR2 from Slave to

Master Transmit

•

move pin P5.12 from B22 to J19

move pin P5.12 from B23 to G19

move pin P5.12 from A22 to G18

move pin P5.12 from A23 to F18

add footnote to port 6.4 alternate output 1 MTSR1

change for port 7.0 the symbol from ADEMUX0 to ADEMUX2

change function description for port 7.1 alternate output 2 MTSR3 from Slave to

Master Mode

•

add footnote to port 7.1 alternate output 2 MTSR3

change for port 8.3 the symbol from OUT43 (GPTA1) to CC62 (CCU60)

add for port 8.5 the symbol CTRAPB (CCU62)

change for port 9.13 the symbol from ECTT2 to ECTT1

change for port 9.14 the symbol from ECTT1 to ECTT2

add for port 9.14 the symbol REQ15

add footnote to port 10.1 alternate output 1 MTSR0

change for port 15 the type from S to D / S

change function description for port 18.1 alternate input MTSR2B from Master to

Slave Mode

•

change function description for port 18.1 alternate output 1 MTSR2 from Slave to

Master Mode

•

add footnote to port 18.1 alternate output 1 MTSR2

move pin V_DDPfrom AD15 to AD16

add clarification that table 9 defines the conditions for all other parameters

add conditions for MLI, MSC, SSC, parameters

add parameters dTxdly and dRxdly to ERAY parameters

correct footnotes for ERAY parameters

split flash parameters tPRD and tPRP in two conditions

add conditions to LVDS pad parameters

remove Pin Reliability in Overload section

add parameters IIN and Sum IIN to absolute ratings

add parameter HYSX to PSC_XTAL

added RDSON values for all driver settings (weak, medium, and strong)

removed footnote 2 of table 10

change load for timing of SSC, MSC, and MLI from C_L= 25 pF to C_L= 50 pF (typical)

add to parameters t_RFand t_FFcondition C_L= 50 pF

add new footnote 7) to ADC parameter table

Data Sheet

V 1.1, 2014-05

TC1798

History

•

add min and max value for Q_CONVand adapt typ value

add load conditions for t_FF1and t_RF1

add conditions to PLL parameter t_L

change DAP parameter t₁₉from SR to CC classification

remove footnote 2 for the FADC

adapt IDs for AB step

move pin AN49 from W2 to W1

move pin AN48 from W1 to W2

removed footnote 2 in table 9

change max value for ADC parameter t_Sfrom 255 to 257

change P1.7 input CC60INB to CC61INB

remove O2 OUT105 for GPTA1 of P14.9

add O2 T3OUt for GPT121 of P14.9

changed the name for O3 from EVTO2 to EVTO1 for P0.5

changed the name for O3 from EVTO3 to EVTO2 for P0.6

changed the name for O3 from EVTO4 to EVTO3 for P0.7

changed the name for O1 and O2 from OUT70 to OUT71 for P1.15

add input function SLSI2 for SSC2 to P4.9

The following changes where done between Version 0.62 and 0.63 of this document:

•

change P1.7 input CC60INB to CC61INB

remove O2 OUT105 for GPTA1 of P14.9

add O2 T3OUt for GPT121 of P14.9

changed the name for O3 from EVTO2 to EVTO1 for P0.5

changed the name for O3 from EVTO3 to EVTO2 for P0.6

changed the name for O3 from EVTO4 to EVTO3 for P0.7

changed the name for O1 and O2 from OUT70 to OUT71 for P1.15

add input function SLSI2 for SSC2 to P4.9

add input function CC60INC forCCU61 for P2.10

change back for port 3.0 for symbol CC60INC from CCU61 to CCU62

change input function T13HRE from CCU60 to CCU63

change for port 6.15 the symbol from CC61(CCU60) to CC60(CCU61)

change for port 8.2 the symbol from CC61(CCU60) to COUT63(CCU61)

change for port 14.10 the symbol from T3OUT(GPT120) to T6OUT(GPT121)

add to all SSC signal the assosiated SSC module where is was missing in the pinning

add section Pin Reliability in Overload

incease values for absolute maximium parameters I_INand SumI_IN

correct P14.8 O2 as this was incorrected label as O1

The following changes where done between Version 0.63 and 0.7 of this document:

•

change value R_ΘJCTfrom 2.6 to 3.5 K/W

change value R_ΘJCBfrom 4.3 to 6.1 K/W

change value R_ΘJAfrom 13.6 to 14.7 K/W

Data Sheet

V 1.1, 2014-05

TC1798

History

•

add parameter t_{POR_APP}

replace in Operating Conditions Parameter Note MA = modulation amplitude by

footnote 1)

•

remove the redundant test condition I_OHfor RDSON NMOS

remove the redundant test condition I_OLfor RDSON PMOS

add parameter V_ILSDto class S pads

remove footnote 2 from FADC

remove capacitance conditions for LVDS pad parameters as loads are defined by

interface (MSC) timings

The following changes where done between Version 0.7 and 1.0 of this document:

•

add product options SAK-TC1798S-512F300EP and SAK-TC1798N-512F300EP

remove product options SAK-TC1798F-512F240EP and SAK-TC1798F-

512F240EL

•

update block diagrams to cover new options

add note to TC1798 Logic Symbol figure and pin list for E-RAY pins availability

add identification registers for new options

adapt Absolute Maximum Rating

clarify pad supply levels in Pin Reliability in Overload section

correct errors for analog inputs in tables 10 and 11

add note at the end of Pin Reliability in Overload section

clarify wording for valid operating conditions

correct section Extended Range Operating Conditions for the 3.3 V area

increase limit in Extended Range Operating Conditions from 1 hour to 1000 hours

add negative limit for class S pad leakage

removed RDSON parameters for class F pads weak driver as only medium is

available and update values

•

change description of parameter t_CALfor the ADC

update footnote 10 for the ADC

update definition of INL and TUE for ADC3

split FADC DNL parameter into two conditions and change value for gain 4 and 8

update all current values of table 28 (Power Supply Parameters)

add footnote 5 to I_DDP

improve parameters I_DDFL3

add footnote for D-Flash currents in power section

add section 5.2.6.1.

rework first sentence for chapter 5.3

increase max values for parameter t_B

reduce min value for t_Lfor both PLLs

split f_VCOfor the system PLL into two conditions

change formula 10

add for MLI and SSC timing parameter: valid strong driver medium edge only

change MLI parameter t₁₇min value

Data Sheet

V 1.1, 2014-05

TC1798

History

•

update parameter description for SSC parameters t₅₂, t₅₃, t₅₆, t₅₇, t₅₈, and t₅₉

change SSC parameters from CC to SR Symbol for t₅₆, t₅₇, t₅₈and t₅₉

add note to ERAY parameters for availability

add parameters t₁₅, t₁₆, t₁₇, t₁₈, and t₁₉to the EBU

adapt EBU parameters for DDR Timming

add footnote to Flash parameter t_ERD

change for parameter N_Enote from Max. data retention to Min.

rework the 3.3 V current part of the Power Supply Parameters for better description

and usage

– Parameters I_{DDP_FP}, I_DDFL3Eand I_DDFL3Rare removed and replaced in the following

way

– I_{DDP_FP}is replaced by I_DDPwith the condition including flash programming current

– I_DDFL3Eis replaced by I_DDPwith the condition including flash erase verify current

– I_DDFL3Ris replaced by I_DDPwith the condition including flash read current

– parameter I_DDFL3Rwas renamed to I_DDFL3

The rework of the 3.3 V current part of the Power Supply Parameters was done for

simplification and clarification. Former given values could still be used if liked, the new

definition results in the same resulting values or slightly better values. The flash module

is supplied via I_DDFL3and I_DDP. For the different flash operating modes in worst case

different allocations for the two domains resulting.

The application typical case ‘flash read’ has max I_DDPof 25 mA and max I_DDFL3of 98 mA

resulting is a sum of 123 mA.

The case ‘flash programming’ has max I_DDPof 55 mA and max I_DDFL3of 29 mA resulting

is a sum of 84 mA.

The case ‘flash erase verify’ has max I_DDPof 40 mA and max I_DDFL3of 98 mA resulting

is a sum of 138 mA.

So for the old parameter I_DDPwith 35 mA, the new version reads as

_DDP= 25+I_{DDP_PORST}= 32 mA for the same application relevant case.

The following changes where done between Version 1.0 and 1.1 of this document:

•

change V_ILSfrom 2.1V to 1.9V in table 23

change t₄₈from 100ns to 200ns in table 42

change t₄₉from 100ns to 200ns in table 42

extend K_OVANconditon from I_OV≤ 0 mA; I_OV≥ -1 mA to I_OV≤ 0 mA; I_OV≥ -2 mA

change t₈from -4ns to -2ns in table 43

change t₁₈from -4ns to -2ns in table 43

change t₃₇parameter description from ‘Data output delay to WR rising edge,

deviation from the ideal programmed value’ to ‘Data output delay to WR falling edge,

deviation from the ideal programmed value’ in table 44

Add R_DSONxinformation for class B pads to table 18

Add exact definition ‘edge= sharp ; pin out driver= strong’ for the pad conviguration

of the rise and fall times in table 18

•

Data Sheet

V 1.1, 2014-05

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

SAK-TC1798F-512F300EP AB [INFINEON]

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