S79FL01GSDSBHBC13_技术文档

S79FL01GS

1 Gb (128 MB) Dual-Quad FL-S Flash SPI

Multi-I/O, 3.0 V

Features

• Density

- 1 Gbit (128 Mbytes)

• Serial peripheral interface (SPI)

- SPI clock polarity and phase modes 0 and 3

- Double data rate (DDR) option

- Extended addressing: 32-bit address

• READ commands

- Dual-Quad SPI Quad Read: 104 MHz clock rate (104 MB/s)

- Dual-Quad SPI Quad DDR Read: 80 MHz clock rate (160 MB/s)

- Normal, Fast, Quad, Quad DDR

- AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected

address

- Common flash interface (CFI) data for configuration information.

• Programming (3 Mbytes/s)

- 1024-byte page programming buffer

- Quad-input page programming (QPP) for slow clock systems

- Automatic error checking and correction (ECC) – internal hardware ECC with single bit error correction

• Erase (1 Mbyte/s)

- Uniform 512-kbyte sectors

- Extended addressing: 24- or 32-bit address options

• Cycling endurance

- 100,000 program-erase cycles, minimum

• Data retention

- 20 year data retention, minimum

• Security features

- Separate one time program (OTP) array of 2048 bytes

- Block protection:

• Status register bits to control protection against program or erase of a contiguous range of sectors

• Hardware and software control options

- Advanced sector protection (ASP)

• Individual sector protection controlled by boot code or password

• 65 nm MIRRORBIT™ technology with Eclipse architecture

• Core supply voltage: 2.7 V to 3.6 V

• Temperature range:

- Industrial (–40°C to +85°C)

- Industrial Plus (–40°C to +105°C)

- Automotive, AEC-Q100 grade 3 (–40°C to +85°C)

- Automotive, AEC-Q100 grade 2 (–40°C to +105°C)

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Performance summary

• Packages (all Pb-free)

- BGA-24 6 × 8 mm

• 5 × 5 ball (ZSA024) footprint

• Software features

- Program suspend and resume

- Erase suspend and resume

- Status register provides status of embedded erase or programming operation

- CFI-compliant — allows the host system to identify the flash device and determine its capabilities

- JEDEC JESD216 serial flash discoverable parameter (SFDP) support

- User-configurable Configuration Register

• Hardware features

- Hardware reset input (RESET#) — resets device to standby state

Performance summary

Maximum read rates SDR dual-quad SPI (V_CC= 2.7 V to 3.6 V)

Command

Clock rate (MHz)

MBps

12.5

33

Read

50

Fast read

Quad read

133

104

Maximum read rates DDR dual-quad SPI (V_CC= 3 V to 3.6 V)

Command

Clock rate (MHz)

MBps

DDR Quad read

80

160

Typical program and erase rates dual-quad SPI

Operation

KBps

3000

1000

Page programming (1024-byte page buffer)

512-kbyte logical sector erase

Typical current consumption, dual-quad SPI

Operation

Current (mA)

32 (max)

Serial read 50 MHz

Serial fast read 133 MHz

Quad read 104 MHz

Program

66 (max)

122 (max)

200 (max)

0.14 (typ)

Erase

Standby

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Table of contents

Features ...........................................................................................................................................1

Performance summary ......................................................................................................................2

Table of contents...............................................................................................................................3

1 Overview .......................................................................................................................................5

1.1 General description ................................................................................................................................................5

2 SPI with multiple input / output (SPI-MIO) dual-quad.........................................................................6

3 Signal descriptions .........................................................................................................................7

3.1 Input/output summary...........................................................................................................................................7

3.2 Multiple Input / Output (Dual-Quad SPI) ...............................................................................................................8

3.3 RESET#.....................................................................................................................................................................8

3.4 Serial Clock (SCK1, SCK2) .......................................................................................................................................8

3.5 Chip Select (CS1#, CS2#).........................................................................................................................................8

3.6 Input Output IO0–IO7 .............................................................................................................................................8

3.7 Core Voltage Supply (V_CC).......................................................................................................................................8

3.8 Versatile I/O Power Supply (V_IO).............................................................................................................................9

3.9 Supply and Signal Ground (V_SS) .............................................................................................................................9

3.10 Not Connected (NC) ..............................................................................................................................................9

3.11 Reserved for Future Use (RFU) .............................................................................................................................9

3.12 Do Not Use (DNU)..................................................................................................................................................9

3.13 Block diagram .....................................................................................................................................................10

4 Signal protocols............................................................................................................................11

4.1 SPI clock modes ....................................................................................................................................................11

4.2 Command protocol...............................................................................................................................................13

4.3 Interface states .....................................................................................................................................................17

4.4 Configuration Register effects on the interface ..................................................................................................21

4.5 Data protection.....................................................................................................................................................21

5 Electrical specifications.................................................................................................................22

5.1 Absolute maximum ratings ..................................................................................................................................22

5.2 Thermal resistance ...............................................................................................................................................22

5.3 Operating ranges ..................................................................................................................................................23

5.4 Power-up and power-down..................................................................................................................................24

5.5 DC characteristics .................................................................................................................................................26

6 Timing specifications ....................................................................................................................27

6.1 Key to switching waveforms.................................................................................................................................27

6.2 AC test conditions .................................................................................................................................................28

6.3 Reset ......................................................................................................................................................................29

6.4 SDR AC characteristics..........................................................................................................................................31

6.5 DDR AC characteristics .........................................................................................................................................33

7 Physical interface .........................................................................................................................36

7.1 Dual-Quad 24-ball BGA package (ZSA024) ..........................................................................................................36

8 Address space maps ......................................................................................................................38

8.1 Overview................................................................................................................................................................38

8.2 Flash memory array ..............................................................................................................................................38

8.3 ID-CFI address space.............................................................................................................................................38

8.4 JEDEC JESD216 serial flash discoverable parameters (SFDP) space .................................................................39

8.5 OTP address space................................................................................................................................................39

8.6 Registers................................................................................................................................................................41

9 Data protection ............................................................................................................................53

9.1 Secure silicon region (OTP) ..................................................................................................................................53

9.2 Write Enable command ........................................................................................................................................53

9.3 Block protection ...................................................................................................................................................54

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Table of contents

9.4 Advanced sector protection .................................................................................................................................55

10 Commands .................................................................................................................................59

10.1 Command set summary .....................................................................................................................................60

10.2 Identification commands ...................................................................................................................................66

10.3 Register Access commands ................................................................................................................................69

10.4 Read Memory Array commands .........................................................................................................................80

10.5 Program Flash Array commands........................................................................................................................89

10.6 Erase Flash Array commands .............................................................................................................................93

10.7 One Time Program Array commands.................................................................................................................97

10.8 Advanced Sector Protection commands...........................................................................................................99

10.9 Reset commands ..............................................................................................................................................106

10.10 Embedded algorithm performance tables ....................................................................................................107

11 Data integrity ........................................................................................................................... 108

11.1 Erase endurance ...............................................................................................................................................108

11.2 Data retention ...................................................................................................................................................108

12 Software interface reference ..................................................................................................... 109

12.1 Serial flash discoverable parameters (SFDP) address map............................................................................109

12.2 Device ID and common flash interface (ID-CFI) address map ........................................................................113

12.3 Device ID and Common Flash Interface (ID-CFI) ASO map — automotive only.............................................132

12.4 Initial delivery state ..........................................................................................................................................133

13 Ordering information ................................................................................................................ 134

13.1 Valid combinations — standard .......................................................................................................................135

13.2 Valid combinations — automotive grade / AEC-Q100.....................................................................................135

Revision history ............................................................................................................................ 136

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Overview

1

Overview

1.1

General description

The S79FL01GS device is a flash non-volatile memory product using:

• MIRRORBIT™ technology — that stores two data bits in each memory array transistor

• Eclipse architecture — that dramatically improves program and erase performance

• 65-nm process lithography

The S79FL01GS device connects two Quad I/O SPI devices with a single CS# resulting in an eight bit I/O data path.

This Byte I/O interface is called Dual-Quad I/O.

This device connects to a host system via a serial peripheral interface (SPI). Traditional SPI single bit serial input

and output (IO1 and IO5) is supported as well as four-bit (Quad I/O or QIO) serial commands. This multiple width

interface is called SPI multi-I/O or MIO. In addition, the S79FL01GS device adds support for double data rate (DDR)

read commands for QIO that transfers address and read data on both edges of the clock.

The Eclipse architecture features a page programming buffer that allows up to 512 words (1024 bytes) to be

programmed in one operation, resulting in significantly faster effective programming (up to 3 MB/s) and erase

(up to 1 MB/s) than prior generation SPI program or erase algorithms.

Executing code directly from flash memory is often called eXecute-in-Place (XIP). By using the S79FL01GS device

at the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match

or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count

dramatically.

The S79FL01GS product offers high density coupled with the fastest read and write performance required by a

variety of embedded applications. It is ideal for code shadowing, XIP, and data storage.

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SPI with multiple input / output (SPI-MIO)

dual-quad

2

SPI with multiple input / output (SPI-MIO) dual-quad

Many memory devices connect to their host system with separate parallel control, address, and data signals that

require a large number of signal connections and larger package size. The large number of connections increase

power consumption due to so many signals switching and the larger package increases cost.

The S79FL01GS device reduces the number of signals for connection to the host system by serially transferring

all control, address, and data information over 10 signals. This reduces the cost of the memory package, reduces

signal switching power, and either reduces the host connection count or frees host connectors for use in

providing other features.

The S79FL01GS Dual-Quad SPI device uses the industry standard single bit serial peripheral interface (SPI) using

two Quad SPI devices in each package (Quad SPI-1 and Quad SPI-2). This interface is called Dual-Quad and

enables support of Byte wide (8 bit) serial transfers. There is one package option available for S79FL01GS:

• 24-ball BGA package with separate balls for CS1#, SCK1 (Quad SPI-1) and CS2#, SCK1 (Quad SPI-2).

For documentation simplicity, all AC timings and waveforms and DC specification are defined using single CS#

(Chip Select) and SCK (Serial Clock) signals. For S79FL01GS, the CS# signal for Quad SPI-1 and Quad SPI-2 are

externally tied together, and the SCK signal for Quad SPI-1 and Quad SPI-2 are externally tied together.

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Signal descriptions

3

Signal descriptions

3.1

Input/output summary

Table 1

Signal name

Dual-quad input/output descriptions

Type

Description

Hardware Reset. LOW = device resets and returns to standby state, ready to receive a

command. The signal has an internal pull-up resistor and may be left unconnected in the host

system if not used.

RESET#

Input

SCK1

SCK2

CS1#

CS2#

IO0

Input

I/O

Serial Clock for Quad SPI-1

Serial Clock for Quad SPI-2

Chip Select for Quad SPI-1

Chip Select for Quad SPI-2

I/O 0 for Quad SPI-1

I/O 1 for Quad SPI-1

I/O 2 for Quad SPI-1

I/O 3 for Quad SPI-1

I/O 0 for Quad SPI-2

I/O 1 for Quad SPI-2

I/O 2 for Quad SPI-2

I/O 3 for Quad SPI-2

Core Power Supply

Ground

IO1

I/O

IO2

I/O

IO3

I/O

IO4

I/O

IO5

I/O

IO6

I/O

IO7

I/O

V

Supply

CC

SS

Not Connected. No device internal signal is connected to the package connector nor is there

any future plan to use the connector for a signal. The connection may safely be used for

NC

Unused routing space for a signal on a printed circuit board (PCB). However, any signal connected to

a NC pin must not have voltage levels higher than the V absolute maximum shown on

CC

Features page (core supply voltage).

Reserved for Future Use. No device internal signal is currently connected to the package

connector but there is potential future use for the connector for a signal. It is recommended

to not use RFU connectors for PCB routing channels so that the PCB may take advantage of

future enhanced features in compatible footprint devices.

RFU

Reserved

Do Not Use. A device internal signal may be connected to the package connector. The

connection may be used by Infineon for test or other purposes and is not intended for

connection to any host system signal. Any DNU signal related function will be inactive when

DNU

the signal is at V . The signal has an internal pull-down resistor and may be left unconnected

IL

in the host system or may be tied to VSS. Do not use these connections for PCB signal routing

channels. Do not connect any host system signal to this connection.

Note

1. For the BGA package, there are two CS# and two SCK balls.

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Signal descriptions

3.2

Multiple Input / Output (Dual-Quad SPI)

Quad input / output (I/O) commands send instructions to the memory only on the IO0 (Quad SPI-1) and IO4 (Quad

SPI-2) signals. Address is sent from the host to the memory as four bit (nibble) on IO0, IO1, IO2, IO3 (Quad

SPI-1)and repeated on IO4, IO5, IO6, IO7 (Quad SPI-2). Data is sent and returned to the host as bytes on IO0–IO7.

3.3

RESET#

The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a

command. When RESET# is driven to logic LOW (V_IL) for at least a period of t_RP, the device:

• terminates any operation in progress,

• tristates all outputs,

• resets the volatile bits in the Configuration Register,

• resets the volatile bits in the Status Registers,

• resets the Bank Address Register to zero,

• loads the Program Buffer with all ones,

• reloads all internal configuration information necessary to bring the device to standby mode,

• and resets the internal control unit to standby state.

RESET# causes the same initialization process as is performed when power comes up and requires t_PUtime.

RESET# may be asserted LOW at any time. To ensure data integrity any operation that was interrupted by a

hardware reset should be reinitiated once the device is ready to accept a command sequence.

When RESET# is first asserted LOW, the device draws I_CC1(50 MHz value) during t_PU. If RESET# continues to be

held at V_SSthe device draws CMOS standby current (I_SB).

RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used.

The RESET# input is not available on all packages options. When not available the RESET# input of the device is

tied to the inactive state, inside the package.

3.4

Serial Clock (SCK1, SCK2)

This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data

input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR

commands, and after every edge in DDR commands.

3.5

Chip Select (CS1#, CS2#)

The chip select signal indicates when a command for the device is in process and the other signals are relevant

for the memory device. When the CS# signal is at the logic HIGH state, the device is not selected and all input

signals are ignored and all output signals are high impedance. Unless an internal program, erase or write registers

(WRR) embedded operation is in progress, the device will be in the Standby Power mode. Driving the CS# input

to logic LOW state enables the device, placing it in the Active Power mode. After power-up, a falling edge on CS#

is required prior to the start of any command.

3.6

Input Output IO0–IO7

These signals are input and outputs for receiving instructions, addresses, and data to be programmed (values

latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in SDR

commands, and on every edge of SCK, in DDR commands).

3.7

Core Voltage Supply (V_CC)

V_CCis the voltage source for all device internal logic. It is the single voltage used for all device internal functions

including read, program, and erase. The voltage may vary from 2.7 V to 3.6 V.

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Signal descriptions

3.8

Versatile I/O Power Supply (V_IO)

V_IOfunctionality is not supported on the standard configuration of the S79FL01GS device. However, this V_IOsignal

(ball E4) is bonded out on the package and must be tied to V_CCon the PCB.

3.9

Supply and Signal Ground (V_SS)

V_SSis the common voltage drain and ground reference for the device core, input signal receivers, and output

drivers.

3.10

Not Connected (NC)

No device internal signal is connected to the package connector nor is there any future plan to use the connector

for a signal. The connection may safely be used for routing space for a signal on a printed circuit board (PCB).

However, any signal connected to an NC must not have voltage levels higher than V_IO.

3.11

Reserved for Future Use (RFU)

No device internal signal is currently connected to the package connector but is there potential future use of the

connector. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take

advantage of future enhanced features in compatible footprint devices.

3.12

Do Not Use (DNU)

A device internal signal may be connected to the package connector. The connection may be used by Infineon

for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related

function will be inactive when the signal is at V_IL. The signal has an internal pull-down resistor and may be left

unconnected in the host system or may be tied to V_SS. Do not use these connections for PCB signal routing

channels. Do not connect any host system signal to these connections.

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Signal descriptions

3.13

Block diagram

IO0 – IO3

Quad SPI-1

SCK1

SCK

CS#

CS1#

RESET#

CS2#

SCK2

Quad SPI-2

IO4 – IO7

SPI HOST

S79FL01GS Dual-Quad SPI Device

Figure 1

SPI host and S79FL01GS dual-quad SPI device with dual CS# and SCK balls in the 24-ball BGA

package (5x5 ball configuration)

Notes

2. The SPI host outputs one Chip Select (CS#) signal, that is routed to CS1# and CS2# balls on the S79FL01GS

device.

3. The SPI host outputs one Clock (SCK) signal, that is routed to SCK1 and SCK2 balls on the S79FL01GS device.

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Signal protocols

4

Signal protocols

SPI clock modes

4.1

4.1.1

Single data rate (SDR)

The S79FL01GS device can be driven by an embedded microcontroller (bus master) in either of the two following

clocking modes.

• Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0

• Mode 3 with CPOL = 1 and, CPHA = 1

For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the

output data is always available from the falling edge of the SCK clock signal.

The difference between the two modes is the clock polarity when the bus master is in standby mode and not

transferring any data.

• SCK will stay at logic LOW state with CPOL = 0, CPHA = 0

• SCK will stay at logic HIGH state with CPOL = 1, CPHA = 1

CPOL=0_CPHA=0_SCK

CPOL=1_CPHA=1_SCK

CS#

IO0

IO1

IO4

IO5

MSB

Figure 2

Dual-quad SPI SDR modes supported

Timing diagrams throughout the remainder of the document are generally shown as both Mode 0 and 3 by

showing SCK as both HIGH and LOW at the fall of CS#. In some cases a timing diagram may show only Mode 0 with

SCK LOW at the fall of CS#. In this case, Mode 3 timing simply means clock is HIGH at the fall of CS# so no SCK

rising edge set up or hold time to the falling edge of CS# is needed for Mode 3.

SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In Mode 0, the

beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of

SCK because SCK is already LOW at the beginning of a command.

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Signal protocols

4.1.2

Double data rate (DDR)

Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always

latched on the rising edge of clock, the same as in SDR commands. However, the address and input data that

follow the instruction are latched on both the rising and falling edges of SCK. The first address bit is latched on

the first rising edge of SCK following the falling edge at the end of the last instruction bit. The first bit of output

data is driven on the falling edge at the end of the last access latency (dummy) cycle.

SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the

next falling edge of SCK. In Mode 0, the beginning of the first SCK cycle in a command is measured from the falling

edge of CS# to the first falling edge of SCK because SCK is already LOW at the beginning of a command.

CPOL=0_CPHA=0_SCK

CPOL=1_CPHA=1_SCK

CS#

Transfer_Phase

Instruction

Inst. 7

Address

Inst. 0 A28 A24

A29 A25

Mode

A0 M4 M0

A1 M5 M1

A2 M6 M2

A3 M7 M3

A0 M4 M0

A1 M5 M1

A2 M6 M2

A3 M7 M3

Dummy / DLP

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

DL

.

DL

.

D0 D1

A30 A26

A31 A27

Inst. 7

Inst. 0 A28 A24

A29 A25

A30 A26

A31 A27

Figure 3

Dual-quad SPI DDR modes supported

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Signal protocols

4.2

Command protocol

All communication between the host system and S79FL01GS memory device is in the form of units called

commands.

All commands begin with an instruction that selects the type of information transfer or device operation to be

performed. Commands may also have an address, instruction modifier, latency period, data transfer to the

memory, or data transfer from the memory. All instruction, address, and data information is transferred serially

between the host system and memory device.

Quad input / output (I/O) commands provide an address sent from the host as four bit (nibble) groups on IO0,

IO1, IO2, IO3 and repeated on IO4, IO5, IO6, IO7, then followed by dummy cycles. Data is returned to the host as

byte on IO0–IO7. This is referenced as 2-8-8 for Quad I/O command protocols.

Commands are structured as follows:

• Each command begins with CS# going LOW and ends with CS# returning HIGH. The memory device is selected

by the host driving the Chip Select (CS#) signal LOW throughout a command.

• The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.

• Each command begins with an 8-bit (byte) instruction. The instruction is always presented only as a single bit

serial sequence on the Serial Input (SI) signal with one bit transferred to the memory device on each SCK rising

edge. The instruction selects the type of information transfer or device operation to be performed.

• The instruction may be stand alone or may be followed by address bits to select a location within one of several

address spaces in the device. The instruction determines the address space used. The address may be either a

24-bit or a 32-bit byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands,

or on every SCK edge, in DDR commands.

• Quad I/O read instructions send an instruction modifier called Continuous Read mode bits, following the

address, to indicate whether the next command will be of the same type with an implied, rather than an explicit,

instruction. These mode bits initiate or end the continuous read mode. In continuous read mode, the next

command thus does not provide an instruction byte, only a new address and mode bits. This reduces the time

needed to send each command when the same command type is repeated in a sequence of commands. The

mode bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.

The width of all transfers following the instruction are determined by the instruction sent. Following transfers

may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in 4-bit groups

per (quad) transfer on the IO0–IO3 signals. Within the quad groups the least significant bit is on IO0. More

significant bits are placed in significance order on each higher numbered IO signal. Single bits or parallel bit

groups are transferred in most to least significant bit order.

• Some instructions send an instruction modifier called mode bits, following the address, to indicate that the

next command will be of the same type with an implied, rather than an explicit, instruction. The next command

thus does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to

send each command when the same command type is repeated in a sequence of commands. The mode bit

transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.

• The address or mode bits may be followed by write data to be stored in the memory device or by a read latency

period before read data is returned to the host.

• Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.

• SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles

(also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from

the outputs on SCK falling edge at the end of the last read latency cycle. The first read data bits are considered

transferred to the host on the following SCK rising edge. Each following transfer occurs on the next SCK rising

edge, in SDR commands, or on every SCK edge, in DDR commands.

• If the command returns read data to the host, the device continues sending data transfers until the host takes

the CS# signal HIGH. The CS# signal can be driven HIGH after any transfer in the read data sequence. This will

terminate the command.

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Signal protocols

• At the end of a command that does not return data, the host drives the CS# input HIGH. The CS# signal must go

HIGH after the eighth bit, of a standalone instruction or, of the last write data byte that is transferred. That is,

the CS# signal must be driven HIGH when the number of clock cycles after CS# signal was driven LOW is an exact

multiple of eight cycles. If the CS# signal does not go HIGH exactly at the eight SCK cycle boundary of the

instruction or write data, the command is rejected and not executed.

• All instruction, address, and mode bits are shifted into the device with the Most Significant bits (MSB) first. The

data bits are shifted in and out of the device MSB first. All data is transferred in byte units with the lowest address

byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address

increments.

• All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)

are ignored. The embedded operation will continue to execute without any affect. A very limited set of

commands are accepted during an embedded operation. These are discussed in the individual command

descriptions.

• Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

4.2.1

Command sequence examples

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 4

Dual-Quad Standalone Instruction command

CS#

SCK

IO0

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Input Data

Figure 5

Dual-Quad Single bit Wide Input command

Note

4. Instruction needs to be the same for both IO0 (Quad SPI-1) and IO4 (Quad SPI-2).

Datasheet

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Signal protocols

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

31

1

0

3 2

1

0

3

2

1 0

IO2-IO3

IO4

IO5

7

6

5

4

7

6

5

4

IO6-IO7

Phase

Instruction

Address

Data 1

Data 2

Figure 6

Dual-Quad Single bit Wide I/O command without latency

CS#

SCK

IO0

7

6

5

4

3

2

1

0

31

1

0

IO1

3

2

1

5

0

4

3

2

6

1

5

0

4

IO2-IO3

IO4

IO5

7

6

7

IO6-IO7

Phase

Instruction

Address

Dummy Cycles

Data 1

Data 2

Figure 7

Dual-Quad Single bit Wide I/O command with latency

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

A

1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

IO2

IO3

IO4

IO5

IO6

IO7

Phase

Instruction

Address

Dummy

D1 D2 D3 D4 D5

Figure 8

Notes

Dual-Quad, Quad Output Read command

5. Instruction needs to be the same for both IO0 (Quad SPI-1) and IO4 (Quad SPI-2).

6. A = MSB of address = 23 for 3-byte address, or 31 for 4-byte address.

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CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0 28

29

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

IO2

30

IO3

31

SIG0

Phase

Address

Instruction

Mode

Dummy D1 D2 D3 D4

Figure 9

Dual-Quad, Quad I/O command

CS#

SCK

IO0

7

6

5

4

3

2

1

0

2824201612 8

2925211713 9

4

5

0

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

IO1

1

2

3

0

1

2

3

IO2

302622181410 6

312723191511 7

IO3

IO4

2824201612 8

2925211713 9

3026221814 2

3127231915 3

Address

4

5

6

7

IO5

IO6

IO7

Phase

Instruction

Mode

Dummy

DLP

D1D2 D3 D4

Figure 10

Dual-Quad DDR Quad I/O Read command

Additional sequence diagrams, specific to each command, are provided in “Commands” on page 59.

Notes

7. Instruction, Address and Mode bits needs to be the same for both IO0–IO3 (Quad SPI-1) and IO4–IO7 (Quad

SPI-2).

8. The gray bits are optional, the host does not have to drive bits during that cycle.

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Signal protocols

4.3

Interface states

This section describes the input and output signal levels as related to the SPI interface behavior.

Table 2

Dual-Quad interface states summary

Interface state

VDD

SCK

X

CS#

X

RESET#

IO0–IO7

Power-Off

Low Power

< V (low)

X

–

X

–

X

CC

–

Hardware Data Protection

< V (cut-off)

X

CC

Power-On (Cold) Reset

 V (min)

X

HH

X

CC

Hardware (Warm) Reset Non-Quad Mode

Hardware (Warm) Reset Quad Mode

Interface Standby

 V (min)

X

HL

HH

CC

 V (min)

X

HH

HL

CC

 V (min)

X

CC

Instruction Cycle (Legacy SPI)

 V (min)

HT

CC

Single Input Cycle

 V (min)

HT

HL

HH

X

CC

Host to Memory Transfer

Single Latency (Dummy) Cycle

 V (min)

CC

Single Output Cycle

 V (min)

CC

Memory to Host Transfer

Quad Input Cycle

 V (min)

HT

HL

HH

X

CC

Host to Memory Transfer

Quad Latency (Dummy) Cycle

 V (min)

CC

Quad Output Cycle

 V (min)

CC

Memory to Host Transfer

DDR Quad Input Cycle

 V (min)

HT

HL

HH

X

CC

Host to Memory Transfer

DDR Latency (Dummy) Cycle

 V (min)

CC

DDR Quad Output Cycle

Memory to Host Transfer

 V (min)

CC

Legend:

Z

= No driver - floating signal

HL = Host driving V

HH = Host driving V

IL

IH

HV = Either HL or HH

X

= HL or HH or Z

HT = Toggling between HL and HH

ML = Memory driving V

MH = Memory driving V

MV = Either ML or MH

IL

IH

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4.3.1

Power-off

When the core supply voltage is at or below the V_CC(low) voltage, the device is considered to be powered off. The

device does not react to external signals, and is prevented from performing any program or erase operation.

4.3.2

Low power hardware data protection

When V_CCis less than V_CC(cut-off), the memory device will ignore commands to ensure that program and erase

operations can not start when the core supply voltage is out of the operating range.

4.3.3

Power-on (cold) reset

When the core voltage supply remains at or below the V_CC(low) voltage for t_PDtime, then rises to  V_{CC (Minimum)}

the device will begin its power-on reset (POR) process. POR continues until the end of t_PU. During t_PU, the device

does not react to external input signals nor drive any outputs. Following the end of t_PU, the device transitions to

the Interface Standby state and can accept commands. For additional information on POR see “Power-on (cold)

reset” on page 29.

4.3.4

Hardware (warm) reset

Some of the device package options provide a RESET# input. When RESET# is driven LOW for t_RPtime the device

starts the hardware reset process. The process continues for t_RPHtime. Following the end of both t_RPHand the

reset hold time following the rise of RESET# (t_RH) the device transitions to the Interface Standby state and can

accept commands. For additional information on hardware reset see “POR followed by hardware reset” on

page 29.

4.3.5

Interface Standby

When CS# is HIGH, the SPI interface is in Standby state. Inputs other than RESET# are ignored. The interface waits

for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes LOW to begin a

new command.

While in Interface Standby state the memory device draws standby current (I_SB) if no embedded algorithm is in

progress. If an embedded algorithm is in progress, the related current is drawn until the end of the algorithm

when the entire device returns to standby current draw.

4.3.6

Instruction cycle

When the host drives the MSB of an instruction and CS# goes LOW, on the next rising edge of SCK the device

captures the MSB of the instruction that begins the new command. On each following rising edge of SCK, the

device captures the next lower significance bit of the 8-bit instruction. The host keeps RESET# HIGH, CS# LOW.

Each instruction selects the address space that is operated on and the transfer format used during the remainder

of the command. The transfer format may be Single, Quad output, Quad I/O, DDR Single I/O, or DDR Quad I/O.

The expected next interface state depends on the instruction received.

Some commands are standalone, needing no address or data transfer to or from the memory. The host returns

CS# HIGH after the rising edge of SCK for the eighth bit of the instruction in such commands. The next interface

state in this case is Interface Standby.

4.3.7

Single input cycle — Host to Memory transfer

Several commands transfer information after the instruction on the single serial input (SI) signal from host to the

memory device. The Quad Output commands send address to the memory using only SI but return read data

using the I/O signals. The host keeps RESET# HIGH, CS# LOW, HOLD# HIGH, and drives SI as needed for the

command. The memory does not drive the Serial Output (IO1 and IO5) signals.

The expected next interface state depends on the instruction. Some instructions continue sending address or

data to the memory using additional single input cycles. Others may transition to single latency, or directly to

Single, or Quad Output.

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Signal protocols

4.3.8

Single latency (dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the latency code in

the Configuration Register (CR[7:6]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW, and SCK

toggles. The host may drive the IO0 and IO4 signals during these cycles or the host may leave IO0 and IO4 floating.

The memory does not use any data driven on IO0 and IO4 or other I/O signals during the latency cycles. In Quad

Read commands, the host must stop driving the I/O signals on the falling edge at the end of the last latency cycle.

It is recommended that the host stop driving I/O signals during latency cycles so that there is sufficient time for

the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents driver

conflict between host and memory when the signal direction changes. The memory does not drive the Serial

Output (IO0 and IO4) or I/O signals during the latency cycles.

The next interface state depends on the command structure i.e. the number of latency cycles, and whether the

read is single, or quad width.

4.3.9

Dual-Quad single output cycle — Memory to Host transfer

Several commands transfer information back to the host on the Serial Outputs (IO1 and IO5) signals. The host

keeps RESET# HIGH, CS# LOW. The memory ignores the Serial Input (IO0 and IO4) signals. The memory drives IO1

and IO5 with data.

The next interface state continues to be dual output cycle until the host returns CS# to HIGH ending the

command.

4.3.10

QPP or QOR address input cycle

The Quad Page Program and Quad Output Read commands send address to the memory only on IO0 and IO4.

The other IO signals are ignored because the device must be in Quad mode for these commands thus the Hold

and Write Protect features are not active. The host keeps RESET# HIGH, CS# LOW, and drives IO0.

For QPP the next interface state following the delivery of address is the quad input cycle.

For QOR the next interface state following address is a quad latency cycle if there are latency cycles needed or

quad output cycle if no latency is required.

4.3.11

Quad input cycle — Host to Memory transfer

The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. The Quad Page

Program command transfers four data bits to the memory in each cycle. The host keeps RESET# HIGH, CS# LOW,

and drives the IO signals.

For Quad I/O Read, the next interface state following the delivery of address and mode bits is a quad latency cycle

if there are latency cycles needed or quad output cycle if no latency is required. For Quad Page Program the host

returns CS# HIGH following the delivery of data to be programmed and the interface returns to Standby state.

4.3.12

Quad latency (dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the latency code in

the Configuration Register (CR[7:6]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW. The host

may drive the IO signals during these cycles or the host may leave the IO floating. The memory does not use any

data driven on IO during the latency cycles. The host must stop driving the IO signals on the falling edge at the

end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that

there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency

cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory

does not drive the IO signals during the latency cycles.

The next interface state following the last latency cycle is a quad output cycle.

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Signal protocols

4.3.13

Quad output cycle — Memory to Host transfer

The Quad Output Read and Quad I/O Read return data to the host eight bits in each cycle. The host keeps RESET#

HIGH, and CS# LOW. The memory drives data on IO0–IO3 signals during the quad output cycles.

The next interface state continues to be quad output cycle until the host returns CS# to HIGH ending the

command.

4.3.14

DDR quad input cycle — Host to Memory transfer

The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Eight bits

are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET#

HIGH, and CS# LOW.

The next interface state following the delivery of address and mode bits is a DDR latency cycle.

4.3.15

DDR latency cycle

DDR Read commands may have one to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the latency code in

the Configuration Register (CR1[7:6]). During the latency cycles, the host keeps RESET# HIGH and CS# LOW. The

host may not drive the IO signals during these cycles. So that there is sufficient time for the host drivers to turn

off before the memory begins to drive. This prevents driver conflict between host and memory when the signal

direction changes. The memory has an option to drive all the IO signals with a data learning pattern (DLP) during

the last 4 latency cycles. The DLP option should not be enabled when there are fewer than five latency cycles so

that there is at least one cycle of high impedance for turn around of the IO signals before the memory begins

driving the DLP. When there are more than 4 cycles of latency the memory does not drive the IO signals until the

last four cycles of latency.

The next interface state following the last latency cycle is a DDR quad output cycle, depending on the instruction.

4.3.16

DDR quad output cycle — Memory to Host transfer

The DDR Quad I/O Read command returns bits to the host on all the IO signals. Eight bits are transferred on the

rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# HIGH, and CS# LOW.

The next interface state continues to be DDR quad output cycle until the host returns CS# to HIGH ending the

command.

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Signal protocols

4.4

Configuration Register effects on the interface

The Configuration Register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code

selects the number of mode bit and latency cycles for each type of instruction.

The Configuration Register Bit-1 (CR1[1]) selects whether Quad mode is enabled and allow Quad Page Program,

Quad Output Read, and Quad I/O Read commands. Quad mode must also be selected to allow Read DDR Quad

I/O commands. This Quad bit is set to ‘1’ by default for Dual-Quad SPI.

4.5

Data protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the

hardware design. These are described in the “Data protection” on page 53. Other software managed protection

methods are discussed in the “Software interface” on page 38 of this document.

4.5.1

Power-up

When the core supply voltage is at or below the V_CC(low) voltage, the device is considered to be powered off. The

device does not react to external signals, and is prevented from performing any program or erase operation.

Program and erase operations continue to be prevented during the power-on reset because no command is

accepted until the exit from POR to the Interface Standby state.

4.5.2

Low power

When V_CCis less than V_CC(cut-off), the memory device will ignore commands to ensure that program and erase

operations can not start when the core supply voltage is out of the operating range.

4.5.3

Clock pulse count

The device verifies that all program, erase, and Write Registers (WRR) commands consist of a clock pulse count

that is a multiple of eight before executing them. A command not having a multiple of 8 clock pulse count is

ignored and no error status is set for the command.

Datasheet

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Electrical specifications

5

Electrical specifications

5.1

Absolute maximum ratings

Table 3

Absolute maximum ratings

Storage temperature plastic packages

–65°C to +150°C

–65°C to +125°C

–0.5 V to +4.0 V

Ambient temperature with power applied

V

CC

[9]

Input Voltage with respect to ground (V )

–0.5 V to +(V + 0.5 V)

SS

IO

[10]

Output short circuit current

100 mA

5.2

Thermal resistance

Table 4

Parameter

Thermal resistance

Description

Test condition

ZSA024

Unit

Thermal resistance (Junction

to ambient)

Theta JA

Theta JB

Theta JC

38

°C/W

Test conditions follow standard test methods

Thermal resistance (Junction and procedures for measuring thermal

18

°C/W

to board)

impedance in accordance with EIA/JESD51.

with Still Air (0 m/s).

Thermal resistance (Junction

to case)

13.78

Notes

9. See “Input signal overshoot” on page 23 for allowed maximums during signal transition.

10.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be

greater than one second.

11.Stresses above those listed under Absolute maximum ratings may cause permanent damage to the device.

This is a stress rating only; functional operation of the device at these or any other conditions above those

indicated in the operational sections of this datasheet is not implied. Exposure of the device to absolute

maximum rating conditions for extended periods may affect device reliability.

Datasheet

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Electrical specifications

5.3

Operating ranges

Operating ranges define those limits between which the functionality of the device is guaranteed.

5.3.1

Temperature ranges

Table 5

Recommended operating ranges

Spec

Parameter

Symbol

Devices

Unit

°C

Min

–40

Max

+85

Industrial (I)

[12]

Industrial Plus (V)

+105

+85

Ambient temperature

T

A

Automotive, AEC-Q100 grade 3 (A)

Automotive, AEC-Q100 grade 2 (B)

°C

+105

5.3.2

Input signal overshoot

During DC conditions, input or I/O signals should remain equal to or between V_SSand V_IO. During voltage

transitions, inputs or I/Os may overshoot V_SSto –2.0 V or overshoot to V_CC+ 2.0 V, for periods up to 20 ns.

20 ns

V_IL

- 2.0V

20 ns

Figure 11

Maximum negative overshoot waveform

20 ns

V_CC+ 2.0V

V_IH

20 ns

Figure 12

Maximum positive overshoot waveform

Note

12.Operating and performance parameters will be determined by device characterization and may vary from

standard industrial temperature range devices as currently shown in this specification.

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Electrical specifications

5.4

Power-up and power-down

The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on V_CC

until V_CCreaches the correct value as follows:

)

V_CC(min) at power-up, and then for a further delay of t_PU

V_SSat power-down

A simple pull-up resistor (generally of the order of 100 k) on Chip Select (CS#) can usually be used to insure safe

and proper power-up and power-down.

The device ignores all instructions until a time delay of t_PUhas elapsed after the moment that V_CCrises above the

minimum V_CCthreshold (see Figure 13). However, correct operation of the device is not guaranteed if V_CCreturns

below V_CC(min) during t_PU. No command should be sent to the device until the end of t_PU

.

After power-up (t_PU), the device is in Standby mode (not Deep Power Down mode), draws CMOS standby current

(I_SB), and the WEL bit is reset.

During power-down or voltage drops below V_CC(cut-off), the voltage must drop below V_CC(low) for a period of

t_PDfor the part to initialize correctly on power-up (see Figure 14). If during a voltage drop the V_CCstays above V_CC

(cut-off) the part will stay initialized and will work correctly when V_CCis again above V_CC(min). In the event

power-on reset did not complete correctly after power up, the assertion of the RESET# signal or receiving a

software reset command (RESET) will restart the POR process.

Normal precautions must be taken for supply rail decoupling to stabilize the V_CCsupply at the device. Each device

in a system should have the V_CCrail decoupled by a suitable capacitor close to the package supply connection

(this capacitor is generally of the order of 0.1 µF).

Table 6

Power-up / power-down voltage and timing

Parameter

Symbol

Min

2.7

Max

Unit

V

(min)

V

(minimum operation voltage)

–

V

CC

(cut-off)

(cut 0ff where re-initialization is needed)

2.4

V

(low voltage for initialization to occur)

1.0

2.3

CC

V

(low)

–

V

CC

(low voltage for initialization to occur at embedded)

t

V

(min) to Read operation

(low) time

–

300

–

µs

PU

CC

1.0

PD

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Electrical specifications

V_CC

(max)

V_CC

(min)

V_CC

t_PU

Full Device Access

Time

Figure 13

Power-up

V_CC

(max)

V_CC

No Device Access Allowed

(min)

V_CC

t_PU

Device Access

Allowed

(cut-off)

V_CC

(low)

V_CC

t_PD

Time

Figure 14

Power-down and voltage drop

Datasheet

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Electrical specifications

5.5

DC characteristics

Table 7

DC characteristics

Parameter

[13]

Symbol

Test conditions

Min

–0.5

0.7 × V

–

Typ

Max

Unit

V

Input low voltage

Input high voltage

Output low voltage

Output high voltage

–

0.2 × V

V

IL

CC

V + 0.4

CC

IH

CC

I

= 1.6 mA, V = V min

0.15 × V

–

OL

OH

OL

CC

= –0.1 mA

0.85 × V

OH

CC

V

= V max,

CC

IN

I

Input leakage current

Output leakage current

–

±4

µA

LI

V = V or V

IH

IL

V

= V max,

CC

IN

–

±4

32

LO

= V or V

IH

IL

Serial SDR @ 50 MHz

Serial SDR @ 133 MHz

Quad SDR @ 80 MHz

Quad SDR @ 104 MHz

Quad DDR @ 80 MHz

Outputs unconnected during

[15]

66/70

100

122

200

Active power supply current

(READ)

I

–

mA

CC1

[14]

read data return

Active power supply current

(Page Program)

I

CS# = V

–

200

mA

CC2

CC3

CC4

CC5

SB

CC

Active power supply current

(WRR)

Active power supply current

(SE)

Active power supply current

(BE)

RESET#, CS# = V ;

CC

SS

Standby current

SI, SCK = V or V ,

–

140

200

600

µA

CC

(Industrial)

Industrial Temperature

RESET#, CS# = V ;

CC

SS

I

(Industrial

SB

SI, SCK = V or V ,

CC

Plus)

Industrial Plus Temperature

5.5.1

Active power and standby power modes

The device is enabled and in the Active Power mode when Chip Select (CS#) is LOW. When CS# is HIGH, the device

is disabled, but may still be in an Active Power mode until all program, erase, and write operations have

completed. The device then goes into the Standby Power mode, and power consumption drops to I_SB

.

Notes

13.Typical values are at T_AI= 25°C and V_CC= 3 V.

14.Outputs switching current is not included.

15.Industrial temperature range / Industrial Plus temperature range.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Timing specifications

6

Timing specifications

6.1

Key to switching waveforms

High Impedance

Any change permitted

Valid at logic high or low

Input

Symbol

Output

Logic High Logic Low

High Impedance

Valid at logic high or low

Changing, state unknown

Figure 15

Waveform element meanings

Input Levels

+ 0.4V

Output Levels

0.85 x V

V

CC

0.7 x V

0.5 x V

0.2 x V

CC

Timing Reference Level

0.15 x V

CC

- 0.5V

Figure 16

Input, output, and timing reference levels

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Timing specifications

6.2

AC test conditions

Device

Under

Test

C

L

Figure 17

Test setup

Table 8

Symbol

AC measurement conditions

Parameter

Min

Max

Unit

30

C

Load capacitance

pF

[19]

L

15

Input rise and fall times

Input pulse voltage

–

2.4

ns

V

0.2 × V to 0.8 × V

CC

Input timing ref voltage

Output timing ref voltage

0.5 × V

V

CC

V

6.2.1

Capacitance characteristics

Table 9

Symbol

Capacitance

Parameter

Test conditions

1 MHz

Min

Max

Unit

pF

C

Input capacitance (applies to SCK, CS#, RESET#)

Output capacitance (applies to All I/O)

–

10

IN

1 MHz

pF

OUT

Notes

16.Output High-Z is defined as the point where data is no longer driven.

17.Input slew rate: 1.5 V/ns.

18.AC characteristics tables assume clock and data signals have the same slew rate (slope).

19.DDR Operation.

20.For more information on capacitance, please consult the IBIS models.

Datasheet

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002-00466 Rev. *H

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Timing specifications

6.3

Reset

6.3.1

Power-on (cold) reset

The device executes a POR process until a time delay of t_PUhas elapsed after the moment that V_CCrises above

the minimum V_CCthreshold. See Figure 13, Table 6, and Table 10. The device must not be selected (CS# to go

HIGH with V_IO) during power-up (t_PU), i.e. no commands may be sent to the device until the end of t_PU. RESET# is

ignored during POR. If RESET# is LOW during POR and remains LOW through and beyond the end of t_PU, CS# must

remain HIGH until t_RHafter RESET# returns HIGH. RESET# must return HIGH for greater than t_RSbefore returning

LOW to initiate a hardware reset.

VCC

VIO

tPU

If RESET# is low at tPU end

CS# must be high at tPU end

RESET#

tRH

CS#

Figure 18

Reset LOW at the end of POR

VCC

tPU

RESET#

CS#

If RESET# is high at tPU end

CS# may stay high or go low at tPU end

Figure 19

Reset HIGH at the end of POR

VCC

tPU

tRS

RESET#

CS#

Figure 20

POR followed by hardware reset

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Timing specifications

6.3.2

Hardware (warm) reset

When the RESET# input transitions from V_IHto V_ILthe device will reset register states in the same manner as POR

but, does not go through the full reset process that is performed during POR. The hardware reset process requires

a period of t_RPHto complete. If the POR process did not complete correctly for any reason during power-up (t_PU),

RESET# going LOW will initiate the full POR process instead of the hardware reset process and will require t_PUto

complete the POR process.

The RESET# input provides a hardware method of resetting the flash memory device to Standby state.

• RESET# must be HIGH for t_RSfollowing t_PUor t_RPH, before going LOW again to initiate a hardware reset.

• When RESET# is driven LOW for at least a minimum period of time (t_RP), the device terminates any operation in

progress, tri-states all outputs, and ignores all read/write commands for the duration of t_RPH. The device resets

the interface to standby state.

• If CS# is LOW at the time RESET# is asserted, CS# must return HIGH during t_RPHbefore it can be asserted LOW

again after t_RH

.

tRP

Any prior reset

tRPH

RESET#

CS#

tRH

tRS

tRPH

Figure 21

Hardware reset

Table 10

Hardware reset parameters

Parameter

Description

Limit

Min

Time

50

Unit

ns

t

Reset setup — prior reset end and RESET# HIGH before RESET# LOW

Reset pulse hold — RESET# LOW to CS# LOW

RESET# pulse width

RS

Min

35

µs

RPH

RP

Min

200

50

ns

Reset hold — RESET# HIGH before CS# LOW

Min

ns

RH

Notes

21.RESET# LOW is optional and ignored during power-up (t_PU). If RESET# is asserted during the end of t_PU, the

device will remain in the Reset state and t_RHwill determine when CS# may go LOW.

22.Sum of t_RPand t_RHmust be equal to or greater than t_RPH

.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Timing specifications

6.4

SDR AC characteristics

Table 11

AC characteristics (V_CC2.7 V to 3.6 V)

Parameter

Symbol

Min

Typ

Max

Unit

F

SCK clock frequency for READ and 4READ instructions

DC

–

50

MHz

SCK, R

SCK clock frequency for single commands

DC

–

133

104

MHz

as shown in Table 38 ^[27]

SCK, C

SCK clock frequency for the following Dual and Quad

commands: QOR, 4QOR, QIOR, 4QIOR

F

DC

MHz

SCK, C

SCK clock frequency for the QPP, 4QPP commands

SCK clock period

–

80



–

SCK, QPP

P

1/ F

SCK

[23]

t

, t

Clock HIGH time

45% P

0.1

ns

WH CH

SCK

[23]

, t

Clock LOW time

–

WL CL

, t

Clock rise time (slew rate)

Clock fall time (slew rate)

–

V/ns

CRT CLCH

, t

0.1

–

CFT CHCL

CS# HIGH time (read instructions)

CS# HIGH time (program/erase)

10

50

t

–

ns

CS

t

CS# active setup time (relative to SCK)

CS# active hold time (relative to SCK)

Data in setup time

3

–

ns

CSS

CSH

SU

[24]

1.5

2

3000

Data in hold time

–

HD

[25]

[26]

[27]

8.0

7.65

6.5

t

Clock LOW to output valid

0

–

ns

V

t

Output hold time

2

0

–

8

–

8

ns

HO

Output disable time

DIS

[28]

t

WP# setup time

20

WPS

WPH

HLCH

CHHH

HHCH

CHHL

HZ

[28]

t

WP# hold time

100

t

HOLD# active setup time (relative to SCK)

HOLD# active hold time (relative to SCK)

HOLD# non active setup time (relative to SCK)

HOLD# non active hold time (relative to SCK)

HOLD# enable to output invalid

HOLD# disable to output valid

3

–

LZ

Notes

23.±10% duty cycle is supported for frequencies  50 MHz.

24.Maximum value only applies during Program/Erase Suspend/Resume commands.

25.Full V_CCrange (2.7 V–3.6 V) and CL = 30 pF.

26.Regulated V_CCrange (3.0 V–3.6 V) and CL = 30 pF.

27.Regulated V_CCrange (3.0 V–3.6 V) and CL = 15 pF.

28.Only applicable as a constraint for WRR instruction when SRWD is set to ‘1’.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Timing specifications

6.4.1

Clock timing

P_SCK

tCH

tCL

V_{IH min}

V_{CC / 2}

V_{IL max}

tCFT

tCRT

Figure 22

Clock timing

6.4.2

Input / output timing

tCS

CS#

tCSS

tCSH

tCSS

SCK

tSU

tHD

tLZ

tHO

tV

tDIS

MSB IN

LSB IN

MSB OUT.

LSB OUT

IO

Figure 23

SPI SDR dual-quad timing

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Timing specifications

6.5

DDR AC characteristics

Table 12

AC characteristics DDR operation

Parameter

Symbol

Min

DC

Typ

–

Max

80



–

Unit

MHz

ns

F

SCK clock frequency for DDR READ instruction

SCK clock period for DDR READ instruction

Clock HIGH time

SCK, R

P

10.75

–

SCK, R

t

, t

45% P

10

–

ns

WH CH

SCK

, t

Clock LOW time

–

ns

WL CL

CS# HIGH time (Read Instructions)

CS# active setup time (relative to SCK)

CS# active hold time (relative to SCK)

IO in setup time

–

ns

CS

3

–

ns

CSS

CSH

SU

3

–

ns

[29]

1.5

–

3000

ns

IO in hold time

–

ns

HD

[30]

Clock LOW to output valid

Output hold time

–

6.5

ns

V

–

ns

HO

Output disable time

–

8

ns

DIS

LZ

Clock to output LOW impedance

First output to last output data valid time

0

–

ns

–

600

ps

O_SKEW

Notes

29.Maximum value only applies during Program/Erase Suspend/Resume commands.

30.Regulated V_CCrange (3.0 V–3.6 V) and CL = 15 pF.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Timing specifications

6.5.1

DDR input timing

tCS

CS#

tCSH

tCSS

SCK

tHD

tSU

tHD

tSU

IO

MSB IN

LSB IN

Figure 24

SPI DDR input timing

6.5.2

DDR output timing

tCS

CS#

SCK

SI

tLZ

tHO

tV

tDIS

IO

MSB

LSB

Figure 25

SPI DDR output timing

Datasheet

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002-00466 Rev. *H

2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Timing specifications

P_SCK

tCL

tCH

SCK

tV

tOTT

tO_SKEW

Slow

D1

Slow

D2

IO0

IO1

IO2

Fast

D1

Fast

D2

IO3

D1

Valid

D2

Valid

IO_valid

tDV

Figure 26

SPI DDR data valid window

Notes

31.t_CLHis the shorter duration of t_CLor t_CH

.

32.t_{O_SKEW}is the maximum difference (delta) between the minimum and maximum t_V(output valid) across all

IO signals.

33.t_OTTis the maximum output transition time from one valid data value to the next valid data value on each IO.

34.t_OTTis dependent on system level considerations including:

a. Memory device output impedance (drive strength).

b. System level parasitics on the IOs (primarily bus capacitance).

c. Host memory controller input V_IHand V_ILlevels at which 0 to 1 and 1 to 0 transitions are recognized.

d. As an example, assuming that the above considerations result a memory output slew rate of 2 V/ns and a

3 V transition (from 1 to 0 or 0 to 1) is required by the host, the t_OTTwould be:

t_OTT= 3 V/(2 V/ns) = 1.5 ns

e. t_OTTis not a specification tested by Infineon, it is system dependent and must be derived by the system

designer based on the above considerations.

35.The minimum data valid window (t_DV) can be calculated as follows:

a. As an example, assuming:

i. 80 MHz clock frequency = 12.5 ns clock period

ii. DDR operations are specified to have a duty cycle of 45% or higher

iii. t_CLH= 0.45 × PSCK = 0.45 × 12.5 ns = 5.625 ns

iv. t_{O_SKEW}= 600 ps

v. t_OTT= 1.5 ns

b. t_DV= t_CLH– t_{O_SKEW}– t_OTT

c. t_DV= 5.625 ns – 600 ps – 1.5 ns = 3.525 ns

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Physical interface

7

Physical interface

Table 13

Model specific connections

Versatile I/O or V – V functionality is not supported on S79FL01GS. This signal must be tied to V on

CC

IO

CC

V

/ V

CC

IO

the PCB.

RESET# signal is bonded out and active on the S79FL01GS. The signal has an internal pull-up resistor and

may be left unconnected in the host system if not used.

RESET#

7.1

Dual-Quad 24-ball BGA package (ZSA024)

Connection diagram

7.1.1

1

2

3

4

5

A

B

C

D

E

RFU

SCK1

CS1#

IO1

CS2# RESET# RFU

SCK2

VSS

RFU

IO7

VSS

RFU

IO0

VCC

IO2

RFU

IO4

IO3

IO6

IO5

VIO/VCC VSS

Figure 27

Dual-Quad 24-ball BGA, 5 x 5 ball footprint (ZSA024), top view

Notes

36.Refer to Table 1 for signal descriptions.

37.The RESET# input has an internal pull-up and may be left unconnected in the system.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Physical interface

7.1.2

Physical diagram

NOTES:

DIMENSIONS

SYMBOL

1. ALL DIMENSIONS ARE IN MILLIMETERS.

MIN.

-

NOM.

MAX.

1.20

-

A

A1

D

-

2. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.

3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

0.20

-

8.00 BSC

6.00 BSC

4.00 BSC

5

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

E

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE

MD X ME.

D1

E1

MD

ME

n

5

24

6

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE

PARALLEL TO DATUM C.

b

0.35

0.40

0.45

eD

eE

SD

SE

1.00 BSC

0.00

7

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE

THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,

0.00

"SD" OR "SE" = 0.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,

METALLIZED MARK INDENTATION OR OTHER MEANS.

CYPRESS

002-15078 **

Company Confidential

TITLE

PACKAGE OUTLINE, 24 BALL FBGA

8.0X6.0X1.2 MM ZSA024

DRAWN BY

KOTA

DATE

THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS

SEMICONDUCTOR CORPORATION THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS

SPEC NO.

REV

5-JUL-16

PACKAGE

002 15078

ZSA024

Figure 28

24-ball FBGA (8.0 × 6.0 × 1.2 mm) package outline, 002-15078

7.1.3

Special handling instructions for FBGA packages

Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package

and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for

prolonged periods of time.

Datasheet

37

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Address space maps

8

Address space maps

Overview

8.1

8.1.1

Extended address

The S79FL01GS device supports 32-bit addresses to enable higher density devices than allowed by previous

generation (legacy) SPI devices that supported only 24-bit addresses. A 24-bit byte resolution address can access

only 16 Mbytes (128 Mbits) of maximum density. A 32-bit byte resolution address allows direct addressing of up

to a 4 Gbytes (32 Gbits) of address space.

Legacy commands continue to support 24-bit addresses for backward software compatibility. Extended 32-bit

addresses are enabled in three ways:

• Bank Address register — a software (command) loadable internal register that supplies the high order bits of

address when legacy 24-bit addresses are in use.

• Extended Address mode — a bank address register bit that changes all legacy commands to expect 32 bits of

address supplied from the host system.

• New commands — that perform both legacy and new functions, which expect 32-bit address.

The default condition at power-up and after reset, is the Bank address register loaded with zeros and the

extended address mode set for 24-bit addresses. This enables legacy software compatible access to the first

128 Mbits of a device.

8.1.2

Multiple address spaces

Many commands operate on the main flash memory array. Some commands operate on address spaces separate

from the main flash array. Each separate address space uses the full 32-bit address but may only define a small

portion of the available address space.

8.2

Flash memory array

The main flash array is divided into erase units called sectors. The sectors are organized as uniform 512-kbyte

sectors.

Table 14

S79FL01GS sector and memory address map, uniform 512-kbyte sectors

Sector size (kbyte)

Sector count

Sector range

Address range (8-bit)

00000000h–0003FFFFh

:

Notes

Sector starting

address

SA00

:

512

256

—

Sector ending

address

SA255

03FC0000h–03FFFFFFh

Note: This is a condensed table that uses a sector as a reference. There are address ranges that are not explicitly

listed. All 512-kB sectors have the pattern XXXX0000h–XXXXFFFFh.

8.3

ID-CFI address space

The RDIDJ command (9Fh) reads information from a separate flash memory address space for device

identification (ID) and common flash interface (CFI) information. See “Device ID and common flash interface

(ID-CFI) address map” on page 113 for the tables defining the contents of the ID-CFI address space. The ID-CFI

address space is programmed by Infineon and read-only for the host system.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Address space maps

8.4

JEDEC JESD216 serial flash discoverable parameters (SFDP) space

The RSFDP command (5Ah) reads information from a separate Flash memory address space for device

identification, feature, and configuration information, in accord with the JEDEC JESD216 standard for serial flash

discoverable parameters. The ID-CFI address space is incorporated as one of the SFDP parameters.

See “Serial flash discoverable parameters (SFDP) address map” on page 109 for the table defining the

contents of the SFDP address space. The SFDP address space is programmed by Infineon and is read-only for the

host system

8.5

OTP address space

Each S79FL01GS memory device has a 2048-byte one time program (OTP) address space that is separate from

the main flash array. The OTP area is divided into 64, individually lockable, 32-byte aligned and length regions.

In the 64-byte region starting at address zero:

• The 16 lowest address bytes are programmed by Infineon with a 128-bit random number. Only Infineon is able

to program these bytes.

• The next 4 higher address bytes (OTP lock bytes) are used to provide one bit per OTP region to permanently

protect each region from programming. The bytes are erased when shipped from Infineon. After an OTP region

is programmed, it can be locked to prevent further programming, by programming the related protection bit

in the OTP lock bytes.

• The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU

bytes may be programmed by the host system but it must be understood that a future device may use those

bits for protection of a larger OTP space. The bytes are erased when shipped from Infineon.

The remaining regions are erased when shipped from Infineon, and are available for programming of additional

permanent data.

Refer to Figure 29 for a pictorial representation of the OTP memory space.

The OTP memory space is intended for increased system security. OTP values, such as the random number

programmed by Infineon, can be used to “mate” a flash component with the system CPU/ASIC to prevent device

substitution.

The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming when

set to ‘1’. This allows trusted boot code to control programming of OTP regions then set the FREEZE bit to prevent

further OTP memory space programming during the remainder of normal power-on system operation.

During the programming of each OTP region, bits 0–3 are programmed on Quad SPI-1 via IO0–IO3, and bits 4–7

are programmed on Quad SPI-2 via IO4–IO7.

Quad SPI-2

Quad SPI-1

32-byte OTP Region 31

32-byte OTP Region 30

32-byte OTP Region 31

32-byte OTP Region 30

32-byte OTP Region 29

.

When programmed to

‘0‘ each lock bit

protects its related 32

byte region from any

further programming

When programmed to

‘0‘ each lock bit

protects its related 32

byte region from any

further programming

32-byte OTP Region 3

32-byte OTP Region 2

32-byte OTP Region 1

32-byte OTP Region 0

32-byte OTP Region 2

32-byte OTP Region 1

32-byte OTP Region 0

...

Lock Bits 31 to 0

...

Lock Bits 31 to 0

{

Reserved

Lock Bytes

16-byte Random Number

Byte 0

Reserved

Lock Bytes

16-byte Random Number

Byte 0

Contents of Region 0

{

Byte 1F

Byte 10

Byte 1F

Byte 10

Figure 29

OTP address space — Quad SPI-1 and Quad SPI-2

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Address space maps

Table 15

OTP address map for Quad SPI-1 and Quad SPI-2

Region

Byte address range (Hex)

Contents

Initial delivery state (Hex)

Least Significant Byte of

Infineon programmed random

number

000

...

Infineon programmed random

number

...

Most Significant Byte of

Infineon programmed random

number

00F

Region 0

Region Locking Bits

Byte 10 [bit 0] locks region 0

from programming when = 0

...

[38]

010 to 013

All bytes = FF

Byte 13 [bit 7] locks region 31

from programming when = 0

014 to 01F

020 to 03F

Reserved for Future Use (RFU)

All bytes = FF

Available for user

programming

Region 1

Region 2

...

Available for user

programming

040 to 05F

...

All bytes = FF

Available for user

programming

Available for user

programming

Region 31

7E0 to 7FF

Note

38.It is recommended that the Lock Bytes for Quad SPI-1 and Quad SPI-2 be programmed with identical data.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Address space maps

8.6

Registers

Registers are small groups of memory cells used to configure how the S79FL01GS memory device operates or to

report the status of device operations. The registers are accessed by specific commands. The commands (and

hexadecimal instruction codes) used for each register are noted in each register description.

The S79FL01GS Dual-Quad SPI device has a register of each type, one for each individual die. These include the

Status Register 1, Status Register 2, Configuration Register, AutoBoot Register, Bank Address Register, ASP

Register, Password Register, PPB Lock Register, PPB Access Register, DYB Access Register, and DDR Data Learning

Registers. Each register must be accessed by a command given in parallel to IO0–IO3 (Quad SPI-1) and for

IO4–IO7 (Quad SPI-2). Reading and writing to each of these registers must also be done in parallel for IO0–IO3

(Quad SPI-1) and for IO4–IO7 (Quad SPI-2).

The individual register bits may be volatile, nonvolatile, or one time programmable (OTP). The type for each bit

is noted in each register description. The default state shown for each bit refers to the state after power-on reset,

hardware reset, or software reset if the bit is volatile. If the bit is nonvolatile or OTP, the default state is the value

of the bit when the device is shipped from Infineon. Nonvolatile bits have the same cycling (erase and program)

endurance as the main flash array.

Table 16

Register descriptions

Register

Abbreviation

SR1[7:0]

Type

Volatile

RFU

Bit location

Status Register 1

7:0

31:0

7:0

15:1

0

Configuration Register 1

Status Register 2

AutoBoot Register

Bank Address Register

ECC Status Register

ASP Register

CR1[7:0]

SR2[7:0]

ABRD[31:0]

BRAC[7:0]

ECCSR[7:0]

ASPR[15:1]

ASPR[0]

Nonvolatile

Volatile

OTP

ASP Register

RFU

Password Register

PPB Lock Register

PASS[63:0]

PPBL[7:1]

Nonvolatile OTP

Volatile

63:0

7:1

Volatile

PPB Lock Register

PPBL[0]

0

Read Only

PPB Access Register

PPBAR[7:0]

DYBAR[7:0]

NVDLR[7:0]

VDLR[7:0]

Nonvolatile

Volatile

7:0

DYB Access Register

SPI DDR Data Learning Registers

Nonvolatile

Volatile

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8.6.1

Status Register 1 (SR1)

Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN 06h),

Write Disable (WRDI 04h), Clear Status Register (CLSR 30h).

Table 17

Bits

Status Register 1 (SR1)

Function

Field

Type

Default state

Description

name

1 = Locks state of SRWD, BP, and Configuration

Register bits when WP# is LOW by ignoring

WRR command

Status Register Write

Disable

7

SRWD

Nonvolatile

0

0 = No protection, even when WP# is LOW

Programming Error Volatile, Read

1 = Error occurred

0 = No Error

6

5

P_ERR

E_ERR

0

Occurred

only

Volatile, Read

only

1 = Error occurred

0 = No Error

Erase Error Occurred

4

3

BP2

BP1

1

Volatile

if CR1[3] = 1,

0

if CR1[3] = 1,

Nonvolatile

if CR1[3] = 0

Protects selected range of sectors (Block)

from Program or Erase.

Block Protection

Write Enable Latch

Write in Progress

whenshipped

from Infineon

2

BP0

1 = Device accepts Write Registers (WRR),

Program or Erase commands

0 = Device ignores Write Registers (WRR),

Program or Erase commands

1

WEL

Volatile

0

This bit is not affected by WRR, only WREN and

WRDI commands affect this bit.

1 = Device Busy, a Write Registers (WRR),

program, erase or other operation is in

progress

Volatile, Read

only

0

WIP

0 = Ready Device is in Standby mode and can

accept commands

The Status Register contains both status and control bits:

Status Register Write Disable (SRWD) SR1[7]: Places the device in the Hardware Protected mode when this bit

is set to ‘1’ and the WP# input is driven LOW. In this mode, the SRWD, BP2, BP1, and BP0 bits of the Status Register

become read-only bits and the Write Registers (WRR) command is no longer accepted for execution. If WP# is

HIGH, the SRWD bit and BP bits may be changed by the WRR command. If SRWD is ‘0’, WP# has no effect and the

SRWD bit and BP bits may be changed by the WRR command. The SRWD bit has the same nonvolatile endurance

as the main flash array.

Program Error (P_ERR) SR1[6]: The Program Error Bit is used as a program operation success or failure

indication. When the Program Error bit is set to ‘1’, it indicates that there was an error in the last program

operation. This bit will also be set when the user attempts to program within a protected main memory sector or

locked OTP region. When the Program Error bit is set to ‘1’, this bit can be reset to ‘0’ with the Clear Status Register

(CLSR) command. This is a read-only bit and is not affected by the WRR command.

Erase Error (E_ERR) SR1[5]: The Erase Error Bit is used as an Erase operation success or failure indication. When

the Erase Error bit is set to ‘1’, it indicates that there was an error in the last erase operation. This bit will also be

set when the user attempts to erase an individual protected main memory sector. The Bulk Erase command will

not set E_ERR if a protected sector is found during the command execution. When the Erase Error bit is set to ‘1’,

this bit can be reset to ‘0’ with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected

by the WRR command.

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Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be software-protected

against program and erase commands. The BP bits are either volatile or nonvolatile, depending on the state of

the BP nonvolatile bit (BPNV) in the configuration register. When one or more of the BP bits is set to ‘1’, the

relevant memory area is protected against program and erase. The Bulk Erase (BE) command can be executed

only when the BP bits are cleared to 0’s. See “Block protection” on page 54 for a description of how the BP bit

values select the memory array area protected. The BP bits have the same nonvolatile endurance as the main

flash array.

Write Enable Latch (WEL) SR1[1]: The WEL bit must be set to ‘1’ to enable program, write, or erase operations

as a means to provide protection against inadvertent changes to memory or register values. The Write Enable

(WREN) command execution sets the Write Enable Latch to ‘1’ to allow any program, erase, or write commands

to execute afterwards. The Write Disable (WRDI) command can be used to set the Write Enable Latch to ‘0’ to

prevent all program, erase, and write commands from execution. The WEL bit is cleared to ‘0’ at the end of any

successful program, write, or erase operation. Following a failed operation the WEL bit may remain set and

should be cleared with a WRDI command following a CLSR command. After a power down/power up sequence,

hardware reset, or software reset, the Write Enable Latch is set to ‘0’. The WRR command does not affect this bit.

Write In Progress (WIP) SR1[0]: Indicates whether the device is performing a program, write, erase operation,

or any other operation, during which a new operation command will be ignored. When the bit is set to ‘1’, the

device is busy performing an operation. While WIP is ‘1’, only Read Status (RDSR1 or RDSR2), Erase Suspend

(ERSP), Program Suspend (PGSP), Clear Status Register (CLSR), and Software Reset (RESET) commands may be

accepted. ERSP and PGSP will only be accepted if memory array erase or program operations are in progress. The

status register E_ERR and P_ERR bits are updated while WIP = 1. When P_ERR or E_ERR bits are set to ‘1’, the WIP

bit will remain set to one indicating the device remains busy and unable to receive new operation commands. A

Clear Status Register (CLSR) command must be received to return the device to standby mode. When the WIP bit

is cleared to 0 no operation is in progress. This is a read-only bit.

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8.6.2

Configuration Register 1 (CR1)

Related Commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h). The Configuration

Register bits can be changed using the WRR command with sixteen input cycles.

The Configuration Register controls certain interface and data protection functions.

Table 18

Bits

Configuration Register 1 (CR1)

Default

state

Field name

Function

Type

Description

7

6

LC1

LC0

0

Selects number of initial read latency cycles

See Table 19 and Table 20

Latency Code

Nonvolatile

Configures Start of

Block Protection

1 = BP starts at bottom (Low address)

0 = BP starts at top (High address)

5

4

3

2

TBPROT

DNU

OTP

DNU

OTP

RFU

0

DNU

Do Not Use

Configures BP2–0 in

Status Register

1 = Volatile

BPNV

RFU

0 = Nonvolatile

RFU

Reserved for Future Use

1 = Quad

Puts the device into

Quad I/O operation

For the S79FL01GS Dual-Quad SPI device, the

default state is set for QUAD and cannot be

changed.

1

QUAD

Nonvolatile

1

Lock current state of

BP2–0 bits in Status

Register, TBPROT in

Configuration

1 = Block Protection and OTP locked

0 = Block Protection and OTP unlocked

0

FREEZE

Volatile

0

Register, and OTP

regions

Latency Code (LC) CR1[7:6]: The Latency Code selects the number of mode and dummy cycles between the end

of address and the start of read data output for all read commands.

Some read commands send mode bits following the address to indicate that the next command will be of the

same type with an implied, rather than an explicit, instruction. The next command thus does not provide an

instruction byte, only a new address and mode bits. This reduces the time needed to send each command when

the same command type is repeated in a sequence of commands.

Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array

before data can be returned to the host system. Some read commands require additional latency cycles as the

SCK frequency is increased.

The following latency code tables provide different latency settings that are configured by Infineon.

Where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported

at the frequency shown. Read is supported only up to 50 MHz but the same latency value is assigned in each

latency code and the command may be used when the device is operated at  50 MHz with any latency code

setting. Similarly, only the Fast Read command is supported up to 133 MHz but the same 10b latency code is used

for Fast Read up to 133 MHz and for the other dual and quad read commands up to 104 MHz. It is not necessary

to change the latency code from a higher to a lower frequency when operating at lower frequencies where a

particular command is supported. The latency code values for a higher frequency can be used for accesses at

lower frequencies.

The Enhanced High Performance settings provide latency options the same or faster than additional alternate

source SPI memories.

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Read DDR Data Learning Pattern (DLP) bits may be placed within the dummy cycles immediately before the start

of read data, if there are five or more dummy cycles. See “Read Memory Array commands” on page 80 for more

information on the DLP.

Table 19

Latency codes for SDR enhanced high performance

Read

Fast Read

(0Bh, 0Ch)

Read Quad Out

(6Bh, 6Ch)

Quad I/O Read

(EBh, ECh)

Freq.

LC

(03h, 13h)

(MHz)

Mode

Dummy

Mode

Dummy

Mode

Dummy

Mode

Dummy

≤ 50

≤ 80

≤ 90

11

00

01

0

–

0

–

0

8

0

2

1

0

–

8

–

2

–

4

5

–

≤ 104 10

≤ 133 10

Table 20

Latency codes for DDR enhanced high performance

DDR Quad I/O Read

(EDh, EEh)

Freq. (MHz)

LC

Mode

Dummy

≤ 50

≤ 80

11

00

1

3

7

Note

39.When using DDR I/O commands with the data learning pattern (DLP) enabled, a latency code that provides

five or more dummy cycles should be selected to allow one cycle of additional time for the host to stop

driving before the memory starts driving the four cycle DLP. So it is recommended to use LC 00 for DDR Quad

IO Read, if the data learning pattern (DLP) for DDR is used.

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Top or Bottom Protection (TBPROT) CR1[5]: This bit defines the operation of the Block Protection bits BP2,

BP1, and BP0 in the Status Register. As described in the status register section, the BP2–0 bits allow the user to

optionally protect a portion of the array, ranging from 1/64, 1/4, 1/2, etc., up to the entire array. When TBPROT is

set to ‘0’, the Block Protection is defined to start from the top (maximum address) of the array. When TBPROT is

set to ‘1’, the Block Protection is defined to start from the bottom (zero address) of the array. The TBPROT bit is

OTP and set to ‘0’ when shipped from Infineon. If TBPROT is programmed to ‘1’, an attempt to change it back to

‘0’ will fail and set the Program Error bit (P_ERR in SR1[6]).

The desired state of TBPROT must be selected during the initial configuration of the device during system

manufacture; before the first program or erase operation on the main flash array. TBPROT must not be

programmed after programming or erasing is done in the main flash array.

CR1[4]: Reserved for Future Use

Block Protection Nonvolatile (BPNV) CR1[3]: The BPNV bit defines whether or not the BP2–0 bits in the Status

Register are volatile or nonvolatile. The BPNV bit is OTP and cleared to a0 with the BP bits cleared to 000 when

shipped from Infineon. When BPNV is set to ‘0’, the BP2–0 bits in the Status Register are nonvolatile. When BPNV

is set to ‘1’, the BP2–0 bits in the Status Register are volatile and will be reset to binary 111 after POR, hardware

reset, or command reset. If BPNV is programmed to ‘1’, an attempt to change it back to ‘0’ will fail and set the

Program Error bit (P_ERR in SR1[6]).

CR1[2]: Reserved for Future Use.

Quad Data Width (QUAD) CR1[1]: When set to ‘1’, this bit switches the data width of the device to 4-bit Quad

mode. The commands for Serial Read still function normally. The QUAD bit in the S79FL01GS device is factory set

to ‘1’ and should not be changed.

Freeze Protection (FREEZE) CR1[0]: The Freeze Bit, when set to ‘1’, locks the current state of the BP2–0 bits in

Status Register, the TBPROT and TBPARM bits in the Configuration Register, and the OTP address space. This

prevents writing, programming, or erasing these areas. As long as the FREEZE bit remains cleared to logic 0 the

other bits of the Configuration Register, including FREEZE, are writable, and the OTP address space is

programmable. Once the FREEZE bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off

to power-on cycle or a hardware reset. Software reset will not affect the state of the FREEZE bit. The FREEZE bit

is volatile and the default state of FREEZE after power-on is ‘0’. The FREEZE bit can be set in parallel with updating

other values in CR1 by a single WRR command.

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8.6.3

Status Register 2 (SR2)

Related Commands: Read Status Register 2 (RDSR2 07h).

Table 21 Status Register 2 (SR2)

Default

state

Bits Fieldname

Function

Type

Description

Reserved for Future Use

7

6

5

4

3

2

RFU

Reserved

–

0

Reserved for Future Use

Volatile, Read

only

1 = In Erase Suspend mode

1

0

ES

PS

Erase Suspend

0

0 = Not in Erase Suspend mode

Volatile, Read

only

1 = In Program Suspend mode

Program Suspend

0 = Not in Program Suspend mode

Erase Suspend (ES) SR2[1]: The Erase Suspend bit is used to determine when the device is in Erase Suspend

mode. This is a status bit that cannot be written. When Erase Suspend bit is set to ‘1’, the device is in erase

suspend mode. When Erase Suspend bit is cleared to ‘0’, the device is not in erase suspend mode. Refer to Erase

Suspend and Resume Commands (75h) (7Ah) for details about the Erase Suspend/Resume commands.

Program Suspend (PS) SR2[0]: The Program Suspend bit is used to determine when the device is in Program

Suspend mode. This is a status bit that cannot be written. When Program Suspend bit is set to ‘1’, the device is in

program suspend mode. When the Program Suspend bit is cleared to ‘0’, the device is not in program suspend

mode. Refer to “Program Suspend (PGSP 85h) and Resume (PGRS 8Ah)” on page 92 for details.

8.6.4

AutoBoot Register

Related Commands: AutoBoot Read (ABRD 14h) and AutoBoot Write (ABWR 15h).

The AutoBoot Register provides a means to automatically read boot code as part of the power on reset, hardware

reset, or software reset process.

Table 22

AutoBoot Register

Default

state

Bits Fieldname

Function

Type

Description

AutoBoot Start

Address

512 byte boundary address for the start of

boot code access

31 to 9

8 to 1

0

ABSA

ABSD

ABE

Nonvolatile

000000h

Number of initial delay cycles between CS#

going LOW and the first bit of boot code being

transferred

AutoBoot Start Delay Nonvolatile

AutoBoot Enable Nonvolatile

00h

0

1 = AutoBoot is enabled

0 = AutoBoot is not enabled

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8.6.5

Bank Address Register

Related Commands: Bank Register Access (BRAC B9h), Write Register (WRR 01h), Bank Register Read (BRRD 16h)

and Bank Register Write (BRWR 17h).

The Bank Address register supplies additional high order bits of the main flash array byte boundary address for

legacy commands that supply only the low order 24 bits of address. The Bank Address is used as the high bits of

address (above A23) for all 3-byte address commands when EXTADD = 0. The Bank Address is not used when

EXTADD = 1 and traditional 3-byte address commands are instead required to provide all four bytes of address.

Table 23

Bank Address Register (BAR)

Bits Fieldname

Function

Type

Default state

Description

1 = 4-byte (32-bits) addressing required from

command.

Extended Address

Enable

7

EXTADD

Volatile

0b

0 = 3-byte (24-bits) addressing from command

+ Bank Address

6 to 2

RFU

BA25

RFU

Reserved

Volatile

00000b

Reserved for Future Use

A25 for 1 Gb device

1

0

Bank Address

0

RFU for lower density device

Extended Address (EXTADD) BAR[7]: EXTADD controls the address field size for legacy SPI commands. By

default (power up reset, hardware reset, and software reset), it is cleared to ‘0’ for 3 bytes (24 bits) of address.

When set to ‘1’, the legacy commands will require 4 bytes (32 bits) for the address field. This is a volatile bit.

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8.6.6

ECC Status Register (ECCSR)

Related Commands: ECC Read (ECCRD 18h). ECCSR does not have user programmable nonvolatile bits. All

defined bits are volatile read only status. The default state of these bits are set by hardware. See “Automatic

ECC” on page 89.

The status of ECC in each ECC unit is provided by the 8-bit ECC Status Register (ECCSR). The ECC Register Read

command is written followed by an ECC unit address. The contents of the status register then indicates, for the

selected ECC unit, whether there is an error in the ECC unit eight bit error correction code, the ECC unit of 16 Bytes

of data, or that ECC is disabled for that ECC unit.

Table 24

ECC Status Register (ECCSR)

Default

state

Bits Fieldname

Function

Type

Description

Reserved for Future Use

7 to 3

2

RFU

Reserved

0

1 = Single Bit Error found in the ECC unit eight

bit error correction code

Volatile, Read

only

EECC

Error in ECC

0

0 = No error

Volatile, Read

only

1 = Single Bit Error corrected in ECC unit data

0 = No error

1

0

EECCD

ECCDI

Error in ECC unit data

ECC Disabled

0

Volatile, Read

only

1 = ECC is disabled in the selected ECC unit

0 = ECC is enabled in the selected ECC unit

ECCSR[2] = 1 indicates an error was corrected in the ECC. ECCSR[1] = 1 indicates an error was corrected in the ECC

unit data. ECCSR[0] = 1 indicates the ECC is disabled. The default state of ‘0’ for all these bits indicates no failures

and ECC is enabled.

ECCSR[7:3] are reserved. These have undefined high or low values that can change from one ECC status read to

another. These bits should be treated as “don’t care” and ignored by any software reading status.

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8.6.7

ASP Register (ASPR)

Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh).

The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector

Protection (ASP) features.

Table 25

ASP Register (ASPR)

Bits Fieldname

Function

Reserved

Type

OTP

Default state

1

Description

Reserved for Future Use

15 to 9

RFU

8

7

6

5

4

3

Note 40

1

Reserved for Future Use

Note 40

0 = Password Protection Mode permanently

enabled

Password Protection

Mode Lock Bit

2

PWDMLB

OTP

1

1 = Password Protection Mode not

permanently enabled

0 = Persistent Protection Mode permanently

enabled

Persistent Protection

Mode Lock Bit

1

0

PSTMLB

RFU

OTP

1

1 = Persistent Protection Mode not

permanently enabled

Reserved

Reserved for Future Use

Reserved for Future Use (RFU) ASPR[15:3, 0].

Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to ‘0’, the Password Protection

Mode is permanently selected.

Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to ‘0’, the Persistent Protection

Mode is permanently selected. PWDMLB and PSTMLB are mutually exclusive, only one may be programmed to ‘0’.

Note

40.Default value depends on ordering part number, see “Initial delivery state” on page 133.

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8.6.8

Password Register (PASS)

Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h).

Table 26

Bits

Password Register (PASS)

Field

Function

Type

Default state

Description

name

Nonvolatile OTP storage of 64-bit password.

The password is no longer readable after the

password protection mode is selected by

programming ASP register bit 2 to ‘0’.

Hidden

63 to 0

PWD

OTP

FFFFFFFF–FFFFFFFFh

Password

8.6.9

PPB Lock Register (PPBL)

Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h)

Table 27

Bits

PPB Lock Register (PPBL)

Field

Function

Type

Default state

Description

name

7 to 1

RFU

Reserved

Volatile

00h

Reserved for Future Use

Persistent Protection

Mode = 1

0 = PPB array protected until next power cycle

or hardware reset

Protect PPB

Array

0

PPBLOCK

Volatile

Password Protection

Mode = 0

1 = PPB array may be programmed or erased.

8.6.10

PPB Access Register (PPBAR)

Related Commands: PPB Read (PPBRD E2h)

Table 28 PPB Access Register (PPBAR)

Default

state

Bits Fieldname

Function

Type

Description

00h = PPB for the sector addressed by the

PPBRD or PPBP command is programmed to

‘0’, protecting that sector from program or

erase operations.

Read or Program per

sector PPB

7 to 0

PPB

Nonvolatile

FFh

FFh = PPB for the sector addressed by the

PPBRD or PPBP command is erased to ‘1’, not

protecting that sector from program or erase

operations.

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8.6.11

DYB Access Register (DYBAR)

Related Commands: DYB Read (DYBRD E0h) and DYB Program (DYBP E1h).

Table 29 DYB Access Register (DYBAR)

Bits Fieldname

Function

Type

Default state

Description

00h = DYB for the sector addressed by the

DYBRD or DYBP command is cleared to ‘0’,

protecting that sector from program or erase

operations.

Read or Write per

sector DYB

7 to 0

DYB

Volatile

FFh

FFh = DYB for the sector addressed by the

DYBRD or DYBP command is set to ‘1’, not

protecting that sector from program or erase

operations.

8.6.12

SPI DDR Data Learning Registers

Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern Read

(DLPRD 41h).

The Data Learning Pattern (DLP) resides in an 8-bit Nonvolatile Data Learning Register (NVDLR) as well as an 8-bit

Volatile Data Learning Register (VDLR). When shipped from Infineon, the NVDLR value is 00h. Once programmed,

the NVDLR cannot be reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the

VDLR. The VDLR can be written to at any time, but on reset or power cycles the data pattern will revert back to

what is in the NVDLR. During the learning phase described in the SPI DDR modes, the DLP will come from the

VDLR. Each IO will output the same DLP value for every clock edge. For example, if the DLP is 34h (or binary

00110100) then during the first clock edge all IOs will output ‘0’; subsequently, the 2nd clock edge all I/O’s will

output ‘0’, the 3rd will output ‘1’, etc.

When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR

commands.

Table 30

Bits

Nonvolatile Data Learning Register (NVDLR)

Field

Function

Type

Default state

Description

name

OTP value that may be transferred to the host

during DDR read command latency (dummy)

cycles to provide a training pattern to help the

host more accurately center the data capture

point in the received data bits.

Nonvolatile Data

Learning Pattern

7 to 0

NVDLP

OTP

00h

Table 31

Bits

Volatile Data Learning Register (NVDLR)

Field

Function

Type

Default state

Description

name

Volatile copy of the NVDLP used to enable and

deliver the Data Learning Pattern (DLP) to the

outputs. The VDLP may be changed by the

host during system operation.

Takes the value of

Volatile Data

7 to 0

VDLP

Volatile NVDLR during POR or

Reset

Learning Pattern

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9

Data protection

9.1

Secure silicon region (OTP)

The device has a 2048-byte one time program (OTP) address space that is separate from the main flash array. The

OTP area is divided into 32, individually lockable, 64-byte aligned and length regions.

The OTP memory space is intended for increased system security. OTP values can “mate” a flash component with

the system CPU/ASIC to prevent device substitution. See “OTP address space” on page 39, “One Time Program

Array commands” on page 97, and “OTP Read (OTPR 4Bh)” on page 98.

9.1.1

Reading OTP memory space

The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 2-kB OTP

address range will yield indeterminate data.

9.1.2

Programming OTP memory space

The protocol of the OTP programming command is the same as Page Program. The OTP Program command can

be issued multiple times to any given OTP address, but this address space can never be erased. The valid address

range for OTP Program is depicted in Figure 29. OTP Program operations outside the valid OTP address range

will be ignored and the WEL in SR1 will remain high (set to ‘1’). OTP Program operations while FREEZE = 1 will fail

with P_ERR in SR1 set to ‘1’.

9.1.3

Infineon programmed random number

Infineon standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF)

with a 128-bit random number using the Linear Congruential Random Number method. The seed value for the

algorithm is a random number concatenated with the day and time of tester insertion.

9.1.4

Lock bytes

The LSB of each Lock byte protects the lowest address region related to the byte, the MSB protects the highest

address region related to the byte. The next higher address byte similarly protects the next higher 8 regions. The

LSB bit of the lowest address Lock Byte protects the higher address 16 bytes of the lowest address region. In other

words, the LSB of location 0x10 protects all the Lock Bytes and RFU bytes in the lowest address region from

further programming. See “OTP address space” on page 39.

9.2

Write Enable command

The Write Enable (WREN) command must be written prior to any command that modifies nonvolatile data. The

WREN command sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to ‘0’ (disables writes) during

power-up, hardware reset, or after the device completes the following commands:

• Reset

• Page Program (PP)

• Sector Erase (SE)

• Bulk Erase (BE)

• Write Disable (WRDI)

• Write Registers (WRR)

• Quad-input Page Programming (QPP)

• OTP Byte Programming (OTPP)

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9.3

Block protection

The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register

TBPROT bit can be used to protect an address range of the main flash array from program and erase operations.

The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range

is selected by the TBPROT bit of the Configuration Register.

Table 32

BP2

Upper array start of protection (TBPROT = 0)

Status register content

Protected memory (kbytes)

Protected fraction of memory array

S79FL01GS

1024 Mb

BP1

BP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

0

Upper 64th

Upper 32nd

Upper 16th

Upper 8th

Upper 4th

Upper Half

All Sectors

2048

4096

8192

16384

32768

65536

131072

Table 33

BP2

Lower array start of protection (TBPROT = 1)

Status register content

Protected memory (kbytes)

Protected fraction of memory array

S79FL01GS

1024 Mb

BP1

BP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

0

Lower 64th

Lower 32nd

Lower 16th

Lower 8th

Lower 4th

Lower Half

All Sectors

2048

4096

8192

16384

32768

65536

131072

When Block Protection is enabled (i.e., any BP2–0 are set to ‘1’), advanced sector protection (ASP) can still be

used to protect sectors not protected by the block protection scheme. In the case that both ASP and block

protection are used on the same sector the logical OR of ASP and Block Protection related to the sector is used.

Recommendation: ASP and block protection should not be used concurrently. Use one or the other, but not both.

9.3.1

Freeze bit

Bit 0 of the Configuration Register is the FREEZE bit. The FREEZE bit locks the BP2–0 bits in Status Register-1 and

the TBPROT bit in the Configuration Register to their value at the time the FREEZE bit is set to ‘1’. Once the FREEZE

bit has been written to a logic 1 it cannot be cleared to a logic 0 until a power-on-reset is executed. As long as the

FREEZE bit is cleared to logic 0 the status register BP bits and the TBPROT bit of the Configuration Register are

writable. The FREEZE bit also protects the entire OTP memory space from programming when set to ‘1’. Any

attempt to change the BP bits with the WRR command while FREEZE = 1 is ignored and no error status is set.

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9.4

Advanced sector protection

Advanced sector protection (ASP) is the name used for a set of independent hardware and software methods

used to disable or enable programming or erase operations, individually, in any or all sectors. An overview of

these methods is shown in Figure 30.

Block Protection and ASP protection settings for each sector are logically OR’d to define the protection for each

sector, i.e. if either mechanism is protecting a sector the sector cannot be programmed or erased. Refer to “Block

protection” on page 54 for full details of the BP2–0 bits.

ASP Register

One Time Programmable

Password Method Persistent Method

(ASPR[2]=0)

(ASPR[1]=0)

6.) Password Method requires a

password to set PPB Lock to ‘1’

to enable program or erase of

PPB bits

7.) Persistent Method only allows

PPB Lock to be cleared to ‘0’ to

prevent program or erase of PPB

bits. Power off or hardware reset

required to set PPB Lock to ‘1’

64-bit Password

(One Time Protect)

4.) PPB Lock bit is volatile and

defaults to ‘1’ (persistent

mode), or ‘0’ (password mode)

upon reset

PBB Lock Bit

‘0’ = PPBs locked

‘1’ =PPBs unlocked

5.) PPB Lock = ‘0’ locks all PPBs

to their current state

Persistent

Protection Bit

(PPB)

Dynamic

Protection Bit

(DYB)

Memory Array

Sector 0

Sector 1

Sector 2

PPB 0

DYB 0

DYB 1

DYB 2

PPB 1

1

PPB 2

Sector N-2

Sector N-1

Sector N

PPB N-2

PPB N-1

PPB N

DYB N-2

DYB N-1

DYB N

3.) DYB are volatile bits

1.) N = Highest Address Sector

a sector is protected if its PPB =’0’

or its DYB = ‘0’

PPB are programmed individually

but erased as a group

2.)

Figure 30

Advanced sector protection overview

Every main flash array sector has a nonvolatile (PPB) and a volatile (DYB) protection bit associated with it. When

either bit is ‘0’, the sector is protected from program and erase operations.

The PPB bits are protected from program and erase when the PPB Lock bit is ‘0’. There are two methods for

managing the state of the PPB Lock bit, Persistent Protection and Password Protection.

The Persistent Protection method sets the PPB Lock bit to ‘1’ during POR, or Hardware Reset so that the PPB bits

are unprotected by a device reset. There is a command to clear the PPB Lock bit to ‘0’ to protect the PPB. There

is no command in the Persistent Protection method to set the PPB Lock bit to ‘1’, therefore the PPB Lock bit will

remain at ‘0’ until the next power-off or hardware reset. The Persistent Protection method allows boot code the

option of changing sector protection by programming or erasing the PPB, then protecting the PPB from further

change for the remainder of normal system operation by clearing the PPB Lock bit to ‘0’. This is sometimes called

Boot-code controlled sector protection.

The Password method clears the PPB Lock bit to ‘0’ during POR, or Hardware Reset to protect the PPB. A 64-bit

password may be permanently programmed and hidden for the password method. A command can be used to

provide a password for comparison with the hidden password. If the password matches, the PPB Lock bit is set

to ‘1’ to unprotect the PPB. A command can be used to clear the PPB Lock bit to ‘0’. This method requires use of

a password to control PPB protection.

The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP Register so

as to permanently select the method used.

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9.4.1

ASP register

The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP) features.

See Table 25.

As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors

unprotected, when power is applied. The device programmer or host system must then choose which sector

protection method to use. Programming either of the, one-time programmable, Protection Mode Lock Bits, locks

the part permanently in the selected mode:

• ASPR[2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.

• ASPR[2:1] = 10 = Persistent Protection Mode permanently selected.

• ASPR[2:1] = 01 = Password Protection Mode permanently selected.

• ASPR[2:1] = 00 = Illegal condition, attempting to program both bits to zero results in a programming failure.

ASP register programming rules:

• If the password mode is chosen, the password must be programmed prior to setting the Protection Mode Lock

Bits.

• Once the Protection Mode is selected, the Protection Mode Lock Bits are permanently protected from

programming and no further changes to the ASP register is allowed.

The programming time of the ASP Register is the same as the typical page programming time. The system can

determine the status of the ASP register programming operation by reading the WIP bit in the Status Register.

See “Status Register 1 (SR1)” on page 42 for information on WIP.

After selecting a sector protection method, each sector can operate in each of the following states:

• Dynamically Locked — A sector is protected and can be changed by a simple command.

• Persistently Locked — A sector is protected and cannot be changed if its PPB Bit is ‘0’.

• Unlocked — The sector is unprotected and can be changed by a simple command.

9.4.2

Persistent protection bits

The persistent protection bits (PPB) are located in a separate nonvolatile flash array. One of the PPB bits is related

to each sector. When a PPB is ‘0’, its related sector is protected from program and erase operations. The PPB are

programmed individually but must be erased as a group, similar to the way individual words may be programmed

in the main array but an entire sector must be erased at the same time. The PPB have the same program and erase

endurance as the main flash memory array. Preprogramming and verification prior to erasure are handled by the

device.

Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical sector

erase time. During PPB bit programming and PPB bit erasing, status is available by reading the Status register.

Reading of a PPB bit requires the initial access time of the device.

9.4.3

Dynamic protection bits

Dynamic protection bits are volatile and unique for each sector and can be individually modified. DYB only

control the protection for sectors that have their PPB set to ‘1’. By issuing the DYB Write command, a DYB is

cleared to ‘0’ or set to ‘1’, thus placing each sector in the protected or unprotected state respectively. This feature

allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy removal of

protection when changes are needed. The DYBs can be set or cleared as often as needed as they are volatile bits.

Notes

41.Each PPB is individually programmed to ‘0’ and all are erased to ‘1’ in parallel.

42.If the PPB Lock bit is ‘0’, the PPB Program or PPB Erase command does not execute and fails without

programming or erasing the PPB.

43.The state of the PPB for a given sector can be verified by using the PPB Read command.

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9.4.4

PPB Lock Bit (PPBL[0])

The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared to ‘0’, it locks all PPBs and when set to

‘1’, it allows the PPBs to be changed.

The PLBWR command is used to clear the PPB Lock bit to ‘0’. The PPB Lock Bit must be cleared to ‘0’ only after

all the PPBs are configured to the desired settings.

In Persistent Protection mode, the PPB Lock is set to ‘1’ during POR or a hardware reset. When cleared to ‘0’, no

software command sequence can set the PPB Lock bit to ‘1’, only another hardware reset or power-up can set

the PPB Lock bit.

In the Password Protection mode, the PPB Lock bit is cleared to ‘0’ during POR or a hardware reset. The PPB Lock

bit can only be set to ‘1’ by the Password Unlock command.

9.4.5

Sector protection states summary

Each sector can be in one of the following protection states:

• Unlocked — The sector is unprotected and protection can be changed by a simple command. The protection

state defaults to unprotected after a power cycle, software reset, or hardware reset.

• Dynamically Locked — A sector is protected and protection can be changed by a simple command. The

protection state is not saved across a power cycle or reset.

• Persistently Locked — A sector is protected and protection can only be changed if the PPB Lock Bit is set to ‘1’.

The protection state is nonvolatile and saved across a power cycle or reset. Changing the protection state

requires programming and or erase of the PPB bits.

Table 34

Sector protection states

Protection bit values

Sector state

PPB lock

PPB

1

DYB

1

0

Unprotected – PPB and DYB are changeable

Protected – PPB and DYB are changeable

1

0

1

Protected – PPB and DYB are changeable

0

Protected – PPB and DYB are changeable

1

Unprotected – PPB not changeable, DYB is changeable

Protected – PPB not changeable, DYB is changeable

1

0

1

0

9.4.6

Persistent Protection mode

The Persistent Protection method sets the PPB Lock bit to ‘1’ during POR or Hardware Reset so that the PPB bits

are unprotected by a device hardware reset. Software reset does not affect the PPB Lock bit. The PLBWR

command can clear the PPB Lock bit to ‘0’ to protect the PPB. There is no command to set the PPB Lock bit

therefore the PPB Lock bit will remain at ‘0’ until the next power-off or hardware reset.

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9.4.7

Password Protection mode

Password Protection mode allows an even higher level of security than the Persistent Sector Protection mode,

by requiring a 64-bit password for unlocking the PPB Lock bit. In addition to this password requirement, after

power up and hardware reset, the PPB Lock bit is cleared to ‘0’ to ensure protection at power-up. Successful

execution of the Password Unlock command by entering the entire password clears the PPB Lock bit, allowing

for sector PPB modifications.

Password protection notes:

• Once the Password is programmed and verified, the Password Mode (ASPR[2] = 0) must be set in order to prevent

reading the password.

• The Password Program Command is only capable of programming ‘0’s. Programming ‘1’ after a cell is

programmed as ‘0’ results in the cell left as ‘0’ with no programming error set.

• The password is all 1’s when shipped from Infineon. It is located in its own memory space and is accessible

through the use of the Password Program and Password Read commands.

• All 64-bit password combinations are valid as a password.

• The Password mode, once programmed, prevents reading the 64-bit password and further password

programming. All further program and read commands to the password region are disabled and these

commands are ignored. There is no means to verify what the password is after the Password Mode Lock Bit is

selected. Password verification is only allowed before selecting the Password Protection mode.

• The Protection Mode Lock Bits are not erasable.

• The exact password must be entered in order for the unlocking function to occur. If the password unlock

command provided password does not match the hidden internal password, the unlock operation fails in the

same manner as a programming operation on a protected sector. The P_ERR bit is set to one and the WIP Bit

remains set. In this case it is a failure to change the state of the PPB Lock bit because it is still protected by the

lack of a valid password.

• The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it

take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an

attempt to correctly match a password. The Read Status Register 1 command may be used to read the WIP bit

to determine when the device has completed the password unlock command or is ready to accept a new

password command. When a valid password is provided the password unlock command does not insert the

100 µs delay before returning the WIP bit to ‘0’.

• If the password is lost after selecting the Password mode, there is no way to set the PPB Lock bit.

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Commands

10

Commands

All communication between the host system and the S79FL01GS memory device is in the form of units called

commands.

All commands begin with an instruction that selects the type of information transfer or device operation to be

performed. Commands may also have an address, instruction modifier, latency period, data transfer to the

memory, or data transfer from the memory. All instruction, address, and data information is transferred serially

between the host system and memory device.

All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.

Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to

the host serially on SO signal.

Quad Output commands provide an address sent to the memory only on the IO0 and IO4 signal. Data will be

returned to the host as a sequence of 8-bit (byte) groups on IO0–IO7.

Quad Input/Output (I/O) commands provide an address sent from the host as four-bit (nibble) groups on Quad

SPI-1 IO0–IO3 and Quad SPI-2 IO4–IO7. Data is returned to the host similarly as 8-bit (byte) groups on IO0–IO7.

Commands are structured as follows:

• Each command begins with an eight bit (byte) instruction.

• The instruction may be stand alone or may be followed by address bits to select a location within one of several

address spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.

• The S79FL01GS Serial Peripheral Interface with multiple IO provides the option for each transfer of address and

data information to be done one, or four bits in parallel. This enables a trade off between the number of signal

connections (IO bus width) and the speed of information transfer. If the host system can support a four-bit wide

IO bus the memory performance can be increased by using the instructions that provide parallel four-bit (quad)

transfers.

• The width of all transfers following the instruction are determined by the instruction sent.

• All single bits or parallel bit groups are transferred in most to least significant bit order.

• Some instructions send instruction modifier (mode) bits following the address to indicate that the next

command will be of the same type with an implied, rather than an explicit, instruction. The next command thus

does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to send

each command when the same command type is repeated in a sequence of commands.

• The address or mode bits may be followed by write data to be stored in the memory device or by a read latency

period before read data is returned to the host.

• Read latency may be zero to several SCK cycles (also referred to as dummy cycles).

• All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted

into the device with the most significant byte first. All data is transferred with the lowest address byte sent first.

Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.

• All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)

are ignored. The embedded operation will continue to execute without any affect. A very limited set of

commands are accepted during an embedded operation. These are discussed in the individual command

descriptions. While a program, erase, or write operation is in progress, it is recommended to check that the

Write-In Progress (WIP) bit is ‘0’ before issuing most commands to the device, to ensure the new command can

be accepted.

• Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

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Commands

• Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces

of the host system and the memory device generally handle the details of signal relationships and timing. For

this reason, signal relationships and timing are not covered in detail within this software interface focused

section of the document. Instead, the focus is on the logical sequence of bits transferred in each command

rather than the signal timing and relationships. Following are some general signal relationship descriptions to

keep in mind. For additional information on the bit level format and signal timing relationships of commands,

see “Command protocol” on page 13.

- The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (IO0 and IO4) for single-bit

wide transfers. The memory drives the IO0–IO7 signals during transfers.

- All commands begin with the host selecting the memory by driving CS# LOW before the first rising edge of

SCK. CS# is kept LOW throughout a command and when CS# is returned HIGH the command ends. Generally,

CS# remains LOW for eight bit transfer multiples to transfer byte granularity information. Some commands

will not be accepted if CS# is returned HIGH not at an 8-bit boundary.

10.1

Command set summary

The S79FL01GS Dual-Quad SPI device contains two Quad SPI devices (Quad SPI-1 and Quad SPI-2)) stacked in a

Dual Die Package (DDP). Both devices are selected to decode each command instruction and address when the

CS# signal, shared by both devices, goes low. Quad SPI-1 device responds to commands, address, data in and

data out on IO0–IO3. Quad SPI-2 device responds to commands, address, data in and data out on IO4–IO7. All

commands are executed by both devices in parallel.

Both Quad SPI devices must be configured, by writing to the various status and configuration registers in parallel,

to define the same overall sector map and behavior of both devices, selected by each CS# for the DDP.

10.1.1

Extended addressing

To accommodate addressing above 256 Mb, there are three options:

1. New instructions are provided with 4-byte address, used to access up to 32 Gb of memory.

Table 35

Instructions and corresponding details

Instruction name

Description

Code (Hex)

4FAST_READ

4READ

4QOR

Read Fast (4-byte Address)

0C

13

6C

EC

EE

12

34

DC

Read (4-byte Address)

Read Quad Out (4-byte Address)

Quad I/O Read (4-byte Address)

DDR Quad I/O Read (4-byte Address)

Page Program (4-byte Address)

Quad Page Program (4-byte Address)

Erase 512 kB (4-byte Address)

4QIOR

4DDRQIOR

4PP

4QPP

4SE

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Commands

2. For backward compatibility to the 3-byte address instructions, the standard instructions can be used in

conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7] is cleared to ‘0’

(following power up and hardware reset), to enable 3-byte (24-bit) addressing. When set to ‘1’, the legacy

commands are changed to require 4 bytes (32 bits) for the address field. The following instructions can be used

in conjunction with EXTADD bit to switch from 3 bytes to 4 bytes of address field.

Table 36

Instructions and corresponding details

Instruction name

Description

Code (Hex)

READ

FAST_READ

QOR

Read (3-byte Address)

Read Fast (3-byte Address)

03

0B

6B

EB

ED

02

32

D8

Read Quad Out (3-byte Address)

Quad I/O Read (3-byte Address)

DDR Quad I/O Read (3-byte Address)

Page Program (3-byte Address)

Quad Page Program (3-byte Address)

Erase 512 kB (3-byte Address)

QIOR

DDRQIOR

PP

QPP

SE

3. For backward compatibility to the 3-byte addressing, the standard instructions can be used in conjunction

with the Bank Address Register:

a. The Bank Address Register is used to switch between 128-Mbit (16-Mbyte) banks of memory, The standard

3-byte address selects an address within the bank selected by the Bank Address Register.

i. The host system writes the Bank Address Register to access beyond the first 128 Mbits of memory.

ii. This applies to read, erase, and program commands.

b. The Bank Register provides the high order (4th) byte of address, which is used to address the available

memory at addresses greater than 16 Mbytes.

c. Bank Register bits are volatile.

i. On power up, the default is Bank 0 (the lowest address 16 Mbytes).

d. For Read, the device will continuously transfer out data until the end of the array.

i. There is no bank to bank delay.

ii. The Bank Address Register is not updated.

iii.The Bank Address Register value is used only for the initial address of an access.

Table 37

Bank address map

Bank address register bits

Bank

Memory array address range (Hex)

Bit 1

Bit 0

0

1

0

1

0

1

0

1

2

3

00000000

01000000

02000000

03000000

00FFFFFF

01FFFFFF

02FFFFFF

03FFFFFF

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Commands

Table 38

S79FL01GS command set (sorted by function)

Maximum

frequency

(MHz)

Command

Instruction

value (Hex)

Function

Command description

name

READ_ID

Read Electronic Manufacturer Signature

(REMS)

90

9F

133

Read ID (JEDEC Manufacturer ID and JEDEC

RDID

Read Device

CFI)

Identification

RES

Read Electronic Signature

Read Serial Flash Discoverable Parameters

Read Status Register 1

Read Status Register 2

Read Configuration Register 1

Write Register (Status 1, Configuration 1)

Write Disable

AB

5A

05

07

35

01

04

06

50

RSFDP

RDSR1

RDSR2

RDCR

WRR

133

WRDI

WREN

Write Enable

Clear Status Register 1 – Erase/Program Fail

Reset

CLSR

30

133

(QUAD = 0)

104

ABRD

AutoBoot Register Read

14

Register Access

(QUAD = 1)

ABWR

BRRD

BRWR

AutoBoot Register Write

Bank Register Read

Bank Register Write

15

16

17

133

Bank Register Access

BRAC

(Legacy Command formerly used for Deep

Power Down)

B9

133

DLPRD

PNVDLR

WVDLR

READ

Data Learning Pattern Read

Program NV Data Learning Register

Write Volatile Data Learning Register

Read (3- or 4-byte address)

Read (4-byte address)

41

43

4A

03

13

0B

0C

6B

6C

EB

EC

ED

EE

133

50

4READ

50

FAST_READ Fast Read (3- or 4-byte address)

4FAST_READ Fast Read (4-byte address)

133

104

80

QOR

4QOR

Read Quad Out (3- or 4-byte address)

Read Quad Out (4-byte address)

Read Flash Array

QIOR

Quad I/O Read (3- or 4-byte address)

Quad I/O Read (4-byte address)

4QIOR

DDRQIOR

DDR Quad I/O Read (3- or 4-byte address)

4DDRQIOR DDR Quad I/O Read (4-byte address)

80

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Commands

Table 38

S79FL01GS command set (sorted by function) (Continued)

Maximum

frequency

(MHz)

Command

Instruction

value (Hex)

Function

Command description

name

PP

Page Program (3- or 4-byte address)

Page Program (4-byte address)

02

12

32

133

80

4PP

QPP

Quad Page Program (3- or 4-byte address)

Quad Page Program - Alternate instruction

(3- or 4-byte address)

Program Flash Array

QPP

38

80

4QPP

PGSP

PGRS

BE

Quad Page Program (4-byte address)

Program Suspend

Program Resume

Bulk Erase

34

85

8A

60

C7

D8

DC

75

7A

42

4B

E0

E1

E2

E3

E4

2B

2F

A7

A6

E7

E8

E9

F0

FF

80

133

BE

Bulk Erase (alternate command)

Erase 512 kB (3- or 4-byte address)

Erase 512 kB (4-byte address)

Erase Suspend

SE

Erase Flash Array

4SE

ERSP

ERRS

OTPP

OTPR

DYBRD

DYBWR

PPBRD

PPBP

PPBE

ASPRD

ASPP

PLBRD

PLBWR

PASSRD

PASSP

PASSU

RESET

MBR

Erase Resume

OTP Program

One Time Program

Array

OTP Read

DYB Read

DYB Write

PPB Read

PPB Program

PPB Erase

ASP Read

Advanced Sector

Protection

ASP Program

PPB Lock Bit Read

PPB Lock Bit Write

Password Read

Password Program

Password Unlock

Software Reset

Reset

Mode Bit Reset

Reserved for Future

Use

Reserved for Multi-I/O-High Performance

Mode (MPM)

MPM

A3

133

RFU

Reserved-18 Reserved

Reserved-E5 Reserved

Reserved-E6 Reserved

18

E5

E6

–

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Commands

10.1.2

Read Device identification

There are multiple commands to read information about the device manufacturer, device type, and device

features. SPI memories from different vendors have used different commands and formats for reading

information about the memories. The S79FL01GS device supports the three most common device information

commands.

10.1.3

Register read or write

There are multiple registers for reporting embedded operation status or controlling device configuration

options. There are commands for reading or writing these registers. Registers contain both volatile and

nonvolatile bits. Nonvolatile bits in registers are automatically erased and programmed as a single (write)

operation.

10.1.3.1

Monitoring operation status

The host system can determine when a write, program, erase, suspend or other embedded operation is complete

by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register 1 command

provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR) bits in the status register

indicate whether the most recent program or erase command has not completed successfully. When P_ERR or

E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy. Under this

condition, only the CLSR, WRDI, RDSR1, RDSR2, and software RESET commands are valid commands. A Clear

Status Register (CLSR) followed by a Write Disable (WRDI) command must be sent to return the device to standby

state. CLSR clears the WIP, P_ERR, and E_ERR bits. WRDI clears the WEL bit. Alternatively, Hardware Reset, or

Software Reset (RESET) may be used to return the device to standby state.

10.1.3.2

Configuration

There are commands to read, write, and protect registers that control interface path width, interface timing,

interface address length, and some aspects of data protection.

10.1.4

Read flash array

Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from

incrementally higher byte addresses until the host ends the data transfer by driving CS# input HIGH. If the byte

address reaches the maximum address of the memory array, the read will continue at address zero of the array.

There are several different read commands to specify different access latency and data path widths. Double Data

Rate (DDR) commands also define the address and data bit relationship to both SCK edges:

• The Read command provides a single address bit per SCK rising edge on the IO0 and IO4 signal with read data

returning a single bit per SCK falling edge on the IO1 and IO5 signal. This command has zero latency between

the address and the returning data but is limited to a maximum SCK rate of 50 MHz.

• Other read commands have a latency period between the address and returning data but can operate at higher

SCK frequencies. The latency depends on the Configuration Register latency code.

• The Fast Read command provides a single address bit per SCK rising edge on the IO0 and IO4 signal with read

data returning a single bit per SCK falling edge on the IO1 and IO5 signal and may operate up to 133 MHz.

• Quad Output read commands provide address a single bit per SCK rising edge on the IO0 and IO4 signal with

read data returning four bits of data per SCK falling edge on the IO0–IO7 signals.

• Quad I/O Read commands provide address four bits per SCK rising edge with read data returning four bits of

data per SCK falling edge on the IO0–IO7 signals.

• Quad Double Data Rate read commands provide address four bits per every SCK edge with read data returning

eight bits of data per every SCK edge on the IO0–IO7 signals. Double Data Rate (DDR) operation is only supported

for core and I/O voltages of 3 V to 3.6 V.

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Commands

10.1.5

Program flash array

Programming data requires two commands: Write Enable (WREN), and Page Program (PP or QPP). The Page

Program command accepts from 1 byte up to 512 consecutive bytes of data (page) to be programmed in one

operation. Programming means that bits can either be left at ‘1’, or programmed from ‘1’ to ‘0’. Changing bits

from ‘0’ to ‘1’ requires an erase operation.

10.1.6

Erase flash array

The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to ‘1’.

A bit needs to be first erased to ‘1’ before programming can change it to ‘0’. While bits can be individually

programmed from ‘1’ to ‘0’, erasing bits from ‘0’ to ‘1’ must be done on a sector-wide (SE) or array-wide (BE) level.

10.1.7

OTP, block protection, and advanced sector protection

There are commands to read and program a separate one time programmable (OTP) array for permanent data

such as a serial number. There are commands to control a contiguous group (block) of flash memory array sectors

that are protected from program and erase operations. There are commands to control which individual flash

memory array sectors are protected from program and erase operations.

10.1.8

Reset

There is a command to reset to the default conditions present after power on to the device. There is a command

to reset (exit from) the Enhanced Performance Read modes.

10.1.9

Reserved

Some instructions are reserved for future use. In this generation of the S79FL01GS some of these command

instructions may be unused and not affect device operation, some may have undefined results.

Some commands are reserved to ensure that a legacy or alternate source device command is allowed without

affect. This allows legacy software to issue some commands that are not relevant for the current generation

S79FL01GS device with the assurance these commands do not cause some unexpected action.

Some commands are reserved for use in special versions of the FL-S not addressed by this document or for a

future generation. This allows new host memory controller designs to plan the flexibility to issue these command

instructions. The command format is defined if known at the time this document revision is published.

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Commands

10.2

Identification commands

10.2.1

Read Identification — REMS (Read_ID or REMS 90h)

The READ_ID command identifies the Device Manufacturer ID and the Device ID. The command is also referred to

as Read Electronic Manufacturer and device Signature (REMS). READ-ID (REMS) is only supported for backward

compatibility and should not be used for new software designs. New software designs should instead make use

of the RDID command.

The command is initiated by shifting on SI the instruction code “90h” followed by a 24-bit address of 00000h.

Following this, the Manufacturer ID and the Device ID are shifted out on SO starting at the falling edge of SCK after

address. The Manufacturer ID and the Device ID are always shifted out with the MSB first. If the 24-bit address is

set to 000001h, then the Device ID is read out first followed by the Manufacturer ID. The Manufacturer ID and

Device ID output data toggles between address 000000H and 000001H until terminated by a low to high transition

on CS# input. The maximum clock frequency for the READ_ID command is 133 MHz.

For the Dual-Quad SPI device the Read Identification (REMS) instruction and data read is only done on Quad SPI-1

using IO0 and IO1.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Manufacture ID

Device ID

Figure 31

Table 39

READ_ID (90h) command sequence

Read_ID values

Device

Manufacturer ID (Hex)

Device ID (Hex)

S79FL01GS

01

21

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Commands

10.2.2

Read Identification (RDID 9Fh)

The Read Identification (RDID) command provides read access to manufacturer identification, device

identification, and common flash interface (CFI) information. The manufacturer identification is assigned by

JEDEC. The CFI structure is defined by JEDEC standard. The device identification and CFI values are assigned by

Infineon.

The JEDEC common flash interface (CFI) specification defines a device information structure, which allows a

vendor-specified software flash management program (driver) to be used for entire families of flash devices.

Software support can then be device-independent, JEDEC manufacturer ID independent, forward and

backward-compatible for the specified flash device families. System vendors can standardize their flash drivers

for long-term software compatibility by using the CFI values to configure a family driver from the CFI information

of the device in use.

Any RDID command issued while a program, erase, or write cycle is in progress is ignored and has no effect on

execution of the program, erase, or write cycle that is in progress.

The RDID instruction is shifted on SI. After the last bit of the RDID instruction is shifted into the device, a byte of

manufacturer identification, two bytes of device identification, extended device identification, and CFI

information will be shifted sequentially out on SO. As a whole this information is referred to as ID-CFI. See “ID-CFI

address space” on page 38 for the detail description of the ID-CFI contents.

Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data. The

RDID command sequence is terminated by driving CS# to the logic HIGH state anytime during data output.

For the S79FL01GS Dual-Quad SPI device, the Read Identification (RDID) instruction and data read is only done

on Quad SPI-1 using IO0 and IO1. The maximum clock frequency for the RDID command is 133 MHz.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Data 1

Data N

Figure 32

Read Identification (RDID 9Fh) command sequence

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Commands

10.2.3

Read Electronic Signature (RES) (ABh)

The RES command is used to read a single byte Electronic Signature from SO. RES is only supported for backward

compatibility and should not be used for new software designs. New software designs should instead make use

of the RDID command.

The RES instruction is shifted in followed by three dummy bytes onto SI. After the last bit of the three dummy

bytes are shifted into the device, a byte of Electronic Signature will be shifted out of SO. Each bit is shifted out by

the falling edge of SCK. The maximum clock frequency for the RES command is 50 MHz.

The Electronic Signature can be read repeatedly by applying multiples of eight clock cycles.

The RES command sequence is terminated by driving CS# to the logic HIGH state anytime during data output.

For the S79FL01GS Dual-Quad SPI device, the Read Electronic Signature (RES) instruction and data read is only

done on Quad SPI-1 using IO0 and IO1.

CS#

SCK

IO0

IO1

7 6 5 4 3 2 1 0 23

Instruction (ABh)

1 0

7 6 5 4 3 2 1 0

Device ID

Phase

Dummy

Figure 33

Table 40

Read Electronic Signature (RES ABh) command sequence

RES values

Device

Device ID (Hex)

S79FL01GS

21

10.2.4

Read serial flash discoverable parameters (RSFDP 5Ah)

The command is initiated by shifting on SI the instruction code ‘5Ah’, followed by a 24-bit address of 000000h,

followed by eight dummy cycles. The SFDP bytes are then shifted out on SO starting at the falling edge of SCK

after the eight dummy cycles. The SFDP bytes are always shifted out with the MSB first. If the 24-bit address is set

to any other value, the selected location in the SFDP space is the starting point of the data read. This enables

random access to any parameter in the SFDP space. The maximum clock frequency for the RSFDP command is

133 MHz.

For the S79FL01GS Dual-Quad device the Read Serial Flash Discoverable Parameters (RSFDP) instruction and

data read is only done on Quad SPI-1 using IO0 and IO1.

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 23

1 0

Address

7 6 5 4

3

2 1 0

Instruction

Dummy Cycles

Data 1

Figure 34

RSFDP command sequence

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Commands

10.3

Register Access commands

10.3.1

Read Status Register 1 (RDSR1 05h)

The Read Status Register 1 (RDSR1) command allows the Status Register 1 contents of Quad SPI-1 to be read from

IO1 and Quad SPI-2 to be read from IO5. The Status Register 1 contents may be read at any time, even while a

program, erase, or write operation is in progress. It is possible to read the Status Register 1 continuously by

providing multiples of eight clock cycles. The status is updated for each eight cycle read. The maximum clock

frequency for the RDSR1 (05h) command is 133 MHz.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO2-IO3

IO4

IO5

IO6-IO7

Phase

Instruction

Status

Updated Status

Figure 35

Dual-Quad Read Status Register 1 (RDSR1 05h) command sequence

10.3.2

Read Status Register 2 (RDSR2 07h)

The Read Status Register 2 (RDSR2) command allows the Status Register 2 contents of Quad SPI-1 to be read from

IO1 and Quad SPI-2 to be read from IO5. The Status Register 2 contents may be read at any time, even while a

program, erase, or write operation is in progress. It is possible to read the Status Register 2 continuously by

providing multiples of eight clock cycles. The status is updated for each eight cycle read. The maximum clock

frequency for the RDSR2 command is 133 MHz.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO2-IO3

IO4

IO5

IO6-IO7

Phase

Instruction

Status

Updated Status

Figure 36

Dual-Quad Read Status Register 2 (RDSR2 07h) command sequence

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Commands

10.3.3

Read Configuration Register (RDCR 35h)

The Read Configuration Register (RDCR) command allows the Configuration Register contents of Quad SPI-1 to

be read from IO1 and Quad SPI-2 to be read from IO5. It is possible to read the Configuration Register continuously

by providing multiples of eight clock cycles. The Configuration Register contents may be read at any time, even

while a program, erase, or write operation is in progress.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO2-IO3

IO4

IO5

IO6-IO7

Phase

Instruction

Register Read

Repeat Register Read

Figure 37

Dual-Quad Read Configuration Register (RDCR 35h) command sequence

10.3.4

Bank Register Read (BRRD 16h)

The Read the Bank Register (BRRD) command allows the Bank address Register contents to be read from SO. The

instruction is first shifted in from SI. Then the 8-bit Bank Register is shifted out on SO. It is possible to read the

Bank Register continuously by providing multiples of eight clock cycles. The maximum operating clock frequency

for the BRRD command is 133 MHz.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO4

IO5

Phase

Instruction

Register Read

Repeat Register Read

Figure 38

Read Bank Register (BRRD 16h) command

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Commands

10.3.5

Bank Register Write (BRWR 17h)

The Bank Register Write (BRWR) command is used to write address bits above A23, into the Bank Address Register

(BAR). The command is also used to write the Extended address control bit (EXTADD) that is also in BAR[7]. BAR

provides the high order addresses needed by devices having more than 128 Mbits (16 Mbytes), when using 3-byte

address commands without extended addressing enabled (BAR[7] EXTADD = 0). Because this command is part of

the addressing method and is not changing data in the flash memory, this command does not require the WREN

command to precede it.

The BRWR instruction is entered, followed by the data byte on SI. The Bank Register is one data byte in length.

The BRWR command has no effect on the P_ERR, E_ERR or WIP bits of the Status and Configuration Registers.

Any bank address bit reserved for the future should always be written as ‘0’.

CS#

SCK

SI_IO0

SO_IO1-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Input Data

Figure 39

Bank Register Write (BRWR 17h) command

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Commands

10.3.6

Bank Register Access (BRAC B9h)

The Bank Register Read and Write commands provide full access to the Bank Address Register (BAR) but they are

both commands that are not present in legacy SPI memory devices. Host system SPI memory controller

interfaces may not be able to easily support such new commands. The Bank Register Access (BRAC) command

uses the same command code and format as the Deep Power Down (DPD) command that is available in legacy

SPI memories. The FL-S family does not support a DPD feature but assigns this legacy command code to the BRAC

command to enable write access to the Bank Address Register for legacy systems that are able to send the legacy

DPD (B9h) command.

When the BRAC command is sent, the S79FL-S family device will then interpret an immediately following Write

Register (WRR) command as a write to the lower address bits of the BAR. A WREN command is not used between

the BRAC and WRR commands. Only the lower two bits of the first data byte following the WRR command code

are used to load BAR[1:0]. The upper bits of that byte and the content of the optional WRR command second data

byte are ignored. Following the WRR command the access to BAR is closed and the device interface returns to the

standby state. The combined BRAC followed by WRR command sequence has no affect on the value of the ExtAdd

bit (BAR[7]).

Commands other than WRR may immediately follow BRAC and execute normally. However, any command other

than WRR, or any other sequence in which CS# goes low and returns high, following a BRAC command, will close

the access to BAR and return to the normal interpretation of a WRR command as a write to Status Register 1 and

the Configuration Register.

The BRAC + WRR sequence is allowed only when the device is in standby, program suspend, or erase suspend

states. This command sequence is illegal when the device is performing an embedded algorithm or when the

program (P_ERR) or erase (E_ERR) status bits are set to ‘1’.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 40

BRAC (B9h) command sequence

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Commands

10.3.7

Write Registers (WRR 01h)

The Write Registers (WRR) command allows new values to be written to both the Status Register 1 and

Configuration Register. Before the Write Registers (WRR) command can be accepted by the device, a Write Enable

(WREN) command must be received. After the Write Enable (WREN) command has been decoded successfully,

the device will set the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The Write Registers (WRR) command is entered by shifting the instruction and the data bytes for Quad SPI-1 on

IO0 and for Quad SPI-2 on IO4. The Status Register is one data byte in length.

The Write Registers (WRR) command will set the P_ERR or E_ERR bits if there is a failure in the WRR operation.

Any Status or Configuration Register bit reserved for the future must be written as ‘0’.

CS# must be driven to the logic HIGH state after the eighth or sixteenth bit of data has been latched. If not, the

Write Registers (WRR) command is not executed. If CS# is driven HIGH after the eighth cycle then only the Status

Register 1 is written; otherwise, after the sixteenth cycle both the Status and Configuration Registers are written.

When the configuration register QUAD bit CR[1] is ‘1’, only the WRR command format with 16 data bits may be

used.

As soon as CS# is driven to the logic HIGH state, the self-timed Write Registers (WRR) operation is initiated. While

the Write Registers (WRR) operation is in progress, the Status Register may still be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is ‘1’ during the self-timed Write Registers (WRR)

operation, and is ‘0’ when it is completed. When the Write Registers (WRR) operation is completed, the Write

Enable Latch (WEL) is set to ‘0’. The maximum clock frequency for the WRR command is 133 MHz.

CS#

SCK

IO0

SO_IO1-IO3

IO4

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

IO5-IO7

Phase

Input Status Register-1

Instruction

Figure 41

Dual-Quad Write Registers

CS#

SCK

IO0

SO_IO1-IO3

IO4

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

IO5-IO7

Phase

Input Status Register-1 Input Conf Register-1

Instruction

Figure 42

Dual-Quad Write Registers (WRR 01h) command sequence

The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and

BP0) bits to define the size of the area that is to be treated as read-only. The Write Registers (WRR) command also

allows the user to set the Status Register Write Disable (SRWD) bit to ‘1’ or ‘0’. The Status Register Write Disable

(SRWD) bit allows the BP bits to be hardware protected.

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Commands

When the Status Register Write Disable (SRWD) bit of the Status Register is ‘0’ (its initial delivery state), it is

possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by

a Write Enable (WREN) command.

The WRR command has an alternate function of loading the Bank Address Register if the command immediately

follows a BRAC command. See “Bank Register Access (BRAC B9h)” on page 72.

10.3.8

Write Enable (WREN 06h)

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1[1]) to ‘1’.

The Write Enable Latch (WEL) bit must be set to ‘1’ by issuing the Write Enable (WREN) command to enable write,

program and erase commands.

CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on IO0

for Quad SPI-1 and IO4 for Quad SPI-2. Without CS# being driven to the logic HIGH state after the eighth bit of the

instruction byte has been latched in on IO0 for Quad SPI-1 and IO4 for Quad SPI-2, the write enable operation will

not be executed.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 43

Dual-Quad Write Enable (WREN 06h) command sequence

10.3.9

Write Disable (WRDI 04h)

The Write Disable (WRDI) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1[1]) to ‘0’.

The Write Enable Latch (WEL) bit may be set to ‘0’ by issuing the Write Disable (WRDI) command to disable Page

Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR), OTP Program (OTPP), and other

commands, that require WEL be set to ‘1’ for execution. The WRDI command can be used by the user to protect

memory areas against inadvertent writes that can possibly corrupt the contents of the memory. The WRDI

command is ignored during an embedded operation while WIP bit = 1.

CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on IO0

for Quad SPI-1 and IO4 for Quad SPI-2. Without CS# being driven to the logic HIGH state after the eighth bit of the

instruction byte has been latched in on IO0 for Quad SPI-1 and IO4 for Quad SPI-2, the write disable operation will

not be executed.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 44

Dual-Quad Write Disable (WRDI 04h) command sequence

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10.3.10

Clear Status Register (CLSR 30h)

The Clear Status Register command resets bit SR1[5] (Erase Fail Flag) and bit SR1[6] (Program Fail Flag). It is not

necessary to set the WEL bit before the Clear SR command is executed. The Clear SR command will be accepted

even when the device remains busy with WIP set to ‘1’, as the device does remain busy when either error bit is

set. The WEL bit will be unchanged after this command is executed.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 45

Dual-Quad Clear Status Register (CLSR 30h) command sequence

10.3.11

ECC Status Register Read (ECCRD 18h)

To read the ECC Status Register, the command is followed by the ECC unit (32 bit) address, the four least

significant bits (LSB) of address must be set to zero. This is followed by eight dummy cycles. Then the 8-bit

contents of the ECC Register, for the ECC unit selected, are shifted out on SO 16 times, once for each byte in the

ECC Unit. If CS# remains low the next ECC unit status is sent through SO 16 times, once for each byte in the ECC

Unit, this continues until CS# goes high. The maximum operating clock frequency for the ECC READ command is

133 MHz. See “Automatic ECC” on page 89 for details on ECC unit.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

31

1

0

7

6

5

4

3

2

1

0

IO2-IO3

IO4

IO5

IO6-IO7

Phase

Instruction

Address

Dummy Cycles

Data Out

Figure 46

ECC Status Register Read command sequence

Note

44.Data Out for Quad SPI-1 is IO1, Quad SPI-2 is IO5.

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10.3.12

AutoBoot

SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command. And,

in order to read boot code from an SPI device, the host memory controller or processor must supply the read

command from a hardwired state machine or from some host processor internal ROM code.

Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time to

start reading boot code.

The AutoBoot feature allows the host memory controller to take boot code from a S79FL01GS device immediately

after the end of reset, without having to send a read command. This saves 32 or more cycles and simplifies the

logic needed to initiate the reading of boot code.

• As part of the power up reset, hardware reset, or command reset process the AutoBoot feature automatically

starts a read access from a pre-specified address. At the time the reset process is completed, the device is ready

to deliver code from the starting address. The host memory controller only needs to drive CS# signal from HIGH

to LOW and begin toggling the SCK signal. The S79FL01GS device will delay code output for a pre-specified

number of clock cycles before code streams out.

- The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is needed by

the host.

- The host cannot send commands during this time.

- If ABSD = 0, the maximum SCK frequency is 50 MHz.

- If ABSD > 0, the maximum SCK frequency is 133 MHz if the QUAD bit CR1[1] is ‘0’ or 104 MHz if the QUAD bit is ‘1’.

• The starting address of the boot code is selected by the value programmed into the AutoBoot Start Address

(ABSA) field of the AutoBoot Register which specifies a 512 byte boundary aligned location; the default address

is 00000000h.

- Data will continuously shift out until CS# returns HIGH.

• At any point after the first data byte is transferred, when CS# returns HIGH, the SPI device will reset to standard

SPI mode; able to accept normal command operations.

- A minimum of one byte must be transferred.

- AutoBoot mode will not initiate again until another power cycle or a reset occurs.

• An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.

The AutoBoot register bits are nonvolatile and provide:

• The starting address (512-byte boundary), set by the AutoBoot Start Address (ABSA). The size of the ABSA field

is 23 bits for devices up to 32-Gbit.

• The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 8-bit count value.

• The AutoBoot Enable.

With the configuration register QUAD bit CR1[1] is set to ‘1’, the boot code will be provided 4 bits per cycle in the

same manner as a Read Quad Out command.

CS#

SCK

IO0

IO1

0

1

2

3

4

5

6

7

0 4

1 5

2 6

3 7

4 0 4 0

5 1 5 1

6 2 6 2

7 3 7 3

IO2

IO3

IO4

4 0 4 0 4 0 4 0

5 1 5 1 5 1 5 1

6 2 6 2 6 2 6 2

7 3 7 3 7 3 7 3

IO5

IO6

IO7

Phase

D1 D2 D3 D4 D5 D6 D7

...

Wait States (ABSD)

Figure 47

AutoBoot sequence (CR1[1] = 1)

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.3.13

AutoBoot Register Read (ABRD 14h)

The AutoBoot Register Read command is shifted into SI. Then the 32-bit AutoBoot Register is shifted out on SO,

least significant byte first, most significant bit of each byte first. It is possible to read the AutoBoot Register

continuously by providing multiples of 32 clock cycles. The maximum operating clock frequency for ABRD

command is 104 MHz.

CS#

SCK

SI_IO0

7

6

5

4

3

2

1

0

SO_IO1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO4

IO5

Phase

Instruction

Data 1

Data N

Figure 48

AutoBoot Register Read (ABRD 14h) command

10.3.14

AutoBoot Register Write (ABWR 15h)

Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and decoded by

the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The ABWR command is entered by shifting the instruction and the data bytes on SI, least significant byte first,

most significant bit of each byte first. The ABWR data is 32 bits in length.

The ABWR command has status reported in Status Register 1 as both an erase and a programming operation. An

E_ERR or a P_ERR may be set depending on whether the erase or programming phase of updating the register

fails.

CS# must be driven to the logic HIGH state after the 32nd bit of data has been latched. If not, the ABWR command

is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed ABWR operation is initiated. While

the ABWR operation is in progress, Status Register 1 may be read to check the value of the Write-In Progress (WIP)

bit. The Write-In Progress (WIP) bit is ‘1’ during the self-timed ABWR operation, and is ‘0’ when it is completed.

When the ABWR cycle is completed, the Write Enable Latch (WEL) is set to ‘0’. The maximum clock frequency for

the ABWR command is 133 MHz.

CS#

SCK

SI_IO0

SO_IO1-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Input Data 1

Figure 49

AutoBoot Register Write (ABWR) command

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.3.15

Program NVDLR (PNVDLR 43h)

Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN) command

must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded

successfully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.

The PNVDLR command is entered by shifting the instruction and the data byte on SI-IO0 for Quad SPI-1 and IO4

for Quad SPI-2.

CS# must be driven to the logic HIGH state after the eighth (8th) bit of data has been latched. If not, the PNVDLR

command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PNVDLR operation is

initiated. While the PNVDLR operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is ‘1’ during the self-timed PNVDLR cycle, and is a ‘0’

when it is completed. The PNVDLR operation can report a program error in the P_ERR bit of the status register.

When the PNVDLR operation is completed, the Write Enable Latch (WEL) is set to ‘0’. The maximum clock

frequency for the PNVDLR command is 133 MHz.

CS#

SCK

SI_IO0

SO_IO1-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Input Data

Figure 50

Program NVDLR (PNVDLR 43h) command sequence

10.3.16

Write VDLR (WVDLR 4Ah)

Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must

be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully,

the device will set the Write Enable Latch (WEL) to enable WVDLR operation.

The WVDLR command is entered by shifting the instruction and the data byte on SI-IO0 for Quad SPI-1 and IO4

for Quad SPI-2.

CS# must be driven to the logic HIGH state after the eighth (8th) bit of data has been latched. If not, the WVDLR

command is not executed. As soon as CS# is driven to the logic HIGH state, the WVDLR operation is initiated with

no delays. The maximum clock frequency for the PNVDLR command is 133 MHz.

CS#

SCK

SI_IO0

SO_IO1-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Input Data

Figure 51

Write VDLR (WVDLR 4Ah) command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.3.17

Data Learning Pattern Read (DLPRD 41h)

The instruction is shifted on SI_IO0, then the 8-bit DLP is shifted out on SO_IO1 and IO5. It is possible to read the

DLP continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the

DLPRD command is 133 MHz.

CS#

SCK

SI_IO0

7

6

5

4

3

2

1

0

SO_IO1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO4

IO5

Phase

Instruction

Data 1

Data N

Figure 52

Dual-Quad DLP Read (DLPRD 41h) command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.4

Read Memory Array commands

Read commands for the main flash array provide many options for prior generation SPI compatibility or

enhanced performance SPI:

• Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate

commands (SDR).

• Some SDR commands transfer address one bit per rising edge of SCK and return data 2, or 8 bits of data per

rising edge of SCK. These are called Read or Fast Read for 2-bit data; Quad Output for 8-bit data.

• Some SDR commands transfer both address and data 8 bits per rising edge of SCK. These are called Quad I/O

for 8 bit.

• Some commands transfer address and data on both the rising edge and falling edge of SCK. These are called

Double Data Rate (DDR) commands.

• There are DDR commands for 1, or 4 bits of address per each die or 8 bit data per SCK edge. These are called

Fast DDR for 1-bit, and Quad I/O DDR for 8-bit per edge transfer.

All of these commands begin with an instruction code that is transferred one bit per SCK rising edge. The

instruction is followed by either a 3- or 4-byte address transferred at SDR or DDR. Commands transferring address

or data 4-bits per clock edge per die are called Multiple I/O (MIO) commands. For FL-S devices at 256 Mbits or

higher density, the traditional SPI 3-byte addresses are unable to directly address all locations in the memory

array. These device have a bank address register that is used with 3-byte address commands to supply the high

order address bits beyond the address from the host system. The default bank address is ‘0’. Commands are

provided to load and read the bank address register. These devices may also be configured to take a 4-byte

address from the host system with the traditional 3-byte address commands. The 4-byte address mode for

traditional commands is activated by setting the External Address (EXTADD) bit in the bank address register to ‘1’.

The Quad I/O commands provide a performance improvement option controlled by mode bits that are sent

following the address bits. The mode bits indicate whether the command following the end of the current read

will be another read of the same type, without an instruction at the beginning of the read. These mode bits give

the option to eliminate the instruction cycles when doing a series of Quad I/O read accesses.

Some commands require delay cycles following the address or mode bits to allow time to access the memory

array. The delay cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory thus

any data provided by the host during these cycles is ‘don’t care’ and the host may also leave the SI signal at high

impedance during the dummy cycles. When MIO commands are used the host must stop driving the IO signals

(outputs are high impedance) before the end of last dummy cycle. When DDR commands are used the host must

not drive the I/O signals during any dummy cycle. The number of dummy cycles varies with the SCK frequency or

performance option selected via the Configuration Register 1 (CR1) Latency Code (LC). Dummy cycles are

measured from SCK falling edge to next SCK falling edge. SPI outputs are traditionally driven to a new value on

the falling edge of each SCK. Zero dummy cycles means the returning data is driven by the memory on the same

falling edge of SCK that the host stops driving address or mode bits.

The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on all

data outputs, in the dummy cycles immediately before the start of data. The DLP can help the host memory

controller determine the phase shift from SCK to data edges so that the memory controller can capture data at

the center of the data eye.

When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides one or more dummy

cycles should be selected to allow additional time for the host to stop driving before the memory starts driving

data, to minimize I/O driver conflict. When using DDR I/O commands with the DLP enabled, an LC that provides

five or more dummy cycles should be selected to allow one cycle of additional time for the host to stop driving

before the memory starts driving the 4 cycle DLP.

Each read command ends when CS# is returned HIGH at any point during data return. CS# must not be returned

HIGH during the mode or dummy cycles before data returns as this may cause mode bits to be captured

incorrectly; making it indeterminate as to whether the device remains in enhanced high performance read mode.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.4.1

Read (Read 03h or 4READ 13h)

The instruction

• 03h (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 03h (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 13h is followed by a 4-byte address (A31–A0)

Then the memory contents, at the address given, are shifted out on IO1 and IO5. The maximum operating clock

frequency for the READ command is 50 MHz.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

A

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO2-IO3

IO4

IO5

IO6-IO7

Phase

Instruction

Address

Data 1

Data N

Figure 53

Dual-Quad Read command sequence (READ 03h or 13h)

Note

45.A = MSB of address = 23 for command 03h, or 31 for command 13h.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.4.2

Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)

The instruction

• 0Bh (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 0Bh (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 0Ch is followed by a 4-byte address (A31–A0)

The address is followed by zero or eight dummy cycles depending on the latency code set in the Configuration

Register. The dummy cycles allow the device internal circuits additional time for accessing the initial address

location. During the dummy cycles the data value on IO1 and IO5 is ‘don’t care’ and may be high impedance. Then

the memory contents, at the address given, are shifted out on IO1 and IO5.

The maximum operating clock frequency for FAST READ command is 133 MHz.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

31

1

0

3

7

2

6

1

5

0

4

3

7

2

6

1

5

0

4

IO2-IO3

IO4

IO5

IO6-IO7

Phase

Instruction

Address

Dummy Cycles

Data 1

Data 2

Figure 54

Dual-Quad SPI Fast Read (FAST_READ) command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.4.3

Quad Output Read (QOR 6Bh or 4QOR 6Ch)

The instruction

• 6Bh (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 6Bh (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 6Ch is followed by a 4-byte address (A31–A0)

Then the memory contents, at the address given, is shifted out eight bits at a time through IO0–IO7. Each nibble

(4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.

The maximum operating clock frequency for Quad Output Read command is 104 MHz. For Quad Output Read

Mode, there may be dummy cycles required after the last address bit is shifted into SI before data begins shifting

out of IO0–IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to set

up for the initial address. During the dummy cycles, the data value on IO0–IO7 is ‘don’t care’ and may be high

impedance. The number of dummy cycles is determined by the frequency of SCK (refer to Table 19).

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

A

1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

IO2

IO3

IO4

IO5

IO6

IO7

Phase

Instruction

Address

Dummy

D1 D2 D3 D4 D5

Figure 55

Dual-Quad, Quad Output Read (QOR 6Bh or 4QOR 6Ch) command sequence

Note

46.A = MSB of address = 23 for command 6Bh, or 31 for command 6Ch.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.4.4

Quad I/O Read (QIOR EBh or 4QIOR ECh)

The instruction

• EBh (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• EBh (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• ECh is followed by a 4-byte address (A31–A0)

The Quad I/O Read command improves throughput with eight I/O signals — IO0–IO7. It is similar to the Quad

Output Read command but allows input of the address bits eight bits per serial SCK clock. In some applications,

the reduced instruction overhead might allow for code execution (XIP) directly from the S79FL01GS device.

The maximum operating clock frequency for Quad I/O Read is 104 MHz.

For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data

begins shifting out of IO0–IO7. This latency period (i.e., dummy cycles) allows the device’s internal circuitry

enough time to access data at the initial address. During latency cycles, the data value on IO0–IO7 are ‘don’t care’

and may be high impedance. The number of dummy cycles is determined by the frequency of SCK and the latency

code table (refer to Table 19). The number of dummy cycles is set by the LC bits in the Configuration Register

(CR1). However, both latency code tables use the same latency values for the Quad I/O Read command.

Following the latency period, the memory contents at the address given, is shifted out eight bits at a time through

IO0–IO7. Each byte (8 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through

the setting of the Mode bits (after the address sequence, as shown in Figure 56 or Figure 57). This added feature

removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits

7–4) of the Mode bits control the length of the next Quad I/O instruction through the inclusion or exclusion of the

first byte instruction code. The lower nibble (bits 3–0) of the Mode bits are ‘don’t care’ (x). If the Mode bits equal

Axh, then the device remains in Quad I/O High Performance Read Mode and the next address can be entered (after

CS# is raised high and then asserted low) without requiring the EBh or ECh instruction, as shown in Figure 56;

thus, eliminating eight cycles for the command sequence. The following sequences will release the device from

Quad I/O High Performance Read mode; after which, the device can accept standard SPI commands:

1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh, then the next

time CS# is raised HIGH the device will be released from Quad I/O High Performance Read mode.

During any operation, if CS# toggles HIGH to LOW to high for eight cycles (or less) and data input (IO0–IO3) are

not set for a valid instruction sequence, then the device will be released from Quad I/O High Performance Read

mode. Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s

internal circuitry latency time to access the initial address after the last address cycle that is clocked into IO0–IO3.

It is important that the IO0–IO7 signals be set to high-impedance at or before the falling edge of the first data out

clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins to

drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0–IO7 signal contention,

for the host system to turn off the IO0–IO7 signal outputs (make them high impedance) during the last ‘don’t care’

mode cycle or during any dummy cycles.

CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

A-3

A-2

A-1

A

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

IO2

IO3

IO4

A-3

A-2

A-1

A

IO5

IO6

IO7

Phase

Instruction

Address

Mode

Dummy

D1 D2 D3 D4

Figure 56

Dual-Quad I/O Read command sequence (3-Byte Address, EBh [ExtAdd = 0], LC = 00b)

CS#

SCK

IO0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

A-3

A-2

A-1

A

4

0

1

2

3

0

1

2

3

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

IO1

5

IO2

6

IO3

7

IO4

A-3

A-2

A-1

A

4

IO5

5

IO6

6

7

IO7

Phase

DN-1 DN

Address

Mode

Dummy

D1 D2 D3 D4

Figure 57

Dual-Quad Continuous Quad I/O Read command sequence (3-Byte Address), LC = 00b

Note

47.A = MSB of address = 23 for command EBh, or 31 for command ECh.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.4.5

DDR Quad I/O Read (EDh, EEh)

The Read DDR Quad I/O command is similar to the Quad I/O Read command but allows input of the address four

bits on every edge of the clock. In some applications, the reduced instruction overhead might allow for code

execution (XIP) directly from the S79FL01GS device. The QUAD bit of the Configuration Register is set (CR[1] = 1)

to enable the Quad capability in the S79FL01GS device.

The instruction

• EDh (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• EDh (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• EEh is followed by a 4-byte address (A31–A0)

The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR

fashion, with four bits at a time on each clock edge through IO0–IO7.

The maximum operating clock frequency for Read DDR Quad I/O command is 80 MHz.

For Read DDR Quad I/O, there is a latency required after the last address and mode bits are shifted into the

IO0–IO7 signals before data begins shifting out of IO0–IO7. This latency period (dummy cycles) allows the device’s

internal circuitry enough time to access the initial address. During these latency cycles, the data value on

IO0–IO7 are ‘don’t care’ and may be high impedance. When the Data Learning Pattern (DLP) is enabled the host

system must not drive the IO signals during the dummy cycles. The IO signals must be left high impedance by the

host so that the memory device can drive the DLP during the dummy cycles.

The number of dummy cycles is determined by the frequency of SCK. The number of dummy cycles is set by the

LC bits in the Configuration Register (CR1).

Both latency tables provide cycles for mode bits so a series of Quad I/O DDR commands may eliminate the 8-bit

instruction after the first command sends a complementary mode bit pattern, as shown in Figure 58. This feature

removes the need for the eight bit SDR instruction sequence and dramatically reduces initial access times

(improves XIP performance). The Mode bits control the length of the next Read DDR Quad I/O operation through

the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0])

of the Mode bits are complementary (i.e. 5h and Ah) the device transitions to Continuous Read DDR Quad I/O

Mode and the next address can be entered (after CS# is raised HIGH and then asserted LOW) without requiring

the EDh or EEh instruction, as shown in Figure 59 thus, eliminating eight cycles from the command sequence.

The following sequences will release the device from Continuous Read DDR Quad I/O mode; after which, the

device can accept standard SPI commands:

1. During the Read DDR Quad I/O Command Sequence, if the Mode bits are not complementary the next time CS#

is raised HIGH and then asserted LOW the device will be released from Read DDR Quad I/O mode.

2. During any operation, if CS# toggles HIGH to LOW to HIGH for eight cycles (or less) and data input (IO0–IO7) are

not set for a valid instruction sequence, then the device will be released from Read DDR Quad I/O mode.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate. The

HOLD function is not valid during Quad I/O DDR commands.

Note that the memory devices drive the IOs with a preamble prior to the first data value. The preamble is a pattern

that is used by the host controller to optimize data capture at higher frequencies. The preamble drives the IO bus

for the four clock cycles immediately before data is output. The host must be sure to stop driving the IO bus prior

to the time that the memory starts outputting the preamble.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

The preamble is intended to give the host controller an indication about the round trip time from when the host

drives a clock edge to when the corresponding data value returns from the memory device. The host controller

will skew the data capture point during the preamble period to optimize timing margins and then use the same

skew time to capture the data during the rest of the read operation. The optimized capture point will be

determined during the preamble period of every read operation. This optimization strategy is intended to

compensate for both the PVT (process, voltage, temperature) of both the memory device and the host controller

as well as any system level delays caused by flight time on the PCB.

Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of

34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all eight IOs). This pattern was

chosen to cover both DC and AC data transition scenarios. The two DC transition scenarios include data low for

a long period of time (two half clocks) followed by a high going transition (001) and the complementary low going

transition (110). The two AC transition scenarios include data low for a short period of time (one half clock)

followed by a high going transition (101) and the complementary low going transition (010). The DC transitions

will typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully

settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data

valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow the

host controller to identify the beginning and ending of the valid data eye. Once the data eye has been

characterized the optimal data capture point can be chosen. See “SPI DDR Data Learning Registers” on page 52

for more details.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

A-3

A-2

A-1

A

8

9

4

5

0

1

2

3

0

1

2

3

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

IO2

10 6

11 7

IO3

IO4

A-3

A-2

A-1

A

8

9

4

5

IO5

IO6

10 6

IO7

3

7

Phase

Instruction

Address

Mode

Dummy

DLP

D1D2

Figure 58

Dual-Quad SPI DDR Quad I/O Read Initial Access

Notes

48.A = MSB of address = 23 for command EDh, or 31 for command EEh.

49.Example DLP of 34h (or 00110100).

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

CS#

SCK

IO0

IO1

A-3

A-2

A-1

A

8

9

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

4

5

6

7

4

5

6

7

0

1

2

3

0

1

2

3

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

IO2

10

11

8

IO3

IO4

A-3

A-2

A-1

A

IO5

9

IO6

10

11

IO7

Phase

Address

Mode

Dummy

DLP

D1 D2

Figure 59

Dual-Quad Continuous DDR Quad I/O Read Subsequent Access

Notes

50.A = MSB of address = 23 for command EDh, or 31 for command EEh.

51.Example DLP of 34h (or 00110100).

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.5

Program Flash Array commands

Program granularity

Automatic ECC

10.5.1

10.5.1.1

Each 16 byte aligned and 16 byte length Programming Block has a hidden error correction code (ECC) value. The

data block plus ECC form an ECC unit. In combination with EDC logic the ECC is used to detect and correct any

single bit error found during a read access. When data is first programmed within an ECC unit the ECC value is set

for the entire ECC unit. If the same ECC unit is programmed more than once the ECC value is changed to disable

the error detection and correction (EDC) function. A sector erase is needed to again enable Automatic ECC on that

Programming Block. The 16 byte Program Block is the smallest program granularity on which Automatic ECC is

enabled.

These are automatic operations transparent to the user. The transparency of the Automatic ECC feature

enhances data accuracy for typical programming operations which write data once to each ECC unit but,

facilitates software compatibility to previous generations of FL-S family of products by allowing for single byte

programming and bit walking in which the same ECC unit is programmed more than once. When an ECC unit has

Automatic ECC disabled, EDC is not done on data read from the ECC unit location.

An ECC status register is provided for determining if ECC is enabled on an ECC unit and whether any errors have

been detected and corrected in the ECC unit data or the ECC (See “ECC Status Register (ECCSR)” on

page 49.)The ECC Status Register Read (ECCRD) command is used to read the ECC status on any ECC unit.

EDC is applied to all parts of the Flash address spaces other than registers. An ECC is calculated for each group of

bytes protected and the ECC is stored in a hidden area related to the group of bytes. The group of protected bytes

and the related ECC are together called an ECC unit.

ECC is calculated for each 16 byte aligned and length ECC unit.

• Single Bit EDC is supported with 8 ECC bits per ECC unit, plus 1-bit for an ECC disable Flag.

• Sector erase resets all ECC bits and ECC disable flags in a sector to the default state (enabled).

• ECC is programmed as part of the standard Program commands operation.

• ECC is disabled automatically if multiple programming operations are done on the same ECC unit.

• Single byte programming or bit walking is allowed but disables ECC on the second program to the same 16-byte

ECC unit.

• The ECC disable flag is programmed when ECC is disabled.

• To re-enable ECC for an ECC unit that has been disabled, the Sector that includes the ECC unit must be erased.

• To ensure the best data integrity provided by EDC, each ECC unit should be programmed only once so that ECC

is stored for that unit and not disabled.

• The calculation, programming, and disabling of ECC is done automatically as part of a programming operation.

The detection and correction, if needed, is done automatically as part of read operations. The host system sees

only corrected data from a read operation.

• ECC protects the OTP region - however a second program operation on the same ECC unit will disable ECC

permanently on that ECC unit (OTP is one time programmable, hence an erase operation to re-enable the ECC

enable/indicator bit is prohibited).

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.5.1.2

Page programming

Page programming is done by loading a Page Buffer with data to be programmed and issuing a programming

command to move data from the buffer to the memory array. This sets an upper limit on the amount of data that

can be programmed with a single programming command. Page programming allows up to a page size (1024

bytes) to be programmed in one operation. The page is aligned on the page size address boundary. It is possible

to program from one bit up to a page size in each Page programming operation. It is recommended that a

multiple of 16 byte length and aligned Program Blocks be written. For the very best performance, programming

should be done in full pages of 512 bytes aligned on 512-byte boundaries with each Page being programmed only

once.

10.5.1.3

Single byte programming

Single byte programming allows full backward compatibility to the standard SPI page programming (PP)

command by allowing a single byte to be programmed anywhere in the memory array.

10.5.2

Page Program (PP 02h or 4PP 12h)

The Page Program (PP) commands allows bytes to be programmed in the memory (changing bits from ‘1’ to ‘0’).

Before the Page Program (PP) commands can be accepted by the device, a Write Enable (WREN) command must

be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully,

the device sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The instruction

• 02h (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 02h (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 12h is followed by a 4-byte address (A31–A0)

and at least one data byte on IO0 and IO4. Up to a page can be provided on IO0 and IO4 after the 3-byte address

with instruction 02h or 4-byte address with instruction 12h has been provided. If the 9 least significant address

bits (A8–A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed

from the start address of the same page (from the address whose 9 least significant bits (A8–A0) are all zero) i.e.

the address wraps within the page aligned address boundaries. This is a result of only requiring the user to enter

one single page address to cover the entire page boundary.

If less than a page of data is sent to the device, these data bytes will be programmed in sequence, starting at the

provided address within the page, without having any affect on the other bytes of the same page.

For optimized timings, using the Page Program (PP) command to load the entire page size program buffer within

the page boundary will save overall programming time versus loading less than a page size into the program

buffer.

The programming process is managed by the flash memory device internal control logic. After a programming

command is issued, the programming operation status can be checked using the Read Status Register 1

command. The WIP bit (SR1[0]) will indicate when the programming operation is completed. The P_ERR bit

(SR1[6]) will indicate if an error occurs in the programming operation that prevents successful completion of

programming.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

A

5

4

3

2

1

0

3

7

2

6

1

5

0

4

3

7

2

6

1

5

0

4

IO5-IO7

Phase

Instruction

Address

Input Data1

Input Data 2

Figure 60

Dual-Quad Page Program (PP 02h or 4PP 12h) command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.5.3

Quad Page Program (QPP 32h or 38h, or 4QPP 34h)

The Quad-input Page Program (QPP) command allows bytes to be programmed in the memory (changing bits

from ‘1’ to ‘0’). The Quad-input Page Program (QPP) command allows up to a page size (512 bytes) of data to be

loaded into the Page Buffer using eight signals: IO0–IO7. QPP can improve performance for PROM Programmer

and applications that have slower clock speeds (< 12 MHz) by loading 8 bits of data per clock cycle. Systems with

faster clock speeds do not realize as much benefit for the QPP command since the inherent page program time

becomes greater than the time it takes to clock-in the data. The maximum frequency for the QPP command is

80 MHz.

To use Quad Page Program the Quad Enable Bit in the Configuration Register must be set (QUAD = 1). A Write

Enable command must be executed before the device will accept the QPP command (Status Register-1, WEL = 1).

The instruction

• 32h (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 32h (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 38h (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 38h (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 34h is followed by a 4-byte address (A31–A0)

and at least two data bytes, into the IO signals. Data must be programmed at previously erased (FFh) memory

locations.

QPP requires programming to be done one full page at a time. While less than a full page of data may be loaded

for programming, the entire page is considered programmed, any locations not filled with data will be left as

ones, the same page must not be programmed more than once.

All other functions of QPP are identical to Page Program. The QPP command sequence is shown in the Figure 61.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

A

1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

0

1

0

1

IO2

2

IO3

3

IO4

4

IO5

5

IO6

6

IO7

7

Phase

Instruction

Address

D1 D2

D3

D4

...

Figure 61

Dual-Quad, Quad Page Program command sequence

Note

52.A = MSB of address = A23 for PP 02h, or A31 for PP 02h, or for 4PP 12h.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.5.4

Program Suspend (PGSP 85h) and Resume (PGRS 8Ah)

The Program Suspend command allows the system to interrupt a programming operation and then read from

any other non-erase-suspended sector or non-program-suspended-page. Program Suspend is valid only during

a programming operation.

Commands allowed after the Program Suspend command is issued:

• Read Status Register 1 (RDSR1 05h)

• Read Status Register 2 (RDSR2 07h)

The Write in Progress (WIP) bit in Status Register 1 (SR1[0]) must be checked to know when the programming

operation has stopped. The Program Suspend Status bit in the Status Register 2 (SR2[0]) can be used to

determine if a programming operation has been suspended or was completed at the time WIP changes to ‘0’. The

time required for the suspend operation to complete is t_PSL, see Table 43.

See Table 41 for the commands allowed while programming is suspend.

The Program Resume command 8Ah must be written to resume the programming operation after a Program

Suspend. If the programming operation was completed during the suspend operation, a resume command is not

needed and has no effect if issued. Program Resume commands will be ignored unless a Program operation is

suspended.

After a Program Resume command is issued, the WIP bit in the Status Register 1 will be set to ‘1’ and the

programming operation will resume. Program operations may be interrupted as often as necessary e.g. a

program suspend command could immediately follow a program resume command but, in order for a program

operation to progress to completion there must be some periods of time between resume and the next suspend

command greater than or equal to t_PRS. See Table 43.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 62

Dual-Quad Program Suspend command sequence

CS#

SCK

IO0

7

6

5

4

3

2

1

0

IO1-IO3

IO4

IO5-IO7

Phase

Instruction

Figure 63

Dual_Quad Program Resume command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.6

Erase Flash Array commands

10.6.1

Sector Erase (SE D8h or 4SE DCh)

The Sector Erase (SE) command sets all bits in the addressed sector to ‘1’ (all bytes are FFh). Before the Sector

Erase (SE) command can be accepted by the device, a Write Enable (WREN) command must be issued and

decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write

operations.

The instruction

• D8h [ExtAdd = 0] is followed by a 3-byte address (A23–A0), or

• D8h [ExtAdd = 1] is followed by a 4-byte address (A31–A0), or

• DCh is followed by a 4-byte address (A31–A0)

CS# must be driven into the logic HIGH state after the twenty-fourth or thirty-second bit of address has been

latched in on IO0 and IO4. This will initiate the erase cycle, which involves the pre-programming and erase of the

chosen sector. If CS# is not driven HIGH after the last bit of address, the sector erase operation will not be

executed.

As soon as CS# is driven into the logic HIGH state, the internal erase cycle will be initiated. With the internal erase

cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been

completed. The WIP bit will indicate ‘1’ when the erase cycle is in progress and ‘0’ when the erase cycle has been

completed.

A Sector Erase (SE) command applied to a sector that has been Write Protected through the Block Protection bits

or ASP, will not be executed and will set the E_ERR status.

ASP has a PPB and a DYB protection bit for each sector.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

A

1

0

IO5-IO7

Phase

Instruction

Address

Figure 64

Dual-Quad Sector Erase (SE 20h or 4SE 21h) command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.6.2

Bulk Erase (BE 60h or C7h)

The Bulk Erase (BE) command sets all bits to ‘1’ (all bytes are FFh) inside the entire flash memory array. Before

the BE command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded

by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on IO0

and IO4. This will initiate the erase cycle, which involves the pre-programming and erase of the entire flash

memory array. If CS# is not driven HIGH after the last bit of instruction, the BE operation will not be executed.

As soon as CS# is driven into the logic HIGH state, the erase cycle will be initiated. With the erase cycle in progress,

the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has been

completed. The WIP bit will indicate ‘1’ when the erase cycle is in progress and ‘0’ when the erase cycle has been

completed.

A BE command can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0’s. If the BP bits

are not ‘0’, the BE command is not executed and E_ERR is not set. The BE command will skip any sectors

protected by the DYB or PPB and the E_ERR status will not be set.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 65

Bulk Erase command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.6.3

Erase Suspend and Resume commands (ERSP 75h or ERRS 7Ah)

The Erase Suspend command, allows the system to interrupt a sector erase operation and then read from or

program data to, any other sector. Erase Suspend is valid only during a sector erase operation. The Erase Suspend

command is ignored if written during the Bulk Erase operation.

When the Erase Suspend command is written during the sector erase operation, the device requires a maximum

of t_ESL(erase suspend latency) to suspend the erase operation and update the status bits. See Table 44.

Commands allowed after the Erase Suspend command is issued:

• Read Status Register 1 (RDSR1 05h)

• Read Status Register 2 (RDSR2 07h)

The Write in Progress (WIP) bit in Status Register 1 (SR1[0]) must be checked to know when the erase operation

has stopped. The Erase Suspend bit in Status Register 2 (SR2[1]) can be used to determine if an erase operation

has been suspended or was completed at the time WIP changes to ‘0’.

If the erase operation was completed during the suspend operation, a resume command is not needed and has

no effect if issued. Erase Resume commands will be ignored unless an Erase operation is suspended.

See Table 41 for the commands allowed while erase is suspend.

After the erase operation has been suspended, the sector enters the erase-suspend mode. The system can read

data from or program data to the device. Reading at any address within an erase-suspended sector produces

undetermined data.

A WREN command is required before any command that will change nonvolatile data, even during erase suspend.

The WRR and PPB Erase commands are not allowed during Erase Suspend, it is therefore not possible to alter the

Block Protection or PPB bits during Erase Suspend. If there are sectors that may need programming during Erase

suspend, these sectors should be protected only by DYB bits that can be turned off during Erase Suspend.

However, WRR is allowed immediately following the BRAC command; in this special case the WRR is interpreted

as a write to the Bank Address Register, not a write to SR1 or CR1.

If a program command is sent for a location within an erase suspended sector the program operation will fail with

the P_ERR bit set.

After an erase-suspended program operation is complete, the device returns to the erase-suspend mode. The

system can determine the status of the program operation by reading the WIP bit in the Status Register, just as

in the standard program operation.

The Erase Resume command 7Ah must be written to resume the erase operation if an Erase is suspend. Erase

Resume commands will be ignored unless an Erase is Suspend.

After an Erase Resume command is sent, the WIP bit in the status register will be set to ‘1’ and the erase operation

will continue. Further Resume commands are ignored.

Erase operations may be interrupted as often as necessary e.g. an erase suspend command could immediately

follow an erase resume command but, in order for an erase operation to progress to completion there must be

some periods of time between resume and the next suspend command greater than or equal to t_ERS. See

Table 44.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 66

Dual-Quad Erase Suspend command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 67

Table 41

Dual-Quad Erase Resume command sequence

Commands allowed during Program or Erase Suspend

Allowed

Instruction

Code

Allowed

during erase

suspend

Instruction

name

during

program

suspend

Comment

(Hex)

Bank address register may need to be changed during a

suspend to reach a sector for read or program.

BRAC

BRRD

BRWR

CLSR

B9

16

17

30

X

–

Bank address register may need to be changed during a

suspend to reach a sector for read or program.

Bank address register may need to be changed during a

suspend to reach a sector for read or program.

Clear status may be used if a program operation fails

during erase suspend.

It may be necessary to remove and restore dynamic

protection during erase suspend to allow programming

during erase suspend.

DYBRD

DYBWR

E0

E1

X

–

It may be necessary to remove and restore dynamic

protection during erase suspend to allow programming

during erase suspend.

ERRS

FAST_READ

4FAST_READ

MBR

7A

0B

0C

FF

X

Required to resume from erase suspend.

All array reads allowed in suspend.

X

All array reads allowed in suspend.

May need to reset a read operation during suspend.

Needed to resume a program operation. A program

resume may also be used during nested program suspend

within an erase suspend.

PGRS

8A

X

PGSP

PP

85

02

12

X

–

Program suspend allowed during erase suspend.

Required for array program during erase suspend.

4PP

Allowed for checking persistent protection before

PPBRD

E2

X

–

attempting a program command during erase suspend.

QPP

4QPP

32, 38

34

X

–

X

Required for array program during erase suspend.

All array reads allowed in suspend.

–

4READ

RDCR

13

35

DDRQIOR

DDRQIOR4

QIOR

ED

EE

All array reads allowed in suspend.

EB

4QIOR

EC

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

Table 41

Commands allowed during Program or Erase Suspend (Continued)

Allowed

Instruction

Code

Allowed

during erase

suspend

Instruction

name

during

program

suspend

Comment

(Hex)

QOR

4QOR

RDSR1

6B

6C

05

X

All array reads allowed in suspend.

Needed to read WIP to determine end of suspend process.

Needed to read suspend status to determine whether the

operation is suspended or complete.

RDSR2

07

X

READ

RESET

WREN

03

F0

06

X

All array reads allowed in suspend.

Reset allowed anytime.

Required for program command within erase suspend.

Bank register may need to be changed during a suspend to

reach a sector needed for read or program. WRR is allowed

when following BRAC.

WRR

01

X

10.7

One Time Program Array commands

OTP Program (OTPP 42h)

10.7.1

The OTP Program command programs data in the One Time Program region, which is in a different address space

from the main array data. The OTP region is 2048 bytes so, the address bits from A25 to A10 must be zero for this

command. Refer to “OTP address space” on page 39 for details on the OTP region. The protocol of the OTP

Program command is the same as the Page Program command. Before the OTP Program command can be

accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets

the Write Enable Latch (WEL) in the Status Register to enable any write operations.

To program the OTP array in bit granularity, the rest of the bits within a data byte can be set to ‘1’.

Each region in the OTP memory space can be programmed one or more times, provided that the region is not

locked. Attempting to program zeros in a region that is locked will fail with the P_ERR bit in SR1 set to ‘1’

Programming ones, even in a protected area does not cause an error and does not set P_ERR. Subsequent OTP

programming can be performed only on the un-programmed bits (that is, 1 data). The protocol of the OTP

Program command is the same as the Page Program command. See “Page Program (PP 02h or 4PP 12h)” on

page 90 for the command sequence.

Datasheet

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002-00466 Rev. *H

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.7.2

OTP Read (OTPR 4Bh)

The OTP Read command reads data from the OTP region. The OTP region is 2048 bytes so, the address bits from

A25 to A10 must be zero for this command. Refer to “OTP address space” on page 39 for details on the OTP

region. The protocol of the OTP Read command is similar to the Fast Read command except that it will not wrap

to the starting address after the OTP address is at its maximum; instead, the data beyond the maximum OTP

address will be undefined. Also, the OTP Read command is not affected by the latency code. The OTP read

command always has one dummy byte of latency as shown in Figure 68.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

31

1

0

3

7

2

6

1

5

0

4

3

7

2

6

1

5

0

4

IO2-IO3

IO4

IO5

IO6-IO7

Phase

Instruction

Address

Dummy Cycles

Data 1

Data 2

Figure 68

Read OTP (OTPR 4Bh) command sequence

Datasheet

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002-00466 Rev. *H

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.8

Advanced Sector Protection commands

ASP Read (ASPRD 2Bh)

10.8.1

The ASP Read instruction 2Bh is shifted into SI by the rising edge of the SCK signal. Then the 16-bit ASP register

contents is shifted out on the serial output SO, least significant byte first. Each bit is shifted out at the SCK

frequency by the falling edge of the SCK signal. It is possible to read the ASP register continuously by providing

multiples of 16 clock cycles. The maximum operating clock frequency for the ASP Read (ASPRD) command is

133 MHz.

CS#

SCK

SI_IO0

SO_IO1

IO2-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5

IO6-IO7

Phase

Instruction

Register Read

Repeat Register Read

Figure 69

Dual-Quad SPI ASPRD command sequence

10.8.2

ASP Program (ASPP 2Fh)

Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN) command must

be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch

(WEL) in the Status Register to enable any write operations.

The ASPP command is entered by driving CS# to the logic LOW state, followed by the instruction and two data

bytes on SI, least significant byte first. The ASP Register is two data bytes in length.

The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner

as any other programming operation.

CS# input must be driven to the logic HIGH state after the sixteenth bit of data has been latched in. If not, the

ASPP command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed ASPP operation

is initiated. While the ASPP operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is ‘1’ during the self-timed ASPP operation, and is ‘0’

when it is completed. When the ASPP operation is completed, the Write Enable Latch (WEL) is set to ‘0’.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Input ASPR Low Byte

Input IRP High Byte

Figure 70

ASPP (2Fh) command

Datasheet

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002-00466 Rev. *H

2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.8.3

DYB Read (DYBRD E0h)

The instruction E0h is latched into SI by the rising edge of the SCK signal. Followed by the 32-bit address selecting

location zero within the desired sector (note, the high order address bits not used by a particular density device

must be zero). Then the 8-bit DYB access register contents are shifted out on the serial output SO. Each bit is

shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read the same DYB access

register continuously by providing multiples of eight clock cycles. The address of the DYB register does not

increment so this is not a means to read the entire DYB array. Each location must be read with a separate DYB

Read command. The maximum operating clock frequency for READ command is 133 MHz.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

A

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO2-IO3

IO4

IO5

IO6-IO7

Phase

Address

Instruction

Register

Repeat Register

Figure 71

DYBRD command sequence

10.8.4

DYB Write (DYBWR E1h)

Before the DYB Write (DYBWR) command can be accepted by the device, a Write Enable (WREN) command must

be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch

(WEL) in the Status Register to enable any write operations.

The DYBWR command is entered by driving CS# to the logic LOW state, followed by the instruction, the 32-bit

address selecting location zero within the desired sector (note, the high order address bits not used by a

particular density device must be zero), then the data byte on SI. The DYB Access Register is one data byte in

length.

The DYBWR command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same

manner as any other programming operation. CS# must be driven to the logic HIGH state after the eighth bit of

data has been latched in. If not, the DYBWR command is not executed. As soon as CS# is driven to the logic HIGH

state, the self-timed DYBWR operation is initiated. While the DYBWR operation is in progress, the Status Register

may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is ‘1’ during the

self-timed DYBWR operation, and is ‘0’ when it is completed. When the DYBWR operation is completed, the Write

Enable Latch (WEL) is set to ‘0’.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

A

5

4

3

2

1

0

3

7

2

6

1

5

0

4

3

7

2

6

1

5

0

4

IO5-IO7

Phase

Instruction

Address

Input Data1

Input Data 2

Figure 72

DYBWR (E1h) command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.8.5

PPB Read (PPBRD E2h)

The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 32-bit address selecting

location zero within the desired sector (note, the high order address bits not used by a particular density device

must be zero) Then the 8-bit PPB access register contents are shifted out on SO.

It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles. The

address of the PPB register does not increment so this is not a means to read the entire PPB array. Each location

must be read with a separate PPB Read command. The maximum operating clock frequency for the PPB Read

command is 133 MHz.

CS#

SCK

SI_IO0

SO_IO1

IO2-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5

IO6-IO7

Phase

Instruction

DY

Register Read

Repeat Register Read

Figure 73

PPBRD (E2h) command sequence

10.8.6

PPB Program (PPBP E3h)

Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN) command must

be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch

(WEL) in the Status Register to enable any write operations.

The PPBP command is entered by driving CS# to the logic LOW state, followed by the instruction, followed by the

32-bit address selecting location zero within the desired sector (note, the high order address bits not used by a

particular density device must be zero).

The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner

as any other programming operation.

CS# must be driven to the logic HIGH state after the last bit of address has been latched in. If not, the PPBP

command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PPBP operation is

initiated. While the PPBP operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is ‘1’ during the self-timed PPBP operation, and is ‘0’

when it is completed. When the PPBP operation is completed, the Write Enable Latch (WEL) is set to ‘0’.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

A

1

0

IO5-IO7

Phase

Instruction

Address

Figure 74

PPBP (E3h) command sequence

Datasheet

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002-00466 Rev. *H

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.8.7

PPB Erase (PPBE E4h)

The PPB Erase (PPBE) command sets all PPB bits to ‘1’. Before the PPB Erase command can be accepted by the

device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable

Latch (WEL) in the Status Register to enable any write operations.

The instruction E4h is shifted into SI by the rising edges of the SCK signal.

CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI.

This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of the entire

PPB memory array. Without CS# being driven to the logic HIGH state after the eighth bit of the instruction, the

PPB erase operation will not be executed.

With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if

the operation has been completed. The WIP bit will indicate ‘1’, when the erase cycle is in progress and ‘0’, when

the erase cycle has been completed. Erase suspend is not allowed during PPB Erase.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 75

PPB Erase (PPBE E4h) command sequence

10.8.8

PPB Lock Bit Read (PLBRD A7h)

The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is

possible to read the PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock

Register contents may only be read when the device is in standby state with no other operation in progress. It is

recommended to check the Write-In Progress (WIP) bit of the Status Register before issuing a new command to

the device.

CS#

SCK

SI_IO0

SO_IO1

IO2-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5

IO6-IO7

Phase

Instruction

DY

Register Read

Repeat Register Read

Figure 76

PPB Lock Register Read command sequence

Datasheet

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002-00466 Rev. *H

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.8.9

PPB Lock Bit Write (PLBWR A6h)

The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to ‘0’. Before the PLBWR command can

be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which

sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The PLBWR command is entered by driving CS# to the logic LOW state, followed by the instruction.

CS# must be driven to the logic HIGH state after the eighth bit of instruction has been latched in. If not, the PLBWR

command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PLBWR operation is

initiated. While the PLBWR operation is in progress, the Status Register may still be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is ‘1’ during the self-timed PLBWR operation, and is ‘0’

when it is completed. When the PLBWR operation is completed, the Write Enable Latch (WEL) is set to ‘0’. The

maximum clock frequency for the PLBWR command is 133 MHz.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 77

PPB Lock Bit Write (PLBWR A6h) command sequence

10.8.10

Password Read (PASSRD E7h)

The correct password value may be read only after it is programmed and before the Password Mode has been

selected by programming the Password Protection Mode bit to ‘0’ in the ASP Register (ASP[2]). After the Password

Protection Mode is selected the PASSRD command is ignored.

The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO, least

significant byte first, most significant bit of each byte first. Each bit is shifted out at the SCK frequency by the

falling edge of the SCK signal. It is possible to read the Password continuously by providing multiples of 64 clock

cycles. The maximum operating clock frequency for the PASSRD command is 133 MHz.

CS#

SCK

SI_IO0

SO_IO1

IO2-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5

IO6-IO7

Phase

Instruction

Data 1

Data 8

Figure 78

Password Read (PASSRD E7h) command sequence

Datasheet

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002-00466 Rev. *H

2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.8.11

Password Program (PASSP E8h)

Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN)

command must be issued and decoded by the device. After the Write Enable (WREN) command has been

decoded, the device sets the Write Enable Latch (WEL) to enable the PASSP operation.

The password can only be programmed before the Password Mode is selected by programming the Password

Protection Mode bit to ‘0’ in the ASP Register (ASP[2]). After the Password Protection Mode is selected the PASSP

command is ignored.

The PASSP command is entered by driving CS# to the logic LOW state, followed by the instruction and the

password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is

sixty-four (64) bits in length.

CS# must be driven to the logic HIGH state after the sixty-fourth (64^th) bit of data has been latched. If not, the

PASSP command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PASSP operation

is initiated. While the PASSP operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is ‘1’ during the self-timed PASSP cycle, and is ‘0’ when

it is completed. The PASSP command can report a program error in the P_ERR bit of the status register. When the

PASSP operation is completed, the Write Enable Latch (WEL) is set to ‘0’. The maximum clock frequency for the

PASSP command is 133 MHz.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Password Byte 1

Password Byte 8

Figure 79

Password Program (PASSP E8h) command sequence

Datasheet

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2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.8.12

Password Unlock (PASSU E9h)

The PASSU command is entered by driving CS# to the logic LOW state, followed by the instruction and the

password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is

sixty-four (64) bits in length.

CS# must be driven to the logic HIGH state after the sixty-fourth (64^th) bit of data has been latched. If not, the

PASSU command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PASSU operation

is initiated. While the PASSU operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is ‘1’ during the self-timed PASSU cycle, and is ‘0’ when

it is completed.

If the PASSU command supplied password does not match the hidden password in the Password Register, an

error is reported by setting the P_ERR bit to ‘1’. The WIP bit of the status register also remains set to ‘1’. It is

necessary to use the CLSR command to clear the status register, the RESET command to software reset the

device, or drive the RESET# input LOW to initiate a hardware reset, in order to return the P_ERR and WIP bits to

‘0’. This returns the device to standby state, ready for new commands such as a retry of the PASSU command.

If the password does match, the PPB Lock bit is set to ‘1’. The maximum clock frequency for the PASSU command

is 133 MHz.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Password Byte 1

Password Byte 8

Figure 80

Password Unlock (PASSU E9h) command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.9

Reset commands

10.9.1

Software Reset command (RESET F0h)

The Software Reset command (RESET) restores the device to its initial power up state, except for the volatile

FREEZE bit in the Configuration register CR1[1] and the volatile PPB Lock bit in the PPB Lock Register. The Freeze

bit and the PPB Lock bit will remain set at their last value prior to the software reset. To clear the FREEZE bit and

set the PPB Lock bit to its protection mode selected power on state, a full power-on-reset sequence or hardware

reset must be done. Note that the nonvolatile bits in the configuration register, TBPROT, TBPARM, and BPNV,

retain their previous state after a Software Reset. The Block Protection bits BP2, BP1, and BP0, in the status

register will only be reset if they are configured as volatile via the BPNV bit in the Configuration Register (CR1[3])

and FREEZE is cleared to ‘0’. The software reset cannot be used to circumvent the FREEZE or PPB Lock bit

protection mechanisms for the other security configuration bits. The reset command is executed when CS# is

brought to HIGH state and requires t_RPHtime to execute.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 81

Dual-Quad Software Reset (RESET F0h) command sequence

10.9.2

Mode Bit Reset (MBR FFh)

The Mode Bit Reset (MBR) command can be used to return the device from continuous high performance read

mode back to normal standby awaiting any new command. Because some device packages lack a hardware

RESET# input and a device that is in a continuous high performance read mode may not recognize any normal

SPI command, a system hardware reset or software reset command may not be recognized by the device. It is

recommended to use the MBR command after a system reset when the RESET# signal is not available or, before

sending a software reset, to ensure the device is released from continuous high performance read mode.

The MBR command sends Ones on IO0 and IO4 for 8 SCK cycles. IO1–IO3 and IO5–IO7 are ‘don’t care’ during these

cycles.

CS#

SCK

IO0

IO1-IO3

IO4

7

6

5

4

3

2

1

0

IO5-IO7

Phase

Instruction

Figure 82

Dual-Quad SPI Mode Bit (MBR FFh) Reset command sequence

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Commands

10.10

Embedded algorithm performance tables

Table 42

Program and erase performance

Parameter

[53]

[54]

Symbol

Min Typ

Max

2000

Unit

ms

t

WRR write time

–

560

340

W

[55, 56]

Page programming (1024 bytes)

750/1300

µs

PP

Sector erase time (512-kB logical sectors = 4 x 128-kB physical

sectors)

t

–

520

103

2600

460

ms

sec

SE

BE

t

Bulk erase time

Table 43

Program suspend AC parameters

Parameter

Program Suspend Latency

Min

Typ

Max

Unit

Comments

The time from Program Suspend command

until the WIP bit is ‘0’.

–

40

µs

(t

)

PSL

Minimum is the time needed to issue the next

Program Suspend command but ≥ typical

periods are needed for Program to progress to

completion

Program Resume to next

Program Suspend (t

0.06

100

–

µs

)

PRS

Table 44

Erase suspend AC parameters

Parameter

Min

Typ

Max

Unit

Comments

The time from Erase Suspend command until

the WIP bit is ‘0’.

Erase Suspend Latency (t

)

–

45

µs

ESL

Minimum is the time needed to issue the next

Erase Suspend command but ≥typical periods

are needed for the Erase to progress to

completion

Erase Resume to next Erase

0.06

100

–

µs

Suspend (t

ERS)

Notes

53.Typical program and erase times assume the following conditions: 25°C, V_CC= 3.0 V; random data pattern.

54.Under worst case conditions of 90°C; 100,000 cycles max.

55.Industrial temperature range / Industrial Plus temperature range.

56.Maximum value also applies to OTPP, PPBP, ASPP, PASSP, ABWR, and PNVDLR programming commands.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Data integrity

11

Data integrity

11.1

Erase endurance

Table 45

Erase endurance

Parameter

Minimum

100K

Unit

Program/erase cycles per main Flash array sectors

P/E cycle

[57]

Program/erase cycles per PPB array or nonvolatile register array

100K

11.2

Data retention

Table 46

Data retention

Parameter

Test conditions

10K program/erase cycles

100K program/erase cycles

Minimum time

Unit

Years

20

2

Data retention time

Note

57.Each write command to a nonvolatile register causes a P/E cycle on the entire nonvolatile register array. OTP

bits and registers internally reside in a separate array that is not P/E cycled.

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

12

Software interface reference

12.1

Serial flash discoverable parameters (SFDP) address map

The SFDP address space has a header starting at address zero that identifies the SFDP data structure and provides

a pointer to each parameter. One Basic Flash parameter is mandated by the JEDEC JESD216B standard. Two

optional parameter tables for Sector Map and 4 Byte Address Instructions follow the Basic Flash table. Infineon

provides an additional parameter by pointing to the ID-CFI address space i.e. the ID-CFI address space is a sub-set

of the SFDP address space. The parameter tables portion of the SFDP data structure are located within the ID-CFI

address space and is thus both a CFI parameter and an SFDP parameter. In this way both SFDP and ID-CFI

information can be accessed by either the RSFDP or RDID commands.

Table 47

SFDP overview map

Byte address

Description

0000h

,,,

Location zero within JEDEC JESD216B SFDP space — start of SFDP header

Remainder of SFDP header followed by undefined space

1000h

...

Location zero within ID-CFI space — start of ID-CFI parameter tables

ID-CFI parameters

1120h

...

Start of SFDP parameter which is also one of the CFI parameter tables

Remainder of SFDP parameter tables followed by either more CFI parameters or undefined space

Datasheet

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

12.1.1

Field definitions

Table 48

SFDP header

Relative byte SFDP Dword

Data

Description

address

This is the entry point for Read SFDP (5Ah) command i.e. location zero

within SFDP space ASCII “S”

00h

53h

SFDP Header

1st DWORD

01h

02h

03h

46h

44h

50h

ASCII “F”

ASCII “D”

ASCII “P”

SFDP Minor Revision (06h = JEDEC JESD216 Revision B) This revision is

backward compatible with all prior minor revisions. Minor revisions are

changes that define previously reserved fields, add fields to the end, or

that clarify definitions of existing fields. Increments of the minor revision

value indicate that previously reserved parameter fields may have been

assigned a new definition or entire Dwords may have been added to the

parameter table. However, the definition of previously existing fields is

unchanged and therefore remain backward compatible with earlier SFDP

parameter table revisions. Software can safely ignore increments of the

minor revision number, as long as only those parameters the software was

designed to support are used i.e. previously reserved fields and additional

Dwords must be masked or ignored. Do not do a simple compare on the

minor revision number, looking only for a match with the revision number

that the software is designed to handle. There is no problem with using a

higher number minor revision.

04h

06h

SFDP Header

2nd DWORD

SFDP Major Revision This is the original major revision. This major revision

is compatible with all SFDP reading and parsing software.

05h

01h

06h

07h

08h

05h

FFh

00h

Number of Parameter Headers (zero based, 05h = 6 parameters)

Unused

Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)

Parameter Minor Revision (00h = JESD216) — This older revision parameter

header is provided for any legacy SFDP reading and parsing software that

requires seeing a minor revision 0 parameter header. SFDP software

designed to handle later minor revisions should continue reading

parameter headers looking for a higher numbered minor revision that

contains additional parameters for that software revision.

09h

00h

Parameter

Header 0

1st DWORD

Parameter Major Revision (01h = The original major revision — all SFDP

software is compatible with this major revision.

0Ah

0Bh

0Ch

01h

09h

Parameter Table Length (in double words = Dwords = 4 byte units) 09h = 9

Dwords

20h

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC Basic SPI

Flash parameter byte offset = 1120h

Parameter

Header 0

0Dh

0Eh

0Fh

11h

00h

FFh

Parameter Table Pointer Byte 1

2nd DWORD

Parameter Table Pointer Byte 2

Parameter ID MSB (FFh = JEDEC defined legacy Parameter ID)

Datasheet

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Table 48

SFDP header (Continued)

Relative byte SFDP Dword

Data

Description

address

10h

00h

Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)

Parameter Minor Revision (05h = JESD216 Revision A) — This older revision

parameter header is provided for any legacy SFDP reading and parsing

software that requires seeing a minor revision 5 parameter header. SFDP

software designed to handle later minor revisions should continue reading

parameter headers looking for a later minor revision that contains

additional parameters.

11h

05h

Parameter

Header 1

1st DWORD

Parameter Major Revision (01h = The original major revision — all SFDP

software is compatible with this major revision.

12h

13h

14h

01h

10h

20h

Parameter Table Length (in double words = Dwords = 4 byte units) 10h =

16 Dwords

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC Basic SPI

Flash parameter byte offset = 1120h address

Parameter

Header 1 2nd

DWORD

15h

16h

17h

18h

19h

11h

00h

FFh

00h

06h

Parameter Table Pointer Byte 1

Parameter Table Pointer Byte 2

Parameter ID MSB (FFh = JEDEC defined Parameter)

Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)

Parameter Minor Revision (06h = JESD216 Revision B)

Parameter

Header 2

Parameter Major Revision (01h = The original major revision - all SFDP

software is compatible with this major revision.

1Ah

1Bh

1Ch

01h

10h

20h

1st DWORD

Parameter Table Length (in double words = Dwords = 4 byte units) 10h =

16 Dwords

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC Basic SPI

Flash parameter byte offset = 1120h address

Parameter

Header 2 2nd

DWORD

1Dh

1Eh

1Fh

20h

11h

00h

FFh

81h

Parameter Table Pointer Byte 1

Parameter Table Pointer Byte 2

Parameter ID MSB (FFh = JEDEC defined Parameter)

Parameter ID LSB (81h = SFDP Sector Map Parameter)

Parameter Minor Revision (00h = Initial version as defined in JESD216

Revision B)

21h

00h

Parameter

Header 3

Parameter Major Revision (01h = The original major revision — all SFDP

software that recognizes this parameter’s ID is compatible with this major

revision.

22h

01h

1st DWORD

Parameter Table Length (in double words = Dwords = 4 byte units) 02h = 2

Dwords

23h

24h

02h

60h

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC parameter

byte offset = 1160h

Parameter

Header 3 2nd

DWORD

25h

26h

27h

28h

11h

00h

FFh

84h

Parameter Table Pointer Byte 1

Parameter Table Pointer Byte 2

Parameter ID MSB (FFh = JEDEC defined Parameter)

Parameter ID LSB (00h = SFDP 4 Byte Address Instructions Parameter)

Parameter Minor Revision (00h = Initial version as defined in JESD216

Revision B)

29h

2Ah

2Bh

00h

01h

02h

Parameter

Header 4

Parameter Major Revision (01h = The original major revision - all SFDP

software that recognizes this parameter’s ID is compatible with this major

revision.

1st DWORD

Parameter Table Length (in double words = Dwords = 4 byte units) (2h = 2

Dwords)

Datasheet

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Table 48

SFDP header (Continued)

Relative byte SFDP Dword

Data

Description

address

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC parameter

byte offset = 1168h

2Ch

68h

Parameter

Header 4 2nd

DWORD

2Dh

2Eh

2Fh

11h

00h

FFh

Parameter Table Pointer Byte 1

Parameter Table Pointer Byte 2

Parameter ID MSB (FFh = JEDEC defined Parameter)

Parameter ID LSB (Infineon Vendor Specific ID-CFI parameter) Legacy

Manufacturer ID 01h = AMD / Infineon

30h

31h

01h

Parameter Minor Revision (01h = ID-CFI updated with SFDP Rev B table)

Parameter Major Revision (01h = The original major revision - all SFDP

software that recognizes this parameter’s ID is compatible with this major

revision.

Parameter

Header 5

32h

01h

1st DWORD

Parameter Table Length (in double words = Dwords = 4 byte units) CFI

starts at 1000h, the final SFDP parameter (CFI ID = A5) starts at 111Eh (SFDP

starting point of 1120h -2hB of CFI parameter header), for a length of 11EhB

excluding the CFI A5 parameter. The final CFI A5 parameter adds an

additional 52hB for a total of 11Eh + 82h = 170hB. 170hB/4 = 5Ch Dwords.

33h

34h

5Ch

00h

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) Entry point for

ID-CFI parameter is byte offset = 1000h relative to SFDP location zero.

Parameter

Header 5 2nd

DWORD

35h

36h

37h

10h

00h

01h

Parameter Table Pointer Byte 1

Parameter Table Pointer Byte 2

Parameter ID MSB (01h = JEDEC JEP106 Bank Number 1)

Datasheet

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12.2

Device ID and common flash interface (ID-CFI) address map

Field definitions

12.2.1

Table 49

Manufacturer and Device ID

Byte address

Data

01h

79h

21h

Description

00h

01h

02h

Manufacturer ID for Infineon

Device ID Most Significant Byte — Memory Interface Type

Device ID Least Significant Byte — Density

ID-CFI Length — number bytes following. Adding this value to the

current location of 03h gives the address of the last valid location in the

ID-CFI address map. A value of 00h indicates the entire 512-byte ID-CFI

space must be read because the actual length of the ID-CFI information

is longer than can be indicated by this legacy single byte field. The

value is OPN dependent.

03h

4Eh

00h (Uniform 512-kB

sectors)

04h

Sector Architecture

05h

06h

80h (FL-S Family)

xxh

Family ID

ASCII characters for Model

Refer to “Ordering information” on page 134 for the model

number definitions.

07h

xxh

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

xxh

Reserved

Table 50

CFI query identification string

Byte address

Data

Description

10h

11h

12h

51h

52h

59h

Query Unique ASCII string “QRY”

13h

14h

02h

00h

Primary OEM Command Set

FL-P backward compatible command set ID

15h

16h

40h

00h

Address for Primary Extended Table

17h

18h

53h

46h

Alternate OEM Command Set

ASCII characters “FS” for SPI (F) interface, S Technology

19h

1Ah

51h

00h

Address for Alternate OEM Extended Table

Datasheet

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Table 51

CFI system interface string

Byte address

Data

Description

Min. (erase/program): 100 millivolts

Max. (erase/program): 100 millivolts

1Bh

1Ch

27h

V

CC

PP

36h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

00h

Min. voltage (00h = no V present)

PP

Max. voltage (00h = no V present)

PP

N

06h

Typical timeout per single byte program 2 µs

N

09h (512B page)

09h (512 kB)

11h (1024 Mb)

02h

Typical timeout for Min. size Page program 2 µs (00h = not supported)

N

Typical timeout per individual sector erase 2 ms

N

Typical timeout for full chip erase 2 ms (00h = not supported)

N

Max. timeout for byte program 2 times typical

N

02h

Max. timeout for page program 2 times typical

N

03h

Max. timeout per individual sector erase 2 times typical

N

03h

Max. timeout for full chip erase 2 times typical (00h = not supported)

Table 52

Device geometry definition for 1024-Mbit device

Byte address

Data

1Bh (1024 Mb)

03h

Description

N

27h

28h

Device Size = 2 bytes;

Flash Device Interface Description;

0000h = x8 only

0001h = x16 only

0002h = x8/x16 capable

0003h = x32 only

29h

01h

0004h = Single I/O SPI, 3-byte address

0005h = Multi I/O SPI, 3-byte address

0102h = Multi I/O SPI, 3- or 4-byte address

0103h = Dual-Quad SPI, 3 or 4-byte address

N

2Ah

2Bh

0Ah

00h

Max. number of bytes in multi-byte write = 2

(0000 = not supported

0009h = 512B page

000Ah = 1024B page)

Number of Erase Block Regions within device

1 = Uniform Device, 2 = Boot Device

2Ch

01h

2Dh

2Eh

FFh

00h

08h

FFh

Erase Block Region 1 Information (refer to JEDEC JEP137)

256 sectors = 256-1 = 00FFh

2Fh

512-kB sectors = 256 bytes x 0800h

30h

31h thru 3Fh

RFU

Datasheet

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Software interface reference

Table 53

CFI primary vendor-specific extended query

Byte address

Data

50h

52h

49h

31h

33h

Description

40h

41h

42h

43h

44h

Query-unique ASCII string “PRI”

Major version number = 1, ASCII

Minor version number = 3, ASCII

Address Sensitive Unlock (Bits 1–0)

00b = Required

01b = Not Required

Process Technology (Bits 5–2)

0000b = 0.23 µm Floating Gate

0001b = 0.17 µm Floating Gate

0010b = 0.23 µm MIRRORBIT™

0011b = 0.11 µm Floating Gate

0100b = 0.11 µm MIRRORBIT™

0101b = 0.09 µm MIRRORBIT™

1000b = 0.065 µm MIRRORBIT™

45h

21h

Erase Suspend

0 = Not Supported

1 = Read Only

46h

02h

2 = Read and Program

Sector Protect

47h

48h

01h

00h

00 = Not Supported

X = Number of sectors in group

Temporary Sector Unprotect

00 = Not Supported

01 = Supported

Sector Protect/Unprotect Scheme

04 = High Voltage Method

49h

08h

05 = Software Command Locking Method

08 = Advanced Sector Protection Method

09 = Secure

Simultaneous Operation

00 = Not Supported

4Ah

4Bh

00h

01h

X = Number of Sectors

Burst Mode (Synchronous sequential read) support

00 = Not Supported

01 = Supported

Page Mode Type, model dependent

00 = Not Supported

01 = 4 Word Read Page

4Ch

05h

02 = 8 Read Word Page

03 = 256-Byte Program Page

04 = 512-Byte Program Page

05 = 1024-Byte Program Page

ACC (Acceleration) Supply Minimum

00 = Not Supported, 100 mV

4Dh

4Eh

00h

ACC (Acceleration) Supply Maximum

00 = Not Supported, 100 mV

Datasheet

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Table 53

CFI primary vendor-specific extended query (Continued)

Byte address

Data

Description

WP# Protection

00 = None

01 = Whole Chip

4Fh

50h

00h

04 = Uniform Device with Bottom WP Protect

05 = Uniform Device with Top WP Protect

07 = Uniform Device with Top or Bottom Write Protect (user select)

Program Suspend

00 = Not Supported

01 = Supported

01h

The alternate vendor-specific extended query provides information related to the expanded command set

provided by the S79FL-S family. The alternate query parameters use a format in which each parameter begins

with an identifier byte and a parameter length byte. Driver software can check each parameter ID and can use the

length value to skip to the next parameter if the parameter is not needed or not recognized by the software.

Table 54

CFI alternate vendor-specific extended query header

Byte address

Data

41h

4Ch

54h

32h

30h

Description

51h

52h

53h

54h

55h

Query-unique ASCII string “ALT”

Major version number = 2, ASCII

Minor version number = 0, ASCII

Datasheet

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Table 55

CFI alternate vendor-specific extended query parameter 0

Parameter relative

byte address offset

Data

Description

00h

Parameter ID (ordering part number)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of the

next parameter)

01h

10h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

53h

37h

ASCII “S” for manufacturer (Infineon)

ASCII “79” for Product Characters (Dual-Quad SPI)

39h

46h

ASCII “FL” for Interface Characters (SPI 3 Volt)

4Ch

30h (1 Gb)

31h (1 Gb)

47h (1 Gb)

53h

ASCII characters for density

ASCII “S” for technology (65-nm MIRRORBIT™)

xxh

Reserved for Future Use (RFU)

xxh

Table 56

CFI alternate vendor-specific extended query parameter 80h address options

Parameter relative byte

address offset

Data

Description

00h

80h

Parameter ID (ordering part number)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of the

next parameter)

01h

F0h

Bits 7:4 - Reserved = 1111b

Bit 3 - AutoBoot support - Yes= 0b, No = 1b

Bit 2 - 4-byte address instructions supported - Yes = 0b, No = 1b

Bit 1 - Bank address + 3-byte address instructions supported - Yes = 0b,

No = 1b

02h

Bit 0 - 3-byte address instructions supported - Yes = 0b, No = 1b

Datasheet

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Software interface reference

Table 57

CFI alternate vendor-specific extended query parameter 84h suspend commands

Parameter relative byte

address offset

Data

Description

00h

84h

Parameter ID (Suspend Commands)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of the

next parameter)

01h

08h

02h

03h

04h

05h

06h

07h

08h

09h

85h

28h

8Ah

64h

75h

2Dh

7Ah

64h

Program suspend instruction code

Program suspend latency maximum (µs)

Program resume instruction code

Program resume to next suspend typical (µs)

Erase suspend instruction code

Erase suspend latency maximum (µs)

Erase resume instruction code

Erase resume to next suspend typical (µs)

Table 58

CFI alternate vendor-specific extended query parameter 88h data protection

Parameter relative byte

address offset

Data

Description

00h

88h

Parameter ID (Data Protection)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of the

next parameter)

01h

04h

N

02h

03h

0Bh

01h

OTP size 2 bytes, FFh = not supported

OTP address map format, 01h = FL-S format, FFh = not supported

Block Protect Type, model dependent

00h = FL-P, FL-S, FFh = not supported

04h

05h

xxh

01h

Advanced Sector Protection type, model dependent

01h = FL-S ASP

Table 59

CFI alternate vendor-specific extended query parameter 8Ch reset timing

Parameter relative byte

address offset

Data

Description

00h

8Ch

Parameter ID (Reset Timing)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of the

next parameter)

01h

06h

02h

03h

04h

05h

06h

07h

96h

01h

23h

00h

23h

00h

POR maximum value

N

POR maximum exponent 2 µs

Hardware Reset maximum value, FFh = not supported

N

Hardware Reset maximum exponent 2 µs

Software Reset maximum value, FFh = not supported

N

Software Reset maximum exponent 2 µs

Datasheet

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Software interface reference

Table 60

CFI alternate vendor-specific extended query parameter 90h — EHPLC (SDR)

Parameter relative byte

address offset

Data

Description

00h

90h

Parameter ID (Latency Code Table)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of the

next parameter)

01h

56h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

06h

0Eh

46h

43h

03h

13h

0Bh

0Ch

FFh

6Bh

6Ch

FFh

EBh

ECh

32h

03h

00h

FFh

00h

FFh

02h

01h

50h

00h

FFh

00h

08h

FFh

Number of rows

Row length in bytes

Start of header (row 1), ASCII “F” for frequency column header

ASCII “C” for Code column header

Read 3-byte address instruction

Read 4-byte address instruction

Read Fast 3-byte address instruction

Read Fast 4-byte address instruction

Read Dual Out 3-byte address instruction

Read Quad Out 3-byte address instruction

Read Quad Out 4-byte address instruction

Dual I/O Read 3-byte address instruction

Dual I/O Read 4-byte address instruction

Quad I/O Read 3-byte address instruction

Quad I/O Read 4-byte address instruction

Start of row 2, SCK frequency limit for this row (50 MHz)

Latency Code for this row (11b)

Read mode cycles

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Quad I/O Read latency cycles

Start of row 3, SCK frequency limit for this row (80 MHz)

Latency Code for this row (00b)

Read mode cycles (FFh = command not supported at this frequency)

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Datasheet

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Software interface reference

Table 60

CFI alternate vendor-specific extended query parameter 90h — EHPLC (SDR) (Continued)

Parameter relative byte

address offset

Data

Description

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

FFh

00h

08h

FFh

02h

04h

5Ah

01h

FFh

00h

08h

FFh

00h

08h

FFh

02h

04h

68h

02h

FFh

00h

08h

FFh

00h

08h

FFh

02h

05h

85h

02h

FFh

00h

08h

FFh

Read Dual Out latency cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Quad I/O Read latency cycles

Start of row 4, SCK frequency limit for this row (90 MHz)

Latency Code for this row (01b)

Read mode cycles (FFh = command not supported at this frequency)

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Read Dual Out latency cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Quad I/O Read latency cycles

Start of row 5, SCK frequency limit for this row (104 MHz)

Latency Code for this row (10b)

Read mode cycles (FFh = command not supported at this frequency)

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Read Dual Out latency cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Quad I/O Read latency cycles

Start of row 6, SCK frequency limit for this row (133 MHz)

Latency Code for this row (10b)

Read mode cycles (FFh = command not supported at this frequency)

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Datasheet

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Software interface reference

Table 60

CFI alternate vendor-specific extended query parameter 90h — EHPLC (SDR) (Continued)

Parameter relative byte

address offset

Data

Description

51h

52h

53h

54h

55h

56h

57h

FFh

Read Dual Out latency cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Quad I/O Read latency cycles

Note:

FFh = Not supported.

Datasheet

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Software interface reference

Table 61

CFI alternate vendor-specific extended query parameter 9Ah — EHPLC (DDR)

Parameter relative byte

address offset

Data

Description

00h

9Ah

Parameter ID (Latency Code Table)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of the

next parameter)

01h

2Ah

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

05h

08h

46h

43h

FFh

EDh

EEh

32h

03h

FFh

01h

03h

50h

00h

FFh

01h

06h

FFh

Number of rows

Row length in bytes

Start of header (row 1), ASCII “F” for frequency column header

ASCII “C” for Code column header

Read Fast DDR 3-byte address instruction

Read Fast DDR 4-byte address instruction

DDR Dual I/O Read 3-byte address instruction

DDR Dual I/O Read 4-byte address instruction

Read DDR Quad I/O 3-byte address instruction

Read DDR Quad I/O 4-byte address instruction

Start of row 2, SCK frequency limit for this row (50 MHz)

Latency Code for this row (11b)

Read Fast DDR mode cycles

Read Fast DDR latency cycles

DDR Dual I/O Read mode cycles

DDR Dual I/O Read latency cycles

Read DDR Quad I/O mode cycles

Read DDR Quad I/O latency cycles

Start of row 3, SCK frequency limit for this row (80 MHz)

Latency Code for this row (00b)

Read Fast DDR mode cycles

Read Fast DDR latency cycles

DDR Dual I/O Read mode cycles

DDR Dual I/O Read latency cycles

Read DDR Quad I/O mode cycles

Read DDR Quad I/O latency cycles

Start of row 4, SCK frequency limit for this row (66 MHz)

Latency Code for this row (01b)

Read Fast DDR mode cycles

Read Fast DDR latency cycles

DDR Dual I/O Read mode cycles

DDR Dual I/O Read latency cycles

Read DDR Quad I/O mode cycles

Read DDR Quad I/O latency cycles

Start of row 5, SCK frequency limit for this row (66 MHz)

Latency Code for this row (10b)

Read Fast DDR mode cycles

Datasheet

122

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

Table 61

CFI alternate vendor-specific extended query parameter 9Ah — EHPLC (DDR) (Continued)

Parameter relative byte

address offset

Data

Description

27h

28h

29h

2Ah

2Bh

FFh

Read Fast DDR latency cycles

DDR Dual I/O Read mode cycles

DDR Dual I/O Read latency cycles

Read DDR Quad I/O mode cycles

Read DDR Quad I/O latency cycles

Note:

FFh = Not supported.

Datasheet

123

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Software interface reference

Table 62

CFI alternate vendor-specific extended query parameter F0h RFU

Parameter relative byte

address offset

Data

Description

00h

F0h

Parameter ID (RFU)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of the

next parameter)

01h

0Fh

02h

...

FFh

RFU

10h

This parameter type (Parameter ID F0h) may appear multiple times and have a different length each time. The

parameter is used to reserve space in the ID-CFI map or to force space (pad) to align a following parameter to a

required boundary.

Table 63

CFI alternate vendor-specific extended query parameter A5h, JEDEC SFDP Rev B

CFI parameter

SFDP parameter

relative byte

SFDP Dword

name

relative byte

Data

Description

address offset

00h

—

N/A

A5h

CFI Parameter ID (JEDEC SFDP)

CFI Parameter Length (The number of

following bytes in this parameter. Adding this

value to the current location value + 1 = the

first byte of the next parameter)

01h

—

N/A

50h

Start of SFDP JEDEC parameter, located at

1120h in the overall SFDP address space.

Bits 7:5 = unused = 111b

Bits 4:3 = 06h is status register write

instruction and status register is default

nonvolatile = 00b

02h

03h

04h

00h

01h

02h

E7h

FFh

EAh

Bit 2 = Program Buffer > 64 bytes = 1

Bits 1:0 = Uniform 4-kB erase unavailable = 11b

JEDEC Basic

Flash

Bits 15:8 = Uniform 4-kB erase opcode = not

supported = FFh

Parameter

Dword-1

Bit 23 = Unused = 1b

Bit 22 = Supports Quad Out Read = Yes = 1b

Bit 21 = Supports Quad I/O Read = Yes =1b

Bit 20 = Supports Dual I/O Read = Yes = 1b

Bit19 = Supports DDR 0 = No, 1 = Yes

Bits 18:17 = Number of Address Bytes, 3 or 4 =

01b

Bit 16 = Supports Dual Out Read = Yes = 1b

05h

06h

07h

08h

09h

03h

04h

05h

06h

07h

FFh

3Fh

Bits 31:24 = unused = FFh

JEDEC Basic

Flash

Density in bits, zero based, 1 Gb = 3FFFFFFFh

Parameter

Dword-2

Datasheet

124

002-00466 Rev. *H

2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

Table 63

CFI alternate vendor-specific extended query parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDP Dword

name

relative byte

Data

Description

address offset

Bits 7:5 = number of Quad I/O Mode cycles =

010b

0Ah

0Bh

0Ch

0Dh

08h

09h

0Ah

0Bh

44h

EBh

08h

6Bh

Bits 4:0 = number of Quad I/O Dummy cycles =

00100b for default latency code 00b

JEDEC Basic

Flash

Quad I/O instruction code

Parameter

Dword-3

Bits 23:21 = number of Quad Out Mode cycles

= 000b

Bits 20:16 = number of Quad Out Dummy

cycles = 01000b

Quad Out instruction code

Bits 7:5 = number of Dual Out Mode cycles (not

supported) = 000b

0Eh

0Fh

0Ch

0Dh

00h

FFh

Bits 4:0 = number of Dual Out Dummy cycles

(not supported) = 00000b for default latency

code

Dual Out instruction code (not supported) =

FFh

JEDEC Basic

Flash

Bits 23:21 = number of Dual I/O Mode cycles

(not supported) = 000b for HPLC

Parameter

Dword-4

Bits 20:16 = number of Dual I/O Dummy cycles

(not supported) = 00000b for EHPLC or 00100b

for HPLC Default Latency code = 00b (not

supported)

10h

0Eh

00h

Dual I/O instruction code (not supported) =

FFh

11h

12h

0Fh

10h

FFh

EEh

Bits 7:5 RFU = 111b

Bit 4 = QPI (supported) = No = 0b

Bits 3:1 RFU = 111b

JEDEC Basic

Flash

Bit 0 = Dual All (not supported) = 0b

Parameter

Dword-5

13h

14h

15h

16h

17h

11h

12h

13h

14h

15h

FFh

Bits 15:8 = RFU = FFh

Bits 23:16 = RFU = FFh

Bits 31:24 = RFU = FFh

Bits 7:0 = RFU = FFh

Bits 15:8 = RFU = FFh

JEDEC Basic

Flash

Bits 23:21 = number of Dual All Mode cycles

(not supported) = 000b

Parameter

Dword-6

18h

16h

00h

Bits 20:16 = number of Dual All Dummy cycles

(not supported) = 00000b

19h

1Ah

1Bh

17h

18h

19h

FFh

Dual All instruction code (not supported) = FFh

Bits 7:0 = RFU = FFh

Bits 15:8 = RFU = FFh

JEDEC Basic

Flash

Bits 23:21 = number of QPI cycles (not

supported) = 000b

Parameter

Dword-7

1Ch

1Dh

1Ah

1Bh

00h

FFh

Bits 20:16 = number of QPI Dummy cycles (not

supported) = 00000b

Bits 31:24 (4-4-4) (not supported) = FFh

Datasheet

125

002-00466 Rev. *H

2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

Table 63

CFI alternate vendor-specific extended query parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDP Dword

name

relative byte

Data

Description

address offset

N

Erase type 1 size 2 bytes (not supported) =

1Eh

1Fh

20h

1Ch

1Dh

1Eh

00h

FFh

00h

JEDEC Basic

Flash

Erase type 1 instruction (not supported) = FFh

N

Parameter

Dword-8

Erase type 2 size 2 bytes (not supported) =

00h

21h

22h

23h

1Fh

20h

21h

FFh

13h

D8h

Erase type 2 instruction (not supported) = FFh

N

Erase type 3 size 2 bytes = 512 kB = 13h

JEDEC Basic

Flash

Erase type 3 instruction

N

Erase type 4 size 2 bytes (not supported) =

Parameter

Dword-9

24h

22h

00h

25h

26h

27h

28h

23h

24h

25h

26h

FFh

F2h

FFh

0Fh

Erase type 4 instruction (not supported) = FFh

Bits 31:30 = Erase type 4 Erase, Typical time

units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:

1 s) = RFU = 11b

Bits 29:25 = Erase type 4 Erase, Typical time

count = RFU = 11111b (typical erase time =

(count + 1) * units = RFU)

Bits 24:23 = Erase type 3 Erase, Typical time

units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:

1 s) = 128 ms = 10b

Bits 22:18 = Erase type 3 Erase, Typical time

count = 00011b (typical erase time = (count +

1) * units = 4*128 ms = 512 ms)

Bits 17:16 = Erase type 2 Erase, Typical time

units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:

1 s) = RFU = 11b

JEDEC Basic

Flash

Bits 15:11 = Erase type 2 Erase, Typical time

count = RFU = 11111b (typical erase time =

(count + 1) * units = RFU)

Parameter

Dword-10

29h

27h

FFh

Bits 10:9 = Erase type 1 Erase, Typical time

units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:

1 s) = RFU = 11b

Bits 8:4 = Erase type 1 Erase, Typical time

count = RFU = 11111b (typical erase time =

(count + 1) * units = RFU)

Bits 3:0 = Multiplier from typical erase time to

maximum erase time = 2*(N+1), N=2h = 6x

multiplier Binary Fields:

11-11111-10-00011-11-11111-11-11111-0010

Nibble Format:

1111_1111_0000_1111_1111_1111_1111_001

0 Hex Format: FF_0F_FF_F2

Datasheet

126

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2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

Table 63

CFI alternate vendor-specific extended query parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDP Dword

name

relative byte

Data

Description

address offset

2Ah

2Bh

2Ch

28h

29h

2Ah

A1h

25h

07h

Bit 31 Reserved = 1b

Bits 30:29 = Chip Erase, Typical time units

(00b: 16 ms, 01b: 256 ms,

10b: 4 s, 11b: 64 s) = 4s = 10b

Bits 28:24 = Chip Erase, Typical time count,

(count + 1)*units, count = 11001b, (typical

program time = (count + 1) * units = 26*.4 µs =

104s

Bit 23 = Byte Program Typical time, additional

byte units (0b:1 µs, 1b:8 µs) =

1 µs = 0b

Bits 22:19 = Byte Program Typical time,

additional byte count, (count + 1)*units, count

= 0000b, (typical program time = (count + 1) *

units =

1*1 µs = 1 µs

Bit 18 = Byte Program Typical time, first byte

units (0b:1 µs, 1b:8 µs) =

JEDEC Basic

Flash

8 µs = 1b

Parameter

Dword-11

Bits 17:14 = Byte Program Typical time, first

byte count, (count + 1)*units, count = 1100b,

(typical program time = (count + 1) * units =

13*8 µs = 104 µs

2Dh

2Bh

D9h

Bit 13 = Page Program Typical time units (0b:8

µs, 1b:64 µs) = 64 µs = 1b

Bits 12:8 = Page Program Typical time count,

(count + 1)*units, count = 00101b, (typical

program time = (count + 1) * units = 6*64 µs =

384 µs)

N

Bits 7:4 = Page size 2 , N=9h, = 512B page

Bits 3:0 = Multiplier from typical time to

maximum for Page or Byte program =

2*(N + 1), N=1h = 4x multiplier Binary Fields:

1-10-11001-0-0000-1-1100-1-00101-1001-000

1 Nibble Format:

1101_1001_0000_0111_0010_0101_1001_000

1 Hex Format: D9_07_25_91

Datasheet

127

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

Table 63

CFI alternate vendor-specific extended query parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDP Dword

name

relative byte

Data

Description

address offset

2Eh

2Fh

30h

2Ch

2Dh

2Eh

ECh

83h

18h

Bit 31 = Suspend and Resume supported = 0b

Bits 30:29 = Suspend in-progress erase max

latency units (00b: 128 ns, 01b: 1 µs, 10b: 8 µs,

11b: 64 µs) = 8 µs = 10b

Bits 28:24 = Suspend in-progress erase max

latency count = 00101b, max erase suspend

latency = (count + 1) * units =

6*8 µs = 48 µs

Bits 23:20 = Erase resume to suspend interval

count = 0001b, interval =

(count + 1) * 64 µs = 2 * 64 µs = 128 µs

Bits 19:18 = Suspend in-progress program max

latency units (00b: 128 ns, 01b: 1 µs, 10b: 8 µs,

11b: 64 µs) = 8 µs = 10b

Bits 17:13 = Suspend in-progress program max

latency count = 00100b, max erase suspend

latency = (count + 1) * units = 5*8 µs = 40 µs

Bits 12:9 = Program resume to suspend

interval count = 0001b, interval =

JEDEC Basic

Flash

(count + 1) * 64 µs = 2 * 64 µs = 128 µs

Bit 8 = RFU = 1b

Parameter

Dword-12

Bits 7:4 = Prohibited operations during erase

suspend = xxx0b: May not initiate a new erase

anywhere (erase nesting not permitted) +

xx1xb: May not initiate a page program in the

erase suspended sector size + x1xxb: May not

initiate a read in the erase suspended sector

size + 1xxxb: The erase and program restric-

tions in bits 5:4 are sufficient = 1110b

Bits 3:0 = Prohibited Operations During

Program Suspend = xxx0b: May not initiate a

new erase anywhere (erase nesting not

permitted) + xx0xb: May not initiate a new

page program anywhere (program nesting not

permitted) + x1xxb: May not initiate a read in

the program suspended page size + 1xxxb: The

erase and program restrictions in bits 1:0 are

sufficient = 1100b Binary Fields:

31h

2Fh

45h

0-10-00101-0001-10-00100-0001-1-1110-1100

Nibble Format:

0100_0101_0001_1000_1000_0011_1110_110

0 Hex Format: 45_18_83_EC

32h

33h

34h

35h

30h

31h

32h

33h

8Ah

85h

7Ah

75h

JEDEC Basic

Flash

Bits 31:24 = Erase Suspend Instruction = 75h

Bits 23:16 = Erase Resume Instruction = 7Ah

Bits 15:8 = Program Suspend Instruction = 85h

Bits 7:0 = Program Resume Instruction = 8Ah

Parameter

Dword-13

Datasheet

128

002-00466 Rev. *H

2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

Table 63

CFI alternate vendor-specific extended query parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDP Dword

name

relative byte

Data

Description

address offset

36h

37h

38h

34h

35h

36h

F7h

FFh

Bit 31 = Deep Power Down Supported (not

supported) = 1

Bits 30:23 = Enter Deep Power Down

Instruction (not supported) = FFh

Bits 22:15 = Exit Deep Power Down Instruction

(not supported) = FFh

Bits 14:13 = Exit Deep Power Down to next

operation delay units = (00b: 128 ns, 01b: 1 µs,

10b: 8 µs, 11b: 64 µs) = 64 µs = 11b

Bits 12:8 = Exit Deep Power Down to next

operation delay count = 11111b, Exit Deep

Power Down to next operation delay =

(count+1)*units (not supported)

Bits 7:4 = RFU = Fh

JEDEC Basic

Flash

Parameter

Dword-14

Bits 3:2 = Status Register Polling Device Busy =

01b: Legacy status polling supported = Use

legacy polling by reading the Status Register

with 05h instruction and checking WIP bit[0] (0

= ready; 1=busy).

39h

37h

FFh

Bits 1:0 = RFU = 11b

Binary Fields:

1-11111111-11111111-11-11111-1111-01-11

Nibble Format:

1111_1111_1111_1111_1111_1111_

1111_0111

Hex Format: FF_FF_FF_F7

3Ah

3Bh

3Ch

38h

39h

3Ah

00h

F6h

5Dh

Bits 31:24 = RFU = FFh

Bit 23 = Hold and WP Disable = not supported

= 0b

Bits 22:20 = Quad Enable Requirements =

101b: QE is bit 1 of the Status Register 2. Status

Register 1 is read using Read Status

instruction 05h. Status Register 2 is read using

instruction 35h. QE is set via Write Status

instruction 01h with two data bytes where bit

1 of the second byte is one. It is cleared via

Write Status with two data bytes where bit 1 of

the second byte is zero.

JEDEC Basic

Flash

Parameter

Dword-15

Bits 19:16 0-4-4 Mode Entry Method = xxx1b:

Mode Bits[7:0] = A5h Note: QE must be set

prior to using this mode + x1xxb: Mode

Bits[7:0] = Axh + 1xxxb: RFU = 1101b

Bits 15:10 0-4-4 Mode Exit Method = xx_xxx1b:

Mode Bits[7:0] = 00h will terminate this mode

at the end of the current read operation +

xx_1xxxb: Input Fh (mode bit reset) on

DQ0-DQ3 for 8 clocks. This will terminate the

mode prior to the next read operation. +

x1_xxxxb: Mode Bit[7:0] != Axh + 1x_x1xx: RFU

3Dh

3Bh

FFh

Datasheet

129

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2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

Table 63

CFI alternate vendor-specific extended query parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDP Dword

name

relative byte

Data

Description

address offset

3Eh

3Fh

40h

3Ch

3Dh

3Eh

F0h

28h

FAh

Bits 31:24 = Enter 4-byte Addressing =

xxxx_1xxxb: 8-bit volatile bank register used

to define A[30:A24] bits. MSB (bit[7]) is used to

enable/disable 4-byte address mode. When

MSB is set to ‘1’, 4-byte address mode is active

and A[30:24] bits are don’t care. Read with

instruction 16h. Write instruction is 17h with 1

byte of data. When MSB is cleared to ‘0’, select

the active 128-Mbit segment by setting the

appropriate A[30:24] bits and use 3-byte

addressing. + xx1x_xxxxb: Supports dedicated

4-byte address instruction set. Consult vendor

data sheet for the instruction set definition or

look for 4 byte Address Parameter Table. +

1xxx_xxxxb: Reserved = 10101000b

Bits 23:14 = Exit 4-byte Addressing = xx_xxxx-

_1xxxb: 8-bit volatile bank register used to

define A[30:A24] bits. MSB (bit[7]) is used to

enable/disable 4-byte address mode. When

MSB is cleared to ‘0’, 3-byte address mode is

active and A30:A24 are used to select the

active 128-Mbit memory segment. Read with

instruction 16h. Write instruction is 17h, data

length is 1 byte. + xx_xx1x_xxxxb: Hardware

reset + xx_x1xx_xxxxb: Software reset (see bits

13:8 in this DWORD) + xx_1xxx_xxxxb: Power

cycle + x1_xxxx_xxxxb: Reserved + 1x_xxxx-

_xxxxb: Reserved = 1111101000b

JEDEC Basic

Flash

Parameter

Dword-16

41h

3Fh

A8h

Bits 13:8 = Soft Reset and Rescue Sequence

Support = x0_1xxxb: issue instruction F0h +

1x_xxxxb: exit 0-4-4 mode is required prior to

other reset sequences above if the device may

be operating in this mode. = 101000b

Bit 7 = RFU = 1

Bits 6:0 = Volatile or Nonvolatile Register and

Write Enable Instruction for Status Register 1

= xx1_xxxxb: Status Register 1 contains a mix

of volatile and nonvolatile bits. The 06h

instruction is used to enable writing of the

register. + x1x_xxxxb: Reserved + 1xx_xxxxb:

Reserved = 1110000b

Binary Fields:

10101000-1111101000-101000-1-1110000

Nibble Format:

1010_1000_1111_1010_0010_1000_

1111_0000

Hex Format: A8_FA_28_F0

42h

43h

44h

40h

41h

42h

FFh

00h

Bits 31:24 = RFU = FFh

JEDEC Sector

Map

Bits 23:16 = Region count (Dwords -1) = 00h:

One region

Parameter

Dword-1

Config-0

Header

Bits 15:8 = Configuration ID = 00h: Uniform 256

kB sectors

Bits 7:2 = RFU = 111111b

Bit 1 = Map Descriptor = 1

Bit 0 = The end descriptor = 1

45h

43h

FFh

Datasheet

130

002-00466 Rev. *H

2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

Table 63

CFI alternate vendor-specific extended query parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDP Dword

name

relative byte

Data

Description

address offset

46h

47h

48h

44h

45h

46h

F4h

FFh

Bits 31:8 = Region size = 00FFFFh: Region size

as count-1 of 256 byte units = 64 MB/256 =

256K Count = 262144, value = count -1 =

262144 -1 = 262143 = 3FFFFh

Bits 4:7 = RFU = Fh Erase Type not supported =

0/ supported = 1

JEDEC Sector

Map

Bit 3 = Erase Type 4 support = 0b — Erase Type

4 is not defined

Parameter

Dword-2

Config-0

Region-0

Bit 2 = Erase Type 3 support = 1b — Erase Type

3 is 512 kB erase and is supported in the

512-kB sector region

49h

47h

7Fh

Bit 1 = Erase Type 2 support = 0b — Erase Type

2 is 64 kB erase and is not supported in the

256-kB sector region

Bit 0 = Erase Type 1 support = 0b — Erase Type

1 is 4 kB erase and is not supported in the

256-kB sector region

4Ah

4Bh

4Ch

48h

49h

4Ah

F3h

88h

FFh

Supported = 1, Not Supported = 0

Bits 31:20 = RFU = FFFh

Bit 19 = Support for nonvolatile individual

sector lock write command, Instruction=E3h =

1

Bit 18 = Support for nonvolatile individual

sector lock read command, Instruction=E2h =

1

Bit 17 = Support for volatile individual sector

lock Write command, Instruction=E1h = 1

Bit 16 = Support for volatile individual sector

lock Read command, Instruction=E0h = 1

Bit 15 = Support for (1-4-4) DTR_Read

Command, Instruction = EEh = 1

Bit 14 = Support for (1-2-2) DTR_Read

Command, Instruction = BEh = 1

Bit 13 = Support for (1-1-1) DTR_Read

Command, Instruction = 0Eh = 1

Bit 12 = Support for Erase Command — Type 4

= 0

JEDEC 4 Byte

Address

Bit 11 = Support for Erase Command — Type 3

= 1

Instructions

Parameter

Dword-1

Bit 10 = Support for Erase Command — Type 2

= 0

4Dh

4Bh

FFh

Bit 9 = Support for Erase Command — Type 1

= 0

Bit 8 = Support for (1-4-4) Page Program

Command, Instruction = 3Eh =0

Bit 7 = Support for (1-1-4) Page Program

Command, Instruction = 34h = 1

Bit 6 = Support for (1-1-1) Page Program

Command, Instruction = 12h = 1

Bit 5 = Support for (1-4-4) FAST_READ

Command, Instruction = ECh = 1

Bit 4 = Support for (1-1-4) FAST_READ

Command, Instruction = 6Ch = 1

Bit 3 = Support for (1-2-2) FAST_READ

Command, Instruction = BCh = 1

Bit 2 = Support for (1-1-2) FAST_READ

Command, Instruction = 3Ch = 1

Bit 1 = Support for (1-1-1) FAST_READ

Command, Instruction = 0Ch = 1

Bit 0 = Support for (1-1-1) READ Command,

Instruction = 13h = 1

Datasheet

131

002-00466 Rev. *H

2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

Table 63

CFI alternate vendor-specific extended query parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDP Dword

name

relative byte

Data

Description

address offset

4Eh

4Fh

50h

4Ch

4Dh

4Eh

FFh

DCh

Bits 31:24 = FFh = Instruction for Erase Type 4:

JEDEC 4 Byte

Address

RFU

Bits 23:16 = DCh = Instruction for Erase Type 3

Instructions

Parameter

Dword-2

Bits 15:8 = FFh = Instruction for Erase Type 2:

RFU

Bits 7:0 = FFh = Instruction for Erase Type 1:

RFU

51h

4Fh

FFh

12.3

Device ID and Common Flash Interface (ID-CFI) ASO map — automotive

only

The CFI Primary Vendor-Specific Extended Query is extended to include Electronic Marking information for device

traceability.

Table 64

Device ID and Common Flash Interface (ID-CFI) map automotive only

# of

Data

Example of

actualdata

Address

Data field

Hex read out of example data

bytes

format

(SA) + 0180h Size of Electronic Marking

1

Hex

20

14h

01h

Revision of Electronic

(SA) + 0181h

Marking

1

Hex

1

(SA) + 0182h

(SA) + 018Ah

(SA) + 018Bh

(SA) + 018Ch

(SA) + 018Dh

Fab Lot #

Wafer #

8

1

7

ASCII

Hex

LD87270 4Ch, 44h, 38h, 37h, 32h, 37h, 30h, FFh

23

10

15

17h

0Ah

0Fh

Die X Coordinate

Die Y Coordinate

Class Lot #

Hex

ASCII

BR33150 42h, 52h, 33h, 33h, 31h, 35h, 30h

FFh, FFh, FFh, FFh, FFh, FFh, FFh, FFh,

(SA) + 0194h

Reserved for Future

12

N/A

FFh, FFh, FFh, FFh

Fab Lot # + Wafer # + Die X Coordinate + Die Y Coordinate gives a unique ID for each device.

Datasheet

132

002-00466 Rev. *H

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Software interface reference

12.4

Initial delivery state

The device is shipped from Infineon with nonvolatile bits set as follows:

• The entire memory array is erased: i.e. all bits are set to ‘1’ (each byte contains FFh).

• The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased to FFh.

• The SFDP address space contains the values as defined in the description of the SFDP address space.

• The ID-CFI address space contains the values as defined in the description of the ID-CFI address space.

• The Status Register 1 contains 00h (all SR1 bits are cleared to 0’s).

• The Configuration Register 1 contains 02h.

• The Autoboot register contains 00h.

• The Password Register contains FFFFFFFF-FFFFFFFFh.

• All PPB bits are ‘1’.

• The ASP Register contents are shown here.

Table 65

ASP Register content

Ordering part number model

C1

ASPR default value

FE7Fh

Datasheet

133

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Ordering information

13

Ordering information

The ordering part number is formed by a valid combination of the following:

S79FL 01G

S

DS

B

H

V

C

1

0

Packing type

0 = Tray

3 = 13” Tape and reel

Model number (sector type)

1 = Uniform 512-kB sectors

Model number (latency type, package details, RESET#)

C = EHPLC, 5 x 5 ball BGA footprint with RESET#

Temperature range / grade

I = Industrial (–40°C to +85°C)

V = Industrial Plus (–40°C to +105°C)

A = Automotive, AEC-Q100 grade 3 (–40°C to +85°C)

B = Automotive, AEC-Q100 grade 2 (–40°C to +105°C)

Package materials

H = Low-Halogen, Lead (Pb)-free

Package type

B = 24-ball BGA 6 x 8 mm package, 1.00 mm pitch

Speed

DS = 80 MHz

AG = 133 MHz

Device technology

S = 65 nm MIRRORBIT™ process technology

Density

01G = 1024 Mbit

Device family

S79FL

3.0 V-Only, Dual-Quad serial peripheral interface (SPI) flash memory

Datasheet

134

002-00466 Rev. *H

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Ordering information

13.1

Valid combinations — standard

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales

office to confirm availability of specific valid combinations and to check on newly released combinations.

Table 66

Valid combinations — standard

Base ordering part

number

Speed

option

Package and

temperature

Model

Packing

type

[60]

Package marking

number

79FL01GS + S + (Temp) + H + (Model

Number)

S79FL01GS

DS

BHV

C1

0, 3

13.2

Valid combinations — automotive grade / AEC-Q100

Table 67 lists configurations that are automotive grade / AEC-Q100 qualified and are planned to be available in

volume. The table will be updated as new combinations are released. Contact your local sales representative to

confirm availability of specific combinations and to check on newly released combinations.

Production part approval process (PPAP) support is only provided for AEC-Q100 grade products.

Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade

products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full

compliance with ISO/TS-16949 requirements.

AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require

ISO/TS-16949 compliance.

Table 67

Valid combinations — automotive grade / AEC-Q100

Base

Speed

option

Package and

temperature

Model

Packing

type

orderingpart

number

Package marking

number

S79FL01GS

DS

BHA, BHB

C1

0, 3

79FL01GS + S + (Temp) + H + (Model Number)

Notes

58.EHPLC = Enhanced High Performance Latency Code table.

59.Uniform 512-kB sectors = All sectors are uniform 512-kB with a 1024B programming buffer.

60.Example, S79FL01GSDSBHVC10 package marking would be 79FL01GSSVHC1.

Datasheet

135

002-00466 Rev. *H

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1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Revision history

Document

Date of release

Description of changes

version

**

2014-10-15

Initial release.

Global: Promoted data sheet from Advance Information to Preliminary

Command Set Summary:

S79FL01GS Command Set (sorted by function) table: corrected ‘Maximum

Frequency (MHz)’ for DDRQIOR and 4DDRQIOR

Serial Flash Discoverable Parameters (SFDP) Address Map: Updated

paragraph, updated SFDP Overview Map table

*A

*B

2015-02-04

2016-02-01

Field Definitions: Updated SFDP Header table

Device ID and Common Flash Interface (ID-CFI) Address Map:

Manufacturer and Device ID table: corrected 03h Data

CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend

Commands table: corrected 07h Data

Added table: CFI Alternate Vendor-Specific Extended Query Parameter A5h,

JEDEC SFDP Rev B

Changed maximum value of “SCK Clock Frequency for DDR READ” from

80 MHz to 93 MHz in all instances across the document.

Updated to Cypress template.

Changed maximum value of “SCK Clock Frequency for DDR READ” from

93 MHz to 80 MHz in all instances across the document.

Added Automotive Temperature Range related information in all instances

across the document.

Updated Electrical specifications:

Added Thermal resistance.

Updated Address space maps:

Updated Registers:

Added ECC Status Register (ECCSR).

Updated Commands:

Updated Register Access commands:

Added ECC Status Register Read (ECCRD 18h).

Updated Program Flash Array commands:

Updated Program granularity:

*C

2017-01-05

Added Automatic ECC.

Added Data integrity.

Updated Software interface reference:

Added Device ID and Common Flash Interface (ID-CFI) ASO map —

automotive only.

Updated Ordering information:

Updated Ordering Information S79FL01GS:

Added Automotive Grade Temperature Range related information.

Added Valid combinations — automotive grade / AEC-Q100.

Updated to new template.

Updated Timing specifications:

Updated SDR AC characteristics:

Updated Table 11:

*D

2017-03-22

Changed minimum value of ^t_SUparameter from 3 ns to 1.5 ns.

Updated to new template.

Datasheet

136

002-00466 Rev. *H

2022-07-19

1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V

Revision history

Document

Date of release

Description of changes

version

Replaced “FAB024” with “ZSA024” in all instances across the document.

Updated Address space maps:

Updated Registers:

*E

2017-06-08

Updated Configuration Register 1 (CR1):

Updated details corresponding to Bit 4 (Replaced “RFU” with “DNU”).

Updated PDF properties data.

Updated to new template.

Completing Sunset Review.

*F

2018-01-29

2018-03-21

Updated Timing specifications:

Updated SDR AC characteristics:

Updated Table 11:

*G

Removed typical value of t_CSHparameter.

Added “3000 ns” as maximum value of t_SUparameter.

Updated Document Title to read as “S79FL01GS, 1 Gb (128 MB) Dual-Quad

FL-S Flash SPI Multi-I/O, 3.0 V”.

Updated Overview:

Removed “Glossary”.

Removed “Other resources”.

Updated SPI with multiple input / output (SPI-MIO) dual-quad:

Replaced “Hardware interface” with “SPI with multiple input / output

(SPI-MIO) Dual-Quad” in heading.

Updated Electrical specifications:

Updated Thermal resistance:

*H

2022-07-19

Updated Table 4.

Removed “Software interface”.

Updated Data integrity:

Updated Data retention:

Updated description.

Migrated to Infineon template.

Datasheet

137

002-00466 Rev. *H

2022-07-19

Please read the Important Notice and Warnings at the end of this document

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

For further information on the product, technology,

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”).

Edition 2022-07-19

Published by

delivery terms and conditions and prices please

contact your nearest Infineon Technologies office

(www.infineon.com).

Infineon Technologies AG

81726 Munich, Germany

With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement of

intellectual property rights of any third party.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Except as otherwise explicitly approved by Infineon

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Technologies in

authorized

a written document signed by

Do you have a question about this

document?

Go to www.infineon.com/support

representatives

of

Infineon

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of the

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

Document reference

002-00466 Rev. *H

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.


型号：	S79FL01GSDSBHBC13
厂家：	Infineon
描述：	Dual QSPI Flash
文件：	总138页 (文件大小：2570K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S79FL01GSDSBHBC13 [INFINEON]

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