S27KS0643GABHV020 [INFINEON]
64MBit 1.8 V Industrial (105°C) xSPI (Octal) HYPERRAM Gen 2.0 in 24 FBGA;
| 型号： | S27KS0643GABHV020 |
| 厂家： | 
Infineon |
| 描述： | 64MBit 1.8 V Industrial (105°C) xSPI (Octal) HYPERRAM Gen 2.0 in 24 FBGA |
| 文件： | 总57页 (文件大小：1166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S27KL0643, S27KS0643
64Mb HYPERRAM™ self-refresh DRAM
(PSRAM)
Octal xSPI, 1.8 V/3.0 V
Features
• Interface
- xSPI (Octal) interface
- 1.8 V / 3.0 V interface support
• Single ended clock (CK) - 11 bus signals
• Optional differential clock (CK, CK#) - 12 bus signals
- Chip select (CS#)
- 8-bit data bus (DQ[7:0])
- Hardware reset (RESET#)
- Bidirectional read-write data strobe (RWDS)
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as read data strobe
• Input during write transactions as write data mask
- Optional DDR center-aligned read strobe (DCARS)
• During read transactions RWDS is offset by a second clock, phase shifted from CK
• The phase shifted clock is used to move the RWDS transition edge within the read data eye
• Performance, power, and packages
- 200 MHz maximum clock rate
- DDR - transfers data on both edges of the clock
- Data throughput up to 400 MBps (3,200 Mbps)
- Configurable burst characteristics
• Linear burst
• Wrapped burst lengths:
16 bytes (8 clocks)
32 bytes (16 clocks)
64 bytes (32 clocks)
128 bytes (64 clocks)
• Hybrid option - one wrapped burst followed by linear burst
- Configurable output drive strength
- Power modes
• Hybrid Sleep mode
• Deep power down
- Array refresh
• Partial memory array (1/8, 1/4, 1/2, and so on)
• Full
- Package
• 24-ball FBGA
- Operating temperature range
• Industrial (I): -40°C to +85°C
• Industrial Plus (V): -40°C to +105°C
• Automotive, AEC-Q100 grade 3: -40°C to +85°C
• Automotive, AEC-Q100 grade 2: -40°C to +105°C
• Technology
- 38-nm DRAM
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 57
002-24693 Rev. *E
2022-04-19
64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Performance summary
Performance summary
Read transaction timings
Unit
200 MHz
35 ns
Maximum clock rate at 1.8 V VCC/VCC
Maximum clock rate at 3.0 V VCC/VCC
Q
Q
Maximum access time, (tACC
)
Maximum current consumption
Burst read or write (Linear burst at 200 MHz, 1.8 V)
Burst read or write (Linear burst at 200 MHz, 3.0 V)
Standby (CS# = VCC = 3.6 V, 105 °C)
Deep power down (CS# = VCC = 3.6 V, 105 °C)
Standby (CS# = VCC = 2.0 V, 105 °C)
Unit
25 mA
30 mA
360 µA
15 µA
330 µA
12 µA
Deep power down (CS# = VCC = 2.0 V, 105 °C)
Logic block diagram
CS#
Memory
CK/CK#
RWDS
Control
Y Decoders
Data Latch
I/O
Logic
DQ[7:0]
RESET#
Data Path
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Table of contents
Table of contents
1 General description.......................................................................................................................10
1.1 xSPI (Octal) interface ............................................................................................................................................10
2 Product overview .........................................................................................................................13
2.1 xSPI (Octal) interface ............................................................................................................................................13
3 Signal description.........................................................................................................................14
3.1 Input/Output summary ........................................................................................................................................14
4 xSPI (Octal) transaction details......................................................................................................15
4.1 Command/address/data bit assignments...........................................................................................................16
4.2 RESET ENABLE transaction ..................................................................................................................................17
4.3 RESET transaction.................................................................................................................................................17
4.4 READ ID transaction..............................................................................................................................................18
4.5 DEEP POWER DOWN transaction .........................................................................................................................19
4.6 READ transaction ..................................................................................................................................................20
4.7 WRITE transaction.................................................................................................................................................21
4.8 WRITE ENABLE transaction ..................................................................................................................................21
4.9 WRITE DISABLE transaction .................................................................................................................................22
4.10 READ ANY REGISTER transaction .......................................................................................................................22
4.11 WRITE ANY REGISTER transaction......................................................................................................................23
4.12 Data placement during memory READ/WRITE transactions ............................................................................24
4.13 Data placement during register READ/WRITE transactions..............................................................................25
5 Memory space ..............................................................................................................................26
5.1 xSPI (Octal) interface ............................................................................................................................................26
5.2 Density and row boundaries ................................................................................................................................26
6 Register space access....................................................................................................................27
6.1 xSPI (Octal) interface ............................................................................................................................................27
6.2 Device Identification registers..............................................................................................................................27
6.2.1 Device Configuration registers..........................................................................................................................28
7 Interface states ............................................................................................................................34
8 Power conservation modes............................................................................................................35
8.1 Interface standby..................................................................................................................................................35
8.2 Active clock stop ...................................................................................................................................................35
8.3 Hybrid sleep ..........................................................................................................................................................36
8.4 Deep power down.................................................................................................................................................37
9 Electrical specifications.................................................................................................................38
9.1 Absolute maximum ratings ..................................................................................................................................38
9.1.1 Input signal overshoot.......................................................................................................................................38
9.2 Latch-up characteristics.......................................................................................................................................39
9.3 Operating ranges ..................................................................................................................................................39
9.3.1 Temperature ranges ..........................................................................................................................................39
9.3.2 Power supply voltages.......................................................................................................................................39
9.4 DC characteristics .................................................................................................................................................40
9.4.1 Capacitance characteristics ..............................................................................................................................41
9.5 Power-up initialization .........................................................................................................................................42
9.6 Power down ..........................................................................................................................................................43
9.7 Hardware Reset.....................................................................................................................................................44
9.8 Software Reset ......................................................................................................................................................45
10 Timing specifications ..................................................................................................................46
10.1 Key to switching waveforms...............................................................................................................................46
10.2 AC test conditions ...............................................................................................................................................46
10.3 CLK characteristics .............................................................................................................................................47
10.4 AC characteristics................................................................................................................................................48
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Table of contents
10.4.1 Read transactions ............................................................................................................................................48
10.4.2 Write transactions............................................................................................................................................50
11 Physical interface .......................................................................................................................51
11.1 FBGA 24-ball 5 x 5 array footprint ......................................................................................................................51
11.2 Package diagrams...............................................................................................................................................52
12 DDR center-aligned read strobe (DCARS) functionality ...................................................................53
12.1 xSPI HYPERRAM™ products with DCARS signal descriptions............................................................................53
12.2 HYPERRAM™ products with DCARS — FBGA 24-ball, 5 x 5 Array footprint .......................................................55
12.3 HYPERRAM™ memory with DCARS timing .........................................................................................................55
13 Ordering information ..................................................................................................................57
13.1 Ordering part number.........................................................................................................................................57
13.2 Valid combinations .............................................................................................................................................58
13.3 Valid combinations — Automotive grade / AEC-Q100.......................................................................................59
14 Acronyms ...................................................................................................................................60
15 Document conventions................................................................................................................61
15.1 Units of measure .................................................................................................................................................61
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
General description
1
General description
The Infineon® 64Mb HYPERRAM™ device is a high-speed CMOS, self-refresh DRAM, with xSPI (Octal) interface. The
DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the
refresh operations on the DRAM array when the memory is not being actively read or written by the xSPI interface
master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the
host as though the memory uses static cells that retain data without refresh. Hence, the memory is more
accurately described as Pseudo Static RAM (PSRAM).
Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host
limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The
host must confine the duration of transactions and allow additional initial access latency, at the beginning of a
new transaction, if the memory indicates a refresh operation is needed.
1.1
xSPI (Octal) interface
xSPI (Octal) is a SPI-compatible low signal count, DDR interface supporting eight I/Os. The DDR protocol in xSPI
(Octal) transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on
xSPI (Octal) consists of a series of 16-bit wide, one clock cycle data transfers at the internal RAM array with two
corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are
LV-CMOS compatible. Device are available as 1.8 V VCC/VCCQ or 3.0 V VCC/VCCQ (nominal) for array (VCC) and I/O
buffer (VCCQ) supplies, through different Ordering Part Number (OPN).
Each transaction on xSPI (Octal) must include a command whereas address and data are optional. The transac-
tions are structures as follows:
• Each transaction begins with CS# going LOW and ends with CS# returning HIGH.
• The serial clock (CK) marks the transfer of each bit or group of bits between the host and memory. All transfers
occur on every CK edge (DDR mode).
• Each transaction has a 16-bit command which selects the type of device operation to perform. The 16-bit
command is based on two 8-bit opcodes. The same 8-bit opcode is sent on both edges of the clock.
• A command may be stand-alone or may be followed by address bits to select a memory location in the device
to access data.
• Read transactions require a latency period after the address bits and can be zero to several CK cycles. CK must
continue to toggle during any read transaction latency period. During the command and address parts of a
transaction, the memory can indicate whether an additional latency period is needed for a required refresh time
(tRFH) which is added to the initial latency period; by driving the RWDS signal to the HIGH state.
• Write transactions to registers do not require a latency period.
• Write transactions to the memory array require a latency period after the address bits and can be zero to several
CK cycles. CK must continue to toggle during any write transaction latency period. During the command and
address parts of a transaction, the memory can indicate whether an additional latency period is needed for a
required refresh time (tRFH) which is added to the initial latency period by driving the RWDS signal to the HIGH
state.
• In all transactions, command and address bits are shifted in the device with the most significant bits (MSb) first.
The individual data bits within a data byte are shifted in and out of the device MSb first as well. All data bytes
are transferred with the lowest address byte sent out first.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
General description
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 1
xSPI (Octal) command only transaction (DDR)
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RW DS
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0], Memory drives RW DS)
W rite Data
Figure 2
xSPI (Octal) write with no latency transaction (DDR) (Register writes)[1]
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS acts as Data mask
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drivesDQ[7:0])
Figure 3
xSPI (Octal) write with 1X latency transaction (DDR) (Memory array writes)[2, 3]
Notes
1. Write with no latency transaction is used for register writes only.
2. RWDS driven by the host.
3. Data DinA and DinA+2 are masked.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
General description
CS#
CK#, CK
Latency Count (2X)
RWDS
High: 2X Latency Count
Low: 1X Latency Count
RWDS acts as Data Mask
DQ[7:0]
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drives DQ[7:0])
Figure 4
xSPI (Octal) write with 2X latency transaction (DDR) (Memory array writes)[4, 5]
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutA+3
[7:0]
Command - Address
(Host drives DQ[7:0] andMemory drivesRWDS)
Read Data
(Memorydrives RWDS)
Figure 5
xSPI (Octal) read with 1X latency transaction (DDR) (All reads)[6]
CS#
CK#, CK
Laten
cy Count (2
X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutB+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 6
xSPI (Octal) read with 2X latency transaction (DDR) (All reads)[7]
Notes
4. RWDS driven by HYPERRAM™ during Command & Address cycles for 2X latency and then driven by the host
for data masking.
5. Data DinA and DinA+2 are masked.
6. RWDS is driven by HYPERRAM™ phase aligned with data.
7. RWDS is driven by HYPERRAM™ during Command & Address cycles for 2X latency and then driven again
phase aligned with data.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Product overview
2
Product overview
The 64 Mb HYPERRAM™ device is 1.8 V or 3.0 V array and I/O, synchronous self-refresh Dynamic RAM (DRAM). The
HYPERRAM™ device provides an xSPI (Octal) slave interface to the host system. The xSPI (Octal) interface has an
8-bit (1 byte) wide DDR data bus and use only word-wide (16-bit data) address boundaries. Read transactions
provide 16 bits of data during each clock cycle (8 bits on both clock edges). Write transactions take 16 bits of data
from each clock cycle (8 bits on each clock edge).
RESET#
V
CC
V
Q
CC
CS#
CK
DQ[7:0]
RWDS
CK#
V
SS
V
Q
SS
Figure 7
xSPI (Octal) HYPERRAM™ interface[8]
2.1
xSPI (Octal) interface
Read and write transactions require three clock cycles to define the target row/column address and then an initial
access latency of tACC. During the CA part of a transaction, the memory will indicate whether an additional latency
for a required refresh time (tRFH) is added to the initial latency; by driving the RWDS signal to the HIGH state.
During a read (or write) transaction, after the initial data value has been output (or input), additional data can be
read from (or written to) the row on subsequent clock cycles in either a wrapped or linear sequence. When
configured in linear burst mode, the device will automatically fetch the next sequential row from the memory
array to support a continuous linear burst. Simultaneously accessing the next row in the array while the read or
write data transfer is in progress, allows for a linear sequential burst operation that can provide a sustained data
rate of 400 MBps (1 byte (8 bit data bus) * 2 (data clock edges) * 200 MHz = 400 MBps).
Note
8. CK# is used in Differential Clock mode, but optional.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Signal description
3
Signal description
3.1
Input/Output summary
The xSPI (Octal) HYPERRAM™ signals are shown in Table 1. Active Low signal names have a hash symbol (#) suffix.
Table 1
Symbol
I/O summary[10]
Type
Description
Chip Select. Bus transactions are initiated with a HIGH to LOW transition. Bus
transactions are terminated with a Low to High transition. The master device has
a separate CS# for each slave.
CS#
Master output,
slave input
Differential Clock. Command, address, and data information is output with
respect to the crossing of the CK and CK# signals. Use of differential clock is
optional.
CK, CK#[9]
DQ[7:0]
Single Ended Clock. CK# is not used, only a single ended CK is used.
The clock is not required to be free-running.
Data Input/Output. Command, Address, and Data information is transferred on
these signals during Read and Write transactions.
Read-Write Data Strobe. During the Command/Address portion of all bus
transactions RWDS is a slave output and indicates whether additional initial
latency is required. Slave output during read data transfer, data is edge aligned
with RWDS. Slave input during data transfer in write transactions to function as
a data mask.
Input/output
RWDS
(HIGH = Additional latency, LOW = No additional latency).
Hardware RESET. When LOW, the slave device will self initialize and return to the
Standby state. RWDS and DQ[7:0] are placed into the HIGH-Z state when RESET#
is LOW. The slave RESET# input includes a weak pull-up, if RESET# is left
unconnected it will be pulled up to the HIGH state.
Master output,
slave input,
internal pull-up
RESET#
VCC
Array Power.
V
VSS
CCQ
Input/Output Power.
Array Ground.
Power supply
VSSQ
Input/Output Ground.
Reserved for Future Use. May or may not be connected internally, the signal/ball
No connect location should be left unconnected and unused by PCB routing channel for
future compatibility. The signal/ball may be used by a signal in the future.
RFU
Notes
9. CK# is used in Differential Clock mode, but optional connection. Tie the CK# input pin to either VCCQ or VSS
if not connected to the host controller, but do not leave it floating.
Q
10. Optional DCARS pinout and pin description are outlined in section “DDR center-aligned read strobe
(DCARS) functionality” on page 48.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
4
xSPI (Octal) transaction details
The xSPI (Octal) master begins a transaction by driving CS# LOW while clock is idle. Then the clock begins toggling
while CA words are transferred.
For memory Read and Write transactions, the xSPI (Octal) master then continues clocking for a number of cycles
defined by the latency count setting in configuration register 0 (Register Write transactions do not require any
latency count). The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is
LOW during the CA cycles, one latency count is inserted. If RWDS is HIGH during the CA cycles, an additional
latency count is inserted. Once these latency clocks have been completed the memory starts to simultaneously
transition the RWDS and output the target data.
During the read data transfers, read data is output edge aligned with every transition of RWDS. Data will continue
to be output as long as the host continues to transition the clock while CS# is LOW. Note that burst transactions
should not be so long as to prevent the memory from doing distributed refreshes.
During the write data transfers, write data is center-aligned with the clock edges. The first byte of data in each
word is captured by the memory on the rising edge of CK and the second byte is captured on the falling edge of
CK. RWDS is driven by the host master interface as a data mask. When data is being written and RWDS is HIGH the
byte will be masked and the array will not be altered. When data is being written and RWDS is LOW the data will
be placed into the array. Because the master is driving RWDS during write data transfers, neither the master nor
the HYPERRAM™ device are able to indicate a need for latency within the data transfer portion of a write trans-
action. The acceptable write data burst length setting is also shown in configuration register 0.
Wrapped bursts will continue to wrap within the burst length and linear burst will output data in a sequential
manner across row boundaries. When a linear burst read reaches the last address in the array, continuing the
burst beyond the last address will provide data from the beginning of the address range. Read transfers can be
ended at any time by bringing CS# HIGH when the clock is idle.
The clock is not required to be free-running. The clock may remain idle while CS# is HIGH.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
4.1
Table 2
Command/address/data bit assignments
Command set[11-15]
Address
Latency
Cycles
Data
Command
Code
CA-Data
Prerequisite
(Bytes)
(Bytes)
Software Reset
REST ENABLE
0x66
0x99
8-0-0
8-0-0
0
0
0
0
0
0
RESET
ENABLE
RESET
Identification
READ ID[11]
Power Modes
DEEP POWER DOWN 0xB9
Read Memory Array
0x9F
8-8-8
8-0-0
8-8-8
4 (0x00)
3-7
0
4
0
0
4
READ (DDR)
Write Memory Array
0xEE
0xDE
3-7
1 to
WRITE
ENABLE
WRITE (DDR)
8-8-8
4
3-7
1 to
Write Enable / Disable
WRITE ENABLE
WRITE DISABLE
0x06
0x04
8-0-0
8-0-0
0
0
0
0
0
0
Read Registers
READ ANY REGISTER 0x65
Write Registers
8-8-8
8-8-8
4
4
3-7
0
2
2
WRITE ANY
REGISTER
WRITE
ENABLE
0x71
Notes
11.The two identification registers contents are read together - identification 0 followed by identification 1.
12.Write Enable provides protection against inadvertent changes to memory or register values. It sets the
internal write enable latch (WEL) which allows write transactions to execute afterwards.
13.Write Disable can be used to disable write transactions from execution. It resets the internal write enable
latch (WEL).
14.The WEL latch stays set to ‘1’ at the end of any successful memory write transaction. After a power down /
power up sequence, or a hardware/software reset, WEL latch is cleared to ‘0’.
15.The internal WEL latch is cleared to ‘0’ at the end of any successful register write transaction.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
4.2
RESET ENABLE transaction
The RESET ENABLE transaction is required immediately before a RESET transaction. Any transaction other than
RESET following RESET ENABLE will clear the reset enable condition and prevent a later RESET transaction from
being recognized.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 8
RESET ENABLE transaction (DDR)
4.3
RESET transaction
The RESET transaction immediately following a RESET ENABLE will initiate the software reset process.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 9
RESET transaction (DDR)
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
4.4
READ ID transaction
The READ ID transaction provides read access to device identification registers 0 and 1. The registers contain the
manufacturer’s identification along with device identification. The read data sequence is as follows.
Table 3
READ ID data sequence
Address space
Byte order
Byte position
Word data bit
DQ
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
A
8
Register 0
Big-endian
7
6
5
4
B
A
B
3
2
1
0
15
14
13
12
11
10
9
8
Register 1
Big-endian
7
6
5
4
3
2
1
0
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
IDRG 0
[15:8]
IDRG 0
[7:0]
IDRG 1
[15:8]
IDRG 1
[7:0]
0x00
0x00
0x00
0x00
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 10
READ ID with 1X latency transaction (DDR)[16]
CS#
CK#, CK
Latency Count (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
IDRG 0
[15:8]
IDRG 0
[7:0]
IDRG 1
[15:8]
IDRG 1
[7:0]
0x00
0x00
0x00
0x00
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 11
READ ID with 2X latency transaction (DDR)[17]
4.5
DEEP POWER DOWN transaction
DEEP POWER DOWN transaction brings the device into Deep Power Down state which is the lowest power
consumption state. Writing a ‘0’ to CR0[15] will also bring the device in Deep Power Down State. All register
contents are lost in Deep Power Down State and the device powers-up in its default state.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 12
Notes
DEEP POWER DOWN transaction (DDR)
16. RWDS is driven by HYPERRAM™ phase aligned with data.
17. RWDS is driven by HYPERRAM™ during Command & Address cycles for 2X latency and then is driven again
phase aligned with data.
Datasheet
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xSPI (Octal) transaction details
4.6
READ transaction
The READ transaction reads data from the memory array. It has a latency requirement (dummy cycles) which
allows the device’s internal circuitry enough time to access the addressed memory location. During these latency
cycles, the host can tristate the data bus DQ[7:0].
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 13
READ with 1X latency transaction (DDR)[18]
CS#
CK#, CK
Latency C
ount (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutB+3
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 14
READ with 2X latency transaction (DDR)[19]
Notes
18. RWDS is driven by HYPERRAM™ phase aligned with data.
19. RWDS is driven by HYPERRAM™ during Command & Address cycles for 2X latency and then is driven again
phase aligned with data.
20. RWDS is driven by the host.
21. Data DinA and DinA+2 are masked.
Datasheet
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xSPI (Octal) transaction details
4.7
WRITE transaction
The WRITE transaction writes data to the memory array. It has a latency requirement (dummy cycles) which
allows the device’s internal circuitry enough time to access the addressed memory location. During these latency
cycles, the host can tristate the data bus DQ[7:0].
WRITE ENABLE transaction which sets the WEL latch must be executed before the first WRITE. The WEL latch stays
set to ‘1’ at the end of any successful memory write transaction. It must be reset by WRITE DISABLE transaction
to prevent any inadvertent writes to the memory array.
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS acts as Data mask
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drives DQ[7:0])
Figure 15
WRITE with 1X latency transaction (DDR)22, 23]
CS#
CK#, CK
Latency Count (2X)
RWDS
High: 2X Latency Count
Low: 1X Latency Count
RWDS acts as Data Mask
DQ[7:0]
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drives DQ[7:0])
Figure 16
WRITE with 2X latency transaction (DDR)[22, 23]
4.8
WRITE ENABLE transaction
The WRITE ENABLE transaction must be executed prior to any transaction that modifies data either in the
memory array or the registers.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RW DS
CM D
[7:0]
CM D
[7:0]
DQ[7:0]
Com m and
(Host drives DQ[7:0])
Figure 17
Notes
WRITE ENABLE transaction (DDR)
22. RWDS is driven by HYPERRAM™ during Command and Address cycles for 2X latency and then is driven by the
host for data masking.
23. Data DinA and DinA+2 are masked.
Datasheet
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xSPI (Octal) transaction details
4.9
WRITE DISABLE transaction
The WRITE DISABLE transaction inhibits writing data either in the memory array or the registers.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 18
WRITE DISABLE transaction (DDR)
4.10
READ ANY REGISTER transaction
The READ ANY REGISTER transaction reads all the device registers. It has a latency requirement (dummy cycles)
which allows the device’s internal circuitry enough time to access the addressed register location. During these
latency cycles, the host can tristate the data bus DQ[7:0].
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory Drives RWDS)
Figure 19
READ ANY REGISTER with 1X latency transaction (DDR)[24]
CS#
CK#, CK
RWDS
Latency Count (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 20
Notes
READ ANY REGISTER with 2X latency transaction (DDR)[25]
24. RWDS is driven by HYPERRAM™ phase aligned with data.
25. RWDS is driven by HYPERRAM™ during Command and Address cycles for 2X latency and then driven again
phase aligned with data.
Datasheet
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xSPI (Octal) transaction details
4.11
WRITE ANY REGISTER transaction
The WRITE ANY REGISTER transaction writes to the device registers. It does not have a latency requirement
(dummy cycles).
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0], Memory drives RWDS)
Write Data
Figure 21
xSPI (Octal) Write with no latency transaction (DDR) (Register writes)[26, 27]
Notes
26. Write with no latency transaction is used for register writes only.
27. Data Mask on RWDS is not supported.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
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xSPI (Octal) transaction details
4.12
Data placement during memory READ/WRITE transactions
Data placement during memory Read/Write is dependent upon the host. The device will output data (read) as it
was written in (write). Hence both Big Endian and Little Endian are supported for the memory array.
Table 4
Data placement during memory READ and WRITE
Address Byte
Byte
Word data
bit
DQ
Bit order
space
order position
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
8
Big-
endian
7
6
5
4
B
3
When data is being accessed in memory space:
2
The first byte of each word read or written is the “A” byte and the second is the “B”
byte.
1
The bits of the word within the A and B bytes depend on how the data was written.
If the word lower address bits 7-0 are written in the A byte position and bits 15-8 are
written into the B byte position, or vice versa, they will be read back in the same
order.
0
Memory
7
6
So, memory space can be stored and read in either little-endian or big-endian
order.
5
4
A
3
2
1
0
Little-
endian
15
14
13
12
11
10
9
B
8
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xSPI (Octal) transaction details
4.13
Data placement during register READ/WRITE transactions
Data placement during register Read/Write is Big Endian.
Table 5
Data placement during register READ/WRITE transactions
Address
space
Byte
Byte
Worddata
bit
DQ
Bit order
order position
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
When data is being accessed in register space:
During a Read transaction on the xSPI (Octal) two bytes are transferred on each
clock cycle. The upper order byte A (Word[15:8]) is transferred between the rising
and falling edges of RWDS (edge aligned). The lower order byte B (Word[7:0]) is
transferred between the falling and rising edges of RWDS.
8
Big-
Register
endian
7
During a write, the upper order byte A (Word[15:8]) is transferred on the CK rising
edge and the lower order byte B (Word[7:0]) is transferred on the CK falling edge.
So, register space is always read and written in Big-endian order because
registers have device dependent fixed bit location and meaning definitions.
6
5
4
B
3
2
1
0
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Memory space
5
Memory space
5.1
xSPI (Octal) interface
Table 6
Memory space address map (byte based - 8 bits with least significant bit A(0) always set to ‘0’)
System byte
Unit type
Count
Address bits
Notes
address bits
A22 - A10
A9 - A4
Rows within 64 Mb device
Row
8192 (rows)
1 (row)
22 - 10
9 - 4
–
512 (16-bit word) or 1 KB
16 (byte
addresses)
16 bytes (8 words)
A0 always set to ‘0’
Half-page
A3 - A0
3 - 0
5.2
Density and row boundaries
The DRAM array size (density) of the device can be determined from the total number of system address bits used
for the row and column addresses as indicated by the Row Address Bit Count and Column Address Bit Count fields
in the ID0 register. For example: a 64 Mb HYPERRAM™ device has 10 column address bits and 13 row address bits
for a total of 23 address bits (byte address) = 223 = 8MB (4M words). The 10 column address bits indicate that each
row holds 210 = 512 words = 1KB. The row address bit count indicates there are 8196 rows to be refreshed within
each array refresh interval. The row count is used in calculating the refresh interval.
Datasheet
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Register space access
6
Register space access
6.1
xSPI (Octal) interface
Table 7
Register space address map (Address bit A0 always set to ‘0’)
Registers
Address (Byte addressable)
Identification Registers 0 (ID0[15:0])
Identification Registers 1 (ID1[15:0])
Configuration Registers 0 (ID0[15:0])
Configuration Registers 1 (ID1[15:0])
0x00000000
0x00000002
0x00000004
0x00000006
Die Manufacture Information Register
(Register 0 to Register 17)
0x00000008, 0x0000000A to 0x0000002A
6.2
Device Identification registers
There are two read-only, nonvolatile, word registers, that provide information on the device selected when CS#
is LOW. The device information fields identify:
• Manufacturer
• Type
• Density
- Row address bit count
- Column address bit count
• Refresh Type
Table 8
Identification Register 0 (ID0) bit assignments
Function
Bits
[15:14]
13
Settings (Binary)
Reserved
Reserved
00 - Default
0 - Default
00000 - One row address bit
...
Row address bit
count
[12:8]
11111 - Thirty-two row address bits
...
01100 - 64 Mb - Thirteen row address bits (default)
0000 - One column address bits
...
Column address bit
count
[7:4]
[3:0]
1000 - Nine column address bits (default)
...
1111 - Sixteen column address bits
0000 - Reserved
0001 - Infineon® (default)
0010 to 1111 - Reserved
Manufacturer
Table 9
Identification Register 1 (ID1) bit assignments
Function
Bits
Settings (Binary)
[15:4]
Reserved
0000_0000_0000 (default)
0001 - HYPERRAM™ 2.0
0000, 0010 to 1111 - Reserved
[3:0]
Device type
Datasheet
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Register space access
6.2.1
Device Configuration registers
Configuration Register 0 (CR0)
6.2.1.1
Configuration Register 0 (CR0) is used to define the power state and access protocol operating conditions for the
HYPERRAM™ device. Configurable characteristics include:
• Wrapped burst length (16, 32, 64, or 128 byte aligned and length data group)
• Wrapped burst type
- Legacy wrap (sequential access with wrap around within a selected length and aligned group)
- Hybrid wrap (Legacy wrap once then linear burst at start of the next sequential group)
• Initial latency
• Variable latency
- Whether an array read or write transaction will use fixed or variable latency. If fixed latency is selected the
memory will always indicate a refresh latency and delay the read data transfer accordingly. If variable latency
is selected, latency for a refresh is only added when a refresh is required at the same time a new transaction
is starting.
• Output drive strength
• Deep power down (DPD) mode
Datasheet
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Register space access
Table 10
CR0 bit
Configuration Register 0 (CR0) bit assignments
Function
Settings (Binary)
1 - Normal operation (default). HYPERRAM™ will automatically set this value
to ‘1’ after DPD exit
0 - Writing 0 causes the device to enter Deep Power Down
Deep power down
enable
[15]
000 - 34 (default)
001 - 115
010 - 67
011 - 46
[14:12]
[11:8]
Drive strength
Reserved
100 - 34
101 - 27
110 - 22
111 - 19
1 - Reserved (default)
Reserved for Future Use. When writing this register, these bits should be set
to 1 for future compatibility.
0000 - 5 Clock Latency @ 133 Max frequency
0001 - 6 Clock Latency @ 166 Max frequency
0010 - 7 Clock Latency @ 200 MHz/166 MHz Max frequency (default)
0011 - Reserved
[7:4]
Initial latency
0100 - Reserved
...
1101 - Reserved
1110 - 3 Clock Latency @ 85 Max frequency
1111 - 4 Clock Latency @ 104 Max frequency
0 - Variable Latency - 1 or 2 times Initial Latency depending on RWDS during
[3]
[2]
Fixed latency enable CA cycles.
1 - Fixed 2 times Initial Latency (default)
0: Wrapped burst sequence to follow hybrid burst sequencing
1: Wrapped burst sequence in legacy wrapped burst manner (default)
Hybrid burst enable
Burst length
00 - 128 bytes
01 - 64 bytes
[1:0]
10- 16 bytes
11 - 32 bytes (default)
Wrapped burst
A wrapped burst transaction accesses memory within a group of words aligned on a word boundary matching
the length of the configured group. Wrapped access groups can be configured as 16, 32, 64, or 128 bytes
alignment and length. During wrapped transactions, access starts at the CA selected location within the group,
continues to the end of the configured word group aligned boundary, then wraps around to the beginning
location in the group, then continues back to the starting location. Wrapped bursts are generally used for critical
word first instruction or data cache line fill read accesses.
Hybrid burst
The beginning of a hybrid burst will wrap within the target address wrapped burst group length before continuing
to the next half-page of data beyond the end of the wrap group. Continued access is in linear burst order until the
transfer is ended by returning CS# HIGH. This hybrid of a wrapped burst followed by a linear burst starting at the
beginning of the next burst group, allows multiple sequential address cache lines to be filled in a single access.
The first cache line is filled starting at the critical word. Then the next sequential line in memory can be read in
to the cache while the first line is being processed.
Datasheet
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Octal xSPI, 1.8 V/3.0 V
Register space access
Table 11
Bit
CR0[2] control of wrapped burst sequence
Default value
Setting details
Hybrid Burst Enable
CR0[2] = 0: Wrapped burst sequence to follow hybrid burst sequencing
CR0[2] = 1: Wrapped burst sequence in legacy wrapped burst manner
CR0[2]
1b
Table 12
Example wrapped burst sequences (Addressing)
Start
(bytes)
Burst Wrap boundary
address
(Hex)
Sequence of byte addresses (Hex) of data words
type
02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26, 28,
2A, 2C, 2E, 30, 32, 34, 36, 38, 3A, 3C, 3E, 00
64 Wrap once
then Linear
Hybrid 64
XXXXXX02 (wrap complete, now linear beyond the end of the initial 64 byte wrap
group)
40, 42, 44, 46, 48, 4A, 4C, 4E, 50, 52, ...
2E, 30, 32, 34, 36, 38, 3A, 3C, 3E,
00, 02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26,
XXXXXX2E 28, 2A, 2C, (wrap complete,
64 Wrap once
then Linear
Hybrid 64
now linear beyond the end of the initial 64 byte wrap group)
40, 42, 44, 46, 48, 4A, 4B, 4C, 4D, 4E, 4F, 50, 52, ...
02, 04, 06, 08, 0A, 0C, 0E, 00
16 Wrap once
then Linear
(wrap complete, now linear beyond the end of the initial 16 byte wrap
Hybrid 16
Hybrid 16
Hybrid 32
XXXXXX02
group)
10, 12, 14, 16, 18, 1A, ..
0C, 0E, 00, 02, 04, 06, 08, 0A
16 Wrap once
then Linear
(wrap complete, now linear beyond the end of the initial 16 byte wrap
XXXXXX0C
group)
10, 12, 14, 16, 18, 1A, ...
0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 00, 02, 04, 06, 08
32 Wrap once
then Linear
(wrap complete, now linear beyond the end of the initial 32 byte wrap
XXXXXX0A
group)
20, 22, 24, 26, 28, 2A, ...
02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26, 28,
XXXXXX02
Wrap 64
Wrap 64
64
64
2A, 2C, 2E, 30, 32, 34, 36, 38, 3A, 3C, 3E, 00, ...
2E, 30, 32, 34, 36, 38, 3A, 3C, 3E,
XXXXXX2E 00, 02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26,
28, 2A, 2C, 2E, 30, ….
Wrap 16
Wrap 16
Wrap 32
Linear
16
XXXXXX02 02, 04, 06, 08, 0A, 0C, 0E, 00, ...
16
32
XXXXXX0C 0C, 0E, 00, 02, 04, 06, 08, 0A, ...
XXXXXX0A 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 00, 02, 04, 06, 08, ...
XXXXXX02 02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, ...
Linear Burst
Datasheet
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Register space access
Initial latency
Memory Space read and write transactions or Register Space read transactions require some initial latency to
open the row selected by the CA. This initial latency is tACC. The number of latency clocks needed to satisfy tACC
depends on the clock input frequency can vary from 3 to 7 clocks. The value in CR0[7:4] selects the number of
clocks for initial latency. The default value is 7 clocks, allowing for operation up to a maximum frequency of
200MHz prior to the host system setting a lower initial latency value that may be more optimal for the system.
In the event a distributed refresh is required at the time a Memory Space read or write transaction or Register
Space read transaction begins, the RWDS signal goes High during the CA to indicate that an additional initial
latency is being inserted to allow a refresh operation to complete before opening the selected row.
Register Space write transactions always have zero initial latency. RWDS may be HIGH or LOW during the CA
period. The level of RWDS during the CA period does not affect the placement of register data immediately after
the CA, as there is no initial latency needed to capture the register data. A refresh operation may be performed
in the memory array in parallel with the capture of register data.
Fixed latency
A configuration register option bit CR0[3] is provided to make all Memory Space read and write transactions or
Register Space read transactions require the same initial latency by always driving RWDS HIGH during the CA to
indicate that two initial latency periods are required. This fixed initial latency is independent of any need for a
distributed refresh, it simply provides a fixed (deterministic) initial latency for all of these transaction types. Fixed
latency is the default POR or reset configuration. The system may clear this configuration bit to disable fixed
latency and allow variable initial latency with RWDS driven HIGH only when additional latency for a refresh is
required.
Drive strength
DQ and RWDS signal line loading, length, and impedance vary depending on each system design. Configuration
register bits CR0[14:12] provide a means to adjust the DQ[7:0] and RWDS signal output impedance to customize
the DQ and RWDS signal impedance to the system conditions to minimize high speed signal behaviors such as
overshoot, undershoot, and ringing. The default POR or reset configuration value is 000b to select the mid point
of the available output impedance options.
The impedance values shown are typical for both pull-up and pull-down drivers at typical silicon process condi-
tions, nominal operating voltage (1.8 V or 3.0 V) and 50°C. The impedance values may vary from the typical values
depending on the Process, Voltage, and Temperature (PVT) conditions. Impedance will increase with slower
process, lower voltage, or higher temperature. Impedance will decrease with faster process, higher voltage, or
lower temperature.
Each system design should evaluate the data signal integrity across the operating voltage and temperature
ranges to select the best drive strength settings for the operating conditions.
Deep power down
When the HYPERRAM™ device is not needed for system operation, it may be placed in a very low power consuming
state called Deep Power Down (DPD), by writing 0 to CR0[15]. When CR0[15] is cleared to 0, the device enters the
DPD state within tDPDIN time and all refresh operations stop. The data in RAM is lost, (becomes invalid without
refresh) during DPD state. Exiting DPD requires driving CS# LOW then HIGH, POR, or a reset. Only CS# and RESET#
signals are monitored during DPD mode. For additional details, see “Deep power down” on page 32.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Register space access
6.2.1.2
Configuration Register 1
Configuration Register 1 (CR1) is used to define the refresh array size, refresh rate and hybrid sleep for the
HYPERRAM™ device. Configurable characteristics include:
• Partial Array Refresh
• Hybrid Sleep State
• Refresh Rate
Table 13
CR1 bit
Configuration Register 1 (CR1) bit assignments
Function
Setting (Binary)
FFh - Reserved (default)
Reserved
[15:8]
[7]
These bits should always be set to FFh
1 - Linear Burst (default)
0 - Wrapped Burst
Burst Type
Master Clock Type
Hybrid Sleep
1 - Single Ended - CK (default)
0 - Differential - CK#, CK
[6]
1 - Causes the device to enter Hybrid Sleep State
0 - Normal operation (default)
[5]
000 - Full Array (default)
001 - Bottom 1/2 Array
010 - Bottom 1/4 Array
011 - Bottom 1/8 Array
100 - None
[4:2]
Partial Array Refresh
101 - Top 1/2 Array
110 - Top 1/4 Array
111 - Top 1/8 Array
10 - 1µs tCSM (Industrial Plus temperature range devices)
11 - Reserved
[1:0]
Distributed Refresh Interval
00 - Reserved
01 - 4µs tCSM (Industrial temperature range devices)
Burst type
Two burst types, namely Linear and Wrapped, are supported in xSPI (Octal) mode by HYPERRAM™. CR1[7] selects
which type to use.
Master clock type
Two clock types, namely single ended and differential, are supported. CR1[6] selects which type to use.
Partial array refresh
The partial array refresh configuration restricts the refresh operation in HYPERRAM™ to a portion of the memory
array specified by CR1[5:3]. This reduces the standby current. The default configuration refreshes the whole
array.
Hybrid Sleep (HS)
When the HYPERRAM™ is not needed for system operation but data in the device needs to be retained, it may be
placed in Hybrid Sleep state to save more power. Enter Hybrid Sleep state by writing 0 to CR1[5]. Bringing CS#
LOW will cause the device to exit HS state and set CR1[5] to 1. Also, POR, or a hardware reset will cause the device
to exit Hybrid Sleep state. Note that a POR or a hardware reset disables refresh where the memory core data can
potentially get lost.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Register space access
Distributed refresh interval
The DRAM array requires periodic refresh of all bits in the array. This can be done by the host system by reading
or writing a location in each row within a specified time limit. The read or write access copies a row of bits to an
internal buffer. At the end of the access the bits in the buffer are written back to the row in memory, thereby
recharging (refreshing) the bits in the row of DRAM memory cells.
HYPERRAM™ devices include self-refresh logic that will refresh rows automatically. The automatic refresh of a
row can only be done when the memory is not being actively read or written by the host system. The refresh logic
waits for the end of any active read or write before doing a refresh, if a refresh is needed at that time. If a new read
or write begins before the refresh is completed, the memory will drive RWDS HIGH during the CA period to
indicate that an additional initial latency time is required at the start of the new access in order to allow the
refresh operation to complete before starting the new access.
The required refresh interval for the entire memory array varies with temperature as shown in Table 14. This is
the time within which all rows must be refreshed. Refresh of all rows could be done as a single batch of accesses
at the beginning of each interval, in groups (burst refresh) of several rows at a time, spread throughout each
interval, or as single row refreshes evenly distributed throughout the interval. The self-refresh logic distributes
single row refresh operations throughout the interval so that the memory is not busy doing a burst of refresh
operations for a long period, such that the burst refresh would delay host access for a long period.
Table 14
Array refresh interval per temperature
Array refresh interval
Device temperature (°C)
Array rows
Recommended tCSM (µs)
(ms)
64
85
8192
8192
4
1
105
16
The distributed refresh method requires that the host does not do burst transactions that are so long as to
prevent the memory from doing the distributed refreshes when they are needed. This sets an upper limit on the
length of read and write transactions so that the refresh logic can insert a refresh between transactions. This limit
is called the CS# LOW maximum time (tCSM). The tCSM value is determined by the array refresh interval divided by
the number of rows in the array, then reducing this calculation by half to ensure that a distributed refresh interval
cannot be entirely missed by a maximum length host access starting immediately before a distributed refresh is
needed. Because tCSM is set to half the required distributed refresh interval, any series of maximum length host
accesses that delay refresh operations will catch up on refresh operations at twice the rate required by the refresh
interval divided by the number of rows.
The host system is required to respect the tCSM value by ending each transaction before violating tCSM. This can
be done by host memory controller logic splitting long transactions when reaching the tCSM limit, or by host
system hardware or software not performing a single read or write transaction that would be longer than tCSM
.
As noted in Table 14 the array refresh interval is longer at lower temperatures such that tCSM could be increased
to allow longer transactions. The host system can either use the tCSM value from the table for the maximum
operating temperature or, may determine the current operating temperature from a temperature sensor in the
system in order to set a longer distributed refresh interval.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Interface states
7
Interface states
Table 15 describes the required value of each signal for each interface state.
Table 15 Interface states
Interface state
VCC / VCCQ
CS#
X
CK, CK# DQ7-DQ0
RWDS
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
RESET#
Power-Off
< VLKO
X
X
X
X
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
X
X
L
Power-On (Cold) Reset
Hardware (Warm) Reset
Interface Standby
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
X
X
H
H
Master
CA
VCC /VCCQ min
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
L
L
L
L
T
T
T
T
Y
H
H
H
H
Output Valid
Read Initial Access Latency
(Data bus turn around
period)
Write Initial Access Latency
(RWDS turn around period)
HIGH-Z
HIGH-Z
L
HIGH-Z
Slave Output
Valid
SlaveOutput
Valid
Read Data Transfer
Z or T
Master
Output Valid
X or T
Write Data Transfer with
Initial Latency
Master
VCC / VCCQ min
VCC / VCCQ min
L
L
T
T
H
H
Output Valid
Write data transfer without
Initial Latency[28]
Master
Slave Output
Output Valid L or HIGH-Z
Master or
SlaveOutput
Active Clock Stop[29]
VCC / VCCQ min
L
Idle
Y
H
Valid or
HIGH-Z
Deep Power Down
Hybrid Sleep
VCC / VCCQ min
VCC / VCCQ min
H
H
X or T
X or T
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
H
H
Legend
L = V
IL
H = V
IH
X = Either V or V
IL
IH
Y = Either V or V or V or V
IL
IH
OL
OH
Z = Either V or V
OL
OH
L/H = Rising edge
H/L = Falling edge
T = Toggling during information transfer
Idle = CK is LOW and CK# is HIGH
Valid = All bus signals have stable L or H level
Notes
28. Writes without initial latency (with zero initial latency), do not have a turn around period for RWDS. The
HYPERRAM™ device will always drive RWDS during the CA period to indicate whether extended latency is
required. Since master write data immediately follows the CA period the HYPERRAM™ device may continue
to drive RWDS LOW or may take RWDS to HIGH-Z. The master must not drive RWDS during Writes with zero
latency. Writes with zero latency do not use RWDS as a data mask function. All bytes of write data are written
(full word writes).
29. Active Clock Stop is described in “Active clock stop” on page 30. DPD is described in “Hybrid sleep” on
page 31.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Power conservation modes
8
Power conservation modes
8.1
Interface standby
Standby is the default, low power, state for the interface while the device is not selected by the host for data
transfer (CS# = HIGH). All inputs, and outputs other than CS# and RESET# are ignored in this state.
8.2
Active clock stop
Design Note: Active Clock Stop feature is pending device characterization to determine if it will be supported.
The Active Clock Stop state reduces device interface energy consumption to the ICC6 level during the data transfer
portion of a read or write operation. The device automatically enables this state when clock remains stable for
tACC + 30 ns. While in Active Clock Stop state, read data is latched and always driven onto the data bus. ICC6 shown
in “DC characteristics” on page 35.
Active Clock Stop state helps reduce current consumption when the host system clock has stopped to pause the
data transfer. Even though CS# may be LOW throughout these extended data transfer cycles, the memory device
host interface will go into the Active Clock Stop current level at tACC + 30 ns. This allows the device to transition
into a lower current state if the data transfer is stalled. Active read or write current will resume once the data
transfer is restarted with a toggling clock. The Active Clock Stop state must not be used in violation of the tCSM
limit. CS# must go HIGH before tCSM is violated. Clock can be stopped during any portion of the active transaction
as long as it is in the LOW state. Note that it is recommended to avoid stopping the clock during register access.
CS#
Clock Stopped
CK#, CK
Latency Count (1X)
High: 2XLatencyCount
Low: 1XLatency Count
RWDS
DQ[7:0]
RWDS&Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutB
[7:0]
DoutA+1
[7:0]
DoutB+1
[7:0]
Output Driven
Read Data
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Figure 22
Active clock stop during Read transaction (DDR)[30]
Note
30. RWDS is LOW during the CA cycles. In this Read Transaction there is a single initial latency count for read
data access because, this read transaction does not begin at a time when additional latency is required by
the slave.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Power conservation modes
8.3
Hybrid sleep
In the Hybrid Sleep (HS) state, the current consumption is reduced (IHS). HS state is entered by writing a 0 to
CR1[5]. The device reduces power within tHSIN time. The data in Memory Space and Register Space is retained
during HS state. Bringing CS# LOW will cause the device to exit HS state and set CR1[5] to 1. Also, POR, or a
hardware reset will cause the device to exit Hybrid Sleep state. Note that a POR or a hardware reset disables
refresh where the memory core data can potentially get lost. Returning to Standby state requires tEXITHS time.
Following the exit from HS due to any of these events, the device is in the same state as entering Hybrid Sleep.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RW DS
tHSIN
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
W rite Data
CR0 Value
Enter Hybrid Sleep
tHSIN
Comm and - Address
(Host drives DQ[7:0], M em ory drives RW DS)
HS
Figure 23
Enter HS transaction
CS#
tCSHS
tEXTHS
Figure 24
Table 16
Exit HS transaction
Hybrid sleep timing parameters
Description
Parameter
tHSIN
Min
Max
3
3000
100
Unit
µs
ns
Hybrid sleep CR1[5] = 0 register write to DPD power level
CS# Pulse Width to Exit HS
–
60
–
tCSHS
tEXTHS
CS# Exit Hybrid sleep to Standby wakeup time
µs
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Power conservation modes
8.4
Deep power down
In the Deep Power Down (DPD) state, current consumption is driven to the lowest possible level (IDPD). DPD state
is entered by writing a 0 to CR0[15]. The device reduces power within tDPDIN time and all refresh operations stop.
The data in Memory Space is lost, (becomes invalid without refresh) during DPD state. Driving CS# LOW then HIGH
will cause the device to exit DPD state. Also, POR, or a hardware reset will cause the device to exit DPD state.
Returning to Standby state requires tEXTDPD time. Returning to Standby state following a POR requires tVCS time,
as with any other POR. Following the exit from DPD due to any of these events, the device is in the same state as
following POR.
Note In xSPI (Octal), Deep Power Down transaction or Write Any register transaction can be used to enter DPD.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RW DS
tDPDIN
CMD
[7:0]
CM D
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
W rite Data
CR0 Value
Enter Deep Power Down
tDPDIN
Command - Address
(Host drives DQ[7:0], Memory drives RW DS)
DPD
Figure 25
Enter DPD transaction
CS#
tCSDPD
tEXTDPD
Figure 26
Table 17
Exit DPD transaction
Deep power down timing parameters
Description
Parameter
Min
Max
Unit
Deep Power Down CR0[15] = 0 register write to DPD power
level
tDPDIN
–
3
µs
tCSDPD
tEXTDPD
CS# Pulse Width to Exit DPD
CS# Exit Deep Power Down to Standby wakeup time
200
–
3000
150
ns
µs
Notes
31. For a complete list of supported MCPs, refer to “Ordering information” on page 52.
32. No extra leakage current will be generated will VCCQ DIE_STK[1:0] connections.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9
Electrical specifications
9.1
Absolute maximum ratings
Storage temperature plastic packages
Ambient temperature with power applied
Voltage with respect to ground
-65 °C to +150 °C
-65 °C to +115 °C
All signals[33]
Output short circuit current[34]
-0.5V to +(VCC + 0.5V)
100 mA
VCC, VCC
Q
-0.5V to +4.0V
9.1.1
Input signal overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VCC. During voltage
transitions, inputs or I/Os may negative overshoot VSS to 1.0V or positive overshoot to VCC +1.0V, for periods up
to 20 ns.
VSSQ to VCC
Q
- 1.0V
20 ns
≤
Figure 27
Maximum negative overshoot waveform
≤ 20 ns
VCCQ + 1.0V
VSSQ to VCC
Q
Figure 28
Maximum positive overshoot waveform
Notes
33. Minimum DC voltage on input or I/O signal is -1.0V. During voltage transitions, input or I/O signals may
undershoot VSS to -1.0V for periods of up to 20 ns. See Figure 27. Maximum DC voltage on input or I/O signals
is VCC +1.0V. During voltage transitions, input or I/O signals may overshoot to VCC +1.0V for periods up to 20
ns. See Figure 28.
34. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be
greater than one second.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.2
Table 18
Latch-up characteristics
Latch-up specifications[36]
Description
Min
Max
Unit
V
Input voltage with respect to VSSQ on all input only
connections
-1.0
VCCQ + 1.0
Input voltage with respect to VSSQ on all I/O connections
-1.0
-100
VCCQ + 1.0
+100
VCCQ current
mA
9.3
Operating ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
9.3.1
Temperature ranges
Spec
Parameter
Symbol
Device
Unit
Min
Max
85
Industrial (I)
Industrial Plus (V)
Automotive, AEC-Q100 grade 3 (A)
Automotive, AEC-Q100 grade 2 (B)
105
85
105
Ambient temperature
TA
-40
°C
9.3.2
Power supply voltages
Description
1.8 V VCC power supply
3.0 V VCC power supply
Min
1.7
2.7
Max
2.0
3.6
Unit
V
Notes
35. Stresses above those listed under “Absolute maximum ratings” on page 33 may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of
the device to absolute maximum rating conditions for extended periods may affect device reliability.
36. Excludes power supplies VCC/VCCQ. Test conditions: VCC = VCCQ, one connection at a time tested,
connections not being tested are at VSS
.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.4
DC characteristics
Table 19
DC characteristics (CMOS compatible)
64 Mb
Parameter
Description
Test conditions
Unit
[37]
Min
Typ
Max
Input leakage current
V
V
= V to V ,
IN
CC
SS
CC
I
I
I
I
LI1
LI2
LI3
LI4
3.0 V device Reset signal high only
= V max
CC
2
Input leakage current
V
V
= V to V ,
SS CC
IN
CC
1.8 V device Reset signal high only
= V max
CC
–
µA
Input leakage current
V
V
= V to V ,
SS CC
IN
CC
[38]
3.0 V device Reset signal low only
= V max
CC
15
Input leakage current
V
V
= V to V ,
SS CC
IN
CC
[38]
1.8 V device Reset signal low only
= V max
CC
CS# = V , @200 MHz,
CC
IL
25
28
30
25
28
30
V
= 2.0 V
CS# = V , @166 MHz,
IL
I
I
V
active Read current
15
CC1
CC2
CC
V
= 3.6 V
CC
CS# = VSS, @200 MHz,
= 3.6V
V
CC
mA
CS# = V , @200 MHz,
IL
V
= 2.0 V
CC
CS# = V , @166 MHz,
IL
V
V
active write current
standby current
15
CC
V
= 3.6 V
CC
CS# = V , @200 MHz,
SS
= 3.6V
V
CC
CS# = V , V = 2.0 V
80
90
220
250
CC
IH CC
I
I
CC4I
(-40°C to +85°C)
CS# = V , V = 3.6 V
IH CC
µA
–
V
standby current
CS# = V , V = 2.0 V
80
90
330
360
CC
IH CC
CC4IP
(-40°C to +105°C)
CS# = VI , V = 3.6 V
H CC
CS# = V ,
IH
I
I
I
I
Reset current
RESET# = V ,
5
8
1
8
CC5
IL
V
= V max
CC
CC
CS# = V ,
IL
Active clock stop current
(-40°C to +85°C)
RESET# = V ,
CC6I
CC6IP
CC7
IH
V
= V max
CC
CC
mA
CS# = V ,
IL
Active clock stop current
(-40°C to +105°C)
RESET# = V ,
12
35
IH
V
= V max
CC
CC
CS# = V
IH,
[37]
V
current during power up
V
V
= V max,
CC
CC
CC
CC
= V Q = 2.0 V or 3.6 V
CC
Deep power down current 3.0 V
(-40°C to +85°C)
I
I
I
I
I
CS# = V , V = 3.6 V
12
10
DPD
DPD
DPD
DPD
HS
IH CC
Deep power down current 1.8 V
(-40°C to +85°C)
–
CS# = V , V = 2.0 V
IH CC
Deep power down current 3.0 V
(-40°C to +105°C)
CS# = V , V = 3.6 V
15
µA
IH CC
Deep power down current 1.8 V
(-40°C to +105°C)
CS# = V , V = 2.0 V
12
IH CC
Hybrid Sleep current 3.0 V
(-40°C to +85°C)
CS# = V , V = 3.6 V
35
230
IH CC
Notes
37. Not 100% tested.
38. RESET# LOW initiates exits from DPD state and initiates the draw of ICC5 reset current, making I during Reset# LOW
LI
insignificant.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
Table 19
DC characteristics (CMOS compatible) (Continued)
64 Mb
Parameter
Description
Test conditions
CS# = V , V = 2.0 V
Unit
[37]
Min
Typ
Max
Hybrid Sleep current 1.8 V
(-40°C to +85°C)
I
I
I
25
200
HS
HS
HS
IH CC
Hybrid Sleep current 3.0 V
(-40°C to +105°C)
CS# = V , V = 3.6 V
–
35
25
310
300
µA
IH CC
Hybrid Sleep current 1.8 V
(-40°C to +105°C)
CS# = V , V = 2.0 V
IH CC
V
V
V
V
Input low voltage
Input high voltage
Output low voltage
Output high voltage
-0.15 V Q
0.35 V Q
CC
IL
CC
–
0.70 V Q
1.15 V Q
IH
CC
CC
–
V
I
I
= 100 µA for DQ[7:0]
= 100 µA for DQ[7:0]
0.20
–
OL
OL
V Q-0.20
OH
OH
CC
Notes
37. Not 100% tested.
38. RESET# LOW initiates exits from DPD state and initiates the draw of ICC5 reset current, making I during Reset# LOW
LI
insignificant.
9.4.1
Table 20
Capacitance characteristics
1.8 V capacitive characteristics[39, 40, 41]
64 Mb
Max
3.0
0.25
3.0
Description
Parameter
Unit
Input capacitance (CK, CK#, CS#)
Delta input capacitance (CK, CK#)
Output capacitance (RWDS)
IO capacitance (DQx)
CI
CID
CO
CIO
CIOD
pF
3.0
0.25
IO capacitance Delta (DQx)
Table 21
3.0 V capacitive characteristics[39, 40, 41]
64 Mb
Max
3.0
0.25
3.0
Description
Parameter
Unit
Input capacitance (CK, CK#, CS#)
Delta input capacitance (CK, CK#)
Output capacitance (RWDS)
IO capacitance (DQx)
CI
CID
CO
CIO
CIOD
pF
3.0
0.25
IO capacitance delta (DQx)
Notes
39. These values are guaranteed by design and are tested on a sample basis only.
40. Contact capacitance is measured according to JEP147 procedure for measuring capacitance using a vector
network analyzer. VCC, VCCQ are applied and all other signals (except the signal under test) floating. DQ’s
should be in the high impedance state.
41. Note that the capacitance values for the CK, CK#, RWDS and DQx signals must have similar capacitance
values to allow for signal propagation time matching in the system. The capacitance value for CS# is not as
critical because there are no critical timings between CS# going active (LOW) and data being presented on
the DQs bus.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.5
Power-up initialization
HYPERRAM™ products include an on-chip voltage sensor used to launch the power-up initialization process. VCC
and VCCQ must be applied simultaneously. When the power supply reaches a stable level at or above VCC(min),
the device will require tVCS time to complete its self-initialization process.
The device must not be selected during power-up. CS# must follow the voltage applied on VCCQ until VCC (min) is
reached during power-up, and then CS# must remain high for a further delay of tVCS. A simple pull-up resistor from
VCCQ to Chip Select (CS#) can be used to insure safe and proper power-up.
If RESET# is LOW during power up, the device delays start of the tVCS period until RESET# is HIGH. The tVCS period
is used primarily to perform refresh operations on the DRAM array to initialize it.
When initialization is complete, the device is ready for normal operation.
Vcc_VccQ
VCC Minimum
Device
Access Allowed
tVCS
CS#
RESET#
Figure 29
Power-up with RESET# HIGH
Vcc_VccQ
CS#
VCC Minimum
Device
Access Allowed
tVCS
RESET#
Figure 30
Table 22
Power-up with RESET# LOW
Power up and Reset parameters[42, 43, 44]
Parameter
VCC
Description
1.8 V VCC power supply
Min
1.7
2.7
–
Max
Unit
V
2.0
3.6
VCC
3.0 V VCC power supply
tVCS
VCC and VCCQ minimum and RESET# HIGH to first access
150
µs
Notes
42. Bus transactions (read and write) are not allowed during the power-up reset time (tVCS).
43. VCCQ must be the same voltage as VCC
44. VCC ramp rate may be non-linear.
.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.6
Power down
HYPERRAM™ devices are considered to be powered-off when the array power supply (VCC) drops below the VCC
Lock-Out voltage (VLKO). During a power supply transition down to the VSS level, VCCQ should remain less than or
equal to VCC. At the VLKO level, the HYPERRAM™ device will have lost configuration or array data.
VCC must always be greater than or equal to VCCQ (VCC VCCQ).
During Power-Down or voltage drops below VLKO, the array power supply voltages must also drop below VCC
Reset (VRST) for a Power Down period (tPD) for the part to initialize correctly when the power supply again rises to
VCC minimum (see Figure 31).
If during a voltage drop the VCC stays above VLKO the part will stay initialized and will work correctly when VCC is
again above VCC minimum. If VCC does not go below and remain below VRST for greater than tPD, then there is no
assurance that the POR process will be performed. In this case, a hardware reset will be required ensure the
device is properly initialized.
V
(Max)
(Min)
CC
V
CC
No Device Access Allowed
V
CC
Device Access
Allowed
t
VCS
V
LKO
V
RST
t
PD
Time
Figure 31
Power down or voltage drop
The following section describes HYPERRAM™ device dependent aspects of power down specifications.
Table 23
Symbol
1.8 V power-down voltage and timing[45]
Parameter
Min
1.7
1.5
0.7
50
Max
2.0
–
–
–
Unit
V
VCC
VLKO
VRST
tPD
VCC power supply
VCC lock-out below which re-initialization is required
VCC low voltage needed to ensure initialization will occur
Duration of VCC VRST
µs
Table 24
Symbol
VCC
3.0 V power-down voltage and timing[45]
Parameter
Min
2.7
2.4
0.7
50
Max
3.6
–
–
–
Unit
V
VCC power supply
VLKO
VRST
tPD
VCC lock-out below which re-initialization is required
VCC low voltage needed to ensure initialization will occur
Duration of VCC VRST
µs
Note
45. VCC ramp rate can be non-linear.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.7
Hardware Reset
The RESET# input provides a hardware method of returning the device to the standby state.
During tRPH the device will draw ICC5 current. If RESET# continues to be held LOW beyond tRPH, the device draws
CMOS standby current (ICC4). While RESET# is LOW (during tRP), and during tRPH, bus transactions are not allowed.
A hardware reset will do the following:
• Cause the configuration registers to return to their default values
• Halt self-refresh operation while RESET# is LOW - memory array data is considered as invalid
• Force the device to exit the Hybrid Sleep state
• Force the device to exit the Deep Power Down state
After RESET# returns HIGH, the self-refresh operation will resume. Because self-refresh operation is stopped
during RESET# LOW, and the self-refresh row counter is reset to its default value, some rows may not be refreshed
within the required array refresh interval per Table 14. This may result in the loss of DRAM array data during or
immediately following a hardware reset. The host system should assume DRAM array data is lost after a hardware
reset and reload any required data.
tRP
RESET#
tRH
tRPH
CS#
Figure 32
Table 25
Hardware Reset timing diagram
Power-up and Reset parameters
Description
Parameter
Min
200
400
Max
Unit
tRP
tRH
tRPH
RESET# pulse width
Time between RESET# (HIGH) and CS# (LOW)
RESET# LOW to CS# LOW
–
ns
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.8
Software Reset
The software reset provides a software method of returning the device to the standby state. During tSR the device
will draw ICC5 current.
A software reset will do the following:
• Cause the configuration registers to return to their default values
• Halt self-refresh operation during the software reset process - memory array data is considered as invalid
After software reset finishes, the self-refresh operation will resume. Because self-refresh operation is stopped,
and the self-refresh row counter is reset to its default value, some rows may not be refreshed within the required
array refresh interval per Table 14. This may result in the loss of DRAM array data during or immediately following
a software reset. The host system should assume DRAM array data is lost after a software reset and reload any
required data.
Table 26
Parameter
tSR
Software Reset timing
Description
Min
Max
Unit
Software Reset transaction CS# HIGH to
device in Standby
–
400
ns
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
10
Timing specifications
The following section describes HYPERRAM™ device dependent aspects of timing specifications.
10.1
Key to switching waveforms
Valid_High_or_Low
High_to_Low_Transition
Low_to_High_Transition
Invalid
High_Impedance
10.2
AC test conditions
Device
Under
Test
CL
Figure 33
Table 27
Test setup
Test specification[47]
Parameter
All speeds
15
Unit
pF
Output load capacitance, CL
Minimum input rise and fall slew rates (1.8 V)[46]
Minimum input rise and fall slew rates (3.0 V)[46]
Input pulse levels
1.13
2.06
0.0-VCCQ
V/ns
V
Input timing measurement reference levels
Output timing measurement reference levels
V
CCQ/2
VccQ
Input VccQ / 2
Measurement Level
VccQ / 2 Output
Vss
Figure 34
Notes
Input waveforms and measurement levels[48]
46. All AC timings assume this input slew rate.
47. Input and output timing is referenced to VCCQ/2 or to the crossing of CK/CK#.
48. Input timings for the differential CK/CK# pair are measured from clock crossings.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
10.3
CLK characteristics
t
CK
t
t
CKHP
CKHP
CK#
V
IX (Max)
VCCQ / 2
V
IX (Min)
CK
Figure 35
Table 28
CK period
Clock characteristics
Clock timings[49, 50, 51]
200 MHZ
166 MHZ
Parameter[52, 53]
Symbol
Unit
Min
5
Max
–
Min
Max
–
tCK
6
ns
CK half period - Duty cycle
tCKHP
0.45
0.55
0.45
0.55
tCK
CK half period at frequency
Min = 0.45 tCK Min
Max = 0.55 tCK Min
tCKHP
2.25
2.75
2.7
3.3
ns
Table 29
Clock AC/DC electrical characteristics[54, 55]
Parameter Symbol
Min
Max
Unit
DC input voltage
VIN
VID(DC)
VID(AC)
VIX
-0.3
VCCQ + 0.3
DC input differential voltage
AC input differential voltage
AC differential crossing voltage
VCCQ 0.4
VCCQ 0.6
VCCQ 0.4
VCCQ + 0.6
V
VCCQ 0.6
Notes
49. Clock jitter of ±5% is permitted
50. Minimum Frequency (Maximum tCK) is dependent upon maximum CS# Low time (tCSM), Initial Latency, and
Burst Length.
51. CK and CK# input slew rate must be 1 V/ns (2 V/ns if measured differentially).
52. CK# is only used on the 1.8V device and is shown as a dashed waveform.
53. The 3V device uses a single ended clock input.
54. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
55. The value of VIX is expected to equal VCCQ/2 of the transmitting device and must track variations in the DC
level of VCCQ.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
10.4
AC characteristics
10.4.1
Read transactions
Table 30
HYPERRAM™ specific read timing parameters
200 MHZ
Min Max
166 MHZ
Min Max
Parameter
Symbol
Unit
Chip Select HIGH between transactions - 1.8V
Chip Select HIGH between transactions - 3.0V
HYPERRAM™ Read-Write recovery time - 1.8V
HYPERRAM™ Read-Write recovery time - 3.0V
Chip Select setup to next CK rising edge
Data Strobe valid - 1.8V
t
6
–
6
CSHI
–
t
35
4.0
–
36
3
RWR
–
t
CSS
DSV
5.0
6.5
t
–
12
Data Strobe valid - 3.0V
Input setup - 1.8V
Input setup - 3.0V
t
IS
0.5
0.6
Input hold - 1.8V
Input hold - 3.0V
t
IH
–
–
HYPERRAM™ read initial access time - 1.8V
HYPERRAM™ read initial access time- 3.0V
Clock to DQs LOW Z
t
35
0
36
0
ACC
t
DQLZ
CK transition to DQ valid - 1.8V
CK transition to DQ valid - 3.0V
CK transition to DQ invalid - 1.8V
CK transition to DQ invalid - 3.0V
5.0
6.5
4.2
5.7
5.5
7
4.6
5.6
t
1
1
CKD
ns
0
0.5
0
0.5
t
CKDI
Data valid (tDV min = the lesser of: tCKHP min - tCKD max +
tCKDI max) or tCKHP min - tCKD min + tCKDI min) - 1.8V
Data valid (tDV min = the lesser of: tCKHP min - tCKD max +
tCKDI max) or tCKHP min - tCKD min + tCKDI min) - 3.0V
CK transition to RWDS valid - 1.8V
CK transition to RWDS valid - 3.0V
1.8
1.3
[56, 57]
tDV
1.45
–
–
–
5.0
6.5
5.5
7
tCKDS
1
RWDS transition to DQ valid - 1.8V
RWDS transition to DQ valid - 3.0V
RWDS transition to DQ invalid - 1.8V
RWDS transition to DQ invalid - 3.0V
Chip Select hold after CK falling edge
Chip Select inactive to RWDS HIGH-Z - 1.8V
Chip Select inactive to RWDS HIGH-Z - 3.0V
Chip Select inactive to DQ HIGH-Z - 1.8V
Chip Select inactive to DQ HIGH-Z - 3.0V
t
DSS
-0.4
0
+0.4
-0.45 +0.45
tDSH
t
–
0
–
–
6
7
6
7
CSH
5.0
6.5
5
tDSZ
tOZ
–
6.5
Notes
56. Refer to Figure 38 for data valid timing.
57. The tDV timing calculation is provided for reference only, not to determine the spec limit. The spec limit is
guaranteed by testing.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
Table 30
HYPERRAM™ specific read timing parameters (Continued)
200 MHZ
Min Max
166 MHZ
Min Max
Parameter
Symbol
Unit
ns
Refresh time - 1.8V
Refresh time - 3.0V
t
35
1
–
36
1
–
RFH
CK transition to RWDS LOW @ CA phase @Read - 1.8V
CK transition to RWDS LOW @ CA phase @Read - 3.0V
5.5
7
5.5
7
t
ns
CKDSR
tCSHI
tCSM
CS#
tCSS
tRWR=Read Write Recovery
tCSH
tACC = Access
4 cycle latency
tCSS
CK#, CK
tDSZ
tCKDS
tCKD
tDSV
High: 2X Latency Count
Low: 1X Latency Count
RWDS
tOZ
tDSS
tIS
tIH
tDQLZ
tDSH
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
Dn
A
Dn+1
A
Dn+2
A
Dn+3
A
DQ[7:0]
RWDS and Data
are Edge aligned
Command - Address
Host drives DQ[7:0] and Memory drives RWDS
Memory drives DQ[7:0]
and RWDS
Figure 36
Read timing diagram — No additional latency required
Figure 37
Read timing diagram — With additional latency required
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
CS#
tCKHP
tCSHS tCSS
CK
CK#
tDSZ
tOZ
tCKDS
RWDS
tDSS
tCKD
tCKDI
tDV
tDQLZ
tCKD
tDSH
Dn
A
Dn
B
Dn+1
A
Dn+1
B
DQ[7:0]
Figure 38
Data valid timing[58, 59, 60]
10.4.2
Write transactions
Table 31
Write timing parameters
200 MHz
166 MHz
Max
Parameter
Symbol
Unit
Min
35
35
35
–
Max
Min
36
36
36
–
Read-write recovery time
Access time
tRWR
tACC
tRFH
tCSM
tCSM
tDMV
–
–
–
4
1
–
–
–
–
4
1
–
ns
Refresh time
Chip select maximum low time (85°C)
Chip select maximum low time (105°C)
RWDS data mask valid
–
0
–
0
µs
Figure 39
Notes
Write timing diagram — No additional latency
58. tCKD and tCKDI parameters define the beginning and end position of data valid period.
59. tDSS and tDSH define how early or late DQ may transition relative to RWDS. This is a potential skew between
the CK to DQ delay tCKD and CK to RWDS delay tCKDS
.
60. Since DQ and RWDS are the same output types, the tCKD, and tCKDS values track together (vary by the same
ratio).
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Physical interface
11
Physical interface
11.1
FBGA 24-ball 5 5 array footprint
HYPERRAM™ devices are provided in Fortified Ball Grid Array (FBGA), 1 mm pitch, 24-ball, 5 5 ball array footprint,
with 6 8 mm body.
1
2
3
4
RESET#
Vcc
5
A
B
C
D
E
RFU
RFU
RFU
DQ4
VssQ
RFU
CK
CS#
Vss
CK#
VssQ
VccQ
DQ7
RFU
DQ1
DQ6
RWDS
DQ0
DQ5
DQ2
DQ3
VccQ
Figure 40
24-ball FBGA, 6 8 mm, 5 5 ball footprint, Top view
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Physical interface
11.2
Package diagram
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
DIMENSIONS
SYMBOL
MIN.
-
NOM.
MAX.
1.00
-
A
A1
D
-
-
2. ALL DIMENSIONS ARE IN MILLIMETERS.
0.20
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
8.00 BSC
4.
5.
"e" REPRESENTS THE SOLDER BALL GRID PITCH.
E
6.00 BSC
4.00 BSC
4.00 BSC
5
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D1
E1
MD
ME
N
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
5
24
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.40
b
0.35
0.45
eE
eD
SD
SE
1.00 BSC
1.00 BSC
0.00 BSC
0.00 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION
OR OTHER MEANS.
8.
9.
JEDEC SPECIFICATION NO. REF: N/A
10.
002-15550 *A
Figure 41
Fortified ball grid array 24-ball 6 8 1.0 mm (VAA024)
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) func-
tionality
12
DDR center-aligned read strobe (DCARS) functionality
The HYPERRAM™ device offers an optional feature that enables independent skewing (phase shifting) of the
RWDS signal with respect to the read data outputs. This feature is provided in certain devices, based on the
Ordering Part Number (OPN).
When the DCARS feature is provided, a second differential Phase Shifted Clock input PSC/PSC# is used as the
reference for RWDS edges instead of CK/CK#. The second clock is generally a copy of CK/CK# that is phase shifted
90 degrees to place the RWDS edges centered within the DQ signals valid data window. However, other degrees
of phase shift between CK/CK# and PSC/PSC# may be used to optimize the position of RWDS edges within the DQ
signals valid data window so that RWDS provides the desired amount of data setup and hold time in relation to
RWDS edges.
PSC/PSC# is not used during a write transaction. PSC and PSC# may be driven LOW and HIGH respectively or,
both may be driven LOW during write transactions.
The PSC/PSC# is used in xSPI (Octal) devices. If single-ended mode is selected, then PSC# must be driven LOW
but must not be left floating (leakage concerns).
12.1
xSPI HYPERRAM™ products with DCARS signal descriptions
RESET#
VCC
VCCQ
CS#
CK
DQ[7:0]
RWDS
CK#
PSC
PSC#
VSS
VSSQ
Figure 42
xSPI product with DCARS signal diagram
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) func-
tionality
Table 32
Symbol
Signal description
Type
Description
Chip Select. xSPI transactions are initiated with a HIGH to LOW transition. xSPI
transactions are terminated with a LOW to HIGH transition.
CS#
Differential Clock. Command, address, and data information is output with
respect to the crossing of the CK and CK# signals. Use of differential clock is
optional.
Single Ended Clock. CK# is not used, only a single ended CK is used.
The clock is not required to be free-running.
CK, CK#
Input
Phase Shifted Clock. PSC/PSC# allows independent skewing of the RWDS signal
with respect to the CK/CK# inputs. If the CK/CK# (differential mode) is configured,
then PSC/PSC# are used. Otherwise, only PSC is used (Single Ended).
PSC (and PSC#) may be driven HIGH and LOW respectively or both may be driven
LOW during write transactions.
PSC, PSC#
Read-Write Data Strobe. Data bytes output during read transactions are aligned
with RWDS based on the phase shift from CK, CK# to PSC, PSC#. PSC, PSC# cause
the transitions of RWDS, thus the phase shift from CK, CK# to PSC, PSC# is used to
place RWDS edges within the data valid window. RWDS is an input during write
transactions to function as a data mask. At the beginning of all bus transactions
RWDS is an output and indicates whether additional initial latency count is
required
RWDS
Output
(1 = additional latency count, 0 = no additional latency count).
Input/
Output
Data Input/Output. CA/Data information is transferred on these DQs during Read
and Write transactions.
DQ[7:0]
Hardware RESET. When LOW, the device will self initialize and return to the idle
state. RWDS and DQ[7:0] are placed into the HIGH-Z state when RESET# is LOW.
RESET# includes a weak pull-up, if RESET# is left unconnected it will be pulled up
to the HIGH state.
RESET#
VCC
Input
Array Power.
V
VSS
CCQ
Input/Output Power.
Array Ground.
Power supply
VSSQ
Input/Output Ground.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) func-
tionality
12.2
HYPERRAM™ products with DCARS — FBGA 24-ball, 5 x 5 Array footprint
1
2
3
4
RESET#
Vcc
5
A
B
C
D
E
RFU
PSC
PSC#
DQ4
VssQ
RFU
CK
CS#
Vss
CK#
VssQ
VccQ
DQ7
RFU
DQ1
DQ6
RWDS
DQ0
DQ5
DQ2
DQ3
VccQ
Figure 43
24-ball FBGA, 5 5 ball footprint, Top view
12.3
HYPERRAM™ memory with DCARS timing
The illustrations and parameters shown here are only those needed to define the DCARS feature and show the
relationship between the Phase Shifted Clock, RWDS, and data.
Figure 44
Notes
HYPERRAM™ memory DCARS timing diagram[61, 62, 63]
61. Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new transac-
tion is initiated.
62. The memory drives RWDS during read transactions.
63. This example demonstrates a latency code setting of four clocks and no additional initial latency required.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) func-
tionality
CS#
tCKHP
tCSH
tCSS
CK,CK#
PSC,PSC#
tPSCRWDS
tDSZ
tIS
tIH
RWDS
tCKDI
tCKD
tDQLZ
tDV
tOZ
tCKD
Dn
A
Dn
B
Dn+1
A
Dn+1
B
DQ[7:0]
RWDS and Data are driven by the memory
Figure 45
Table 33
DCARS data valid timing[64, 65, 66, 67]
DCARS read timing
200 MHZ
166 MHZ
Parameter
Symbol
Unit
Min
Max
Min
Max
Input Setup - CK/CK# setup w.r.t
PSC/PSC# (edge to edge)
CK Half Period - Duty cycle
(edge to edge)
tIS
0.5
–
0.6
–
tIH
ns
HYPERRAM™ PSC transition to RWDS
transition
tPSCRWDS
–
5
–
6.5
Time delta between CK to DQ valid and
tPSCRWDS - tCKD
-1.0
+0.5
-1.0
+0.5
PSC to RWDS[68]
Notes
64. Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new
transaction is initiated.
65. This figure shows a closer view of the data transfer portion of Figure 42 in order to more clearly show the
Data Valid period as affected by clock jitter and clock to output delay uncertainty.
66. The delay (phase shift) from CK to PSC is controlled by the xSPI master interface (Host) and is generally
between 40 and 140 degrees in order to place the RWDS edge within the data valid window with sufficient
set-up and hold time of data to RWDS. The requirements for data set-up and hold time to RWDS are
determined by the xSPI master interface design and are not addressed by the xSPI slave timing parameters.
67. The xSPI timing parameters of tCKD, and tCKDI define the beginning and end position of the data valid period.
The tCKD and tCKDI values track together (vary by the same ratio) because RWDS and Data are outputs from
the same device under the same voltage and temperature conditions.
68. Sampled, not 100% tested.
Datasheet
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002-24693 Rev. *E
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Ordering information
13
Ordering information
13.1
Ordering part number
The ordering part number is formed by a valid combination of the following:
S27KS 064
1
DP
B
H
I
02
0
Packing type
0 = Tray
3 = 13” Tape and reel
Model number (Additional ordering options)
02 = Standard 6 x 8 x 1.0 mm package (VAA024)
03 = DDR center-aligned read strobe (DCARS) 6 x 8 x 1.0 mm package (VAA024)
Temperature range / grade
I = Industrial (-40°C to + 85°C)
V = Industrial plus (-40°C to + 105°C)
A = Automotive, AEC-Q100 grade 3 (-40°C to + 85°C)
B = Automotive, AEC-Q100 grade 2 (-40°C to + 105°C)
Package materials
H = Low-Halogen, Lead (Pb)-free
Package type
B = 24-ball FBGA 1.00 mm pitch (5 5 ball footprint)
Speed
GA = 200 MHz
DP = 166 MHz
Device technology
2 = 38-nm DRAM process technology - HYPERBUS™
3 = 38-nm DRAM process technology - Octal
Density
064 = 64 Mb
Device family
S27KS or S70KS Memory 1.8 V-only, HYPERRAM™ Self-refresh DRAM
S27KL or S70KS Memory 3.0 V-only, HYPERRAM™ Self-refresh DRAM
Datasheet
52 of 57
002-24693 Rev. *E
2022-04-19
64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Ordering information
13.2
Valid combinations
The Recommended Combinations table lists configurations planned to be available in volume. Table 34 will be
updated as new combinations are released. Contact your local sales representative to confirm availability of
specific combinations and to check on newly released combinations.
Table 34
Valid combinations — Standard
Package,
Device
family
Model
Packing
type
Ordering part
number
Density Technology Speed
material, and
temperature
Package marking
number
0
3
0
3
0
3
0
3
S27KL0643DPBHI020
S27KL0643DPBHI023
S27KL0643GABHI020
S27KL0643GABHI023
S27KL0643DPBHV020
S27KL0643DPBHV023
S27KL0643GABHV020
S27KL0643GABHV023
DP
GA
7KL0643DPHI02
7KL0643GAHI02
7KL0643DPHV02
7KL0643GAHV02
BHI
02
02
S27KL
064
3
DP
GA
BHV
0
3
0
3
S27KS0643GABHI020
S27KS0643GABHI023
S27KS0643GABHV020
S27KS0643GABHV023
BHI
7KS0643GAHI02
7KS0643GAHV02
S27KS
064
3
GA
02
BHV
13.3
Valid combinations — Automotive grade / AEC-Q100
Table 35 lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in
volume. The table will be updated as new combinations are released. Consult your local sales representative to
confirm availability of specific combinations and to check on newly released combinations.
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade
products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full
compliance with ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require
ISO/TS-16949 compliance.
Table 35
Valid combinations — Automotive grade / AEC-Q100
Package,
Device
family
Model
Packing
Ordering part
number
Density Technology
Speed
material, and
temperature
Package marking
number
type
0
3
0
3
0
3
S27KL0643DPBHA020
S27KL0643DPBHA023
S27KL0643DPBHB020
S27KL0643DPBHB023
S27KL0643GABHB020
S27KL0643GABHB023
DP
DP
GA
BHA
BHB
02
02
7KL0643DPHA02
7KL0643DPHB02
7KL0643GAHB02
S27KL
064
064
3
3
BHA
BHB
BHA
BHB
0
3
0
3
S27KS0643GABHA020
S27KS0643GABHA023
S27KS0643GABHB020
S27KS0643GABHB023
7KS0643GAHA02
7KS0643GAHB02
S27KS
GA
02
Datasheet
53 of 57
002-24693 Rev. *E
2022-04-19
64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Acronyms
14
Acronyms
Table 36
Acronym
CMOS
DCARS
DDR
Acronyms used in this document
Description
complementary metal oxide semiconductor
DDR Center-Aligned Read Strobe
double data rate
DPD
deep power down
DRAM
HS
dynamic RAM
hybrid sleep
MSb
most significant bit
POR
power-on reset
PSRAM
PVT
RWDS
SPI
pseudo static RAM
process, voltage, and temperature
read-write data strobe
serial peripheral interface
expanded serial peripheral interface
xSPI
Datasheet
54 of 57
002-24693 Rev. *E
2022-04-19
64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Document conventions
15
Document conventions
15.1
Table 37
Symbol
°C
Units of measure
Units of measure
Unit of measure
degree Celsius
MHz
µA
µs
mA
mm
ns
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
%
percent
pF
V
picofarad
volt
W
watt
Datasheet
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002-24693 Rev. *E
2022-04-19
64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Revision history
Revision history
Document
Date of release
Description of changes
version
*D
2021-11-25
Changed document status to Final.
Migrated to Infineon template.
Table 19: Fixed typos in ILI1 and ILI2 Max. limits.
Table 30: Updated Min. and Max. values for 166 MHz RWDS transition to DQ
valid and invalid. Add notes to tDV
.
*E
2022-04-19
Added Figure 38 and related notes.
Table 34, Table 35: Updated valid combinations.
Deleted Table 35. Valid combinations - DCARS.
Deleted Table 37. Valid combinations - DCARS automotive grade / AEC-Q100.
Datasheet
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002-24693 Rev. *E
2022-04-19
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
For further information on the product, technology,
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-04-19
Published by
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
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Document reference
002-24693 Rev. *E
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
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