ITD50N04S4L-07 [INFINEON]
车规级MOSFET;
Infineon 
ITD50N04S4L-07
OptiMOSTM-T2 Power-Transistor
Product Summary
VDS
40
7.2
50
V
RDS(on),max
ID
mΩ
A
Features
• Dual N-channel Logic Level Common Drain - Enhancement mode
• AEC qualified
PG-TO252-5
• MSL1 up to 260°C peak reflow
• 175°C operating temperature
• Green Product (RoHS compliant)
• 100% Avalanche tested
Type
Package
Marking
PG-TO252-5-311
ITD50N04S4L-07
4T04L07
Maximum ratings, at T j=25 °C, unless otherwise specified 4)
Value
Parameter
Symbol
Conditions
Unit
Continuous drain current1)
I D
T C=25°C, VGS=10V
50
42
A
T C=100°C, VGS=10V2)
Pulsed drain current2)
I D,pulse
EAS
I AS
T C=25°C
200
45
Avalanche energy, single pulse2)
Avalanche current, single pulse
Gate source voltage
I D=25A
mJ
A
-
50
VGS
Ptot
-
+20/-16
46
V
T C=25°C
Power dissipation
W
°C
T j, T stg
-
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
-
-
-55 ... +175
55/175/56
Rev. 1.0
page 1
2013-06-05
ITD50N04S4L-07
Values
Parameter
Symbol
Conditions
Unit
min.
typ.
max.
Thermal characteristics2), 4)
R thJC
R thJA
Thermal resistance, junction - case
SMD version, device on PCB
-
-
-
-
-
-
-
3.2
62
40
K/W
minimal footprint
6 cm2 cooling area3)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics 4)
V(BR)DSS VGS=0V, I D= 1mA
VGS(th) VDS=VGS, I D=18µA
Drain-source breakdown voltage
Gate threshold voltage
40
-
-
V
1.2
1.7
2.2
VDS=40V, VGS=0V,
T j=25°C
I DSS
Zero gate voltage drain current
-
-
0.01
1
1
µA
V
DS=40V, VGS=0V,
100
T j=125°C2)
I GSS
VGS=20V, VDS=0V
Gate-source leakage current
-
-
-
-
100 nA
R DS(on) VGS=4.5V, I D=25A
Drain-source on-state resistance
9.0
5.9
10.6
7.2
mΩ
V
GS=10 V, I D=50 A
Rev. 1.0
page 2
2013-06-05
ITD50N04S4L-07
Values
Parameter
Symbol
Conditions
Unit
min.
typ.
max.
Dynamic characteristics2), 4)
Input capacitance
C iss
C oss
Crss
-
-
-
-
-
-
-
1911
370
16
2480 pF
480
VGS=0 V, VDS=25 V,
f =1 MHz
Output capacitance
Reverse transfer capacitance
Turn-on delay time
37
t d(on)
5.5
-
-
-
-
ns
5.5
t r
V
DD=30V, VGS=10V,
Rise time
I D=50A, R G=3.5Ω
t d(off)
Turn-off delay time
25.5
19.0
t f
Fall time
Gate Charge Characteristics2), 4)
Gate to source charge
Gate to drain charge
Q gs
-
-
-
-
6.2
2.7
25
8.1
6.3
33
-
nC
Q gd
VDD=32V, I D=50A,
GS=0 to 10V
V
Q g
Gate charge total
Vplateau
Gate plateau voltage
3.2
V
A
Reverse Diode 4)
Diode continous forward current2)
Diode pulse current2)
I S
-
-
-
-
50
T C=25°C
I S,pulse
200
VGS=0V, I F=50A,
T j=25°C
VSD
Diode forward voltage
-
-
-
0.95
34
1.3
V
VR=20V, I F=50A,
diF/dt =100A/µs
Reverse recovery time2)
Reverse recovery charge2)
t rr
-
-
ns
nC
Q rr
29
1) Current is limited by bondwire; with an R thJC = 3.2K/W the chip is able to carry 66A at 25°C.
2) Defined by design. Not subject to production test.
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
4) Per channel
Rev. 1.0
page 3
2013-06-05
ITD50N04S4L-07
1 Power dissipation
2 Drain current
P
tot = f(T C); VGS ≥ 6 V
I D = f(T C); VGS ≥ 6 V
50
50
40
30
20
10
0
40
30
20
10
0
0
50
100
150
200
0
50
100
150
200
TC [°C]
TC [°C]
3 Safe operating area
4 Max. transient thermal impedance, one chip
Z thJC = f(t p)
I D = f(VDS); T C = 25 °C; D = 0
parameter: t p
parameter: D =t p/T
101
1000
100
10
0.5
1 µs
100
10 µs
0.1
0.05
100 µs
10-1
0.01
single pulse
1 ms
10-2
1
0.1
1
10
100
10-6
10-5
10-4
10-3
10-2
10-1
100
tp [s]
VDS [V]
Rev. 1.0
page 4
2013-06-05
ITD50N04S4L-07
5 Typ. output characteristics
I D = f(VDS); T j = 25 °C
parameter: VGS
6 Typ. drain-source on-state resistance
R DS(on) = f(I D); T j = 25 °C
parameter: VGS
200
25
8 V
10 V
23
3.2 V
160
120
80
40
0
21
19
17
15
13
11
9
7.5 V
3.5 V
10 V
4 V
4.5 V
4.5 V
5 V
3.5 V
2.5 V
7
6 V
8 V
10 V
5
0
0
1
2
3
4
25
ID [A]
50
VDS [V]
7 Typ. transfer characteristics
I D = f(VGS); VDS = 6V
parameter: T j
8 Typ. drain-source on-state resistance
R DS(on) = f(T j); I D = 50 A; VGS = 10 V
200
150
100
50
12
10
8
25 °C
175 °C
-55 °C
6
0
4
1.6
2.6
3.6
4.6
5.6
-60
-20
20
60
100
140
180
VGS [V]
Tj [°C]
Rev. 1.0
page 5
2013-06-05
ITD50N04S4L-07
9 Typ. gate threshold voltage
GS(th) = f(T j); VGS = VDS
10 Typ. capacitances
V
C = f(VDS); VGS = 0 V; f = 1 MHz
parameter: I D
104
2.5
Ciss
2
1.5
1
103
Coss
180 µA
18 µA
Crss
102
101
0.5
100
0
0
5
10
15
20
25
30
35
40
-60
-20
20
60
Tj [°C]
100
140
180
VDS [V]
11 Typical forward diode characteristicis
IF = f(VSD
12 Avalanche characteristics
I A S= f(t AV
)
)
parameter: T j
parameter: Tj(start)
103
100
100 °C
150 °C
102
25 °C
10
101
175 °C
25 °C
100
0
1
1
0.2
0.4
0.6
0.8
1
1.2
1.4
10
100
1000
VSD [V]
tAV [µs]
Rev. 1.0
page 6
2013-06-05
ITD50N04S4L-07
13 Avalanche energy
AS = f(T j)
14 Drain-source breakdown voltage
E
VBR(DSS) = f(T j); I D = 1 mA
parameter: I D
44
200
180
160
140
120
100
80
42
40
38
36
12.5 A
60
40
25 A
50 A
20
0
-55
-15
25
65
105
145
25
75
125
175
Tj [°C]
Tj [°C]
15 Typ. gate charge
16 Gate charge waveforms
V
GS = f(Q gate); I D = 50 A pulsed
parameter: VDD
10
9
8
7
6
5
4
3
2
1
V GS
32 V
8 V
Q g
V gs(th)
Q g(th)
Q sw
Q gd
Q gate
Q gs
0
0
20
Qgate [nC]
Rev. 1.0
page 7
2013-06-05
ITD50N04S4L-07
Published by
Infineon Technologies AG
81726 Munich, Germany
©
Infineon Technologies AG 2013
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein, any typical values stated
herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties
of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact
the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the
express written approval of Infineon Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body or to support and/or maintain and sustain and/or protect human life.
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.0
page 8
2013-06-05
ITD50N04S4L-07
Revision History
Version
Date
Changes
Revision 0.1
Revision 1.0
08.04.2011
05.06.2013
Initial target data sheet
Final Datasheet
Rev. 1.0
page 9
2013-06-05
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