IRU1030CT [INFINEON]
3A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR; 3A低压差正可调稳压型号: | IRU1030CT |
厂家: | Infineon |
描述: | 3A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR |
文件: | 总11页 (文件大小:72K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet No. PD94124
IRU1030
3A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
FEATURES
DESCRIPTION
Guaranteed < 1.3V Dropout at Full Load Current
Fast Transient Response
The IRU1030 is a low dropout three-terminal adjustable
regulator with minimum of 3A output current capability.
This product is specifically designed to provide well regu-
lated supply for low voltage IC applications such as
Pentiumä P54Cä , P55Cä as well as GTL+ termina-
tion for Pentium Proä and Klamathä processor appli-
cations. The IRU1030 is also well suited for other pro-
cessors such as Cyrixä , AMD and Power PCä appli-
cations. The IRU1030 is guaranteed to have <1.3V drop-
out at full load current making it ideal to provide well
regulated outputs of 2.5V to 3.3V with 4.75V to 7V input
supply.
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-In Thermal Shutdown
APPLICATIONS
Low Voltage Processor Applications such as:
P54Cä , P55Cä , Cyrix M2ä ,
POWER PCä , AMD
GTL+ Termination
PENTIUM PROä , KLAMATHä
Low Voltage Memory Termination Applications
Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
5V
C1
1500uF
V
IN
3
2
1
V
OUT
3.3V / 3A
R1
IRU1030
121
C2
1500uF
R2
200
Adj
Figure 1 - Typical Application of IRU1030 in a 5V to 3.3V regulator.
Notes:Pentium P54C, P55C, Klamath, Pentium Pro, VRE are trademarks of Intel Corp.Cyrix M2 is trademark of Cyrix Corp.
Power PC is trademark of IBM Corp.
PACKAGE ORDER INFORMATION
TJ (°C)
2-PIN PLASTIC
TO-252 (D-Pak)
IRU1030CD
3-PIN PLASTIC
TO-263 (M)
IRU1030CM
3-PIN PLASTIC
TO-220 (T)
0 To 150
IRU1030CT
Rev. 1.3
08/20/02
www.irf.com
1
IRU1030
ABSOLUTE MAXIMUM RATINGS
Input Voltage (VIN) .................................................... 7V
Power Dissipation ..................................................... Internally Limited
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 150°C
PACKAGE INFORMATION
2-PIN PLASTIC TO-252 (D-Pak)
3-PIN PLASTIC TO-263 (M)
3-PIN PLASTIC TO-220 (T)
FRONT VIEW
FRONT VIEW
FRONT VIEW
Tab is
VOUT
3
3
3
2
1
V
IN
V
IN
VIN
Tab is
VOUT
Tab is
VOUT
2
1
VOUT
VOUT
1
Adj
Adj
Adj
qJA=70°C/W for 0.5" Square pad
qJA=35°C/W for 1" Square pad
qJT=2.7°C/W qJA=60°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over CIN=1µF, COUT=10µF, and TJ=0 to 1508C.
Typical values refer to TJ=258C.
PARAMETER
Reference Voltage
SYM
VREF
TEST CONDITION
Io=10mA, TJ=258C, (VIN-Vo)=1.5V
Io=10mA, (VIN-Vo)=1.5V
MIN
TYP
MAX UNITS
1.238 1.250 1.262
V
1.225 1.250 1.275
Line Regulation
Io=10mA, 1.3V<(VIN-Vo)<7V
VIN=3.3V, VADJ=0, 10mA<Io<3A
0.2
0.4
%
%
Load Regulation (Note 1)
Dropout Voltage (Note 2)
Current Limit
Minimum Load Current (Note 3)
Thermal Regulation
Ripple Rejection
∆VO Note 2, Io=3A
VIN=3.3V, ∆Vo=100mV
1.1
1.3
V
A
mA
%/W
3.1
60
VIN=3.3V, VADJ=0V
5
10
30ms Pulse, VIN-Vo=3V, Io=3A
f=120Hz, Co=25µF Tantalum,
Io=1.5A, VIN-Vo=3V
0.01
0.02
70
dB
Adjust Pin Current
IADJ
Io=10mA, VIN-Vo=1.5V, TJ=258C,
Io=10mA, VIN-Vo=1.5V
55
0.2
120
5
µA
µA
%
Adjust Pin Current Change
Temperature Stability
Long Term Stability
Io=10mA, VIN-Vo=1.5V, TJ=258C
VIN=3.3V, VADJ=0V, Io=10mA
TJ=1258C, 1000Hrs
0.5
0.3
1
%
RMS Output Noise
TJ=258C, 10Hz<f<10KHz
0.003
%VO
Note 1: Low duty cycle pulse testing with Kelvin con- Note 3: Minimum load current is defined as the mini-
nections is required in order to maintain accurate data. mum current required at the output in order for the out-
put voltage to maintain regulation. Typically the resistor
Note 2: Dropout voltage is defined as the minimum dif- dividers are selected such that this current is automati-
ferential voltage between VIN and VOUT required to main- cally maintained.
tain regulation at VOUT. It is measured when the output
voltage drops 1% below its nominal value.
Rev. 1.3
08/20/02
www.irf.com
2
IRU1030
PIN DESCRIPTIONS
PIN # PIN SYMBOL
PIN DESCRIPTION
1
2
Adj
A resistor divider from VOUT to Adj pin to ground sets the output voltage.
VOUT
The output of the regulator. A minimum of 10mF capacitor must be connected from this pin
to ground to insure stability.
3
VIN
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum drop out
voltage during the load transient response. This pin must always be 1.3V higher than VOUT
in order for the device to regulate properly.
BLOCK DIAGRAM
VIN 3
2 VOUT
+
+
1.25V
CURRENT
LIMIT
THERMAL
SHUTDOWN
1 Adj
Figure 2 - Simplified block diagram of the IRU1030.
APPLICATION INFORMATION
Introduction
The IRU1030 adjustable Low Dropout (LDO) regulator is seconds at the processor pins, which translates to an
a three-terminal device which can easily be programmed approximately 300 to 500ns current step at the regula-
with the addition of two external resistors to any volt- tor. In addition, the output voltage tolerances are also
ages within the range of 1.25 to 5.5V. This regulator un- extremely tight and they include the transient response
like the first generation of the three-terminal regulators as part of the specification. For example Intel VREä
such as LM117 that required 3V differential between the specification calls for a total of ±100mV including initial
input and the regulated output, only needs 1.3V differen- tolerance, load regulation and 0 to 4.6A load step.
tial to maintain output regulation. This is a key require-
ment for today’s microprocessors that need typically The IRU1030 is specifically designed to meet the fast
3.3V supply and are often generated from the 5V sup- current transient needs as well as providing an accurate
ply. Another major requirement of these microproces- initial voltage, reducing the overall system cost with the
sors such as the Intel P54Cä is the need to switch the need for fewer output capacitors.
load current from zero to several amps in tens of nano-
Rev. 1.3
08/20/02
www.irf.com
3
IRU1030
Output Voltage Setting
to the load side, the effective resistance between the
The IRU1030 can be programmed to any voltages in the regulator and the load is gained up by the factor of (1+R2/
range of 1.25V to 5.5V with the addition of R1 and R2 R1), or the effective resistance will be RP(eff)=RP×(1+R2/
external resistors according to the following formula:
R1). It is important to note that for high current applica-
tions, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to mini-
mize this effect.
R2
R1
VOUT = VREF× 1+
+IADJ×R2
( )
Where:
PARASITIC LINE
RESISTANCE
VREF = 1.25V Typically
IADJ = 50µA Typically
R1 and R2 as shown in Figure 3:
RP
VIN
VOUT
VIN
IRU1030
VOUT
VIN
VIN
VOUT
Adj
RL
R1
R2
IRU1030
Adj
VREF
R1
R2
IADJ = 50uA
Figure 4 - Schematic showing connection
for best load regulation.
Figure 3 - Typical application of the IRU1030
for programming the output voltage.
Stability
The IRU1030 requires the use of an output capacitor as
The IRU1030 keeps a constant 1.25V between the out- part of the frequency compensation in order to make the
put pin and the adjust pin. By placing a resistor R1 across regulator stable. Typical designs for microprocessor ap-
these two pins a constant current flows through R1, add- plications use standard electrolytic capacitors with a
ing to the IADJ current and into the R2 resistor producing typical ESR in the range of 50 to 100mΩ and an output
a voltage equal to the (1.25/R1)×R2 + IADJ×R2 which capacitance of 500 to 1000µF. Fortunately as the ca-
will be added to the 1.25V to set the output voltage. pacitance increases, the ESR decreases resulting in a
This is summarized in the above equation. Since the fixed RC time constant. The IRU1030 takes advantage
minimum load current requirement of the IRU1030 is of this phenomena in making the overall regulator loop
10mA, R1 is typically selected to be 121Ω resistor so stable. For most applications a minimum of 100µF alu-
that it automatically satisfies the minimum current re- minum electrolytic capacitor such as Sanyo MVGX se-
quirement. Notice that since IADJ is typically in the range ries, Panasonic FA series as well as the Nichicon PL
of 50µA it only adds a small error to the output voltage series insures both stability and good transient response.
and should only be considered when a very precise out-
put voltage setting is required. For example, in a typical Thermal Design
3.3V application where R1=121Ω and R2=200Ω the er- The IRU1030 incorporates an internal thermal shutdown
ror due to IADJ is only 0.3% of the nominal set point.
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
Load Regulation
Since the IRU1030 is only a three-terminal device, it is tures in the range of 1508C, it is recommended that the
not possible to provide true remote sensing of the output selected heat sink be chosen such that during maxi-
voltage at the load. Figure 4 shows that the best load mum continuous load operation the junction tempera-
regulation is achieved when the bottom side of R2 is ture is kept below this number. The example below
connected to the load and the top side of R1 resistor is shows the steps in selecting the proper regulator heat
connected directly to the case or the VOUT pin of the sink for the GTL+ terminator using a separate regulator
regulator and not to the load. In fact, if R1 is connected for each end.
Rev. 1.3
08/20/02
www.irf.com
4
IRU1030
Assuming the following specifications:
Air Flow (LFM)
0
100
Thermalloy 6109PB 6110PB
AAVID
200
300
VIN = 3.3V
VOUT = 1.5V
IOUT(MAX) = 2.7A
TA = 358C
7141
7178
575002 507302 576802B 577102
The steps for selecting a proper heat sink to keep the Note: For further information regarding the above com-
junction temperature below 135°C is given as:
panies and their latest product offerings and application
support contact your local representative or the num-
bers listed below:
1) Calculate the maximum power dissipation using:
PD = IOUT×(VIN - VOUT)
AAVID................PH# (603) 528 3400
Thermalloy..........PH# (214) 243-4321
PD = 2.7×(3.3 - 1.5) = 4.86W
2) Select a package from the regulator data sheet and Designing for Microprocessor Applications
record its junction to case (or tab) thermal resistance. As it was mentioned before the IRU1030 is designed
specifically to provide power for the new generation of
Selecting TO-220 package gives us:
the low voltage processors requiring voltages in the range
of 2.5V to 3.6V generated by stepping down the 5V
supply. These processors demand a fast regulator that
θJC = 2.78C/W
3) Assuming that the heat sink is black anodized, cal- supports their large load current changes. The worst case
culate the maximum heat sink temperature allowed: current step seen by the regulator is anywhere in the
range of 1 to 7A with the slew rate of 300 to 500ns which
Assume, θcs=0.05°C/W (heat-sink-to-case thermal could happen when the processor transitions from “Stop
resistance for black anodized)
Clock” mode to the “Full Active” mode. The load current
step at the processor is actually much faster, in the or-
der of 15 to 20ns, however the decoupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
TS = TJ - PD×(θJC + θCS)
TS = 135 - 4.86×(2.7 + 0.05) = 121.78C
4) With the maximum heat sink temperature calculated levels. Because of this requirement the selection of high
in the previous step, the heat-sink-to-air thermal re- frequency low ESR and low ESL output capacitors is
sistance (θSA) is calculated by first calculating the imperative in the design of these regulator circuits.
temperature rise above the ambient as follows:
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
∆T = TS - TA = 121.7 - 35 = 86.78C
DT=Temperature Rise Above Ambient
∆T 86.7
the ESR of the output capacitor produces an instanta-
neous drop equal to the (DVESR=ESR×DI) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (DVESL
θSA =
=
= 17.88C/W
PD
4.86
5) Next, a heat sink with lower θSA than the one calcu- =L×DI/Dt). The output capacitance effect is a droop in
lated in step 4 must be selected. One way to do this the output voltage proportional to the time it takes for the
is to simply look at the graphs of the “Heat Sink Temp regulator to respond to the change in the current,
Rise Above the Ambient” vs. the “Power Dissipation” (DVc=Dt×DI/C) where Dt is the response time of the
and select a heat sink that results in lower tempera- regulator.
ture rise than the one calculated in the previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
Rev. 1.3
08/20/02
www.irf.com
5
IRU1030
2) With the output capacitance being 1500µF:
∆t × ∆I 2 × 2.7
V ESR
V ESL
∆Vc =
=
= 3.6mV
V C
C
1500
T
Where:
∆t = 2µs is the regulator response time
LOAD
1030plt1-1.0
CURRENT
To set the output DC voltage, we need to select R1 and
R2:
LOAD CURRENT RISE TIME
3) Assuming R1 = 121Ω, 0.5%:
Figure 5 - Typical regulator response to
the fast load current step.
VOUT -1
1.5
-1
R2 =
×R1 =
×121 = 24.2Ω
( VREF ) (1.25 )
An example of a regulator design to meet the Intel
Pentium Pro GTL+ specification is given below.
Select R2 = 24.3Ω, 0.5%
Assume the specification for the processor as shown in
Table 1:
Selecting both R1 and R2 resistors to be 0.5% toler-
ance, results in the least amount of error introduced
by the resistor dividers leaving » ±1.3% error budget
for the IRU1030 reference which is within the initial
accuracy of the device.
Type of
Processor Nominal
Pentium Pro 1.50 V
VOUT
IMAX
Max Allowed
Output Tolerance
±150 mV
2.7 A
Finally, the input capacitor is selected as follows:
Table 1 - GTL+ Specification for Pentium Pro
4) Assuming that the input voltage can drop 150mV be-
fore the main power supply responds, and that the
main power supply response time is » 50µs, then
the minimum input capacitance for a 2.7A load step
is given by:
The first step is to select the voltage step allowed in the
output due to the output capacitor’s ESR:
1) Assuming the regulator’s initial accuracy plus the re-
sistor divider tolerance is » ±30mV (±2% of 1.5V nomi-
nal), then the total step allowed for the ESR and the
ESL, is - 120 mV.
2.7 × 50
CIN =
= 900µF
0.15
The ESR should be less than:
Assuming that the ESL drop is - 10mV, the remain-
ing ESR step will be - 110mV. Therefore the output
capacitor ESR must be:
(VIN - VOUT - ∆V - VDROP)
ESR =
∆I
Where:
110
2.7
ESR ≤
= 40mΩ
VDROP L Input voltage drop allowed in step 4
∆V L Maximum regulator dropout voltage
∆I L Load current step
The Sanyo MVGX series is a good choice to achieve
both price and performance goals. The 6MV1500GX,
1500µF, 6.3V has an ESR of less than 36mΩ typ.
Selecting a single capacitor achieves our design goal.
(3.3 - 1.5 - 1.2 - 0.15)
ESR =
= 0.16Ω
2.7
The next step is to calculate the drop due to the ca- Selecting a single 1500µF the same type as the output
pacitance discharge and make sure that this drop in capacitors exceeds our requirements. However, the same
voltage is less than the selected ESL drop in the input capacitor can also support the second regulator
previous step.
for the other end of termination.
Rev. 1.3
08/20/02
www.irf.com
6
IRU1030
Figure 6 shows the completed schematic for our ex- Layout Consideration
ample.
The output capacitors must be located as close to the
VOUT terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the VOUT pin to the output capacitors to
prevent any high frequency oscillation that may result
due to excessive trace inductance.
VIN
VOUT
3.3V
1.5V
C1
1500uF
C2
1500uF
IRU1030
R1
R3
Adj
121
0.5%
150
0.5%
VREF
R2
R4
24.3
0.5%
75
0.5%
Figure 6 - Final schematic for half of the
GTL+ termination regulator.
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.3
08/20/02
www.irf.com
7
IRU1030
(D) TO-252 Package
2-Pin
K
A
B
C
L
M
N
78
458
D
J
E
O
P
Q
R
G
F
S
H
R1
SYMBOL MIN
MAX
A
B
6.477 6.731
5.004 5.207
0.686 0.838
7.417 8.179
C
D
E
C
L
9.703 10.084
0.635 0.889
2.286 BSC
F
G
H
J
4.521 4.623
∅1.52 ∅1.62
2.184 2.388
0.762 0.864
K
L
M
N
O
P
1.016
1.118
5.969 6.223
1.016
0
1.118
0.102
Q
R
R1
S
0.534 0.686
R0.31 TYP
R0.51 TYP
0.428 0.588
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.3
08/20/02
www.irf.com
8
IRU1030
(M) TO-263 Package
3-Pin
A
E
U
K
S
V
B
M
H
L
P
D
G
N
R
C
C
L
SYMBOL
MIN
MAX
A
B
C
D
E
G
H
K
L
10.05 10.312
8.28
4.31
0.66
1.14
8.763
4.572
0.91
1.40
2.54 REF
14.73 15.75
1.40
0.00
2.49
0.33
1.68
0.254
2.74
M
N
P
R
S
U
V
0.58
2.286 2.794
08
88
2.41
2.67
6.50 REF
7.75 REF
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.3
08/20/02
www.irf.com
9
IRU1030
(T) TO-220 Package
3-Pin
H1
Q
L
b1
e3
e
e1
C
L E
b
R
E-PIN
CP
a (5x)
C1
J1
A
C
L
F
D
SYMBOL
MIN
4.06
38
MAX
A
a
4.83
7.58
b
0.63
1.14
0.38
1.02
1.52
0.56
b1
C1
CP
D
3.71D 3.96D
14.22 15.062
E
9.78
2.29
4.83
1.14
1.14
5.94
2.29
10.54
2.79
5.33
1.40
1.40
6.55
2.92
e
e1
e3
F
H1
J1
L
13.716 14.22
Q
2.62
2.87
6.17
R
5.588
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.3
08/20/02
www.irf.com
10
IRU1030
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
PARTS
PARTS
T & R
DESIG
DESCRIPTION
COUNT
PER TUBE
PER REEL
Orientation
D
M
T
TO-252, (D-Pak)
2
3
3
75
50
50
2500
750
---
Fig A
Fig B
---
TO-263
TO-220
1
1
1
1
1
1
Feed Direction
Figure A
Feed Direction
FigureB
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.3
08/20/02
www.irf.com
11
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