IRS2011S [INFINEON]
EiceDRIVER™ 200 V 高边和低边栅极驱动器 IC：适用于 IGBT 和 MOSFET，可输出1 A 典型拉电流、1 A 典型灌电流，采用8 引脚 SOIC 封装。也提供 8 引脚 PDIP 封装。;
| 型号： | IRS2011S |
| 厂家： | 
Infineon |
| 描述： | EiceDRIVER™ 200 V 高边和低边栅极驱动器 IC：适用于 IGBT 和 MOSFET，可输出1 A 典型拉电流、1 A 典型灌电流，采用8 引脚 SOIC 封装。也提供 8 引脚 PDIP 封装。 栅极驱动 双极性晶体管 光电二极管 驱动器 |
| 文件： | 总22页 (文件大小：1219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRS2011(S)PBF
High and Low Side Driver
Features
Product Summary
Floating channel designed for bootstrap operation
Fully operational to 200V
VOFFSET (max)
IO+/- (typ)
200V
1.0A / 1.0A
10 – 20V
60ns
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 to 20V
Independent low and high side channels
Input logic HIN/LIN active high
Undervoltage lockout for both channels
3.3V and 5V logic compatible
VOUT
ton/off (typ)
Delay Matching (max)
20ns
CMOS Schmitt-triggered inputs with pull-down
Matched propagation delay for both channels
Description
Package Options
The IRS2011 is a high power, high speed power MOSFET
driver with independent high and low side referenced output
channels. Logic inputs are compatible with standard CMOS
or LSTTL output, down to 3.3V logic. The output drivers
feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are
matched to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power
MOSFET in the high side configuration which operates up to
200 volts. Proprietary HVIC and latch immune CMOS
technologies enable ruggedized monolithic construction.
8-Lead PDIP
8-Lead SOIC
Applications
Converters
DC motor drive
Ordering Information
Standard Pack
Base Part Number
Orderable Part Number
Package Type
Form
Quantity
50
IRS2011PBF
IRS2011SPBF
IRS2011SPBF
PDIP8
SO8N
SO8N
Tube
Tube
IRS2011PBF
95
IRS2011SPBF
IRS2011STRPBF
Tape and Reel
2500
1
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Typical Connection Diagram
(Refer to Lead Assignments for correct configuration.) This diagram shows electrical connections only. Please refer to our Application Notes
and Design Tips for proper circuit board layout.
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
VB
Definition
Min.
-0.3
VB - 20
VS - 0.3
-0.3
-0.3
-0.3
—
Max.
220†
Units
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
VS
VB + 0.3
VB + 0.3
20†
VHO
V
VCC
VLO
VIN
VCC + 0.3
VCC + 0.3
50
Logic input voltage (HIN, LIN)
Allowable offset supply voltage transient
dVs/dt
V/ns
W
8-Lead PDIP
—
1.0
Package power dissipation
@ TA ≤ +25°C
PD
8-Lead SOIC
8-Lead PDIP
8-Lead SOIC
—
0.625
125
—
Thermal resistance, junction to
ambient
RthJA
°C/W
°C
—
200
TJ
TS
TL
Junction temperature
Storage temperature
—
150
-55
150
Lead temperature (soldering, 10 seconds)
—
300
†
All supplies are fully tested at 25V and an internal 20V clamp exists for each supply
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The VS and COM offset
ratings are tested with all supplies biased at 15V differential.
Symbol
Definition
Min.
Max.
VS + 20
200
Units
VB
VS
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
VS + 10
††
VHO
VCC
VLO
VIN
VS
VB
V
10
0
20
VCC
VCC
125
COM
-40
Logic input voltage (HIN, LIN)
Ambient temperature
TA
°C
†† Logic operational for VS of -5 to +200V. Logic state held for VS of -5V to -VBS
.
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, CL = 1000pF and TA = 25°C unless otherwise specified. Figure 1 shows the timing
definitions.
Symbol Definition
Min.
—
Typ. Max. Units
Test Conditions
VS = 0V
ton
toff
tr
Turn-on propagation delay
60
60
25
15
80
80
40
35
Turn-off propagation delay
Turn-on rise time
—
VS = 200V
—
tf
Turn-off fall time
—
ns
Turn-on delay matching
| ton (H) - ton (L) |
Turn-off delay matching
| toff (H) - toff (L) |
DM1
DM2
—
—
—
—
20
20
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
COM and are applicable to all logic input leads: HIN and LIN. The VO and IO parameters are referenced to COM
and are applicable to the respective output leads: HO or LO.
Symbol Definition
Min.
2.5
—
Typ. Max. Units
Test Conditions
VIH
VIL
Logic “1” input voltage
—
—
—
0.7
1.4
0.1
50
VCC = 10V – 20V
Logic “0” input voltage
V
VOH
VOL
ILK
High level output voltage, VBIAS - VO
Low level output voltage, VO
Offset supply leakage current
Quiescent VBS supply current
Quiescent VCC supply current
Logic “1” input bias current
Logic “0” input bias current
—
—
IO = 0A
IO = 20mA
—
—
—
—
VB = VS = 200V
IQBS
IQCC
IIN+
IIN-
—
120
200
3
210
300
10
VIN = 0V or 3.3V
—
μA
—
VIN = 3.3V
VIN = 0V
—
—
5
VBS supply undervoltage positive
going threshold
VBSUV+
VBSUV-
VCCUV+
VCCUV-
IO+
8.3
7.5
8.3
7.5
—
9.0
8.2
9.0
8.2
1.0
1.0
9.7
8.9
9.7
8.9
—
VBS supply undervoltage negative
going threshold
V
A
VCC supply undervoltage positive
going threshold
VCC supply undervoltage negative
going threshold
Output high short circuit pulsed
current
VO = 0V,
PW ≤ 10 μs
Output low short circuit pulsed
current
VO = 15V
IO-
—
—
PW ≤ 10 μs
4
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Functional Block Diagram
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Lead Definitions
Symbol Description
HIN
LIN
VB
Logic input for high side gate driver outputs (HO), in phase
Logic input for low side gate driver outputs (LO), in phase
High side floating supply
HO
VS
High side gate drive output
High side floating supply return
Low side supply
VCC
LO
Low side gate drive output
Low side return
COM
Lead Assignments
8-Lead PDIP
8-Lead SOIC
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Application Information and Additional Details
’
Figure 1. Timing Diagram
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 2A. Turn-on Propagation Delay vs.
Temperature
Figure 2B. Turn-on Propagation Delay vs. Supply
Voltage
Figure 3A. Turn-off Propagation Delay vs.
Temperature
Figure 3B. Turn-off Propagation Delay vs. Supply
Voltage
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 4A. Turn-on Rise Time vs. Temperature
Figure 4B. Turn-on Rise Time vs. Supply Voltage
Figure 5A. Turn-off Fall Time vs. Temperature
Figure 5B. Turn-off Fall Time vs. Supply Voltage
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 6A. Turn-on Delay Matching Time vs.
Temperature
Figure 6B. Turn-on Delay Matching Time vs. Supply
Voltage
Figure 7A Turn-off Delay Matching Time vs.
Temperature
Figure 7B. Turn-off Delay Matching Time vs. Supply
Voltage
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 8A. Logic “1” Input Voltage vs. Temperature
Figure 8B. Logic “1” Input Voltage vs. Supply
Voltage
Figure 9A. Logic “0” Input Voltage vs. Temperature
Figure 9B. Logic “0” Input Voltage vs. Supply
Voltage
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 10A. High Level Output Voltage vs.
Temperature (IO = 0mA)
Figure 10B. High Level Output Voltage vs. Supply
Voltage (IO = 0mA)
Figure 11A. Low Level Output Voltage vs.
Temperature
Figure 11B. Low Level Output vs. Supply Voltage
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 12A. Offset Supply Leakage Current vs.
Temperature
Figure 12B. Offset Supply Leakage Current vs.
Supply Voltage
Figure 13A. VBS Supply Current vs. Temperature
Figure 13B. VBS Supply Current vs. Supply Voltage
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 14A. VCC Supply Current vs. Temperature
Figure 14B. VCC Supply Current vs. Supply Voltage
Figure 15A. Logic “1” Input Current vs.
Figure 15 B. Logic “1” Input Current vs. Supply
Temperature
Voltage
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 16A. Logic “0” Input Bias Current vs.
Figure 16B. Logic “0” Input Bias Current vs.
Temperature
Voltage
Figure 17. VCC and VBS Undervoltage Threshold (+)
vs. Temperature
Figure 18. VCC and VBS Undervoltage Threshold (-)
vs. Temperature
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 19A. Output Source Current vs. Temperature
Figure 19B. Output Source Current vs. Supply
Voltage
Figure 20A. Output Sink Current vs. Temperature
Figure 20B. Output Sink Currnt vs. Supply Voltage
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 21. Maximum VS Negative Offset
vs. VBS Floating Supply Voltage
Figure 22. IRS2011S vs. Frequency (IRFBC20)
Figure 23. IRS2011S vs. Frequency (IRFB30)
Rgate = 33Ω, VCC = 12v
Rgate = 22Ω, VCC = 12V
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Figure 24. IRS2011S vs. Frequency (IRFBC40)
Figure 25. IRS2011S vs. Frequency (IRFB23N15D)
Rgate = 15Ω, VCC = 12V
Rgate = 10Ω, VCC = 12V
Figure 26. IRS2011S vs. Frequency (IRFB4212)
Rgate = 10Ω, VCC = 12V
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Package Details
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Tape and Reel Details
LOADED TAPE FEED DIRECTION
B
A
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 8SOICN
Metric Imperial
Code
A
B
C
D
E
F
G
H
Min
7.90
3.90
11.70
5.45
6.30
5.10
1.50
1.50
Max
8.10
4.10
12.30
5.55
6.50
5.30
n/a
Min
Max
0.318
0.161
0.484
0.218
0.255
0.208
n/a
0.311
0.153
0.46
0.214
0.248
0.200
0.059
0.059
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
329.60
20.95
12.80
1.95
98.00
n/a
14.50
12.40
Max
330.25
21.45
13.20
2.45
102.00
18.40
17.10
14.40
Min
12.976
0.824
0.503
0.767
3.858
n/a
Max
13.001
0.844
0.519
0.096
4.015
0.724
0.673
0.566
0.570
0.488
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Part Marking Information
Part number
Date code
IRxxxxx
YWW ?
IR logo
Pin 1
Identifier
? XXXX
Lot Code
(Prod mode –
4 digit SPN code)
?
MARKING CODE
P
Lead Free Released
Non-Lead Free Released
Assembly site code
Per SCOP 200-002
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Qualification Information†
Industrial††
(per JEDEC JESD 47)
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
MSL2†††
Qualification Level
Moisture Sensitivity Level
RoHS Compliant
8-Lead SOIC
(per IPC/JEDEC J-STD-020)
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
†† Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of
other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any
patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This
document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
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© 2015 International Rectifier
October 28, 2015
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