IRPS5401M_技术文档

IRPS5401 PMIC Datasheet

IRPS5401 PMIC

Flexible Power Management Unit

Features



Full power system including 5 integrated outputs

4A, 4A, 2A and 2A Switching Regulators

500mA Source/Sink Linear regulator

Single rail operation 5.5V to 12V

Output Range from 0.25V to 5.1V for outputs A-D and 0.5V to 3.6V for LDO

Allows combining outputs and/or the use of an external IR MOSFET™ Power Stage to increase output

current to as high as 50A



Emulated current mode control without external compensation

Differential voltage sensing on Switcher A for higher accuracy

I2C / PMBus with integrated level shifter

Advanced Sequencing control

Extensive PMBus command set of 74 commands

Integrated current sensing and full telemetry including voltage, current, temperature and faults

Rated for -40°C to +125°C T_Joperation

Pb-Free, RoHS6, 7x7mm, 56-pin, 0.4mm pitch QFN

Potential applications



High density ASIC, FPGA & CPU multi-rail systems

Embedded Computing systems

Communications and Storage systems

Description

The IRPS5401 is a complete power management unit delivering up to 5 output voltages to processors, FPGA’s

and other multi-rail power systems. Four high efficiency configurable switching regulators and a Source/Sink

Linear regulator provide the typical rails required such as core voltage, memory voltage and I/O voltages.

Integrated, accurate current, voltage and temperature sensing allows telemetry and fault reporting through the

I2C/PMBus.

The IRPS5401 switching regulators utilize fixed frequency emulated current mode control, and thus no external

compensation is required.

The IRPS5401 is highly flexible. Switchers A and B deliver 2A each. Switchers C and D, deliver 4A each and can

also be combined to deliver 8A. Further, Switcher A can be configured to use an external IR MOSFET™ Power

Stage to deliver up to 50A or more.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Table of contents

Features ........................................................................................................................................ 1

Potential applications..................................................................................................................... 1

Description .................................................................................................................................... 1

Table of contents............................................................................................................................ 2

1

2

3

4

5

6

7

8

Ordering Information ............................................................................................................. 4

Application Circuit.................................................................................................................. 6

Pinout Diagram...................................................................................................................... 7

Pin Function .......................................................................................................................... 8

Block Diagram ......................................................................................................................11

Absolute Maximum Ratings ....................................................................................................12

Electrical Specifications.........................................................................................................13

Typical Application Diagrams .................................................................................................20

9

9.1

9.2

9.3

9.4

9.5

9.6

9.7

Description...........................................................................................................................24

One-time Programmable (OTP) Memory .............................................................................................24

MTP pin (pin 54).....................................................................................................................................24

Device Power-up and Initialization.......................................................................................................25

Addressing the IRPS5401 ......................................................................................................................26

Switching Frequency.............................................................................................................................27

Synchronizing to an External Clock......................................................................................................28

Switcher A in External Powerstage Mode.............................................................................................28

Digital Controller & PWM.......................................................................................................................29

Diode Emulation / Discontinuous Mode Operation/AOT.....................................................................30

Output Voltage Sensing, Telemetry and Faults ...................................................................................30

Output Over Voltage Protection (OVP) .................................................................................................31

Output Under Voltage Protection (UVP)...............................................................................................32

Current Sensing, Telemetry and Faults ................................................................................................33

Over-current Protection (OCP) .............................................................................................................34

Input Voltage Sensing, Telemetry and Faults ......................................................................................35

Die Temperature Sensing, Telemetry and Faults.................................................................................36

Power Sequencing and Global Faults...................................................................................................36

Sleep ......................................................................................................................................................38

Combined Switcher C and D Operation................................................................................................38

Linear Regulator....................................................................................................................................38

LDO Monitoring and Faults ...................................................................................................................39

Output Voltage Reporting, Output Overvoltage Protection and Undervoltage Protection...............39

Input Voltage Reporting, Input UVLO and Input Overvoltage Protection...........................................39

Over Current Protection........................................................................................................................39

I2C Security............................................................................................................................................40

Password Protection.............................................................................................................................41

Pin Protection........................................................................................................................................41

9.8

9.9

9.10

9.11

9.12

9.13

9.14

9.15

9.16

9.17

9.18

9.19

9.20

9.21

9.22

9.23

9.24

9.25

9.26

9.27

10

Layout Guidelines .................................................................................................................43

10.1

Sample layout........................................................................................................................................44

11

11.1

Typical Performance .............................................................................................................47

Typical thermal performance at max output power............................................................................48

12

PMBUS Commands ................................................................................................................49

Datasheet

2 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Table of contents

13

Marking Information .............................................................................................................55

14

Package Information .............................................................................................................56

PCB Pad Size..........................................................................................................................................57

PCB Pad Spacing ...................................................................................................................................58

Solder Paste Stencil Pad Size................................................................................................................59

Solder Paste Stencil Pad Spacing.........................................................................................................60

14.1

14.2

14.3

14.4

15

Environmental Qualifications .................................................................................................61

Datasheet

3 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Ordering Information

1

Ordering Information

Table 1

Ordering Information

Package type

Base part

number

Standard pack Orderable part number

Description

IRPS5401M QFN 7 mm x 7 mm Tape and Reel IRPS5401MTRPBF

IRPS5401M QFN 7 mm x 7 mm Tape and Reel IRPS5401MXI03TRP

Unprogrammed

Pre-programmed per

Table 2

IRPS5401M QFN 7 mm x 7 mm Tape and Reel IRPS5401MXI04TRPXUMA1

Pre-programmed per

Table 3

Table 2

Config

IRPS5401MXI03TRP Loop Configurations

R_MTP

A (bold =

B

C

D

LDO

R_ADDR external PS)

(supplied from)

1

8.87kΩ

10kΩ

1.8V/0.5A

1.2V/1.2A

1.8V/0.5A

0.85V/16A

0.85V/25A

3.3V/1.4A

0.72V/9A

0.72V/15A

1.8V/1A

1.8V/1.4A

0.85V/0.6A

5V/1.5A

0.85V/0.6A

3.3V/1.5A

3.3V/3.3A

1.8V/1A

0.85V/3.7A

0.85V/4A

0.85V/2A

1.8V/4A

1.2V (B)

2

1.8V (C)

3

11kΩ

1.8V (C)

4

2.32kΩ

2.87kΩ

3.48kΩ

4.12kΩ

4.75kΩ

5.49kΩ

6.19kΩ

6.98kΩ

7.87kΩ

1.2V/1.5A

1.8V/1A

1.2V (D or external)

0.85V (A)

5

1.8V/1A

1.8V/4A

6

0.9V/3A

1.2V/3A

7

3.3V/2A

0.85V/7A

1.8V/4A

1.2V (B)

8

3.3V/2A

1.2V (B)

9

1.2V/1.5A

1.2V/1.2A

2.5V/1.5A

1.2V/2A

1.8V/2A

1.8V (D)

10

11

12

0.9V/2A

1.8V/2.5A

0.85V/4A

0.85V (C)

0.72V/9A

0.72V/20A

1.2V (D or external)

Datasheet

4 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Ordering Information

Table 3

Config

IRPS5401MXI04TRPAUMA1 Loop Configurations

R_MTP

A (bold =

B

C

D

LDO

R_ADDR external PS)

(supplied from)

1

2

3

Not

used

Not

used

Not

used

0.85V/ 15A

3.3V/10A

1.8V/2A

0.9V/0.5A

(external 2.5V)

4

5

2.32kΩ

1.2V/5A

5V/2.1A

1.13V/1A

1.8V/3A

2.87kΩ

0.85V/0.5A (external

2.5V)

0.85V/15A

3.3V/10A

1.8V/2A

2.5V/2A

3.3V/0.5A (optional)

6

7

3.48kΩ

4.12kΩ

0.85V/7A

1.2V/6A

0.85V/0.5A

(external 2.5V)

1.2V/6A

2.5V/0.5A

1.8V/5A

1.8V/0.5A

(external 2.5V)

8

4.75kΩ

Datasheet

5 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Application Circuit

2

Application Circuit

6-12V

BOOT_A

BOOT_C

VOUT_C

VOUT_A

VOUT_B

PHASE_A

BOOT_B

PHASE_C

2A

4A

BOOT_D

VOUT_D

PHASE_B

1.8V

PHASE_D

VIN_LDO

4A

1.2V to 5.5V

5V

500mA

VO_LDO

VDDIO

SLEEP#

PG

5

1.8V – 5V

ALERT#

CLK

I2C /

PMBus

EN

SYNC_IN

DATA

ADDR_PROT

MTP

GND

Figure 1

IRPS5401 Basic application circuit

Figure 2

System efficiency with VO= 2.5V, FSW=800kHz, Tj=45°C

Datasheet

6 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Pinout Diagram

3

Pinout Diagram

56

55

54

53

52

51

50

49

48

47

46

45

44

43

EN_A

FB_A

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

VIN_D

RTN_A

VIN_A

3

4

BOOT_D

BOOT_A

5

6

PHASE_D

PHASE_A

PHASE_B

IRPS5401

56 Pin7x7 Pin QFN

0.4 mm Pitch

7

8

9

PHASE_C

BOOT_C

BOOT_B

VIN_B

10

11

12

13

14

FB_B

PG_B

VIN_C

57 GND

SLEEP#

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Figure 3

Pinout diagram 7mm x 7mm QFN (Top View)

Datasheet

7 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Pin Function

4

Pin Function

Table 4

PIN Function

Description

If not used

#

Name

VIN_D

TYP

P [I]

1,2,3

Input supply voltage pins for Switcher D. Decouple locally by

connecting a ceramic capacitor from this pin to GND.

Short To

GND

4

BOOT_D

A [B]

Supply input for Switcher D high side FET gate drive. Connect

a 0.1uF MLCC between this pin and PHASE_ D pins. An

internal diode is connected between VDRV and this pin

Open

5,6,7

PHASE_D

PHASE_C

P [O]

Switch node of Switcher D. Connect directly to the output

inductor.

Open

8,9,

10

Switch node of Switcher C. Connect directly to the output

inductor.

11

BOOT_C

A [B]

Supply input for Switcher C high side FET gate drive. Connect

a 0.1uF MLCC between this pin and PHASE_C pins. An internal Open

diode is connected between VDRV and this pin

12,

13,14

15

VIN_C

FB_C

P [I]

A [I]

Input supply voltage pins for Switcher C. Decouple locally by

connecting a ceramic capacitor from this pin to GND.

Short To

GND

Switcher C feedback input. Connect directly to VOUT_C for

output voltages less than 2.55V. Connect to VOUT_C with a

2:1 resistor divider for output voltages greater than 2.55V.

Open

16

17

PG_D

D [O]

Open drain power good output indicating Switcher D is

powered up

ALERT#

I2C/PMBus Alert line. This alert signal can indicate one or

more faults, allowing the system bus manager to poll the

device and identify the root cause. All faults or customer

selected faults such as overcurrent or over-temperature may

be specifically masked to this pin.

Open

18

19

20

CLK

D [B]

P [I]

I2C/PMBus Clock Line. Pull up to VDDIO with 10K

I2C/PMBus Data Line. Pull up to VDDIO with 10K

n/a

DATA

VDDIO

Pull-up signal voltage for I2C communications. Connect to the

same I/O rail used by the I2C master.

n/a

21

22

1V8

A [O]

P [I]

1.8V reference used by the device for internal analog and

digital control. Decouple using a 1.0uF X7R type ceramic

capacitor

n/a

VIN_LDO

Input to the linear regulator. See linear regulator section for

specific requirements. This voltage can range from 1.2V to

5.5V, with restrictions on overall power dissipation

Short To

GND

23

24

25

VO_LDO

FB_L

A[O]

A [I]

D[I]

LDO output

Open

LDO feedback input

PG_L

Open drain power good output indicating LDO is powered up.

Pull up to 5V with 10K

Open

26

PG_A

D[I]

Open drain power good output indicating switcher A is

powered up. Pull up to 5V with 10K

Datasheet

8 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Pin Function

Description

If not used

#

Name

PG_C

TYP

D[I]

27

28

Open drain power good output indicating switcher C is

powered up. Pull up to 5V with 10K

Open

EN_L

D[I]

LDO enable input control. Active High, external termination

required, do not leave floating. LVTTL threshold levels. ‘ON’

threshold is 2.1V minimum

Short To

GND

29

SLEEP#

Active low signal to place the device in a low power mode

LVTTL threshold levels. ‘SLEEP ENABLED’ threshold is 0.8V

maximum

Short to

VCC

30

31

PG_B

FB_B

D[I]

A [I]

Open drain power good output indicating switcher B is

powered up. Pull up to 5V with 10K

Open

Switcher B feedback input. Connect directly to VOUT_B for

output voltages less than 2.55V. Connect to VOUT_B with a

2:1 resistor divider for output voltages greater than 2.55V.

32

33

VIN_B

P [I]

Input supply voltage pin for Switcher B. Decouple locally by

connecting a ceramic capacitor from this pin to GND.

Short To

GND

BOOT_B

A [B]

Supply input for Switcher B high side FET gate drive. Connect

a 0.1uF MLCC between this pin and PHASE_ B pins. An

internal diode is connected between VDRV and this pin

Open

34,35 PHASE_B

36,37 PHASE_A

P [O]

A [B]

Switch node of Switcher B. Connect directly to the output

inductor.

Open

Switch node of Switcher A. Connect directly to the output

inductor.

38

BOOT_A

Supply input for Switcher A high side FET gate drive. Connect

a 0.1uF MLCC between this pin and PHASE_A pins. An internal Open

diode is connected between VDRV and this pin

39

40

41

VIN_A

RTN_A

FB_A

P [I]

A [I]

Input supply voltage pin for Switcher A. Decouple locally by

connecting a ceramic capacitor from this pin to GND.

Short To

GND

Differential feedback return signal for Switcher A. This can be Short

connected remotely to the return location of VOUT_A.

together

Differential feedback positive signal for Switcher A. Connect

directly to VOUT_A for output voltages less than 2.55V.

Connect to VOUT_A with a 2:1 resistor divider for output

voltages greater than 2.55V.

Short

together

42

43

EN_A

D [I]

Switcher A enable input control; external termination

required, do not leave floating. LVTTL threshold levels. ‘ON’

threshold is 2.1V minimum

Short To

GND

PWM_A

A [O]

PWM signal for Switcher A to be used when Switcher A is

configured for use with an external IR MOSFET™ Power

Stage. This PWM pin is a 5V PWM. This pin is used to drive a

5V capable external power stage such as an IR355x power

stage and is a tri-state or tri-level signal. A resistor and zener

clamp must be used when paired with a 3.3V only power stage

(see figure 11). Leave floating if this pin is not used

Open

44

EN_B

D [I]

Switcher B enable input control; external termination

required, do not leave floating. LVTTL threshold levels. ‘ON’

Short To

GND

Datasheet

9 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Pin Function

Description

If not used

#

Name

TYP

A[I]

threshold is 2.1V minimum

45

46

47

ISEN_A-

Negative (return) sense point for Switcher A external IOUT

sense.

Short

together

ISEN_A+

VDRV

A[I]

Positive sense point for Switcher A external IOUT sense.

Short

together

A [O]

5V drive voltage used to power the internal MOSFET drivers.

Use a 2.2Ω, 2.2uF filter from VCC to insure noise from this

switching node is not injected into the VCC pin. See the

application section. Terminate decoupling cap to GND (pin 57)

n/a

48

VCC

A [O]

5V source used by the device to power internal analog and

digital control. When VCC is self-generated by the device (from

VSUPPLY), do not load this pin with any load other than VDRV. n/a

Decouple using a 2.2uF X7R type ceramic capacitor.

Terminate decoupling cap to AGND (pin 50)

49

VSUPPLY

A [I]

D[I]

Input voltage for internal LDO for internally generated VCC

Short to

VCC

50

51

AGND

EN_C

Ground reference for the analog and digital control.

n/a

Switcher C enable input control; external termination

required, do not leave floating. LVTTL threshold levels. ‘ON’

threshold is 2.1V minimum

Short To

GND

52

53

SYNC_CLK

EN_D

D[I]

External Synchronization pin. LVTTL threshold levels. ‘HIGH’

threshold is 2.1V minimum, ‘LOW’ is 0.8V maximum

Short to

GND

D [I]

Switcher D enable input control; external termination

required, do not leave floating. LVTTL threshold levels. ‘ON’

threshold is 2.1V minimum

Short to

GND

54

MTP

A [I]

A resistor placed to ground on this pin selects which of 15 MTP

banks of memory are used. By allowing up to 15 MTP

memory banks, a user can use up to 15 identical IRPS5401

devices on a single board using just one customer-

configuration file. If this pin is above 2V when POR occurs, the

device will not load OTP and the I2C address will be 0Ah.

Decouple with 0.01uF cap.

n/a

55

ADDR_PROT

Use a resistor on this pin to set the I2C and/or PMBus Address

offset for the device If the I2C register R/W protect security

function is used and ‘PIN’ protect is enabled, this pin must be

asserted high to disable the R/W protection. Decouple with

0.01uF cap.

56

57

FB_D

GND

A [I]

Switcher D feedback input. Connect directly to VOUT_D for

output voltages less than 2.55V. Connect to VOUT_D with a

2:1 resistor divider for output voltages greater than 2.55V.

Open

n/a

Ground. The large metal pad on the bottom must be

connected to Ground.

Datasheet

10 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Block Diagram

5

Block Diagram

VIN

SWITCHER C – 4A

SWITCHER A – 2A

5-12V

VDRV

BOOT

VOUT_A

VOUT_C

PHASE

PWM_A

5V

GND

Internal Current Sense

GND

FB

Internal Current Sense

IS+

IS-

External DCR Current Sense

VIN

SWITCHER D – 4A

5-12V

VDRV

BOOT

FB_A

RTN_A

VOUT_D

VIN

PHASE

SWITCHER B – 2A

5-12V

VDRV

5V

BOOT

VOUT_B

GND

PHASE

Internal Current Sense

5V

FB

VDRV

VSUPPLY

VCC

Reference

Circuit

GND

1.8V

Internal Current Sense

FB_B

FB/REF

VIN_LDO

1.8V

5V

VDDIO

CLK

Margin Control

ΔV

I2C Interface

+

VO_LDO

15%

DATA

w variable Ref.

ALERT

_

ADDR_PROT

GND

5

0.5V Ref

EN

PG

Sequencing &

Ramp Control

Tracking/Non-Tracking LDO

Timing & Phase

CLK

SYNC_CLK

ØA 0Ø°

ØB - 180°

ØC - 90°

ØD - 270°

Registers and

MTP Memory

MTP

PLL &

Phase Block

Figure 4

IRPS5401 Block Diagram

Datasheet

11 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Absolute Maximum Ratings

6

Absolute Maximum Ratings

Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these or any other conditions beyond

those indicated in the operational sections of the specifications are not implied.

Table 5

Voltage Ratings

Vin [A_B_C_D], VSUPPLY

VCC, VDRIVE

-0.3V to 16V

-0.3V to 6V

VDDIO

-0.3 to 5.5V

1V8

-0.3V to 2V

BOOT [A_B_C_D]

BOOT [A_B_C_D] <10ns transient

SW [A_B_C_D]

-0.3V to 22V

-0.3V to 24V

-0.3V to 16V

SW [A_B_C_D] <10ns transient

BOOT to SW [A_B_C_D]

Input / Output Pins

GND to AGND

-4V to 18V

-0.3V to VCC +0.3V (Note2)

-0.3V to VCC +0.3V (Note1)

-0.3V to +0.3V

Table 6

Thermal Information

Junction to Ambient Thermal Resistance Ɵ_JA

Junction to PCB Thermal Resistance Ɵ_J-PCB

Maximum Storage Temperature Range

13.5°C/W

3°C/W

-55°C To 150°C

-40°C To 125°C (Note 3)

300°C

Maximum Junction Operating Temperature Range

Maximum Lead Temperature (Soldering 10s)

Note:

1. Voltages referenced to GND unless otherwise specified

2. Must not exceed 6V

3. Cold temperature performance is verified via correlation using statistical quality control. Not tested in

production.

Datasheet

12 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Electrical Specifications

7

Electrical Specifications

RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN

Table 7

Recommended Operating Ambient Temperature Range*

VIN [A to D]

-40°C to 85°C

1.2V to 14V (with external VCC)

VSUPPLY (for Internal VCC)

External VCC and VDRIVE Voltage Range

VDDIO

6V to 14V

4.5V to 5.5V

3.3V

SWA and SWB Output Load

SWC and SWD Output Load

Combined SWC+SWD Output Load

0A to 2A

0A to 4A

0A to 8A

Note:

The electrical characteristics table lists the spread of values verified within the recommended

operating conditions. Typical values represent the median values, which are related to 25°C.

*For operation below 0°C, a delay of 60ms between applying power and output ramp up is

required. See more details in 9.3

Table 8

Electrical Characteristics

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

UVLO Turn-on

Threshold

4.2

4.5

V

UVLO Turn-off

Threshold

3.6

3.9

40

25

10

V

All outputs disabled

(low power disabled)

All outputs disabled

(low power enabled)

SLEEP# = low

Supply Current

I_VCC

45

30

25

mA

uA

Supply Current

(Sleep Mode Enabled)

VDRV

UVLO Turn-on

Threshold

4.2

3.9

15

4.5

V

UVLO Turn-off

Threshold

3.6

V

All outputs Enabled, fsw

=800kHz

Supply Current

I_vdrv

mA

Internal Supply VCC

LDO

Input Voltage

Output Voltage (on Vcc

pin)

6

-

14

V

Ta=25°C, 6.0V<VSUPPLY<14V,

0mA<Iout<50mA

V_cc

4.6

4.85

5.1

Datasheet

13 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Electrical Specifications

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Output Current

I_outmax

-

75

mA

VDDIO

Input Voltage¹

Input High Voltage

Input Low Voltage

Input Leakage

I2C termination voltage

% of VDDIO

1.62

60

-

5.5

-

V

%

µA

% of VDDIO

30

1

Vpad = 0 to 5.5V

-1

Reference Voltage

(DAC) [A to D]

Range

0.25

-0.8

2.55

0.8

V

Resolution

Accuracy

(0°C to 85°C junction

temperature)

5

-

mV

VID = 1.0 to 2.55V

%

VID = 0.5V to 0.995V

VID = 0.25V to 0.495V

-8

-

8

mV

-10

10

Accuracy¹

VID = 1.0 to 2.55V

-1.5

-

1.5

%

(-40°C to 125°C junction

temperature)

VID = 0.5V to 0.995V

VID = 0.25V to 0.495V

-15

-20

-

15

20

mV

Oscillator & PWM

Generator

Internal Oscillator¹

-

48

-

3

MHz

%

0°C to 85°C junction

temperature

Frequency Accuracy

-3

Frequency Accuracy

PWM Frequency Range¹

PWM Resolution¹

-40°C to 125°C

-6.25

200

-

+6.25

%

-

2000 kHz

2.6

-

ns

Digital Inputs – TTL

ADDR_PROT,

EN_x

Input High Voltage

Input Low Voltage

Input Leakage

2.1

-

0.8

1

V

Vpad = 0 to 5.5V

-1

µA

Digital Inputs – TTL

Input High Voltage

Input Low Voltage

Input Leakage

SLEEP#

SYNC

2.1

-

V

0.8

10

V

-10

µA

External Sync

Frequency range

Voltage Range

200

0

1000 kHz

5

Vdc

V

Input High voltage

Datasheet

2.1

14 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Electrical Specifications

Parameter

Symbol

Conditions

Min.

Typ.

Max.

0.8

±5

Unit

V

Input Low Voltage

Input Leakage current

Sync pin capacitance

Vpad = 0 to 5.5V

µA

pF

10

Synchronization Range

(From OTP setting)

0°C to 85°C

-6.25

+6.25

%

Synchronization Range

(From OTP setting)

-40°C to 125°C

-3

+3

55

%

Sync signal Duty Cycle

45

50

Remote Voltage Sense FB [A to D],

Inputs

RTN_A

FB_x Input Current

RTN_A Input Current

VOUT = 0.25V to 2.55V

RTN_A = ±100mV

-35

-

90

-

µA

V

-50

Differential Input

Voltage Range¹

0

2.55

RTN_A Input CM

-100

-

100

mV

Voltage¹

Remote Current Sense ISEN_A+/ISEN_A

Inputs

-

Common Mode Voltage

Range¹

-0.1

-10

-

Vcc-1

60

V

Differential Voltage

Range¹

mV

Analog Address/Level

Inputs

ADDR_PROT,

MTP

Output Current¹

Vpad = 0 to 1.2V

96

100

104

µA

Open-Drain Outputs

PG_x, DATA,

ALERT#

Output Low Voltage

Output Leakage

PWM I/O

4mA

-

0.3

±5

V

Vpad = 0 to 5.5V

µA

PWM_A

Output Low Voltage

I = -4mA

-

0.4

V

VCC-

0.45V

I = +4mA

Output High Voltage

Tri-State Leakage

I2C/PMBus

-

V

Vpad = 0 to Vcc

-

±1

µA

Bus Speed¹

Normal

Fast

-

100

400

-

kHz

Maximum

1000

Datasheet

15 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Electrical Specifications

Telemetry Reporting -

Switching Outputs [A

to D]

0.97,

1.9,

3.8,

Iout, Iin, Vin and

Temperature Filter

Rate¹

Selectable

(Selected Frequency applies

to all parameters for all

loops)

-

7.7,

-

Hz

15.5,

31, 63,

126

Iout, Iin, Vin,

Temperature Update

Rate¹

25

kHz

Vin Reporting Range¹

0

-2

-5

-

17.5

2

V

Vin Reporting Accuracy

(-2 to 2%)

VIN = 12V

VIN = 5V

-

%

mV

V

Vin Reporting Accuracy

-

31.25

-

5

Vin Reporting

-

Resolution¹

Vout Reporting Range¹

With 2:1 scaling

-

5.1

Vout Reporting

Accuracy¹

READ_VOUT reports DAC

setting

0.5

%

User Selectable

per output

through

VOUT_MODE

command.

Actual

resolution is

5mV/10mV

depending on

VOUT_SCALING

0.244

1.953

3.906

Vout Reporting

Resolution¹

-

mV

Iout Reporting Gain

Accuracy¹

Iread=Iout(1±gain_error)±I_o

s*full scale

gain_error

I_os

-5

5

%

Iout Reporting Offset

Accuracy¹

full Scale = 2A for A/B

and 4A for C/D

-2.5

2.5

%

Iout Reporting

Resolution¹

-

15.625

7.8125

31.25

0.25

-

mA

mW

Iin Reporting

Resolution¹

P_in Reporting

Resolution¹

P_out Reporting

Resolution¹

Temperature Reporting

Resolution¹

°C

%

Temperature Reporting

-2

2

Datasheet

16 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Electrical Specifications

Accuracy¹

Telemetry Reporting -

Switching Output A

with External IR

MOSFET™ Power Stage

Iout Reporting

Resolution¹

-

-6

-

125

-

6

-

mA

%

Iout Reporting

Accuracy¹

At 100% full load. Assumes ±

5% accurate external source

Iin Reporting

Resolution¹

62.5

250

mA

mW

P_in Reporting

Resolution¹

-

P_out Reporting

-

Resolution¹

Telemetry Reporting -

LDO

Vin Reporting Range¹

0

-

8

-

V

Vin Reporting

Resolution¹

7.812

mV

Vin Reporting Accuracy

Vout Reporting Range¹

-2

0

-

2

4

%

V

Vout is measured

-

Vout Reporting

Resolution¹

0.244

1.953

3.906

-

User Selectable through

VOUT_MODE command.

-

mV

Vout Reporting Accuracy

Iout Reporting Range¹

-2

0

2

%

A

-

0.72

Iout Reporting

-

-10

-

0.976

-

10

-

mA

%

Resolution¹

Iout Reporting Accuracy¹

At 500mA

P_in Reporting

15.625

mW

Resolution¹

P_out Reporting

Resolution¹

-

mW

Datasheet

17 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Electrical Specifications

Fault Protection -

Switchers [A to D]

OVP Threshold During

Start-up (until output

reaches 1V)

OVP Threshold During

Start-up (until output

reaches 1V)

1.2

2.4

1.35

2.75

1.5

3.0

V

OVP and UVP Operating

Relative to VID, 1:1 scaling

Relative to VID, 2:1 scaling

50

-

400

-

mV

Threshold¹

Range:

Resolution:

50

OVP and UVP Operating

100

800

Threshold¹

Range:

Resolution:

OVP and UVP delay¹

OVP and UVP threshold

-

100

-

mV

ns

After exceeding threshold

For thresholds > 200mV

150

-20

0

20

%

A

Tolerance¹

OC WARN and FAULT

Range²

Switcher A and B

-

4

OC WARN and FAULT

Switcher C and D

0

-

8

15.97

-

A

Range²

OC WARN and FAULT

Range²

OC WARN and FAULT

Resolution

Switcher C in C+D mode

0

A

-

31.25

mA

OC FAULT Threshold

Tolerance

(0°C to 85°C junction

temperature)

At 3A for A and B, 6A for C and

D, at 12A for C+D

-10

-20

+10

+20

%

OC FAULT Threshold

Tolerance¹

At 3A for A and B, 6A for C and

D, at 12A for C+D

(-40°C to 125°C junction

temperature)

OT WARN and FAULT

0

-

255

-

°C

Range¹

OT WARN and FAULT

Resolution¹

1

Fault Protection -

Switcher A with

External IR MOSFET™

Power Stage

OC WARN and FAULT

Range²

0

-

255

A

OC WARN and FAULT

Resolution

0.25

62

-

A

External ISENSE Filter

Bandwidth

-

kHz

Datasheet

18 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Electrical Specifications

Fault Protection - LDO

Read Only, % of VOUT as set

in ldo_target_register - Non

tracking OR

OV FAULT

-

125

-

%

measured VIN/2 - Tracking

OV WARN

-

112.5

75

-

%

A

UV FAULT

-

UV WARN

-

87.5

0.72

-

OC FAULT

Read Only

-

0.72

-

OC WARN Range

OC WARN Resolution

0

-

A

3.9

mA

MOSFET - Switcher A

and B

High Side Switch

Resistance

Tj = 20°C, BOOT-PHASE = 5V

Tj = 20°C, VDRV = 5V

-

150

45

-

mΩ

Low Side Switch

Resistance

MOSFET – Switcher C

and D

High Side Switch

Resistance

Tj = 20°C, BOOT-PHASE = 5V

Tj = 20°C, VDRV = 5V

-

85

25

-

mΩ

Low Side Switch

Resistance

LDO

Input Voltage

V_{in_ldo}

1.2

0.5

-

5.5

3.6

0.5

510

515

V

Output Voltage

Dropout Voltage

Output Current

Reference Voltage

V_{out_ldo}

V_{dropout_ldo}

I_{out_ldo}

-

V

Iout=0.5A, Tj=125°C

V

-

A

V_{ref_ldo}

Ta = 25°C

490

485

500

mV

-40°C<Tj < 85°C

Timing Information

Automatic

Time from POR to end of

configuration loaded from

NVM to working registers

Configuration from

-

1

-

ms

MTP¹

Isense AMP Automatic

Trim Time¹

-

1

3

-

ms

µs

Delay from Enable high

to ramp start¹

Low power mode disabled

Low power mode enabled

Delay from Enable high

to ramp start¹

600

1. Verified by design

2. Actual OC limit (MAX sustained load the VR can handle) is a function of inductor ISAT and system thermal

solution. SW A and B limited to 2A max DC load. SW C and D limited to 4A max DC load

Datasheet

19 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Typical Application Diagrams

8

Typical Application Diagrams

Vin

PWM_A NC

BOOT_A

VDRV

VOUT_A

Vcc

PHASE_A

2A Max

1.8V

RTN_A

FB_A

Route sense lines

differentially

Vin

VSUPPLY

Divider optional; only

required for 2:1 scaling

ISEN_A+ NC

ISEN_A- NC

5.5V Max

VIN_LDO

VO_LDO

3.6V, 0.5A Max

BOOT_B

VOUT_B

FB_L

PG_L

EN_L

PHASE_B

2A Max

IRPS5401

PG_A

EN_A

PG_B

EN_B

PG_C

EN_C

PG_D

EN_D

FB_B

Divider optional; only

required for 2:1 scaling

BOOT_C

VOUT_C

PHASE_C

4A Max

VDDIO

1.6V – 5V, I2C

pull up voltage

I2C or SMBus

Terminate to VDDIO

with 4.7K

ALERT#

CLK

FB_C

Divider optional; only

required for 2:1 scaling

DATA

ADDR_PROT

BOOT_D

VOUT_D

SYNC_CLK

SLEEP#

PHASE_D

4A Max

Active Low, pull up to Vcc

MTP

FB_D

Divider optional; only

required for 2:1 scaling

GND

Figure 5

IRPS5401 in 5 output configuration with Vcc from internal LDO

Datasheet

20 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Typical Application Diagrams

Vin

PHASE_A

BOOT_A

NC

VDRV

P5V

Vcc

Vin

VSUPPLY

IR3555 Boot

P5V

Vcc

VOUT_A

PWM

PWM_A

Switch

IOUT

ISEN_A+

TOUT

GND

REFIN

To SMC

To IR3555 REFIN

1.8V

ISEN_A-

To 1.8V Reference

FB_A

Route sense lines differentially

5.5V

MAX

RTN_A

VIN_LDO

3.6V, 0.5A Max

VO_LDO

BOOT_B

VOUT_B

FB_L

PG_L

EN_L

PHASE_B

2A Max

IRPS5401

PG_A

EN_A

PG_B

EN_B

PG_C

EN_C

PG_D

EN_D

FB_B

Divider optional; only

required for 2:1 scaling

BOOT_C

VOUT_C

PHASE_C

4A Max

VDDIO

1.6V – 5V, I2C

pull up voltage

I2C or SMBus

Terminate to

VDDIO with 4.7K

ALERT#

CLK

FB_C

Divider optional; only

required for 2:1 scaling

DATA

ADDR_PROT

BOOT_D

VOUT_D

SYNC_CLK

SLEEP#

PHASE_D

4A Max

Active Low, pull up to Vcc

MTP

FB_D

Divider optional; only

required for 2:1 scaling

GND

Figure 6

IRPS5401 using external IR MOSFET™ Power Stage for high Current Output

Datasheet

21 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Typical Application Diagrams

Vin

PHASE_A

BOOT_A

NC

VDRV

P5V

Vcc

Vin

VSUPPLY

IR3555 Boot

P5V

Vcc

VOUT_A

PWM

PWM_A

Switch

IOUT

ISEN_A+

TOUT

GND

REFIN

To SMC

To IR3555 REFIN

1.8V

ISEN_A-

To 1.8V Reference

FB_A

Route sense lines differentially

RTN_A

5.5V Max

VIN_LDO

3.6V, 0.5A Max

VO_LDO

BOOT_B

VOUT_B

FB_L

PG_L

EN_L

PHASE_B

2A Max

IRPS5401

PG_A

EN_A

PG_B

EN_B

PG_C

EN_C

PG_D

FB_B

Divider optional; only

required for 2:1 scaling

BOOT_C

NC

VOUT_C

PHASE_C

NC EN_D

VDDIO

4A Max

1.0V – 5V, I2C

pull up voltage

I2C or SMBus

Terminate to

VDDIO with 4.7K

ALERT#

CLK

FB_C

DATA

ADDR_PROT

BOOT_D

SYNC_CLK

SLEEP#

PHASE_D

4A Max

Active Low, pull up to Vcc

MTP

FB_D NC

GND

Figure 7

IRPS5401 using Switcher C and Switcher D in parallel for higher current applications

Datasheet

22 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Typical Application Diagrams

TYPICAL OPERATING CHARACTERISTICS

VCC=5V, -40°C to 125°C

Typical DAC Error at 0.5V

Typical DAC Error at 2.5V

3.0

10

8

2.5

2.0

1.5

1.0

0.5

0.0

6

4

2

0

-50

0

50

100

150

-50

0

50

100

150

Temperature (°C)

Typical ICC in Low Power Mode

Typical ICC

39

38

37

36

35

34

25

24

23

22

-50

0

50

100

150

-50

0

50

100

150

Temperature (°C)

Sync FET Rdson

Control FET Rdson

70

60

50

40

30

20

10

0

250

200

150

100

50

A&B

C&D

A&B

C&D

0

-50

0

50

100

150

-50

0

50

100

150

Temperature (°C)

Datasheet

23 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

9

Description

The IRPS5401 is a digitally configurable flexible power management unit, with an I2C/PMBus interface. It can

support up to 5 rails, with 4 independent switching regulators and one linear regulator.

The switching frequency is programmable from 200 kHz to 2MHz and provides the capability of optimizing the

design in terms of size and performance.

The IRPS5401 switchers provide precisely regulated output voltages programmable from 0.25V to 2.55V without

a resistor divider and up to 5.1V with a resistor divider.

The IRPS5401 can operate with an internal bias supply (LDO), typically 5.0V. This allows operation with a single

supply by connecting the input of the LDO (VSUPPLY) to the bus voltage (Vin_x). A 1uF capacitor should be used

at the VSUPPLY pin for decoupling purposes. The output of this LDO is brought out at the Vcc pin and must be

bypassed to the analog ground (pin 50) with a 1.0uF decoupling capacitor. An additional voltage, VDRV,

required by the internal driver circuitry is derived by using a 2 ohm-1uF filter from the Vcc pin to the VDRV pin.

Note that the 1uF at the VDRV pin must be bypassed to the system power ground (pin 57). The Vcc pin may also

be connected to the VSUPPLY pin, and an external Vcc supply between 4.5V and 5.5V may be used, allowing for

an extended operating bus voltage (Vin_x) range from 1.2V to 14V.

The device utilizes the on-resistance of the low side MOSFET (synchronous MOSFET) as the current sense

element. This method enhances the converter’s efficiency and reduces cost by eliminating the need for external

current sense resistors.

9.1

One-time Programmable (OTP) Memory

The IRPS5401 has 64K of OTP non-volatile memory. The OTP design is based on a patented split-channel non-

volatile anti-fuse memory cell. The OTP memory has a data retention rating of 20 years and an operating

temperature range of -40°C to 150°C (-55°C to 150°C storage rating)

This memory space is divided up into 26 OTP segments that can be programmed 1 time. The memory space is

therefore referred to as Multiple-times Programmable (MTP). This allows the user to; a) change the

configuration registers and re-program the MTP up to 26 times or b) save up to 15 configuration files during

initial programing and use the MTP pin to choose which file to load at start up. If option b is used, the

remaining unused MTP segments are available for the user to make additional changes to the configuration file

and save to MTP using the PowIRCenter GUI device programmer utility.

9.2

MTP pin (pin 54)

The table below shows the MTP segment that will be selected with a given resistor value connected to the MTP

pin. The resistor must be connected to the AGND pin and bypassed with a 10nF X7R type multi-layer ceramic

capacitor.

Datasheet

24 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

Table 9

MTP pin Resistor

MTP Segment selected

*0.845kΩ

*1.30kΩ

*1.78kΩ

2.32kΩ

2.87kΩ

3.48kΩ

4.12kΩ

4.75kΩ

5.49kΩ

6.19kΩ

6.98kΩ

7.87kΩ

8.87kΩ

10.00kΩ

11.00kΩ

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+10

+11

+12

+13

+14

Note:

Do not use these values for applications with ambient temperatures <0°C

The number of segments that the user chooses to program with multiple configuration files is set

by a configuration register called max_prog. The max_prog register value needs to be set to the

number of configuration files that will be programmed. For example, if the user programs

segments +0, +1, and +2, then the max_prog register needs to have a value of 3. For applications

with junction temperatures below 0°C, segments +0, +1, and +2 are not available.

9.3

Device Power-up and Initialization

During the power-up sequence, when VIN is brought up, the internal LDO converts it to a regulated 5.0V at VCC.

There is another LDO which further converts this down to 1.8V to supply the internal digital circuitry. An under-

voltage lockout circuit monitors the voltage of the VCC pin and the P1V8 pin, and holds the POR low until these

voltages exceed their thresholds and the internal 48 MHz oscillator is stable. When the device comes out of

reset, it initializes an MTP load cycle, where the contents of the MTP are loaded into the working registers. Once

the registers are loaded from MTP, the designer can use I2C/PMBus to re-configure the registers to suit the

specific VR design requirements if desired, irrespective of the status of the enable pins.

Datasheet

25 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

**60 ms if Tamb < 0° C

2 ms

Vsupply=VIN_x

VCC

P1V8

POR

Trims done, MTP loaded

and address offset resistor read

En_x

Vout

Figure 8

Power up sequence

In the default configuration, power conversion for a given loop is enabled only when the corresponding En_x

pin voltage is asserted high, the Vin_x bus voltage exceeds its under voltage threshold (as stored in the MTP

registers and commanded by the PMBus commands VIN_ON and VIN_OFF), the contents of the MTP have been

fully loaded into the working registers and the device address has been read. IRPS5401 provides additional

options to enable the device power conversion through software and these options may be configured to

override the default by using the I2C interface or PMBus.

Note:

The VDDIO pin voltage must remain stable after device POR. Cycling the VDDIO voltage after a

device POR will cause a timing violation of the I2C bus protocol and may result in I2C and PMBus

communication issues

Note:

**For Internal Switchers only (Switcher A, B, C, and D), a 60ms delay is required for applications

that operate with an ambient temperature less than 0°C. The delay can also be accomplished by

delaying the EN pin, using the PMBus TON_DELAY command, or a combination of both. This delay

does not apply to the LDO output or Switcher A if Switcher A is configured in External Switcher

mode

9.4

Addressing the IRPS5401

The IRPS5401 has two 7-bit registers that are used to set the base I2C address and base PMBus address of the

device, as follows.

Table 10

Register

Description

Default

10h

i2c_device_address

The chip I2C address. An address of 0 will disable I2C communication

pmb_device_address The chip PMBus address. An address of 0 will disable PMBus

communication.

40h

Setting another bit, i2c_take_addr_from_ext, to 1, will allow the user to offset the base address of the device

using a resistor from ADDR_PROT to AGND. In such a case, the table below provides the resistor values needed

to realize up to 15 offsets from the base address. For applications with junction temperatures below 0°C,

address offsets of +0, +1, and +2 are not available.

Datasheet

26 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

Table 11

ADDR_PROT Resistor

I2C Address Offset

*0.845kΩ

*1.30kΩ

*1.78kΩ

2.32kΩ

2.87kΩ

3.48kΩ

4.12kΩ

4.75kΩ

5.49kΩ

6.19kΩ

6.98kΩ

7.87kΩ

8.87kΩ

10.00kΩ

11.00kΩ

12.10kΩ

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+10

+11

+12

+13

+14

+15

Note:

Do not use these values for applications with ambient temperatures <0°C

Another bit i2c_pmb_addr_lock, if set, allows the user to lock the I2C and PMBus addresses.

9.5

Switching Frequency

The switching frequency (fsw) setting of the IRPS5401 is stored in MTP and can be configured by using the

PMBus command FREQUENCY_SWITCH.

The IRPS5401 with will ACK any FREQUENCY_SWITCH command from 200 kHz to 2MHz in increments of 1kHz

(increments of 2kHz with commands above 1MHz). Internally the command is decoded and the actual FSW is

set to the nearest value that can be supported with a 48MHz internal clock. For example, 500 kHz can be

supported with ninety-six (96) 48 MHz clocks. So if you ask for 500 kHz, you get exactly 500 kHz. But if you

wanted 450 kHz, the number of clocks required is 106.6667 (48/0.45). In this case, the frequency would be set

to one hundred and seven (107) 48MHz clocks or 448.6 kHz. Fractional values of 0.5 and above are rounded up

to the next whole number.

Because of the enforced phase relationship between the four switching regulators, the switching frequency for

all four switching regulators is determined by the FREQUENCY_SWITCH command sent to Switcher C.

FREQUENCY_SWITCH commands sent to Switchers A, B, and D will be ACK’d and ignored. A

FREQUENCY_SWITCH read command sent to Switchers A, B, or D will respond with the value that the user

wrote into the device but the actual switching frequency for Switcher B and D will be the switching frequency of

Switcher C. The switching frequency of Switcher A will be the switching of Switcher C if the

FREQUENCY_SWITCH value for Switcher A is the same as or greater than Switcher C. The switching frequency

of Switcher A will be one half of the switching frequency of Switcher C if the FREQUENCY_SWITCH value for

Switcher A is less than Switcher C. The switching frequency of Switcher A will be ½ of Switcher C even when

synced to an external CLK. This frequency relationship between Switcher A and Switcher C is the same with

Datasheet

27 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

Switcher A using internal mode or external power stage mode. Switcher A will have the same switching

frequency as Switcher C if Switcher C frequency is less than 400 kHz.

Even when running off an internal clock, all four switchers exhibit fixed phase relationships with one another,

with Switcher A leading Switcher C by 90⁰

which in turn leads loop B by 90^o. Finally loop D lags loop B by 90⁰. Thus loops A and B are out of phase by 180⁰

as are loops C and D.

Figure 9

Switcher phase relationship

9.6

Synchronizing to an External Clock

IRPS5401 implements a frequency lock loop which forces all four switcher loops to operate at the same

frequency as an external synchronization clock. The four switchers still maintain the same phase relationships

with each other as they do when running from an internal clock. Switcher A shows a small phase offset (~80ns)

from the sync clock.



If the sync clock is within ± 6.25% of the programmed frequency, the device will phase and frequency lock to

the incoming sync clock.



If the sync clock is more than ± 12.5% away from the programmed frequency, the device will lose sync and

will relax gradually to the programmed frequency.



Once the device is in sync, it will have a ± 10 ns uncertainty or jitter with respect to the sync clock.

It takes about 110us for the circuit to lock to the Sync clock.

9.7

Switcher A in External Powerstage Mode

Switchers B, C and D can only be operated in internal power stage mode, and their PWM signals are not brought

out to a pin. However, using an MTP register bit, sw_a_use_internal_driver, Switcher A can be configured to

operate in either internal power stage mode (sw_a_use_internal_driver=1) or in external power stage mode

(sw_a_use_internal_driver = 0). In the external power stage mode, the PWM output of Switcher A is brought out

to the PWM_A pin and can be connected to the PWM input pin of industry standard tri-state type drivers or

Infineon power stage devices. The logic of operation for the tri-state drivers is depicted in the figure below.

Note that the PWM_A output is tri-stated whenever the Switcher A is disabled, the shut-down ramp has

completed or before the soft-start ramp is initiated.

Datasheet

28 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

Figure 10

PWM_A tri-state details

PWM_A is a 5V PWM signal. A 3V zener clamp must be used to limit the power stage PWM pin voltage when the

IRPS5401 is paired with an external power stage that does not support 5V PWM input. A series resistance of 402

Ω must used to limit the zener current.

Figure 11

Zener clamp details when using power stages that only support 3.3V PWM input

9.8

Digital Controller & PWM

For the switcher loops A, B, C and D, the IRPS5401 uses a proprietary emulated current mode control scheme,

which makes it possible to use PI control to stabilize the loop for all types of inductors and capacitors, including

MLCC. The digitized error voltage from the high-speed voltage error ADC is processed by a digital compensator,

the proportional (K_p) and Integral (K_i) coefficients, which are programmable. The output of the compensator is

then compared with an emulated current signal to generate the PWM signal, with a resolution of 2.6ns to avoid

limit cycling. As a close realization to a Type II analog compensator, the control engine also implements a low

pass, programmable single pole (K_pole) filter. This defaults to 1.1MHz and in general, it should not be necessary

to change the location of this pole over a wide range of applications.

Ordinarily, a power stage using low ESR capacitors such as MLCCs requires the use of Type III compensation or

PID control, but, in the IRPS5401, the emulated current mode modulator provides another pole-zero pair,

unburdening the compensator and allowing a simple PI compensator to stabilize even such demanding

applications.

The compensator transfer function is defined as









Ki

(Kp  ) 

1





s

1





p₁







Where, ωp₁is the pole typically positioned to filter noise and ripple, and programmable through the register

K_pole1[3:0]

K_pis the proportional coefficient, programmable through the register k_p[5:0]

Datasheet

29 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description



And K_iis the integral coefficient programmable through the register k_i[5:0].

9.9

Diode Emulation / Discontinuous Mode Operation/AOT

Under very light loads, efficiency can become dominated by MOSFET switching losses. Using the manufacturer

specific PMBus command MFR_FCCM, it is possible to enhance the light load efficiency by allowing the

controller to work in an adaptive on time (AOT) or diode emulation mode.

Table 12

MTP Register

diode_emu_thresh

diode_emu_pw

Function

Default

Sets the error voltage at which an on-time pulse is started in 2mV

steps

0h

Sets the duration of the on-time pulse

4h

0h

Reduces the calculated low-side FET on-time in 62.5ns steps. Useful

for compensating for DrMOS or other drivers’ tri-state delay for a

better prediction of the zero-crossing

de_off_time_adjust

Error threshold to go from discontinuous conduction mode to

continuous conduction mode; 4 mV resolution. If Vout drops by this

amount, the control will be handed to PWM and diode-emulation is

ended.

1h

le_th

Total current threshold below which it is assumed that the inductor

current has a negative component.

00h

Inductor_ni_thresh

When the current reading drops below ni_thresh, the controller determines that the inductor current has a

negative component, and if MFR_FCCM=0, will allow AOT mode operation. Internal circuitry determines, using

diode_emu_pw and the read values of Vinx and Voutx, when the inductor current declines to zero on a cycle by

cycle basis and shuts off the low-side MOSFET at the appropriate time in each cycle. This reduces conduction

losses and also lowers the switching frequency resulting in improved efficiency because the inductor and low-

side MOSFET are not sinking power from the output capacitors at light loads.

In AOT mode, if Vout drops below a certain threshold (le_th) due to applying a fast transient load, the operation

is switched to continuous current mode (CCM) instantly.

Industry standard tri-state drivers typically have slow tri-state entry times, which allows negative current

to build up reducing efficiency and causing ringing.

The off_time_adjust variable allows the designer to compensate for the tri-state delay by reducing the low-side

FET on-time by an equivalent amount.

9.10

Output Voltage Sensing, Telemetry and Faults

The IRPS5401 provides true differential remote sensing for the Switcher A output. The FB_A and RTN_A pins are

connected to the load sense pins of the Switcher A output voltage to provide true differential remote voltage

sensing with high common-mode rejection. This allows Switcher A (in external power stage mode) to provide

excellent regulation even in high current applications. Switcher loops B, C and D have single ended feedback

connections for sensing and regulation. Each loop has a high bandwidth error amplifier that generates the

error voltage between this remote sense voltage and the target voltage. The error voltage is digitized by a fast,

high-precision ADC. This digitized error is used for Vout under voltage fault and warning detection as well as for

Vout overvoltage fault warning detection. Vout is reported using the READ_VOUT PMBus command. The

reported Vout is the DAC reference value and not the actual measure output voltage.

Datasheet

30 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

As shown in the figure below, the Vsen and Vrtn inputs have a 20kΩ pull-up to an internal 1V rail. This causes

some current flow in the Vsen and Vrtn lines so external impedance should be kept to a minimum to avoid

creating an offset in the sensed output voltage.

1V

20K

FB_A

+

-

RTN_A

RTN_B,C,D

terminated to GND

internally

Figure 12

Output Voltage Sensing impedance

9.11

Output Over Voltage Protection (OVP)

If the output voltage exceeds a user-programmable (through PMBUS) threshold, the IRPS5401 detects an

output over-voltage fault and latches on the low-side MOSFET to limit the output voltage rise

It should be noted, however, that although the overvoltage threshold is programmable to any value using the

PMBus command, VOUT_OV_FAULT_LIMIT, internally it is translated into an offset from the commanded or

reference voltage, with a resolution of 50 mV (100 mV if a 2:1 divider is used) and with a minimum value of 50

mV (100 mV if a 2:1 divider is used) and maximum value of 400 mV (800 mV if a 2:1 divider is used).

Under OVP conditions, depending on the setting of the VOUT_OV_FAULT_RESPONSE, the converter can be

configured to keep regulating or to go into a latched shutdown, where the high side FET or Control FET is

turned off and low side FET or Sync FET is turned on. Note however that there is an MTP register,

vpu_high_release_en, that allows the low side FET operation to be configured in one of two ways: a) remain

latched on indefinitely or b) remain latched on until the output voltage falls below 200mV at which time the

low-side FET is released. This release mode can reduce or prevent undershoot of the output voltage.

During soft-start, OVP is triggered at the fixed soft-start level. This level can be chosen, using an MTP register,

from two different values of 1.35V or 2.75V respectively. If a 2:1 divider is used, these values automatically scale

to 2.7V and 5.5V respectively. In fact, it is this value which limits the maximum output voltage the IRPS5401 can

support to 5.5V.

Note that in the FET release mode, if the output voltage rises above the fixed OVP level, the low side MOSFET’s

will again be turned on until Vout drops below the release threshold level.

The user can cycle out of a latched over voltage fault by cycling En_x, VCC or the PMBus Operation command.

The other output are unaffected by the OVP event unless global_fault_en=1

Note:

An OCP event may cause the VOUT_OV_WARN bit in the STATUS_VOUT register to falsely assert

Datasheet

31 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

Figure 13

OVP with vpu_high_release_en=1

Figure 14

OVP with vpu_high_release_en=0

9.12

Output Under Voltage Protection (UVP)

The IRPS5401 detects an output under-voltage condition if the sensed voltage is below the user-programmable

(through PMBus) UVP threshold. Upon detecting of an output under-voltage condition, the IRPS5401 can be

configured using the PMBus command, VOUT_UV_FAULT_RESPONSE to keep regulating or to go into a latched

shutdown.

It should be noted, however, that although the undervoltage threshold is programmable to any value using the

PMBus command, VOUT_UV_FAULT_LIMIT, internally the UV threshold depends upon the setting of a register

bit, vout_uv_by_adc, which can be set to either 0 (Vout undervoltage mechanism is through an analog

comparator) or to 1 (Vout undervoltage mechanism is through the hign speed error ADC saturation).

If the Vout undervoltage mechanism by comparator is selected, the VOUT_UV_FAULT_LIMIT is translated into

an offset from the commanded or reference voltage, with a resolution of 50 mV (100 mV if a 2:1 divider is used)

and with a minimum value of 50 mV (100 mV if a 2:1 divider is used) and maximum value of 400 mV (800 mV if a

2:1 divider is used).

On the other hand, if the ADC saturation mechanism is selected, the undervoltage threshold is implicitly 250 mV

(500 mV if a 2:1 divider is used) below the commanded or reference value.

The user can cycle out of a latched under voltage fault by cycling Enable, VCC or the PMBus Operation

command.

Datasheet

32 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

9.13

Current Sensing, Telemetry and Faults

The IRPS5401 has two different current sense mechanisms; a) Sync FET Rdson current sensing in internal

powerstage mode and b) DCR, shunt current sensing, or Rdson sense in external powerstage mode.

Current sensing for Switchers B, C and D is always across the Rdson of the Sync FET. Current sensing for

Switcher A is also across the Sync FET Rdson if in internal powerstage mode. A proprietary patented scheme

allows reconstruction of the average inductor current from the voltage sensed across the Sync FET Rdson. It

should be noted here that in internal powerstage mode it is this reconstructed average inductor current that is

digitized by the monitor ADC and used for output current reporting. However, in this mode, the overcurrent

protection mechanism relies on an analog comparator and does not depend on the ADC or on the output

current reporting.

If Switcher A is operated in external powerstage mode, the current is sensed through the drop across a

precision current shunt, the drop across the inductor DCR, or the IOUT signal of an Infineon Rdson power stage

like the IR3555 and is fed to a differential current sense amplifer at the ISEN_A+ and ISEN_A- pins of the

IRPS5401.

For DCR sensing, a suitable resistor-capacitor network of R_senand C_senis connected across the inductor as

shown in the figure below. The time constant of this RC network is set to be equal to the inductor time constant

(L/DCR) such that the voltage across the capacitor C_senis equal to the voltage across the inductor DCR. A 100K

NTC thermistor is also recommended across C_sento compensate for the positive temperature coefficient of

inductor DCR

L_out

DCR

V

out

Csen

NTC

Rsen

I I_{L_out}

ISEN_A+

ISEN_A-

+

-

Figure 15

DCR Current Sensing

The recommended value for C_senis a 220nF NPO type capacitor.

ꢀꢁꢂꢃ = (ꢄ_ꢅꢆꢇ) ⁄ (ꢈꢉꢀ ∗ ꢉꢁꢂꢃ)

For example, if L_out is a 1uH, 2mΩ inductor, then Rsen would be set to 5kΩ (with Csen = 0.1uF)

These components must be placed close to the IRPS5401 pins.

For Rdson current sense, the signal from the power stage IOUT pin is reporting IOUT with a gain of 5mV/A. This

signal should be attenuated with a 5:1 divider so that the input to the ISENSE amp is 1mV/A. For noise

immunity reasons, the differential ISENSE signal is offset above GND by connecting the ISEN_A- pin to a

reference voltage. This is usually the 1.8V reference provided by the internal 1.8V LDO

Datasheet

33 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

P5V

12V

Vcc

Vin

BOOT

PWM

L_out

I I_{L_out}

R1

IR3555

Switch

10K

ISEN_A+

ISEN_A-

IOUT

+

-

2.49K

R2

REFIN

To 1.8V Reference

Figure 16

Rdson Current Sensing

The output of this differential current sense amplifier, the gain of which is programmable through an MTP

register d2a_ecs_gain [2:0], is digitized by the monitor ADC. The output code of the ADC is then converted using

the MTP register ecs_scale [7:0] into output current (in Amps), which is reported on the bus and also used for

overcurrent fault detection.

Current is reported using the READ_IOUT PMBus command.

Note:

Switcher outputs that are in the ‘OFF’ state will falsely report an output current if the user sends a

READ_IOUT command to an output that is ‘OFF’. This false output current will cause the

IOUT_OC_WARN bit to assert in the STATUS_IOUT register. The user will need to send the

CLEAR_FAULTS command after the output has been enabled.

9.14

Over-current Protection (OCP)

In internal powerstage mode, the over current (OC) protection is implemented by sensing current through the

R_DS(on)of the Synchronous MOSFET (Sync FET). This method enhances the converter’s efficiency, reduces cost by

eliminating a current sense resistor and eliminates any layout related noise issues. The current limit scheme in

the IRPS5401 uses an internal temperature compensated current source that has the same temperature

coefficient as the R_DS(on)of the Sync FET. As a result, the over-current trip threshold remains almost constant

over temperature. Moreover, the IRPS5401 also incorporates Vgs compensation that limits the OCP variation

with changes in VCC voltage.

The OCP circuit samples the current at the center point of the Sync FET conduction time, and trips the analog

overcurrent comparator if it is more than the overcurrent protection setting as dictated by the PMBus

command IOUT_OC_FAULT_LIMIT. Although the PMBus comand will allow setting the OC threshold up to a

maximum of 15.97A (for internal driver), the internal circuitry saturates the current limit at 4A for Switchers A

and B with the 2A internal power stages and to 8A for Switchers C and D with the 4A power stages. Moreover,

the threshold set by the PMBus command is rounded to the closest higher 250 mA for the 2A power stages and

to the closest higher 500 mA for the 4A power stages.

In external power stage mode, an over current fault is flagged when the digital reading of the output current

exceeds IOUT_OC_FAULT_LIMIT.

Additionally, through the PMBus command IOUT_OC_FAULT_RESPONSE, the user can choose between 3 types

of responses to an overcurrent fault.

Datasheet

34 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

Table 13

OCP Response Mode

Immediate shutdown and then latch off

Immediate shutdown and retry 6 times before latching off, 22ms period

Immediate shutdown and retry indefinitely, 22ms period

The user can cycle out of a latched over current fault by cycling En_x, VCC, VINx, or the PMBus OPERATION

command (with correct ON_OFF_CONFIG setting).

Additionally, in both the internal and external power stage modes, an over current warning is flagged if the

digital reading of the output current exceeds IOUT_OC_WARN_LIMIT.

9.15

Input Voltage Sensing, Telemetry and Faults

For the switchers, the input voltage is fed through a 14:1 divider to a monitor ADC. The digitized voltage is

reported over the PMBus using the READ_VIN command. It is also used to implement an input under voltage

lockout threshold, an input voltage warning threshold and an input voltage over voltage threshold through the

following PMBus commands.

Table 14

Function

PMBus Command

Default

UVLO

VIN_ON

F001h

F000h

E000h

E200h

VIN_OFF

Under voltage warning

Overvoltage fault

VIN_UV_WARN_LIMIT

VIN_OV_FAULT_LIMIT

Additionally, through the PMBus command VIN_OV_FAULT_RESPONSE, the user can choose between 2 types of

responses.

Table 15

VIN OV Response Mode

Ignore

Immediate shutdown and then latch off

The user can cycle out of a latched VIN Overvoltage fault by cycling En_x, VCC, or the PMBus Operation

command.

Datasheet

35 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

9.16

Die Temperature Sensing, Telemetry and Faults

The IRPS5401 uses on-die temperature sensing for accurate temperature reporting and over temperature

detection. Also, to account for temperature gradients across the die, temperature sensing is actually done by

two separate sense circuits at different locations on the die. So, Switchers A and B share one temperature

sensor, while Switchers C and D as well as the LDO share another temperature sensor. Therefore, the

READ_TEMPERATURE PMBus command reports the same temperature on Switchers A and B. Also, Switchers C

and D as well as the LDO report the same temperature. The reporting resolution is 0.250°C.

PMBus commands OT_FAULT_LIMIT and OT_WARN_LIMIT allow the user to set the over temperature fault and

warning thresholds respectively.

Additionally, through the PMBus command OT_ _FAULT_RESPONSE, the user can choose between 3 types of

responses to an over temperature fault, i.e., when the digital reading of the temperature exceeds

OT_FAULT_LIMIT.

Table 16

OT Response Mode

Ignore

Immediate shutdown and then latch off

Auto restart if fault condition disappears

The user can cycle out of a latched over temperature fault by cycling En_x, VCC or the PMBus Operation

command.

9.17

Power Sequencing and Global Faults

The IRPS5401 provides flexibility in sequencing the startup and shutdown of the five outputs via the following

PMBus commands:

Table 17

Output

Sequencing Function

Startup

PMBus command

TON_DELAY

Default

Switchers A,B,C and D

F800h

F004h

F800h

F004h

F800h

TON_RISE

Shutdown

Startup

TOFF_DELAY

TOFF_FALL

TON_DELAY

LDO

The figure below shows the four outputs starting up and shutting down with each output delayed 0.5ms from

the previous.

Datasheet

36 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

Figure 17

VO sequencing

An extra level of flexibility in sequencing the different outputs is provided by the Global Faults feature in

IRPS5401. This is a useful feature that forces all 5 rails to shut down in response to a fault that shuts down any

one of the rails. This is enabled by setting an MTP register bit global_fault_en. The figure below shows the

response of all the IRPS5401 outputs in response to a shutdown of Switcher A by an output over voltage fault

when global_fault_en=1, enabling global fault shutdown and global_fault_en=0, disabling global fault

shutdown.

Figure 18

Global_fault_en=1

Figure 19

Global_fault_en=0

Datasheet

37 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

9.18

Sleep

The IRPS5401 has an input pin, SLEEP#, which can be pulled low to act as a master disable for all the rails if MTP

register bit, por_sleep_mode_en, is set. In fact, pulling this pin low will put the device into an ultra-low power

state with <10 uA quiescent current. It will cause the 1.8V to go low, disable all communication and force a

power-on reset, so that the contents of all the volatile registers are lost and restored to their reset values. If this

pin is pulled high again, the device has to go through a POR cycle again requiring a full MTP load.

9.19

Combined Switcher C and D Operation

Switchers C and D may be combined into a single output and operated in parallel to support load currents up to

8A. In order to do this an MTP register bit, combine_outputs_c_d, must be set to 1. In this mode Switcher C and

D SW pin output are 180° out of phase. Switcher C takes over the error voltage sensing and the control loop and

the internal PWM_C signal is used for the internal power stages of both loops C and D. The table below

summarizes the modification to the reporting, fault and warning thresholds as a result of combining Switchers

C and D. Any PMBus command to Switcher D will be NACK’d

Table 18

PMBus Command

to Switcher C

READ_IOUT

Response

Will report the total Switcher C+D output current

READ_VIN

Will report the Switcher C input voltage (VIN_D and VIN_C

must be connected to the same input)

READ_IIN

Will report the total input current for Switcher C+D

Will set the Switcher C and D FAULT value to ½ this value

Will set the Switcher C and D WARN value to ½ this value

Will be applied to Switcher C

IOUT_OC_FAULT_LIMIT

IOUT_OC_WARN_LIMIT

VIN_ON

VIN_OFF

(VIN_D and VIN_C must be connected to the same input)

Will be applied to the total Switcher C+D output current

IOUT_CAL_OFFSET

9.20

Linear Regulator

The IRPS5401 also has a linear regulator (LDO) in addition to the four switchers. This regulator can accept a

wide input voltage range from 1.2V to 5.5V and provide output voltages from 0.5V to 3.3V, delivering up to 0.5A

of continuous current with a low dropout voltage of 0.6V. Moreover, the regulator can be configured using an

MTP register bit ldo_track_config. To operate in source-only mode, set ldo_track_config to 0. To operate in

tracking mode, set ldo_track_config to 1. The tracking mode of operation makes it ideal for use in memory

termination tracking applications (Vtt). The LDO also supports a manufacturer specific PMBus command,

MFR_LDO_MARGIN, to allow margining the output voltage ±15%.

The reference voltage for the LDO is nominally 0.5V and hence a resistor divider is needed from Vo_LDO to FB_L

to generate output voltages higher than 0.5V. In tracking mode, the reference is an internal 2:1 divider to

Vin_LDO. It should be noted here that for the LDO, the VOUT_OV_FAULT_LIMIT, VOUT_UV_FAULT_LIMIT,

OUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT PMBus commands are Read-Only, and they report the

corresponding thresholds calculated internally based on either 1/2Vin_LDO (tracking mode) or on the contents

of an MTP register ldo_target_vout [7:0] (non-tracking mode).

Datasheet

38 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

9.21

LDO Monitoring and Faults

Unlike the switcher loops, fault detection for all LDO faults except overcurrent fault relies on digital monitoring

and digital comparison.

9.22

Output Voltage Reporting, Output Overvoltage Protection and

Undervoltage Protection

The output voltage is fed through an internal 3.2:1 divider to a 10-bit monitor ADC. The digitized voltaged is

then reported on the PMBus using the READ_VOUT command. It is this MTP register that is used to “tell” the

device what the target output voltage is based on the 0.5V reference and the feedback divider. This register has

a resolution of 1/64V.

The various output voltage fault and warning thresholds are shown in the table below:

Table 19

Non-Tracking

125% target voltage

75% target voltage

112.5% target voltage

87.5% target voltage

Tracking

OV Fault limit

UV Fault limit

OV Warn limit

UV Warn limit

125% (Vin_LDO/2)

75% (Vin_LDO/2)

112.5% (Vin_LDO/2)

87.5% (Vin_LDO/2)

The responses to both the overvoltage and undervoltage faults can be programmed to either ignore or to

shutdown, similar to the switchers.

9.23

Input Voltage Reporting, Input UVLO and Input Overvoltage Protection

The input voltage is fed through an internal 6.4:1 divider to a 10-bit monitor ADC. The digitized voltaged is then

reported on the PMBus using the READ_VIN command. It is also used to implement an input under voltage

lockout threshold, an input under voltage warning threshold and an input over voltage threshold through the

following PMBus commands

Table 20

Function

PMBus Command

Default

UVLO

VIN_ON

D808h

D800h

C800h

CAC0h

VIN_OFF

Under voltage Warning

Overvoltage fault

VIN_UV_WARN_LIMIT

VIN_OV_FAULT_LIMIT

Additionally, through the PMBus command VIN_OV_FAULT_RESPONSE, the user can choose to ignore a VIN

over voltage fault or to shut down in response to it.

The user can cycle out of a latched VIN over voltage fault by cycling Enable, VCC or the PMBus Operation

command.

9.24

Over Current Protection

The PMBus command IOUT_OC_FAULT_LIMIT is implemented as Read_Only for the LDO, and it reads 0.72A.

Thus, the LDO has a fixed overcurrent limit of 0.72A. An internal analog control loop limits the current to this

threshold and hence causes the output voltage to drop. When the output voltage drops below the UV fault limit

Datasheet

39 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

of the LDO, it flags a UV fault (rather than an over current fault), but still responds based on the setting of

IOUT_OC_FAULT_RESPONSE (constant current limiting or shutdown).

Further, if IOUT_OC_FAULT_RESPONSE is configured for a constant current response; an additional MTP bit,

ldo_foldback_enable, can be configured to allow for a current limit foldback response when the UV fault limit is

exceeded. The ldo_foldback_enable configuration with constant current response will further reduce the

overcurrent limit of 0.72A to ~1/4 of this value, or ~0.18A, after the UV fault limit is exceeded.

The output current can be read on the PMBus using the READ_IOUT command.

9.25

I2C Security

The IRPS5401 provides robust and flexible security options to meet a wide variety of customer applications.

A combination of hardware pin and software password prevents accidental overwrites, discourages hackers,

and secures custom configurations and operating data.

The following MTP registers can be used to set the Read and Write Security Zones.

Table 21

Register

Description

Default

Write_protect_section

Choose among 3 options 1) No protection or Open zone 2)

Protect only configuration registers or No Configuration zone 3) or Open zone

Protect all registers or Secure zone

No protection

Read_protect_section

Choose among 4 options 1) No protection or Open zone 2)

Protect only configuration registers or No Configuration zone 3) or Open zone

Telemetry zone 4) Protect all registers or Secure zone

No protection

The tables below describe the access levels in each of these security zones.

Table 22

Read Security Zones

Zone

Locked

Unlocked

Open

All

No Configuration

Telemetry

Debug & Telemetry

Telemetry

Secure

None

Table 23

Write security zones

Zone

Locked

Unlocked

Open

All

No Configuration

Secure

Debug & Telemetry

None

Further, the following protection modes or methods are available.

Datasheet

40 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

Table 24

Read or Write Unlock Options

Password Only

Pin Only

Pin & Password

Lock Forever

9.26

Password Protection

The system designer can set any 16-bit password (other than 00h) and this is stored in MTP in the register

usr_password[15:0]. To unlock, a user must write the correct password into a “Password Try” register called

usr_try_password[15:0] which is a volatile read/write register. To lock, write an incorrect password into the

“Password Try” register. After a certain number of incorrect tries, the IC will lock up to prevent unauthorized

access.

The following pseudo-code illustrates how to change a password:

#first unlock the IC

Write old password to R/W Try register

#now write new password into MTP

Write new password to the MTP Password register

# password change complete, status is locked

#Need to write new password to Try register to unlock

9.27

Pin Protection

The ADDR_PROT pin is a dual function pin. When the IC is enabled, the resistor value is latched and stored for

use in the I2C address offset function. Thereafter, the pin acts entirely as a PROTECT pin. If enabled, the

PROTECT pin must be driven high to unlock and low to lock. Note, if the resistor address offset function is being

used, care must be taken to allow the IC to read the resistor value before driving the pin high or low to set the

security state otherwise an erroneous address offset value may be latched in.

Datasheet

41 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Description

Recommended Circuit and Operating Parameters for Internal Switchers

Table 25

Min L_out for Min C_out for

Input

Voltage

Output

Voltage

Switching 1Ap-p inductor

Frequency

ripple ¹

kHz

800

±3% AC

regulation ²

Kp ³

Decimal

35

Ki ³

Decimal

42

V

uH

1.1

1.6

2

uF

12

0.5 to 1

1 to 1.5

1.5 to 2

2 to 2.5

2.5 to 3.3

3.3 to 5

0.5 to 1

1 to 1.5

1.5 to 2

2 to 2.5

2.5 to 3.3

3.3 to 5

0.5 to 1

1 to 1.5

1.5 to 2

2 to 2.5

2.5 to 3.3

7 x 22uF

6 x 22uF

5 x 22uF

4 x 22uF

3 x 22uF

7 x 22uF

6 x 22uF

5 x 22uF

4 x 22uF

3 x 22uF

7 x 22uF

6 x 22uF

5 x 22uF

4 x 22uF

36

43

38

43

2.5

3

40

44

42

46

3.6

1.1

1.5

2

42

50

9

5

36

43

37

43

38

43

2.2

2.7

1

40

44

42

46

42

50

38

44

1.3

1.5

38

45

40

48

41

50

42

53

Note:

1. 1A p-p = 25% of IMAX on the 4A rail, 50% of IMAX on the 2A rails

2. With 1A load step, 5A/us slew rate

3. Fco ~ 50kHz MIN, PWM jitter ~ 20% of pulse width MAX

Datasheet

42 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Layout Guidelines

10

Layout Guidelines

1. The IRPS5401 can supply relatively large amounts of output current from four separate outputs. The ability

of the part to dissipate the heat generated in the part is a concern and as such as much copper as possible

should be dedicated on the top layer to GND, VIN, and SW to maximize cooling

2. Place output inductors as close as possible to the SW nodes to minimize the length of the copper area of the

SW node. This will help to minimize the parasitic capacitance and radiated emissions

3. The PGND thermal pad (pin 57) must be connected to a dedicated GND plane with VIAS as shown.

Additional internal GND layers should also be connected to the VIAS as well

4. Make PCB patterns for VIN, SW, VOUT, and GND as broad as possible

5. Decouple VIN with a minimum 1uF X7R type MLCC as close as possible to the VIN pin

6. Decouple VCC to AGND pin with 1uF X7R MLCC

7. Connect VCC to VDRV with 2Ω resistor and decouple VDRV to PGND with 1uF X7R MLCC

8. Connect MTP and ADDR_PROT resistors to AGND

9. Decouple MTP and ADDR_PROT pins with 10nF X7R MLCC to AGND

10. There must be a single point contact from AGND to PGND

11. Route sensitive nets away from SW nodes

12. Place a GND plane on the layer 2, the layer directly underneath the top side components

13. Do not allow switching current, including pulsing input currents, to be routed under the device

14. Keep the switching current loops as small as possible

15. If a scaling resistors divider is used, the lower resistor must be terminated to PGND

16. If a 2:1 scaling resistor divider is used, the recommended value is 249Ω, 1%

Datasheet

43 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Layout Guidelines

10.1

Sample layout

Figure 20

LAYER 1-TOP SIDE COMPONENTS PLUS POWER PLANE

Figure 21

LAYER 2 – GROUND PLANE

Figure 22

LAYER 3 – Signal Layer

Datasheet

44 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Layout Guidelines

Figure 23

LAYER 4 – GrouND Plane

Figure 24

LAYER 5 – Power PLANE

Figure 25

LAYER 6 – Power PLANE

Datasheet

45 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Layout Guidelines

Figure 26

LAYER 7 – GROUND PLANE

Figure 27

LAYER 8 – Botton side comp plus POWER and GROUND PLANES

Datasheet

46 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Typical Performance

11

Typical Performance

VIN=12V, VOUT=2.5V, IOUT=4A, TAMB=25°C

20mVp-p

250mVp-p

10mV/div,

Infinite persistence

20MHz BW

500mV/div,

20MHz BW

Figure 28

Output ripple

Figure 29

Figure 31

Figure 33

Input ripple

±3% deviation

Vpeak = 13.6V

Jitter = 11.2nsec

50mV/div, 20usec/div

1A Step, 2.5A/usec

20MHz BW

2V/div, 40nsec/div

Infinite persistence

500MHz BW Hardware limit

Figure 30

Transient response

Switch node peak and jitter

0msec delay,

1msec rise

PG_ON=2.4V

200usec/div

0msec delay,

1msec fall

PG_OFF=2.3V

200usec/div

PG

VO

ENABLE

Figure 32

Enable start

Enable shut down

Datasheet

47 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Typical Performance

11.1

Typical thermal performance at max output power

VIN=12V, VOUT A, B, C, D=5V, IOUT A, B, C, D = 2A, 2A, 4A, and 4A, POUT = 60W, TAMB=25°C

VIN=12V, VOUT=5V, FSW=800KHz

95

90

85

80

75

70

65

60

55

8

7

6

5

4

3

2

1

0

10

20

30

40

Output Power (W)

50

60

70

Figure 34

Total System Efficiency and power dissipation from 0W to 60W out

Total system power dissipation is 6.9W.

IRPS5401 power dissipation is estimated

at ~5.32W

Figure 35

Temperature rise at room temp, natural convection cooling, 60W out

Figure 36

PCB construction details (8 layers, 11.6 oz total Cu Thickness)

Datasheet

48 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

PMBUS Commands

12

PMBUS Commands

Table 26

PMBus commands (See UN0049 for more details)

Default

PMBUS

PROTOCOL

COMMAND

CODE

COMMAND

DESCRIPTION

Read/Write

Byte

Read/Write

Byte

N/A

PAGE

00h

01h

Allows access to each output via paging.

Enables or disables the output and controls 00h

margining.

OPERATION

Configures the combination of Enable pin

and OPERATION command needed to turn

the unit on and off.

17h

Read/Write

Byte

ON_OFF_CONFIG

02h

03h

N/A

00h

CLEAR FAULTS

PAGE_PLUS_READ

Send Byte

Block Read 06h

Read/Write

Byte

Clear contents of Fault registers

Provides protection from accidental

changes

WRITE_PROTECT

10h

N/A

RESTORE_DEFAULT_ALL

STORE_USER_ALL

RESTORE_USER_ALL

Send Byte

12h

15h

16h

Reloads the OTP

Stores the user OTP section

Reloads the user OTP section

Returns 1010xxxx to indicate Packet Error

Checking is supported and Maximum bus

speed is 400kHz

CAPABILITY

Read Byte

19h

Set to prevent warning or fault conditions

from asserting the SMBALERT# signal. Write

command code for STATUS register to be

masked in the low byte, the bit to be

masked in the High byte.

Sets the format for VOUT related

commands. Linear mode, -8, -9, and -12

exponents supported. No LDO support

N/A

18h

Block

Write/

Block Read

Process Call

SMBALERT_MASK

1Bh

Read/Write

Byte

VOUT_MODE

VOUT_COMMAND

VOUT_TRIM

20h

21h

22h

24h

Sets the voltage to which the device should 0000h

set the output. Format according to

VOUT_MODE. No LDO support

Read/Write

Word

Applies a fixed offset to the output voltage

command value. Format according to

VOUT_MODE. No LDO support

Sets an upper limit on the output voltage

the unit can command. Format according

to VOUT_MODE. No LDO support

Sets the margin high voltage when

commanded by OPERATION. Must be in

format determined by VOUT_MODE. No

LDO support

Sets the margin low voltage when

commanded by OPERATION. Must be in

format determined by VOUT_MODE. No

LDO support

Sets the rate at which the output changes

voltage due to VOUT_COMMAND or

0000h

0800h

0000h

Read/Write

Word

Read/Write

Word

VOUT_MAX

Read/Write

Word

VOUT_MARGIN_HIGH

VOUT_MARGIN_LOW

25h

0000h

E808h

Read/Write

Word

26h

27h

Read/Write

Word

VOUT_TRANSITION_RATE

Datasheet

49 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

PMBUS Commands

Default

PMBUS

COMMAND

CODE

COMMAND

PROTOCOL

DESCRIPTION

OPERATION commands.

mV/s; Exp = -3. No LDO support

Supports scale factor 1 and 0.5. No LDO

support

Sets the switching frequency in kHz. Exp =

0, 1. No LDO support

Read/Write

Word

Read/Write

FREQUENCY_SWITCH

Word

E808h

0320h

VOUT_SCALE_LOOP

29h

33h

Sets the value of the input voltage at which SW;F001h

Read/Write

VIN_ON

Word

35h

36h

the unit should begin power conversion.

Exp = -2 for Switchers, -5 for LDO.

Sets the value of the input voltage that the

unit, once operation has started, should

stop power conversion.

LDO;D808

h

SW;F000h

LDO;D800

h

Read/Write

VIN_OFF

Word

Exp = -2 for Switchers, -5 for LDO

Used to null out any offsets in the output

current sensing circuitry. Exp = -10 for LDO, LDO:B000

-6 for Internal, -3 for External

Sets fault limit relative to VOUT…

LDO=read only

SW:D000h

Read/Write

IOUT_CAL_OFFSET

Word

39h

40h

41h

h

Read/Write

VOUT_OV_FAULT_LIMIT

Word

8000h

Instructs the device on what action to take

in response to an output over voltage fault.

Only shutdown and ignore are supported.

Sets the value of the output voltage,

measured at the sense or output pins, that

causes an output overvoltage warning.

Format as determined by VOUT_MODE…

LDO=read only

Sets the value of the output voltage,

measured at the sense or output pins, that

causes an output voltage low warning.

Format as determined by VOUT_MODE…

LDO=read only

Sets fault limit relative to VOUT…

LDO=read only

Instructs the device on what action to take

in response to an output under voltage

fault. Only shutdown and ignore are

supported.

00h

VOUT_OV_FAULT_RESPON Read/Write

SE

Byte

8000h

Read/Write

Word

VOUT_OV_WARN_LIMIT

42h

43h

0000h

Read/Write

Word

VOUT_UV_WARN_LIMIT

VOUT_UV_FAULT_LIMIT

Read/Write

Word

0000h

00h

44h

45h

VOUT_UV_FAULT_RESPON Read/Write

SE

Byte

Sets the value of the output current, in

amperes, that causes the overcurrent

detector to indicate an overcurrent fault

condition. Set by writing this command in

Linear format. Exp = -5 for internal and -2

for external … LDO=read only

SW:D900h

LDO:C0B8

h

Read/Write

Word

IOUT_OC_FAULT_LIMIT

46h

47h

Instructs the device on what action to take

SW:F8h

in response to an output overcurrent fault. LDO:C0h

Only C0h (latch off), F8h (hiccup forever),

and F0h (hiccup 6 times then latch off) are

supported…LDO supports C0h (latch off)

and 00h (current limiting)

IOUT_OC_FAULT_RESPONS Read/Write

Byte

E

Datasheet

50 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

PMBUS Commands

Default

PMBUS

COMMAND

CODE

COMMAND

PROTOCOL

DESCRIPTION

Sets the value of the output current that

SW:D900h

causes an output over current warning. Set LDO:C0B8

Read/Write

IOUT_OC_WARN_LIMIT

Word

4Ah

by writing this command in Linear format.

Exp = -10 for LDO, -5 for internal and -2 for

external.

h

Sets the temperature in °C that would

should indicate an over temperature fault.

Linear format, Exp = 0.

Instructs the device on what action to take

in response to an over temperature fault.

Only 80h (shutdown), 00h (ignore), and C0h

(inhibit then restart) are supported.

Sets the temperature in °C that would

indicate an over temperature warning

alarm. Linear format, Exp = 0.

0080h

00h

Read/Write

OT_FAULT_LIMIT

Word

4Fh

50h

Read/Write

OT_FAULT_RESPONSE

Byte

0080h

Read/Write

OT_WARN_LIMIT

Word

51h

55h

Sets the value of the input voltage that

causes an input overvoltage fault. Exp = -4

for switchers, -7 for LDO

SW:E200h

LDO:CAC0

h

Read/Write

VIN_OV_FAULT_LIMIT

Word

Instructs the device on what action to take

in response to an input overvoltage fault.

Only 80h (shutdown) and 00h (ignore) are

supported.

00h

Read/Write

VIN_OV_FAULT_RESPONSE

Byte

56h

Sets the value of the input voltage that

causes an input voltage low warning. Exp = LDO:C800

-4 for switchers, -7 for LDO

SW:E000h

Read/Write

VIN_UV_WARN_LIMIT

Word

58h

5Eh

5Fh

60h

h

Sets the output voltage at which the

POWER_GOOD signal will be asserted.

Format according to VOUT_MODE.

Sets the output voltage at which the

POWER_GOOD signal will be de-asserted.

Format according to VOUT_MODE.

Sets the time, in milliseconds, from when a F800h

start condition is received until the output

voltage starts to rise. Exp = -1.

0000h

Read/Write

POWER_GOOD_ON

Word

0000h

Read/Write

POWER_GOOD_OFF

Word

Read/Write

TON_DELAY

Word

Sets the time, in milliseconds, from when

the output starts to rise until the voltage

has entered the regulation band.

Exp = -2. No LDO support

Sets an upper limit, in milliseconds, on how F004h

long the unit can attempt to power up the

output without reaching the output under

voltage fault limit. Exp = -2.

F004h

Read/Write

TON_RISE

Word

61h

62h

Read/Write

TON_MAX_FAULT_LIMIT

Word

Instructs the device on what action to take

in response to a TON_MAX fault. Only 80h

(shutdown) and 00h (ignore) are

supported.

Sets the time, in milliseconds, from when a F800h

stop condition is received until the unit

00h

TON_MAX_FAULT_RESPON Read/Write

63h

64h

SE

Byte

Read/Write

Word

TOFF_DELAY

starts ramping down to 0V. Exp = -1. No

Datasheet

51 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

PMBUS Commands

Default

PMBUS

COMMAND

CODE

COMMAND

PROTOCOL

DESCRIPTION

LDO support

Sets the time, in milliseconds, for the

output to ramp to 0V. Exp = -2. No LDO

support

Returns 1 byte where the bit meanings are: N/A

Bit <7> Reserved

Bit <6> Output off (due to fault or enable)

Bit <5> Output over-voltage fault

Bit <4> Output over-current fault

Bit <3> Input Under-voltage fault

Bit <2> Temperature fault

F004h

Read/Write

TOFF_FALL

Word

65h

78h

Read/Write

STATUS_BYTE

Byte

Bit <1> Communication/Memory/Logic

fault

Bit <0>: None of the above

Returns 2 bytes where the Low byte is the

same as the STATUS_BYTE data. The High

byte has bit meanings are:

Bit <7> Output high or low fault

Bit <6> Output over-current fault

Bit <5> Input under-voltage fault

Bit <4> MFR_SPECIFIC

N/A

Read/Write

STATUS_WORD

Word

79h

7Ah

Bit <3> POWER_GOOD#

Bit <2:0> Reserved

Bit <7> Output Over voltage Fault

Bit <6> Output Over voltage Warning

Bit <5> Output Under voltage Warning

Bit <4> Output Under voltage Fault

Bit <3> VOUT_MAX Warning

Bit <2> TON_MAX_FAULT

Bit <1> Reserved

N/A

Read/Write

STATUS_VOUT

Byte

Bit <0> Reserved

Bit <7> Output Over current Fault

Bit <6> Reserved

Bit <5> Output Over current Warning

Bit <4:0> Reserved

Bit <7> Input Overvoltage Fault

Bit <6> Reserved

Bit <5> Input Under voltage Warning

Bit <4> Reserved

N/A

Read/Write

STATUS_IOUT

Byte

7Bh

7Ch

Read/Write

STATUS_INPUT

Byte

Bit <3> Unit Off For Insufficient Input

Voltage

Bit <2:0> Reserved

Bit <7> Over Temperature Fault

Bit <6> Over Temperature Warning

Bit <5:0> Reserved

Returns 1 byte where the bit meanings are: N/A

Bit <7> Invalid or unsupported command

Bit <6> Invalid or unsupported data or send

too may bytes

N/A

Read/Write

STATUS_TEMPERATURE

Byte

7Dh

7Eh

Read/Write

STATUS_CML

Byte

Datasheet

52 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

PMBUS Commands

Default

PMBUS

COMMAND

CODE

COMMAND

PROTOCOL

DESCRIPTION

Bit <5> PEC fault

Bit <4:2> Reserved

Bit <1> Other communication fault not

listed here

Bit <0> Reserved

Returns the input voltage in Volts. Exp = -5

for Switchers and -7 for LDO

Returns the input current in Amperes. Exp = N/A

-7 for Internal, and -4 for External

Returns the output voltage in the format

set by VOUT_MODE

N/A

READ_VIN

READ_IIN

Read Word

88h

89h

8Bh

N/A

READ_VOUT

Returns the output current in Amperes.

Exp = -10 for LDO, -6 for Internal, and -3 for

External

Returns the addressed loop temperature in N/A

°C. Switcher A and B have a common

sensor, Switcher C, D and LDO have a

common sensor. Exp = -2

N/A

READ_IOUT

Read Word

8Ch

8Dh

READ_TEMPERATURE_1

Returns the output power in Watts. Exp = -

6 for LDO, -5 for Internal, and -2 for External

Returns the input power in Watts. Exp = -6

for LDO, -5 for Internal, and -2 for External

Reports PMBus Part I rev 1.1 & PMBus Part

II rev 1.2

N/A

READ_POUT

READ_PIN

Read Word

Read Byte

96h

97h

98h

N/A

22h

PMBUS_REVISION

Block

004952h

The MFR_ID is set to IR (ASCII 52 49) unless

programmed different in the USER registers

of the controller.

Read/Write

Byte count

= 3

MFR_ID

99h

9Ah

9Bh

Block

00000052

h

Read/Write

byte count

= 4

MFR_MODEL

MFR_REVISION

Block

00000002

h

Read/Write

byte count

= 4

Block Read

byte count

= 1

Block Read

byte count

= 1

Custom

MFR

protocol

Read/Write

Byte

Returns a 1 byte code with the following

values:

52h = IRPS5401

N/A

IC_DEVICE_ID

ADh

AEh

D0h

IC_DEVICE_REV

The IC revision that is stored inside the IC

MFR_REG_ACCESS

MFR_I2C_ADDRESS

Read/Write I2C registers

Reads I2C address

D6h

B8h

Read/Write

Word

Sets delay from PG threshold crossed to PG 0000h

assertion.

MFR_TPGDLY

Datasheet

53 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

PMBUS Commands

Default

PMBUS

COMMAND

CODE

COMMAND

PROTOCOL

DESCRIPTION

Exp = 0

Write a 1 to force continuous current mode 01h

(CCM) and disable constant on time (COT)

mode at light load. No LDO support

Read/Write

MFR_FCCM

Byte

B9h

DBh

Reads maximum VOUT recorded since the

last read. Reading the register

automatically clears the value. Resolution

set by VOUT_MODE

N/A

MFR_VOUT_PEAK

MFR_IOUT_PEAK

Read Word

Reads maximum IOUT recorded since the

last read. Reading the register

automatically clears the value.

Exp = -10 for LDO, -6 for Internal, and -3 for

External

N/A

DCh

Reads maximum temp recorded since the

last read. Reading the register

automatically clears the value.

Exp = 0, -2 for LDO

N/A

00h

MFR_TEMPERATURE_PEAK Read Word

DDh

DEh

Read/Write

MFR_LDO_MARGINING

Byte

Allows margining of the LDO output ± 15%

Note:

1. If a low to high to low transaction occurs on the DIO line while the CLK is low after the a START or RESTART

and before the first CLK pulse occurs, the transaction will be NAK’d

2. The MFR_LDO_MARGIN command is readable and writeable but cannot be saved in the configuration file

3. The MFR_TPGDLY command is readable and writeable but cannot be saved in the configuration file

4. To avoid inadvertently setting the MFR_LDO_MARGIN and MFR_TPGDLY commands to non-0 values, the LDO

VOUT_MODE command must be set to -8, the LDO POWER_GOOD_ON command must be set to 0.109V (or 0V),

and the LDO POWER_GOOD_OFF command must be set to 0.063V (or 0V)

5. To avoid inadvertently masking LDO STATUS_INPUT register bits 5, 6, and 7 and LDO STATUS_TEMPURATURE

bits 7 and 6, the LDO VIN_UV_WARN_LIMIT command must be set to a value no larger than 0.49V

Table 27 PMBus Commands Saved to MTP

OPERATION

VOUT_COMMAND

VOUT_MIN

VIN_OFF

ON_OFF_CONFIG

VOUT_MAX

WRITE_PROTECT

VOUT_TRANSITION_RATE

POWER_MODE

VOUT_MODE

VOUT_SCALE_LOOP

FREQUENCY_SWITCH

IOUT_CAL_GAIN

VOUT_OV_FAULT_LIMIT

VOUT_OV_FAULT_RESPONSE

VOUT_UV_FAULT_LIMIT

OT_FAULT_RESPONSE

IOUT_CAL_OFFSET

VOUT_UV_WARN_LIMIT

OT_FAULT_LIMIT

TON_DELAY

VIN_ON

VOUT_OV_WARN_LIMIT

VIN_UV_WARN_LIMIT IOUT_OC_WARN_LIMIT

OT_WARN_LIMIT VIN_OV_FAULT_LIMIT

IIN_OC_WARN_LIMIT POWER_GOOD_ON

VIN_OV_FAULT_RESPONSE

TON_MAX_FAULT_RESPONSE

IOUT_OC_FAULT_RESPONSE

RESET_TRANSITION_RATE

STATUS_TEMPERATURE (Mask)

STATUS_MFR_SPECIFIC (Mask)

POWER_GOOD_OFF

TON_RISE

TON_MAX_FAULT_LIMIT TOFF_DELAY

TOFF_FALL

VOUT_RESET

POUT_OP_WARN_LIMIT PIN_OP_WARN_LIMIT

STATUS_INPUT (Mask)

STATUS_CML (Mask)

STATUS_VOUT (Mask)

STATUS_IOUT (Mask)

Datasheet

54 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Marking Information

13

Marking Information

Figure 37

Package Marking

Datasheet

55 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Package Information

14

Package Information

Figure 38

Package information

Datasheet

56 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Package Information

14.1

PCB Pad Size

Figure 39

PCB PAD Size

Datasheet

57 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Package Information

14.2

PCB Pad Spacing

Figure 40

PCB PAD Spacing

Datasheet

58 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Package Information

14.3

Solder Paste Stencil Pad Size

Figure 41

Solder paste stencil pad size

Datasheet

59 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Package Information

14.4

Solder Paste Stencil Pad Spacing

Figure 42

Solder paste stencil pad spacing

Datasheet

60 of 61

V 2.8

2022-07-06

IRPS5401 PMIC

Flexible Power Management Unit

Environmental Qualifications

15

Environmental Qualifications

Qualification Level

Industrial

Moisture Sensitivity Level

Human Body Model

7mm x 7mm PQFN

JEDEC Level 2 @ 260°C

Class 1B

(JS-001-2014)

Charged Device Model

(JESD22-C101F)

500V to <1000V

Class C3

>1000V

ESD

RoHS2 Compliant

Yes (6/6)

Datasheet

61 of 61

V 2.8

2022-07-06


型号：	IRPS5401M
厂家：	Infineon
描述：	IRPS5401是一个完整的电源管理单元，可为处理器，FPGA和其他多轨电源系统提供5个输出电压。四个高效可配置开关稳压器和一个拉/灌线性稳压器提供所需的典型电压轨，如核心电压，存储器电压和I / O电压。开关存储稳压器
文件：	总62页 (文件大小：1673K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRPS5401M [INFINEON]

相关型号：

IRPT1053

IRPT1053A

IRPT1053C

IRPT1053CPBF

IRPT1053D

IRPT1053E

IRPT1056

IRPT1056A

IRPT1057

IRPT1057A

IRPT1058

IRPT1058A