IRL7472L1 [INFINEON]
The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. ;
| 型号： | IRL7472L1 |
| 厂家： | 
Infineon |
| 描述： | The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. |
| 文件： | 总12页 (文件大小：527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
StrongIRFET™
IRL7472L1TRPbF
DirectFET™ N-Channel Power MOSFET
Application
Brushed Motor drive applications
BLDC Motor drive applications
Battery powered circuits
Half-bridge and full-bridge topologies
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
DC/DC and AC/DC converters
DC/AC Inverters
VDSS
40V
RDS(on) typ.
0.34m
max
@ VGS = 10V
0.45m
0.52m
0.70m
375A
RDS(on) typ.
max
@ VGS = 4.5V
ID (Package Limited)
Benefits
Optimized for Logic Level Drive
Improved Gate, Avalanche and Dynamic dv/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dv/dt and di/dt Capability
Lead-Free, RoHS Compliant
S
S
S
S
S
S
D
D
S
G
S
L8
Standard Pack
Base part number
Package Type
Orderable Part Number
IRL7472L1TRPbF
Form
Quantity
4000
IRL7472L1PbF
Direct FET Large Can (L8)
Tape and Reel
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
700
600
500
400
300
200
100
0
I
= 195A
D
Limited by package
T
= 125°C
= 25°C
J
T
J
2
4
6
8
10 12 14 16 18 20
25
50
75
100
125
150
175
T
, Case Temperature (°C)
C
V
Gate -to -Source Voltage (V)
GS,
Fig 2. Maximum Drain Current vs. Case Temperature
Fig 1. Typical On-Resistance vs. Gate Voltage
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IRL7472L1TRPbF
Absolute Maximum Ratings
Symbol
Parameter
Max.
645
456
68
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)
A
375
1500
IDM
Pulsed Drain Current
Maximum Power Dissipation
Maximum Power Dissipation
Linear Derating Factor
A
PD @TC = 25°C
PD @TA = 25°C
341
W
3.8
0.025
W/°C
V
Gate-to-Source Voltage
Operating Junction and
± 20
VGS
TJ
-55 to + 175
°C
Storage Temperature Range
TSTG
Avalanche Characteristics
EAS (Thermally limited)
308
765
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy
Avalanche Current
mJ
EAS (Thermally limited)
IAR
A
mJ
See Fig.15,16, 23a, 23b
EAR
Repetitive Avalanche Energy
Thermal Resistance
Symbol
Parameter
Typ.
–––
12.5
20
Max.
40
Units
Junction-to-Ambient
RJA
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
Junction-to-PCB Mounted
–––
–––
0.44
–––
RJA
°C/W
RJA
RJC
RJA-PCB
–––
1.0
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
40
––– –––
V
–––
30 ––– mV/°C Reference to 25°C, ID = 5.0mA
V(BR)DSS/TJ
RDS(on)
––– 0.34 0.45
––– 0.52 0.70
VGS = 10V, ID = 195A
m
V
GS = 4.5V, ID = 98A
VGS(th)
IDSS
Gate Threshold Voltage
1.0
1.7 2.5
V
VDS = VGS, ID = 250µA
––– ––– 1.0
––– ––– 150
––– ––– 100
––– ––– -100
––– 1.0 –––
VDS = 40V, VGS = 0V
Drain-to-Source Leakage Current
µA
VDS = 40V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
VGS = 20V
GS = -20V
nA
V
RG
Notes:
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
TC measured with thermocouple mounted to top (Drain) of part.
Used double sided cooling , mounting pad with large heatsink.
Mounted to a PCB with small clip
heatsink (still air)
Mounted on minimum footprint full size
board with metalized back and with
small clip heatsink (still air)
Surface mounted on 1 in. square Cu
board (still air).
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IRL7472L1TRPbF
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
DS = 10V, ID = 195A
gfs
Qg
232 ––– –––
––– 220 330
S
V
ID = 195A
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
95
87
–––
–––
VDS = 20V
nC
VGS = 4.5V
ID = 195A, VDS =0V, VGS = 4.5V
VDD = 20V
ID = 30A
RG = 2.7
––– 133 –––
––– 68 –––
––– 176 –––
––– 174 –––
––– 137 –––
––– 20082 –––
––– 2436 –––
––– 1594 –––
ns
VGS = 4.5V
VGS = 0V
VDS = 25V
ƒ = 10kHz
pF
C
C
oss eff. (ER) Effective Output Capacitance (Energy Related) ––– 2855 –––
oss eff. (TR) Effective Output Capacitance (Time Related) ––– 3544 –––
VGS = 0V, VDS = 0V to 32V
VGS = 0V, VDS = 0V to 32V
Diode Characteristics
Symbol Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
MOSFET symbol
showing the
integral reverse
p-n junction diode.
D
––– –––
341
A
G
ISM
––– –––
––– –––
1500
1.2
S
VSD
Diode Forward Voltage
V
TJ= 25°C, IS =195A, VGS = 0V
dv/dt
Peak Diode Recovery
TJ =175°C, IS =195A,
VDS = 40V
––– 1.3
–––
V/ns
trr
Reverse Recovery Time
–––
–––
––– 103
––– 114
––– 3.1
57
58
–––
–––
–––
–––
–––
TJ = 25° C VR = 34V,
ns
IF = 195A
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
di/dt = 100A/µs
Qrr
IRRM
Reverse Recovery Charge
Reverse Recovery Current
nC
A
Notes:
Package limit current based on source connection technology
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.016mH, RG = 50, IAS = 195A, VGS =10V.
ISD ≤ 195A, di/dt ≤ 984A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS
.
Coss eff. (ER) is a fixed capacitance that gives the
R is measured at TJ approximately 90°C.
same energy as Coss while VDS is rising from 0 to 80% VDSS.
Limited by TJmax, starting TJ = 25°C, L = 1.0mH, RG = 50, IAS = 39A, VGS =10V.
Silicon limit current based on maximum allowable junction temperature TJmax.
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IRL7472L1TRPbF
10000
1000
100
10
10000
1000
100
10
VGS
15V
10V
6.0V
5.0V
4.5V
4.0V
3.5V
3.0V
VGS
15V
10V
6.0V
5.0V
4.5V
4.0V
3.5V
3.0V
TOP
TOP
BOTTOM
BOTTOM
3.0V
3.0V
60µs PULSE WIDTH
Tj = 175°C
60µs PULSE WIDTH
Tj = 25°C
1
1
0.01
0.1
1
10
100
0.01
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 3. Typical Output Characteristics
Fig 4. Typical Output Characteristics
10000
1000
100
10
2.0
1.7
1.4
1.1
0.8
0.5
I
= 195A
= 10V
D
V
GS
T
= 175°C
T
= 25°C
J
J
V
= 10V
DS
60µs PULSE WIDTH
1.0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
100000
10000
1000
14
V
C
= 0V,
f = 10 KHZ
GS
I
= 195A
= C + C , C SHORTED
D
iss
gs
gd ds
C
= C
12
10
8
rss
gd
V
V
= 32V
= 20V
DS
DS
C
= C + C
oss
ds
gd
C
iss
C
oss
6
C
rss
4
2
0
1
10
100
0
60 120 180 240 300 360 420 480 540 600
, Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
DS
Q
G
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
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IRL7472L1TRPbF
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
1000
100
10
100µsec
T
= 175°C
T
= 25°C
J
J
1msec
Limited by Package
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
1.4
GS
1.0
0.1
0.2
0.4
V
0.6
0.8
1.0
1.2
1.6
0.1
1
10
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode Forward Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
50
Id = 5.0mA
49
48
47
46
45
44
43
42
41
-5
0
5
10 15 20 25 30 35 40
-60
-20
20
60
100
140
180
T
, Temperature ( °C )
J
V
Drain-to-Source Voltage (V)
DS,
Fig 11. Drain-to-Source Breakdown Voltage
Fig 12. Typical Coss Stored Energy
1.8
Vgs = 3.5V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Vgs = 4.0V
Vgs = 4.5V
Vgs = 5.5V
Vgs = 6.0V
Vgs = 8.0V
Vgs = 10V
0
20 40 60 80 100 120 140 160 180 200
, Drain Current (A)
I
D
Fig 13. Typical On-Resistance vs. Drain Current
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IRL7472L1TRPbF
1
0.1
D = 0.50
0.20
0.10
0.05
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 125°C and
Tstart =25°C (Single Pulse)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 125°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Avalanche Current vs. Pulse Width
350
300
250
200
150
100
50
TOP
Single Pulse
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 )
1.Avalanche failures assumption:
BOTTOM 1.0% Duty Cycle
= 195A
I
D
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
0
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
25
50
75
100
125
150
175
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
I
av = 2T/ [1.3·BV·Zth]
Fig 16. Maximum Avalanche Energy vs. Temperature
EAS (AR) = PD (ave)· av
t
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IRL7472L1TRPbF
20
18
16
14
12
10
8
2.5
2.0
1.5
1.0
0.5
0.0
I
= 117A
= 34V
F
V
R
T = 25°C
J
T = 125°C
J
I
I
I
= 250µA
= 1.0mA
= 1.0A
D
D
D
6
4
2
100
200
300
400
500
600
-60 -40 -20 0 20 40 60 80 100120140160180
, Temperature ( °C )
di /dt (A/µs)
T
F
J
Fig 17. Threshold Voltage vs. Temperature
Fig 18. Typical Recovery Current vs. dif/dt
20
18
16
14
12
10
8
1000
900
800
700
600
500
400
300
200
100
I
= 195A
= 34V
F
I
= 117A
= 34V
V
F
R
V
T = 25°C
R
J
T = 25°C
T = 125°C
J
J
T = 125°C
J
6
4
2
100
200
300
400
500
600
100
200
300
400
500
600
di /dt (A/µs)
F
di /dt (A/µs)
F
Fig 20. Typical Stored Charge vs. dif/dt
Fig 19. Typical Recovery Current vs. dif/dt
1000
I
F
= 195A
= 34V
900
V
R
800
700
600
500
400
300
200
100
T = 25°C
J
T = 125°C
J
100
200
300
400
500
600
di /dt (A/µs)
F
Fig 21. Typical Stored Charge vs. dif/dt
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IRL7472L1TRPbF
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V
(BR)DSS
t
p
15V
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
I
0.01
t
AS
p
Fig 23a. Unclamped Inductive Test Circuit
Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit
Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
VDD
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 25b. Gate Charge Waveform
Fig 25a. Gate Charge Test Circuit
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2016-10-14
IRL7472L1TRPbF
DirectFET™ Board Footprint, L8 Outline
(Large Size Can, 8-Source Pads)
Please see DirectFET™ application note AN-1035 for all details regarding the assembly of DirectFET™.
This includes all recommendations for stencil and substrate designs.
G = GATE
D = DRAIN
S = SOURCE
D
D
D
D
D
D
S
S
S
S
S
S
S
S
G
Note: For the most current drawing please refer to website at http://www.irf.com/package/
9
2016-10-14
IRL7472L1TRPbF
DirectFET™ Outline Dimension, L8 Outline
(Large Size Can, 8-Source Pads)
Please see DirectFET™ application note AN-1035 for all details regarding the assembly of DirectFET™.
This includes all recommendations for stencil and substrate designs.
DIMENSIONS
METRIC
IMPERIAL
CODE MIN MAX
MIN
MAX
0.360
0.280
0.236
0.026
0.024
0.048
0.040
0.030
0.017
0.057
0.104
0.215
0.029
0.007
0.003
A
B
C
D
E
F
9.05 9.15
6.85 7.10
5.90 6.00
0.55 0.65
0.58 0.62
1.18 1.22
0.98 1.02
0.73 0.77
0.38 0.42
1.35 1.45
2.55 2.65
5.35 5.45
0.68 0.74
0.09 0.17
0.02 0.08
0.356
0.270
0.232
0.022
0.023
0.046
0.039
0.029
0.015
0.053
0.100
0.211
0.027
0.003
0.001
G
H
J
K
L
L1
M
P
R
DirectFET™ Part Marking
GATE MARKING
LOGO
+
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates "Lead-Free"
Note: For the most current drawing please refer to website at http://www.irf.com/package/
10
2016-10-14
IRL7472L1TRPbF
DirectFET™ Tape & Reel Dimension (Showing component orientation).
LOADED TAPE FEED DIRECTION
+
NOTE: Controlling dimensions in mm
Std reel quantity is 4000 parts. Order as IRF7472L1TRPBF).
DIMENSIONS
METRIC
REEL DIMENSIONS
IMPERIAL
STANDARD OPTION (QTY 4000)
METRIC
IMPERIAL
NOTE: CONTROLLING
DIMENSIONS IN MM
CODE
MIN
MAX
0.476
0.161
0.642
0.299
0.291
0.398
N.C
MIN
MAX
12.10
4.10
A
B
C
D
E
F
4.69
11.90
3.90
15.90
7.40
7.20
9.90
1.50
1.50
CODE
MIN
12.992
0.795
0.504
0.059
3.900
N.C
MAX
N.C
MIN
MAX
N.C
0.154
0.623
0.291
0.283
0.390
0.059
0.059
A
B
C
D
E
F
330.00
20.20
12.80
1.50
16.30
7.60
N.C
N.C
13.20
N.C
0.520
N.C
7.40
10.10
N.C
99.00
N.C
3.940
0.880
0.720
0.760
100.00
22.40
18.40
19.40
G
H
1.60
0.063
G
H
0.650
0.630
16.40
15.90
Note: For the most current drawing please refer to website at http://www.irf.com/package/
Qualification Information
Industrial *
(per JEDEC JESD47F† guidelines)
Qualification Level
MSL1
DirectFET (Large -Can)
Moisture Sensitivity Level
RoHS Compliant
(per JEDEC J-STD-020D†)
Yes
† Applicable version of JEDEC standard at the time of product release.
* Industrial qualification standards except autoclave test conditions.
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IRL7472L1TRPbF
Revision History
Date
Comments
Changed datasheet with Infineon logo - all pages.
Changed max Rdson @ 10V/4.5V from “0.59m /0.97m" to “0.45m" / 0.7m" - on pages 1 & 2.
Changed ID @ TC 25C/100C from “564A/399A” to “645A/456A” - on pages 1 & 2.
Changed ID @ TA 25C from “59A” to “68A” - on pages 1 & 2.
Changed Fig.2 -on page 2.
08/09/2016
10/14/2016
Corrected Outline Dimension, L8 Outline on page 10.
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™,
CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™,
GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™,
OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID
FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
Edition 2016-04-19
Published by
Infineon Technologies AG
81726 Munich, Germany
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
Please note that this product is not qualified
according to the AEC Q100 or AEC Q101 documents
of the Automotive Electronics Council.
© 2016 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
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12
2016-10-14
相关型号：
IRL7486M
The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters.
INFINEON
IRL7486MTRPBF
Power Field-Effect Transistor, 209A I(D), 40V, 0.00125ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET
INFINEON
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