IRL40SC209 [INFINEON]

The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. ;
IRL40SC209
型号: IRL40SC209
厂家: Infineon    Infineon
描述:

The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. 

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IR MOSFET  
StrongIRFET™  
IRL40SC209  
HEXFET® Power MOSFET  
Application  
Brushed Motor drive applications  
BLDC Motor drive applications  
Battery powered circuits  
Half-bridge and full-bridge topologies  
Synchronous rectifier applications  
Resonant mode power supplies  
OR-ing and redundant power switches  
DC/DC and AC/DC converters  
DC/AC Inverters  
VDSS  
RDS(on) typ.  
max  
40V  
0.6m  
0.8m  
478A  
ID (Silicon Limited)  
ID (Package Limited)  
300A  
D
Benefits  
S
S
S
Optimized for Logic Level Drive  
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness  
Fully Characterized Capacitance and Avalanche SOA  
Enhanced body diode dV/dt and dI/dt Capability  
Lead-Free*  
S
S
S
G
RoHS Compliant, Halogen-Free  
G
D
S
Gate  
Drain  
Source  
Standard Pack  
Base Part Number  
Package Type  
Orderable Part Number  
Form  
Tape and Reel Left  
Quantity  
IRL40SC209  
D2PAK-7Pin  
800  
IRL40SC209  
500  
400  
300  
200  
100  
0
5.0  
4.0  
3.0  
2.0  
1.0  
0.0  
Limited By Package  
I
= 100A  
D
T
= 125°C  
= 25°C  
J
T
J
25  
50  
75  
100  
125  
150  
175  
2
4
6
8
10 12 14 16 18 20  
T
, Case Temperature (°C)  
C
V
Gate -to -Source Voltage (V)  
GS,  
Fig 2. Maximum Drain Current vs. Case Temperature  
Fig 1. Typical On-Resistance vs. Gate Voltage  
1
2017-05-12  
IRL40SC209  
Absolute Maximum Rating  
Symbol  
Parameter  
Max.  
Units  
ID @ TC = 25°C  
Continuous Drain Current, VGS @ 10V (Silicon Limited)  
478  
338  
300  
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)  
A
ID @ TC = 25°C  
IDM  
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)  
Pulsed Drain Current   
1200  
375  
PD @TC = 25°C  
Maximum Power Dissipation  
Linear Derating Factor  
W
W/°C  
V
2.5  
VGS  
TJ  
Gate-to-Source Voltage  
± 20  
Operating Junction and  
-55 to + 175  
300  
°C  
TSTG  
Storage Temperature Range  
Soldering Temperature, for 10 seconds (1.6mm from case)  
Avalanche Characteristics  
EAS (Thermally limited)  
728  
Single Pulse Avalanche Energy   
mJ  
EAS (Thermally limited)  
1404  
Single Pulse Avalanche Energy   
Avalanche Current   
Repetitive Avalanche Energy   
IAR  
EAR  
A
mJ  
See Fig 15, 16, 23a, 23b  
Thermal Resistance  
Symbol  
Parameter  
Typ.  
–––  
0.50  
–––  
Max.  
0.4  
Units  
Junction-to-Case   
RJC  
RCS  
RJA  
Case-to-Sink, Flat Greased Surface  
°C/W  
–––  
62  
Junction-to-Ambient   
Static @ TJ = 25°C (unless otherwise specified)  
Symbol  
V(BR)DSS  
Parameter  
Drain-to-Source Breakdown Voltage  
Breakdown Voltage Temp. Coefficient  
Min. Typ. Max. Units  
40 ––– –––  
––– 0.031 –––  
Conditions  
VGS = 0V, ID = 250µA  
V
V/°C Reference to 25°C, ID = 5mA   
V(BR)DSS/TJ  
–––  
–––  
1.0 –––  
––– –––  
––– ––– 150  
––– ––– 100  
––– ––– -100  
0.6  
0.8  
0.8  
1.1  
2.4  
1.0  
V
V
GS = 10V, ID = 100A   
GS = 4.5V, ID = 50A   
RDS(on)  
Static Drain-to-Source On-Resistance  
Gate Threshold Voltage  
m  
V
VGS(th)  
VDS = VGS, ID = 250µA  
DS = 40 V, VGS = 0V  
VDS = 40V,VGS = 0V,TJ =125°C  
V
IDSS  
Drain-to-Source Leakage Current  
µA  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Gate Resistance  
V
V
GS = 20V  
GS = -20V  
IGSS  
RG  
nA  
–––  
2.1  
–––  
  
Notes:  
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 300A. Note that  
Current imitations arising from heating of the device leads may occur with some lead mounting arrangements.  
(Refer to AN-1140)  
Repetitive rating; pulse width limited by max. junction temperature.  
Limited by TJmax, starting TJ = 25°C, L = 0.146mH, RG = 50, IAS = 100A, VGS =10V.  
ISD 100A, di/dt 954A/µs, VDD V(BR)DSS, TJ 175°C.  
Pulse width 400µs; duty cycle 2%.  
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS  
.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS  
.
Ris measured at TJ approximately 90°C.  
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 53A, VGS =10V.  
Pulse drain current is limited to 1200A by source bonding technology.  
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques  
refer to application note #AN-994: http://www.infineon.com/technical-info/appnotes/an-994.pdf  
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2017-05-12  
IRL40SC209  
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)  
Symbol  
gfs  
Parameter  
Forward Transconductance  
Total Gate Charge  
Min.  
244  
–––  
–––  
–––  
–––  
–––  
–––  
Typ. Max. Units  
Conditions  
–––  
178  
49  
–––  
267  
–––  
–––  
–––  
–––  
–––  
S
VDS = 10V, ID = 100A  
Qg  
ID = 100A  
VDS = 20V  
Qgs  
Gate-to-Source Charge  
Gate-to-Drain Charge  
Total Gate Charge Sync. (Qg– Qgd)  
Turn-On Delay Time  
nC  
Qgd  
88  
VGS = 4.5V  
Qsync  
td(on)  
tr  
90  
63  
VDD = 20V  
ID = 30A  
Rise Time  
182  
ns  
td(off)  
tf  
Turn-Off Delay Time  
Fall Time  
–––  
–––  
182  
138  
–––  
–––  
RG= 2.7  
V
GS = 4.5V  
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
––– 15270 –––  
VGS = 0V  
–––  
–––  
1960  
1370  
–––  
–––  
VDS = 25V  
ƒ = 1.0MHz, See Fig.7  
pF  
Coss eff.(ER) Effective Output Capacitance (Energy Related) –––  
2305  
2935  
–––  
–––  
VGS = 0V, VDS = 0V to 32V  
VGS = 0V, VDS = 0V to 32V  
Coss eff.(TR) Output Capacitance (Time Related)  
–––  
Diode Characteristics  
Symbol  
IS  
Parameter  
Continuous Source Current  
(Body Diode)  
Pulsed Source Current  
(Body Diode)  
Min.  
Typ. Max. Units  
Conditions  
MOSFET symbol  
D
–––  
––– 478  
A
––– 1200  
showing the  
G
integral reverse  
p-n junction diode.  
ISM  
–––  
S
VSD  
Diode Forward Voltage  
–––  
–––  
–––  
–––  
2.2  
51  
1.2  
V
TJ = 25°C,IS =100A,VGS = 0V   
dv/dt  
Peak Diode Recovery dv/dt   
––– V/ns TJ = 175°C,IS = 100A,VDS = 40V  
–––  
TJ = 25°C  
VDD = 34V  
IF = 100A,  
trr  
Reverse Recovery Time  
ns  
–––  
–––  
–––  
–––  
53  
79  
82  
2.5  
–––  
–––  
–––  
–––  
TJ = 125°C  
TJ = 25°C di/dt = 100A/µs   
Qrr  
Reverse Recovery Charge  
Reverse Recovery Current  
nC  
A
TJ = 125°C  
IRRM  
TJ = 25°C  
3
2017-05-12  
IRL40SC209  
1000  
100  
10  
1000  
100  
10  
3.25V  
3.25V  
VGS  
15V  
10V  
6.0V  
5.0V  
4.5V  
4.0V  
3.5V  
3.25V  
VGS  
15V  
10V  
6.0V  
5.0V  
4.5V  
4.0V  
3.5V  
3.25V  
TOP  
TOP  
60µs  
Tj = 175°C  
PULSE WIDTH  
60µs  
Tj = 25°C  
PULSE WIDTH  
BOTTOM  
BOTTOM  
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
DS  
V
, Drain-to-Source Voltage (V)  
DS  
Fig 4. Typical Output Characteristics  
Fig 3. Typical Output Characteristics  
1000  
100  
10  
2.2  
1.8  
1.4  
1.0  
0.6  
I
= 100A  
= 10V  
D
V
GS  
T
= 175°C  
J
T
= 25°C  
J
1
V
= 10V  
DS  
60µs PULSE WIDTH  
0.1  
0
1
2
3
4
5
-60  
-20  
T
20  
60  
100  
140  
180  
, Junction Temperature (°C)  
J
V
, Gate-to-Source Voltage (V)  
GS  
Fig 6. Normalized On-Resistance vs. Temperature  
Fig 5. Typical Transfer Characteristics  
1000000  
100000  
10000  
1000  
14  
V
C
= 0V,  
f = 1 MHZ  
GS  
= C + C , C SHORTED  
I
= 100A  
V
iss  
gs  
gd ds  
D
12  
10  
8
C
= C  
rss  
gd  
= 32V  
= 20V  
DS  
C
= C + C  
oss  
ds  
gd  
V
DS  
VDS= 8V  
C
iss  
C
oss  
6
C
rss  
4
2
100  
0
0.1  
1
10  
100  
0
50 100 150 200 250 300 350 400 450  
, Total Gate Charge (nC)  
V
, Drain-to-Source Voltage (V)  
Q
DS  
G
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage  
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage  
4
2017-05-12  
IRL40SC209  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R (on)  
DS  
1000  
100  
10  
100µsec  
Limited by Package  
T
= 175°C  
1msec  
J
T
= 25°C  
J
10msec  
1
1
DC  
Tc = 25°C  
Tj = 175°C  
Single Pulse  
V
= 0V  
GS  
0.1  
0.1  
0.1  
1
10  
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1  
, Source-to-Drain Voltage (V)  
V
, Drain-toSource Voltage (V)  
DS  
V
SD  
Fig 10. Maximum Safe Operating Area  
Fig 9. Typical Source-Drain Diode Forward Voltage  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
52  
Id = 5.0mA  
50  
48  
46  
44  
42  
40  
0
10  
20  
30  
40  
-60  
-20  
20  
60  
100  
140  
180  
T
, Temperature ( °C )  
J
V
Drain-to-Source Voltage (V)  
DS,  
Fig 11. Drain-to-Source Breakdown Voltage  
Fig 12. Typical Coss Stored Energy  
2.0  
VGS = 3.5V  
VGS = 4.5V  
VGS = 6.0V  
VGS = 8.0V  
VGS = 10V  
1.6  
1.2  
0.8  
0.4  
0
50  
100  
150  
200  
I
, Drain Current (A)  
D
Fig 13. Typical On-Resistance vs. Drain Current  
5
2017-05-12  
IRL40SC209  
1
0.1  
D = 0.50  
0.20  
0.10  
0.05  
0.01  
0.02  
0.01  
SINGLE PULSE  
( THERMAL RESPONSE )  
0.001  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
0.0001  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
t
, Rectangular Pulse Duration (sec)  
1
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case  
1000  
100  
10  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming Tj = 150°C and  
Tstart = 25°C (Single Pulse)  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming j = 25°C and  
Tstart = 150°C.  
1
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
1.0E-01  
tav (sec)  
Fig 15. Avalanche Current vs. Pulse Width  
800  
700  
600  
500  
400  
300  
200  
100  
0
TOP  
BOTTOM 1.0% Duty Cycle  
= 100A  
Single Pulse  
Notes on Repetitive Avalanche Curves , Figures 15, 16:  
(For further info, see AN-1005 at www.infineon.com)  
1.Avalanche failures assumption:  
I
D
Purely a thermal phenomenon and failure occurs at a  
temperature far in excess of Tjmax. This is validated for every  
part type.  
2. Safe operation in Avalanche is allowed as long asTjmax is not  
exceeded.  
3. Equation below based on circuit and waveforms shown in Figures  
23a, 23b.  
4. PD (ave) = Average power dissipation per single avalanche pulse.  
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage  
increase during avalanche).  
6. Iav = Allowable avalanche current.  
7. T = Allowable rise in junction temperature, not to exceed Tjmax  
(assumed as 25°C in Figure 14, 15).  
tav = Average time in avalanche.  
D = Duty cycle in avalanche = tav ·f  
25  
50  
75  
100  
125  
150  
175  
ZthJC(D, tav) = Transient thermal resistance, see Figures 14)  
Starting T , Junction Temperature (°C)  
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC  
I
av = 2T/ [1.3·BV·Zth]  
EAS (AR) = PD (ave)· av  
t
Fig 16. Maximum Avalanche Energy vs. Temperature  
6
2017-05-12  
IRL40SC209  
21  
18  
15  
12  
9
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
I
= 60A  
= 34V  
F
V
R
T = 25°C  
J
T = 125°C  
J
ID = 250µA  
ID = 1.0mA  
ID = 1.0A  
6
3
0
0
200  
400  
600  
800  
-75  
-25  
T
25  
75  
125  
175  
di /dt (A/µs)  
F
, Temperature ( °C )  
J
Fig 17. Threshold Voltage vs. Temperature  
Fig 18. Typical Recovery Current vs. dif/dt  
1500  
1250  
1000  
750  
500  
250  
0
18  
15  
12  
9
I
= 60A  
= 34V  
I
= 100A  
= 34V  
F
F
V
V
R
R
T = 25°C  
T = 25°C  
J
J
T = 125°C  
J
T = 125°C  
J
6
3
0
0
200  
400  
600  
800  
0
200  
400  
600  
800  
di /dt (A/µs)  
F
di /dt (A/µs)  
F
Fig 19. Typical Recovery Current vs. dif/dt  
Fig 20. Typical Stored Charge vs. dif/dt  
1000  
I
= 100A  
F
V
= 34V  
R
T = 25°C  
J
750  
500  
250  
0
T = 125°C  
J
0
200  
400  
600  
800  
di /dt (A/µs)  
F
Fig 21. Typical Stored Charge vs. dif/dt  
7
2017-05-12  
IRL40SC209  
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs  
V
(BR)DSS  
t
p
15V  
DRIVER  
+
L
V
DS  
D.U.T  
AS  
R
G
V
DD  
-
I
A
20V  
I
0.01  
t
p
AS  
Fig 23a. Unclamped Inductive Test Circuit  
Fig 23b. Unclamped Inductive Waveforms  
Fig 24a. Switching Time Test Circuit  
Fig 24b. Switching Time Waveforms  
Id  
Vds  
Vgs  
VDD  
Vgs(th)  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Fig 25b. Gate Charge Waveform  
Fig 25a. Gate Charge Test Circuit  
8
2017-05-12  
IRL40SC209  
D2Pak - 7 Pin Package Outline (Dimensions are shown in millimeters (inches))  
D2Pak - 7 Pin Part Marking Information  
PART NUMBER  
INTERNATIONAL  
RECTIFIER LOGO  
F1324S-7P  
YWWP  
DATE CODE  
Y = YEAR  
W = WEEK  
89  
17  
ASSEMBLY  
LOT CODE  
P = LEADFREE  
9
2017-05-12  
IRL40SC209  
Qualification Information  
Qualification Level  
Industrial  
(per JEDEC JESD47F)†  
MSL1  
D2PAK-7Pin  
Moisture Sensitivity Level  
RoHS Compliant  
(per JEDEC J-STD-020D)  
Yes  
Applicable version of JEDEC standard at the time of product release.  
Revision History  
Date  
Comments  
 Corrected package picture added “s” on pin number 4 - page 1.  
05/12/2017  
Published by  
Infineon Technologies AG  
81726 München, Germany  
© Infineon Technologies AG 2015  
All Rights Reserved.  
IMPORTANT NOTICE  
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics  
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any  
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and  
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third  
party.  
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this  
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of  
the product of Infineon Technologies in customer’s applications.  
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of  
customer’s technical departments to evaluate the suitability of the product for the intended application and the  
completeness of the product information given in this document with respect to such application.  
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest  
Infineon Technologies office (www.infineon.com).  
WARNINGS  
Due to technical requirements products may contain dangerous substances. For information on the types in question  
please contact your nearest Infineon Technologies office.  
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized  
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a  
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.  
10  
2017-05-12  

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