IRFS7430 [INFINEON]

40V 单个 N 通道 HEXFET Power MOSFET, 采用无铅 D2-Pak 封装;


型号：	IRFS7430
厂家：	Infineon
描述：	40V 单个 N 通道 HEXFET Power MOSFET, 采用无铅 D2-Pak 封装
文件：	总13页 (文件大小：304K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

StrongIRFET

IRFS7430PbF

IRFSL7430PbF

HEXFET^®Power MOSFET

Applications

V_DSS

R_DS(on)typ.

max.

40V

0.97m

1.2m

l Brushed motor drive applications

l BLDC motor drive applications

l Battery powered circuits

l Half-bridge and full-bridge topologies

l Synchronous rectifier applications

l Resonant mode power supplies

l OR-ing and redundant power switches

l DC/DC and AC/DC converters

l DC/AC inverters

426A

I_D

(Silicon Limited)

195A

I_D

(Package Limited)

Benefits

l Improved gate, avalanche and dynamic dV/dt

ruggedness

D²Pak

IRFS7430PbF

TO-262

IRFSL7430PbF

l Fully characterized capacitance and avalanche

SOA

l Enhanced body diode dV/dt and dI/dt capability

l Lead-free

Gate

Drain

Source

Base Part Number

Package Type

Standard Pack

Form

Tube

Orderable Part Number

Quantity

IRFSL7430PbF

IRFS7430PbF

TO-262

D2-Pak

IRFSL7430PbF

IRFS7430PbF

Tube

Tape and Reel Left

800

IRFS7430TRLPbF

6.0

4.0

2.0

0.0

500

400

300

200

100

= 100A

Limited By Package

= 125°C

= 25°C

12 14 16

18 20

100

125

150

175

, Case Temperature (°C)

Gate -to -Source Voltage (V)

GS,

Fig 2. Maximum Drain Current vs. Case Temperature

Fig 1. Typical On-Resistance vs. Gate Voltage

Submit Datasheet Feedback November 6, 2014

IRFS/SL7430PbF

Absolute Maximum Ratings

Symbol

I_D@ T_C= 25°C

I_D@ T_C= 100°C

I_D@ T_C= 25°C

I_DM

Parameter

Max.

426

301

195

1524

Units

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

Continuous Drain Current, V_GS@ 10V (Wire Bond Limited)

Pulsed Drain Current

P_D@T_C= 25°C

Maximum Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Operating Junction and

375

2.5

± 20

W/°C

V_GS

T_J

-55 to + 175

T_STG

Storage Temperature Range

°C

Soldering Temperature, for 10 seconds (1.6mm from case)

300

Avalanche Characteristics

Single Pulse Avalanche Energy

Avalanche Current

E_{AS (Thermally limited)}

I_AR

760

1452

See Fig. 15, 16, 22a, 22b

Repetitive Avalanche Energy

E_AR

Thermal Resistance

Symbol

Parameter

Junction-to-Case

Junction-to-Ambient (PCB Mount, steady-state)

Typ.

–––

Max.

0.40

Units

R_θJC

R_θJA

°C/W

Static @ T_J= 25°C (unless otherwise specified)

Symbol

V_(BR)DSS

ΔV_(BR)DSS/ΔT_J

Parameter

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Min.

–––

2.2

–––

Typ.

–––

0.014

0.97

1.2

–––

2.1

Max.

–––

1.2

–––

3.9

Units

V/°C

mΩ

Conditions

V_GS= 0V, I_D= 250μA

Reference to 25°C, I_D= 1.0mA

V_GS= 10V, I_D= 100A

V_GS= 6.0V, I_D= 50A

V_DS= V_GS, I_D= 250μA

V_DS= 40V, V_GS= 0V

V_DS= 40V, V_GS= 0V, T_J= 125°C

R_DS(on)

Static Drain-to-Source On-Resistance

V_GS(th)

I_DSS

Gate Threshold Voltage

Drain-to-Source Leakage Current

μA

1.0

150

100

-100

–––

I_GSS

R_G

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Internal Gate Resistance

_GS= 20V

V_GS= -20V

Notes:

Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 195A. Note that current

limitations arising from heating of the device leads may occur with

ꢀ Pulse width ≤ 400μs; duty cycle ≤ 2%.

C_osseff. (TR) is a fixed capacitance that gives the same charging time

as C_osswhile V_DSis rising from 0 to 80% V_DSS

C_osseff. (ER) is a fixed capacitance that gives the same energy as

some lead mounting arrangements. (Refer to AN-1140)

Repetitive rating; pulse width limited by max. junction

temperature.

Limited by T_Jmax, starting T_J= 25°C, L = 0.15mH

R_G= 50Ω, I_AS= 100A, V_GS=10V.

I_SD≤ 100A, di/dt ≤ 990A/μs, V_DD≤ V_(BR)DSS, T_J≤ 175°C.

C_osswhile V_DSis rising from 0 to 80% V_DSS

R_θis measured at T_Japproximately 90°C..

Limited by T_Jmaxstarting T_J= 25°C, L= 1mH, R_G= 50Ω, I_AS= 54A, V_GS=10V.

When mounted on 1" square PCB (FR-4 or G-10 Material). For recom-

mended footprint and soldering techniques refer to application note #AN-994.

http://www.irf.com/technical-info/appnotes/an-994.pdf

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November 6, 2014

IRFS/SL7430PbF

Dynamic @ T_J= 25°C (unless otherwise specified)

Symbol Parameter

Forward Transconductance

Min.

150

–––

Typ.

–––

300

202

105

160

100

Max.

–––

460

–––

Units

Conditions

gfs

Q_g

V_DS= 10V, I_D= 100A

I_D= 100A

_DS=20V

V_GS= 10V

_D= 100A, V_DS=0V, V_GS= 10V

V_DD= 20V

_D= 30A

Total Gate Charge

Q_gs

Q_gd

Q_sync

t_d(on)

t_r

Gate-to-Source Charge

Gate-to-Drain ("Miller") Charge

Total Gate Charge Sync. (Q_g- Q_gd)

Turn-On Delay Time

Rise Time

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

R_G= 2.7Ω

V_GS= 10V

V_GS= 0V

V_DS= 25V

ƒ = 1.0 MHz

C_iss

C_oss

C_rss

C_osseff. (ER)

C_osseff. (TR)

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Effective Output Capacitance (Energy Related)

Effective Output Capacitance (Time Related)

––– 14240 –––

–––

2130

1460

2605

2920

–––

V_GS= 0V, V_DS= 0V to 32V

Diode Characteristics

Symbol

Parameter

Min.

–––

Typ.

–––

Max.

426

Units

Conditions

MOSFET symbol

I_S

Continuous Source Current

(Body Diode)

showing the

integral reverse

I_SM

Pulsed Source Current

(Body Diode)

–––

1524

p-n junction diode.

V_SD

dv/dt

t_rr

Diode Forward Voltage

Peak Diode Recovery

Reverse Recovery Time

–––

0.86

2.7

1.2

–––

V/ns

T_J= 25°C, I_S= 100A, V_GS= 0V

T_J= 175°C, I_S= 100A, V_DS= 40V

T_J= 25°C

T_J= 125°C

T_J= 25°C

T_J= 125°C

T_J= 25°C

V_R= 34V,

I_F= 100A

di/dt = 100A/μs

Q_rr

Reverse Recovery Charge

Reverse Recovery Current

2.3

I_RRM

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November 6, 2014

IRFS/SL7430PbF

1000

100

1000

100

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

4.8V

4.5V

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

4.8V

4.5V

TOP

BOTTOM

4.5V

60μs PULSE WIDTH

≤

60μs PULSE WIDTH

≤

Tj = 175°C

Tj = 25°C

0.1

100

0.1

100

, Drain-to-Source Voltage (V)

Fig 3. Typical Output Characteristics

Fig 4. Typical Output Characteristics

1000

2.0

= 100A

= 10V

1.8

1.6

1.4

1.2

1.0

0.8

0.6

100

= 25°C

T = 175°C

= 25V

≤60μs PULSE WIDTH

1.0

-60 -40 -20 0 20 40 60 80 100120140160180

, Junction Temperature (°C)

, Gate-to-Source Voltage (V)

Fig 6. Normalized On-Resistance vs. Temperature

Fig 5. Typical Transfer Characteristics

100000

10000

1000

14.0

= 0V,

= C

f = 1 MHZ

I = 100A

+ C , C

SHORTED

iss

12.0

= C

rss

oss

= C + C

= 32V

= 20V

10.0

8.0

6.0

4.0

2.0

0.0

iss

oss

rss

, Drain-to-Source Voltage (V)

100

50 100 150 200 250 300 350 400

Q , Total Gate Charge (nC)

Fig 7. Typical Capacitance vs. Drain-to-Source Voltage

Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage

Submit Datasheet Feedback November 6, 2014

IRFS/SL7430PbF

1000

100

10000

1000

100

OPERATION IN THIS AREA

LIMITED BY R

(on)

= 175°C

100μsec

1msec

= 25°C

10msec

Tc = 25°C

Tj = 175°C

Single Pulse

= 0V

0.1

100

0.0

0.5

1.0

1.5

2.0

2.5

, Drain-toSource Voltage (V)

, Source-to-Drain Voltage (V)

Fig 10. Maximum Safe Operating Area

Fig 9. Typical Source-Drain Diode

Forward Voltage

2.5

Id = 1.0mA

= 0V to 32V

2.0

1.5

1.0

0.5

0.0

10 15 20 25 30 35 40 45

Drain-to-Source Voltage (V)

-60 -40 -20 0 20 40 60 80 100120140160180

T , Temperature ( °C )

DS,

Fig 11. Drain-to-Source Breakdown Voltage

Fig 12. Typical C_OSSStored Energy

6.0

= 5.5V

= 6.0V

= 7.0V

= 8.0V

=10V

4.0

2.0

0.0

200

400

600

800 1000 1200

I , Drain Current (A)

Fig 13. Typical On-Resistance vs. Drain Current

November 6, 2014

IRFS/SL7430PbF

0.1

D = 0.50

0.20

0.10

0.05

0.02

0.01

0.001

0.0001

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

100

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔΤ j = 25°C and

Tstart = 150°C.

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Avalanche Current vs.Pulsewidth

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in

excess of T_jmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

6. I_av= Allowable avalanche current.

7. ΔT = Allowable rise in junction temperature, not to exceed T_jmax(assumed as

25°C in Figure 15, 16).

t_{av =}Average time in avalanche.

D = Duty cycle in avalanche = t_av·f

800

700

600

500

400

300

200

100

TOP

BOTTOM 1.0% Duty Cycle

= 100A

Single Pulse

Z_thJC(D, t_av) = Transient thermal resistance, see Figures 14)

P_{D (ave)}= 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC

I_av= 2DT/ [1.3·BV·Z_th]

100

125

150

175

E_{AS (AR)}= P_{D (ave)}·t_av

Starting T , Junction Temperature (°C)

Fig 16. Maximum Avalanche Energy vs. Temperature

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IRFS/SL7430PbF

4.0

3.5

3.0

2.5

2.0

1.5

1.0

I = 60A

= 34V

T = 25°C

T = 125°C

= 250μA

= 1.0mA

= 1.0A

-75 -50 -25

25 50 75 100 125 150 175

200

400

600

800

1000

T , Temperature ( °C )

di /dt (A/μs)

Fig. 18 - Typical Recovery Current vs. di_f/dt

Fig 17. Threshold Voltage vs. Temperature

300

I = 100A

I = 60A

= 34V

250

200

150

100

T = 25°C

T = 125°C

200

400

600

800

1000

200

400

600

800

1000

di /dt (A/μs)

Fig. 19 - Typical Recovery Current vs. di_f/dt

Fig. 20 - Typical Stored Charge vs. di_f/dt

260

I = 100A

= 34V

220

180

140

100

T = 25°C

T = 125°C

200

400

600

800

1000

di /dt (A/μs)

Fig. 21 - Typical Stored Charge vs. di_f/dt

November 6, 2014

IRFS/SL7430PbF

Driver Gate Drive

P.W.

D =

D.U.T

Period

=10V

CircuitLayoutConsiderations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

D.U.T. V Waveform

Diode Recovery

dv/dt

V_DD

Re-Applied

Voltage

• dv/dtcontrolledbyR_G

R_G

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

InductorCurrent

Inductor Curent

Ripple

≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

(BR)DSS

15V

DRIVER

D.U.T

2V0_GV_S

0.01

Fig 22b. Unclamped Inductive Waveforms

Fig 22a. Unclamped Inductive Test Circuit

R_D

V_DS

90%

V_GS

D.U.T.

R_G

V_DD

10V

V_GS

10%

PulseWidth ≤ 1 µs

Duty Factor≤ 0.1 %

d(on)

d(off)

Fig 23a. Switching Time Test Circuit

Fig 23b. Switching Time Waveforms

Current Regulator

Same Type as D.U.T.

Vds

Vgs

50KΩ

.2μF

12V

.3μF

D.U.T.

Vgs(th)

3mA

Qgs1

Qgs2

Qgd

Qgodr

Current Sampling Resistors

Fig 24a. Gate Charge Test Circuit

Fig 24b. Gate Charge Waveform

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IRFS/SL7430PbF

D²Pak (TO-263AB) Package Outline

Dimensions are shown in millimeters (inches)

D²Pak (TO-263AB) Part Marking Information

THIS IS AN IRF530S WITH

PART NUMBER

LOT CODE 8024

INTERNATIONAL

RECTIFIER

LOGO

AS SEMBLED ON WW 02, 2000

IN THE ASS EMBLY LINE "L"

F530S

DATE CODE

YEAR 0 = 2000

WE EK 02

AS S E MB L Y

LOT CODE

LINE L

PART NUMBER

INTERNATIONAL

RECTIFIER

LOGO

F530S

DATE CODE

P = DE S IGNAT E S L E AD - F RE E

PRODUCT (OPTIONAL)

AS S E MB L Y

LOT CODE

YEAR 0 = 2000

WE EK 02

A = AS S E MB L Y S IT E CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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November 6, 2014

IRFS/SL7430PbF

TO-262 Package Outline

Dimensions are shown in millimeters (inches)

TO-262 Part Marking Information

E XAMPLE : THIS IS AN IRL3103L

LOT CODE 1789

PART NUMB E R

INT ERNATIONAL

RE CT IFIE R

LOGO

AS S EMB LE D ON WW 19, 1997

IN T HE AS S E MB LY LINE "C"

DAT E CODE

YE AR 7 = 1997

WE EK 19

AS S E MBLY

LOT CODE

LINE C

PART NU MBE R

INT E RNAT IONAL

RE CT IF IE R

LOGO

DATE CODE

P = DE S IGNAT E S LE AD-F R EE

PRODUCT (OPTIONAL)

YEAR 7 = 1997

AS S E MB LY

LOT CODE

WE E K 19

A = AS S EMB LY S IT E CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

November 6, 2014

IRFS/SL7430PbF

D²Pak (TO-263AB) Tape & Reel Information Dimensions are shown in millimeters (inches)

TRR

1.60 (.063)

1.50 (.059)

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

0.368 (.0145)

0.342 (.0135)

FEED DIRECTION

TRL

11.60 (.457)

11.40 (.449)

1.85 (.073)

1.65 (.065)

24.30 (.957)

23.90 (.941)

15.42 (.609)

15.22 (.601)

1.75 (.069)

1.25 (.049)

10.90 (.429)

10.70 (.421)

4.72 (.136)

4.52 (.178)

16.10 (.634)

15.90 (.626)

FEED DIRECTION

13.50 (.532)

12.80 (.504)

27.40 (1.079)

23.90 (.941)

330.00

(14.173)

MAX.

60.00 (2.362)

MIN.

30.40 (1.197)

MAX.

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

26.40 (1.039)

24.40 (.961)

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

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November 6, 2014

IRFS/SL7430PbF

Qualification information

†

Qualification level

Industrial

(per JEDEC JESD47F^††guidelines)

Moisture Sensitivity Level

D2Pak

MS L 1

(per JEDEC J-S TD-020D^††)

Not applicable

TO-262

RoHS compliant

Yes

Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/

Applicable version of JEDEC standard at the time of product release.

Revision History

Date

Comment

•

Updated E_{AS (L =1mH)}= 1452mJ on page 2

11/6/2014

• Updated note 9 “Limited by T_Jmax, starting T_J= 25°C, L = 1mH, R_G= 50Ω, I_AS= 54A, V_GS=10V”. on page 2

•

Updated package outline on page 9 & 10

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

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November 6, 2014

IMPORTANT NOTICE

The information given in this document shall in no For further information on the product, technology,

event be regarded as a guarantee of conditions or delivery terms and conditions and prices please

characteristics (“Beschaffenheitsgarantie”) .

contact your nearest Infineon Technologies office

(www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement

of intellectual property rights of any third party.

WARNINGS

Due to technical requirements products may

contain dangerous substances. For information on

the types in question please contact your nearest

Infineon Technologies office.

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and

standards concerning customer’s products and any

use of the product of Infineon Technologies in

customer’s applications.

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized

representatives

Infineon

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of

the product or any consequences of the use thereof

can reasonably be expected to result in personal

injury.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.

IRFS7430 [INFINEON]

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