IRFS3107-7P [INFINEON]
75V 单个 N 通道 HEXFET Power MOSFET, 采用 D2-Pak 7 引脚封装;
| 型号： | IRFS3107-7P |
| 厂家： | 
Infineon |
| 描述： | 75V 单个 N 通道 HEXFET Power MOSFET, 采用 D2-Pak 7 引脚封装 |
| 文件： | 总10页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFS3107-7PPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
D
S
VDSS
RDS(on) typ.
max.
75V
2.1m
Ω
2.6mΩ
260A
240A
G
l Hard Switched and High Frequency Circuits
ID
ID (Package Limited)
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
D
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
S
S
S
S
G
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Max.
260
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Continuous Drain Current, VGS @ 10V
190
A
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
240
1060
370
PD @TC = 25°C
W
Maximum Power Dissipation
Linear Derating Factor
2.5
W/°C
V
VGS
± 20
Gate-to-Source Voltage
13
Peak Diode Recovery
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
320
mJ
A
Avalanche Current
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.40
40
Units
°C/W
Rθ
JC
Junction-to-Case
Rθ
JA
–––
Junction-to-Ambient (PCB Mount)
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1
IRFS3107-7PPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
75 ––– –––
––– 0.083 ––– V/°C Reference to 25°C, ID = 5mA
Conditions
VGS = 0V, ID = 250µA
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
2.0
2.1
2.6
4.0
20
VGS = 10V, ID = 160A
VDS = VGS, ID = 250µA
mΩ
V
VGS(th)
–––
IDSS
Drain-to-Source Leakage Current
––– –––
µA VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0V, TJ = 125°C
nA VGS = 20V
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
VGS = -20V
RG(int)
–––
2.1
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 25V, ID = 160A
nC ID = 160A
DS = 38V
VGS = 10V
ID = 160A, VDS =0V, VGS = 10V
ns VDD = 49V
260 ––– –––
S
––– 160 240
Qgs
Gate-to-Source Charge
–––
–––
38
57
–––
–––
V
Qgd
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Qsync
––– 103 –––
td(on)
Turn-On Delay Time
–––
–––
17
80
–––
–––
tr
Rise Time
ID = 160A
td(off)
Turn-Off Delay Time
––– 100 –––
––– 64 –––
RG = 2.7Ω
VGS = 10V
tf
Fall Time
Ciss
Input Capacitance
––– 9200 –––
––– 850 –––
––– 400 –––
––– 1150 –––
––– 1500 –––
VGS = 0V
Coss
Output Capacitance
VDS = 50V
Crss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
pF ƒ = 1.0MHz
Coss eff. (ER)
Coss eff. (TR)
VGS = 0V, VDS = 0V to 60V
VGS = 0V, VDS = 0V to 60V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
D
S
IS
Continuous Source Current
––– –––
A
260
(Body Diode)
Pulsed Source Current
(Body Diode)
showing the
integral reverse
G
ISM
––– ––– 1060
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
V
TJ = 25°C, IS = 160A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 64V,
–––
–––
52
63
ns
IF = 160A
di/dt = 100A/µs
Qrr
Reverse Recovery Charge
––– 110 –––
––– 160 –––
nC
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
3.8
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.026mH
RG = 25Ω, IAS = 160A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 160A, di/dt ≤ 1420A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
ꢀ Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero.
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IRFS3107-7PPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
4.8V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 25°C
≤
60µs PULSE WIDTH
≤
Tj = 175°C
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 160A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
= 25V
J
1
V
DS
60µs PULSE WIDTH
≤
0.1
2
3
4
5
6
7
8
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
V
, Gate-to-Source Voltage (V)
J
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
10000
1000
14.0
V
C
= 0V,
f = 1 MHZ
GS
I = 160A
D
= C + C , C SHORTED
iss
gs gd ds
12.0
C
= C
V
V
= 60V
= 38V
rss
gd
DS
DS
C
= C + C
ds gd
oss
10.0
8.0
6.0
4.0
2.0
0.0
C
iss
C
oss
C
rss
100
1
10
100
1000
0
25 50 75 100 125 150 175 200 225
, Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
Q
DS
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFS3107-7PPbF
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100µsec
T
= 25°C
10msec
J
1msec
DC
1
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0.0
0.5
1.0
1.5
2.0
1
10
100
1000
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
300
250
200
150
100
50
95
90
85
80
75
70
Id = 5mA
Limited By Package
0
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T
, Case Temperature (°C)
T , Temperature ( °C )
C
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1400
I
D
1200
1000
800
600
400
200
0
TOP
28A
50A
BOTTOM 160A
-10
0
10 20 30 40 50 60 70 80
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
V
J
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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4
IRFS3107-7PPbF
1
D = 0.50
0.20
0.1
R1
R1
R2
R2
R3
R3
R4
R4
0.10
0.05
Ri (°C/W) τi (sec)
0.01083
0.05878
0.15777
0.17478
0.00001
τ
τ
J τJ
τ
Cτ
0.000086
0.001565
0.011192
1τ1
Ci= τi/Ri
τ
τ
τ
2 τ2
3τ3
4τ4
0.01
0.02
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
∆
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
∆Τ
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
350
300
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1.0% Duty Cycle
= 160A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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IRFS3107-7PPbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
30
25
20
15
10
5
I = 106A
F
V
= 64V
R
T = 25°C
J
T = 125°C
J
I
I
I
= 250µA
= 1.0mA
= 1.0A
D
D
D
0
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
0
200
400
600
800
1000
T
di /dt (A/µs)
J
F
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
30
1000
I = 160A
F
I = 106A
F
900
800
700
600
500
400
300
200
100
V
= 64V
V
= 64V
25
20
15
10
5
R
R
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/µs)
di /dt (A/µs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
1000
I = 160A
F
900
V
= 64V
R
T = 25°C
J
800
700
600
500
400
300
200
T = 125°C
J
0
200
400
600
800
1000
di /dt (A/µs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFS3107-7PPbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Fig 24b. Gate Charge Waveform
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IRFS3107-7PPbF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
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IRFS3107-7PPbF
D2Pak - 7 Pin Part Marking Information
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
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January 28, 2014
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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