IRFS3004TRL-7PPBF [INFINEON]
Power Field-Effect Transistor, 240A I(D), 40V, 0.00125ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE, PLASTIC, D2PAK-7;
| 型号： | IRFS3004TRL-7PPBF |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 240A I(D), 40V, 0.00125ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE, PLASTIC, D2PAK-7 开关 脉冲 晶体管 |
| 文件： | 总9页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97378
IRFS3004-7PPbF
HEXFET® Power MOSFET
Applications
D
l High Efficiency Synchronous Rectification in SMPS
VDSS
RDS(on) typ.
40V
0.90m
1.25m
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
Ω
Ω
max.
G
ID
ID
400A
c
(Silicon Limited)
Benefits
240A
S
(Package Limited)
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
D
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
S
S
S
S
G
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Parameter
Max.
400c
280c
240
Units
A
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current d
1610
PD @TC = 25°C
380
W
Maximum Power Dissipation
2.5
Linear Derating Factor
W/°C
V
VGS
± 20
Gate-to-Source Voltage
2.0
Peak Diode Recovery f
dv/dt
TJ
V/ns
-55 to + 175
Operating Junction and
TSTG
°C
Storage Temperature Range
300
Soldering Temperature, for 10 seconds (1.6mm from case)
Avalanche Characteristics
Single Pulse Avalanche Energy e
EAS (Thermally limited)
290
mJ
A
Avalanche Currentꢀd
IAR
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy d
EAR
mJ
Thermal Resistance
Symbol
Parameter
Junction-to-Case kl
Typ.
–––
Max.
0.40
40
Units
°C/W
RθJC
RθJA
–––
Junction-to-Ambient (PCB Mount) j
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1
02/26/09
IRFS3004-7PPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
40 ––– –––
––– 0.038 ––– V/°C Reference to 25°C, ID = 5mAd
Conditions
VGS = 0V, ID = 250µA
V
––– 0.90 1.25
V
GS = 10V, ID = 195A g
mΩ
V
VGS(th)
2.0
–––
4.0
20
VDS = VGS, ID = 250µA
IDSS
Drain-to-Source Leakage Current
––– –––
µA
VDS = 40V, VGS = 0V
VDS = 40V, VGS = 0V, TJ = 125°C
VGS = 20V
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA
VGS = -20V
RG
–––
2.0
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Min. Typ. Max. Units
Conditions
VDS = 10V, ID = 195A
1300 ––– –––
S
Qg
Total Gate Charge
––– 160 240
nC ID = 180A
VDS =20V
Qgs
Qgd
Qsync
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
42
65
95
23
–––
–––
–––
–––
VGS = 10V g
ID = 180A, VDS =0V, VGS = 10V
ns
VDD = 26V
––– 240 –––
––– 91 –––
ID = 240A
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 2.7Ω
VGS = 10V g
––– 160 –––
––– 9130 –––
––– 2020 –––
––– 990 –––
––– 2590 –––
––– 2650 –––
Ciss
Coss
Crss
Input Capacitance
pF
VGS = 0V
Output Capacitance
Reverse Transfer Capacitance
VDS = 25V
ƒ = 1.0 MHz, See Fig. 5
Coss eff. (ER)
Effective Output Capacitance (Energy Related)
V
GS = 0V, VDS = 0V to 32V i, See Fig. 11
GS = 0V, VDS = 0V to 32V h
iꢀ
Coss eff. (TR)
V
Effective Output Capacitance (Time Related)
h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
––– –––
A
MOSFET symbol
D
S
400
c
(Body Diode)
Pulsed Source Current
(Body Diode)ꢀd
showing the
integral reverse
G
ISM
––– ––– 1610
A
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
–––
–––
–––
V
TJ = 25°C, IS = 195A, VGS = 0V g
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 34V,
–––
–––
–––
–––
–––
49
51
37
41
3.2
ns
IF = 240A
di/dt = 100A/µs g
Qrr
Reverse Recovery Charge
nC
A
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
ISD ≤ 240A, di/dt ≤ 740A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢀ Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Bond wire current limit is 240A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
.
.
Limited by TJmax, starting TJ = 25°C, L = 0.01mH
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero.
RG = 25Ω, IAS = 240A, VGS =10V. Part not recommended for use
above this value .
2
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IRFS3004-7PPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
TOP
BOTTOM
BOTTOM
1
4.5V
60µs PULSE WIDTH
≤
60µs PULSE WIDTH
4.5V
≤
Tj = 175°C
Tj = 25°C
0.1
0.1
1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.0
1.5
1.0
0.5
I
= 195A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
3
4
5
6
7
8
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
14.0
100000
10000
1000
V
= 0V,
= C
f = 1 MHZ
GS
I = 180A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
12.0
= C
rss
oss
gd
= C + C
V
V
= 32V
= 20V
DS
DS
ds
gd
10.0
8.0
6.0
4.0
2.0
0.0
C
iss
C
oss
C
rss
100
0
50
100
150
200
250
1
10
, Drain-to-Source Voltage (V)
100
Q , Total Gate Charge (nC)
V
DS
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS3004-7PPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100
10
1
100µsec
T
= 25°C
J
1msec
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
DC
V
= 0V
GS
0.1
1
0.0
0.5
1.0
1.5
2.0
0
1
10
100
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
420
360
300
240
180
120
60
50
48
46
44
42
40
Id = 5mA
Limited By Package
0
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T
, Case Temperature (°C)
T
, Temperature ( °C )
C
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1200
I
D
TOP
44A
80A
BOTTOM 240A
1000
800
600
400
200
0
-5
0
5
10 15 20 25 30 35 40 45
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
V
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRFS3004-7PPbF
1
D = 0.50
0.1
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.00757 0.000006
τ
τ
J τJ
Cτ
0.06508 0.000064
0.18313 0.001511
0.14378 0.009800
τ
τ
1τ1
Ci= τi/Ri
τ
τ
2τ2
0.02
0.01
3τ3
4τ4
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
∆
pulsewidth, tav, assuming Tj = 150°C and
0.01
Tstart =25°C (Single Pulse)
0.05
0.10
Allowed avalanche Current vs avalanche
∆Τ
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
320
280
240
200
160
120
80
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1.0% Duty Cycle
= 240A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
40
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFS3004-7PPbF
10
9
4.5
4.0
3.5
3.0
2.5
I = 96A
F
V
= 34V
R
T = 25°C
J
8
T = 125°C
J
7
6
I
I
I
= 250µA
= 1.0mA
= 1.0A
D
D
D
5
2.0
1.5
1.0
4
3
2
100
200
300
400
500
-75 -50 -25
0
25 50 75 100 125 150 175 200
, Temperature ( °C )
di /dt (A/µs)
F
T
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
140
12
I = 96A
I = 144A
F
F
11
10
9
V
= 34V
V
= 34V
R
R
120
100
80
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
8
7
6
60
5
4
40
3
20
2
100
200
300
400
500
100
200
300
400
500
di /dt (A/µs)
F
di /dt (A/µs)
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
180
I = 144A
F
V
160
140
120
100
80
= 34V
R
T = 25°C
J
T = 125°C
J
60
40
20
100
200
300
400
500
di /dt (A/µs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFS3004-7PPbF
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01Ω
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFS3004-7PPbF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRFS3004-7PPbF
D2Pak - 7 Pin Part Marking Information
ꢀ14
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/2009
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9
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