IRFR7446TRPBF_技术文档

StrongIRFET

IRFR7446PbF

Applications

l Brushed Motor drive applications

l BLDC Motor drive applications

l PWM Inverterized topologies

l Battery powered circuits

l Half-bridge and full-bridge topologies

l Synchronous rectifier applications

l Resonant mode power supplies

l OR-ing and redundant power switches

l DC/DC and AC/DC converters

HEXFET^®Power MOSFET

D

V_DSS

R_DS(on)typ.

max.

40V

3.0m

3.9m

Ω

G

I_D

120A

56A

(Silicon Limited)

S

I_D

(Package Limited)

D

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

S

G

Ruggedness

l Fully Characterized Capacitance and Avalanche

D-Pak

IRFR7446TRPbF

SOA

l Enhanced body diode dv/dt and dI/dt Capability

l Lead-Free

G

D

S

Gate

Drain

Source

Ordering Information

Orderable part number

Package Type

Standard Pack

Form

Complete Part Number

Quantity

75

IRFR7446PBF

IRFR7446TRPBF

D-PAK

Tube/Bulk

Tape and Reel

IRFR7446PBF

2000

IRFR7446TRPBF

10

8

120

LIMITED BY PACKAGE

I

= 56A

D

100

80

60

40

20

0

6

T

= 125°C

J

4

T

= 25°C

J

2

4

8

12

16

20

25

50

75

100

125

150

175

V

, Gate-to-Source Voltage (V)

T , Case Temperature (°C)

GS

C

Fig 2. Maximum Drain Current vs. Case Temperature

Fig 1. Typical On-Resistance vs. Gate Voltage

1

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IRFR7446PbF

Absolute Maximum Ratings

Symbol

Parameter

Max.

Units

120

84

I_D@ T_C= 25°C

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

I_D@ T_C= 100°C

I_D@ T_C= 25°C

I_DM

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

Continuous Drain Current, V_GS@ 10V (Wire Bond Limited)

Pulsed Drain Current

A

56

520

98

P_D@T_C= 25°C

Maximum Power Dissipation

W

W/°C

V

0.66

± 20

Linear Derating Factor

V_GS

T_J

Gate-to-Source Voltage

Operating Junction and

-55 to + 175

300

°C

T_STG

Storage Temperature Range

Soldering Temperature, for 10 seconds (1.6mm from case)

Avalanche Characteristics

125

251

E_{AS (Thermally limited)}

Single Pulse Avalanche Energy

Avalanche Current

mJ

E_{AS (Thermally limited)}

I_AR

A

See Fig 15,16, 23a, 23b

E_AR

Repetitive Avalanche Energy

mJ

Thermal Resistance

Symbol

Parameter

Junction-to-Case

Typ.

–––

Max.

1.52

50

Units

R_θ_JC

R_θJA

Junction-to-Ambient (PCB Mount)

Junction-to-Ambient

°C/W

110

Static @ T_J= 25°C (unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Units

Conditions

V_GS= 0V, I_D= 250μA

Reference to 25°C, I_D= 1mA

V_(BR)DSS

Drain-to-Source Breakdown Voltage

40

–––

V

ΔV_(BR)DSS/ΔT_J

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

–––

26

–––

3.9

mV/°C

V_GS= 10V, I_D= 56A

R_DS(on)

3.0

4.4

3.0

–––

1.5

mΩ

V_GS= 6.0V, I_D= 28A

–––

3.9

m

Ω

V_DS= V_GS, I_D= 100μA

V_GS(th)

I_DSS

Gate Threshold Voltage

2.2

–––

V

V_DS= 40V, V_GS= 0V

Drain-to-Source Leakage Current

1.0

μA

nA

Ω

V

_DS= 40V, V_GS= 0V, T_J= 125°C

V_GS= 20V

_GS= -20V

150

100

-100

–––

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Internal Gate Resistance

V

R_G

Notes:

ꢀ Pulse width ≤ 400μs; duty cycle ≤ 2%.

Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 56A. Note that current

limitations arising from heating of the device leads may occur with

someleadmountingarrangements. (RefertoAN-1140)

Repetitive rating; pulse width limited by max. junction

temperature.

Limited by T_Jmax, starting T_J= 25°C, L = 0.08mH

R_G= 50Ω, I_AS= 56A, V_GS=10V.

I_SD≤ 100A, di/dt ≤ 1306A/μs, V_DD≤ V_(BR)DSS, T_J≤ 175°C.

C_osseff. (TR) is a fixed capacitance that gives the same charging time

as C_osswhile V_DSis rising from 0 to 80% V_DSS

C_osseff. (ER) is a fixed capacitance that gives the same energy as

C_osswhile V_DSis rising from 0 to 80% V_DSS

When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

R_θis measured at T_Japproximately 90°C.

.

Limited by T_Jmaxstarting T_J= 25°C, L= 1mH, R_G= 50Ω, I_AS= 22A, V_GS=10V.

*

L_Dand L_Sare Internal Drain Inductance and Internal Source Inductance

2

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IRFR7446PbF

Dynamic @ T_J= 25°C (unless otherwise specified)

Symbol

gfs

Q_g

Parameter

Forward Transconductance

Total Gate Charge

Min. Typ. Max. Units

170 ––– –––

Conditions

S

V_DS= 10V, I_D= 56A

nC I_D=56A

_DS=20V

V_GS= 10V

I_D= 56A, V_DS=0V, V_GS= 10V

ns V_DD= 20V

–––

65

18

22

43

9.8

13

32

20

130

–––

Q_gs

Gate-to-Source Charge

Gate-to-Drain ("Miller") Charge

Total Gate Charge Sync. (Q_g- Q_gd)

Turn-On Delay Time

V

Q_gd

Q_sync

t_d(on)

t_r

Rise Time

I_D= 30A

t_d(off)

Turn-Off Delay Time

R = 2.7

Ω

G

t_f

Fall Time

V_GS= 10V

C_iss

Input Capacitance

––– 3150 –––

––– 480 –––

––– 330 –––

––– 570 –––

––– 680 –––

pF V_GS= 0V

C_oss

Output Capacitance

V_DS= 25V

C_rss

Reverse Transfer Capacitance

Effective Output Capacitance (Energy Related)

_osseff. (TR)

Effective Output Capacitance (Time Related)

ƒ = 1.0 MHz, See Fig. 5

C_osseff. (ER)

V

_GS= 0V, V_DS= 0V to 32V

See Fig. 12

C

V

Diode Characteristics

Symbol

Parameter

Continuous Source Current

Min. Typ. Max. Units

Conditions

MOSFET symbol

D

I_S

––– –––

A

V

120

(Body Diode)

Pulsed Source Current

showing the

G

I_SM

––– ––– 480

integral reverse

S

(Body Diode)

Diode Forward Voltage

p-n junction diode.

T_J= 25°C, I_S= 56A, V_GS= 0V

V_SD

dv/dt

t_rr

–––

0.9

4.8

20

1.3

––– V/ns T_J= 175°C, I_S= 56A, V_DS= 40V

Peak Diode Recovery

T_J= 25°C

T_J= 125°C

T_J= 25°C

T_J= 125°C

T_J= 25°C

V_R= 34V,

Reverse Recovery Time

–––

ns

nC

A

I_F= 56A

di/dt = 100A/μs

21

Q_rr

Reverse Recovery Charge

13

I_RRM

t_on

Reverse Recovery Current

Forward Turn-On Time

1.8

*

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

3

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IRFR7446PbF

1000

100

10

1000

100

10

VGS

15V

10V

7.0V

6.0V

5.5V

5.0V

4.5V

4.3V

VGS

TOP

15V

10V

7.0V

6.0V

5.5V

5.0V

4.5V

4.3V

BOTTOM

4.3V

1

≤ 60μs PULSE WIDTH

Tj = 25°C

≤ 60μs PULSE WIDTH

Tj = 175°C

0.1

1

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 3. Typical Output Characteristics

Fig 4. Typical Output Characteristics

1000

2.0

1.5

1.0

0.5

I

= 56A

D

V

= 10V

GS

100

10

1

T

= 175°C

J

T

= 25°C

= 10V

J

V

DS

≤

60μs PULSE WIDTH

0.1

2.0

3.0

V

4.0

5.0

6.0

7.0

8.0

-60 -40 -20

0

20 40 60 80 100 120 140 160 180

, Gate-to-Source Voltage (V)

GS

T

, Junction Temperature (°C)

J

Fig 6. Normalized On-Resistance vs. Temperature

Fig 5. Typical Transfer Characteristics

100000

10000

1000

16

V

C

= 0V,

f = 1 MHZ

GS

I

= 56A

D

= C + C , C SHORTED

iss

gs

gd ds

C

= C

V

= 32V

= 20V

rss

gd

DS

C

= C + C

ds

12

8

oss

gd

Ciss

Coss

Crss

4

0

100

0

20

40

60

80

100

1

10

100

Q

Total Gate Charge (nC)

G

V

, Drain-to-Source Voltage (V)

DS

Fig 7. Typical Capacitance vs. Drain-to-Source Voltage

Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage

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IRFR7446PbF

1000

100

10

1000

100

10

100μsec

T

= 175°C

J

1msec

imited by Package

L

OPERATION IN THIS AREA

LIMITED BY R (on)

DS

10msec

DC

T

= 25°C

J

1

Tc = 25°C

Tj = 175°C

Single Pulse

V

= 0V

GS

0.1

1

10

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

V

, Drain-toSource Voltage (V)

V

, Source-to-Drain Voltage (V)

DS

SD

Fig 10. Maximum Safe Operating Area

Fig 9. Typical Source-Drain Diode

Forward Voltage

0.4

49

48

47

46

45

44

43

42

41

40

Id = 1.0mA

0.3

0.2

0.1

0.0

0

10

20

30

40

-60 -40 -20 0 20 40 60 80 100120140160180

V

Drain-to-Source Voltage (V)

DS,

T

, Temperature ( °C )

J

Fig 11. Drain-to-Source Breakdown Voltage

Fig 12. Typical C_OSSStored Energy

16.0

V

= 5.5V

= 6.0V

= 7.0V

14.0

12.0

10.0

8.0

GS

VGS = 8.0V

=10V

V

GS

6.0

4.0

2.0

0

20 40 60 80 100 120 140 160 180 200

, Drain Current (A)

I

D

Fig 13. Typical On-Resistance vs. Drain Current

5

January 6, 2015

IRFR7446PbF

10

1

D = 0.50

0.20

0.10

0.05

0.1

0.02

0.01

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

t

, Rectangular Pulse Duration (sec)

1

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100

10

1

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 150°C and

Δ

Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming

Tstart = 150°C.

j = 25°C and

ΔΤ

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

Fig 15. Typical Avalanche^taC^vu^(srr^ee^cn⁾t vs.Pulsewidth

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in

excess of T_jmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 23a, 23b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

140

120

100

80

TOP

BOTTOM 1.0% Duty Cycle

= 56A

Single Pulse

I

D

6. I_av= Allowable avalanche current.

60

7. ΔT = Allowable rise in junction temperature, not to exceed T_jmax(assumed as

25°C in Figure 14, 15).

t_{av =}Average time in avalanche.

40

D = Duty cycle in avalanche = t_av·f

Z_thJC(D, t_av) = Transient thermal resistance, see Figures 14)

20

0

P_{D (ave)}= 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC

I_av= 2DT/ [1.3·BV·Z_th]

25

50

75

100

125

150

175

E_{AS (AR)}= P_{D (ave)}·t_av

Starting T , Junction Temperature (°C)

J

Fig 16. Maximum Avalanche Energy vs. Temperature

6

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IRFR7446PbF

4.5

4.0

3.5

3.0

2.5

2.0

1.5

6

4

2

0

I

= 34A

= 34V

F

V

R

T = 25°C

J

T = 125°C

J

I

=50μA

D

= 250μA

= 1.0mA

= 1.0A

-75 -50 -25

0

J

25 50 75 100 125 150 175

, Temperature ( °C )

0

200

400

600

800

1000

T

di /dt (A/μs)

F

Fig. 18 - Typical Recovery Current vs. di_f/dt

Fig 17. Threshold Voltage vs. Temperature

80

6

I

= 34A

= 34V

I

= 56A

= 34V

F

V

R

T = 25°C

J

60

40

20

0

J

T = 125°C

J

T = 125°C

J

4

2

0

200

400

600

800

1000

0

200

400

600

800

1000

di /dt (A/μs)

F

Fig. 19 - Typical Recovery Current vs. di_f/dt

Fig. 20 - Typical Stored Charge vs. di_f/dt

80

I

= 56A

= 34V

F

V

R

T = 25°C

J

60

40

20

0

T = 125°C

J

0

200

400

600

800

1000

di /dt (A/μs)

F

Fig. 21 - Typical Stored Charge vs. di_f/dt

7

January 6, 2015

IRFR7446PbF

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

+

-

*

=10V

V

GS

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

-

+

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

+

-

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Current

Inductor Curent

I

SD

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

V

(BR)DSS

15V

t

p

DRIVER

+

L

V

DS

D.U.T

AS

R

G

V

DD

-

I

A

2V0_GV_S

Ω

0.01

t

p

I

AS

Fig 23b. Unclamped Inductive Waveforms

Fig 23a. Unclamped Inductive Test Circuit

R_D

V_DS

V

DS

90%

V_GS

D.U.T.

R_G

+

V_DD

-

10V

V_GS

10%

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

V

GS

t

r

t

f

d(on)

d(off)

Fig 24a. Switching Time Test Circuit

Fig 24b. Switching Time Waveforms

Id

Current Regulator

Same Type as D.U.T.

Vds

Vgs

50KΩ

.2μF

12V

.3μF

+

V

DS

D.U.T.

-

Vgs(th)

V

GS

3mA

I

D

G

Qgs1

Qgs2

Qgd

Qgodr

Current Sampling Resistors

Fig 25a. Gate Charge Test Circuit

Fig 25b. Gate Charge Waveform

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IRFR7446PbF

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120

WIT H AS S E MB LY

PART NUMBER

INTERNATIONAL

RECTIFIER

LOGO

LOT CODE 1234

DATE CODE

YEAR 1 = 2001

WEEK 16

IRFR120

116A

ASSEMBLED ON WW 16, 2001

IN THE ASSEMBLY LINE "A"

12

34

LINE A

Note: "P" in assembly lineposition

ASSEMBLY

LOT CODE

indicates "L ead-F ree"

"P" in assembly lineposition indicates

"L ead-F ree" qualification to the cons umer-level

PART NUMBER

DATE CODE

P = DE S IGNAT E S L E AD-F R EE

PRODUCT (OPTIONAL)

INTERNATIONAL

RECTIFIER

OR

IRFR120

12 34

LOGO

P = DE S IGNAT E S L E AD-F R EE

PRODUCT QUALIFIED TOTHE

ASSEMBLY

LOT CODE

CONSUMER LEVEL (OPTIONAL)

YEAR 1 = 2001

WEE K 16

A= ASSEMBLY SITE CODE

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

9

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IRFR7446PbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

10

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IRFR7446PbF

Qualification information^†

Industrial^††

Qualification level

(per JEDEC JESD47F^†††guidelines)

MS L 1

D-PAK

(per JEDEC J-S T D-020D^†††

)

RoHS compliant

Yes

Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/

Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information: http:www.irf.com/whoto-call/salesrep/

Applicable version of JEDEC standard at the time of product release.

Revision History

Date

Comment

•

Updated E_{AS (L =1mH)}= 251mJ on page 2

Ω

Updated note 10 “Limited by T_Jmax, starting T_J= 25°C, L = 1mH, R_G= 50 , I_AS= 22A, V_GS=10V”. on page 2

1/6/2015

Updated package outline on page 9.

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

11

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型号：	IRFR7446TRPBF
厂家：	Infineon
描述：	Power Field-Effect Transistor, 56A I(D), 40V, 0.0039ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, DPAK-3/2 开关脉冲晶体管
文件：	总11页 (文件大小：298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFR7446TRPBF [INFINEON]

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