IRF7769L1PBF_15 [INFINEON]
Optimized for Synchronous Rectification;型号: | IRF7769L1PBF_15 |
厂家: | Infineon |
描述: | Optimized for Synchronous Rectification |
文件: | 总10页 (文件大小:267K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IRF7769L1TRPbF
DirectFET Power MOSFET
Typical values (unless otherwise specified)
l RoHS Compliant, Halogen Free
l Lead-Free (Qualified up to 260°C Reflow)
l Ideal for High Performance Isolated Converter
Primary Switch Socket
l Optimized for Synchronous Rectification
VDSS
VGS
RDS(on)
2.8mΩ@ 10V
Vgs(th)
100V min ±20V max
Qg tot
Qgd
l Low Conduction Losses
200nC
110nC
2.7V
l High Cdv/dt Immunity
l Low Profile (<0.7mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface Mount Techniques
l Industrial Qualified
S
S
S
S
S
S
S
S
G
D
D
DirectFET ISOMETRIC
L8
Applicable DirectFET Outline and Substrate Outline
SB
SC
M2
M4
L4
L6
L8
Description
The IRF7769L1TRPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve
the lowest on-state resistance in a package that has a footprint smaller than a D2PAK and only 0.7 mm profile. The DirectFET package is
compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering
techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual
sided cooling to maximize thermal transfer in power systems.
The IRF7769L1TRPbF is optimized for high frequency switching and synchronous rectification applications. The reduced total losses in the
device coupled with the high level of thermal performance enables high efficiency and low temperatures, which are key for system reliability
improvements, and makes this device ideal for high performance power converters.
Part number
Package Type
Standard Pack
Form
Tape and Reel
Note
Quantity
4000
IRF7769L1TRPbF
DirectFET Large Can
"TR" suffix
Absolute Maximum Ratings
Max.
100
±20
124
88
Parameter
Units
V
VDS
Drain-to-Source Voltage
Gate-to-Source Voltage
VGS
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TA = 25°C
ID @ TC = 25°C
IDM
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
A
20
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
375
500
260
74
EAS
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
IAR
12.00
10.00
8.00
6.00
4.00
2.00
3.10
3.00
2.90
2.80
I
= 74A
T = 25°C
D
A
V
= 7.0V
GS
V
= 8.0V
= 10V
GS
T
= 125°C
= 25°C
V
J
GS
V
= 15V
GS
T
J
0.00
2.0
4.0 6.0
8.0 10.0 12.0 14.0 16.0
20
40
60
I , Drain Current (A)
80
100
V
, Gate-to-Source Voltage (V)
GS
Fig 1. Typical On-Resistance vs. Gate Voltage
D
Fig 2. Typical On-Resistance vs. Drain Current
Notes:
TC measured with thermocouple mounted to top (Drain) of part.
ꢀ Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 0.09mH, RG = 25Ω, IAS = 74A.
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
1
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© 2012 International Rectifier
February 18, 2013
IRF7769L1TRPbF
Static @ TJ = 25°C (unless otherwise specified)
Conditions
VGS = 0V, ID = 250μA
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
100
–––
–––
2.0
–––
0.02
2.8
2.7
-10
–––
–––
–––
–––
–––
200
30
–––
–––
3.5
4.0
V
V/°C
mΩ
V
Reference to 25°C, ID = 2mA
VGS = 10V, ID = 74A
V
/ T
J
ΔΒ DSS Δ
RDS(on)
VDS = VGS, ID = 250μA
VGS(th)
ΔVGS(th)/ΔTJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
410
–––
–––
–––
–––
–––
–––
–––
–––
––– mV/°C
VDS = 100V, VGS = 0V
20
250
100
-100
–––
300
–––
–––
165
–––
–––
–––
–––
–––
–––
–––
–––
μA
nA
S
VDS = 80V, VGS = 0V, TJ = 125°C
V
GS = 20V
VGS = -20V
DS = 25V, ID = 74A
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
V
gfs
Qg
VDS = 50V
GS = 10V
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
RG
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
Output Charge
V
9.0
110
51
nC
ID = 74A
See Fig. 9
119
53
VDS = 16V, VGS = 0V
nC
Gate Resistance
1.5
44
Ω
VDD = 50V, VGS = 10V
ID = 74A
td(on)
tr
td(off)
tf
Turn-On Delay Time
–––
–––
–––
–––
Rise Time
32
RG=1.8Ω
Turn-Off Delay Time
92
ns
Fall Time
41
VGS = 0V
Ciss
Coss
Crss
Coss
Coss
Input Capacitance
––– 11560 –––
––– 1240 –––
VDS = 25V
ƒ = 1.0MHz
Output Capacitance
pF
Reverse Transfer Capacitance
Output Capacitance
–––
––– 6665 –––
––– 690 –––
590
–––
VGS = 0V, VDS = 1.0V, f=1.0MHz
VGS = 0V, VDS = 80V, f=1.0MHz
Output Capacitance
Diode Characteristics
Conditions
MOSFET symbol
Parameter
Continuous Source Current
Min. Typ. Max. Units
IS
–––
–––
124
showing the
(Body Diode)
A
ISM
integral reverse
Pulsed Source Current
(Body Diode)
–––
–––
500
p-n junction diode.
TJ = 25°C, IS = 74A, VGS = 0V
TJ = 25°C, IF = 74A, VDD = 50V
di/dt = 100A/μs
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
75
1.3
112
330
V
ns
nC
Qrr
220
Notes:
ꢀ Repetitive rating; pulse width limited by max. junction temperature.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
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© 2012 International Rectifier
February 18, 2013
IRF7769L1TRPbF
Absolute Maximum Ratings
Parameter
Max.
Units
PD @TC = 25°C
Power Dissipation
Power Dissipation
Power Dissipation
125
63
W
PD @TC = 100°C
PD @TA = 25°C
3.3
TP
Peak Soldering Temperature
Operating Junction and
270
°C
TJ
-55 to + 175
TSTG
Storage Temperature Range
Thermal Resistance
Parameter
Typ.
–––
12.5
20
Max.
Units
RθJA
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Can
45
RθJA
–––
–––
1.2
0.4
RθJA
°C/W
RθJ-Can
RθJ-PCB
–––
–––
Junction-to-PCB Mounted
10
1
D = 0.50
0.20
0.10
0.1
0.05
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.02
0.01
0.01
0.1080
0.6140
0.4520
1.47e-05
0.000171
0.053914
0.006099
0.036168
τ
τ
J τJ
τ
Cτ
1τ1
Ci= τi/Ri
τ
τ
τ
2 τ2
3τ3
4τ4
SINGLE PULSE
( THERMAL RESPONSE )
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Notes:
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
Surface mounted on 1 in. square Cu board, steady state.
TC measured with thermocouple incontact with top (Drain) of part.
Used double sided cooling, mounting pad with large heatsink.
R is measured at TJ of approximately 90°C.
θ
Surface mounted on 1 in. square Cu
board (still air).
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink. (still air)
3
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© 2012 International Rectifier
February 18, 2013
IRF7769L1TRPbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
10V
8.0V
6.0V
5.0V
4.5V
4.0V
TOP
TOP
10V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM
BOTTOM
3.5V
1
3.5V
3.5V
60μs PULSE WIDTH
≤
60μs PULSE WIDTH
Tj = 175°C
≤
Tj = 25°C
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 4. Typical Output Characteristics
Fig 5. Typical Output Characteristics
1000
2.5
2.0
1.5
1.0
0.5
V
= 25V
I
= 74A
DS
≤ 60μs PULSE WIDTH
D
V
= 10V
GS
100
10
1
T
T
T
= 175°C
= 25°C
= -40°C
J
J
J
0.1
2.0
2.5
V
3.0
3.5
4.0
4.5
5.0
5.5
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 6. Typical Transfer Characteristics
Fig 7. Normalized On-Resistance vs. Temperature
100000
14
V
C
= 0V,
f = 1 MHZ
GS
I = 74A
D
= C + C , C SHORTED
iss
gs
gd ds
V
V
V
= 80V
= 50V
= 20V
12
10
8
DS
DS
DS
C
= C
rss
gd
C
= C + C
ds
oss
gd
Ciss
10000
1000
100
Coss
Crss
6
4
2
0
0
50
100
150
200
250
300
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 9. Typical Total Gate Charge vs
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
www.irf.com © 2012 International Rectifier
Gate-to-Source Voltage
4
February 18, 2013
IRF7769L1TRPbF
10000
1000
100
10
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100μsec
T
T
T
= 175°C
= 25°C
= -40°C
J
J
J
DC
10msec
1
1
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
V
= 0V
GS
0.1
0.1
0
1
10
100
1000
0.2
0.4
V
0.6
0.8
1.0
1.2
V
, Drain-toSource Voltage (V)
DS
, Source-to-Drain Voltage (V)
SD
Fig 10. Typical Source-Drain Diode Forward Voltage
Fig11. Maximum Safe Operating Area
125
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250μA
100
75
50
25
0
25
50
75
100
125
150
175
-75 -50 -25
0
J
25 50 75 100 125 150 175
, Temperature ( °C )
T
, CaseTemperature (°C)
T
C
Fig 13. Typical Threshold Voltage vs.
Fig 12. Maximum Drain Current vs. Case Temperature
Junction Temperature
1200
I
D
TOP
13A
20A
1000
800
600
400
200
0
BOTTOM 74A
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
Fig 14. Maximum Avalanche Energy Vs. Drain Current
© 2012 International Rectifier
5
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February 18, 2013
IRF7769L1TRPbF
1000
100
10
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
pulsewidth, tav, assuming Tj = 150°C and
Δ
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 19a, 19b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
280
240
200
160
120
80
TOP
BOTTOM 1% Duty Cycle
= 74A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
40
0
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Fig 16. Maximum Avalanche Energy Vs. Temperature
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·ta
Driver Gate Drive
P.W.
D.U.T
Period
D =
Period
P.W.
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
-
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
• di/dt controlled by RG
Re-Applied
Voltage
RG
+
-
• Driver same type as D.U.T.
Body Diode
Inductor Current
Forward Drop
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Diode Reverse Recovery Test Circuit for N-Channel HEXFET® Power MOSFETs
www.irf.com © 2012 International Rectifier February 18, 2013
6
IRF7769L1TRPbF
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgodr
Qgd
Fig 18a. Gate Charge Test Circuit
Fig 18b. Gate Charge Waveform
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
V
R
D.U.T
AS
GS
G
V
DD
-
I
A
20V
t
0.01Ω
p
I
AS
Fig 19b. Unclamped Inductive Waveforms
Fig 19a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 20a. Switching Time Test Circuit
Fig 20b. Switching Time Waveforms
7
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© 2012 International Rectifier
February 18, 2013
IRF7769L1TRPbF
DirectFET Board Footprint, L8 (Large Size Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
G = GATE
D = DRAIN
S = SOURCE
D
D
D
D
D
D
S
S
S
S
S
S
S
S
G
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
8
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© 2012 International Rectifier
February 18, 2013
IRF7769L1TRPbF
DirectFET Outline Dimension, L8 Outline (LargeSize Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DIMENSIONS
IMPERIAL
MIN
METRIC
MAX
CODE
MIN
9.05
6.85
5.90
0.55
0.58
1.18
0.98
0.73
0.38
1.34
2.52
0.616
0.020
0.09
MAX
0.360
0.280
0.236
0.026
0.024
0.048
0.017
0.030
0.017
0.058
0.106
0.0274
0.0031
0.007
9.15
7.10
6.00
0.356
0.270
0.232
A
B
C
D
E
F
0.65 0.022
0.62
1.22
1.02
0.77
0.42
0.023
0.046
0.015
0.029
0.015
G
H
J
1.47 0.053
K
L
2.69
0.099
0.676
0.080
0.18
M
N
P
0.0235
0.0008
0.003
DirectFET Part Marking
GATE MARKING
LOGO
+
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates "Lead-Free"
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
9
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© 2012 International Rectifier
February 18, 2013
IRF7769L1TRPbF
DirectFET Tape & Reel Dimension (Showing component orientation).
LOADED TAPE FEED DIRECTION
+
NOTE:
Controlling dimensions in mm
Std reel quantity is 4000 parts. (ordered as IRF7769L1TRPBF).
REEL DIMENSIONS
DIMENSIONS
METRIC
STANDARD OPTION (QTY 4000)
IMPERIAL
METRIC
IMPERIAL
NOTE: CONTROLLING
DIMENSIONS IN MM
CODE
MIN
MIN
11.90
3.90
15.90
7.40
7.20
9.90
1.50
1.50
MAX
12.10
4.10
MAX
0.476
0.161
0.642
0.299
0.291
0.398
N.C
MIN
CODE
MAX
N.C
MIN
MAX
N.C
A
B
C
D
E
F
4.69
12.992
0.795
0.504
0.059
3.900
N.C
A
B
C
D
E
F
330.00
20.20
12.80
1.50
0.154
0.623
0.291
0.283
0.390
0.059
0.059
N.C
N.C
16.30
7.60
7.40
10.10
N.C
13.20
N.C
100.00
22.40
18.40
19.40
0.520
N.C
99.00
N.C
3.940
0.880
0.720
0.760
G
H
0.650
0.630
16.40
15.90
G
H
0.063
1.60
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
Qualification Information†
Industrial †† *
Qualification level
MSL1
Moisture Sensitivity Level
RoHS Compliant
DirectFET
(per JEDEC J-STD-020D†††
)
Yes
Qualification standards can be found at International Rectifier’s web site
http://www.irf.com/product-info/reliability
Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information:
http://www.irf.com/whoto-call/salesrep/
Applicable version of JEDEC standard at the time of product release.
* Industrial qualification standards except auto-clav test conditions
Revision History
Date
Comments
2/13/2013
TR1 option removed and Tape & Reel Info updated accordingly. Hyperlinks added throw-out the document
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
10
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© 2012 International Rectifier
February 18, 2013
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