IR38363M [INFINEON]
OptiMOS™ IPOL DC-DC转换器,单输入电压,15 A降压稳压器,配备SVIDO;型号: | IR38363M |
厂家: | Infineon |
描述: | OptiMOS™ IPOL DC-DC转换器,单输入电压,15 A降压稳压器,配备SVIDO DC-DC转换器 稳压器 |
文件: | 总64页 (文件大小:3385K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DCDC Converter
OptiMOS™ IPOL
IR38163/363/165/365
Single-input Voltage, 15 A & 30 A
Buck Regulators with SVID
FEATURES
DESCRIPTION
Internal LDO allows single 16 V operation
Output Voltage Range: 0.5 V to 0.875*PVin
0.5% accurate Reference Voltage
Intel VR12.5 (Rev 1.5); VR13 (Rev 1.0) and SVID
(Rev 1.7) compliant
This family of OptiMOS™ IPOL devices offers easy-to-use,
fully integrated and highly efficient DC/DC regulators with
Intel SVID and I2C/PMBus™ interface. The on-chip PWM
controller and co-packaged low duty cycle optimized
MOSFETs make these devices a space-efficient solution,
providing accurate power delivery for low output voltage
and high current applications that require an Intel SVID
interface.
Enhanced line/load regulation with Feedforward
Frequency programmable by PMBus™ up to 1.5
MHz
Enable input with Voltage Monitoring Capability
Remote Sense Amplifier with True Differential
Voltage Sensing
Fast mode I2C and 400 kHz PMBus™ interface for
programming, sequencing and margining output
voltage, and for monitoring input voltage, output
voltage, output current and temperature.
PMBus™ configurable fault thresholds for input
UVLO, output OVP, OCP and thermal shutdown.
Thermally compensated pulse-by-pulse current
limit and Hiccup Mode Over Current Protection
Dedicated output voltage sensing for power good
indication and overvoltage protection which
remains active even when Enable is low.
These versatile devices offer programmability of switching
frequency, output voltage, and fault/warning thresholds
and fault responses while operating over a wide input
range. Thus, they offer flexibility as well as system level
security in event of fault conditions.
The switching frequency is programmable from 150 kHz to
1.5 MHz.
The on-chip sensors and ADC along with the SVID and
PMBus™ interfaces (IR18163 and IR38363) or SVID and I2C
interfaces (IR38165 and IR38365) make it easy to monitor
and report input voltage, output voltage, output current
and temperature.
Enhanced Pre-Bias Start up
Integrated MOSFET drivers and Bootstrap diode
Operating junction temp: -40oC<Tj<125oC
Thermal Shut Down
Post Package trimmed rising edge dead-time
PMBus™ Programmable Power Good Output
Small Size 5 mm x 7 mm PQFN
Pb-Free (RoHS Compliant)
External resistor allows setting up to 16 PMBus™
addresses
APPLICATIONS
Intel® VR13 and VR12.5 based systems
Servers and High End Desktop CPU VRs for non-
core applications
BASIC APPLICATION
For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor.
5.5V <Vin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable Vin
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
PGood
RS-
SV_CLK
SV_DIO
RSo
Fb
CPU
serial
bus
SV_ALERT
ADDR
Comp
LGnd
PGnd
Placeholder
for capacitor
Figure 1: Typical application circuit
1
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
PIN DIAGRAM
Figure 2: IR38163/363/165/365 Package Top View
5mm X 7mm PQFN
*IR38165 and IR38365 do not support PMBus™ and pin 17 is a no connect (NC)
ORDERING INFORMATION
Tape and Reel
Description
Package
Part Number
Qty
PQFN
PQFN
PQFN
PQFN
4000
4000
4000
4000
IR38163MTRPbF
IR38363MTRPbF
IR38165MTRPbF
IR38365MTRPbF
30A Buck Regulator with SVID and PMBus™ for Vccio
15A Buck Regulator with SVID and PMBus™ for Vmcp
30A Buck Regulator with SVID for Vccio
15A Buck Regulator with SVID for Vmcp
2
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
FUNCTIONAL BLOCK DIAGRAM
VCC
Vin
P1V8
LDO
VLDOref
LDO
LGND
-
OT_Fault
OC_Fault
+
UVcc
BOOT
PVIN
VCC
UVcc
FAULT
CONTROL
UVEN
Fault
COMP
Fault
VDAC2
HDrv
+
-
E/A
HDin
GATE
DRIVE
LOGIC
OV_Fault
FCCM
SW
FB
VCC
LDrv
LDin
EN/
FCCM
PGND
Rso
CONTROL AND FAULT LOGIC
RS-
PGood
RS+
ISense
TMON
Current Sense
SDA
SVID Interface, SMBus
Interface,
Logic, Command and Status registers
Temperature
Sense
SCL
SAlert#/NC
Vcc
ADDR
Vsns
SV_ALERT
SV_CLK SV_DIO
Figure 3: Simplified Block Diagram for IR38163/IR38363/IR38165/IR38365
3
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
PVIN
Input voltage for power stage. Bypass capacitors between PVin and PGND should be
connected very close to this pin and PGND. Typical applications use four 22 uF input
capacitors and a low ESR, low ESL 0.1uF decoupling capacitor in a 0603/0402 case size. A
3.3nF capacitor may also be used in parallel with these input capacitors to reduce ringing on
the Sw node.
2
Boot
Supply voltage for high side driver. A 0.1uF capacitor should be connected from this pin to
the Sw pin. It is recommended to provide a placement for a 0 ohm resistor in series with the
capacitor. For applications in which PVin>14V, a 1 ohm resistor is required in series with
boot capacitor.
3
4
ENABLE
ADDR
Enable pin to turn on and off the IC
A resistor should be connected from this pin to LGnd to set the PMBus™ address offset for
the device. It is recommended to provide a placement for a 10 nF capacitor in parallel with
the offset resistor.
5
6
Vsns
FB
Sense pin for OVP and PGood. Typically connected to a local Vout capacitor at the output of
the inductor.
Inverting input to the error amplifier. This pin is connected directly to the output of the
regulator or to the output of the remote sense amplifier, via resistor divider to set the output
voltage and provide feedback to the error amplifier.
7
8
COMP
RSo
Output of error amplifier. An external resistor and capacitor network is typically connected
from this pin to FB to provide loop compensation.
Remote Sense Amplifier Output. When the remote sense amplifier is used, this is connected
to the feedback compensation network
9
RS-
RS+
Remote Sense Amplifier input. Connect to ground at the load.
Remote Sense Amplifier input. Connect to output at the load.
10
11
PGood
Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to VCC.
If the power good voltage before VCC UVLO needs to be limited to < 500 mV, use a 49.9K
pullup, otherwise a 4.99K pullup will suffice.
12,25
PGND
Power ground. This pin should be connected to the system’s power ground plane. Bypass
capacitors between PVin and PGND should be connected very close to PVIN pin (pin 1) and
this pin.
13
14
15
16
17
18
LGND
SV_CLK
SV_DIO
SV_ALERT
SAlert#/NC
SDA
Signal ground for internal reference and control circuitry. This should be connected to the
PGnd plane at a quiet location using a single point connection.
SVID CLK line. This is pulled up to VDDIO/VCCIO voltage. It is recommended to provide a
placement for a 0603 resistor between the pin and the pullup resistor
SVID Data line. This is pulled up to VDDIO/VCCIO voltage. It is recommended to provide a
placement for a 0603 resistor between the pin and the pullup resistor
SVID Alert line. This is pulled up to VDDIO/VCCIO voltage through a resistor.
SMBus Alert line; open drain SMBALERT# pin. This should be pulled up to 3.3V-5V with a
1K-5K resistor. For IR38165 and IR38365, this a no connect pin.
SMBus data serial input/output line. This should be pulled up to 3.3V-5V with a 1K-5K
resistor
4
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
PIN #
PIN NAME
PIN DESCRIPTION
19
20
SCL
SMBus clock line. This should be pulled up to 3.3V-5V with a 1K-5K resistor
P1V8
This is the supply for the digital circuits; bypass with a 10uF capacitor to PGnd. A 2.2uF
capacitor is valid however a10uF capacitor is recommended.
21
22
Vin
Input Voltage for LDO. A 1 uF capacitor is placed from this pin to PGnd. If the internal bias
LDO is used, tie this pin to PVin. If an external bias voltage (typically 5V) is available for Vcc,
tie the Vin pin to Vcc.
VCC
Bias Voltage for IC and driver section, output of LDO. Add 10 uF bypass cap from this pin to
PGnd.
23,26
24
NC
NC
SW
Switch node. This pin is connected to the output inductor.
5
Rev 3.6
Jun 7, 2019
DCDC Converter
OPTIMOS IPOL
IR38163
25A Single-input Voltage, Synchronous
Buck Regulator with PMBus™ Interface
ABSOLUTE MAXIMUM RATINGS
Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin, Vin
-0.3V to 25V
VCC
-0.3V to 6V
P1V8
-0.3V to 2 V
SW
-0.3V to 25V (DC), -4V to 25V (AC, 100ns)
-0.3V to 31V
BOOT
BOOT to SW
-0.3V to 6V (DC) (Note 1), -0.3V to 6.5V (AC, 100ns)
-0.3V to 6V (Note 1)
PGD, other Input/output pins
PGND to GND, RS- to GND
-0.3V to + 0.3V
THERMAL INFORMATION
Junction to Ambient Thermal Resistance ƟJA
11.1 C/W (Note 2)
18.9 C/W (Note 3)
4.16 C/W (Note 4)
Junction to case top Thermal Resistance θJC(top)
Junction to PCB Thermal Resistance ƟJB
Junction to case top parameter ΨJT (top)
0.32 C/W (Note 2)
-55°C to 150°C
Storage Temperature Range
Junction Temperature Range
-40°C to 150°C
(Voltages referenced to GND unless otherwise specified)
Note 1: Must not exceed 6V.
Note 2: Value obtained via thermal simulation under natural convention on a VCCIO demo board.
10 layer, 7”x5.5”x0.072” PCB with 1.5 oz copper at the top and bottom layer. Inner layers 2, 3, 8 and 9 have
1 oz copper and layers 4,5,6,7 have 2 oz copper. Ta = 25C was used for the simulation.
Note 3: PCB from note 2 and package is considered in thermal simulation with Ta=25 ⁰C. Pin 12 is considered.
Note 4: Only package is considered. Simulation is used with a cold plate that fixes top of package at Ta=25 ⁰C.
6
Rev 3.3
Dec 15, 2017
IR38163/363/165/365
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
SYMBOL
DEFINITION
MIN
MAX
UNITS
PVin
Input Bus Voltage
1.5
5.3
4.5
4.5
0.5
0
16*
16
V
Vin
LDO supply voltage
LDO output/Bias supply voltage
High Side driver gate voltage
Output Voltage
VCC
5.5
Boot to SW
5.5
VO
IO
0.875*PVin
30
Output Current
A
Fs
TJ
Switching Frequency
Junction Temperature
150
-40
1500
125
kHz
°C
* SW Node must not exceed 25V
PARAMETER
MOSFET Rds(on)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Rds(on)_Top
Rds(on)_Bot
Top Switch
VBoot – VSW = 5V, ID = 30A, Tj
= 25°C
2.2
mΩ
Bottom Switch
Vcc =5V, ID = 30A, Tj = 25°C
0.78
Reference Voltage
1.25V<VFB<2.555V
VOUT_SCALE_LOOP=1;
-1
+1
%
Accuracy
00C<Tj<850C
0.75V<VFB<1.25V
VOUT_SCALE_LOOP=1;
-0.75
-0.5
+0.75
+0.5
0.45V<VFB<0.75V
%
%
VOUT_SCALE_LOOP=1;
1.25V<VFB<2.555V
VOUT_SCALE_LOOP=1;
-1.6
-1.0
-2.0
+1.6
+1.0
+2.0
Accuracy
-400C<Tj<1250C
0.75V<VFB<1.25V
VOUT_SCALE_LOOP=1;
%
%
0.45V<VFB<0.75V
VOUT_SCALE_LOOP=1;
Supply Current
PVin range (using
external Vcc=5V)
1.5-
16
V
V
Vin range (using internal
LDO)
Fsw=600kHz
5.3-
16
7
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
PARAMETER
SYMBOL
CONDITIONS
Fsw=1.5MHz
MIN
TYP
MAX
UNIT
5.5-
16
Vin range (when
Vin=Vcc)
4.5
5.0
2.7
39
5.5
4
V
Iin(Standby)
Vin Supply Current
(Standby) (internal Vcc)
Enable low, No Switching,
Vin=16V, low power mode
enabled
mA
mA
mA
mA
Iin(Dyn)
Vin Supply Current
(Dyn)(internal Vcc)
Enable high, Fs = 600kHz,
Vin=16V
50
5
Icc(Standby)
VCC Supply Current
(Standby)(external Vcc)
Enable low, No Switching,
Vcc=5.5V, low power mode
enabled
2.7
39
Icc(Dyn)
VCC Supply Current
(Dyn)(external Vcc)
Enable high, Fs = 600kHz,
Vcc=5.5V
50
Under Voltage Lockout
VCC – Start – Threshold
VCC – Stop – Threshold
VCC_UVLO_Start
VCC_UVLO_Stop
Enable_UVLO_Start
VCC Rising Trip Level
VCC Falling Trip Level
Supply ramping up
4.0
3.7
4.2
3.9
4.4
4.1
V
Enable – Start –
Threshold
0.55
0.35
0.6
0.4
0.65
V
Enable_UVLO_Stop
Ien
Enable – Stop –
Threshold
Supply ramping down
Enable=5.5V
0.45
1
Enable leakage current
Oscillator
uA
Vramp
Ramp Amplitude
PVin=5V, D=Dmax, Note 2
PVin=12V, D=Dmax, Note 2
PVin=16V,D=Dmax, Note 2
Note 2
0.71
1.84
2.46
0.22
35
Vp-p
Ramp (os)
Dmin (ctrl)
Ramp Offset
Min Pulse Width
Fixed Off Time
Max Duty Cycle
Error Amplifier
Input Bias Current
Sink Current
V
Note 2
50
150
89
ns
ns
%
Note 2 Fs=1.5MHz
Fs=400kHz
100
87.5
Dmax
86
IFb(E/A)
Isink(E/A)
Isource(E/A)
SR
-0.5
0.6
8
+0.5
1.8
25
µA
mA
mA
V/µs
MHz
dB
1.1
13
Source Current
Slew Rate
Note 2
Note 2
Note 2
7
12
20
GBWP
Gain-Bandwidth Product
DC Gain
20
100
2.8
30
40
Gain
110
3.9
120
4.3
100
Vmax(E/A)
Vmin(E/A)
Maximum Voltage
Minimum Voltage
V
mV
8
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Remote Sense Differential Amplifier
BW_RS
Unity Gain Bandwidth
Note 2
Note 2
3
6.4
MHz
dB
Gain_RS
DC Gain
110
0.5V<RS+<2.555V, 4kOhm
load
270C<Tj<850C
-1.6
-3
0
1.6
3
Offset_RS
Offset Voltage
mV
0.5V<RS+<2.555V, 4kOhm
load
-400C<Tj<1250C
Isource_RS
Isink_RS
Slew_RS
Rin_RS+
Rin_RS-
Source Current
Sink Current
V_RSO=1.5V, V_RSP=4V
11
0.4
2
16
2
mA
mA
1
4
Slew Rate
Note 2, Cload = 100pF
8
V/µs
Kohm
Kohm
V
RS+ input impedance
RS- input impedance
Maximum Voltage
Minimum Voltage
Bootstrap Diode
Forward Voltage
Switch Node
36
36
0.5
55
55
1
74
74
1.5
20
Note 2
Vmax_RS
Min_RS
V(VCC) – V(RS+)
4
mV
I(Boot) = 40mA
150
300
18
450
1
mV
µA
Lsw
SW Leakage Current
SW = 0V, Enable = 0V
SW=0; Enable= 2V
Isw_En
Internal Regulator (VCC/LDO)
VCC
Output Voltage
Vin(min) = 5.5V, Io=0mA,
Cload = 10uF
4.8
4.5
5.15
4.99
5.4
5.2
0.7
V
Vin(min) = 5.5V, Io=70mA,
Cload = 10uF
VCC_drop
Ishort
VCC dropout
Io=0-70mA, Cload = 10uF,
Vin=5.1V
V
Short Circuit Current
110
mA
Internal Regulator (P1V8)
P1V8
Output Voltage
Vin(min) = 4.5V, Io = 0‐1mA,
Cload = 2.2uF
1.795
1.83
1.905
V
P1V8_UVLO_Start
P1V8_UVLO_Stop
1.8V UVLO Start
1.8V UVLO Stop
1.8V Rising Trip Level
1.66
1.59
1.72
1.63
1.78
1.68
V
V
1.8V Falling Trip Level
Adaptive On time Mode
ZC_Vth
Zero-crossing
comparator threshold
-4
-1
2
mV
S
ZC_Tdly
Zero-crossing
comparator delay
8/Fs
9
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
PARAMETER
SYMBOL
CONDITIONS
FAULTS
MIN
TYP
MAX
UNIT
Power Good
Power_Good_High
Power_Good_Low
Power Good High
threshold
Vsns rising,
VOUT_SCALE_LOOP=1,
Vout=0.5V, PMBus™ mode
0.45
0.43
V
Power Good Low
Threshold
Vsns falling,
VOUT_SCALE_LOOP=1,
Vout=0.5V, PMBus™ mode
V
TPDLY
Power Good High
Threshold Rising Delay
Vsns rising, Vsns >
Power_Good_High
0
ms
VPG_low_Dly
PG (voltage)
Power Good Low
Threshold Falling delay
Vsns falling, Vsns <
Power_Good_Low
150
175
200
0.5
µs
V
PGood Voltage Low
IPGood = -5mA
Over Voltage Protection (OVP)
OVP (trip)
OVP Trip Threshold
Vsns rising,
VOUT_SCALE_LOOP=1,
Vout=0.5V
0.60
5
0.57
20
0.63
40
V
OVP (hyst)
OVP comparator
Hysteresis
Vsns falling,
VOUT_SCALE_LOOP=1,
Vout=0.5V
30
mV
ns
OVP (delay)
OVP Fault Prop Delay
Vsns rising, Vsns-
OVP(trip)>200 mV
200
Over-Current Protection
ITRIP IR38163/165
ITRIP IR38363/365
Tblk_Hiccup
OC limit=40, VCC = 5.05V,
Tj=250C
36
40
16
20
44
A
A
A
OC limit=16A, VCC = 5.05V,
Tj=250C
12.5
16.5
12.5
19.5
23.5
19.5
OC Trip Current
OC limit=20A, VCC = 5.05V,
Tj=250C
OC limit=16A, VCC = 5.05V,
Tj=250C
16
20
A
Hiccup blanking time
Thermal Shutdown
Thermal Shutdown
Hysteresis
Note 2
ms
Note 2
Note 2
145
25
°C
°C
Input Over-Voltage Protection
PVinOV
PVin overvoltage
threshold
22
23.7
2.4
25
V
V
PVin ov hyst
PVin overvoltage
Hysteresis
10
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
MONITORING AND REPORTING
Bus Speed1
100
78
400
kHz
Hz
Iout & Vout filter
31.2
5
Iout & Vout Update rate
Vin & Temperature filter
kHz
Hz
78
Vin
update rate
&
Temperature
31.2
5
kHz
Output Voltage Reporting
Resolution
NVout
1/256
0
Note 2
V
V
Vomon_low
Vomon_high
Lowest reported Vout
Highest reported Vout
Vsns=0V
VOUT_SCALE_LOOP=1,
Vsns=3.3V
3.3
6.6
V
V
V
V
VOUT_SCALE_LOOP=0.5,
Vsns=3.3V
VOUT_SCALE_LOOP=0.25,
Vsns=3.3V
13.2
26.4
VOUT_SCALE_LOOP=0.125
, Vsns=3.3V
Vout reporting accuracy
00C to 850C, 4.5V<Vcc<5.5V,
1V<Vsns≤ 1.5V
VOUT_SCALE_LOOP=1
+/-
0.6
00C to 850C, 4.5V<Vcc<5.5V,
Vsns> 1.5V
+/-1
VOUT_SCALE_LOOP=1
%
00C to 1250C,
4.5V<Vcc<5.5V, Vsns>0.9V
VOUT_SCALE_LOOP=1
+/-
1.5
00C to 1250C,
4.5V<Vcc<5.5V,
0.5V<Vsns<0.9V
VOUT_SCALE_LOOP=1
+/-3
Iout Reporting
NIout
Resolution
Note 2
0.06
25
A
Iout_dig
IR38163/165
0
40
20
A
A
Iout (digital) monitoring
Range
Iout_dig
IR38363/365
0
00C to 1250C, 4.5V<Vcc<5.5V,
5A < Iout <30A
IR38163/165
i2c/PMBus™ mode
Iout_dig Accuracy
+/-5
%
00C to 1250C, 4.5V<Vcc<5.5V,
IR38363/365
i2c/PMBus™ mode
11
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
PARAMETER
SYMBOL
CONDITIONS
5A < Iout <15A
MIN
TYP
MAX
UNIT
00C to 1250C, 4.5V<Vcc<5.5V
Intel
VR1
3
SVID mode
IR38163/165/363/365
Intel
VR13
spec
Intel
VR13
spec
spec
Temperature Reporting
NTmon
Resolution
Note 2
Note 2
Note 2
1
°C
°C
Tmon_dig
Temperature Monitoring
Range
-40
150
Thermal shutdown
hysteresis
25
°C
Input Voltage Reporting
Resolution
NPVin
1/32
V
V
PMBVinmon
Monitoring Range
Monitoring accuracy
0
21
00C to 850C, 4.5V<Vcc<5.5V,
PVin>10V
-1.5
1.5
-400C to 1250C,
4.5V<Vcc<5.5V, PVin>14V
-1.5
-4
1.5
4
%
-400C to 1250C,
4.5V<Vcc<5.5V,
7V<PVin<14V
PMBus™ Interface Timing Specifications
FSMB
SMBus Operating
frequency
400
kHz
µs
TBUF
Bus Free time between
Start and Stop condition
1.3
0.6
THD:STA
Hold time after
(Repeated) Start
Condition. After this
period, the first clock is
generated.
µs
TSU:STA
Repeated start condition
setup time
0.6
0.6
µs
µs
TSU:STO
Stop condition setup
time
Data Rising Threshold
Data Falling Threshold
Clock Rising Threshold
Clock Falling Threshold
1.339
1.048
1.339
1.048
1.766
1.495
1.766
1.499
V
V
V
V
Data Rising Threshold
LVT
0.7
0.9
V
12
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Data Falling Threshold
LVT
0.45
0.7
0.65
0.9
V
V
V
Clock Rising Threshold
LVT
Clock Falling Threshold
LVT
0.45
0.65
900
THD:DAT
Data Hold Time
Data Setup Time
300
100
ns
ns
TSU:DAT
Data pulldown
resistance
8
9
11
12
16
Ω
Ω
SALERT# pulldown
resistance
17
35
TTIMEOUT
TLOW
Clock low time out
Clock low period
Clock High Period
25
1.3
0.6
ms
µs
µs
THIGH
50
Notes
2. Guaranteed by design but not tested in production
3. Guaranteed by statistical correlation, but not tested in production
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TYPICAL APPLICATION DIAGRAMS
5.5V <Vin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
For PVin >14V, a 1 ohm resistor is
required
P1V8
PVin
Enable
Vin
Boot
SW
Vo
Vcc/
LDO_out
Vsns
RS+
PGood
PGood
RS-
SV_CLK
SV_DIO
RSo
Fb
CPU
serial
bus
SV_ALERT
ADDR
Comp
LGnd
PGnd
Placeholder
for capacitor
Figure 4: Using the internal LDO, Vo < 2.555V
For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor.
5.5V <Vin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable
Vin
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
R2
PGood
RS-
SV_CLK
SV_DIO
CPU
serial
bus
RSo
Fb
Recommend R2=499 ohm
SV_ALERT
ADDR
Comp
LGnd
PGnd
Placeholder
for capacitor
Figure 5: Using the internal LDO, Vo > 2.555V
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TYPICAL APPLICATION DIAGRAMS
1.5V <PVin<16V
Optional placeholder for boot resistor.
Default should be 0 ohm
For PVin >14V, a 1 ohm resistor is
required
P1V8
PVin
Enable
Vin
Boot
Vcc=5V
PGood
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
RS-
SV_CLK
SV_DIO
CPU
serial
bus
RSo
Fb
SV_ALERT
Comp
LGnd
ADDR
PGnd
Placeholder
for capacitor
Figure 6: Using external Vcc, Vo<2.555V
PVin=Vin=Vcc= 5V
Optional placeholder for boot resistor.
Default should be 0 ohm
Boot
P1V8
PVin
Enable
Vin
Vo
Vcc/
LDO_out
SW
Vsns
RS+
PGood
PGood
RS-
SV_CLK
SV_DIO
RSo
Fb
CPU
serial
bus
SV_ALERT
ADDR
Comp
LGnd
PGnd
Placeholder
for capacitor
Figure 7: Single 5V application, Vo<2.555V
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TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
16
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TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
17
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TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
18
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TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
19
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IOUT REPORTING CURVES (SVID)
SVID readings with typical reporting gain
SVID readings with minimum reporting gain
SVID readings with maximum reporting gain
The Mean, min and max within each plot represent the variability in the SVID reading on a single part, due to
noise. The table below provides a summary of measurement gain and offset taken on a statistically significant
sample of parts.
Gain
Offset
Average
Standard deviation
Min
0.954
0.019
0.919
1.009
0.137
0.257
-0.465
0.95
Max
20
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TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = 12V, VCC = 5V, Io=0-30A, Fs= 600 kHz, Room Temperature, No Air Flow. Note that the losses of the
inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below
shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
LOUT (uH)
0.15
P/N
DCR (mΩ)
0.15
0.8
1
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-101 (Delta)
FP1308R3-R32-R (Cooper)
FP1308R3-R32-R (Cooper)
0.15
0.15
0.15
0.15
0.32
0.32
0.15
0.15
0.15
0.15
0.32
0.32
1.2
1.5
1.8
3.3
5
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TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = 12V, Internal LDO, Io=0-30A, Fs= 600 kHz, Room Temperature, No Air Flow. Note that the losses of the
inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below
shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
LOUT (uH)
0.15
P/N
DCR (mΩ)
0.15
0.8
1
HCB178380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
HCB138380D-101 (Delta)
FP1308R3-R32-R (Cooper)
FP1308R3-R32-R (Cooper)
0.15
0.15
0.15
0.15
0.32
0.32
0.15
0.15
0.15
0.15
0.32
0.32
1.2
1.5
1.8
3.3
5
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TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = VCC = 5V, Io=0-30A, Fs= 600 kHz, Room Temperature, No Air Flow. Note that the losses of the inductor,
input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the
indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
LOUT (uH)
0.1
P/N
DCR (mΩ)
0.15
0.8
1
1.2
1.5
1.8
HCB138380D-101 (Delta)
HCB138380D-101 (Delta)
HCB138380D-101 (Delta)
HCB138380D-151 (Delta)
HCB138380D-151 (Delta)
0.1
0.15
0.15
0.15
0.15
0.15
0.15
0.15
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THERMAL DERATING CURVES
The measurements were done on a standard evaluation kit demo board. The PCB is 7.0” x 5.5” x 0.072” with 10-
layers, FR4 material and 2 oz. copper. The conditions used were, PVin = Vin = 12V, Internal LDO, Io=30A, Fs=
978 kHz.
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THEORY OF OPERATION
DESCRIPTION
The IR38163 and IR38165 are 30A rated synchronous buck converters that support PMBus™ and I2C digital
interfaces respectively. The IR38363 and IR38365 are the corresponding 15A rated versions. All the four devices
in this family of OptiMOS™ IPOL devices are Intel SVID compliant and can support VR12.5 as well as VR13.
They use an externally compensated fast, analog, PWM voltage mode control scheme to provide good noise
immunity as well as fast dynamic response in a wide variety of applications. At the same time, the digital
communication interfaces allow complete configurability of output setting and fault functions, as well as telemetry.
The switching frequency is programmable from 150 kHz to 1.5 MHz and provides the capability of optimizing the
design in terms of size and performance. It is recommended to operate at 500 kHz or higher.
These devices provide precisely regulated output voltages from 0.5V to 0.875*PVin programmed via two external
resistors or through the communication interfaces. They operate with an internal bias supply (LDO), typically 5.2V.
This allows operation with a single supply. The output of this LDO is brought out at the Vcc pin and must be
bypassed to the system power ground with a 10 uF decoupling capacitor. The Vcc pin may also be connected to
the Vin pin, and an external Vcc supply between 4.5V and 5.5V may be used, allowing an extended operating bus
voltage (PVin) range from 1.5V to 16V.
The device utilizes the on-resistance of the low side MOSFET (synchronous MOSFET) as current sense element.
This method enhances the converter’s efficiency and reduces cost by eliminating the need for external current
sense resistor.
These devices includes two low Rds(on) MOSFETs using Infineon’s OptiMOS™ technology. These are specifically
designed for low duty cycle, high efficiency applications.
DEVICE POWER-UP AND INITIALIZATION
During the power-up sequence, when Vin is brought up, the internal LDO converts it to a regulated 5.2V at Vcc.
There is another LDO which further converts this down to 1.8V to supply the internal digital circuitry. An under-
voltage lockout circuit monitors the voltage of VCC pin and the P1V8 pin, and holds the Power-on-reset (POR)
low until these voltages exceed their thresholds and the internal 48 MHz oscillator is stable. When the device
comes out of reset, it initializes a multiple times programmable (MTP) memory load cycle, where the contents of
the MTP are loaded into the working registers. Once the registers are loaded from MTP, the designer can use
PMBus™ commands to re-configure the various parameters to suit the specific VR design requirements if
desired, irrespective of the status of Enable.
The typical default configuration utilizes the internal LDO to supply the VCC rail when PVin is brought up. For this
configuration power conversion is enabled only when the Enable pin voltage exceeds its under voltage threshold,
the PVin bus voltage exceeds its under voltage threshold, the contents of the MTP have been fully loaded into the
working registers and the device address has been read. The initialization sequence is shown in Figure 8.
Another common default configuration uses an external power supply for the VCC rail. While in this configuration
it is recommended to ensure the VCC rail reaches its target voltage prior the enable signal goes high.
Additional options are available to enable the device power conversion through software and these options may
be configured to override the default by using the I2C interface or PMBus™. For further details see the UN0075
IR3816x_IR3826x_IR3836x_PMBus™ commandset user note.
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PVIN=VIN
VCC
P1V8
UVOK
clkrdy
POR
Initialization
done
Enable
Vout
Figure 8: Initialization sequence showing PVin, Vin, Vcc, 1.8V, Enable and Vout signals as well as the internal logic
signals
I2C AND PMBUS™ COMMUNICATION
All the devices in this family have two 7-bit registers that are used to set the base I2C address and base PMBus™
address of the device, as shown below in Table 1.
Table 1: Registers used to set device base address
Register
I2c_address[6:0]
Description
The chip I2C address. An
address of 0 will disable
I2C communication. Note
that disabling I2C does not
disable PMBus™.
PMBus™_address[6:0]
The chip PMBus™
address. An address of 0
will disable PMBus™
communication. Note that
disabling PMBus™ does
not disable I2C.
In addition, a resistor may be connected between the ADDR and LGND pins to set an offset from the default
preconfigured I2C address (0x10) /PMBus™ address (0x40) in the MTP. Up to 16 different offsets can be set,
allowing 16 devices with unique addresses in a single system. This offset, and hence, the device address, is read
by the internal 10 bit ADC during the initialization sequence.
Table 2 below provides the resistor values needed to set the 16 offsets from the base address.
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Table 2 : Address offset vs. External Resistor(RADDR
)
ADDR Resistor
(Ohm)
Address Offset
+0
+1
499
1050
1540
2050
2610
3240
3830
4530
5230
6040
6980
7870
8870
9760
10700
>11800
+2
+3
+4
+5
+6
+7
+8
+9
+10
+11
+12
+13
+14
+15
The device will then respond to I2C/PMBus™ commands sent to this address. There is also a register bit
i2c_disable_addr_offset that may be set in order to instruct the device to ignore the resistor offset for both i2c and
PMBus™. If this bit is set, the device will always respond to commands sent to the base address.
MODES FOR SETTING OUTPUT VOLTAGES
These devices provide a configuration bit that allows the user to choose between PMBus™ and VID modes.
When this bit is set, the output voltage will ramp to the configured boot voltage and subsequently, respond to
voltage set commands issued by the CPU on the Serial VID (SVID) interface. The VID tables for 5mV and 10mV
VID steps are shown in the tables below. A VID code of 0 corresponds to 0V as well as the regulator shutdown
code in SVID mode. Vboot which is utilized in the SVID mode should never be set to 0 V as this will shutdown the
regulator. When this bit is zero, the regulation is determined by the output voltage set by the PMBus™ commands
(for the IR38163 and IR38363) or by the corresponding MTP registers (for the IR38165 and IR38365). It should
be noted that irrespective of the mode used to set the output voltage, telemetry information always remains
available on both the communications busses.
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Table 3: Intel 5mV VID table
VID
(Hex)
Voltage
(V)
VID
(Hex)
Voltage
(V)
VID
(Hex)
Voltage
(V)
VID
(Hex)
Voltage
(V)
VID
(Hex)
Voltage
(V)
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
EF
EE
ED
EC
EB
EA
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
1.52
1.515
1.51
1.505
1.5
1.495
1.49
1.485
1.48
1.475
1.47
1.465
1.46
1.455
1.45
1.445
1.44
1.435
1.43
1.425
1.42
1.415
1.41
1.405
1.4
1.395
1.39
1.385
1.38
1.375
1.37
1.365
1.36
1.355
1.35
1.345
1.34
1.335
1.33
1.325
1.32
1.315
1.31
1.305
1.3
1.295
1.29
1.285
1.28
1.275
1.27
1.265
1.26
1.255
1.25
1.245
1.24
C5
C4
C3
C2
C1
C0
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
BB
BA
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
AF
AE
AD
AC
AB
AA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
9F
9E
9D
9C
9B
9A
99
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
1.18
1.175
1.17
1.165
1.16
1.155
1.18
1.175
1.17
1.165
1.16
1.155
1.15
1.145
1.14
1.135
1.13
1.125
1.12
1.115
1.11
1.105
1.1
1.095
1.09
1.085
1.08
1.075
1.07
1.065
1.06
1.055
1.05
1.045
1.04
1.035
1.03
1.025
1.02
1.015
1.01
1.005
1
0.995
0.99
0.985
0.98
91
90
8F
8E
8D
8C
8B
8A
89
88
87
86
85
84
83
82
81
80
7F
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
5F
5E
5D
5C
5B
5A
59
58
0.97
0.965
0.96
0.955
0.95
0.945
0.94
0.935
0.93
0.925
0.92
0.915
0.91
0.905
0.9
0.895
0.89
0.885
0.88
0.875
0.87
0.865
0.86
0.855
0.85
0.845
0.84
0.835
0.83
0.825
0.82
0.815
0.81
0.805
0.8
0.795
0.79
0.785
0.78
0.775
0.77
0.765
0.76
0.755
0.75
0.745
0.74
0.735
0.73
0.725
0.72
0.715
0.71
0.705
0.7
0.695
0.69
57
56
55
54
53
52
51
50
4F
4E
4D
4C
4B
4A
49
48
47
58
57
56
55
54
53
52
51
50
4F
4E
4D
4C
4B
4A
49
48
47
46
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
0.68
0.675
0.67
0.665
0.66
0.655
0.65
0.645
0.64
0.635
0.63
0.625
0.62
0.615
0.61
0.605
0.6
0.685
0.68
0.675
0.67
0.665
0.66
0.655
0.65
0.645
0.64
0.635
0.63
0.625
0.62
0.615
0.61
0.605
0.6
0.595
0.59
0.585
0.58
0.575
0.57
0.565
0.56
0.555
0.55
0.545
0.54
0.535
0.53
0.525
0.52
0.515
0.51
0.505
0.5
0.495
0.49
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
13
12
11
10
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
0.48
0.475
0.47
0.465
0.46
0.455
0.45
0.445
0.44
0.435
0.43
0.425
0.42
0.415
0.41
0.405
0.4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
98
97
96
95
94
93
92
1.235
0.975
0.685
0.485
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Table 4: Intel 10mV VID table
VID
(HEX)
VOLTAGE
(V)
VID
(HEX)
VOLTAGE
(V)
VID
(HEX)
VOLTAGE
(V)
VID
(HEX)
VOLTAGE
(V)
VID
(HEX)
VOLTAGE
(V)
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
EF
EE
ED
EC
EB
EA
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
2.94
2.93
2.92
2.91
2.90
2.89
2.88
2.87
2.86
2.85
2.84
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
2.74
2.73
2.72
2.71
2.70
2.69
2.68
2.67
2.66
2.65
2.64
2.63
2.62
2.61
2.60
2.59
2.58
2.57
2.56
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
C5
C4
C3
C2
C1
C0
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
AF
AE
AD
AC
AB
AA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
9F
9E
9D
9C
9B
9A
99
2.46
2.45
2.44
2.43
2.42
2.41
2.40
2.39
2.38
2.37
2.36
2.35
2.34
2.33
2.32
2.31
2.30
2.29
2.28
2.27
2.26
2.25
2.24
2.23
2.22
2.21
2.20
2.19
2.18
2.17
2.16
2.15
2.14
2.13
2.12
2.11
2.10
2.09
2.08
2.07
2.06
2.05
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
1.95
1.94
1.93
1.92
1.91
1.90
1.89
8B
8A
89
88
87
86
85
84
83
82
81
80
7F
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
5F
5E
5D
5C
5B
5A
59
58
57
56
55
54
53
52
1.88
1.87
1.86
1.85
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
1.75
1.74
1.73
1.72
1.71
1.70
1.69
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
1.60
1.59
1.58
1.57
1.56
1.55
1.54
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.40
1.39
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.31
51
50
4F
4E
4D
4C
4B
4A
49
48
47
46
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
1.30
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.16
1.15
1.14
1.13
1.12
1.11
1.10
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
0.91
0.90
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.74
0.73
17
16
15
14
13
12
11
10
F
0.72
0.71
0.70
0.69
0.68
0.67
0.66
0.65
0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.51
0.50
E
D
C
B
A
9
8
7
6
5
4
3
2
1
98
97
96
95
94
93
92
91
90
8F
8E
8D
8C
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BUS VOLTAGE UVLO
If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be
ensured that the device does not turn on until the bus voltage reaches the desired level as shown in Figure 9.
Only after the bus voltage reaches or exceeds this level and voltage at the Enable pin exceeds its threshold
(typically 0.6V) will the device be enabled. Therefore, in addition to being logic input pin to enable the converter,
the Enable feature, with its precise threshold, also allows the user to override the default 8 V Under-Voltage
Lockout for the bus voltage (PVin). This is desirable particularly for high output voltage applications, where we
might want the device to be disabled at least until PVin exceeds the desired output voltage level. Alternatively, the
default 8 V PVin UVLO threshold may be reconfigured/overridden using the VIN_ON and VIN_OFF PMBus™
commands or the corresponding registers. It should be noted that the input voltage is also fed to an ADC through
a 21:1 internal resistive divider. However, the digitized input voltage is used only for the purposes of reporting the
input voltage through the READ_VIN PMBus™ command. It has no impact on the bus voltage UVLO, input
overvoltage faults and input undervoltage warnings, all of which are implemented by using analog comparators to
compare the input voltage to the corresponding thresholds programmed by the PMBus™ commands VIN_ON,
VIN_OFF, VIN_OV_FAULT_LIMIT and VIN_UV_WARN_LIMIT respectively. The bus voltage reading as reported
by READ_VIN has no effect on the input feedforward function either.
12V
10.2V
1 V
PVin
Vcc
> 0.6V
0.6V
EN_UVLO_START
EN
DAC2 (Reference DAC)
Figure 9: Normal Start up, device turns on when the bus voltage reaches 10.2A. A resistor divider is used at EN pin
from PVin to turn on the device at 10.2V.
PVin=Vin
Vcc
> 0.6V
EN
DAC2 (Reference DAC)
Figure 10: Recommended startup for Normal operation
Figure 10 shows the recommended startup sequence for the normal operation of the device, when Enable is used
as logic input.
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PRE-BIAS STARTUP
These devices can start up into a pre-charged output, which prevents oscillation and disturbances of the output
voltage.
The output starts in asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate
signal for control MOSFET (Ctrl FET) is generated. Figure 11 shows a typical Pre-Bias condition at start up. The
sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty
cycle with a step of 12.5%, with 16 cycles at each step, until it reaches the steady state value. Figure 12 shows
the series of 16x8 startup pulses.
[V]
Vo
Pre-Bias
Voltage
[Time]
Figure 11: Pre-Bias startup
...
HDRv
...
...
...
...
87.5%
12.5%
16
25%
...
LDRv
...
...
...
End of
PB
...
16
Figure 12: Pre-Bias startup pulses
SOFT-START (REFERENCE DAC RAMP)
These devices have an internal soft starting DAC to control the output voltage rise and to limit the current surge at
the start-up. To ensure correct start-up, the DAC sequence initiates only after power conversion is enabled when
the Enable pin voltage exceeds its undervoltage threshold, the PVin bus voltage exceeds its undervoltage
threshold and the contents of the MTP have been fully loaded into the working registers. Figure 13 shows the
waveforms during soft start. It should be noted that the part may also be configured to require software Enable
(set through the PMBus™ or the corresponding MTP register) instead of or in addition to a “hardware” signal at
the Enable pin. In PMBus™ mode, the reference DAC soft-start may be delayed from the time power conversion
is enabled. The range for this programmable delay is 0ms to 127 ms, and the resolution is 1 ms. Further, in this
mode, the soft start time may be configured from 1ms to 127 ms with 1 ms resolution.
In SVID mode, the rise time is determined by the slow slew rate specified by Intel, and may be programmed to
one of four values: 0.625mV/us, 1.25 mV/us, 2.5 mV/us and 5 mV/us. In this mode, the device uses 2.5 mV/us by
default. It should be noted, however, that if Vboot is 0, the output voltage does not ramp until the CPU issues a
voltage setting command at either the fast slew rate or slow slew rate specified by the CPU.
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For more details on the PMBus™ commands TON_DELAY and TON_RISE used to program the startup
sequence, please see the UN0075 IR3816x_IR3826x_IR3836x_PMBUS™ commandset user note.
Internal Enable
Reference
DAC
Vout
Ton_delay
t1
Ton_rise
t3
t
2
Figure 13: DAC2 (VREF) Soft start
During the startup sequence the over-current protection (OCP) and over-voltage protection (OVP) are active to
protect the device against any short circuit or over voltage condition.
OPERATING FREQUENCY
Using the FREQUENCY_SWITCH PMBus™ command, or the corresponding registers, the switching frequency
may be programmed between 150 kHz and 1.5 MHz. For best telemetry accuracy, it is recommended that the
following switching frequencies be avoided: 250 kHz, 300 kHz, 400 kHz, 500 kHz, 600 kHz, 750 kHz, 800 kHz, 1
MHz, 1.2 MHz and 1.5 MHz. Instead, it is recommended to use the following values 251 kHz, 302 kHz, 403 kHz,
505 kHz, 607 kHz, 762 kHz, 813 kHz, 978 kHz, 1171 kHz and 1454 kHz respectively.
SHUTDOWN
In the default configuration, the device can be shutdown by pulling the Enable pin below its 0.4V threshold.
During shutdown the high side and the low side drivers are turned off. By default, the device exhibits an
immediate shutdown with no delay and no soft stop.
Alternatively, the part may be configured to allow shutdown using the OPERATION PMBus™ command or the
corresponding register. It may also be configured to allow a soft or controlled turned off. In PMBus™ mode, if the
soft-off option is used, the turn off may be delayed from the time the power conversion is disabled. The range for
this programmable delay is 0ms to 127 ms, and the resolution is 1 ms. Further, in this mode, the soft stop time
may be configured from 1ms to 127 ms with 1 ms resolution. The programmable turn off delay only applies in
PMBus™ mode. In PVID mode, if the soft-stop option is used, the output voltage slews down at 0.625 mV/us.
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CURRENT SENSING, TELEMETRY AND OVER CURRENT PROTECTION
Current sensing for both, telemetry as well as overcurrent protection is done by sensing the voltage across the
sync FET Rdson. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense
resistor and any minimizes sensitivity to layout related noise issues. A novel, patented scheme allows
reconstruction of the average inductor current from the voltage sensed across the Sync FET Rdson. It should be
noted here that it is this reconstructed average inductor current that is digitized by the ADC and used for output
current reporting as well as for overcurrent warning, the threshold for which may be set using the
IOUT_OC_WARN_LIMIT command. The current is reported in 1/16A resolution using the READ_IOUT PMBus™
command. For the IR38165 and IR38365, which support I2C communication, but not PMBus™, the current
information may be read back through the 8-bit register output_current_byte, which reports the current in 1/4 A
resolution.
The Over current (OC) fault protection circuit also uses the voltage sensed across the RDS(on) of the Synchronous
MOSFET; however, the protection mechanism relies on a fast comparator to compare the sensed signal to the
overcurrent threshold and does not depend on the ADC or reported current. The current limit scheme uses an
internal temperature compensated current source that has the same temperature coefficient as the RDS(on) of the
Synchronous MOSFET. As a result, the over-current trip threshold remains almost constant over temperature.
Over Current Protection circuitry senses the inductor current flowing through the Synchronous FET closer to the
valley point. The OCP circuit samples this current for 75 ns typically after the rising edge of the PWM set pulse
which is an internal signal that has a width of 12.5% of the switching period. The PWM pulse that turns on the
high side FET starts at the falling edge of the PWM set pulse. This makes valley current sense more robust as
current is sensed close to the bottom of the inductor downward slope where transient and switching noise is low.
This helps to prevent false tripping due to noise and transients.
The actual DC output current limit point will be greater than the valley point by an amount equal to approximately
half of the peak to peak inductor ripple current. The current limit point will be a function of the inductor value, input
voltage, output voltage and the frequency of operation. On equation 1, ILimit is the value set when configuring the
OCP value. The user should account for the inductor ripple to obtain the actual DC output current limit.
i
2
IOCP ILIMIT
(1)
IOCP
ILIMIT
Δi
= DC current limit hiccup point
= Current Limit Valley Point
= Inductor ripple current
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Current Limit
Hiccup
Tblk_Hiccup
20 ms
IL
0
HDrv
...
...
0
LDrv
0
PGood
0
Figure 14: Timing Diagram for Current Limit Hiccup
In the default configuration, if the overcurrent detection trips the OCP comparator for a total of 8 cycles, the device
goes into a hiccup mode. The hiccup is performed by de-asserting the internal Enable signal to the analog and
power conversion circuitry and holding it low for 20 ms.
Following this, the OCP signal resets and the converter recovers. After every hiccup cycle, the converter stays in
this mode until the overload or short circuit is removed. This behavior is shown in Figure 14.
It should be noted that on some units, a false OCP maybe experienced during device start-up due to noise. The
part will ride through this false OCP due to the pulse by pulse current limiting feature and successfully ramp to the
correct output voltage. However, it is recommended to send a PMBUS™ Clear_Faults command after start-up to
reset the PMBUS™ SAlert# to a high and to clear the PMBUS™ status register for faults.
Note that the user can override the default overcurrent threshold using the PMBus™ command
IOUT_OC_FAULT_LIMIT. For the IR38163/IR38165 it is recommended that the overcurrent threshold be
programmed to at least 16A for good accuracy. For the IR38363/IR38365 a minimum threshold of 12A is
recommended. While these devices will still offer overcurrent protection for thresholds programmed lower than
these recommended values, the thresholds will not be as accurate.
Also, using the PMBus™ command IOUT_OC_FAULT_RESPONSE or the corresponding registers, the part may
be configured to respond to an overcurrent fault in one of two ways
1) Pulse by pulse current limiting for a programmed number of 8 switching cycles followed by a latched
shutdown.
2) Pulse by pulse current limiting for a programmed number of 8 switching cycles followed by hiccup. This is
the default explained above.
The pulse-by-pulse or constant current limiting mechanism is briefly explained below.
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IOUT_OC_FAULT_LIMIT
IL
20 ms
0
HDrv
0
LDrv
0
CLK
Fs
0
OCP High
1
2
3
4
5
6
7
8
Internal
Enable
Figure 15: Pulse by pulse current limiting for 8 cycles, followed by hiccup.
In Figure 15, overcurrent response is set to pulse-by-pulse current limiting for 8 cycles followed by hiccup, the
converter is operating at D<0.125 when the overcurrent condition occurs. In such a case, no duty cycle limiting is
applied.
IO UT_OC_FAULT_LIMIT
IL
0
HDrv
0
LDrv
0
CLK
Fs
0
OCP High
1
2
3
4
5
6
7
8
9
10
11
...
Internal
Enable
Figure 16: Constant current limiting.
Figure 16 depicts a case where the overcurrent condition happens when the converter is operating at D>0.5 and
the overcurrent response has been set to Constant current operation through pulse by pulse current limiting. In
such a case, after 3 consecutive overcurrent cycles are recognized, the pulse width is dropped such that D=0.5
and then after 3 more consecutive OCP cycles, to 0.25 and then finally to 0.125 at which it keeps running until the
total OCP count reaches the programmed maximum following which the part enters hiccup mode. Conversely,
when the overcurrent condition disappears, the pulse width is restored to its nominal value gradually, by a similar
mechanism in reverse; every sequence of 4 consecutive cycles in which the current is below the overcurrent
threshold doubles the duty cycle, so that D goes from 0.125 to 0.25, then to 0.5 and finally to its nominal value.
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DIE TEMPERATURE SENSING, TELEMETRY AND THERMAL SHUTDOWN
On die temperature sensing is used for accurate temperature reporting and over temperature detection. The
READ_TEMEPRATURE PMBus™ command reports this temperature in 10C resolution. For the IR38165 and
IR38365, which do not support PMBus™ communication, the temperature may be read back through the 8-bit
register temp_byte, which reports the die temperature in 10C resolution, offset by 400C. Thus, the temperature is
given by temp_byte +400C.
The trip threshold is set by default to 125oC. The default over temperature response of the device is to inhibit
power conversion while the fault is present, followed by automatic restart after the fault condition is cleared.
Hence, in the default configuration, when trip threshold is exceeded, the internal Enable signal to the power
conversion circuitry is de-asserted, turning off both MOSFETs.
Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 25oC
hysteresis in the thermal shutdown threshold.
The default overtemperature threshold as well as overtemperature response may be re-configured or overridden
using the OT_FAULT_LIMIT and OT_FAULT_RESPONSE PMBus™ commands respectively. For the IR38165
and IR38365, which do not support PMBus™, the corresponding registers may be used. The devices support
three types of responses to an over-temperature fault:
1) Ignore
2) Inhibit when over temperature condition exists and auto-restart when over temperature condition
disappears
3) Latched shutdown.
REMOTE VOLTAGE SENSING
True differential remote sensing in the feedback loop is critical to high current applications where the output
voltage across the load may differ from the output voltage measured locally across an output capacitor at the
output inductor, and to applications that require die voltage sensing.
The RS+ and RS- pins form the inputs to a remote sense differential amplifier with high speed, low input offset
and low input bias current, which ensure accurate voltage sensing and fast transient response in such
applications.
The input range for the differential amplifier is limited to 1.5V below the VCC rail. Therefore, for applications in
which the output voltage is more than 3V, it is recommended to use local sensing, or if remote sensing is a must,
then the voltage between the RS+ and RS-pins must be divided down to less than 3V using a resistive voltage
divider. It’s recommended that the divider be placed at the input of the remote sense amplifier and that a low
impedance such as 499 Ω be used between the RS+ and RS- nodes. A typical schematic for this setup is shown
on Figure 5. Please note, however, that this modifies the open loop transfer function and requires a change in the
compensation network to optimally stabilize the loop.
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FEED-FORWARD
Feed-Forward (F.F.) is an important feature, because it can keep the converter stable and preserve its load
transient performance when PVin varies over a wide range. The PWM ramp amplitude (Vramp) is proportionally
changed with PVin to maintain PVin/Vramp almost constant throughout PVin variation range (as shown in Figure
17). Thus, the control loop bandwidth and phase margin can be maintained constant. The feed-forward function
can also minimize impact on output voltage from fast PVin change. The feed-forward is disabled for PVin<4.7V.
Hence, for PVin<4.7V, a re-calculation of control loop parameters is needed for re-compensation.
21V
12V
12V
5V
PVin
0
PWM Ramp
Ramp Offset
0
Figure 17: Timing Diagram for Feed-Forward (F.F.) Function
LIGHT LOAD EFFICIENCY ENHANCEMENT (AOT)
These devices implement a diode emulation scheme with Adaptive On Time control or AOT to improve light load
efficiency. It is based on a COT (Constant On Time) control scheme with some novel advancements that make
the on-time during diode emulation adaptive and dependent upon the pulse width in constant frequency operation.
This allows the scheme to be combined with a PWM scheme, while providing relatively smooth transition between
the two modes of operation. In other words, the switching regulator can operate in AOT mode at light loads and
automatically switch to PWM at medium and heavy loads and vice versa. Therefore, the regulator will benefit from
the high efficiency of the AOT mode at light loads, and from the constant frequency and fast transient response of
the PWM at medium to heavy loads.
In PMBus™ mode, a MFR_SPECIFIC PMBus™ command (MFR_FCCM) can be used to enable AOT operation
at light load for the IR38163 and IR38363. For the IR38165 and IR38365, the corresponding mtp register bit
mfr_fccm must be set to 0 to allow AOT operation. In SVID mode, there are two ways in which AOT operation
may be enabled:
a) Auto-PS: Set the mfr_fccm bit to 0.
b) PS commands issued by the CPU: Set the mfr_fccm bit to 1. The device will then allow AOT operation
only if commanded to power states PS2, PS3 or PS4 by the CPU. Conversely, a command to power
states PS0 or PS1 or a VID command to a higher voltage will disable AOT operation.
If it is desired that AOT operation be disabled altogether (recommended), allowing neither Auto-PS nor PS
commands issued by the CPU to enable AOT operation, it is essential to
a) The svid_ps_override bit must be set to 1.
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b) Set svid_ps_override_val[2:0] to 0.
c) Set the mfr_fccm bit to 1.
Shortly after the reference voltage has finished ramping up, an internal circuit which is called the “calibration
circuit” starts operation. It samples the Comp voltage (output of the error amplifier), digitizes it and stores it in a
register. There is a DAC which converts the value of this register to an analog voltage which is equal to the
sampled Comp voltage. At this time, the regulator is ready to enter AOT mode if the load condition is appropriate.
If the load is so low that the inductor current becomes negative before the next SW pulse, the operation can be
switched to AOT mode. The condition to enter AOT is the occurrence of 8 consecutive inductor current zero
crossings in eight consecutive switching cycles. If this happens, operation is switched to AOT mode as shown in
Figure 18. The inductor current is sensed using the RDS_ON of the Sync-FET and no direct inductor current
measuring is required. In AOT mode, just like COT operation, pulses with constant width are generated and diode
emulation is utilized. This means that a pulse is generated and LDrv is held on until the inductor current becomes
zero. Then both HDrv and LDrv remain off until the voltage of the sense pin comes down and reaches the
reference voltage. At this moment the next pulse is generated. The sense pin is connected to the output voltage
by a resistor divider which has the same ratio as the voltage divider which is connected to the feedback pin (Fb).
...
Vout
0
8/Fs delay
Diode
Emulation
IL
...
0
Ton
...
...
SW
...
...
0
HDrv
0
LDrv
...
...
0
Reduced Switching
Frequency
1/Fs
Figure 18: Timing Diagram for Reduced Switching Frequency and Diode Emulation in Light Load Condition (AOT
mode)
When the load increases beyond a certain value, the control is switched back to PWM through either of the
following two mechanisms:
1) If due to the increase in load, the output voltage drops to 95% of the reference voltage.
2) If Vsense remains below the reference voltage for 3 consecutive inductor current zero-cross events
It is worth mentioning that in AOT mode, when Vsense comes down to reference voltage level, a new pulse in
generated only if the inductor current is already zero. If at this time the inductor current (sensed on the Sync-FET)
is still positive, the new pulse generation is postponed till the current decays to zero. The second condition
mentioned above usually happens when the load is gradually increased.
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AOT is disabled during output voltage transitions. It is enabled only after reference voltage finishes its ramp (up or
down) and the calibration circuit has sampled and held the new Comp voltage.
In general, AOT operation is more jittery and noisier than FCCM operation, where the switching frequency may
vary from cycle to cycle, giving increased Vout ripple and noisier, inconsistent telemetry. Therefore, it is
recommended to use FCCM mode of operation as far as possible.
OUTPUT VOLTAGE SENSING, TELEMETRY AND FAULTS
For this family of devices, the voltage sense and regulation circuits are decoupled, enabling ease of testing as
well as redundancy. In order to do this, the device uses the sense voltage at the dedicated Vsns pin for output
voltage reporting (in 1/256 V resolution, using the READ_VOUT PMBus™ command) as well as for power good
detection and output overvoltage protection.
Power good detection and output overvoltage detection rely on fast analog comparator circuits, whereas
overvoltage warnings as well as undervoltage faults and warnings rely on comparing the digitized Vsns to the
corresponding
thresholds
programmed
using
PMBus™
commands
VOUT_OV_WARN_LIMIT,
VOUT_UV_FAULT_LIMIT and VOUT_UV_WARN_LIMIT respectively (or the corresponding registers in the case
of IR38165 and IR38365).
Power Good Output
The Vsns voltage is an input to the window comparator with programmable thresholds. The PGood signal is high
whenever Vsns voltage is within the PGood comparator window thresholds. The PGood pin is open drain and it
needs to be externally pulled high. High state indicates that output is in regulation. For the IR38163 and IR38363,
the Power Good thresholds may be changed through the POWER_GOOD_ON and POWER_GOOD_OFF
commands, which set the rising and falling PGood thresholds respectively. For the IR38165 and IR38365, which
lack PMBus™, the thresholds may be programmed using the corresponding mtp registers. However, when no
resistive divider is used, such as for output voltages lower than 2.555V, the Power Good thresholds must be
programmed to within 630 mV of the output voltage, otherwise, the effective power good threshold changes from
an absolute threshold to one that tracks the output voltage with a 630 mV offset. By default, the PGood signal will
assert as soon as the Vsns signal enters the regulation window. In digital mode, this delay is programmable from
0 to 10ms with a 1 ms resolution, using the MFR_TPGDLY command.
The threshold is set differently in SVID mode. In this mode, the thresholds set by the POWER_GOOD_ON and
POWER_GOOD_OFF commands (or the corresponding registers) are ignored. Power Good is asserted when the
output voltage is within the tolerance band of the boot voltage. Following this, the Power Good signal remains
asserted irrespective of any output voltage transitions and is de-asserted only in the event of a fault that shuts
down power conversion, or, if so programmed, in the event of a command by the CPU to change the output
voltage to 0 V.
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Fault DAC
0
Reference DAC
0
Power Good upper threshold
Vsns
0
Power Good lower threshold
PGD
0
160us
Figure 19: Power Good in PMBus™ mode
Fault DAC
0
Reference DAC
0
Vboot+/-TOB
Vsns
0
PGD
0
Figure 20: Power Good in SVID mode, Vboot >0 V
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Over-Voltage Protection (OVP)
Over-voltage protection is achieved by comparing sense pin voltage Vsns to a configurable overvoltage threshold.
The OVP threshold may be reprogrammed to within 655 mV of the output voltage (for output voltages lower than
2.555V, without any resistive divider on the Fb pin), using the VOUT_OV_FAULT_LIMIT PMBus™ command or
the corresponding registers (for IR38363 and IR38365). For an OVP threshold programmed to be more than 655
mV greater than the output voltage, the effective OV threshold ceases to be an absolute value and instead tracks
the output voltage with a 655 mV offset.
When Vsns exceeds the over voltage threshold, an over voltage trip signal asserts after 200ns (typ.) delay. The
default response is that the high side drive signal HDrv is latched off immediately and PGood flags are set low.
The low side drive signal is kept on until the Vsns voltage drops below the threshold. HDrv remains latched off
until a reset is performed by cycling either Vcc or Enable or the OPERATION command. The device allows the
user to reconfigure this response by the use of the VOUT_OV_FAULT_RESPONSE PMBus™ command. In
addition to the default response described above, this command can be used to configure the device such that
Vout overvoltage faults are ignored and the converter remains enabled. (However, they will still be flagged in the
STATUS_REGISTERS and by¯S¯A¯le¯r¯t ). For further details on the corresponding PMBus™ commands related to
OVP, please refer to the UN0075 IR3816x_IR3826x_IR3836x_PMBUS™ commandset user note.
Vsns voltage is set by an external resistive voltage divider connected to the output. This divider ratio must match
the divider used on the feedback pin or on the RS+ pin.
It should be noted that the overvoltage threshold applies in PMBus™ mode as well as SVID mode.
DAC1+OV_OFFSET_DAC
Vout
DAC1
hysteresis
0
HDrv
0
LDrv
0
Comp
0
PGood
0
200 ns
200 ns
Figure 21: Timing Diagram for OVP in non-tracking mode
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MINIMUM ON TIME CONSIDERATIONS
The minimum ON time is the shortest amount of time for Ctrl FET to be reliably turned on. This is a very critical
parameter for low duty cycle, high frequency applications. In the conventional approach, when the error amplifier
output is near the bottom of the ramp waveform with which it is compared to generate the PWM output,
propagation delays can be high enough to cause pulse skipping, and hence limit the minimum pulse width that
can be realized. Moreover, in the conventional approach, the bottom of the ramp often presents a high gain region
to the error amplifier output, making the modulator more susceptible to noise and requiring the use of lower
control loop bandwidth to prevent noise, jitter and pulse skipping.
Infineon has developed a proprietary scheme to improve and enhance the minimum pulse width which minimizes
these delays and hence, allows stable operation with pulse-widths as small as 35ns. At the same time, this
scheme also has greater noise immunity, thus allowing stable, jitter free operation down to very low pulse widths
even with a high control loop bandwidth, thus reducing the required output capacitance.
Any design or application using these devices must ensure operation with a pulse width that is higher than the
minimum on-time and at least 50 ns of on-time is recommended in the application. This is necessary for the circuit
to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage
ripple.
Vout
Fs PV Fs
D
(2)
ton
in
In any application that uses these devices, the following condition must be satisfied:
(3)
ton(min) ton
Vout
ton(min)
(4)
(5)
PV Fs
in
Vout
PV Fs
in
ton(min)
The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.5V. Therefore, for Vout(min)
0.5V,
=
Vout
(6)
PV Fs
in
ton(min)
0.5V
PVin Fs
10 V/μs
50ns
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Therefore, at the maximum recommended input voltage 16V and minimum output voltage, the converter should
be designed at a switching frequency that does not exceed 625 kHz. Conversely, for operation at the maximum
recommended operating frequency (1.5 MHz) and minimum output voltage (0.5V), the input voltage (PVin) should
not exceed 6.7 V, otherwise pulse skipping may happen.
MAXIMUM DUTY RATIO
An upper limit on the operating duty ratio is imposed by the larger of a) A fixed off time (dominant at high
switching frequencies) b) blanking provided by the PWMSet or clock pulse, which has a pulse width that is 1/8 of
the switching period. The latter mechanism is dominant at lower switching frequencies (typically below 1.25 MHz).
This upper limit ensures that the Sync FET turns on for a long enough duration to allow recharging the bootstrap
capacitor and also allows current sensing. Figure 22 shows a plot of the maximum duty ratio vs. the switching
frequency with built in input voltage feed forward mechanism.
Figure 22: Maximum duty cycle vs. switching frequency
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BOOTSTRAP CAPACITOR
To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW
pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration,
which comprises the internal bootstrap diode and an external bootstrap capacitor (C1). Typically a 0.1uF
capacitor is used. A layout placement for a 0 ohm resistor in series with the capacitor is also recommended. For
applications where PVin>14V, a 1 ohm resistor is required. The operation of the circuit is as follows: When the
sync FET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges
towards Vcc through the internal bootstrap diode (Figure 23), which has a forward voltage drop VD. The voltage Vc
across the bootstrap capacitor C1 is approximately given as:
Vc Vcc VD
(7)
When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage
PVin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately
unchanged and the voltage at the Boot pin becomes:
VBoot PV V VD
(8)
in
cc
Cvin
PVIN
+ VD
-
Boot
V
cc
+
Vc
-
C1
SW
L
IR38163
PGnd
Figure 23: Bootstrap circuit to generate high side drive voltage
INTEL SVID INTERFACE
These devices implement a fully compliant Intel® VR 13, and VR 12.5 Serial VID (SVID) interface. This is a three-
wire interface between an Intel processor and a VR that consists of clock, data and alert# signals.
This family of devices implements all the required SVID registers and commands per Intel specifications. For the
selected Intel mode, these devices also implement most of the optional commands and registers with very few
exceptions.
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The default SVID addresses of these devices are as below. This address can be re-programmed in MTP.
Device
Default SVID address
IR38163, IR38165
IR38363, IR38365
02
03
ALL CALL SUPPORT
All Call for these devices can be configured in following ways:
0E and 0F.
0E only.
0F only.
No All Call
The devices can be configured to be used as VR for CPU which is All Call 0F or Memory which is All Call 0E.
VR 12.5 OPERATION
VR 12.5 mode is selectable via MTP bit. The boot voltage in VR 12.5 is also selectable and can be taken from the
boot registers. The resolution is programmable via MTP bit to 10 mV to be compatible to VR12.5 mode.
VR 13 OPERATION
VR 13 mode is selectable via MTP bit. The boot voltage in VR 13 mode is configured in the boot register. The
resolution is programmable via MTP bit to 5 mV to be compatible to VR13 mode.
SET WORK POINT
This family of devices supports SVID Set WP command to Set VID voltage for all rails through all call address.
When processor asserts a Set WP command, all the rails of the VR settle to the corresponding new set voltage
encoded in WP registers. Slew rate and power state of all the rails are identical during a set work point operation.
DYNAMIC VID SLEW RATE
The device provides the VR designer 16 fast slew rates that govern the rate of VID transitions. The slow slew rate
is also programmable as a function of the fast slew rate, and 4 different options are available for each setting of
the fast slew rate as shown below in Table 5.
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TABLE 5: SLEW RATES
x 1/2
x 1/4
Fast
Rate
x 1/8
Factor
x 1/16
Factor
Factor
Factor
10
15
20
25
30
35
40
45
50
55
60
65
70
80
5.0
7.5
10
2.50
3.75
5.00
6.25
7.5
1.25
1.875
2.50
3.125
3.75
4.375
5.0
0.0625
0.94
1.25
1.56
1.88
2.19
2.5
12.5
15
17.5
20
8.75
10
mV/
µs
22.5
25
11.25
12.5
13.75
15
5.625
6.25
6.875
7.5
2.81
3.125
3.4375
3.75
4.0625
4.375
5
27.5
30
32.5
35
16.25
17.5
20
8.125
8.75
10
40
LOOP COMPENSATION
Feedback loop compensation is achieved using standard Type III techniques and the compensation values can
be easily calculated using Infineon’s design tool. The design tool can also be used to predict the control
bandwidth and phase margin for the loop for any set of user defined compensation component values. For a
theoretical understanding of the calculations used, please refer to Infineon’s Application Note AN-1162
“Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier”.
DYNAMIC VID COMPENSATION
This family of devices uses an analog control scheme with voltage mode control. In this scheme, the compensator
acts on the Vout signal and not just on the error signal. For load and line transients, with a steady and unchanging
reference voltage, this has the same dynamic characteristics as for a compensator that acts on only the error
signal. However, for reference voltage changes, as in the case of Dynamic VID, the dynamics are altered. A
proprietary and patented dynamic VID compensation scheme allows the dynamic VID response to be tuned
optimally to the feedback compensator values. Once properly optimized, the output voltage will follow the DAC
more closely during a positive dynamic VID, and provide better dynamic VID alert timing, as required by Intel®
processors. Infineon’s design tool will allow the user to quickly and conveniently calculate the dynamic VID
compensation parameters for optimal dynamic VID response.
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LAYOUT RECOMMENDATIONS
The layout is very important when designing high frequency switching converters. Layout will affect noise pickup
and can cause a good design to perform with less than expected results.
Make the connections for the power components in the top layer with wide, copper filled areas or polygons. In
general, it is desirable to make proper use of power planes and polygons for power distribution and heat
dissipation.
The input capacitors, inductor, output capacitors and the device should be as close to each other as possible.
This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place
the input capacitor directly at the PVin pin of IR38x6x.
Power vias should be at least 20/10 mil and a good rule of thumb is to design at 2A/via.
The feedback part of the system should be kept away from the inductor and other noise sources.
The critical bypass components such as capacitors for Vin, VCC and 1.8V should be close to their respective
pins. It is important to place the feedback components including feedback resistors and compensation
components close to Fb and Comp pins.
In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to
which all signals are referenced. The goal is to localize the high current path to a separate loop that does not
interfere with the more sensitive analog control functions. These two grounds must be connected together on the
PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground
plane in top layer.
The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at
least a 6-layer PCB. To effectively remove heat from the device the exposed pad should be connected to the
ground plane using vias.
IR38163/165/363/365 devices have 3 pins, SCL, SDA and SALERT# that are used for I2C/PMBus™
communication. It is recommended that the traces used for these communication lines be at least 10 mils wide
with spacing between the SCL and SDA traces that is at least 2-3 times the trace width.
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I2C PROTOCOLS
All registers may be accessed using either I2C or PMBus™ protocols. I2C allows the use of a simple format
whereas PMBus™ provides error checking capability. Figure 24 shows the I2C format employed by the IC.
S: Start Condition
1
S
7
1
1
A
8
1
A
8
1
A
1
P
A: Acknowledge (0')
N: Not Acknowledge (1')
Sr: Repeated Start Condition
P: Stop Condition
Slave
Register
Address
WRITE
READ
W
Data Byte
Address
R: Read (1')
1
7
1
1
P
1
S
7
1
8
1
S
1
R
8
W: Write (0')
Slave
Register
Address
Slave
A
Data Byte
A
A
N
W
Address
Address
PEC: Packet Error Checking
*: Present if PEC is enabled
: Master to Slave
: Slave to Master
Figure 24: I2C Format
SMBUS/PMBUS™ PROTOCOLS
To access IR’s configuration and monitoring registers, 4 different protocols are required:
the SMBus Read/Write Byte/Word protocol with/without PEC (for status and monitoring)
the SMBus Send Byte protocol with/without PEC (for CLEAR_FAULTS only)
the SMBus Block Read protocol for accessing Model and Revision information
the SMBus Process call (for accessing Configuration Registers)
In addition, the IC supports:
Alert Response Address (ARA)
Bus timeout
Group Command for writing to many VRs within one command
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S: Start Condition
8
1
S
7
1
1
8
1
8
1
1
1
P
A: Acknowledge (0')
N: Not Acknowledge (1')
Sr: Repeated Start Condition
P: Stop Condition
Slave
Command
Code
A*
BYTE
A
A
Data Byte
A
PEC*
W
Address
1
S
1
R: Read (1')
7
1
8
8
1
Slave
Command
Code
Data Byte
Low
W: Write (0')
WORD
A
A
A
W
Address
…
PEC: Packet Error Checking
*: Present if PEC is enabled
: Master to Slave
1
8
1
1
P
8
Data Byte
High
A*
PEC*
A
: Slave to Master
Figure 25: SMBus Write Byte/Word
1
1
P
1
1
1
8
1
1
7
1
R
1
8
1
7
8
Slave
Command
Code
Slave
Data Byte
A*
A
A
A
PEC*
N
BYTE
S
W
Sr
Address
Address
1
S
7
1
1
8
1
1
7
1
R
1
8
1
Slave
Slave
Command
Code
Data Byte
A
A
Sr
A
A
WORD
W
Address
Low
Address
…
1
1
8
1
8
Data Byte
A*
PEC*
N
P
High
Figure 26: SMBus Read Byte/Word
1
S
7
1
1
8
1
8
1
1
P
Slave
Command
Code
PEC*
A
A*
A
W
Address
Figure 27: SMBus Send Byte
1
7
1
1
8
1
Slave
Command
Code
S
W
A
A
Address
…
1
7
1
R
1
8
8
8
1
1
1
1
Slave
Byte Count =1
Data Byte
A*
A
A
PEC*
N
P
Sr
Address
Figure 28: SMBus Block Read with Byte Count=1
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PMBus
Address
Command
D1h
Register
Address
Data Byte
PEC*
S
W
A
A
A
A
A
P
Figure 29: MFR specific command to Write an internal register
PMBus
Address
Command
D0h
Register
Address
S
W
A
A
A
...
PMBus
Address
Address+1
Data Byte
Data Byte
PEC*
Sr
R
A
A
A*
N
P
Figure 30: SMBus Custom Process Call to Read an internal register
1
S
7
1
1
8
1
8
1
8
1
8
1
Slave
Low
High
Command
A*
A
A
A
W
A
PEC1*
Address 1
Data Byte
Data Byte
Code 1
…
…
…
1 or more bytes
7
1
1
1
8
1
A
8
1
8
1
8
1
Low
Slave
High
Command
Code 2
A*
A
A
A
Sr
W
PEC2*
Data Byte
Address 2
Data Byte
…
1 or more bytes
1
7
1
1
1
8
1
8
1
8
1
8
1
Low
Slave
Command
Code n
High
A
A
A
P
Sr
W
A
A
PECn*
Data Byte
Address n
Data Byte
…
1 or more bytes
Figure 31: Group Command
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PCB PADS AND COMPONENT
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PCB COPPER AND SOLDER RESIST (PAD SIZES)
PCB COPPER AND SOLDER RESIST (PAD SPACING)
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SOLDER PASTE STENCIL (PAD SIZES)
SOLDER PASTE STENCIL (PAD SPACING)
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MARKING INFORMATION FOR FINAL PRODUCTION
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MARKING INFORMATION FOR EARLY PRODUCTION
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PACKAGE INFORMATION
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ENVIRONMENTAL QUALIFICATIONS
Industrial
Qualification Level
Moisture Sensitivity Level
Machine Model
5mm x 7mm PQFN
MSL 2 260C
JEDEC Class A
JEDEC Class 1C
JEDEC Class 3
(JESD22-A115A)
Human Body Model
(JESD22-A114F)
ESD
Charged Device Model
(JESD22-C101F)
RoHS Compliant
Yes (with Exemption 7a)
† Qualification standards can be found at International Rectifier web site: http://www.irf.com
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SUPPORTED PMBUS™ COMMANDS
Comma
nd
Code
SMBus
transactio
n
No. of
bytes
Resoluti Default
Command Name
Range
Description
on
Value
Enables or disables the device and controls
margining
01h
OPERATION
R/W Byte
1
Configures the combination of Enable pin input and
serial bus commands needed to turn the unit on and
off.
02h
03h
10h
ON_OFF_CONFIG
CLEAR_FAULTS
WRITE_PROTECT
R/W Byte
Send Byte
R/W Byte
1
0
1
Clear contents of Fault registers
Used to control writing to the PMBus™ device. The
intent of this command is to provide protection
against accidental changes.
15h
16h
STORE_USER_ALL
Send Byte
Send Byte
0
0
Burns the User section registers into OTP memory
Copies the OTP registers into User memory
RESTORE_USER_ALL
Returns 1011xxxx to indicate Packet Error Checking
is supported, maximum bus speed is 400kHz and
SMBAlert# is supported.
19h
CAPABILITY
Read Byte
1
Write
word/Block
read
Process
call
May be used to prevent a warning or fault condition
from asserting the SMBALERT# signal.
1Bh
SMBALERT_MASK
2
Causes the device to set its output voltage to the
commanded value.
VS= VOUT_SCALE_LOOP
0-
21h
22h
24h
VOUT_COMMAND16
VOUT_TRIM16
R/W Word
R/W Word
R/W Word
2
2
2
5mV/VS
1V
0V
2V
2.555V/VS
-128-
+128V
Available to the device user to trim the output voltage
Sets an upper limit on the output voltage the unit can
command regardless of any other commands or
combinations.
VOUT_MAX16
Sets the MARGIN high voltage when commanded by
OPERATION
VS= VOUT_SCALE_LOOP
Sets the MARGIN low voltage when commanded by
OPERATION
VL= VOUT_SCALE_LOOP
0-
25h
VOUT_MARGIN_HIGH16
VOUT_MARGIN_LOW16
R/W Word
R/W Word
2
5mV/VS
5mV/VS
2.555V/VS
0-
26h
27h
29h
33h
35h
2
2
2
2
2
2.555V/VS
0-
0.0625m 0.0625m Sets the rate in mV/μs at which the output should
VOUT_TRANSITION_RATE11 R/W Word
63.9mV/us V/us
V/us change voltage. Exponent 0 to -4 allowed.
1
Compensates for external resistor divider in feedback
path and in the sense path. Values 1, 0.5, 0.25,
0.125 allowed. Exponent -3 allowed.
Sets the switching frequency, in kHz. Exponent 0 to
1 allowed.
Sets the value of the input voltage, in volts, at which
the unit should start power conversion. Exponent -1
allowed.
VOUT_SCALE_LOOP11
FREQUENCY_SWITCH11
VIN_ON11
R/W Word
R/W Word
R/W Word
0.125-1
166-
1500kHz
978kHz
8V
0-16.5V
0-16V
0.5V
Sets the value of the input voltage, in volts, at which
36h
39h
40h
41h
VIN_OFF11
R/W Word
R/W Word
R/W Word
R/W Byte
2
2
2
1
0.5V
7.0V the unit, once operation has started, should stop
power conversion. Exponent -1 allowed.
-128A-
+127.5A
Used to null out any offsets in the output current
sensing circuit. Exponent -2 allowed.
Sets the value of the output voltage measured at the
IOUT_CAL_OFFSET11
VOUT_OV_FAULT_LIMIT16
0.25A
0A
(25-
655mV)/VS
10mV/VS 2.102V sense pin that causes an output overvoltage fault.
VS= VOUT_SCALE_LOOP
VOUT_OV_FAULT_RESPONS
E
Ignore/Shu
tdown
Shutdow Instructs the device on what action to take in
n
response to an output overvoltage fault.
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Comma
nd
Code
SMBus
transactio
n
No. of
bytes
Resoluti Default
Command Name
Range
Description
Sets the value of the output voltage at the
on
Value
42h
VOUT_OV_WARN_LIMIT16
R/W Word
2
3.9mV
1.902V sense pin that causes an output voltage high
warning.
Sets the value of the output voltage at the
Sense pin that causes an output voltage low warning.
Sets the value of the output voltage at the
sense pin that causes an output undervoltage fault.
Instructs the device on what action to
take in response to an output undervoltage fault.
43h
44h
45h
VOUT_UV_WARN_LIMIT16
VOUT_UV_FAULT_LIMIT16
R/W Word
R/W Word
R/W Byte
2
2
1
3.9mV
3.9mV
0.902V
0.898V
VOUT_UV_FAULT_RESPONS
E
Ignore/Shu
tdown
Ignore
Sets the value of the output current, in
40A,
46h
IOUT_OC_FAULT_LIMIT11
R/W Word
2
12-56A
4A
amperes, that causes the overcurrent detector to
20A
indicate an overcurrent fault. Exponent -1 allowed.
Pulse by
pulse for
8 cycles
followed
by
hiccup,
Instructs the device on what action to
take in response to an output overcurrent fault.
47h IOUT_OC_FAULT_RESPONSE R/W Byte
1
retry
after 20
ms
Sets the value of the output current, in
35A, amperes, that causes the overcurrent detector to
17.5A indicate an overcurrent warning. Exponent -1
allowed.
4Ah
IOUT_OC_WARN_LIMIT11
R/W Word
2
0-63.5A
0.5A
Set the temperature, in degrees Celsius, of the unit at
which it should indicate an Overtemperature Fault.
Exponent 0 allowed.
4Fh
50h
OT_FAULT_LIMIT11
R/W Word
R/W Byte
2
1
0-150°C
1°C
125°C
Ignore/Shu
tdown/Inhi
biit
Auto- Instructs the device on what action to take in
start response to an overtemperature fault.
OT_FAULT_RESPONSE
Set the temperature, in degrees Celsius, of the unit at
which it should indicate an Overtemperature Warning
alarm. Exponent 0 allowed.
Sets the value of the input voltage that causes an
input overvoltage fault. Exponent -2 allowed.
Instructs the device on what action to take
51h
55h
56h
OT_WARN_LIMIT11
R/W Word
R/W Word
2
2
1
0-150°C
1°C
100°C
VIN_OV_FAULT_LIMIT11
6.25V-24V 0.25V
15V
Ignore/Shu
tdown
VIN_OV_FAULT_RESPONSE R/W Byte
Ignore in response to an input overvoltage fault.
Sets the value of the input voltage PVin, in volts,
that causes an input overvoltage fault. Exponent -1
allowed.
58h
5Eh
5Fh
VIN_UV_WARN_LIMIT11
POWER_GOOD_ON16
POWER_GOOD_OFF16
R/W Word
R/W Word
R/W Word
2
2
2
0-16V
0.5V
7.5V
Sets the output voltage at which an optional
(0-
0.63V)/VS
10mV/VS
0.5V POWER_GOOD signal should be asserted.
VS=VOUT_SCALE_LOOP
Sets the output voltage at which an optional
10mV/VS 0.25V POWER_GOOD signal should be negated.
VS=VOUT_SCALE_LOOP
(0-
0.63V)/VS
Sets the time, in milliseconds, from when a start
condition is received (as programmed by the
ON_OFF_CONFIG command) until the output
voltage starts to rise. Exponent 0 allowed.
60h
61h
62h
TON_DELAY11
TON_RISE11
R/W Word
R/W Word
R/W Word
2
2
2
0-127ms
0-127ms
0-127ms
1ms
1ms
1ms
0ms
Sets the time, in milliseconds, from when the output
1ms starts to rise until the voltage has entered the
regulation band. Exponent 0 allowed.
Sets an upper limit, in milliseconds, on how long the
unit can attempt to power up the output without
reaching the output undervoltage fault limit.
Exponent 0 allowed.
0
TON_MAX_FAULT_LIMIT11
(Disable
d)
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Comma
nd
Code
SMBus
transactio
n
No. of
bytes
Resoluti Default
Command Name
Range
Description
on
Value
Instructs the device on what action to
take in response to a TON_MAX fault.
TON_MAX_FAULT_RESPONS
E
Ignore/Shu
tdown
63h
R/W Byte
1
Ignore
Sets the time, in milliseconds, from a stop condition
is received (as programmed by the
64h
TOFF_DELAY
TOFF_FALL
R/W Word
2
0-127ms
0-127ms
1ms
1ms
0ms ON_OFF_CONFIG command) until the unit stops
transferring energy to the output. Exponent 0
allowed.
Sets the time, in milliseconds, in which the reference
voltage ramps down to zero (If a soft off is allowed by
the configuration of the ON_OFF_CONFIG
65h
78h
R/W Word
Read Byte
2
1
1ms
command). Exponent 0 allowed.
Returns 1 byte where the bit meanings are:
Bit <7> device busy fault
Bit <6> output off (due to fault or enable)
Bit <5> Output over-voltage fault
Bit <4> Output over-current fault
Bit <3> Input Under-voltage fault
Bit <2> Temperature fault
STATUS BYTE
Bit <1> Communication/Memory/Logic fault
Bit <0>: None of the above
Returns 2 bytes where the Low byte is the same as
the STATUS_BYTE data. The High byte has bit
meanings are:
Bit <7> Output high or low fault
Bit <6> Output over-current fault
Bit <5> Input under-voltage fault
Bit <4> Reserved; hardcoded to 0
Bit <3> Output power not good
Bit <2:0> Hardcoded to 0
79h
STATUS WORD
Read Word
2
7Ah
7Bh
7Ch
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
Read Byte
Read Byte
Read Byte
1
1
1
Reports types of VOUT related faults.
Reports types of IOUT related faults.
Reports types of INPUT related faults.
Returns Over Temperature warning and Over
Temperature fault (OTP level). Does not report under
temperature warning/fault. The bit meanings are:
Bit <7> Over Temperature Fault
Bit <6> Over Temperature Warning
Bit <5> Under Temperature Warning
Bit <4> Under Temperature Fault
Bit <3:0> Reserved
7Dh
STATUS_TEMPERATURE
Read Byte
1
Returns 1 byte where the bit meanings are:
Bit <7> Command not Supported
Bit <6> Invalid data
Bit <5> PEC fault
7Eh
STATUS_CML
Read Byte
1
Bit <4> OTP fault
Bit <3:2> Reserved
Bit<1> Other communication fault
Bit<0> Other memory or logic fault; hardcoded to 0
61
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IR38163/363/165/365
Comma
nd
Code
SMBus
transactio
n
No. of
bytes
Resoluti Default
Command Name
Range
Description
on
Value
88h
8Bh
8Ch
8Dh
96h
READ_VIN11
READ_VOUT16
Read Word
Read Word
Read Word
Read Word
Read Word
2
2
2
2
2
Returns the input voltage in Volts
Returns the output voltage in Volts
READ_IOUT11
Returns the output current in Amperes
Returns the device temperature in degrees Celsius
Returns the output power in Watts
READ_TEMPERATURE11
READ_POUT11
Reports PMBus™ Part I rev 1.2 & PMBus™
Part II rev 1.2
98h
99h
PMBUS™_REVISION
Read Byte
1
2
Block
Read/Write
Returns 2 bytes used to read the manufacturer’s ID.
User can overwrite with any value.
MFR_ID
IR
If set to 0, returns a 1 byte code corresponding to
IC_DEVICE_ID.
Block
Read/Write
Set
000000
9Ah
9Bh
MFR_MODEL
3
3
Alternatively, user can set to any non-zero value
If set to 0, returns a 1 byte code corresponding to
IC_DEVICE_REV.
Block
Read/Write
Set
000000
MFR_REVISION
Alternatively, user can set to any non-zero value
Used to read the type or part number of an IC.
IR38163: 63h
ADh
IC_DEVICE_ID
Block Read
2
IR38165:64h
IR38363: 67h
IR38365: 68h
AEh
D0h
IC_DEVICE_REV
MFR_READ_REG
Block Read
Custom
1
2
Used to read the revision of the IC
Manufacturer Specific: Read from configuration
registers
Manufacturer Specific: Write to configuration & status
registers
D1h
D8h
MFR_WRITE_REG
MFR_TPGDLY
Custom
2
2
Sets the delay in ms, between the output voltage
0ms entering the regulation window and the assertion of
the PGood signal. Exponent 0 allowed.
R/W Word
0-10ms
1ms
Allows the user to choose between forced continuous
1 (CCM) conduction mode and adaptive on-time operation at
light load.
D9h
MFR_FCCM
R/W Byte
1
0-1
D6h
DBh
MFR_I2C_address
R/W Word
Read Word
1
2
0-7Fh
10h
Sets and returns the device I2C base address
Continuously records and reports the highest value of
Read Vout.
MFR_VOUT_PEAK16
Continuously records and reports the highest value of
Read Iout.
Continuously records and reports the highest value of
Read_Temperature
DCh
MFR_IOUT_PEAK11
Read Word
2
2
DDh MFR_TEMPERATURE_PEAK11 Read Word
Notes
11 Uses LINEAR11 format
16 Uses LINEAR16 format with exponent set to-8
62
Rev 3.6
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IR38163/363/165/365
Revision History
3.0
3.1
3.2
3/9/2017
3/20/2017
5/8/2017
Initial Release.
Changed 1.8V LDO regulation current to 1 mA, added a note on bootstrap circuit and
layout recommendations, stencil drawings updated
Added requirement of 1 ohm series resistor for PVin>14V
Fixed OCP description and diagram plus updated other functionality sections. Added
recommendation to use 10uF bypass capacitor at P1V8 pin. Updated the default values
on the PMBUS™ section. Updated application diagrams.
3.3
3.4
12/12/2017
9/12/2018
Updated packaging markings, added thermal de-rating curves, corrected PMBUS revision.
Updated diagrams to show SAlert# instead of SAlert. Remove the 5900 ppm/C OC set
parameter. This is an internal tempco parameter used in the OCP circuit that is misleading.
The OCP circuit is more complex and this one temp co does not represent the OCP
relationship across temperature.
3.5
3.6
4/1/2019
6/7/2019
Removed comments in the revision history that came before the initial release. Post Rev
3.0 comments.
63
Rev 3.6
Jun 7, 2019
IR38163/363/165/365
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
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(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information
regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any
kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the
product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s
technical departments to evaluate the suitability of the product for the intended application and the completeness of the
product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question please
contact your nearest Infineon Technologies office.
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or any consequences of the use thereof can reasonably be expected to result in personal injury.
64
Rev 3.6
Jun 7, 2019
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