IR3821AMPBF_08 [INFINEON]

HIGHLY INTEGRATED 9A WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR; 高度集成的9A宽电压输入，同步降压稳压器


型号：	IR3821AMPBF_08
厂家：	Infineon
描述：	HIGHLY INTEGRATED 9A WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR 高度集成的9A宽电压输入，同步降压稳压器稳压器输入元件
文件：	总21页 (文件大小：678K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PD-60332

IR3821AMPbF

SupIRBuck

HIGHLY INTEGRATED 9A

WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR

Features

Description

•

Wide Input Voltage Range 2.5V to 21V

Wide Output Voltage Range 0.6V to 12V

Continuous 9A Load Capability

300kHz High Frequency Operation

Programmable Over-Current Protection

Programmable PGood Output

Hiccup Current Limit

The IR3821A SupIRBuck^TMis an easy-to-use,

fully integrated and highly efficient DC/DC

regulator. The onboard switching controller and

MOSFETs make the IR3821A a space-efficient

solution, providing accurate power delivery for

low output voltage applications.

Precision Reference Voltage (0.6V)

Programmable Soft-Start

The IR3821A operates from a single 4.5V to 14V

input supply and generates an output voltage

adjustable from 0.6V to 0.8*Vin at loads up to 9A.

Pre-Bias Start-up

Thermal Protection

A versatile regulator offering programmability of

startup time, power good threshold and current

limit, the IR3821A’s fixed 300kHz switching

frequency allows the use of small external

components.

Thermally Enhanced Package

Small Size 5mmx6mm QFN

Pb-Free (RoHS Compliant)

Applications

•

Distributed Point-of-Loads

Server and Workstations

Embedded Systems

The IR3821A also features important protection

functions, such as Pre-Bias startup, hiccup

current limit and thermal shutdown to provide the

required system level security in the event of fault

conditions.

Storage Systems

DDR Applications

Graphics Cards

Game Consoles

Computing Peripheral Voltage Regulators

Fig. 1. Typical application diagram

01/08/08

PD-60332

IR3821AMPbF

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to GND)

•

V_INSupply Voltage

Vcc Supply Voltage

Vc Supply Voltage

-0.3V to 24V

-0.3V to 16V

-0.3V to 30V

PGood

-0.3V to 16V

Fb,COMP,SS,Vsns

OCSet

-0.3V to 3.5V

10mA

AGnd to PGnd

-0.3V to +0.3V

-65°C To 150°C

-40°C To 150°C

JEDEC, JESD22-A114

JEDEC Level 3 @ 260^oC

Storage Temperature Range

Operating Junction Temperature Range

ESD Classification

Moisture Sensitivity Level

Caution: Stresses beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the

device. These are stress ratings only and functional operation of the device at these or any other conditions beyond

those indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum

Rating” conditions for extended periods may affect device reliability.

PACKAGE INFORMATION

5mm x 6mm POWER QFN

V_IN

PGnd

θ_JA= 35^oC / W

θ_J-PCB= 2^oC / W

AGnd

PGood

V_CC

V_C

Vsns FB COMP AGnd AGnd SS OCSet

Fig. 2: Package outline (Top view)

ORDERING INFORMATION

PKG

PACKAGE

PARTS

DESIG

COUNT

PER TUBE

PER REEL

DESCRIPTION

IR3821AMTRPbF

---------------

4000

01/08/08

PD-60332

IR3821AMPbF

Block Diagram

Fig. 3. Simplified block diagram of the IR3821A.

01/08/08

PD-60332

IR3821AMPbF

Pin Description

Pin Name

Description

Vsns

PGood sense pin. Use two external resistors to program the power

good threshold.

Inverting input to the error amplifier. This pin is connected directly to the

output of the regulator via resistor divider to set the output voltage and

provide feedback to the error amplifier.

Comp

AGnd

Output of error amplifier.

Signal ground for internal reference and control circuitry.

SS/SD Soft start / shutdown. This pin provides user programmable soft-start

function. Connect an external capacitor from this pin to signal ground

(AGnd) to set the start up time of the output voltage. The converter can

be shutdown by pulling this pin below 0.3V.

OCSet Current limit set point. A resistor from this pin to SW pin will set the

current limit threshold.

V_CC

This pin provides biasing voltage for the internal blocks of the IC. It also

powers the low side driver. A minimum of 0.1uF, high frequency

capacitor must be connected from this pin to power ground (PGnd).

PGood Power Good status pin. Output is open collector. Connect a pull up

resistor from this pin to Vcc.

PGnd

Power Ground. This pin serves as a separated ground for the MOSFET

drivers and should be connected to the system’s power ground plane.

V_IN

Switch node. This pin is connected to the output inductor

Input voltage connection pin

V_C

This pin is connected to the high side Mosfet gate. Connect a small

capacitor from this pin to switch node (SW).

This pin powers the high side driver and must be connected to a voltage

higher than input voltage. A minimum of 0.1uF high frequency capacitor

must be connected from this pin to the power ground (PGnd).

Signal ground for internal reference and control circuitry.

AGnd

Pins 4, 5 and 15 need to be connected together on system board.

01/08/08

PD-60332

IR3821AMPbF

Recommended Operating Conditions

Symbol

Definition

Min

Max

Units

V_in

V_cc

V_c

V_o

I_oNote1

T_j

Input Voltage

2.5

4.5

Vin + 5V

0.6

Supply Voltage

Output Voltage

Output Current

-40

Junction Temperature

125

^oC

Electrical Specifications

Unless otherwise specified, these specification apply over Vin=V_cc=V_c=12V, 0^oC<T_j(Ic)<105^oC.

Typical values are specified at T_a= 25^oC.

Parameter

Power Loss

Symbol

Test Condition

Min

TYP

MAX

Units

Power Loss

P_loss

Vcc=V_in=12V, Vc=24V, V_o=1.8V,

2.3

I_o=9A, L=1.2uH, Note3

MOSFET R_ds(on)

Top Switch

R_{ds(on)_Top}

R_{ds(on)_Bot}

I_D=11A, Tj(MOSFET)=25^oC

10.5

13.4

mΩ

Bottom Switch

Reference Voltage

Feedback Voltage

V_FB

0.6

Accuracy

0^oC<Tj<105^oC

-1.35

-1.5

+1.35

+1.5

-40^oC<Tj<105^oC, Note2

Supply Current

V_CCSupply Current (Static)

I_CC(Static)

I_C(Static)

I_CC(Dynamic)

I_C(Dynamic)

SS=0V, No Switching

4.5

V_CSupply Current

(Static)

V_CCSupply Current

(Dynamic)

V_CSupply Current

(Dynamic)

SS=3V, V_c=24V, V_cc=V_in=12V.

V_o=1.8V, Io=0A

SS=3V, V_c=24V, V_cc=V_in=12V.

V_o=1.8V, Io=0A

Under Voltage Lockout

V_CC-Start-Threshold

V_CC_UVLO(R)

V_CC_UVLO(F)

Supply ramping up

4.0

3.7

4.4

4.1

V_CC-Stop-Threshold

V_CC-Hysteresis

Supply ramping down

Supply ramping up and down

Supply ramping up

0.15

3.1

0.25

0.2

0.3

V_C-Start-Threshold

V_C-Stop-Threshold

V_C-Hysteresis

V_C_UVLO(R)

V_C_UVLO(F)

3.5

Supply ramping down

Supply ramping up and down

2.85

0.15

3.25

0.25

01/08/08

PD-60332

IR3821AMPbF

Parameter

SYM

Test Condition

Min

TYP

MAX

Units

Oscillator

Frequency

F_S

270

300

1.25

330

kHz

Note3

Fb=0V

Ramp Amplitude

Min Pulse Width

Max Duty Cycle

V_ramp

D_min(ctrl)

D_max

Error Amplifier

Input Bias Current

I_FB1

I_FB2

SS=3V

SS=0V

-0.1

-0.5

Input Bias Current

Source/Sink Current

Transconductance

μA

I(source/Sink)

1000

1300

1600

μmho

Soft Start/SD

Soft Start Current

I_SS

SS=0V

μA

Shutdown Output

Threshold

0.25

Power Good

Vsns Low Trip Point

Vsns(trip)

PGood(Hys)

PG(voltage)

Isns

Vsns Ramping Down

I_PGood=4mA

0.35

0.38

27.5

0.25

0.3

0.41

Hysteresis

PGood Output Low

Voltage

0.5

Input Bias Current

μA

Over Current Protection

OCSET Current

Hiccup Current

I_OCSET

I_Hiccup

μA

Note3

Hiccup Duty Cycle

Hiccup(duty)

_Hiccup/ I_SS, Note3

Thermal Shutdown

Threshold

140

Note3

^oC

Thermal Shutdown

Hysteresis

Note1: Continuous output current determined by input and output voltage setting and thermal environment.

Note2: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.

Note3: Guaranteed by Design but not tested in production.

01/08/08

PD-60332

IR3821AMPbF

TYPICAL OPERATING CHARACTERISTICS (-40^oC - 125^oC)

Ic(static)

Icc(static)

7.0

6.0

5.0

4.0

3.0

2.0

13.0

12.0

11.0

10.0

9.0

8.0

7.0

-40

-20

100

120

-40

-20

100

120

Temp[oC]

Icc(dynamic)

Ic(dynamic)

21.0

19.0

17.0

15.0

13.0

11.0

21.0

19.0

17.0

15.0

13.0

11.0

-40

-20

100

120

-40

-20

100

120

Temp[oC]

ISS

Vfb

27.0

25.0

23.0

21.0

19.0

17.0

15.0

605.0

600.0

595.0

590.0

585.0

-40

-20

100

120

-40

-20

100

120

Temp[oC]

Transconductance

IOCSET

1.60

1.55

1.50

1.45

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.05

1.00

26.0

25.0

24.0

23.0

22.0

21.0

20.0

19.0

18.0

17.0

16.0

15.0

-40

-20

100

120

-40

-20

100

120

Temp[oC]

01/08/08

PD-60332

IR3821AMPbF

Circuit Description

THEORY OF OPERATION

The IR3821A is

voltage mode PWM

Pre-Bias Startup

synchronous regulator and operates with a fixed

300kHz switching frequency, allowing the use of

small external components.

The IR3821A is able to start up into pre-charged

output, which prevents oscillation and

disturbances of the output voltage.

The output voltage is set by feedback pin (Fb)

and the internal reference voltage (0.6V). These

are two inputs to error amplifier. The error signal

between these two inputs is amplified and it is

compared to a fixed frequency linear sawtooth

ramp.

The output starts in asynchronous fashion and

keeps the synchronous MOSFET off until the first

gate signal for control MOSFET is generated.

Figure 4 shows a typical Pre-Bias condition at

start up.

Depending on system configuration, a specific

amount of output capacitors may be required to

prevent discharging the output voltage.

A trailing edge modulation is used for generating

fixed frequency pulses (PWM) which drives the

internal N-channel MOSFETs.

The internal oscillator circuit uses on-chip

circuitry, eliminating the need for external

components.

The IR3821A operates with single input voltage

from 4.5V to 14V allowing an extended operating

input voltage range.

Pre-Bias Voltage

The over-current protection is performed by

sensing current through the R_DS(on)of low side

MOSFET. This method enhances the converter’s

efficiency and reduces cost by eliminating a

current sense resistor. The current limit is

programmable by using an external resistor.

Time

Fig. 4: Pre-Bias start up

Under-Voltage Lockout

The under-voltage lockout circuit monitors the

two input supplies (Vcc and Vc) and assures that

the MOSFET driver outputs remain in the off

state whenever the supply voltage drops below

set thresholds. Lockout occurs if Vcc or Vc fall

below 4.3V and 3.3V respectively. Normal

operation resumes once Vcc and Vc rise above

the set values.

Shutdown

The output can be shutdown by pulling the soft-

start pin below 0.3V. This can easily be done by

using an external small signal transistor. During

shutdown both MOSFET drivers will be turned

off. Normal operation will resume by cycling soft

start pin.

Power Good

Thermal Shutdown

The IR3821A provides an open collector power

good signal which reports the status of the

output. The output is sensed through the

dedicated Vsns pin. The power good threshold

can be externally programmed using two external

resistors. The power good comparator is

internally set to 0.38V (typical).

Temperature sensing is provided inside the

IR3821A. The trip threshold is typically set to

140^oC. When trip threshold is exceeded, thermal

shutdown turns off both MOSFETs. Thermal

shutdown is not latched and automatic restart is

initiated when the sensed temperature drops

within the operating range. There is a 20^oC

hysteresis in the thermal shutdown threshold.

01/08/08

PD-60332

IR3821AMPbF

Soft-Start

The IR3821A has programmable soft-start to

control the output voltage rise and limit the inrush

current during start-up.

20uA

SS/SD

Comp

To ensure correct start-up, the soft-start

sequence initiates when Vcc and Vc rise above

their threshold and generate the Power On

Ready (POR) signal. The soft-start function

operates by sourcing current to charge an

external capacitor to about 3V.

40uA

POR

Error Amp

24K

0.6V

Initially, the soft-start function clamps the output

of error amplifier by injecting a current (40uA)

into the Fb pin and generates a voltage about

0.96V (40ux24K) across the negative input of

error amplifier (see figure 5).

24K

The magnitude of the injected current is inversely

proportional to the voltage at the soft-start pin. As

the soft-start voltage ramps up, the injected

current decreases linearly and so does the

voltage at negative input of error amplifier.

Fig. 5: Soft-Start circuit for IR3821A

When the soft-start capacitor is around 1V, the

voltage at the positive input of the error amplifier

is approximately 0.6V.

Output of UVLO

POR

The output of error amplifier will start increasing

and generating the first PWM signal. As the soft-

start capacitor voltage continues to rise up, the

current flowing into the Fb pin will keep

decreasing.

≅2V

≅1V

Soft-Start

Voltage

The feedback voltage increases linearly as the

soft start voltage ramps up. When soft-start

voltage is around 2V, the output voltage reaches

the steady state and the injected current is zero.

40uA

Current flowing

into Fb pin

0uA

0.96V

Voltage at negative input ^≅

of Error Amp

Figure

shows the theoretical operating

waveforms during soft-start.

0.6V

The output voltage start-up time is the time

period when soft-start capacitor voltage

increases from 1V to 2V.

Voltage at Fb pin

The start-up time will be dependent on the size of

the external soft-start capacitor and can be

estimated by:

Fig. 6: Theoretical operation waveforms

during soft-start

start

20μA∗

= 2V −1V

C_ss

For a given start-up time, the soft-start capacitor

can be estimated as:

C_SS≅ 20μA*T (ms)

--(1)

start

01/08/08

PD-60332

IR3821AMPbF

Over-Current Protection

The over-current protection is performed by

sensing current through the R_DS(on)of the low

side MOSFET. This method enhances the

converter’s efficiency and reduces cost by

eliminating a current sense resistor. As shown in

figure 7, an external resistor (R_SET) is connected

between OCSet pin and the inductor point which

sets the current limit set point.

The internal current source develops a voltage

across R_SET. When the low side MOSFET is

turned on, the inductor current flows through the

Q2 and results a voltage which is given by:

Fig. 8: 3uA current source for discharging

soft-start capacitor during hiccup

The OCP circuit starts sampling current when the

low gate drive is about 3V. The OCSet pin is

internally clamped about 1.5V during on time of

high side gate to prevent false trigging, figure 9

shows the OCSet pin during one switching cycle.

As shown, there is about 150ns delay to mask

the dead time. Since this node contains switching

noises, this delay also functions as a filter.

V_OCSet= (I_OCSet∗ R_OCSet) − (R_DS(on)∗I_L)

--( 2)

Deadtime

Blanking time

I_OCSet*R_OCSet

Clamp voltage

Fig. 7: Connection of over current sensing resistor

The critical inductor current can be calculated by

setting:

_OCSet= (I_OCSet∗R_OCSet)−(R_DS(on)∗I_L) = 0

Fig. 9: OCset pin during normal condition

Ch1: Inductor point, Ch3:OCSet

R_OCSet∗ I_OCSet

I_SET= I_{L(critical )}

--( 3 )

R_{DS (on )}

The value of R_SETshould be checked in an actual

circuit to ensure that the over-current protection

circuit activates as expected. The IR3821A

current limit is designed primarily as disaster

preventing, and doesn't operate as a precision

current regulator.

An over-current is detected if the OCSet pin goes

below ground. This trips the OCP comparator

and cycles the soft start function in hiccup mode.

The hiccup is performed by charging and

discharging the soft-start capacitor in a certain

slope rate. As shown in figure 8 a 3uA current

source is used to discharge the soft-start

capacitor.

The OCP comparator resets after every soft start

cycle. The converter stays in this mode until the

overload or short circuit is removed. The

converter will automatically recover.

01/08/08

PD-60332

IR3821AMPbF

Soft-Start Programming

Application Information

Design Example:

The following example is a typical application for

the IR3821A. The application circuit is shown in

page 17.

The soft-start timing can be programmed by

selecting the soft-start capacitance value. The

start-up time of the converter can be calculated

by using:

C_SS≅ 20μA*T

--(1)

start

Where T_startis the desired start-up time (ms)

For a start-up time of 11ms, the soft-start

capacitor will be 0.22uF.

V_in=12V,(13.2V,max )

V_o=1.8V

I_o= 9A

Vc supply for single input voltage

ΔV_o≤ 30mV

F_s= 300 kHz

To drive the high-side switch, it is necessary to

supply a gate voltage at least 4V greater than the

bus voltage. This is achieved by using a charge

pump configuration as shown in figure 11. This

method is simple and inexpensive. The operation

of the circuit is as follows: when the lower

MOSFET is turned on, the capacitor (C1) is

pulled down to ground and charges, up to V_BUS

value, through the diode (D1). The bus voltage

will be added to this voltage when upper

MOSFET turns on in next cycle, and providing

supply voltage (Vc) through diode (D2). Vc is

approximately:

Output Voltage Programming

Output voltage is programmed by reference

voltage and external voltage divider. The Fb pin

is the inverting input of the error amplifier, which

is internally referenced to 0.6V. The divider is

ratioed to provide 0.6V at the Fb pin when the

output is at its desired value. The output voltage

is defined by using the following equation:

⎛

⎞

R₈

R₉

V ≅ 2∗V

−

(

V_D1+V_D2

)

--(6)

⎜

⎟

V_o=V_ref∗ 1 +

--(4)

bus

⎜

⎝

⎠

Capacitors in the range of 0.1uF are generally

adequate for most applications. The diodes must

be a fast recovery device to minimize the amount

of charge fed back from the charge pump

capacitor into V_BUS. The diodes need to be able

to block the full power rail voltage, which is seen

when the high side MOSFET is switched on. For

low voltage application, schottky diodes can be

used to minimize forward drop across the diodes

at start up.

When an external resistor divider is connected to

the output as shown in figure 10.

VOUT

IR3624

IR3821A

Fig. 10: Typical application of the IR3821A for

programming the output voltage

Equation (4) can be rewritten as:

⎛

⎞

V_ref

⎜

⎟

R₉= R₈∗

--(5)

V_O−V_ref

⎝

⎠

For the calculated values of R₈and R₉see

feedback compensation section.

Fig. 11: Charge pump circuit to generate

Vc voltage

01/08/08

PD-60332

IR3821AMPbF

Input Capacitor Selection

IfΔi ≈ 47%(I_o,)then the output inductor will be:

L = 1.2uH

The input filter capacitor should be selected

based on how much ripple the supply can

tolerate on the DC input line. The ripple current

generated during the on time of upper MOSFET

should be provided by the input capacitor. The

RMS value of this ripple is expressed by:

Delta MPL-104 series provides a range of

inductors in different values, low profile suitable

for large currents.

Output Capacitor Selection

I_RMS= I_o∗ D∗(1−D) --(7)

The voltage ripple and transient requirements

determine the output capacitors’ type and values.

The criteria is normally based on the value of the

Effective Series Resistance (ESR). However the

actual capacitance value and the Equivalent

Series Inductance (ESL) are other contributing

components. These components can be

described as:

V_o

D =

Where:

D is the Duty Cycle

I_RMSis the RMS value of the input capacitor

current.

Io is the output current.

For Io=9A and D=0.15, the I_RMS=3.21A.

ΔV = ΔV_o(ESR)+ ΔV_o(ESL)+ ΔV

o(C)

Ceramic capacitors are recommended due to

their peak current capabilities. They also feature

low ESR and ESL at higher frequency which

results in better efficiency.

ΔV

= ΔI_L*ESR - -(9)

o(ESR)

Use 3x10uF, 16V ceramic capacitors from

Panasonic.

⎛

⎜

⎞

⎟

ΔV

*ESL

o(ESL)

⎝

⎠

Inductor Selection

ΔI_L

8 *C_o*F

ΔV

o(C)

The inductor is selected based on output power,

operating frequency and efficiency requirements.

A low inductor value causes a large ripple

current, resulting in the smaller size, faster

response to a load transient but poor efficiency

and high output noise. Generally, the selection of

the inductor value can be reduced to the desired

ΔV =Output voltage ripple

ΔI_L= Inductor ripple current

Since the output capacitor has a major role in the

overall performance of the converter and

determine the result of transient response,

selection of the capacitor is critical. The IR3821A

can perform well with all types of capacitors.

(Δi)

maximum ripple current in the inductor

. The

optimum point is usually found between 20% and

50% ripple of the output current.

For the buck converter, the inductor value for the

desired operating ripple current can be

determined using the following:

As a rule the capacitor must have low enough

ESR to meet output ripple and load transient

requirements, yet have high enough ESR to

satisfy stability requirements.

Δi

Δt

V −V = L∗ ; Δt = D∗

The goal for this design is to meet the voltage

ripple requirement in the smallest possible

capacitor size. Therefore, a ceramic capacitor is

selected due to its low ESR and small size. Six of

the Panasonic ECJ2FB0J226M (22uF, 6.3V, X5R

and EIA 0805 case size) are a good choice.

L =

(

V −V

)

∗

--(8)

V ∗Δi *F

Where:

V = Maximum input voltage

V_o= Output Voltage

Δi = Inductor ripple current

F_s= Switching frequency

Δt = Turn on time

In the case of tantalum or low ESR electrolytic

capacitors, the ESR dominates the output

voltage ripple, equation (9) can be used to

calculate the required ESR for the specific

voltage ripple.

D = Duty cycle

01/08/08

PD-60332

IR3821AMPbF

Feedback Compensation

The ESR zero of the output capacitor expressed

as follows:

The IR3821A is a voltage mode controller; the

control loop is a single voltage feedback path

including error amplifier and error comparator. To

achieve fast transient response and accurate

output regulation, a compensation circuit is

necessary. The goal of the compensation

network is to provide a closed loop transfer

function with the highest 0dB crossing frequency

and adequate phase margin (greater than 45^o).

- - -(12)

ESR

2∗π *ESR*C_o

VOUT

Comp

E/A

CPOLE

VREF

The output LC filter introduces a double pole, –

40dB/decade gain slope above its corner

resonant frequency, and a total phase lag of 180^o

(see figure 13). The resonant frequency of the LC

filter expressed as follows:

Gain(dB)

H(s) dB

Frequency

F =

- - -(11)

2 π L C_o

Fig. 14: TypeII compensation network

and its asymptotic gain plot

Figure 13 shows gain and phase of the LC filter.

Since we already have 180^ophase shift from the

output filter alone, the system risks being

unstable.

The transfer function (Ve/Vo) is given by:

Gain

Phase

R₉

1+sRC₄

H(s)= g_m*

- - -(13)

R₉+R₈

0ꢀ

0dB

-40dB/decade

The (s) indicates that the transfer function varies

as a function of frequency. This configuration

introduces a gain and zero, expressed by:

-180

ꢀ

Frequency

FLC

LC Frequency

⎛

⎞

R₉

⎜

⎟

[

(

)

]

= g_m*

* R₃- - -(14)

⎜

⎝

R₉+R₈

⎠

Fig. 13: Gain and Phase of LC filter

F =

- - -(15)

2π *R₃*C₄

The IR3821A’s error amplifier is a differential-

input transconductance amplifier. The output is

available for DC gain control or AC phase

compensation.

The gain is determined by the voltage divider and

error amplifier’s transconductance gain.

First select the desired zero-crossover frequency

(Fo):

The error amplifier can be compensated either in

type II or typeIII compensation. When it is used in

type II compensation the transconductance

properties of the error amplifier become evident

and can be used to cancel one of the output filter

poles. This will be accomplished with a series RC

circuit from Comp pin to ground as shown in

figure 14.

F > F_ESRandF ≤

(

1/5~1/10 *F

)

Use the following equation to calculate R4:

V * F * F_ESR* (R₈+R₉)

osc

R₃=

- - -(16)

V * F²* R₉* g_m

Where:

V_in= Maximum Input Voltage

_osc= Oscillator Ramp Voltage

F_o= Crossover Frequency

_ESR= Zero Frequency of the Output Capacitor

_LC= Resonant Frequency of the Output Filter

This method requires that the output capacitor

should have enough ESR to satisfy stability

requirements. In general the output capacitor’s

ESR generates a zero typically at 5kHz to 50kHz

which is essential for an acceptable phase

margin.

R₈and R₉= Feedback Resistor Dividers

g_m= Error Amplifier Transconductance

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IR3821AMPbF

To cancel one of the LC filter poles, place the

zero before the LC filter resonant frequency pole:

VOUT

ZIN

F =75%F

F = 0.75*

- - -(17)

R10

2π L *C_o

Use equations (15) and (16) to calculate C4.

One more capacitor is sometimes added in

parallel with C4 and R3. This introduces one

more pole which is mainly used to suppress the

switching noise.

E/A

Comp

VREF

Gain(dB)

The additional pole is given by:

H(s) dB

F =

C₄*C_POLE

2π *R₃*

C₄+C_POLE

Frequency

FP3

The pole sets to one half of switching frequency

which results in the capacitor C_POLE

Fig.15: Compensation network with local

feedback and its asymptotic gain plot

C_POLE

≅

π * R₃* F

π * R₃* F −

As known, a transconductance amplifier has high

impedance (current source) output, therefore,

consideration should be taken when loading the

error amplifier output. It may exceed its

source/sink output current capability, so that the

amplifier will not be able to swing its output

voltage over the necessary range.

C₄

For F_P<<

For a general solution for unconditional stability

for any type of output capacitors, in a wide range

of ESR values we should implement local

feedback with a compensation network (type III).

The typically used compensation network for

voltage-mode controller is shown in figure 15.

The compensation network has three poles and

two zeros and they are expressed as follows:

In such a configuration, the transfer function is

F_P1= 0

given by:

V_e1 − g_mZ_f

V_o1 + g_mZ_IN

F_P2

F_P3

2π * R₁₀*C₇

≅

⎛

⎞

2π * R₃*C₃

C₄*C₃

C₄+ C₃

The error amplifier gain is independent of the

transconductance under the following condition:

⎜

⎟

2π * R₃

⎝

⎠

F_z1=

g_m* Z_f>>1 and g_m* Z_in>>1 - - - (18)

2π * R₃*C₄

By replacing Z_inand Z_faccording to figure 15, the

transformer function can be expressed as:

F_z2

≅

2π *C₇* (R₈+ R₁₀) 2π *C₇* R₈

(1 + sR₃C₄) *

[

1 + sC₇

(

R₈+ R₁₀

)

]

Cross over frequency is expressed as:

H(s) =

sR₈(C₄+ C₃)

⎡

⎤

⎥

⎦

⎛

⎞

C₄*C₃

C₄+ C₃

⎜

⎟

1 + sR

* (1 + sR C )

⎢

F = R₃*C *

⎝

⎠

⎣

2π *L *C_o

osc

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PD-60332

IR3821AMPbF

The DC gain will be large enough to provide high

DC-regulation accuracy (typically -5dB to -12dB).

The phase margin should be greater than 45^ofor

overall stability.

Based on the frequency of the zero generated by

output capacitor and its ESR versus crossover

frequency, the compensation type can be

different. The table below shows the

compensation types and location of crossover

frequency.

Θ_max=70^o

Desired Phase Boost:

Compensator

type

Output

capacitor

F_ESRvs. F_o

1-SinΘ

1+SinΘ

=10.58kHz

= F *

Type II(PI)

Electrolytic

, Tantalum

F_LC<F_ESR<F_o<F_s/2

F_LC<F_o<F_ESR<F_s/2

Type III(PID)

Tantalum,

ceramic

Method A

1+SinΘ

1-SinΘ

= 340.28kHz

= F *

Type III(PID)

Ceramic

F_LC<F_o<F_s/2<F_ESR

Method B

Table1- The compensation type and location

of F_ESRversus F_o

Select: F = 0.5* F and F_P3= 0.5* F

Select:C =180pF

The details of these compensation types are

discussed in application note AN-1043 which can

be downloaded from IR’s website at www.irf.com.

2π * F * L_o*C_o*V

R₃=

^OSC, R₃=18.85KΩ, checkR₃≥

C *V

g_m

For this design we have:

Select:R₃=18.70KΩ

CalculateC₄andC₃:

V_in=12V

V_o=1.8V

V_osc=1.25V

V_ref=0.6V

g_m=1000umoh

L_o=1.2uH

C_o=6x22uF, ESR=0.5mOhm

F_s=300kHz

C₄=

;C₄=1.61nF, Select: C₄=1.8nF

2π * F * R

C₃=

;C₃= 56.7pF, Select:C₃= 47pF

These result to:

2π * F * R₃

F_LC=17.12kHz

_ESR=4.4MHz

_s/2=300kHz

CalculateR ,R₈andR₉:

Select crossover frequency:

R =

;R = 2.60KΩ, checkR ≥

2π *C * F

g_m

F < F_ESRandF ≤

(

1/5~1/10 *F

)

Select:R = 2.61KΩ

Fo=60kHz

Since: F_LC<F_o<F_s/2<F_ESR, typeIII method B is

selected to place the poles and zeros.

R₈=

R₉=

R ;R₈= 80.97KΩ, Select: R₈= 80.6KΩ

2π *C * F

The following design rules will give a crossover

frequency approximately one-tenth of the

switching frequency. The higher the band width,

the potentially faster the load transient response.

ref

* R₈;R₉= 40.30KΩ, Select:R₉= 40.2KΩ

ref

01/08/08

PD-60332

IR3821AMPbF

Layout Consideration

Programming the Current-Limit

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to

perform with less than expected results.

The Current-Limit threshold can be set by

connecting a resistor (R_SET) from drain of the

low-side MOSFET to the OCSet pin. The

resistor can be calculated by using equation (3).

Start to place the power components, making all

the connection in the top layer with wide, copper

filled areas.

The R_DS(on)has

positive temperature

coefficient and it should be considered for the

worse case operation. This resistor must be

placed close to the IC, place a small ceramic

capacitor from this pin to power ground (PGnd)

for noise rejection purposes.

The inductor, output capacitor and the IR3821A

should be as close to each other as possible.

This helps to reduce the EMI radiated by the

power traces due to the high switching currents

through them. Place the input capacitor directly to

the Vin pin of IR3821A. To reduce the ESR

replace the single input capacitor with two

parallel units.

The feedback part of the system should be kept

away from the inductor and other noise sources.

The critical bypass components such as

capacitors for Vcc and Vc should be close to their

respective pins. It is important to place the

feedback components including feedback

resistors and compensation components close to

Fb and Comp pins.

R_OCSet∗I_OCSet

I_SET=I_L(critica)l

- -(3)

R_DS(on)

R_DS(on)=10.5mΩ ∗υ =10.5mΩ ∗1.5 =15.75mΩ

where:

υ :Temperature Dependency

Note :Use14.5 mΩ for low - side MOSFET

if 5V is used for V

Δi

I_SET= (I_o∗1.5) +

where:

I_o: MaxOutputCurrent

In a multilayer PCB use one layer as a power

ground plane and have a control circuit ground

(analog ground), to which all signals are

referenced. The goal is to localize the high

current path to a separate loop that does not

interfere with the more sensitive analog control

function. These two grounds must be connected

together on the PC board layout at a single point.

The Power QFN is a thermally enhanced

package. Based on thermal performance it is

recommended to use at least a 4-layers PCB. To

effectively remove heat from the device the

exposed pad should be connected to the ground

plane using vias.

Δi : Inductor ripplecurrent

Δi = (V -V_o)∗

V ∗L∗F

I_SET= (9A∗1.5)+ 2.1A=15.6A

R_OCSet= R₇=12.4KΩ

Setting the Power Good Threshold

Power Good threshold can be programmed by

using two external resistors (see figure 16).

The following formula can be used to set the

threshold:

0.38V

R₂=

--(19)

0.9*V -0.38V

out

Where:

0.38V is reference of the internal comparator

0.9*Vout is selectable threshold for power good,

for this design it is 1.62V.

Select R₁=10KOhm

Using (18): R₂=3.06KOhm

Select R₂=3.09K

Use a pull up resistor (4.99K) from PGood pin to

Vcc.

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IR3821AMPbF

Typical Application for IR3821A

12V to 1.8V @ 9A

Fig.16: Typical Application circuit for 12V to 1.8V at 9A using ceramic output capacitors

01/08/08

PD-60332

IR3821AMPbF

PCB Metal and Components Placement

The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The

minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting.

Lead land length should be equal to the maximum part lead length + 0.3 mm outboard

extension. The outboard extension ensures a large and inspectable toe fillet.

The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal

to maximum part pad length and width. However, the minimum metal-to-metal spacing

should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper

and no less than 0.23mm for 3 oz. Copper.

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IR3821AMPbF

Solder Resist

It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder

resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure

NSMD pads.

The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder

resist onto the copper of 0.05mm to accommodate solder resist mis-alignment.

Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to

the high aspect ratio of the solder resist strip separating the lead lands from the pad land.

01/08/08

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IR3821AMPbF

Stencil Design

•

The Stencil apertures for the lead lands should be approximately 80% of the area of

the lead lads. Reducing the amount of solder deposited will minimize the

occurrences of lead shorts. If too much solder is deposited on the center pad the part

will float and the lead lands will be open.

•

The maximum length and width of the land pad stencil aperture should be equal to

the solder resist opening minus an annular 0.2mm pull back to decrease the

incidence of shorting the center land to the lead lands when the part is pushed into

the solder paste.

01/08/08

PD-60332

IR3821AMPbF

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

This product has been designed and qualified for the Consumer market.

Visit us at www.irf.com for sales contact information

Data and specifications subject to change without notice. 10/07

01/08/08

IR3821AMPBF_08 [INFINEON]

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