IR3720MTRPBF [INFINEON]
Power Supply Support Circuit, Fixed, 1 Channel, 3 X 3 MM, ROHS COMPLIANT, DFN-10;
| 型号： | IR3720MTRPBF |
| 厂家： | 
Infineon |
| 描述： | Power Supply Support Circuit, Fixed, 1 Channel, 3 X 3 MM, ROHS COMPLIANT, DFN-10 光电二极管 |
| 文件： | 总20页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR3720
DATA SHEET
Power Monitor IC with
Digital I2C Interface
FEATURES
DESCRIPTION
Accurate TruePower™ monitor
The IR3720 measures the output voltage and inductor
current of low-voltage DC-to-DC converters and reports
the average power over a user specified time interval as
a digital word on the I2C. The output current is
measured across a current sensing resistor or indirectly
across the inductor’s DCR winding resistance.
Additionally, the current measurement method is also
applicable to multiphase converters.
•
•
Minimizes dynamic errors
Reports voltage, current, or power
Digital interface
•
SMBus and I2C compatible
Programmable averaging interval
Flexible current sensing
•
Resistive or Inductor DCR
Applications
The real time voltage and current signals are multiplied,
digitized, and averaged over a user selectable
averaging interval providing Patent Pending
•
•
Synchronous rectified buck converters
Multiphase converters
10pin 3x3 DFN lead free package
RoHS compliant
TruePower™ measurement of highly dynamic loads.
TYPICAL APPLICATION CIRCUIT
3.3V
DCR
Phase
L
Output
Capacitors
VO VDD
LOAD
Rcs1
Rcs2
To system
Controller
Single
Phase
Converter
CCS1
CCS2
IR3720
I2C Bus
2
VREF
VCS
RT
GND
Power
Return
GND
ORDERING INFORMATION
Device
IR3720MTRPBF
* IR3720MPBF
Package
10 lead DFN (3x3 mm body)
10 lead DFN (3x3 mm body)
Order Quantity
3000 piece reel
121 Piece tube
* Samples only
Page 1 of 20
www.irf.com
09/09/08
IR3720
DATA SHEET
ABSOLUTE MAXIMUM RATINGS
All voltages referenced to GND
VDD: ................................................................3.9V
ALERT#:...........................................................3.9V
ALERT#..............................................<VDD + 0.3V
EXTCLK ...........................................................3.9V
All other Analog and Digital pins......................3.9V
Operating Junction Temperature.... -10°C to 150oC
Storage Temperature Range.......... -65oC to 150oC
Thermal Impedance (θJC)............................53°C/W
ESD Rating ............HBM Class 2 JEDEC Standard
MSL Rating ..................................................Level 2
Reflow Temperature ..................................... 260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply: VDD = 3.3V ± 5%, 0oC ≤ TJ ≤ 125oC, 0.5 ≤ VO ≤ 1.8 V, and
operation in the system accuracy test circuit. See notes following table.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
IC SYSTEM ACCURACY
Power accuracy,
IC only
RCS2 = 600 Ω, RT = 25.5 kΩ, VDCR = 20 mV,
VO=1 volt, CCS2 = 1μF
3.3
%
Sampling frequency 512 kHz.
Sampling interval 8 ms, 0OC ≤ TJ ≤ 85OC
Notes 1, 2
BIAS SUPPLY
VDD Turn-on Threshold, VDDUP
VDD Turn-off Threshold, VDDDN
VDD Operating Current
VDD Shutdown Current
VOLTAGE REFERENCE
VREF Voltage
3.1
V
V
2.4
RT = 25.5 kΩ
480
17
660
100
μA
μA
Config Reg enable bit d4=1
RT = 25.5 kΩ
1.4
1.5
1.6
40
V
Reference load, RT
Note 1
20
25.5
kꢀ
VOLTAGE SENSOR
Voltage error
VO=1V; VDCR=0 mV, 0OC ≤ TJ ≤ 85OC
-0.75
0.75
%
V
R
CS2=600 ꢀ, RT=25.5 kꢀ, Note 1
Voltage, full scale VFS
CURRENT SENSOR
Voltage, Current Gain, VIG
Current range, Io x DCR
Current error
1.854
1.5
RT = 25.5 kꢀ
V
mV
%
RCS2=600 ꢀ , RT=25.5 kꢀ
VO=1V; VDCR=20 mV, 0OC ≤ TJ ≤ 85OC
RCS2=600 ꢀ, RT=25.5 Kꢀ, Note 1
-35
35
-2.4
2.4
Page 2 of 20
www.irf.com
09/09/08
IR3720
DATA SHEET
PARAMETER
TEST CONDITION
MIN
435
TYP
512
MAX
UNIT
DIGITIZER
Internal Sampling frequency
External Sampling frequency
Transition time
Driven from internal clock
589
1126
50
kHz
kHz
ns
Driven from external clock
Driven from external clock Note 1
922
1024
POWER INFORMATION
Minimum Averaging Interval
Maximum Averaging Interval
Config Reg [d3..d0] = b‘0000, Note 1
Config Reg [d3..d0] = b‘1000, Note 1
0.9
230
1
1.1
282
ms
ms
256
1440
Output Register
Measuring power
VO=1V; VDCR=20 mV
RCS2=600 ꢀ , RT=25.5 kꢀ, Note 1,2
1380
1500
HEX
Output Register
Measuring power
VO=0.5V; VDCR=20 mV
0980
FF40
F740
3DC0
0A00
0000
F800
3F80
0A80
00C0
F8C0
4000
HEX
HEX
HEX
HEX
R
CS2=600 ꢀ, RT=25.5 kꢀ, Note 1,2
VO=1V; VDCR=0 mV
CS2=600 ꢀ, RT=25.5 kꢀ, Note 1,2
Output Register
Measuring power
R
Output Register
Measuring power
VO=1V; VDCR=-8 mV
RCS2=600 ꢀ, RT=25.5 kꢀ, Note 1,2
Full Scale Output Register
Measuring power
VO = 1.8; VDCR=35 mV
RCS2=600 ꢀ, RT=25.5 kꢀ, Note 1,2
DIGITAL INPUT AND OUTPUT
ALERT# pull down resistance
SDA & SCL HIGH Level
SDA & SCL Low Level
SCL Input current
Sink 3 mA
Note 1
250
Ω
V
2.1
-5
Note 1
0.8
+5
V
Note 1
uA
V
SDA pull down voltage
TIMING
Sink 4 mA Note 1
0.4
Maximum Frequency
Note 1
Note 1
10
400
kHz
us
Bus free time between stop and
start TBUF
1.3
Hold time after (repeated) start
condition THD:STA
Note 1
Note 1
0.6
0.6
us
us
Repeated start condition setup
time TSU:STA
Stop condition setup time TSU:STO Note 1
0.6
300
100
1.3
0.6
20
us
ns
ns
us
us
ns
ns
Data hold time THD:DAT
Data setup time TSU:DAT
Clock low period TLOW
Clock high period THIGH
Clock or data fall time TF
Clock or data rise time TR
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
300
300
20
NOTE:
1. Guaranteed by design, not tested in production
2. Average of eight data samples
Page 3 of 20
www.irf.com
09/09/08
IR3720
DATA SHEET
SYSTEM ACCURACY TEST CIRCUIT
VDCR
VDD
RCS2
CCS2
VCS
VO
VDD
ALERT#
EXTCLK
ADDR
SDA
VO
VDD
Bypass
Cap
VREF
SCL
RT
GND
Page 4 of 20
www.irf.com
09/09/08
IR3720
DATA SHEET
BLOCK DIAGRAM
IC PIN DESCRIPTION
NAME
VCS
NUMBER I/O LEVEL DESCRIPTION
1
2
Analog
Analog
Analog
Current sensing input
Voltage sensing input
Thermistor sensing input
IC bias supply and signal ground
3.3V bias supply
VO
VREF
GND
3
4
VDD
5
3.3V
EXTCLK
ADDR
SCL
6
3.3V Digital Input for optional external clock
3.3V Digital I2C Address selection input; See Table 1 for address
3.3V Digital I2C Clock; Input only
3.3V Digital I2C Data; Input / Open drain output
7
8
SDA
9
ALERT#
BASE PAD
10
3.3V Digital Programmable output function; Open drain output clamped to VDD
Connect to pin 4
Page 5 of 20
www.irf.com
09/09/08
IR3720
DATA SHEET
IC PIN FUNCTIONS
VDD PIN
ADDR PIN
This pin provides operational bias current to circuits
internal to the IR3720. Bypass it with a high quality
ceramic capacitor to the GND pin.
The ADDR pin is an input that establishes the I2C
address. Valid addresses are selected by grounding,
floating, or wiring to VDD the ADDR pin. Table 1,
“User Selectable Addresses”, provides a mapping of
possible selections.
GND PIN
This pin returns operational bias current to its source.
It is also the reference to which the voltage VO is
measured, and it sinks the reference current
established by the external resistor RT.
Table 1 User selectable addresses
ADDR pin configuration
I2C Address
b’1110 000
b’1110 010
b’1110 110
Low
Open
High
VO PIN
Connect this pin to the location in the circuit where
voltage for the power calculation is desired to be
monitored. Since it also measures DCR voltage drop
it is critical that it be Kelvin connected to the buck
inductor output. Power accuracy may be degraded if
EXTCLK
This pin is a Schmitt trigger input for an optional
externally provided square wave clock. The duty ratio
of this externally provided clock, if used, shall be
between 40% and 60%. If no external clock is used,
connect this pin to GND and the internal clock will be
used.
the voltage at this pin is below VOmin
.
VCS PIN
The average current into this pin is used to calculate
power. A switched current source internal to the
IR3720 will maintain the average voltage of this pin
equal to the voltage of the VO pin.
SCL
SCL is the I2C clock and is capable of functioning
with a rate as low as 10 kHz. It will continue to
function as the rate is increased to 400 kHz. This
device is considered a slave, and therefore uses the
SCL as an input only.
VREF FUNCTION
A voltage reference internal to the IR3720 drives the
VREF pin while the pin current is monitored and used
to set the amplitude of the current monitor switched
current source IREF. This pin should be connected to
GND through a precision resistor network RT. This
network may include provision for canceling the
positive temperature coefficient of the buck inductor’s
DC resistance (DCR).
SDA
SDA is monitored as data input during master to
slave transactions, and is driven as data output
during slave to master transactions as indicated in
the Packet Protocol section to follow.
ALERT# FUNCTION
The ALERT# pin is a multi-use pin. During normal
use it can be configured via the I2C as an open drain
ALERT# pin that will be driven logic low when new
data is available in the output register. After the
output register has been read via the I2C the ALERT#
will be released to its high resistance state. This pin
can also be programmed to pull low when the output
exceeds the programmable level.
Page 6 of 20
www.irf.com
09/09/08
TYPICAL PERFORMANCE CHARACTERISTICS
(System Accuracy Test Circuit, VDD=3.3 V, RCS2 = 600 ꢀ, CCS2 = 1 μF, RT = 25.5 k ꢀ)
Typical error - Current Configuration
Average of 8 samples
Typical transfer characteristic - Power configuration
Average of 8 samples
8
7
6
5
4
3
2
1
0
300
Vo = 0.5V
Vo = 1.0V
Vo = 1.8V
Ideal Code
Vo = 0.5V
Vo = 1.0V
Vo = 1.8V
0
-300
-0.035
0.000
0.035
VDCR (V)
0
0.005
0.01
0.015
0.02
DCR(V)
0.025
0.03
0.035
V
Typical error - Power Configuration
Average of 8 samples
8
7
6
5
4
3
2
1
0
Vo = 1.0V
Vo = 1.8V
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
VDCR (V)
Page 7 of 20
www.irf.com
09/09/08
FUNCTIONAL DESCRIPTION
Please refer to the Functional Description Diagram
below. Power flow from the buck converter is the
product of output voltage times the current IL flowing
through the inductor.
The full-scale voltage that can be measured is VFS.
The full-scale positive current that can be measured
is
Average power is measured with the aid of
V
RCS1 +RCS2
)
.
IG
IFS
=
⋅
(1)
International Rectifier’s proprietary TruePower™
circuit. Voltage, current, or the product of voltage Vo
and current is digitized over the interval of interest
and ported to the OUTPUT register. The VCS pin is
maintained at an average voltage equal to Vo.
RT
DCR
Full-scale current capability is designed by specifying
the external circuit values of equation 1.
The full scale power PFS that can be measured is the
product of full-scale voltage and full scale current.
IL
DCR
CCS1
Vin
Phase
VO
L
RCS1
RCS2
ALERT#
Pull-up
Resistor
CCS2
VCS
VDD
VDD
VO
ALERT#
VDD
Bypass
Cap
EXTCLK
VREF
IR3720
ADDR
External
Clock
SDA
SCL
RT
GND
Figure 1 Functional Description Diagram
Page 8 of 20
www.irf.com
09/09/08
RESISTOR SENSING APPLICATION
The voltage on the shunt resistor of the circuit below
is directly proportional to the current from the source.
Shunts developing 5 mV to 75 mV at IFS have been
used. Accuracy is enhanced at the higher voltage.
Select RT to be a 25.5 kꢀ 1% or better initial
RCS2 should be chosen such that this current through
it develops the same voltage that is developed by the
shunt at full scale current.
C
CS2 is the integrator capacitor and should be
between 0.1 μF and 10 μF.
tolerance resistor. This value will sink 1.5V /RT of
current from the VREF pin of the IR3720.
IL
SHUNT
DCR
Vin
VO
Phase
L
RCS2
CCS2
VDD
VCS
VO
VDD
ALERT#
VDD
Bypass
Cap
EXTCLK
ADDR
SDA
VREF
IR3720
SCL
RT
GND
Figure 2 Resistor Sensing Circuit
Page 9 of 20
www.irf.com
09/09/08
INDUCTOR DCR CURRENT SENSING APPLICATION
Referring to the Functional Description Diagram, it
can be seen that the shunt function can be
accomplished by the DC resistance of the inductor
that is already present. Omitting the resistive shunt
reduces BOM cost and increases efficiency. In
exchange for these two significant advantages two
easily compensated design complications are
introduced, a time constant and a temperature
coefficient.
The inductor voltage sensed between the Rcs1
resistors is not simply proportional to the inductor
current, but rather is expressed in the Laplace
equation below.
Select a standard value CCS1 that is larger than
4⋅L
DCR⋅RSUM
. Solve for Req.
We now know Req and Rsum, but we do not know
the individual resistor values RCS1 or RCS2. The next
step is to solve for them simultaneously. By
substituting Rsum into the Req equation the following
can be written:
RCS1 ⋅RCS2
Req
=
, which can then be rearranged to
Rsum
L
⎛
⎞
⎟
V = Ι ⋅DCR 1+ s
⎜
RC2S1 −RCS1 ⋅Rsum +Req ⋅Rsum = 0 .
L
L
DCR
⎝
⎠
Note that this equation is of the form
ax2 + bx + c = 0 where a=0, b=-Rsum, and
This inductor time constant is canceled when
RCS1 ⋅RCS2
c=Req•Rsum. The roots of this quadratic equation
will be RCS1 and RCS2. Use the higher value resistor
as RCS1 in order to minimize ripple current in CCS1
L
=
⋅CCS1 .
DCR RCS1 +RCS2
.
RCS1 ⋅RCS2
RCS1 +RCS2
Let
= Req .
Req
1+ 1− 4⋅
RSUM
RCS1 = RSUM
⋅
⋅
A second equation is used to set the full scale
inductor current.
2
and
V
(
RCS1 + RCS2
)
. Let
IG
Req
IFS
=
⋅
1− 1− 4⋅
RT
DCR
RSUM
RCS1 = RSUM
2
RCS1 +RCS2 = Rsum and solve for Rsum.
Page 10 of 20
www.irf.com
09/09/08
THERMAL COMPENSATION FOR INDUCTOR DCR CURRENT
SENSING
The positive temperature coefficient of the DCR can
be compensated if RT varies inversely proportional to
the DCR. DCR of a copper coil, as a function of
temperature, is approximated by
where Rth(T) is the thermistor resistance at some
temperature T, Rth(T0) is the thermistor resistance at
the reference temperature T0, and β is the material
constant provided by the thermistor manufacturer.
Degrees Kelvin are used in equation 3. If RS is large
and RP is small, the curvature of the effective network
resistance can be reduced from the curvature of the
thermistor alone. Although the exponential equation 3
can never compensate linear equation 2 at all
temperatures, a spreadsheet can be constructed to
minimize error over the temperature interval of
interest. The resistance RT of the network shown as a
function of temperature is
DCR(T) = DCR(TR ) ⋅ (1+ (T −TR ) ⋅TCRCu ) .
(2)
TR is some reference temperature, usually 25 °C, and
TCRCu is the resistive temperature coefficient of
copper, usually assumed to be 0.0039 near room
temperature. Note that equation 2 is linearly
increasing with temperature and has an offset of
DCR(TR) at the reference temperature.
If RT incorporates a negative temperature coefficient
thermistor then temperature effects of DCR can be
minimized. Consider a circuit of two resistors and a
thermistor as shown below.
1
RT(T) = Rs +
(4)
1
1
+
Rp Rth(T)
using Rth(T) from equation 3.
Equation 1 of the last section may be rewritten as a
new function of temperature using equations 2 and 4
as follows:
Rs
V
(
RCS1 +RCS2
DCR(T)
)
.
IG
IFS(T) =
⋅
(5)
Rp
Rth
RT(T)
With Rs and Rp as additional free variables, use a
spreadsheet to solve equation 5 for the desired full
scale current while minimizing the IFS(T) variation
over temperature.
Figure 3 RT Network
If Rth is an NTC thermistor then the value of the
network will decrease as temperature increases.
Unfortunately, most thermistors exhibit far more
variation with temperature than copper wire. One
equation used to model thermistors is
⎛
⎜
⎞
⎟
⎟
⎠
⎛
⎞
⎟
⎟
⎠
1
1
⎜
β⋅
−
⎜
Rth (T) = Rth (T0 ) ⋅ e⎝⎜
(3)
T
T0
⎝
Page 11 of 20
www.irf.com
09/09/08
TYPICAL 2-PHASE DCR-SENSING APPLICATION
The IR3720 is capable of monitoring power in a
multiphase converter. A two-phase circuit is shown
below. The voltage output of any phase is equal to
that of any and every other phase, and monitored at
VO as before.
If DCR1=DCR2, and RCS1=RCS3, then ICS can be
simplified to
(IL1 + IL2 ) ⋅ DCR1
RCS1 + 2RCS2
ICS
=
Output current is the sum of the two inductor currents
(IL1 + IL2). Superposition is used to derive the transfer
function for multiphase sensing. The voltage on RCS2
due to IL1 is
Full scale ICS current corresponds to
V
IG
ICSFS
=
RT
(RCS2 || RCS3
)
which yields 256 digital current counts
(0100 0000 0000 0000).
IL1 ⋅ DCR1 ⋅
RCS1 + (RCS2 || RCS3
)
Full scale total inductor current is
Likewise, the voltage on RCS2 due to IL2 is
(RCS2 || RCS1
RCS3 + (RCS 2 || RCS1
V
(RCS1 + 2⋅RCS2 )
IG
(IL1 +IL2 FS
)
=
⋅
RT
DCR
)
IL2 ⋅ DCR2 ⋅
)
The current through RCS2 due to both inductor
currents is ICS. From the two equations above
IL1DCR1RCS3 + IL2DCR2RCS1
RCS1RCS2 + RCS1RCS3 + RCS2RCS3
ICS
=
IL1
3.3V
Phase 1
L
DCR1
RCS1
VO
VDD
Multiphase
Converter
CCS1
CCS2
RCS2
GNIDR3720
LOAD
RCS3
VCS
Ics
RT
2
I2C Bus
VREF
Phase 2
L
T
DCR2
To system
Controller
IL2
Power
Return
RTN
Figure 4Two Phase DCR Sensing Circuit
Page 12 of 20
www.irf.com
09/09/08
ERROR MANAGEMENT
Component value errors external to the IR3720
contribute to power and current measurement error.
The power reported by the IR3720 is a function not
only of actual power or current, but also of products
and quotients of RT, RCS1, RCS2, DCR (or RSHUNT), as
well as parameters internal to the IR3720. The
tolerance of these components increases the total
power or current error. Small signal resistors are
typically available in 1% tolerance, but 0.1% parts are
available. Shunts are also available at 1% or 0.1%
tolerance. The DCR tolerance of inductors can be
5%, but 3% are available. Fortunately, it is not typical
that worst-case errors would systematically stack in
one direction. It is statistically likely that a high going
value would be paired with a low going value to
somewhat cancel the error. Because of this,
Quantization error occurs in digital systems because
the full scale is partitioned into a finite number of
intervals and the number of the interval containing
the measured value is reported. It is not likely that the
measured value would correspond exactly to the
center of the interval. The error could be as large as
half the width of the interval. With a binary word size
of eight, full scale is partitioned into 255 intervals.
Consider a measurement made near full scale. Any
signal in this interval is less than ± .2% (one-half of
100% / 256) away from the interval’s center, and
would therefore never have more error than that due
to quantization. On the other hand, consider a
measurement at one-tenth full scale. One-half of an
interval size at this level corresponds to 2% of the
reported value! Relative quantization error increases
as the measured value becomes small compared to
the full-scale value.
tolerances can be added in quadrature (RSS). As an
example, a 3% DCR used with a 1% RT, a 1% RCS,
and 3.3% IR3720 contributes
Quantization error can be reduced by averaging a
sequence of returned values.
(0.03)2 + (0.01)2 + (0.01)2 + (0.033)2 ≈ 4.7%
error to a typical system.
Page 13 of 20
www.irf.com
09/09/08
CONFIGURATION REGISTER
A configuration register is maintained via the I2C
MFR_SPECIFIC_00 command, code # D0h. The low
order nibble (d3, d2, d1, d0) contains a binary
number N from zero to eight. The averaging interval
is 2N milliseconds. N defaults to zero on start up.
The results of a configuration register change will be
reflected in the OUTPUT REGISTER after previously
requested operations have completed.
BIT #
CONFIGURATION REGISTER
The next bit (d4) is to be used as a function enable
bit. b’1 commands an energy saving shut down
mode, and power on default b’0 commands fully
functioning mode.
d0
d1
d2
Averaging interval (LSB)
Averaging interval
Averaging interval
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
Averaging interval (MSB)
Enable
External clock
d5 high enables the EXTCLK pin to receive the
external clock signal, and default d5 low enables the
internal clock.
OUTPUT config (LSB)
OUTPUT config (MSB)
ALERT# configuration
ALERT# threshold (LSB + 2)
ALERT# threshold
ALERT# threshold
ALERT# threshold
ALERT# threshold
ALERT# threshold
ALERT# threshold (MSB)
The next two bits (d7, d6) program the output
parameter. B’00 causes power to be measured and is
the power on default state. B’01 causes voltage to be
measured. B’10 causes current to be measured. B’11
is not defined and should not be used.
The next bit (d8) is used to configure the ALERT#
pin. b’0 is the power on default, and commands
ALERT# being pulled low when new data is available.
b’1 programs the ALERT# to pull low when the
programmable threshold level is exceeded, whether it
is power, voltage, or current.
Register bits (d15...d9) are the ALERT# threshold
register. If the output register is larger than this
register, and if (d8) is b’1, then the ALERT# pin will
pull low. The two least significant bits of the output
register are not represented in the ALERT# threshold
register. d15…d9 defaults to zero on start up.
Page 14 of 20
www.irf.com
09/09/08
OUTPUT REGISTER
The output register is loaded with a two’s compliment
factor of voltage, current, or power, depending on the
last request loaded into the configuration register. I2C
“Direct Data Format” is used. The value of the output
register is to be multiplied by a scale factor that is
derived from equations 1 and 2 above. Maximum
power is the product of maximum voltage and
maximum current.
The equations below convert digital counts to
engineering units:
VFS
Voltage = counts⋅
when configuration register
256
bits (d7, d6) are set to (01).
V ⋅(RCS1 +RCS2
256⋅RT ⋅DCR
)
IG
The range of valid values is indicated in Table 2
below.
Current = counts⋅
when
configuration register bits (d7, d6) are set to (10).
Table 2 Output Register Range of Returned
Values
VFS ⋅ V ⋅(RCS1 +RCS2
256⋅RT ⋅DCR
configuration register bits (d7, d6) are set to (00).
)
IG
Power = counts⋅
when
Parameter
Returned value
(twos compliment
binary)
0100 0000 0000 0000
0000 0000 0000 0000
0100 0000 0000 0000
1100 0000 0000 0000
0100 0000 0000 0000
1100 0000 0000 0000
Returned
value
(decimal)
256
0
256
-256
256
-256
FS voltage
Zero voltage
+FS current
-FS current
+FS power
-FS power
There is but one output register, and it holds the
measurement type (voltage, current, or power) last
requested by the configuration register. It is
incumbent upon the user to establish correct
configuration before requesting a read.
READ_VOUT, READ_IOUT, and READ_POUT are
equivalent in that each returns the contents of the
same output register.
A binary point is implicitly located to the left of the first
six least significant figures, as in the example below.
SYYY YYYY YY.00 0000
BIT#
OUTPUT REGISTER
d15:d0
Output variable, D0 is LSB
The “S” above is the twos compliment sign bit, and
the “Y’s” are the twos compliment. Six zeros pad out
the two byte response. These padding zeros could be
considered a factor of the slope, which is allowed by
the Direct Data Format. The output register multiplied
by its scale factor Kx yields the requested quantity in
engineering units of volts, amps, or watts.
RESERVED COMMAND
CODES
Command codes D2h through D5h, D7h, and D8h
are reserved for manufacturing use only and could
lead to undesirable device behavior.
Page 15 of 20
www.irf.com
09/09/08
PACKET PROTOCOL
S
W
R
A
=
=
=
=
=
=
Start Condition
Bus write (lo)
Bus read (hi)
Acknowledge, = 0 for ACK, =1 for NACK
Stop Condition
P
master to slave
=
slave to master
Bus Write CONFIGURATION Register
S
S
Slave Address
see Table 1
W A
Command Code
A
A
Data Byte Low
A
A
Data Byte High
A P
A P
0
A 1 1 0 1 0 0 0 0
d7 d6 d5 d4 d3 d2 d1 d0
d15
d14
d13
d12
d11
d10 d9 d8
Bus Read CONFIGURATION Register
Slave
Address
see
Table 1
Slave
Address
See
Table 1
S
S
W
0
A
Command Code A S
R A
Data Byte Low
A
A
Data Byte High
A P
1 P
d7 d6 d5 d4 d3 d2 d1 d0
1 A
d15 d14 d13 d12 d11 d10 d9
d8
d8
d8
d8
A 1 1 0 1 0 0 0 0 A S
Bus Read_VOUT (Output Register for Configuration register Data Byte Low = 01XXXXXX)
Slave
Address
see
Slave
Address
See
S
S
W
0
A
Command Code A S
R A
1 A
Data Byte Low
A
A
Data Byte High
A P
1 P
d7 d6 d5 d4 d3 d2 d1 d0
d15 d14 d13 d12 d11 d10 d9
A 1 0 0 0 1 0 1 1 A S
Table 1
Table 1
Bus Read_IOUT (Output Register for Configuration register Data Byte Low = 10XXXXXX)
Slave
Address
see
Slave
Address
See
S
S
W
0
A
Command Code A S
R A
1 A
Data Byte Low
A
A
Data Byte High
A P
1 P
d7 d6 d5 d4 d3 d2 d1 d0
d15 d14 d13 d12 d11 d10 d9
A 1 0 0 0 1 1 0 0 A S
Table 1
Table 1
Bus Read_POUT (Output Register for Configuration register Data Byte Low = 00XXXXXX)
Slave
Address
see
Slave
Address
See
S
S
W
0
A
Command Code A S
R A
1 A
Data Byte Low
A
A
Data Byte High
A P
1 P
d7 d6 d5 d4 d3 d2 d1 d0
d15 d14 d13 d12 d11 d10 d9
A 1 0 0 1 0 1 1 0 A S
Table 1
Table 1
Page 16 of 20
www.irf.com
09/09/08
PCB PAD AND COMPONENT PLACEMENT
The figure below shows suggested pad and component placement.
Page 17 of 20
www.irf.com
09/09/08
SOLDER RESIST
The figure below shows the suggested solder resist placement.
Page 18 of 20
www.irf.com
09/09/08
STENCIL DESIGN
The figure below shows a suggested stencil design.
Page 19 of 20
www.irf.com
09/09/08
PACKAGE INFORMATION
3X3 MM 10L DFN LEAD FREE
Data and specifications subject to change without notice.
This product has been designed and qualified for the consumer market.
Qualification standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Page 20 of 20
www.irf.com
09/09/08
相关型号：
©2020 ICPDF网 联系我们和版权申明