IQE022N06LM5 [INFINEON]
IQE022N06LM5 is Infineon’s new best-in-class OptiMOS™ 5 power MOSFET 60 V logic level in PQFN 3.3x3.3 Source-Down package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C and superior thermal performance. The OptiMOS™ Source-Down is a revolutionary technology with a flipped silicon die inside, offering several advantages such as better thermal capability, higher power density and improved layout possibilities. Combined with industrial standard PQFN 3.3x3.3 package, IQE022N06LM5 is targeted for high power density and performance SMPS products commonly found in telecom and data servers.;型号: | IQE022N06LM5 |
厂家: | Infineon |
描述: | IQE022N06LM5 is Infineon’s new best-in-class OptiMOS™ 5 power MOSFET 60 V logic level in PQFN 3.3x3.3 Source-Down package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C and superior thermal performance. The OptiMOS™ Source-Down is a revolutionary technology with a flipped silicon die inside, offering several advantages such as better thermal capability, higher power density and improved layout possibilities. Combined with industrial standard PQFN 3.3x3.3 package, IQE022N06LM5 is targeted for high power density and performance SMPS products commonly found in telecom and data servers. |
文件: | 总11页 (文件大小:1119K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IQE022N06LM5
MOSFET
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
PG-TSON-8
5
6
7
8
Features
•ꢀOptimizedꢀforꢀhighꢀperformanceꢀSMPS,ꢀe.g.ꢀsynchronousꢀrectification
•ꢀN-channel,ꢀlogicꢀlevel
•ꢀVeryꢀlowꢀon-resistanceꢀRDS(on)
•ꢀSuperiorꢀthermalꢀresistance
4
3
2
1
•ꢀ100%ꢀavalancheꢀtested
•ꢀPb-freeꢀleadꢀplating;ꢀRoHSꢀcompliant
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21
Productꢀvalidation
FullyꢀqualifiedꢀaccordingꢀtoꢀJEDECꢀforꢀIndustrialꢀApplications
Drain
Pin 5-8
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
Gate
Pin 4
Parameter
Value
Unit
Source
Pin 1-3
VDS
60
V
RDS(on),maxꢀ@10V
RDS(on),max@4.5V
ID
2.2
2.9
151
45
mΩ
mΩ
A
Qoss
nC
nC
QGꢀ(0V...4.5V)
26
Typeꢀ/ꢀOrderingꢀCode
Package
Marking
RelatedꢀLinks
IQE022N06LM5
PG-TSON-8
022N6L5
-
Final Data Sheet
1
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
TableꢀofꢀContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Final Data Sheet
2
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
1ꢀꢀꢀꢀꢀMaximumꢀratings
atꢀTA=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
-
-
-
-
-
-
-
-
151
107
93
VGS=10ꢀV,ꢀTC=25ꢀ°C
VGS=10ꢀV,ꢀTC=100ꢀ°C
Continuous drain current1)
ID
A
VGS=4.5ꢀV,ꢀTC=100ꢀ°C
24
VGS=10ꢀV,TA=25°C,RthJA=60°C/W2)
Pulsed drain current3)
Avalanche energy, single pulse4)
ID,pulse
EAS
-
-
-
-
604
241
20
A
TA=25ꢀ°C
-
mJ
V
ID=20ꢀA,ꢀRGS=25ꢀΩ
Gate source voltage
VGS
-20
-
-
-
-
-
100
2.5
TC=25ꢀ°C
Power dissipation
Ptot
W
TA=25ꢀ°C,ꢀRthJA=60ꢀ°C/W2)
Operating and storage temperature
Tj,ꢀTstg
-55
-
175
°C
-
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Values
Typ.
0.9
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Thermal resistance, junction - case
RthJC
RthJA
-
1.5
°C/W -
°C/W -
Thermal resistance, junction - ambient,
6 cm² cooling area2)
-
-
60
1) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature
as specified. For other case temperatures please refer to Diagram 2. De-rating will be required based on the actual
environmental conditions.
2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
3) See Diagram 3 for more detailed information
4) See Diagram 13 for more detailed information
Final Data Sheet
3
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics
atꢀTj=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics
Values
Typ.
-
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
60
Max.
-
Drain-source breakdown voltage
Gate threshold voltage
V(BR)DSS
VGS(th)
V
V
VGS=0ꢀV,ꢀID=1ꢀmA
VDS=VGS,ꢀID=48ꢀµA
1.1
1.7
2.3
-
-
0.1
10
1.0
100
VDS=60ꢀV,ꢀVGS=0ꢀV,ꢀTj=25ꢀ°C
VDS=60ꢀV,ꢀVGS=0ꢀV,ꢀTj=125ꢀ°C
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
IDSS
µA
nA
IGSS
-
10
100
VGS=20ꢀV,ꢀVDS=0ꢀV
-
-
1.9
2.5
2.2
2.9
VGS=10ꢀV,ꢀID=20ꢀA
VGS=4.5ꢀV,ꢀID=10ꢀA
RDS(on)
mΩ
Gate resistance
Transconductance1)
RG
gfs
-
-
1.1
93
1.4
-
Ω
-
S
|VDS|≥2|ID|RDS(on)max,ꢀID=20ꢀA
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Input capacitance1)
Output capacitance1)
Reverse transfer capacitance1)
Ciss
Coss
Crss
-
-
-
3400 4420 pF
VGS=0ꢀV,ꢀVDS=30ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=30ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=30ꢀV,ꢀf=1ꢀMHz
720
35
936
63
pF
pF
VDD=30ꢀV,ꢀVGS=10ꢀV,ꢀID=20ꢀA,
RG,ext=1.6ꢀΩ
Turn-on delay time
Rise time
td(on)
tr
td(off)
tf
-
-
-
-
6.1
4.1
26
-
-
-
-
ns
ns
ns
ns
VDD=30ꢀV,ꢀVGS=10ꢀV,ꢀID=20ꢀA,
RG,ext=1.6ꢀΩ
VDD=30ꢀV,ꢀVGS=10ꢀV,ꢀID=20ꢀA,
RG,ext=1.6ꢀΩ
Turn-off delay time
Fall time
VDD=30ꢀV,ꢀVGS=10ꢀV,ꢀID=20ꢀA,
RG,ext=1.6ꢀΩ
5.9
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics2)ꢀ
Values
Typ.
8.5
5.9
8
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Gate to source charge
Gate charge at threshold
Gate to drain charge1)
Switching charge
Gate charge total1)
Gate plateau voltage
Gate charge total
Qgs
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
V
VDD=30ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV
VDD=30ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV
VDD=30ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV
VDD=30ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV
VDD=30ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV
VDD=30ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV
VDD=30ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDS=30ꢀV,ꢀVGS=0ꢀV
Qg(th)
Qgd
-
12
-
Qsw
Qg
10.7
26
33
-
Vplateau
Qg
2.5
53
-
nC
nC
Output charge1)
Qoss
45
59
1) Defined by design. Not subject to production test.
2) See ″Gate charge waveforms″ for parameter definition
Final Data Sheet
4
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode
Values
Typ.
-
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
91
Diode continuous forward current
Diode pulse current
IS
-
-
-
-
-
-
-
A
TC=25ꢀ°C
IS,pulse
VSD
trr
-
604
1.0
52
A
TC=25ꢀ°C
Diode forward voltage
0.79
26
V
VGS=0ꢀV,ꢀIF=20ꢀA,ꢀTj=25ꢀ°C
VR=30ꢀV,ꢀIF=20ꢀA,ꢀdiF/dt=100ꢀA/µs
VR=30ꢀV,ꢀIF=20ꢀA,ꢀdiF/dt=100ꢀA/µs
VR=30ꢀV,ꢀIF=20ꢀA,ꢀdiF/dt=1000ꢀA/µs
VR=30ꢀV,ꢀIF=20ꢀA,ꢀdiF/dt=1000ꢀA/µs
Reverse recovery time1)
Reverse recovery charge1)
Reverse recovery time1)
Reverse recovery charge1)
ns
nC
ns
nC
Qrr
trr
19
38
17
34
Qrr
98
196
1) Defined by design. Not subject to production test.
Final Data Sheet
5
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams
Diagramꢀ1:ꢀPowerꢀdissipation
Diagramꢀ2:ꢀDrainꢀcurrent
120
175
150
125
100
75
100
80
60
40
20
0
50
25
0
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
TCꢀ[°C]
TCꢀ[°C]
Ptot=f(TC)
ID=f(TC);ꢀVGS≥10ꢀV
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance
103
102
1 µs
single pulse
0.01
0.02
0.05
0.1
0.2
0.5
10 µs
102
101
101
100 µs
1 ms
100
10-1
10-2
10-3
DC
100
10 ms
10-1
10-2
10-1
100
101
102
10-6
10-5
10-4
10-3
10-2
10-1
100
VDSꢀ[V]
tpꢀ[s]
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp
ZthJC=f(tp);ꢀparameter:ꢀD=tp/T
Final Data Sheet
6
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
700
6
5 V
2.8 V
10 V
4.5 V
600
500
400
300
200
100
0
5
3 V
3.5 V
4
4 V
4 V
3
2
1
0
4.5 V
5 V
3.5 V
10 V
3 V
2.8 V
0
1
2
3
4
5
0
40
80
120
160
200
240
280
320
VDSꢀ[V]
IDꢀ[A]
ID=f(VDS),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
RDS(on)=f(ID),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
700
6
600
500
400
300
200
100
0
5
4
25 °C
175 °C
3
2
1
0
175 °C
25 °C
0
1
2
3
4
5
0
2
4
6
8
10
12
14
16
VGSꢀ[V]
VGSꢀ[V]
ID=f(VGS),ꢀ|VDS|>2|ID|RDS(on)max;ꢀparameter:ꢀTj
RDS(on)=f(VGS),ꢀID=20ꢀA;ꢀparameter:ꢀTj
Final Data Sheet
7
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage
2.4
2.4
2.0
1.6
1.2
0.8
0.4
0.0
2.0
1.6
1.2
480 µA
48 µA
0.8
0.4
0.0
-75 -50 -25
0
25 50 75 100 125 150 175 200
-75 -50 -25
0
25 50 75 100 125 150 175 200
Tjꢀ[°C]
Tjꢀ[°C]
RDS(on)=f(Tj),ꢀID=20ꢀA,ꢀVGS=10ꢀV
VGS(th=f(Tj),ꢀVGS=VDS;ꢀparameter:ꢀID
Diagramꢀ11:ꢀTyp.ꢀcapacitances
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode
104
103
25 °C
25 °C, max
175 °C
175 °C, max
Ciss
103
102
101
102
101
100
Coss
Crss
0
10
20
30
40
50
60
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
VDSꢀ[V]
VSDꢀ[V]
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz
IF=f(VSD);ꢀparameter:ꢀTj
Final Data Sheet
8
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
Diagramꢀ13:ꢀAvalancheꢀcharacteristics
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge
102
10
12 V
30 V
48 V
8
6
4
2
0
101
25 °C
100 °C
150 °C
100
10-1
100
101
102
103
0
10
20
30
40
50
60
tAVꢀ[µs]
Qgateꢀ[nC]
IAS=f(tAV);ꢀRGS=25ꢀΩ;ꢀparameter:ꢀTj,start
VGS=f(Qgate),ꢀID=20ꢀAꢀpulsed,ꢀTj=25ꢀ°C;ꢀparameter:ꢀVDD
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage
Diagram Gate charge waveforms
65
64
63
62
61
60
59
58
57
-75 -50 -25
0
25 50 75 100 125 150 175 200
Tjꢀ[°C]
VBR(DSS)=f(Tj);ꢀID=1ꢀmA
Final Data Sheet
9
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
5ꢀꢀꢀꢀꢀPackageꢀOutlines
MILLIMETERS
DIMENSION
DOCUMENT NO.
Z8B00198723
MIN.
MAX.
1.10
0.05
0.40
A
A1
b
-
-
REVISION
01
0.20
c
0.20
3.30
D
SCALE 10:1
D1
E
2.31
2.51
2mm
0
1
3.30
0.65
e
L
0.35
0.10
0.40
1.35
0.26
0.84
0.77
0.55
0.30
0.60
1.55
0.46
1.04
0.97
EUROPEAN PROJECTION
L1
L2
L3
L4
L5
L6
ISSUE DATE
06.11.2019
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TSON-8,ꢀdimensionsꢀinꢀmm
Final Data Sheet
10
Rev.ꢀ2.0,ꢀꢀ2023-01-12
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ60ꢀV
IQE022N06LM5
RevisionꢀHistory
IQE022N06LM5
Revision:ꢀ2023-01-12,ꢀRev.ꢀ2.0
Previous Revision
Revision Date
Subjects (major changes since last revision)
Release of final version
2.0
2023-01-12
Trademarks
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Publishedꢀby
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Inꢀaddition,ꢀanyꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀisꢀsubjectꢀtoꢀcustomer’sꢀcomplianceꢀwithꢀitsꢀobligationsꢀstatedꢀinꢀthis
documentꢀandꢀanyꢀapplicableꢀlegalꢀrequirements,ꢀnormsꢀandꢀstandardsꢀconcerningꢀcustomer’sꢀproductsꢀandꢀanyꢀuseꢀofꢀthe
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technicalꢀdepartmentsꢀtoꢀevaluateꢀtheꢀsuitabilityꢀofꢀtheꢀproductꢀforꢀtheꢀintendedꢀapplicationꢀandꢀtheꢀcompletenessꢀofꢀtheꢀproduct
informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.
Information
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon
TechnologiesꢀOfficeꢀ(www.infineon.com).
Warnings
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
Final Data Sheet
11
Rev.ꢀ2.0,ꢀꢀ2023-01-12
相关型号:
IQE022N06LM5CG
IQE022N06LM5CG is Infineon’s new best-in-class OptiMOS™ 5 Power MOSFET 60 V logic level in PQFN 3.3x3.3 Source-Down Center-Gate (CG) package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C, superior thermal performance, and optimized parallelization. The OptiMOS™ Source-Down is a revolutionary technology with a flipped silicon die inside, offering several advantages such as better thermal capability, higher power density and improved layout possibilities. Combined with the new PQFN 3.3x3.3 Center-Gate package, IQE022N06LM5CG is targeted for high power density and performance SMPS products commonly found in telecom and data servers.
INFINEON
IQE022N06LM5CGSC
IQE022N06LM5CGSC is Infineon’s new best-in-class OptiMOS™ 5 power MOSFET 60 V logic level in a PQFN 3.3x3.3 Source-Down Center-Gate (CG) dual-side cooling (DSC) package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C , superior thermal performance, and optimized parallelization. The OptiMOS™ Source-Down is a revolutionary design with a flipped silicon die inside, which offers several advantages, such as increased thermal capability, advanced power density and improved layout possibilities. Combined with the innovative dual-side cooling package, which can dissipate up to three times more power than the traditional overmolded package, IQE022N06LM5CGSC is targeted for high power density and performance SMPS products commonly found in telecom and data servers.
INFINEON
IQE022N06LM5SC
IQE022N06LM5SC is Infineon’s new best-in-class OptiMOS™ 5 power MOSFET 60 V logic level in PQFN 3.3x3.3 Source-Down dual-side cooling (DSC) package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C and superior thermal performance. The OptiMOS™ Source-Down is a revolutionary design with a flipped silicon die inside, which offers several advantages, such as increased thermal capability, advanced power density and improved layout possibilities. Combined with the innovative dual-side cooling package, which can dissipate up to three times more power than the traditional overmolded package, IQE022N06LM5SC is targeted for high power density and performance SMPS products commonly found in telecom and data servers.
INFINEON
IQE030N06NM5CG
IQE030N06NM5CG 是英飞凌对创新性 源极底置 技术的延伸。 OptiMOS™ 5 30 V PQFN 3.3x3.3 源极底置具有 30 V 和极低 0.85 mOhm RDS(on)。革命性的源极底置技术使硅片倒置在元件内部。调整后,源极电位(而非漏极电位)即可通过导热垫连接到 PCB。这样就能提供多项优势,如增强热性能、高功率密度和改善布局。此外,更高的效率、更低的主动散热要求及有效的热管理布局有利于实现系统级优势。RDS(on) 新标杆和创新布局能力使 源极底置 概念在温度管理方面处于领先地位。源极底置产品组合解决了各种应用问题,包括 电机驱动、 电信、 SMPS 或 服务器。目前,有两种不同的产品尺寸采用了这项新技术:源极底置标准栅极和源极底置置中栅极(并行优化)。
INFINEON
IQE030N06NM5CGSC
英飞凌推出了创新型 源极底置 技术系列扩展的新产品, PQFN 3.3x3.3 源极底置 DSC 封装OptiMOSTM 5 60 V:IQE030N06NM5CGSC。革命性的源极底置技术引入了倒置式硅芯片,该芯片在组件内部上下颠倒。这种调整使得源极电位(而不是漏极电位)可以通过导热垫与 PCB 连接。因此,它具有几点优势,如热能力增强,先进的功率密度,或具有改善板上布局的可能性。
INFINEON
IQE046N08LM5
IQE046N08LM5 is Infineon’s new best-in-class OptiMOS™ 5 power MOSFET 80 V logic level in PQFN 3.3x3.3 Source-Down package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C and superior thermal performance. The OptiMOS™ Source-Down is a revolutionary technology with a flipped silicon die inside, offering several advantages such as better thermal capability, higher power density and improved layout possibilities. Combined with industrial standard PQFN 3.3x3.3 package, IQE046N08LM5 is targeted for high power density and performance SMPS products commonly found in telecom and data servers.
INFINEON
IQE046N08LM5CGSC
IQE046N08LM5CGSC is Infineon’s new best-in-class OptiMOS™ 5 power MOSFET 80 V logic level in PQFN 3.3x3.3 Source-Down Center-Gate (CG) dual-side cooling (DSC) package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C , superior thermal performance, and optimized parallelization. The OptiMOS™ Source-Down is a revolutionary design with a flipped silicon die inside, which offers several advantages, such as increased thermal capability, advanced power density and improved layout possibilities. Combined with the innovative dual-side cooling package, which can dissipate up to three times more power than the traditional overmolded package, IQE046N08LM5CGSC is targeted for high power density and performance SMPS products commonly found in telecom and data servers
INFINEON
IQE046N08LM5SC
IQE046N08LM5SC is Infineon’s new best-in-class OptiMOS™ 5 power MOSFET 80 V logic level in PQFN 3.3x3.3 Source-Down dual-side cooling (DSC) package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C and superior thermal performance. The OptiMOS™ Source-Down is a revolutionary design with a flipped silicon die inside, which offers several advantages, such as increased thermal capability, advanced power density and improved layout possibilities. Combined with the innovative dual-side cooling package, which can dissipate up to three times more power than the traditional overmolded package, IQE046N08LM5SC is targeted for high power density and performance SMPS products commonly found in telecom and data servers.
INFINEON
IQE050N08NM5
IQE050N08NM5 是英飞凌对创新性 源极底置 技术的延伸。 OptiMOS™ 5 30 V PQFN 3.3x3.3 源极底置具有 30 V 和极低 0.85 mOhm RDS(on)。革命性的源极底置技术使硅片倒置在元件内部。调整后,源极电位(而非漏极电位)即可通过导热垫连接到 PCB。这样就能提供多项优势,如增强热性能、高功率密度和改善布局。此外,更高的效率、更低的主动散热要求及有效的热管理布局有利于实现系统级优势。RDS(on) 新标杆和创新布局能力使 源极底置 概念在温度管理方面处于领先地位。源极底置产品组合解决了各种应用问题,包括 电机驱动、 电信、 SMPS 或 服务器。目前,有两种不同的产品尺寸采用了这项新技术:源极底置标准栅极和源极底置置中栅极(并行优化)。
INFINEON
IQE050N08NM5CG
IQE050N08NM5CG 是英飞凌对创新性 源极底置 技术的延伸。 OptiMOS™ 5 30 V PQFN 3.3x3.3 源极底置具有 30 V 和极低 0.85 mOhm RDS(on)。革命性的源极底置技术使硅片倒置在元件内部。调整后,源极电位(而非漏极电位)即可通过导热垫连接到 PCB。这样就能提供多项优势,如增强热性能、高功率密度和改善布局。此外,更高的效率、更低的主动散热要求及有效的热管理布局有利于实现系统级优势。RDS(on) 新标杆和创新布局能力使 源极底置 概念在温度管理方面处于领先地位。源极底置产品组合解决了各种应用问题,包括 电机驱动、 电信、 SMPS 或 服务器。目前,有两种不同的产品尺寸采用了这项新技术:源极底置标准栅极和源极底置置中栅极(并行优化)。
INFINEON
IQE050N08NM5CGSC
英飞凌推出了创新型 源极底置 技术系列扩展的新产品, PQFN 3.3x3.3 源极底置 DSC 封装OptiMOSTM 5 80 V:IQE050N08NM5CGSC。革命性的源极底置技术引入了倒置式硅芯片,该芯片在组件内部上下颠倒。这种调整使得源极电位(而不是漏极电位)可以通过导热垫与 PCB 连接。因此,它具有几点优势,如热能力增强,先进的功率密度,或具有改善板上布局的可能性。
INFINEON
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