IAUC100N08S5N034 [INFINEON]
The IAUC100N08S5N034 is a 3.4mR 80V MOSFET in a 5x6 mm² SSO8 package, using Infineon’s leading OptiMOS™ 5 technology. Next to others it is used in 48V auxiliaries, DCDC converter as well as power distribution.;
| 型号： | IAUC100N08S5N034 |
| 厂家： | 
Infineon |
| 描述： | The IAUC100N08S5N034 is a 3.4mR 80V MOSFET in a 5x6 mm² SSO8 package, using Infineon’s leading OptiMOS™ 5 technology. Next to others it is used in 48V auxiliaries, DCDC converter as well as power distribution. CD |
| 文件： | 总10页 (文件大小：1290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IAUC100N08S5N034
OptiMOS™-5 Power Transistor
Product Summary
VDS
80
3.4
100
V
Features
RDS(on),max
ID
mW
• OptiMOS™ power MOSFET for automotive applications
A
• N-channel - Enhancement mode - Normal Level
• MSL1 up to 260°C peak reflow
• 175 °C operating temperature
PG-TDSON-8-34
• Green product (RoHS compliant)
• 100% Avalanche tested
Type
Package
Marking
IAUC100N08S5N034
PG-TDSON-8-34
5N08034
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol
Conditions
Unit
V GS=10 V, Chip
limitation1,2)
I D
Drain current
132
A
V GS=10V, DC
current3)
T a=85 °C, V GS=10 V,
RthJA on 2s2p 2,4)
100
22
Pulsed drain current2)
I D,pulse
E AS
T C=25 °C
400
240
Avalanche energy, single pulse2)
Avalanche current, single pulse
Gate source voltage
I D=50 A
mJ
A
I AS
-
100
V GS
-
±20
V
P tot
T C=25 °C
Power dissipation
136
W
°C
T j, T stg
Operating and storage temperature
-
-55 ... +175
Rev. 1.1
page 1
2021-06-18
IAUC100N08S5N034
Values
typ.
Parameter
Symbol
Conditions
Unit
min.
max.
Thermal characteristics2)
R thJC
Thermal resistance, junction - case
-
-
-
-
-
1.1
-
K/W
Thermal resistance, junction -
ambient4)
R thJA
23.5
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
V (BR)DSS V GS=0V, I D=1mA
V GS(th) V DS=V GS, I D=78 µA
Drain-source breakdown voltage
Gate threshold voltage
80
-
-
V
2.2
3.0
3.8
V DS=80V, V GS=0V,
T j=25°C
I DSS
Zero gate voltage drain current
-
-
0.1
1
1
µA
V DS=80V, V GS=0V,
T j=85°C2)
20
I GSS
V GS=20V, V DS=0V
Gate-source leakage current
-
-
-
-
-
100 nA
R DS(on) V GS=6V, I D=25A
V GS=10V, I D=50A
Drain-source on-state resistance
3.9
2.8
1.5
4.8
3.4
-
mW
Gate resistance2)
R G
-
W
Rev. 1.1
page 2
2021-06-18
IAUC100N08S5N034
Values
typ.
Parameter
Symbol
Conditions
Unit
min.
max.
Dynamic characteristics2)
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Turn-off delay time
Rise time
C iss
C oss
Crss
t d(on)
t d(off)
t r
-
-
-
-
-
-
-
3507
620
27
4559 pF
806
V GS=0V, V DS=40V,
f =1MHz
41
10
-
-
-
-
ns
18
V DD=40V, V GS=10V,
I D=50A, R G,ext=3.5W
6
t f
Fall time
12
Gate Charge Characteristics2)
Gate to source charge
Gate to drain charge
Gate charge total
Q gs
-
-
-
-
17
12
51
4.7
22
18
66
-
nC
Q gd
V DD=40V, I D=50A,
V GS=0 to 10V
Q g
V plateau
Gate plateau voltage
V
A
Reverse Diode
Diode continous forward current2)
Diode pulse current2)
I S
T C=25°C
T C=25 °C
-
-
-
-
100
400
I S,pulse
V GS=0V, I F=50 A,
T j=25°C
V SD
Diode forward voltage
-
0.9
1.2
V
Reverse recovery time2)
t rr
-
-
48
55
-
-
ns
V R=40V, I F=50A,
di F/dt =100A/µs
Reverse recovery charge2)
Q rr
nC
1) Practically the current is limited by the overall system design including the customer-specific PCB.
2) The parameter is not subject to production test - verified by design/characterization.
3) The product can operate at a specified current based on best practice to minimize electro-migration at the solder joint.
For rare events and inrush currents, the value may be exceeded.
4) Device on a four-layer 2s2p FR4 PCB defined in accordance with JEDEC standards (JESD51-5-7). PCB is vertical in
still air.
Rev. 1.1
page 3
2021-06-18
IAUC100N08S5N034
1 Power dissipation
2 Drain current
P tot = f(T C); V GS = 10 V
I D = f(T C); V GS = 10 V
150
120
90
60
30
0
150
Chip Limit
120
DC Current
90
60
30
0
0
50
100
150
200
0
50
100
150
200
TC [°C]
TC [°C]
3 Safe operating area
4 Max. transient thermal impedance
I D = f(V DS); T C = 25 °C; D = 0
parameter: t p
Z thJC = f(t p)
parameter: D =t p/T
101
1000
100
10
1 µs
10 µs
100
0.5
100 µs
150 µs
0.1
10-1
0.05
0.01
10-2
single pulse
10-3
1
0.1
1
10
100
10-6
10-5
10-4
10-3
10-2
10-1
100
VDS [V]
tp [s]
Rev. 1.1
page 4
2021-06-18
IAUC100N08S5N034
5 Typ. output characteristics
6 Typ. drain-source on-state resistance
I D = f(V DS); T j = 25 °C
parameter: V GS
R DS(on) = f(I D); T j = 25 °C
parameter: V GS
18
400
10 V
7 V
6.5 V
5.5 V
14
300
6 V
10
200
5.5 V
5V
6 V
6.5 V
6
100
5 V
7 V
10 V
2
0
0
100
200
ID [A]
300
400
0
1
2
3
4
5
6
7
VDS [V]
7 Typ. transfer characteristics
8 Typ. drain-source on-state resistance
I D = f(V GS); V DS = 6V
parameter: T j
R DS(on) = f(T j);
parameter: ID, VGS
400
300
200
100
0
10
9
-55 °C
25 °C
8
7
175 °C
VGS=6V, ID=25A
6
5
4
3
2
VGS=10V, ID=50A
1
0
2
3
4
5
6
7
8
-60
-20
20
60
100
140
180
VGS [V]
Tj [°C]
Rev. 1.1
page 5
2021-06-18
IAUC100N08S5N034
9 Typ. gate threshold voltage
10 Typ. capacitances
V GS(th) = f(T j); V GS = V DS
parameter: I D
C = f(V DS); V GS = 0 V; f = 1 MHz
104
4
Ciss
3.5
780 µA
3
2.5
2
103
Coss
78 µA
102
Crss
1.5
1
101
0
20
40
60
80
-60
-20
20
60
Tj [°C]
100
140
180
VDS [V]
11 Typical forward diode characteristics
IF = f(VSD
12 Avalanche characteristics
I AS= f(t AV
)
)
parameter: T j
parameter: Tj(start)
103
1000
102
100
25 °C
150 °C
100 °C
25 °C
175 °C
101
10
100
0
1
0.2
0.4
0.6
0.8
1
1.2
0.1
1
10
100
1000
VSD [V]
tAV [µs]
Rev. 1.1
page 6
2021-06-18
IAUC100N08S5N034
13 Avalanche energy
E AS = f(T j)
14 Drain-source breakdown voltage
V BR(DSS) = f(T j); I D = 1 mA
parameter: I D
88
86
84
82
80
78
76
500
25 A
400
300
50 A
200
100 A
100
0
-60
-20
20
60
100
140
180
25
75
125
175
Tj [°C]
Tj [°C]
15 Typ. gate charge
16 Gate charge waveforms
V GS = f(Q gate); I D = 50 A pulsed
parameter: V DD
10
9
8
7
6
5
4
3
2
1
0
V GS
16 V
Q g
64V
40 V
V gs(th)
Q g(th)
Q sw
Q gate
0
10
20
30
40
50
60
Q gd
Q gs
Qgate [nC]
Rev. 1.1
page 7
2021-06-18
IAUC100N08S5N034
Package Outline
Footprint
Packaging
Rev. 1.1
page 8
2021-06-18
IAUC100N08S5N034
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 2021
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein, any typical values stated
herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties
of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact
the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the
express written approval of Infineon Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body or to support and/or maintain and sustain and/or protect human life.
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.1
page 9
2021-06-18
IAUC100N08S5N034
Revision History
Version
Date
Changes
Revision 1.0
Revision 1.1
2021-05-17
2021-06-18
Final Data Sheet
- Company logo size adjusted
- Datasheet file name updated
Rev. 1.1
page 10
2021-06-18
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