HYS72V64220GU-8B-A [INFINEON]
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| 型号： | HYS72V64220GU-8B-A |
| 厂家： | 
Infineon |
| 描述： | 暂无描述 动态存储器 |
| 文件： | 总17页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 V 16M × 64/72-Bit SDRAM Modules
3.3 V 32M × 64/72-Bit SDRAM Modules
3.3 V 64M × 64/72-Bit SDRAM Modules
HYS 64/72V16200GU
HYS 64/72V32220GU
HYS 64/72V32200GU
HYS 64/72V64220GU
PC100-168 pin unbuffered DIMM Modules
Preliminary Information
• 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications
• One bank 16M × 64, 16M × 72, 32M × 64 and 32M × 72 organization
• Two bank 32M × 64, 32M × 72, 64M × 64 and 64M × 72 organization
• Optimized for byte-write non-parity or ECC applications
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• JEDEC standard Synchronous DRAMs (SDRAM)
• SDRAM Performance:
-8
100
6
-8B
100
6
Units
MHz
ns
fCK
tAC
Clock frequency (max.)
Clock access time
• Programmed Latencies:
Product Speed
PC100
CL
tRCD
tRP
-8
2
3
2
2
3
-8B
PC100
2
• Single + 3.3 V (± 0.3 V) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 32M × 8 SDRAMs in TSOPII-54 packages
• Uses SIEMENS 128Mbit and 256Mbit SDRAM components
• Gold contact pad
• Card Size: 133.35 mm × 31.75 mm × 4.00 mm
Semiconductor Group
1
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
The HYS 64/72V1600, HYS 64/72V32220, HYS 64/72V32200 and HYS 64/72V64220 are industry
standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 16M × 64,
16M × 72, 32M × 64 and 32M × 72 in 1 bank and 32M × 64, 32M × 72, 64M × 64 and 64M × 72 in
two banks high speed memory arrays designed with 128M and 256M Synchronous DRAMs
(SDRAMs) for non-parity and ECC applications. The DIMMs use -8 and -8B speed sort for 16M × 8
and 32M × 8 SDRAM devices in TSOP-54 packages to meet the PC100 requirement. Decoupling
capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC 100
module specification.
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
available to the end user.
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm
long footprint, with 1.25“ (31.75 mm) height.
Ordering Information
Type
Ordering Code
Package
Descriptions
Module
Height
HYS 64V16200GU-8
HYS 72V16200GU-8
HYS 64V32220GU-8
HYS 72V32220GU-8
PC100-222-620 L-DIM-168-30 PC100 16M × 64 1 bank 1.25“
SDRAM module
PC100-222-620 L-DIM-168-30 PC100 16M × 72 1 bank 1.25“
SDRAM module
PC100-222-620 L-DIM-168-30 PC100 32M × 64 2 bank 1.25“
SDRAM module
PC100-222-620 L-DIM-168-30 PC100 32M × 72 2 bank 1.25“
SDRAM module
HYS 64V16200GU-8B PC100-323-620 L-DIM-168-30 PC100 16M × 64 1 bank 1.25“
SDRAM module
HYS 72V16200GU-8B PC100-323-620 L-DIM-168-30 PC100 16M × 72 1 bank 1.25“
SDRAM module
HYS 64V32220GU-8B PC100-323-620 L-DIM-168-30 PC100 32M × 64 2 bank 1.25“
SDRAM module
HYS 72V32220GU-8B PC100-323-620 L-DIM-168-30 PC100 32M × 72 2 bank 1.25“
SDRAM module
HYS 64V32200GU-8
HYS 72V32200GU-8
HYS 64V64220GU-8
HYS 72V64220GU-8
PC100-222-620 L-DIM-168-30 PC100 32M × 64 1 bank 1.25“
SDRAM module
PC100-222-620 L-DIM-168-30 PC100 32M × 72 1 bank 1.25“
SDRAM module
PC100-222-620 L-DIM-168-30 PC100 64M × 64 2 bank 1.25“
SDRAM module
PC100-222-620 L-DIM-168-30 PC100 64M × 72 2 bank 1.25“
SDRAM module
Semiconductor Group
2
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Ordering Information (cont’d)
Type Ordering Code
Package
Descriptions
Module
Height
HYS 64V32200GU-8B PC100-323-620 L-DIM-168-30 PC100 32M × 64 1 bank 1.25“
SDRAM module
HYS 72V32200GU-8B PC100-323-620 L-DIM-168-30 PC100 32M × 72 1 bank 1.25“
SDRAM module
HYS 64V64220GU-8B PC100-323-620 L-DIM-168-30 PC100 64M × 64 2 bank 1.25“
SDRAM module
HYS 72V64220GU-8B PC100-323-620 L-DIM-168-30 PC100 64M × 72 2 bank 1.25“
SDRAM module
Pin Names
A0-A12
Address Inputs
CLK0 - CLK3
Clock Input
(RA0 ~ RA10/CA0 ~ CA9)
BA0, BA1
DQ0 - DQ63
CB0-CB7
Bank Selects
DQMB0 - DQMB7 Data Mask
Data Input/Output
CS0 - CS3
Chip Select
Check Bits
VCC
Power (+ 3.3 Volt)
(× 72 organization only)
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Read/Write Input
VSS
Ground
SCL
SDA
Clock for Presence Detect
Serial Data Out for Presence
Detect
CKE0, CKE1
Clock Enable
N.C. / DU
No Connection
Address Format
Part Number
Rows Columns Bank
Select
Refresh Period Interval
16M × 64/72 HYS 64/72V16200GU 12
32M × 64/72 HYS 64/72V32220GU 12
32M × 64/72 HYS 64/72V32220GU 13
64M × 64/72 HYS 64/72V64220GU 13
10
10
10
10
2
2
2
2
4k
4k
8k
8k
64ms
64ms
64ms
64ms
15.6 µ
15.6 µ
7.8 µ
7.8 µ
Semiconductor Group
3
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Pin Configuration
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
1
2
3
4
5
6
VSS
43
44
45
46
47
48
VSS
DU
85
86
87
88
89
90
VSS
127
128
129
130
131
132
VSS
CKE0
CS3
DQ0
DQ1
DQ2
DQ3
VCC
DQ32
DQ33
DQ34
DQ35
VCC
CS2
DQMB2
DQMB3
DU
DQMB6
DQMB7
NC
7
DQ4
49
91
DQ36
133
VCC
VCC
8
DQ5
DQ6
DQ7
DQ8
VSS
50
51
52
53
54
NC
92
93
94
95
96
DQ37
DQ38
DQ39
DQ40
VSS
134
135
136
137
138
NC
9
NC
NC
10
11
12
NC (CB2)
NC (CB3)
VSS
CB6
CB7
VSS
13
14
15
16
17
DQ9
DQ10
DQ11
DQ12
DQ13
55
56
57
58
59
DQ16
DQ17
DQ18
DQ19
VCC
97
DQ41
DQ42
DQ43
DQ44
DQ45
139
140
141
142
143
DQ48
DQ49
DQ50
DQ51
VCC
98
99
100
101
18
60
DQ20
102
144
DQ52
VCC
VCC
19
20
21
22
DQ14
61
62
63
64
NC
103
104
105
106
DQ46
145
146
147
148
NC
DQ15
DU
DQ47
DU
NC (CB0)
NC (CB1)
CKE1
VSS
NC (CB4)
NC (CB5)
NC
VSS
DQ53
23
65
DQ21
107
149
VSS
VSS
24
25
26
NC
66
67
68
DQ22
DQ23
VSS
108
109
110
NC
150
151
152
DQ54
DQ55
VSS
NC
NC
VCC
VCC
27
28
29
30
31
WE
69
70
71
72
73
DQ24
DQ25
DQ26
DQ27
VCC
111
112
113
114
115
CAS
DQMB4
DQMB5
CS1
153
154
155
156
157
DQ56
DQ57
DQ58
DQ59
VCC
DQMB0
DQMB1
CS0
DU
RAS
32
74
DQ28
116
158
DQ60
VSS
A0
A2
A4
A6
VSS
A1
A3
A5
A7
33
34
35
36
75
76
77
78
DQ29
DQ30
DQ31
VSS
117
118
119
120
159
160
161
162
DQ61
DQ62
DQ63
VSS
37
38
39
40
A8
79
80
81
82
CLK2
NC
121
122
123
124
A9
163
164
165
166
CLK3
NC
A10
BA1
VCC
BA0
A11
VCC
WP
SA0
SDA
SA1
41
42
83
84
SCL
125
126
CLK1
167
168
SA2
VCC
CLK0
A12
VCC
VCC
Note: Pinnames in brackets are for the x72 ECC versions
Semiconductor Group
4
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
WE
CS0
CS
DQM
WE
CS
DQM
WE
DQMB0
DQ(7:0)
DQMB4
DQ0-DQ7
DQ(39:32)
DQ0-DQ7
D0
D4
CS
DQM
WE
CS
DQM
WE
DQMB1
DQMB5
DQ(15:8)
DQ0-DQ7
DQ(47:40)
DQ0-DQ7
D1
D5
CS
WE
DQM
CB(7:0)
CS2
DQ0-DQ7
D8
CS
DQM
WE
CS
DQM
WE
DQMB2
DQMB6
DQ(23:16)
DQ0-DQ7
DQ(55:48)
DQ0-DQ7
D2
D6
CS
DQM
WE
CS
DQM
WE
DQMB3
DQMB7
DQ(31:24)
DQ0-DQ7
DQ(63:56)
DQ0-DQ7
D3
D0-D7, (D8)
D7
E2PROM (256 word x 8 Bit)
A0-A11, (A12), BA0, BA1
VCC
SA0
SA0
SA1
SA2
SCL
SA1
SA2
SCL
SDA
WP
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
C
VSS
47 k
Ω
RAS
CAS
CKE0
Clock Wiring
32 M x 64
32 M x 72
5 SDRAM
Termination
4 SDRAM + 3.3 pF
Termination
CLK0
4 SDRAM + 3.3 pF
Termination
4 SDRAM + 3.3 pF
Termination
CLK1
CLK2
CLK3
Note: D8 is only used in the x72 ECC version.
SPB03970
Block Diagram for 16M × 64/72 & 32M × 64/72 one bank SDRAM DIMM Modules
(HYS 64/72V16200GU & HYS 64/72V32200GU)
Semiconductor Group
5
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
CS1
CS0
CS
CS
CS
CS
DQMB0
DQ(7:0)
DQM
DQM
DQMB4
DQM
DQM
DQ0-DQ7
DQ0-DQ7
DQ(39:32)
DQ0-DQ7
DQ0-DQ7
D0
D1
D8
D9
D4
D5
D12
D13
CS
CS
CS
CS
DQMB1
DQM
DQM
DQMB5
DQM
DQM
DQ(15:8)
DQ0-DQ7
DQ0-DQ7
DQ(47:40)
DQ0-DQ7
DQ0-DQ7
CS
CS
DQM
DQM
DQ0-DQ7
CB(7:0)
DQ0-DQ7
D16
D17
CS3
CS2
CS
CS
CS
CS
DQMB2
DQM
DQM
DQMB6
DQM
DQM
DQ(23:16)
DQ0-DQ7
DQ0-DQ7
DQ(55:48)
DQ0-DQ7
DQ0-DQ7
D2
D3
D10
D11
D6
D7
D14
D15
CS
CS
CS
CS
DQMB3
DQM
DQM
DQMB7
DQM
DQM
DQ(31:24)
DQ0-DQ7
DQ0-DQ7
DQ(63:56)
DQ0-DQ7
DQ0-DQ7
A0-A12, BA0, BA1
VDD
D0-D15, (D16, D17)
D0-D15, (D16, D17)
E2PROM (256 word x 8 Bit)
SA0
SA0
SA1
SA2
SCL
SA1
SA2
SCL
SDA
WP
C0-C31, (C32...C35)
VSS
D0-D7, (D8)
47 k
Ω
RAS, CAS, WE
CKE0
D0-D15, (D16, D17)
Clock Wiring
64 M x 64
D0-D7, (D16)
D9-D15, (D17)
VDD
10 k
64 M x 72
5 SDRAM
5 SDRAM
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
Ω
CLK0
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
CLK1
CLK2
CLK3
CKE1
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted.
SPB03971
Block Diagram for 32M × 64/72 & 64M × 64/72 two bank SDRAM DIMM Modules
Semiconductor Group
6
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
max.
Unit
min.
2.0
Input high voltage
VIH
VIL
V
CC + 0.3
V
Input low voltage
– 0.5
2.4
0.8
–
V
Output high voltage (IOUT = – 2.0 mA)
Output low voltage (IOUT = 2.0 mA)
VOH
VOL
II(L)
V
–
0.4
40
V
Input leakage current, any input
– 40
µA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output leakage current
IO(L)
– 40
40
µA
(DQ is disabled, 0 V < VOUT < VCC)
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
max. max.
32M×64 32M×72 32M×64 32M×72
Unit
max.
max.
Input capacitance
CI1
45
55
80
90
pF
(A0 to A11, BA0, BA1, RAS, CAS, WE)
Input capacitance (CS0 - CS3)
Input capacitance (CLK0 - CLK3)
Input capacitance (CKE0, CKE1)
Input capacitance (DQMB0 - DQMB7)
CI2
CICL
CI3
CI4
CIO
20
22
22
13
13
25
38
38
13
12
30
22
50
20
20
35
38
55
20
20
pF
pF
pF
pF
pF
Input/Output capacitance
(DQ0 - DQ63, CB0 - CB7)
Input Capacitance (SCL, SA0 - 2)
Input/Output Capacitance
CSC
CSD
8
8
8
8
pF
pF
10
10
10
10
Semiconductor Group
7
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Operating Currents
TA = 0 to 70 °C, VCC = 3.3 V ± 0.3 V 1
Recommended Operating Conditions unless otherwise noted
Parameter & Test Condition
Symb. -8/-8B -10
max.
Unit Note
Operating current
ICC1
t
RC ≥ tRC(MIN.), tCK ≥ tCK(MIN.)
2
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner to maximize
gapless data access
× 4
× 8
× 16
210
210
210
165
165
165
mA
mA
mA
2
t
CK = min.
Precharged Standby Current in
Power Down Mode
ICC2P
2
2
mA
CS = VIH(MIN.), CKE ≤ VIL(MAX.)
2
t
CK = min.
Precharged Standby Current in Non-
power Down Mode
ICC2N
19
16
mA
CS = VIH(MIN.), CKE ≥ VIH(MIN.)
2
CKE ≥ VIH(MIN.)
CKE ≤ VIL(MAX.)
No operating current
ICC3N
ICC3P
45
10
40
10
mA
t
CK = min., CS = VIH(MIN.),
2
active state (max. 4 banks)
mA
–
Burst operating current
ICC4
× 4
× 8
2, 3
t
CK = min.,
210
210
210
165
165
165
mA
mA
mA
Read command cycling
× 16
2
–
Auto refresh current
ICC5
240
195
mA
t
CK = min.,
Auto Refresh command cycling
2
Self refresh current
standard version ICC6
2.5
2.5
mA
Self Refresh Mode, CKE = 0.2 V
Notes
1. All values are shown per one SDRAM component.
2. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8
and at 66 MHz for -10 parts. Input signals are changed once during tCK, excepts for ICC6 and for
standby currents when tCK = infinity.
3. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 is assumed and the VDDQ current is excluded.
Semiconductor Group
8
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
1, 2
AC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
Unit Note
-8
PC100-222
-8B
PC100-323
min. max.
min.
max.
Clock and Clock Enable
Clock Cycle Time
tCK
fCK
tAC
CAS Latency = 3
CAS Latency = 2
10
10
–
–
10
12
–
–
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
–
–
100
100
–
–
100
83
MHz
MHz
Clock Access Time
3, 4
CAS Latency = 3
CAS Latency = 2
–
–
6
6
–
–
6
7
ns
ns
4
Clock High Pulse Width
tCH
3
3
2
1
2
–
–
–
–
–
3
3
2
1
2
–
–
–
–
–
ns
4
Clock Low Pulse Width
Input Setup Time
Input Hold Time
tCL
ns
5
tCS
ns
5
tCH
ns
6
CKE Setup Time
tCKSP
ns
(Power down mode)
7
CKE Setup Time
(Self Refresh Exit)
tCKSR
tT
10
1
–
–
–
–
–
–
ns
Transition Time (rise and fall)
ns
Common Parameters
RAS to CAS Delay
Cycle Time
tRCD
tRC
tRAS
tRP
tRRD
tCCD
20
70
48
20
16
1
–
–
–
–
–
–
20
70
48
30
20
1
–
–
–
–
–
–
ns
ns
Active Command Period
Precharge Time
ns
ns
Bank to Bank Delay Time
ns
CAS to CAS Delay Time
(same bank)
CLK
Semiconductor Group
9
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
AC Characteristics (cont’d) 1, 2
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
Unit Note
-8
PC100-222
-8B
PC100-323
min. max.
min.
max.
Refresh Cycle
9
Self Refresh Exit Time
Refresh Period
tSREX
tREF
10
64
–
–
10
64
–
–
ns
6
ms
Refresh Interval
128Mbit SDRAM based modules
256Mbit SDRAM based modules
–
–
15.6
7.8
–
–
15.6
7.8
µs
µs
Read Cycle
2
Data Out Hold Time
tOH
3
0
3
–
–
8
3
0
3
–
ns
Data Out to Low Impedance Time tLZ
–
ns
8
Data Out to High Impedance
Time
tHZ
10
ns
DQM Data Out Disable Latency
tDQZ
–
2
2
–
–
2
2
–
CLK
CLK
Write Cycle
Data Input to Precharge
(write recovery)
tWR
Data In to Active/Refresh
DQM Write Mask Latency
tDAL
5
0
–
–
5
0
–
–
CLK
CLK
tDQW
Semiconductor Group
10
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Notes
1. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command
must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set
Operation can begin.
2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V
crossover point. The transition time is measured between VIH and VIL. All AC measurements
assume tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are
measured with a 50 pF only, without any resisitve termination and with a input signal of 1 V/ns
edge rate between 0.8 V and 2.0 V.
tCH
2.4 V
0.4 V
CLOCK
tT
tCL
tHOLD
tSETUP
INPUT
1.4 V
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
AC and tOH
OUTPUT
1.4 V
t
tHZ
SPT03404
3. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
4. Rated at 1.5 V
5. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
6. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
7. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
8. Referenced to the time which the output achieves the open circuit condition, not to output
voltage levels.
Semiconductor Group
11
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
A serial presence detect storage device - E2PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a serial presence detect protocol (I2C synchronous 2-wire bus).
SPD-Table for 256MBit SDRAM based PC100 Modules
Byte# Description
SPD Entry
Value
Hex
32M×64 32M×64 32M×72 32M×72
one bank one bank one bank one bank
-8
-8B
-8
-8B
0
1
2
3
Number of SPD bytes
128
80
08
04
0D
80
80
08
04
0D
80
Total bytes in Serial PD
Memory Type
256
08
08
SDRAM
13
04
04
Number of Row
Addresses
0D
0D
(without BS bits)
4
Number of Column
Addresses (for 32M×8
SDRAMs)
10
0A
0A
0A
0A
5
6
7
Number of DIMM Banks
Module Data Width
1
01
40
00
01
40
00
01
48
00
01
48
00
64/72
0
Module Data Width
(cont’d)
8
9
Module Interface Levels LVTTL
01
A0
01
A0
01
A0
01
A0
SDRAM Cycle Time at
CL = 3
10.0 ns
10
SDRAM Access time
from Clock at CL = 3
6.0 ns
60
60
60
60
11
12
Dimm Configuration
Refresh Rate/Type
none / ECC
00
82
00
82
02
82
02
82
Self-Refresh,
7.8 µs
13
14
SDRAMwidth,Primary
x8
08
00
08
00
08
08
08
08
Error Checking SDRAM n/a/x8
data width
15
Minimum clock delay for
back-to-back random
column address
t
CCD = 1 CLK
01
01
01
01
16
17
Burst Length supported
1, 2, 4, 8 & full
page
8F
04
8F
04
8F
04
8F
04
Number of SDRAM
banks
4
Semiconductor Group
12
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte# Description
SPD Entry
Value
Hex
32M×64 32M×64 32M×72 32M×72
one bank one bank one bank one bank
-8
-8B
-8
-8B
18
Supported CAS
Latencies
CAS latency = 2 06
& 3
06
06
06
19
20
21
CS Latencies
WE Latencies
CS latency = 0
01
01
01
00
01
01
00
01
01
00
Write latency = 0 01
SDRAM DIMM module
attributes
non buffered/
non re.
00
06
A0
60
FF
FF
22
23
24
25
26
SDRAM Device
Attributes: General
V
CC tol ± 10%
06
C0
70
FF
FF
06
A0
60
FF
FF
06
C0
70
FF
FF
Min. Clock Cycle Time at 10.0 / 12.0 ns
CAS Latency = 2
Max. data access time
from Clock for CL = 2
6.0 / 7.0 ns
Minimum Clock Cycle
Time at CL = 1
not supported
not supported
Maximum Data Access
Time from Clock at
CL = 1
27
28
29
30
31
Minimum Row Precharge 20 / 30 ns
Time
14
10
14
32
40
1E
14
14
3C
40
14
10
14
32
40
1E
14
14
3C
40
Minimum Row Active to
16 / 20 ns
Row Active delay tRRD
Minimum RAS to CAS
20 ns
delay tRCD
Minimum RAS pulse
width tRAS
50 / 60 ns
256 MByte
Module Bank Density
(per bank)
32
33
34
SDRAM input setup time 2 ns
20
10
20
20
10
20
20
10
20
20
10
20
SDRAM input hold time
1 ns
2 ns
SDRAM data input hold
time
35
SDRAM data input setup 1 ns
time
10
10
10
10
Semiconductor Group
13
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte# Description
SPD Entry
Value
Hex
32M×64 32M×64 32M×72 32M×72
one bank one bank one bank one bank
-8
-8B
-8
-8B
62-61 Superset information
(may be used in future)
–
FF
FF
FF
FF
62
63
SPD Revision
Revision 1.2
–
12
–
12
–
12
–
12
–
Checksum for bytes
0 - 62
64-
Manufacturers
–
XX
XX
XX
XX
125
information (optional)
(FFH if not used)
126
127
Frequency Specification 100 MHz
100 MHz support details
64
AF
FF
64
64
AF
FF
64
–
AD
FF
AD
FF
128+ Unused storage locations –
SPD-Table for 256MBit SDRAM based PC100 Modules
Byte# Description
SPD Entry
Value
Hex
64M×64 64M×64 64M×72 64M×72
two bank two bank two bank two bank
-8
-8B
-8
-8B
0
1
2
3
Number of SPD bytes
128
80
08
04
0D
80
80
08
04
0D
80
Total bytes in Serial PD
Memory Type
256
08
08
SDRAM
13
04
04
Number of Row
Addresses
0D
0D
(without BS bits)
4
Number of Column
Addresses
10
0A
0A
0A
0A
(for 32M × 8 SDRAMs)
5
6
7
Number of DIMM Banks
Module Data Width
2
02
40
00
02
40
00
02
48
00
02
48
00
64/72
0
Module Data Width
(cont’d)
8
9
Module Interface Levels LVTTL
01
A0
01
A0
01
A0
01
A0
SDRAM Cycle Time at
CL = 3
10.0 ns
Semiconductor Group
14
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte# Description
SPD Entry
Value
Hex
64M×64 64M×64 64M×72 64M×72
two bank two bank two bank two bank
-8
-8B
-8
-8B
10
SDRAM Access time
6.0 ns
60
60
60
60
from Clock at CL = 3
Dimm Configuration
Refresh Rate/Type
11
12
none/ECC
00
82
00
82
02
82
02
82
Self Refresh,
7.8 µs
13
14
SDRAMwidth,Primary
× 8
08
00
08
00
08
08
08
08
Error Checking SDRAM n/a/× 8
data width
15
Minimum clock delay for
back-to-back random
column address
tCCD = 1 CLK
01
01
01
01
16
17
18
Burst Length supported
1, 2, 4, 8 & full
page
8F
04
8F
04
06
8F
04
06
8F
04
06
Number of SDRAM
banks
4
Supported CAS
Latencies
CAS latency = 2 06
& 3
19
20
21
CS Latencies
WE Latencies
CS latency = 0
01
01
01
00
01
01
00
01
01
00
Write latency = 0 01
SDRAM DIMM module
attributes
non buffered/
non re.
00
06
A0
60
FF
FF
22
23
24
25
26
SDRAM Device
Attributes: General
V
CC tol ± 10%
06
C0
70
FF
FF
06
A0
60
FF
FF
06
C0
70
FF
FF
Min. Clock Cycle Time at 10.0/12.0 ns
CAS Latency = 2
Max. data access time
from Clock for CL = 2
6.0/7.0 ns
Minimum Clock Cycle
Time at CL = 1
not supported
not supported
Maximum Data Access
Time from Clock at
CL = 1
27
Minimum Row Precharge 20/30 ns
Time
14
1E
14
1E
Semiconductor Group
15
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte# Description
SPD Entry
Value
Hex
64M×64 64M×64 64M×72 64M×72
two bank two bank two bank two bank
-8
-8B
-8
-8B
28
29
30
31
Minimum Row Active to
Row Active delay tRRD
16/20 ns
20 ns
10
14
10
14
Minimum RAS to CAS
delay tRCD
14
32
40
14
3C
40
14
32
40
14
3C
40
Minimum RAS pulse
width tRAS
50/60 ns
256 MByte
Module Bank Density
(per bank)
32
33
34
SDRAM input setup time 2 ns
20
10
20
20
10
20
20
10
20
20
10
20
SDRAM input hold time
1 ns
2 ns
SDRAM data input hold
time
35
SDRAM data input setup 1 ns
time
10
FF
10
FF
10
FF
10
FF
62-61 Superset information
(may be used in future)
62
63
SPD Revision
Revision 1.2
12
10
12
65
12
22
12
77
Checksum for bytes
0 - 62
64-
Manufacturers
XX
XX
XX
XX
125
information (optional)
(FFH if not used)
126
127
Frequency Specification 100 MHz
100 MHz support details
64
FF
FF
64
FD
FF
64
FF
FF
64
FD
FF
128+ Unused storage locations
Semiconductor Group
16
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Package Outlines
L-DIM-168-30
SDRAM DIMM Module Package
133.35
4
127.35
*)
1
10
11
6.35
40
41
6.35
84
1.27±
0.1
3
1.27
42.18
91 x 1.27 = 115.57
124 125
2
85 94
95
168
*)
R1.27+0.1
3 min.
2.26
Detail of Contacts
*) on ECC modules only
1±
0.05
1.27
GLD09159
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
1998-08-01
SMD = Surface Mounted Device
Semiconductor Group
17
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