HYS72T128020GR-5-A [INFINEON]
DDR2 Registered Memory Modules; DDR2寄存式内存模块
| 型号： | HYS72T128020GR-5-A |
| 厂家： | 
Infineon |
| 描述： | DDR2 Registered Memory Modules |
| 文件： | 总33页 (文件大小：896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 0.85, Apr. 2004
HYS72T64000[G/H]R-x-A (512 MByte)
HYS72T128000[G/H]R-x-A (1 GByte)
HYS72T128020[G/H]R-x-A (1 GByte)
HYS72T256020[G/H]R-x-A (2 GByte)
HYS72T256220[G/H]R-x-A (2 GByte)
DDR2 Registered Memory Modules
Memory Products
N e v e r s t o p t h i n k i n g .
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Preliminary Data Sheet Rev. 0.85 (Apr. 2004)
Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet
512 MByte, 1 GByte & 2 GByte Modules
PC2-3200R, PC2-4300R
•
•
•
•
•
240-pin Registered 8-Byte ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation
and Server main memory applications
•
Programmable CAS Latencies (3, 4 & 5),
Burst Length (4 & 8) and Burst Type.
•
•
•
Auto Refresh and Self Refresh
One rank 64Mb x 72, 128Mb x 72 and
two ranks 128Mb × 72 and 256Mb x 72
organizations
All inputs and outputs SSTL_1.8 compatible
Re-drive for all input signals using register
and PLL devices.
JEDEC standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with
+ 1.8 V (± 0.1 V) power supply
•
OCD (Off-Chip Driver Impedance
Adjustment) and ODT (On-Die Termination)
512MB and 1 GB modulesModules built with
512Mb DDR2 SDRAMs in 60-ball FBGA
chipsize packages
•
•
Serial Presence Detect with E2PROM
Low Profile Modules form factor:
133.35 mm x 30,00 mm (MO-237)
Two versions of 2 GB modules
built with 63-ball FBGA dual die chipsize packages
(2 x 512Mb components) or 60-ball FBGA packages
•
Based on JEDEC standard reference card
designs
Performance:
Speed Grade Indicator
–5
DDR2–400
PC2–3200R
200
–3.7
DDR2–533
PC2–4300R
200
Unit
Component Speed Grade on Module
Module Speed Grade
Max. Clock Frequency @ CL = 3
Max. Clock Frequency@ CL = 4 & 5
MHz
MHz
200
266
1.0 Description
The INFINEON HYS72Taaabcd[G/H]R module family are low profile Registered DIMM modules
with 30,00 mm height based on DDR2 technology. DIMMs are available in 64M x 72 (512MByte),
128M x 72 (1GByte) and 256M x 72 (2GByte) organisation and density, intended for mounting into
240 pin connector sockets.
The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for
ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one
cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide
a proper voltage supply impedance over the whole frequency range of operations as number and
values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based
on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to the customer.
2
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
1.1 Ordering Information
Product Type
Compliance Code
Description
SDRAM Technology
PC2-3200 (DDR2-400)
HYS72T64000GR-5-A
HYS72T128020GR-5-A
HYS72T128000GR-5-A
HYS72T256220GR-5-A
HYS72T256020GR-5-A
PC2-4300 (DDR2-533)
HYS72T64000GR-3.7-A
PC2-3200R-333-11-A one rank 512 MB Reg. DIMM
PC2-3200R-333-11-B two ranks 1024 MB Reg.DIMM
PC2-3200R-333-11-C one rank 1024 MB Reg. DIMM
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x4)
PC2-3200R-333-11
PC2-3200R-333-11
two ranks 2048 MB Reg. DIMM 512 Mbit (x4)
two ranks 2048 MB Reg. DIMM 512 Mbit (x4)
PC2-4300R-444-11-A one rank 512 MB Reg. DIMM
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x4)
HYS72T128020GR-3.7-A PC2-4300R-444-11-B two ranks 1024 MB Reg.DIMM
HYS72T128000GR-3.7-A PC2-4300R-444-11-C one rank 1024 MB Reg. DIMM
HYS72T256020GR-3.7-A PC2-4300R-444-11
two ranks 2048 MB Reg. DIMM 512 Mbit (x4)
PC2-3200 (DDR2-400)
HYS72T64000HR-5-A
HYS72T128020HR-5-A
HYS72T128000HR-5-A
HYS72T256220HR-5-A
HYS72T256020HR-5-A
PC2-4300 (DDR2-533)
PC2-3200R-333-11-A one rank 512 MB Reg. DIMM 512 Mbit (x8)
PC2-3200R-333-11-B two ranks 1024 MB Reg.DIMM
PC2-3200R-333-11-C one rank 1024 MB Reg. DIMM
512 Mbit (x8)
512 Mbit (x4)
PC2-3200R-333-11
PC2-3200R-333-11
two ranks 2048 MB Reg. DIMM 512 Mbit (x4)
two ranks 2048 MB Reg. DIMM 512 Mbit (x4)
HYS72T64000HR-3.7-A
PC2-4300R-444-11-A one rank 512 MB Reg. DIMM
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x4)
HYS72T128020HR-3.7-A PC2-4300R-444-11-B two ranks 1024 MB Reg.DIMM
HYS72T128000HR-3.7-A PC2-4300R-444-11-C one rank 1024 MB Reg. DIMM
HYS72T256020HR-3.7-A PC2-4300R-444-11
Notes:
two ranks 2048 MB Reg. DIMM 512 Mbit (x4)
1. For all INFINEON DDR2 module and component nomenclature see section 8 of this data sheet.
2. The Compliance Code is printed on the module label and describes the speed grade, e. g. “PC2-4300R-444-11-C”, where
4300R means Registered modules with 4.26 GB/sec Module Bandwidth and “444-11” means CAS latency = 4, trcd latency
= 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card “C”.
1.2 Address Format
Product Type
DIMM Density Organization DIMM Ranks SDRAMs # of SDRAMs # of row/bank/
column bits
HYS72T64000GR
HYS72T64000HR
512 MB
1024 MB
1024 MB
2048 MB
2048 MB
64Mb × 72
2 x 64Mb × 72
128Mb x 72
1
2
1
2
2
(512Mb)
64Mb × 8
9
14/2/10
14/2/10
14/2/11
14/2/11
14/2/11
HYS72T128020GR
HYS72T128020HR
(512Mb)
64Mb × 8
18
18
36
36
HYS72T128000GR
HYS72T128000HR
(512Mb)
128Mb × 4
HYS72T256220GR
HYS72T256220HR
2 x 128Mb × 72
2 x 128Mb × 72
(512Mb)
128Mb × 4
HYS72T256020GR
HYS72T256020HR
(512Mb)
128Mb × 4
Data Sheet
Preliminary
3
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
1.3 Components on Modules and RawCard
DIMM
Density
DRAM components
reference datasheet
PLL
1:10, 1.8V, CU877
1:10, 1.8V, CU877
1:10, 1.8V, CU877
tbd.
Register
1:1 25-bit 1.8V SSTU32864
1:2 14-bit 1.8V SSTU32864
1:2 14-bit 1.8V SSTU32864
tbd.
Raw Card
512 MB
1024 MB
1024 MB
2048 MB
2048 MB
HYB18T512800AC
HYB18T512800AF
A
B
HYB18T512800AC
HYB18T512800AF
HYB18T512400AC
HYB18T512400AF
C
HYB18T512400AC
HYB18T512400AF
tbd.
tbd.
HYB18T512400AC
HYB18T512400AF
tbd.
tbd.
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component data
sheet
1.4 Pin Definition and Function
Pin Name
A[13:0]
Description
Row Address Inputs
Pin Name
CB[7:0]
Description
DIMM ECC Check Bits
SDRAM low data strobes
A11, A[9:0]
A10/AP
Column Address Inputs 4)
DQS[8:0]
Column Address Input for Auto-
Precharge
DM[8:0] /
DQS[17:9]
SDRAM low data mask/
high data strobes
BA[1:0]
CK0
SDRAM Bank Selects
DQS[17:0]
SCL
SDRAM differential data strobes
Serial bus clock
Clock input
(positive line of differential pair)
CK0
Clock input
(negative line of differential pair)
SDA
Serial bus data line
RAS
Row Address Strobe
Column Address Strobe
Read/Write Input
Chip Selects 3)
SA[2:0]
VDD
slave address select
Power (+ 1.8 V)
CAS
WE
VREF
I/O reference supply
Ground
CS[1:0]
CKE[1:0]
ODT[1:0]
DQ[63:0]
VSS
Clock Enable 3)
VDDSPD
EEPROM power supply
Register and PLL control pin 2)
No connection
Active termination control lines 1) 3) RESET
Data Input/Output NC
1) Active termination only applies to DQ, DQS, DQS and DM signals
2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the
PLL will remain synchronized with the input clock
3) CS1, ODT1 and CKE1 are used on dual rank modules only
4) Column address A11 is used on modules based on x4 organised 512Mb DDR2 components only.
Data Sheet
Preliminary
4
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
1.5 Pin Configuration
PIN# Symbol
PIN#
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Symbol
VSS
PIN#
61
Symbol
A4
PIN#
181
182
183
184
Symbol
VDDQ
A3
1
VREF
VSS
2
DQ4
62
VDDQ
A2
3
DQ0
DQ5
63
A1
4
DQ1
VSS
64
VDD
VDD
5
VSS
DM0, DQS9
DQS9
VSS
KEY
KEY
6
DQS0
DQS0
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VSS
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
CK0
7
VSS
CK0
8
DQ6
VDD
VDD
9
DQ2
DQ7
NC
A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ3
VSS
VDD
VDD
VSS
DQ12
DQ13
VSS
A10/AP
BA0
BA1
DQ8
VDDQ
RAS
DQ9
VDDQ
WE
VSS
DM1, DQS10
DQS10
VSS
CS0
DQS1
DQS1
VSS
CAS
VDDQ
ODT0
A13
VDDQ
CS1
NC
RESET
NC
NC
ODT1
VDDQ
VSS
VDD
VSS
VSS
VSS
DQ14
DQ15
VSS
DQ36
DQ37
VSS
DQ10
DQ11
VSS
DQ32
DQ33
VSS
DQ20
DQ21
VSS
DM4, DQS13
DQS13
VSS
DQ16
DQ17
VSS
DQS4
DQS4
VSS
DM2, DQS11
DQS11
VSS
DQ38
DQ39
VSS
DQS2
DQS2
VSS
DQ34
DQ35
VSS
DQ22
DQ23
VSS
DQ44
DQ45
VSS
DQ18
DQ19
VSS
DQ40
DQ41
VSS
DQ28
DQ29
VSS
DM5, DQS14
DQS14
VSS
DQ24
DQ25
VSS
DQS5
DQS5
VSS
DM3, DQS12
DQS12
VSS
DQ46
DQ47
VSS
DQS3
DQS3
VSS
DQ42
DQ43
VSS
DQ30
DQ31
VSS
DQ52
DQ53
VSS
DQ26
DQ27
DQ48
DQ49
Data Sheet
Preliminary
5
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Pin Configuration (cont’d)
PIN# Symbol
PIN#
Symbol
CB4
PIN#
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
VSS
PIN#
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
NC
41
VSS
CB0
CB1
VSS
DQS8
DQS8
VSS
CB2
CB3
VSS
VDDQ
CKE0
VDD
NC
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
CB5
SA2
NC
VSS
NC
VSS
DM8, DQS17
DQS17
VSS
VSS
DM6, DQS15
DQS15
VSS
DQS6
DQS6
VSS
CB6
DQ54
DQ55
VSS
CB7
DQ50
DQ51
VSS
VSS
VDDQ
NC, CKE1
VDD
DQ60
DQ61
VSS
DQ56
DQ57
VSS
NC
DM7, DQS16
DQS16
VSS
NC
DQS7
DQS7
VSS
NC
VDDQ
A12
VDDQ
A11
DQ62
DQ63
VSS
A9
DQ58
DQ59
VSS
A7
VDD
VDD
A5
A8
VDDSPD
SA0
A6
SDA
SCL
SA1
1.6 Pin Locations
Front
120
240
pin
1
64
65
pin 121
185
184
Backside
240 pin Modules (MO-237)
Data Sheet
Preliminary
6
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
1.7 Registered DIMM Input/Output Functional Description
Type Polarity
Function
Symbol
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and the falling edge of CK. An on-board DLL circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
CK0, CK0
Input Cross point
CKE high activates and CKE low deactivates internal clock signals and device input buffers
Active High and output drivers of the SDRAMs. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
Input
Input
CKE[1:0]
CS[1:0]
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations con-
Active Low
tinue. The input signals also disable all outputs (except CKE and ODT) of the register(s) on
the DIMM when both inputs are high. When both CS[1:0] are high, all register outputs (except
CK, ODT and Chip select) remain in the previous state.
Active High On-Die Termination control signals
Input
Input
ODT[1:0]
RAS, CAS,
WE
When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to
Active Low
be executed by the SDRAM.
DM[8:0]
Active High Masks write data when high, issued concurrently with input data.
Input
Input
-
Selects which internal SDRAM memory bank is activated
BA[1:0]
During Bank Activate command cycle, Address defines the row address. During a Read or
Write command cycle, Address defines the column address. In addition to the column
address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read
or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be
precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all
banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to
define which bank to precharge.
A[13:0]
-
Input
DQ[63:0],
CB[7:0]
I/O
I/O
-
Data and Check Bit Input /Output pins.
The data strobes, associated with one data byte, source with data transfer. In Write mode,
the data strobe is sourced by the controller and is centered in the data window. In Read
mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the
data window. DQS signals are complements, and timing is relative to the crosspoint of
respective DQS and DQS. If the module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed appropriately.
DQS[17:0],
DQS[17:0]
Cross point
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial
SPD EEPROM address range
-
-
-
-
Input
I/O
SA[2:0]
SDA
This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor
maybe connected from the SDA bus line to VDDSPD on the system planar to act as a pull-
up.
This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from
the SCL bus line to VDDSPD on the system planar to act as a pull-up.
Input
Input
SCL
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL.
When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the
register(s) will be set to low level. The PLL will remain synchronized with the input clock.
RESET
VDD, VSS
Supply
Supply
-
-
Power and ground for the DDR SDRAM input buffers and core logic.
Reference voltage for the SSTL-18 inputs.
V
REF
Serial EEPROM positive power supply, wired to a separated power pin at the connector
which supports from 1.7 Volt to 3.6 Volt.
Supply
-
V
DDSPD
Note: CS1, ODT1 and CKE1 are used on dual rank modules only.
Data Sheet
Preliminary
7
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
2.0 Block Diagrams
2.1 One Rank 64M x 72 (512 MByte) DDR2 SDRAM DIMM Module (x8 components)
HYS72T64000[G/H] on Raw Card A
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
DM4/DQS13
NU/
DM/
NU/
RDQS
DM/
RDQS
CS DQS DQS
CS DQS DQS
DQS9
RDQS RDQS
DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS5
DQS1
DQS5
DQS1
DM5/DQS14
DM1/DQS10
NU/
DM/
NU/
DM/
CS DQS DQS
CS DQS DQS
DQS10
DQS14
RDQS RDQS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS6
DQS0
DQS6
DM2/DQS11
DM6/DQS15
NU/
DM/
NU/
DM/
DQS
DQS DQS
CS DQS
D2
CS
DQS11
DQS15
RDQS RDQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
DM7/DQS16
NU/
DM/
CS DQS DQS
NU/
DM/
CS DQS DQS
DQS12
RDQS RDQS
DQS16
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
DQS8
DQS8
V
DM8/DQS17
Serial PD
DDSPD
NU/
RDQS
DM/
RDQS
Serial PD
CS DQS DQS
DQS17
SCL
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
V
V
DD, DDQ
VREF
SDA
D0 - D8
D0 - D8
D8
WP A0
A1 A2
V
SS
SA0 SA1
SA2
D0 - D8
1:1
RS0 -> C S : SDRAMs D0-D8
CK0
CK 0
PCK0-PCK6,PCK8,PCK9
PCK8,PCK9
CK : SDRAMs D0-D8
CK : SDRAMs D0-D8
CS0 *
R
E
G
I
S
T
E
R
RBA0 -RBA1-> BA 0-BA1 : SDRAMs D0-D8
RA0 -RA 13-> A0 -A13: SDRA Ms D0 -D8
P
L
L
BA0-BA1
A0 -A13
PCK0-PCK6,
RAS
CAS
WE
RRAS -> RAS : SDRAMs D0- D8
RCAS -> C AS: SDRAMs D0-D8
RW E -> WE: SDRAMs D0-D8
PCK7
-> CK : Register
OE
RESET
PCK7 > CK : Register
CKE0
ODT0
RCK E0 -> CKE : SDR A
RODT0 -> ODT 0: SDRAMs D0-D8
D0-D8
Notes:
RESET
PCK7
PCK 7
RST
1. DQ-to-I/O wiring may be changed within a byte
2. Unless otherwise noted, resistor values are 22 Ohms
*) CS0 connects to DCS and VDD connects to CSR on the Registers
Data Sheet
Preliminary
8
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Block Diagrams (cont’d)
2.2 128M x 72 (1GByte) two rank DDR2 SDRAM DIMM Modules (x8 components)
HYS72T128020[G/H] on Raw Card B
RS1
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
DM4/DQS13
NU/
DM/
NU/
DM/
NU/
DM/
NU/
DM/
CS DQS DQS
CS
DQS DQS
CS DQS DQS
CS DQS DQS
DQS9
DQS13
RDQS RDQS
RDQS RDQS
RDQS RDQS
RDQS RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D9
D0
D4
D13
DQS5
DQS1
DQS5
DQS1
DM5/DQS14
DM1/DQS10
NU/
RDQS
DM/
RDQS
NU/
DM/
NU/
RDQS
DM/
RDQS
NU/
RDQS
DM/
RDQS
CS DQS DQS
CS DQS DQS
CS
DQS DQS
CS DQS DQS
DQS14
DQS10
RDQS RDQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
D10
D5
D14
D1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS6
DQS0
DQS6
DM2/DQS11
DM6/DQS15
NU/
DM/
NU/
RDQS
DM/
RDQS
NU/
DM/
CS DQS DQS
NU/
RDQS
DM/
RDQS
CS DQS DQS
CS
DQS DQS
CS DQS DQS
RDQS RDQS
DQS15
DQS11
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D11
D6
D15
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
DM7/DQS16
NU/
DM/
NU/
RDQS
DM/
RDQS
NU/
RDQS
DM/
RDQS
CS DQS
D3
DQS
CS
DQS DQS
NU/
DM/
CS DQS DQS
CS DQS DQS
DQS12
RDQS RDQS
DQS16
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
D7
D16
DQS8
DQS8
V
Serial PD
DDSPD
DM0/DQS17
NU/
DM/
NU/
RDQS
DM/
RDQS
CS DQS DQS
CS DQS DQS
DQS17
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
V
V
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DD, DDQ
D0 - D17
D0 - D17
VREF
D8
D17
V
SS
D0 - D17
Serial PD
SCL
SDA
1:2
WP A0
SA0 SA1 SA2
PCK0-PCK6, PCK8,PCK9
A1 A2
RS0 -> C S : SDRAMs D0-D8
RS1 -> C S : SDRAMs D9-D17
CS0 *
CS1 *
R
E
G
I
S
T
E
R
A0-BA1 : SDRAMs D0-D17
RBA0 -RBA1-> B
RA0 -RA 13-> A0 -A13: SDRA Ms D0-D17
RRAS -> RAS : SDRAMs D0-D17
RCAS -> C AS: SDRAMs
RW E -> WE: SDRAMs
BA 0-BA1
A0 -A13
CK
: SDRAMs D0-D17
CK 0
CK 0
RAS
CAS
WE
P
L
L
CK : SDRAMs D0-D17
PCK0-PCK6,
PCK8,PCK9
D0-D17
D0-D17
:
CKE0
RCK E0 -> CKE
RCK E1 -> CKE
:
SDRAMs D0-D8
SDRAMs D9-D17
PCK7 -> CK Register
PCK7 > CK
CKE1
ODT0
ODT1
:
RESET
OE
: Register
D0-D8
RODT0 -> ODT : SDRAMs
RODT1 -> ODT :SDRAMs D9-D17
RESET
PCK7
PCK 7
RST
DQ-to-I/O wiring may be changed within a byte
DQ/DQS/DQS, adress and control resistors are 22 Ohms
*) CS0 connects to CRS, CS1 connects to CSR on a Register. CS1 connects to DCS and CS0 connects to CSR on another Register.
RESET, PCK7 and PCK7 connect to bother Registers. Other signals connect to one of two Registers.
Data Sheet
Preliminary
9
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Block Diagrams (cont’d)
2.3 One Rank 128M x 72 (1 GByte) DDR2 SDRAM DIMM Modules (x4 components)
HYS72T128000[G/H] on Raw Card C
VSS
RS0
DQS0
DQS0
DQS9
DQS9
DM
DM
CS DQS DQS
D0
CS DQS DQS
D9
DQ0
DQ1
DQ2
DQ4
DQ5
DQ6
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ3
DQ7
DQS1
DQS0
DQS10
DQS10
DM
DM
DQS
CS DQS
D1
CS
DQS DQS
DQ8
DQ9
DQ10
DQ12
DQ13
DQ14
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D10
DQ11
DQ15
DQS2
DQS2
DQS11
DQS11
DM
DM
CS DQS DQS
D2
CS DQS DQS
D11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS12
DQS12
DQS3
DQS3
DM
DM
CS DQS DQS
D3
CS DQS DQS
D12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS13
DQS13
DQS4
DQS4
DM
DM
DQS
CS DQS
D4
CS
DQS DQS
DQ32
DQ33
DQ34
DQ36
DQ37
DQ38
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D13
DQ35
DQ39
DQS5
DQS5
DQS14
DQS14
DM
DM
CS DQS DQS
D5
CS DQS DQS
D14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS15
DQS15
DQS6
DQS6
DM
DM
CS DQS DQS
D6
CS DQS DQS
D15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS7
DQS7
DQS16
DQS16
DM
DM
CS DQS DQS
D7
CS DQS DQS
D16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS8
DQS8
DQS17
DQS17
DM
DM
CS DQS DQS
D8
CS DQS DQS
D17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
V
Serial PD
Serial PD
DDSPD
1:2
SCL
RS0 -> C S : SDRAMs D0-D17
CS0 *
BA0-BA1
A0 -A13
R
E
SDA
V
A 0-BA1 : SDRAMs
V
RBA0 -RBA1-> B
DD, DDQ
VREF
D0 - D17
D0 - D17
WP A0
A1 A2
G
RA0 -RA13-> A0 -A 13: SDR AMs D0-D17
RRAS -> RAS : SDRAMs D0-D17
I
S
T
E
R
RAS
CAS
WE
SA0 SA1 SA2
V
RCAS -> C AS: SDRAMs
RW E -> WE: SDRAMs
SS
D0-D17
D0-D17
D0-D17
D0 - D17
CKE0
RCKE0 -> CKE
:
SDRAMs
P
L
L
CK 0
CK 0
PCK0-PCK6, PCK8,PCK9
PCK0-PCK6, PCK8,PCK9
CK
: SDRAMs D0-D17
ODT0
RESET
PCK7
RODT0 ->
: SDRAMs D0-D17
ODT
CK : SDRAMs D0-D17
RST
PCK 7
: Register
PCK7 -> CK
RESET
OE
*) CS0 connects to DCS of Register 1 and CSR of Register 2,
CSR of Register 1 and DCS of Register 2 connects to VDD
**) RESET, PCK7 and PCK7 connet to both Registers.
Other signals connect to one of two Registers.
PCK7 > CK : Register
DQ-to-I/O wiring may be changed within per nibble
Unless otherwise noted, resistor values are 22 Ohms
Data Sheet
Preliminary
10
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Block Diagrams (cont’d)
2.4 256M x 72 (2 GByte) two rank DDR2 SDRAM DIMM Modules (x4 components)
HYS72T256020[G/H] / HYS72T256220[G/H]
RS1
VSS
RS0
DQS0
DQS0
DQS9
DQS9
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DQ0
DQ1
DQ2
DQ4
DQ5
DQ6
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
DQ3
D0-0
D0-1
I/O 3
I/O 3
D9-0
I/O 3
D9-1
I/O 3
DQ7
DQS1
DQS1
DQS10
DQS10
DM
DQS DQS
DM CS DQS DQS
CS
DM CS DQS DQS
DM CS DQS DQS
DQ8
DQ9
DQ10
DQ12
DQ13
DQ14
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
DQ11
D1-0
D1-1
I/O 3
DQ15
D10-0
D10-1
I/O 3
I/O 3
DQS2
DQS2
DQS11
DQS11
DM CS DQS DQS
DM CS DQS DQS
DM
DQS DQS
DM
CS
CS
DQS DQS
DQ20
DQ21
DQ22
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
DQ16
DQ17
DQ18
DQ19
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
D2-0
I/O 3
D2-1
DQ23
D11-0
D11-1
DQS3
DQS3
DQS12
DQS12
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DQ24
DQ25
DQ26
DQ27
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
DQ28
DQ29
DQ30
I/O 3
D3-0
I/O 3
D3-1
D12-0
D12-1
I/O 3
I/O 3
DQ31
DQS4
DQS4
DQS13
DQS13
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DQ32
DQ33
DQ34
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
DQ36
DQ37
DQ38
DQ39
D4-0
D4-1
DQ35
I/O 3
I/O 3
D13-0
D13-1
I/O 3
I/O 3
DQS5
DQS5
DQS14
DQS14
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DQ40
DQ41
DQ42
DQ43
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
D5-0
D5-1
I/O 3
I/O 3
D14-0
D14-1
I/O 3
I/O 3
DQS6
DQS6
DQS15
DQS15
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
DQ48
DQ49
DQ50
DQ51
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
DQ52
DQ53
DQ54
DQ55
D6-0
D6-1
I/O 3
I/O 3
D15-0
D15-1
I/O 3
I/O 3
DQS7
DQS7
DQS16
DQS16
DM CS DQS DQS
DM CS DQS DQS
DM
DQS DQS
DM
CS
CS
DQS DQS
DQ56
DQ57
DQ58
DQ59
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ60
DQ61
DQ62
D7-0
D7-1
I/O 3
I/O 3
D16-0
D16-1
DQ63
DQS8
DQS8
DQS17
DQS17
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
CB0
CB1
CB2
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 0
I/O 1
I/O 2
D8-0
D8-1
CB3
I/O 3
I/O 3
D17-0
SDA
D17-1
I/O 3
I/O 3
V
Serial PD
Serial PD
DDSPD
1:2
SCL
D0-0 ~ D17-0
D0-1 ~ D17-1
RS0 -> C S : SDRAMs
RS1 -> C S : SDRAMs
CS0 *
CS1 *
V
V
DD, DDQ
VREF
D0 - D17
D0 - D17
WP A0
A1 A2
R
E
G
I
S
T
E
R
BA 0-BA1
A0 -A13
RBA0 -RBA1-> BA 0-BA1 : SDRAMs D0~D17
RA0 -RA 13-> A0 -A 13: SDRA Ms D0~D17
SA0 SA1 SA2
V
SS
D0 - D17
CK
: SDRAMs D0-D17
RAS
CAS
WE
CKE0
CKE1
D0~D17
RRA S -> RAS : SDRAMs
RCAS -> C A S: SDRAMs
RW E -> WE : SDRAMs
RCK E0 -> CKE :SDRAMs
CK 0
CK 0
PCK0-PCK6, PCK8,PCK9
D0~D17
D0~D17
D0-0 ~ D17-0
P
L
L
CK : SDRAMs D0-D17
PCK0-PCK6, PCK8,PCK9
RCKE1 -> CKE
:
D0-1 ~ D17-1
SDRAMs
: SDRAMs D0-0 ~ D17-0
PCK7 -> CK
: Register
: Register
> CK
RESET
OE
ODT0
ODT1
RODT0 ->
RODT1 ->
ODT
PCK7
D0-1 ~ D17-1
ODT :SDRAMs
Notes:
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistors values are 22 Ohms
RESET
PCK7
PCK7
RST
*) CS0 connects to CRS, CS1 connects to CSR on a Register. CS1 connects to DCS and CS0 connects to CSR on another Register.
RESET, PCK7 and PCK7 connect to bother Registers. Other signals connect to one of two Registers.
Data Sheet
Preliminary
11
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
3.0 Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
2.3
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
Voltage on VDD Q relative to VSS
Storage temperature range
VIN, VOUT
VDD
– 0.5
– 1.0
– 0.5
-55
V
V
2.3
VDDQ
2.3
TSTG
+100
oC
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
3.1 Operating Temperature Range
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
TOPR
0
0
+55
+95
oC
TCASE
oC
1 - 4
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2.
2. Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85oC case temperature before initiating self-refresh operation.
3.2 Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit
Notes
min.
1.7
nom.
max.
1.9
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
EEPROM Supply Voltage
DC Input Logic High
VDD
1.8
V
V
-
VDDQ
VREF
VDDSPD
VIH (DC)
VIL (DC)
IL
1.7
1.8
1.9
1)
2)
0.49 x VDDQ
1.7
0.5 x VDDQ
0.51 x VDDQ
3.6
V
–
–
–
–
V
VREF + 0.125
– 0.30
– 5
VDDQ + 0.3
VREF – 0.125
5
V
DC Input Logic Low
V
In / Output Leakage Current
µA
3)
1
2
3
Under all conditions, VDDQ must be less than or equal to VDD
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations in VDDQ
For any pin on the DIMM connector under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V.
.
Data Sheet
Preliminary
12
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
4.0 IDD Specifications and Conditions
4.1 512 MByte Registered Module HYS72T64000[G/H] (one rank, nine components x8)
512 MByte HYS72T64000[G/H]
Symbol Parameter / Condition
IDD0
Operating Current
IDD1
PC2-3200R “-5”
PC2-4300R “-3.7”
max.
745
790
286
538
475
367
295
565
880
925
1330
304
36
max.
918
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Operating Current
1008
369
Precharge PD Standby Current
Precharge Standby Current
Precharge Quiet Standby Current
Active PD Standby Current
IDD2P
IDD2N
IDD2Q
IDD3P(0)
639
603
477
IDD3P(1) LP Active PD Standby Current
378
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
Active Standby Current
693
Operating Current Burst Read
Operating Current Burst Write
Auto-Refresh Current (tRFCmin.)
Auto-Refresh Current (tREFI)
Self-Refresh Current
1143
1188
1503
387
36
IDD7
Operating Current
1420
1593
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
4.2 1024 MByte Registered Module HYS72T128020[G/H] (two ranks, 18 components x8)
1024 MByte HYS72T128020[G/H]
Symbol Parameter / Condition
IDD0
Operating Current
IDD1
PC2-3200R “-5”
max.
899
PC2-4300R “-3.7”
max.
Unit Note
1111
1201
562
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1, 2
1, 2
1, 3
1, 3
1, 3
1, 3
1, 3
1, 3
1, 2
1, 2
1, 2
1, 3
1, 3
1, 2
Operating Current
944
IDD2P
IDD2N
IDD2Q
Precharge PD Standby Current
Precharge Standby Current
Precharge Quiet Standby Current
440
944
1210
1030
778
818
IDD3P(0) Active PD Standby Current
IDD3P(1) LP Active PD Standby Current
602
458
580
Active Standby Current
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
998
1210
1336
1381
1696
598
Operating Current Burst Read
Operating Current Burst Write
Auto-Refresh Current (tRFCmin.)
Auto-Refresh Current (tREFI)
Self-Refresh Current
1034
1079
1484
476
72
72
Operating Current
IDD7
1574
1786
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
Data Sheet
Preliminary
13
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
4.3 1024 Mbyte Registered Module HYS72T128000[G/H] (one rank, 18 components x4)
1024 MByte HYS72T128000[G/H]
Symbol Parameter / Condition
IDD0
Operating Current
IDD1
PC2-3200R “-5”
max.
1358
1448
440
PC2-4300R “-3.7”
max.
Unit Note
1660
1840
562
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Operating Current
IDD2P
IDD2N
IDD2Q
Precharge PD Standby Current
Precharge Standby Current
Precharge Quiet Standby Current
944
1210
1030
778
818
IDD3P(0) Active PD Standby Current
IDD3P(1) LP Active PD Standby Current
602
458
580
Active Standby Current
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
998
1210
2110
2200
2830
598
Operating Current Burst Read
Operating Current Burst Write
Auto-Refresh Current (tRFCmin.)
Auto-Refresh Current (tREFI)
Self-Refresh Current
1628
1718
2528
476
72
72
Operating Current
IDD7
2708
3010
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
4.4 2048 MByte Registered Module HYS72T256[0/2]20[G/H] (two ranks, 36 components x4)
2048 MByte HYS72T256020[G/H]
PC2-3200R “-5”
PC2-4300R “-3.7”
2048 MByte HYS72T256220[G/H]
Symbol Parameter / Condition
IDD0
Operating Current
IDD1
max.
1394
1520
512
max.
1696
1912
623
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1, 2
1, 2
1, 3
1, 3
1, 3
1, 3
1, 3
1, 3
1, 2
1, 2
1, 2
1, 3
1, 3
1, 2
Operating Current
IDD2P
IDD2N
IDD2Q
Precharge PD Standby Current
Precharge Standby Current
Precharge Quiet Standby Current
1520
1268
836
1930
1570
1066
670
IDD3P(0) Active PD Standby Current
IDD3P(1) LP Active PD Standby Current
548
Active Standby Current
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
1628
1700
1790
2600
584
1930
2182
2272
2902
706
Operating Current Burst Read
Operating Current Burst Write
Auto-Refresh Current (tRFCmin.)
Auto-Refresh Current (tREFI)
Self-Refresh Current
144
144
Operating Current
IDD7
2780
3082
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
Data Sheet
Preliminary
14
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
4.5 IDD Measurement Conditions
(VDD = 1.8V ± 0.1V; VDDQ = 1.8V ± 0.1V)
Symbol
Parameter/Condition
Operating Current - One bank Active - Precharge
tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control
inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,tRCD = tRCDmin.,AL = 0, CL = CLmin.;
CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
IDD1
IDD2P
IDD2N
Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.;
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.;
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.;
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2Q
Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
IDD3P(0)
IDD3P(1)
IDD3N
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax; tRP = tRPmin.,CKE is HIGH; CS is high between
valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA.
IDD4R
IDD4W
Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
Burst Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH
IDD5B
IDD5D
IDD6
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current: CKE ≤ 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING, Data bus
inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max.
All Bank Interleave Read Current:
1. All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address
bus inputs are STABLE during DESELECTS. Iout = 0mA.
2. Timing pattern:
IDD7
- DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
- DDR2 -533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
- DDR2 -667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Notes:
1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
2. Definitions for IDD:
LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min.
STABLE is defined as inputs are stable at a HIGH or LOW level.
FLOATING is defined as inputs are VREF = VDDQ / 2.
SWITCHING is defined as:
inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and
inputs changing between HIGH and LOW every other clock (once per cycle) for DQ signals not including mask or strobes.
3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
4. RESET signal is high for all currents, except for IDD6 “Self Refresh”.
5. All current measurements includes Register and PLL current consumption.
Data Sheet
Preliminary
15
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
4.5 IDD Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
PC2-3200R “-5“
PC2-4300R “-3.7”
Unit
Parameter
Symbol
3-3-3
3
4-4-4
4
CAS Latency
CLmin
tCKmin
tCK
ns
ns
ns
ns
ns
ns
ns
µs
Clock Cycle Time
5
3.75
15
Active to Read or Write delay
tRCDmin
15
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
Active to Precharge Command
tRCmin
60
60
x4 & x8 tRRDmin
tRASmin
7.5
45
7.5
45
Precharge Command Period
tRPmin
15
15
Auto-Refresh to Active / Auto-Refresh command period
Average periodic Refresh interval
tRFCmin
105
7.8
105
7.8
tREFI
4.6 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The cur-
rent consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long
a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State min. typ. max. Unit
A6 = 0, A2 = 1
5
6
3
7.5 mA/DQ
3.75 mA/DQ
15 mA/DQ
7.5 mA/DQ
Enabled ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are FLOATING
IODTO
IODTT
A6 = 1, A2 = 0 2.5
A6 = 0, A2 = 1 10
12
6
Active ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
A6 = 1, A2 = 0
5
note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
Preliminary
16
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
5.0 Electrical Characteristics & AC Timings
5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only)
-5
-3.7
DDR2-400
DDR2-533
Symbol
Parameter
Unit
Min
Max
Min
Max
DQ output access time from CK / CK
DQS output access time from CK / CK
CK, CK high-level width
− 600
− 500
0.45
+ 600
-500
−450
0.45
0.45
+500
ps
ps
tAC
tDQSCK
tCH
+ 500
0.55
0.55
+450
0.55
0.55
tCK
tCK
CK, CK low-level width
0.45
tCL
Clock Half Period
min. (tCL, tCH)
min. (tCL, tCH)
tHP
CL = 3
Clock cycle time
5000
5000
600
8000
8000
-
5000
3750
600
8000
8000
-
ps
ps
ps
tCK
CL = 4 & 5
tIS
tIH
Address and control input setup time
Address and control input hold time
DQ and DM input setup time
600
400
-
600
350
-
ps
ps
ps
tCK
tCK
ps
ps
ps
tDS
tDH
tIPW
-
-
DQ and DM input hold time
400
-
350
-
Control and Addr. input pulse width (each input)
0.6
-
0.6
-
tDIPW DQ and DM input pulse width (each input)
tHZ
Data-out high-impedance time from CK / CK
0.35
-
0.35
-
-
tACmax
tACmax
tACmax
-
tACmax
tACmax
tACmax
tLZ(DQ) DQ low-impedance from CK / CK
tLZ(DQS) DQS low-impedance from CK / CK
2*tACmin
tACmin
2*tACmin
tACmin
DQS-DQ skew
tDQSQ
-
350
-
300
ps
ps
(for DQS & associated DQ signals)
Data hold skew factor
-
450
-
-
400
-
tQHS
tQH
Data Output hold time from DQS
tHP-tQHS
tHP-tQHS
WL
WL
WL
WL
Write command to 1st DQS latching transition
DQS input low (high) pulse width (write cycle)
tCK
tCK
tCK
tDQSS
tDQSL,H
tDSS
-0.25
+0.25
-0.25
+0.25
0.35
0.2
-
-
0.35
0.2
-
-
DQS falling edge to CLK setup time
(write cycle)
DQS falling edge hold time from CLK
(write cycle)
tDSH
0.2
-
0.2
-
tCK
Mode register set command cycle time
Write preamble
2
-
-
2
-
-
tCK
tCK
tCK
tCK
tCK
ns
tMRD
tWPRE
tWPST
tRPRE
tRPST
tRAS
0.25
0.40
0.9
0.25
0.40
0.9
Write postamble
0.60
1.1
0.60
70000
-
0.60
1.1
0.60
70000
-
Read preamble
Read postamble
0.40
45
0.40
45
Active to Precharge command
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command period
60
60
ns
tRC
105
-
105
-
ns
tRFC
Data Sheet
Preliminary
17
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
-5
-3.7
DDR2-400
DDR2-533
Symbol
Parameter
Unit
Min
Max
Min
Max
Active to Read or Write delay (with and without Auto-Pre-
charge) delay
15
15
-
15
15
-
ns
ns
ns
tRCD
tRP
Precharge command period
-
-
-
-
Active bank A to Active bank
B command
x4 & x8
(1k page size)
tRRD
7.5
7.5
tCCD CAS A to CAS B Command Period
2
15
-
-
-
-
-
2
15
-
-
-
-
-
tCK
ns
tWR
Write recovery time
Auto precharge write recovery + precharge time
tDAL
WR+tRP
10
WR+tRP
7.5
tCK
ns
tWTR Internal write to read command delay
tRTP
Internal read to precharge command delay
7.5
7.5
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
2
6 - AL
2
-
-
-
2
6 - AL
2
-
-
-
tCK
tCK
tCK
Exit active power-down mode to read command
(slew exit, lower power)
tXARDS
Exit precharge power-down to any valid command (other
than NOP or Deselect)
tXP
tXSRD Exit Self-Refresh to read command
200
-
-
200
-
-
tCK
ns
tXSNR Exit Self-Refresh to non-read command
tRFC + 10
tRFC + 10
tCKE
tOIT
CKE minimum high and low pulse width
OCD drive mode output delay
3
0
-
3
0
-
tCK
ns
12
12
Minimum time clocks remain ON after CKE asynchro-
nously drops low
tIS+tCK
+tIH
tIS+tCK
+tIH
tDELAY
tREFI
-
-
ns
µs
0oC - 85oC
-
-
7.8
3.9
-
-
7.8
3.9
Average Periodic Refresh
Interval
85oC - 95oC
1. For details and notes see the relevant INFINEON component datasheet
2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code
for these parameters.
5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
min.
2
max.
2
Units
ODT turn-on delay
tAOND
tAON
tCK
DDR2-400/533
DDR2-667
tAC(min)
tAC(min)
tAC(min) + 2 ns
tAC(max) + 1 ns
tAC(max) + 0.7 ns
2 tCK + tAC(max) + 1 ns
ODT turn-on
ns
tAONPD ODT turn-on (Power-Down Modes)
tAOFD ODT turn-off delay
ns
tCK
ns
ns
tCK
tCK
2.5
2.5
tAOF
ODT turn-off
tAC(min)
tAC(max) + 0.6 ns
tAOFPD ODT turn-off delay (Power-Down Modes)
tANPD ODT to Power Down Mode Entry Latency
tAXPD ODT Power Down Exit Latency
tAC(min) + 2 ns
2.5 tCK + tAC(max) + 1 ns
3
8
-
-
Data Sheet
Preliminary
18
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
6.0 Serial Presence Detect Codes for Registered Modules
6.1 SPD Codes for PC2–4300R (–3.7)
Product Type
Organization
2 GByte
1 GByte
1 GByte
512 MB
×72
×72
×72
×72
2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
Label Code
PC2–4300R–444
Jedec SPD Revision
Byte# Description
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
1
08
08
08
08
2
08
08
08
08
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
0E
0B
61
0E
0B
60
0E
0A
61
0E
0A
60
4
5
6
48
48
48
48
7
Not used
00
00
00
00
8
Interface Voltage Level
05
05
05
05
9
t
CK @ CLmax (Byte 18) [ns]
3D
50
3D
50
3D
50
3D
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
02
02
02
02
82
82
82
82
04
04
08
08
04
04
08
08
00
00
00
00
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
Not used
0C
04
0C
04
0C
04
0C
04
38
38
38
38
00
00
00
00
DIMM Type Information
DIMM Attributes
01
01
01
01
07
05
05
04
Component Attributes
01
01
01
01
t
t
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
CK @ CLmax -2 (Byte 18) [ns]
AC SDRAM @ CLmax -2 [ns]
RP.min [ns]
3D
50
3D
50
3D
50
3D
50
50
50
50
50
60
60
60
60
3C
1E
3C
1E
3C
1E
3C
1E
RRD.min [ns]
Data Sheet
Preliminary
19
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
1 GByte
1 GByte
512 MB
×72
×72
×72
×72
2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
Label Code
PC2–4300R–444
Jedec SPD Revision
Byte# Description
Rev. 1.1
HEX
3C
2D
01
Rev. 1.1
HEX
3C
2D
01
Rev. 1.1
HEX
3C
2D
80
Rev. 1.1
HEX
3C
2D
80
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
t
t
RCD.min [ns]
RAS.min [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
25
25
25
25
37
37
37
37
10
10
10
10
DH.min [ns]
22
22
22
22
WR.min [ns]
3C
1E
1E
00
3C
1E
1E
00
3C
1E
1E
00
3C
1E
1E
00
WTR.min [ns]
RTP.min [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.min [ns]
00
00
00
00
3C
69
3C
69
3C
69
3C
69
RFC.min [ns]
CK.max [ns]
80
80
80
80
DQSQ.max [ns]
QHS.max [ns]
1E
28
1E
28
1E
28
1E
28
PLL Relock Time
CASE.max Delta / ∆T4R4W Delta
0F
51
0F
51
0F
51
0F
51
T
Psi(T-A) DRAM
78
78
78
78
∆T0
3E
22
3E
22
3E
22
3E
22
∆T2N (UDIMM) or ∆T2Q (RDIMM)
∆T2P
∆T3N
∆T3P.fast
∆T3P.slow
∆T4R / ∆T4R4W Sign
∆T5B
1E
1E
24
1E
1E
24
1E
1E
24
1E
1E
24
17
17
17
17
34
34
34
34
1E
20
1E
20
1E
20
1E
20
∆T7
Psi(ca) PLL
Psi(ca) REG
∆TPLL
C4
8C
61
C4
8C
61
C4
8C
61
C4
8C
61
Data Sheet
Preliminary
20
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
1 GByte
1 GByte
512 MB
×72
×72
×72
×72
2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
Label Code
PC2–4300R–444
Jedec SPD Revision
Byte# Description
Rev. 1.1
HEX
78
Rev. 1.1
HEX
78
Rev. 1.1
HEX
78
Rev. 1.1
HEX
78
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
∆TREG / Toggle Rate
SPD Revision
11
11
11
11
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2)
JEDEC ID Code of Infineon (3)
JEDEC ID Code of Infineon (4)
JEDEC ID Code of Infineon (5)
JEDEC ID Code of Infineon (6)
JEDEC ID Code of Infineon (7)
JEDEC ID Code of Infineon (8)
Module Manufacturer Location
Product Type, Char 1
8E
C1
00
8B
C1
00
12
10
C1
00
C1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
xx
xx
xx
xx
37
37
37
37
Product Type, Char 2
32
32
32
32
Product Type, Char 3
54
54
54
54
Product Type, Char 4
32
31
31
36
Product Type, Char 5
35
32
32
34
Product Type, Char 6
36
38
38
30
Product Type, Char 7
30
30
30
30
Product Type, Char 8
32
30
32
30
Product Type, Char 9
30
30
30
47 / 48
52
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
47 / 48
52
47 / 48
52
47 / 48
52
33
33
33
33
2E
37
2E
37
2E
37
2E
37
41
41
41
41
20
20
20
20
20
20
20
20
20
20
20
20
20
0x
2x
2x
2x
xx
xx
xx
xx
Data Sheet
Preliminary
21
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
1 GByte
1 GByte
512 MB
×72
×72
×72
×72
2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
Label Code
PC2–4300R–444
Jedec SPD Revision
Byte# Description
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
93
94
95
96
97
98
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
Not used
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
99 -
127
00
00
00
00
Data Sheet
Preliminary
22
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
6.2 SPD Codes for PC2–3200R (–5)
Product Type
Organization
2 GByte
2 GByte
1 GByte
1 GByte
512 MB
×72
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
Label Code
PC2–3200R–333
Jedec SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
0
Programmed SPD Bytes in
EEPROM
80
80
80
80
80
1
Total number of Bytes in
EEPROM
08
08
08
08
08
2
3
4
5
Memory Type (DDR2)
08
08
0E
0B
61
08
0E
0B
60
08
0E
0A
61
08
0E
0A
60
Number of Row Addresses
0E
Number of Column Addresses 0B
DIMM Rank and Stacking
Information
61
6
Data Width
48
00
05
50
48
00
05
50
60
48
00
05
50
60
48
00
05
50
60
48
00
05
50
60
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLmax (Byte 18) [ns]
10
AC SDRAM @ CLmax (Byte 18) 60
[ns]
11
Error Correction Support (non- 02
ECC, ECC)
02
02
02
02
12
13
14
15
16
17
Refresh Rate and Type
Primary SDRAM Width
82
04
82
04
04
00
0C
04
82
04
04
00
0C
04
82
08
08
00
0C
04
82
08
08
00
0C
04
Error Checking SDRAM Width 04
Not used
00
Burst Length Supported
0C
Number of Banks on SDRAM 04
Device
18
19
20
21
22
23
24
25
26
Supported CAS Latencies
Not used
38
00
01
07
01
50
60
50
60
38
00
01
07
01
50
60
50
60
38
00
01
05
01
50
60
50
60
38
00
01
05
01
50
60
50
60
38
00
01
04
01
50
60
50
60
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
CK @ CLmax -2 (Byte 18) [ns]
AC SDRAM @ CLmax -2 [ns]
Data Sheet
Preliminary
23
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
2 GByte
1 GByte
1 GByte
512 MB
×72
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
Label Code
PC2–3200R–333
Jedec SPD Revision
Byte# Description
Rev. 1.1
HEX
3C
1E
3C
2D
01
Rev. 1.1
HEX
3C
1E
3C
2D
01
Rev. 1.1
HEX
3C
1E
3C
2D
01
Rev. 1.1
HEX
3C
1E
3C
2D
80
Rev. 1.1
HEX
3C
1E
3C
2D
80
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
t
t
t
t
RP.min [ns]
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.min and tCS.min [ns]
AH.min and tCH.min [ns]
DS.min [ns]
35
35
35
35
35
47
47
47
47
47
15
15
15
15
15
DH.min [ns]
27
27
27
27
27
WR.min [ns]
3C
28
3C
28
3C
28
3C
28
3C
28
WTR.min [ns]
RTP.min [ns]
1E
00
1E
00
1E
00
1E
00
1E
00
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.min [ns]
00
00
00
00
00
3C
69
3C
69
3C
69
3C
69
3C
69
RFC.min [ns]
CK.max [ns]
80
80
80
80
80
DQSQ.max [ns]
QHS.max [ns]
23
23
23
23
23
2D
0F
2D
0F
2D
0F
2D
0F
2D
0F
PLL Relock Time
T
CASE.max Delta / ∆T4R4W Delta 51
51
51
51
51
Psi(T-A) DRAM
78
32
1D
78
78
78
78
∆T0
32
32
32
32
∆T2N (UDIMM) or ∆T2Q
1D
1D
1D
1D
(RDIMM)
51
52
53
54
55
56
57
58
∆T2P
∆T3N
∆T3P.fast
∆T3P.slow
∆T4R / ∆T4R4W Sign
∆T5B
1E
1B
1E
17
28
1B
1E
C4
1E
1B
1E
17
28
1B
1E
C4
1E
1B
1E
17
28
1B
1E
C4
1E
1B
1E
17
28
1B
1E
C4
1E
1B
1E
17
28
1B
1E
C4
∆T7
Psi(ca) PLL
Data Sheet
Preliminary
24
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
2 GByte
1 GByte
1 GByte
512 MB
×72
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
Label Code
PC2–3200R–333
Jedec SPD Revision
Byte# Description
Rev. 1.1
HEX
8C
Rev. 1.1
HEX
8C
59
Rev. 1.1
HEX
8C
59
Rev. 1.1
HEX
8C
59
Rev. 1.1
HEX
8C
59
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Psi(ca) REG
∆TPLL
∆TREG / Toggle Rate
SPD Revision
59
5C
5C
11
5C
11
5C
11
5C
11
11
Checksum of Bytes 0-62
C3
C3
C1
00
C0
C1
00
47
45
JEDEC ID Code of Infineon (1) C1
JEDEC ID Code of Infineon (2) 00
JEDEC ID Code of Infineon (3) 00
JEDEC ID Code of Infineon (4) 00
JEDEC ID Code of Infineon (5) 00
JEDEC ID Code of Infineon (6) 00
JEDEC ID Code of Infineon (7) 00
JEDEC ID Code of Infineon (8) 00
Module Manufacturer Location xx
C1
00
C1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
xx
xx
xx
xx
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
37
32
54
32
35
36
30
32
30
47 / 48
52
35
41
20
20
20
20
20
0x
37
37
37
37
32
32
32
32
54
54
54
54
32
31
31
36
35
32
32
34
36
38
38
30
32
30
30
30
32
30
32
30
30
30
30
47 / 48
52
47 / 48
52
47 / 48
52
47 / 48
52
35
35
35
35
41
41
41
41
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
0x
2x
2x
2x
Data Sheet
Preliminary
25
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
2 GByte
1 GByte
1 GByte
512 MB
×72
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
Label Code
PC2–3200R–333
Jedec SPD Revision
Byte# Description
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
Rev. 1.1
HEX
xx
92
93
Test Program Revision Code
Module Manufacturing Date
Year
xx
xx
xx
xx
xx
94
Module Manufacturing Date
Week
xx
xx
xx
xx
xx
95
96
97
98
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
Not used
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
99 -
127
Data Sheet
Preliminary
26
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
7.0 Package Outline
7.1 Raw Card A
Module Package
DDR2 Registered DIMM Modules Raw Card A
one physical rank, 9 components x8 organised
+ 0.15
-
133.35
2.7 max.
Front View
4.0
PLL
120
240
pin 1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Backside View
185
pin 121
184
3
3
Detail of Contacts B
5.0
Detail of Contacts A
0.75R
0.8 +- 0.05
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
Data Sheet
Preliminary
27
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
7.2 Raw Card B
Module Package
DDR2 Registered DIMM Modules Raw Card B
two one physical rank, 18 components x8 organised
+ 0.15
-
133.35
4.0 m ax.
Front View
4.0
PLL
120
pin
1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Backside View
pin 121
240
185
184
3
3
D etail of C ontacts
A
Detail of C ontacts
5.0
B
0.75R
+ 0.05
-
0.8
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
Data Sheet
Preliminary
28
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
7.3 Raw Card C
Module Package
DDR2 Registered DIMM Modules Raw Card C
one physical rank, 18 components x4 organised
+ 0.15
-
133.35
4.0 m ax.
Front View
4.0
PLL
120
pin
1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Backside View
pin 121
240
185
184
3
3
D etail of C ontacts
A
Detail of C ontacts
5.0
B
0.75R
+ 0.05
-
0.8
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
Data Sheet
Preliminary
29
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
7.4 Raw Card (tbd)
Module Package
DDR2 Registered DIMM Modules Raw Card (tbd.)
two physical ranks, 36 components x4 organised - planar version
+ 0.15
-
133.35
4.0 max.
Front View
4.0
120
240
pin 1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Backside View
185
pin 121
184
3
3
Detail of Contacts B
5.0
Detail of Contacts A
0.75R
0.8 -+ 0.05
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO237)
Data Sheet
Preliminary
30
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
8.0 Nomenclature (Modules & Components)
8.1 DDR2 DIMM Modules
1
2
3
4
5
6
7
8
9
10
11
H Y S 7 2
T
1 2 8
0
2
0
G
R
- 5
-A
Example:
0 = standard
2 = dual die package
1
2
INFINEON Prefix
HYS for DIMM Modules
7
8
Product Variations
Package
64 = Non-ECC Modules
72 = ECC Modules
G= BGA components
Module Data Width
R = Registered DIMMs
U = Unbuffered DIMMs
DL = Small Outline DIMMs
T = DDR2
DRAM Technology
Module Type
3
4
5
6
9
64 = 64 Mb
Memory Density per I/O 128 = 128 Mb
256 = 256 Mb
-5 = PC2-3200 (DDR2-400)
-3.7 = PC2-4300 (DDR2-533)
-3 = PC2-5400 (DDR2-667)
10 Speed Grade
11 Die Revision
A = 1st Generation
B = 2nd Generation
C = 3rd Generation
Raw Card Generation
0 = first generation
Multiplying “Memory Density per I/O” with “Module Data Width”
and dividing by 8 for Non-ECC and 9 for ECC modules gives the
overall module memory density in MBytes.
Number of Memory
Ranks
0 = One Rank
2 = Two Ranks
8.2 DDR2 Memory Components
1
2
3
4
5
6
7
8
9
H Y B 1 8
T
5 1 2 4 0
0
A
- 5
C
Example:
INFINEON
Component Prefix
0 = standard
2 = dual die package
1
2
HYB for DRAM Components
18 = 1.8 V Power Supply
6
7
Product Variations
Die Revision
A = 1st Generation
B = 2nd Generation
C = 3rd Generation
Power Supply Voltage
DRAM Technology
Memory Density
C = BGA package
F = BGA package (lead and
halogen free)
3
4
5
T = DDR2
8
9
Package Type
Speed Grade
256 = 256 Mb
512 = 512 Mb
1G = 1024Mb
-5 =...DDR2-400
-3.7 =.DDR2-533
-3 =...DDR2-667
40 = x4, 4 data in/outputs
80 = x8, 8 data in/outputs
16 = x16, 16 data in/outputs
Memory Organisation
Data Sheet
Preliminary
31
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Data Sheet
Preliminary
32
Rev. 0.85, 2004-04
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