HYS72D64020GR-8-B [INFINEON]
2.5 V 184-pin Registered DDR-I SDRAM Modules; 2.5 V 184针注册DDR- SDRAM我模块
| 型号： | HYS72D64020GR-8-B |
| 厂家： | 
Infineon |
| 描述： | 2.5 V 184-pin Registered DDR-I SDRAM Modules |
| 文件： | 总23页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
2.5 V 184-pin Registered DDR-I SDRAM Modules
256MB, 512MB &1GByte Modules
PC1600 & PC2100
Preliminary Datasheet revision 0.91
•
184-pin Registered 8-Byte Dual-In-Line
DDR-I SDRAM Module for PC and Server
main memory applications
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Re-drive for all input signals using register
and PLL devices.
•
•
One bank 32M × 72, 64M x 72, and two bank
64M x 72 and 128M × 72 organization
•
•
Serial Presence Detect with E2PROM
JEDEC standard Double Data Rate
Synchronous DRAMs (DDR-I SDRAM) with a
single + 2.5 V (± 0.2 V) power supply
Jedec standard MO-206 form factor:
133.35 mm (nom.) × 43.18 mm (nom.) × 4.00
mm (max.)
•
•
Built with 256Mbit DDR-I SDRAMs in 66-
Lead TSOPII package
(6,80 mm max. with stacked components)
•
•
Jedec standard reference layout:
Raw Cards A, B and C
Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
Gold plated contacts
•
Performance:
-7
-8
Unit
Component Speed Grade
Module Speed Grade
DDR266A DDR200
PC2100
143
PC1600
125
fCK
fCK
Clock Frequency (max.) @ CL = 2.5
Clock Frequency (max.) @ CL = 2
MHz
MHz
133
100
Description
The HYS 72Dxx0x0GR are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs)
organized as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1GB). The memory array is
designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock
distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM
timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes
are programmed with configuration data and the second 128 bytes are available to the customer.
INFINEON Technologies
1
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Ordering Information
Type
Compliance Code
Description
SDRAM
Technology
PC2100 (CL=2):
HYS 72D32000GR-7-B
HYS 72D64000GR-7-B
HYS 72D64020GR-7-B
HYS 72D128020GR-7-B
PC2100R-20330-A1
PC2100R-20330-B1
PC2100R-20330-A1
PC2100R-20330-C1
one bank 256 MB Reg. DIMM
one bank 512 MB Reg. DIMM
two banks 512 MB Reg. DIMM
two banks 1 GByte Reg. DIMM
256 MBit (x8)
256 Mbit (x4)
256 MBit (x8)
256 MBit (x4)
(stacked with
soldering process)
HYS 72D128021GR-7-B
PC2100R-20330-C1
two banks 1 GByte Reg. DIMM
256 MBit (x4)
(stacked with
laser welding
process)
PC1600 (CL=2):
HYS 72D32000GR-8-B
HYS 72D64000GR-8-B
HYS 72D64020GR-8-B
HYS 72D128020GR-8-B
PC1600R-20220-A1
PC1600R-20220-B1
PC1600R-20220-A1
PC1600R-20220-C1
one bank 256 MB Reg. DIMM
one bank 512 MB Reg. DIMM
two banks 512 MB Reg. DIMM
two banks 1 GByte Reg. DIMM
256 MBit (x8)
256 Mbit (x4)
256 MBit (x8)
256 MBit (x4)
(stacked with
soldering process)
HYS 72D128021GR-8-B
PC1600R-20220-C1
two banks 1 GByte Reg. DIMM
256 MBit (x4)
(stacked with
laser welding
process)
Note: All part numbers end with a place code (not shown), designating the silicon-die revision. Reference
information available on request. Example: HYS 72D32000GR-8-B, indicating Rev.B die are used for
SDRAM components
The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100R”, the
latencies (f.e. “20330” means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card
used for this module.
INFINEON Technologies
2
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A11,A12
Address Inputs
VDD
Power (+ 2.5 V)
(A12 for 256Mb & 512Mb based modules)
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS
Bank Selects
VSS
Ground
Data Input/Output
VDDQ
VDDID
VDDSPD
VREF
I/O Driver power supply
VDD Indentification flag
EEPROM power supply
I/O reference supply
Serial bus clock
Check Bits (x72 organization only)
Row Address Strobe
Column Address Strobe
Read/Write Input
CAS
WE
SCL
CKE0, CKE1
DQS0 - DQS8
CK0, CK0
Clock Enable
SDA
SA0 - SA2
NC
Serial bus data line
slave address select
no connect
SDRAM low data strobes
Differential Clock Input
DM0 - DM8
SDRAM low data mask/
DU
don’t use
DQS9 - DQS17
high data strobes
CS0 - CS1
Chip Selects
RESET
Reset pin (forces register
inputs low) *)
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the
Application Note at the end of this datasheet
Address Format
Density Organization
Memory SDRAMs
Banks
# of
# of row/bank/
Refresh Period Interval
SDRAMs columns bits
256 MB 32M x 72
512 MB 64M × 72
512 MB 64M x 72
1
1
2
2
32M x 8
64M × 4
32M x 8
64M × 4
9
13/2/10
13/2/11
13/2/10
13/2/11
8k
8k
8k
8k
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
18
18
36
1 GB
128M × 72
INFINEON Technologies
3
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Pin Configuration
PIN# Symbol
PIN#
48
49
50
51
Symbol
A0
CB2
VSS
CB3
PIN#
93
94
95
96
97
98
99
Symbol
VSS
DQ4
Symbol
DM8/DQS17
A10
CB6
VDDQ
CB7
1
2
3
4
5
6
7
8
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
140
141
142
143
144
DQ5
VDDQ
DM0/DQS9
DQ6
DQ7
VSS
NC
NC
NC
52
BA1
KEY
KEY
VSS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
RAS
DQ45
VDDQ
CS0
CS1
DM5/DQS14
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
RESET
VSS
DQ8
DQ9
DQS1
VDDQ
DU
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
NC
DQ20
NC / A12
VSS
DQ21
A11
DM2/DQS11
VDD
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VDDQ
DM3/DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
CK0
VSS
BA0
DQ35
DQ40
VDDQ
WE
DQ41
CAS
DU
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
DU
DU
VDD
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
DM6/DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDDQ
SA0
VSS
A1
CB0
CB1
VDD
DQS8
NC
SDA
SCL
SA1
SA2
VDDSPD
Note: A12 is used for 256Mbit and 512Mbit based modules only
INFINEON Technologies
4
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
RS0
DQS0
DQS4
DM4/DQS13
DM0/DQS9
DM
I/O 0
DQS
CS
D4
DQS
CS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ2
DQ3
DQ36
DQ37
DQ38
DQ39
DQ4
DQ5
DQ6
DQ7
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
CS
D5
CS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ8
DQ9
DQ10
DQ11
I/O 4
I/O 5
I/O 6
I/O 7
DQ44
DQ45
DQ46
DQ47
DQ12
DQ13
DQ14
DQ15
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D6
DQS
DM
CS DQS
DQ48
DQ49
DQ50
DQ51
I/O 0
DQ16
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ17
DQ18
DQ19
D2
DQ52
DQ53
DQ54
DQ55
DQ20
DQ21
DQ22
DQ23
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DM
I/O 0
CS DQS
CS
D3
DM
DQS
DQ56
DQ57
DQ58
DQ59
I/O 0
DQ24
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D7
DQ60
DQ61
DQ62
DQ63
DQS8
DM8/DQS17
V
EEPROM
D0 - D8
DDSPD
Serial PD
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D8
DQS
V
V
CB0
CB1
CB2
CB3
DD, DDQ
D0 - D8
D0 - D8
SDA
SCL
VREF
A0
SA0 SA1 SA2
A1
A2
V
SS
D0 - D8
CB4
CB5
CB6
CB7
V
DDID
Strap: see Note 4
CS0
RS0 -> CS : SDRAMs D0-D8
R
E
G
I
S
T
E
R
Notes:
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8
BA0-BA1
A0-A12
RAS
1. DQ-to-I/O wiring may be changed within a byte.
RA0-RA12 -> A0-A12: SDRAMs D0 - D8
RRAS -> RAS : SDRAMs D0 - D8
RCAS -> CAS : SDRAMs D0 - D8
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
CAS
CKE0
WE
RCKE0 -> CKE: SDRAMs D0 - D8
RWE -> WE : SDRAMs D0 - D8
5. SDRAM placement alternates between the back
and front of the DIMM.
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
PCK
PCK
RESET
Block Diagram: One Bank 32Mb x 72 DDR-I SDRAM DIMM Module
HYS72D32000GR using x8 organized SDRAMs on Raw Card Version A
INFINEON Technologies
5
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
RS1
RS0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
DM
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D0
CS DQS
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D13
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D9
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D5
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
CS
D1
DQS
DM
CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
DQ8
DQ9
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D14
D10
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
DQS
DQS
DM
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
DQ48
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D15
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D11
D2
I/O 4
I/O 5
I/O 6
I/O 7
I/O 4
I/O 5
I/O 6
I/O 7
DQS7
DM7/DQS16
DQS3
DM3/DQS12
CS
D7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
DM
CS
DQS
DQ56
I/O 0
DQ24
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D16
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
D12
DQS8
DM8/DQS17
Serial PD
V
EEPROM
D0 - D17
DDSPD
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
CS DQS
DQS
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
SCL
V
V
DD, DDQ
A0
SA0 SA1
A1
A2
D17
VREF
D0 - D17
D0 - D17
SA2
V
SS
V
DDID
Strap: see Note 4
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
CS0
RS0 -> CS : SDRAM D0-D8
RS1 -> CS : SDRAM D9-D17
CS1
R
E
G
I
S
T
E
R
Notes:
BA0-BA1
A0-A12
RAS
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RA12 -> A0-A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0 -> CKE: SDRAMs D0 - D8
RCKE1 -> CKE: SDRAMs D9 - D17
RWE -> WE : SDRAMs D0 - D17
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
CAS
CKE0
CKE1
WE
STRAP OUT (OPEN): VDD = VDDQ
PCK
PCK
RESET
5. SDRAM placement alternates between the back
and front of the DIMM.
Block Diagram: Two Bank 64Mb x 72 DDR-I SDRAM DIMM Modules
HYS 72D64020GR Using x8 Organized SDRAMs on Raw Card Version A
INFINEON Technologies
6
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
VSS
RS0B
RS0A
DQS0
DM0/DQS9
DM
DQS
CS
D0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DM
DQ0
DQ1
DQ2
DQ3
DQ4
I/O 0
I/O 1
I/O 2
I/O 3
DQ5
DQ6
DQ7
DQS1
DQS2
DQS3
DM1/DQS10
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D1
DM
DQS
CS
DQ8
DQ9
DQ10
DQ11
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
DQ13
DQ14
DQ15
D10
DM2/DQS11
DQS
DQS
CS
CS DM
D2
I/O 0
I/O 1
I/O 2
I/O 3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
D11
DM3/DQS12
DM
CS
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
D12
D3
DQS4
DM4/DQS13
V
EEPROM
D0 - D17
DDSPD
DQS
DM
CS
DM
DM
DQS
CS
DQ32
DQ33
DQ34
DQ35
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
V
V
DD, DDQ
D4
D13
VREF
D0 - D17
D0 - D17
V
DQS5
DQS6
SS
DM5/DQS14
DQS
CS
DQS
CS DM
D5
V
DDID
Strap: see Note 4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D14
Serial PD
DM6/DQS15
CS DM
D15
DQS
CS
D6
DQS
DM
SDA
DQ48
DQ49
DQ50
DQ51
I/O 0
I/O 1
I/O 2
I/O 3
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
SCL
A0
SA0 SA1 SA2
A1 A2
DQS7
DQS8
DM7/DQS16
DM
DM
DM
DM
CS
DQS
CS
D7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
D16
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
DM8/DQS17
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
DQS
CS
D8
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
D17
5. SDRAM placement alternates between the back
and front of the DIMM.
CS0
RS 0 -> CS : SDRAMs D0-D17
R
E
G
I
S
T
E
R
BA0-BA1
A0-A11,A12
RAS
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0A -> CKE: SDRAMs D0 - D8
RCKEB -> CKE: SDRAMs D9 - D17
RWE -> WE: SDRAMs D0 - D17
CAS
CKE0
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
WE
PCK
PCK
RESET
Block Diagram: One Bank 64Mb x 72 DDR-I SDRAM DIMM Modules
HYS 72D64000GR using x4 Organized SDRAMs on Raw Card Version B
INFINEON Technologies
7
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
V
SS
1
RS
0
RS
DQS0
DM0/DQS9
DM
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D18
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
DM
DM
DM
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
D27
DQS1
DM1/DQS10
DQS
CS
D1
DQS
CS
DQS
CS
DQS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
D19
D10
D28
DM2/DQS11
DQS2
DQS3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQS
DM
CS
CS
CS DM
D2
CS DM
D20
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D11
D29
DM3/DQS12
DM
CS
DM
CS
CS
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D12
D30
D3
D21
DQS4
DM4/DQS13
DQS
DQS
DM
CS
DM
CS
DQS
DQS
CS DM
D13
CS DM
D31
DQ32
DQ33
DQ34
DQ35
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D4
D22
DQS5
DQS6
DM5/DQS14
DQS
DQS
S
DM
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS DM
D5
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS DM
D23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D14
D32
DM6/DQS15
CS DM
D15
CS DM
D33
DQS
CS DM
D6
DQS
CS DM
D24
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS7
DQS8
DM7/DQS16
DM
CS
DM
CS
DM
CS
DM
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ60
DQ61
DQ62
DQ63
D7
D25
D16
D34
DM8/DQS17
DM
CS
DM
CS
DM
CS
DM
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
D8
D26
D17
DDSPD
V
D35
CK0, CK 0 --------- PLL*
Serial PD
A0
V
V
EEPROM
* Wire per Clock Loading Table/Wiring Diagrams
SDA
CS0
RS0 -> CS : SDRAMs D0-D17
SCL
DD,
D0 - D35
A1 A2
DDQ
CS1
R
E
G
I
S
T
E
R
RS1 -> CS : SDRAMs D18 -D35
VREF
D0 - D35
D0 - D35
BA0-BA1
A0-A12
RAS
SA0 SA1
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35
RA0-RA12 -> A0-A12: SDRAMs D0 - D35
RRAS -> RAS : SDRAMs D0 - D35
RCAS -> CAS : SDRAMs D0 - D35
RCKE0 -> CKE: SDRAMs D0 - D17
RCKE1 -> CKE: SDRAMs D18 - D35
RWE -> WE: SDRAMs D0 - D35
SA2
V
SS
V
DDID
Strap: see Note 4
Notes:
CAS
1. DQ-to-I/O wiring may be changed within a byte.
CKE0
CKE1
WE
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
PC
K
PC
K
RESET
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
Block Diagram: Two Bank 128Mb x 72 DDR-I SDRAM DIMM Modules
HYS 72D128020GR using x4 Organized SDRAMs on Raw Card Version C
INFINEON Technologies
8
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
– 0.5
– 0.5
-55
–
max.
3.6
3.6
+150
1
Input / Output voltage relative to VSS
Power supply voltage on VDD/VDDQ to VSS
Storage temperature range
VIN, VOUT
VDD, VDDQ
TSTG
V
V
oC
W
mA
Power dissipation (per SDRAM component)
Data out current (short circuit)
PD
IOS
–
50
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Supply Voltage Levels
Parameter
Symbol
Limit Values
nom.
Unit
Notes
min.
max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
Termination Voltage
VDD
2.3
2.5
2.7
V
V
V
V
V
-
VDDQ
VREF
VTT
2.3
2.5
2.7
1)
2)
3)
0.49 x VDDQ
VREF – 0.04
2.3
0.5 x VDDQ
VREF
0.51 x VDDQ
VREF + 0.04
3.6
EEPROM supply voltage
VDDSPD
2.5
1
2
Under all conditions, VDDQ must be less than or equal to VDD
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC)
VREF is also expected to track noise variations in VDDQ
VTT of the transmitting device must track VREF of the receiving device.
.
.
3
DC Operating Conditions (SSTL_2 Inputs)
(VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS)
Parameter
Symbol
Limit Values
max.
Unit
Notes
min.
DC Input Logic High
DC Input Logic Low
Input Leakage Current
Output Leakage Current
VIH (DC)
VIL (DC)
IIL
VREF + 0.15
– 0.30
– 5
VDDQ + 0.3
V
1)
–
VREF – 0.15
V
5
5
µA
µA
1)
2)
IOL
– 5
1) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what
determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving
device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but
has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must
tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV).
2) For any pin under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V. Values are shown per DDR-SDRAM component.
INFINEON Technologies
9
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC1600)
256MB 512MB 512MB 1GB
x72
1bank 1bank 2bank 2bank
-8 -8 -8 -8
MAX MAX MAX MAX
x72
x72
x72
Notes
5
Symbol
IDD0
Parameter/Condition
Unit
mA
Operating Current
: one bank; active / precharge; tRC = tRC MIN; tCK =
tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle; address
810
1620
1215
2430
1, 4
and control inputs changing once every two clock cycles
Operating Current: one bank; active/read/precharge; Burst = 4;
IDD1
900
63
1800
126
1305
126
2610
252
mA 1, 3, 4
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current
: all banks idle; power-down
IDD2P
mA
mA
2, 4
2, 4
mode; CKE <= VIL MAX; tCK = tCK MIN
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
changing once per clock cycle, VIN = VREF for DQ, DQS and DM.
315
630
630
1260
IDD2F
Precharge Quiet Standby Current
: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable
at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
198
144
396
288
396
288
792
576
IDD2Q
mA
mA
2, 4
2, 4
Active Power-Down Standby Current
: one bank active; power-down
mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and
IDD3P
DM.
Active Standby Current: one bank active; active / precharge;CS >= VIH
MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
IDD3N
IDD4R
IDD4W
405
855
945
810
1710
1890
810
1260
1350
1620
2520
2700
mA
2, 4
Operating Current
: one bank active; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A,
CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
mA 1, 3, 4
Operating Current
: one bank active; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A,
CL=3 for DDR333; tCK = tCK MIN
mA
1, 4
Auto-Refresh Current
: tRC = tRFC MIN, distributed refresh
1530
27,0
3060
54
1935
54
3870
108
IDD5
IDD6
mA
mA
1, 4
2, 4
Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
Operating Current
: four bank; four bank interleaving with BL=4;
IDD7
1890
3780
2295
4590
mA 1, 3, 4
Refer to the following page for detailed test conditions.
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
2 * n * IDDx[component]
for single bank modules (n: number of components per module bank)
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
10
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2100)
256MB 512MB 512MB 1GB
x72 x72 x72 x72
1bank 1bank 2bank 2bank
-7 -7 -7 -7
MAX MAX MAX MAX
Notes
5
Symbol
Parameter/Condition
Unit
mA
Operating Current
: one bank; active / precharge; tRC = tRC MIN; tCK = tCK
IDD0 MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and
900
1800
1395
2790
1, 4
control inputs changing once every two clock cycles
Operating Current
: one bank; active/read/precharge; Burst = 4;
IDD1
990
72
1980
144
1485
144
2970
288
mA 1, 3, 4
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current
: all banks idle; power-down
IDD2P
mA
mA
2, 4
2, 4
mode; CKE <= VIL MAX; tCK = tCK MIN
Precharge Floating Standby Current
>= VIH MIN; tCK = tCK MIN ,address and other control inputs changing once
per clock cycle, VIN = VREF for DQ, DQS and DM.
: /CS >= VIH MIN, all banks idle; CKE
360
720
720
1440
IDD2F
Precharge Quiet Standby Current
: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at
>= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
225
162
450
324
450
324
900
648
IDD2Q
mA
mA
2, 4
2, 4
Active Power-Down Standby Current: one bank active; power-down mode;
CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
: one bank active; active / precharge;CS >= VIH
MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS
inputs changing twice per clock cycle; address and control inputs changing
once per clock cycle
IDD3N
IDD4R
IDD4W
495
1035
1125
990
990
1530
1620
1980
3060
3240
mA
2, 4
Operating Current
: one bank active; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A,
CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
2070
2250
mA 1, 3, 4
Operating Current
: one bank active; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A,
CL=3 for DDR333; tCK = tCK MIN
mA
1, 4
Auto-Refresh Current
: tRC = tRFC MIN, distributed refresh
1620
27,0
3240
54
2115
54
4230
108
IDD5
IDD6
mA
mA
1, 4
2, 4
Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
Operating Current
: four bank; four bank interleaving with BL=4;
IDD7
2025
4050
2520
5040
mA 1, 3, 4
Refer to the following page for detailed test conditions.
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
2 * n * IDDx[component]
for single bank modules (n: number of components per module bank)
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
11
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
SPD Codes
256MB 256MB 512MB 512MB 512MB 512MB 1GB
x72 x72 x72 x72 x72 x72 x72
1GB
x72
Byte#
Description
1bank 1bank 1bank 1bank 2bank 2bank 2bank 2bank
-7
-8
-7
-8
-7
-8
-7
-8
HEX
HEX
HEX
HEX
HEX
HEX
HEX
HEX
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes
128
80
08
07
0D
0A
01
48
00
04
70
75
02
82
08
08
80
08
07
0D
0A
01
48
00
04
80
80
02
82
08
08
80
08
07
0D
0B
01
48
00
04
70
75
02
82
04
04
80
08
07
0D
0B
01
48
00
04
80
80
02
82
04
04
80
08
07
0D
0A
02
48
00
04
70
75
02
82
08
08
80
08
07
0D
0A
02
48
00
04
80
80
02
82
08
08
80
08
07
0D
0B
02
48
00
04
70
75
02
82
04
04
80
08
07
0D
0B
02
48
00
04
80
80
02
82
04
04
Total Bytes in Serial PD
Memory Type
256
DDR-SDRAM
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
13
10 / 11
1 / 2
x72
0
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 2.5
SSTL_2.5
7ns / 8ns
0.75ns / 0.8ns
ECC
Self-Refresh, 7.8ms
x8 / x4
10
11
12
13
14
Access Time from Clock at CL = 2.5
DIMM Config
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-Back
Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
na
15
tccd = 1 CLK
01
01
01
01
01
01
01
01
16
17
18
19
20
21
2, 4 & 8
4
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
CAS latency = 2 & 2.5
CS latency = 0
Write latency = 1
registered
Concurrent Auto
Precharge
7.5ns / 10ns
0.75ns / 0.8ns
not supported
not supported
20ns
WE Latencies
SDRAM DIMM Module Attributes
22
SDRAM Device Attributes: General
C0
C0
C0
C0
C0
C0
C0
C0
23
24
Min. Clock Cycle Time at CAS Latency = 2
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1.5
Access Time from Clock at CL = 1.5
Minimum Row Precharge Time
Minimum Row Act. to Row Act. Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
Addr. and Command Setup Time
Addr. and Command Hold Time
Data Input Setup Time
75
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
CA
C1
INFI-
A0
80
00
00
50
3C
50
32
40
B0
B0
60
60
00
46
50
30
3C
A0
00
00
BF
C1
INFI-
75
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
03
C1
INFI-
A0
80
00
00
50
3C
50
32
80
B0
B0
60
60
00
46
50
30
3C
A0
00
00
F8
C1
INFI-
75
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
CB
C1
INFI-
A0
80
00
00
50
3C
50
32
40
B0
B0
60
60
00
46
50
30
3C
A0
00
00
C0
C1
INFI-
75
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
04
C1
INFI-
A0
80
00
00
50
3C
50
32
80
B0
B0
60
60
00
46
50
30
3C
A0
00
00
F9
C1
INFI-
25
26
27
28
29
15ns
20ns
30
45ns / 50ns
256MByte / 512MByte
0.9ns / 1.1ns
0.9ns / 1.1ns
0.5ns / 0.6ns
0.5ns / 0.6ns
–
31
32
33
34
35
Data Input Hold Time
36-40
41
42
Superset Information
Minimum Core Cycle Time tRC
Min. Auto Refresh Cmd Cycle Time tRFC
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew tDQSQ
X-Factor tQHS
65ns / 70ns
75ns / 80ns
12ns
43
44
45
0.5ns / 0.6ns
0.75ns / 1.0ns
–
46-61
62
63
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Revision 0.0
–
64
Manufacturers JEDEC ID Code
–
65-71
Manufacturer
–
NEON NEON NEON NEON NEON NEON NEON NEON
72
Module Assembly Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
–
–
–
–
–
–
–
73-90
91-92
93-94
95-98
99-127
128-255
open for Customer use
–
INFINEON Technologies
12
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V)
DDR266A
-7
DDR200
-8
Symbol
tAC
Parameter
Unit Notes
Min
Max
Min
Max
+ 0.8
+ 0.8
0.55
0.55
DQ output access time from CK/CK
− 0.75 + 0.75
− 0.75 + 0.75
− 0.8
− 0.8
0.45
0.45
ns
ns
tCK
tCK
ns
ns
ns
ns
ns
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
tDQSCK DQS output access time from CK/CK
tCH
tCL
tHP
tCK
tCK
tDH
tDS
CK high-level width
CK low-level width
Clock Half Period
0.45
0.45
0.55
0.55
min (tCL, tCH)
min (tCL, tCH)
CL = 2.5
CL = 2.0
7
12
12
8
12
12
Clock cycle time
7.5
0.5
0.5
10
0.6
0.6
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width (each
input)
tIPW
2.2
2.5
2
ns
ns
1, 10
1-4,
11
tDIPW DQ and DM input pulse width (each input)
1.75
tHZ
tLZ
Data-out high-impedence time from CK/CK
Data-out low-impedence time from CK/CK
− 0.75 + 0.75
− 0.75 + 0.75
− 0.8
− 0.8
0.75
+ 0.8
+ 0.8
1.25
ns
ns
tCK
1-4, 5
1-4, 5
1-4
tDQSS Write command to 1st DQS latching transition
0.75
1.25
+ 0.5
DQS-DQ skew
tDQSQ
+ 0.6
ns
1-4
(for DQS & associated DQ signals)
tQHS
tQH
Data hold skew factor
+ 0.75
+ 1.0
ns
ns
tCK
1-4
1-4
1-4
Data Output hold time from DQS
tHP-tQHS
0.35
tHP-tQHS
0.35
tDQSL,H DQS input low (high) pulse width (write cycle)
DQS falling edge to CK setup time (write
tDSS
0.2
0.2
0.2
0.2
tCK
tCK
1-4
1-4
cycle)
DQS falling edge hold time from CK (write
cycle)
tDSH
tMRD Mode register set command cycle time
tWPRES Write preamble setup time
tWPST Write postamble
14
0
16
0
ns
ns
1-4
1-4, 7
0.40
0.25
0.9
1.0
0.9
1.0
0.9
0.40
45
0.60
0.40
0.25
1.1
1.1
1.1
1.1
0.9
0.40
50
0.60
tCK 1-4, 6
tWPRE Write preamble
tCK
ns
ns
ns
ns
tCK
tCK
ns
ns
1-4
fast slew rate
Address and control
tIS
input setup time
slow slew rate
2-4,
10,11
fast slew rate
Address and control
tIH
input hold time
slow slew rate
tRPRE Read preamble
tRPST Read postamble
1.1
0.60
1.1
0.60
1-4
1-4
1-4
1-4
120,000
tRAS
tRC
Active to Precharge command
120,000
Active to Active/Auto-refresh command period
65
70
INFINEON Technologies
13
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V)
DDR266A
-7
DDR200
-8
Symbol
Parameter
Unit Notes
Min
75
Max
Min
Max
Auto-refresh to Active/Auto-refresh
command period
tRFC
80
ns
1-4
tRCD
tRP
tRRD
tWR
Active to Read or Write delay
Precharge command period
Active bank A to Active bank B command
Write recovery time
20
20
15
15
20
20
15
15
ns
ns
ns
ns
1-4
1-4
1-4
1-4
Auto precharge write recovery
+ precharge time
tDAL
(twr/tck) + (trp/tck)
tCK
1-4,9
tWTR Internal write to read command delay
tXSNR Exit self-refresh to non-read command
tXSRD Exit self-refresh to read command
Average Periodic
1
1
tCK
ns
tCK
1-4
1-4
1-4
75
80
200
200
tREFI
7.8
7.8
µs
1-4, 8
256Mbit based
Refresh Interval
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Character-
istics (Note 3) is VTT
.
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parame-
ters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or
begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for
this parameter, but system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or
before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifi-
cations of the device. When no writes were previously in progress on the bus, DQS will be transitioning
from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning
from HIGH to LOW at this time, depending on tDQSS
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the
actual system clock cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK
slew rate >1.0 V/ns, measured between VOH(ac) and VOL(ac)
INFINEON Technologies
14
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Package Outlines Raw Card A (one memory bank)
Module Package
DDR-I Registered DIMM Modules Raw Card A
256MByte Modules (one physical bank, 9 components)
Front View
4.0 max.
+ 0.15
-
133.35
4.0
Register
PLL
Register
53
92
52
pin 1
2.3 typ.
+ 0.1
-
1.27
64.77
49.53
6.62
Backside View
144
pin 93
145
184
2.5D
3
3
Detail of Contacts B
6.35
Detail of Contacts A
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-DIM-184-10, Raw Card A, one
bank
INFINEON Technologies
15
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Package Outlines Raw Card A (two memory banks)
Module Package
DDR-I Registered DIMM Modules Raw Card A
512MByte Module (two physical banks, 18 components)
Front View
4.0 max.
+ 0.15
-
133.35
4.0
Register
PLL
Register
53
92
52
pin 1
2.3 typ.
+ 0.1
-
1.27
64.77
49.53
6.62
Backside View
144 145
pin 93
184
2.5D
3
3
Detail of Contacts A
Detail of Contacts B
6.35
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-DIM-184-10, Raw Card A, two
banks
INFINEON Technologies
16
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Package Outlines Raw Card B
Module Package
DDR-I Registered DIMM Modules Raw Card B
512MByte Modules
(one physical bank, 18 components)
Front View
4.0 max.
+ 0.15
-
133.35
4.0
Register
PLL
Register
92
53
52
pin 1
2.3 typ.
+ 0.1
-
1.27
64.77
49.53
6.62
Backside View
144 145
pin 93
184
2.5D
3
3
Detail of Contacts A
Detail of Contacts B
6.35
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-DIM-184-8, Raw Card
B
INFINEON Technologies
17
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Package Outlines Raw Card C
Module Package
DDR-I Registered DIMM Modules Raw Card C
1 GByte Modules (two physical banks, 36 components)
Front View
6.8 max.
+ 0.15
-
133.35
4.0
Register
PLL
Register
92
53
52
pin 1
2.3 typ.
+ 0.1
-
1.27
64.77
49.53
6.62
Backside View
144 145
pin 93
184
2.5D
3
3
Detail of Contacts A
Detail of Contacts B
6.35
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-DIM-184-11, Raw Card
C
INFINEON Technologies
18
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
APPLICATION NOTE:
Power Up and Power Management on DDR Registered DIMMs
(according to JEDEC ballot JC-42.5 Item 1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up
and to minimize power consumption during low power mode. One feature is externally controlled via a system-
generated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipa-
tions and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-
Locked Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other
SDRAM inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low
level, all the register outputs are forced to a low level, and all differential register input receivers are powered
down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven
from the system as an asynchronous signal according to the attached details. Using this function also permits the
system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs
stay in Self Refresh mode.
The function for RESET is as follows:
Register
Register Inputs
Outputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
H
H
Rising
Rising
L or H
Falling
Falling
L or H
H
L
H
L
X
Qo
Illegal input
conditions
H
L
High Z
High Z
X
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
X : Don’t care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK
risning and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until acti-
vated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of
20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operat-
ing frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz
(actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are
INFINEON Technologies
19
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
made High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less
than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is
tied inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Regis-
tered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for
a 2-bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely
control CKE to one physical DIMM bank through the use of the RESET pin.
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low
state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable
low-level at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM
PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When
a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior
to SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-
nector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these com-
mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a
‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent
with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-
pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
INFINEON Technologies
20
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
1. The system applies Self Refresh entry command.
(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)
Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-
level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to
a specific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the reg-
ister (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address sig-
nals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in
which the clocks and the control and the address signals must maintain valid levels after RESET low has
been applied. It is highly recommended that CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM.
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM
PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-
nector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these com-
mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to be con-
sistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
RESET timing relationship to a specific clock edge is not required (during this period, register inputs must
remain stable).
4. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers suffi-
cient time to be turned on and become stable. During this time the system must maintain the valid logic levels
described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE out-
puts to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t
(ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
INFINEON Technologies
21
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh,
this is an alternate operating mode for these DIMMs.
1. System enters Self Refresh entry command.
(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the data and
clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes
the time in which the clocks and the control and the address signals must maintain valid levels after RESET
low has been applied. It is highly recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-
nector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these com-
mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a
‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent
with the state of the register outputs.
2. The system switches RESET to a logic 'high' level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to
remain stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers suffi-
cient time to be turned on and become stable. During this time the system must maintain the valid logic levels
described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE out-
puts in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to
accept an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
INFINEON Technologies
22
2002-09-10 (revision 0.91)
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
sequence defined in this application note. In the case where RESET remains high and the clocks are powered
off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown
DIMM state will result.
INFINEON Technologies
23
2002-09-10 (revision 0.91)
相关型号：
©2020 ICPDF网 联系我们和版权申明