HYS64T32000LM-5-A [INFINEON]
Double-Data-Rate-Two SDRAM Micro-DIMM; 双倍数据速率 - 双微SDRAM -DIMM
| 型号： | HYS64T32000LM-5-A |
| 厂家： | 
Infineon |
| 描述： | Double-Data-Rate-Two SDRAM Micro-DIMM |
| 文件： | 总31页 (文件大小：913K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 0.6, June 2004
HYS64T32000[H/K/L]M–[3.7/5]–A
HYS64T64020[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
DDR2 MDIMM
Memory Products
N e v e r s t o p t h i n k i n g .
The information in this document is subject to change without notice.
Edition 2004-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 0.6, June 2004
HYS64T32000[H/K/L]M–[3.7/5]–A
HYS64T64020[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
DDR2 MDIMM
Memory Products
N e v e r s t o p t h i n k i n g .
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Preliminary
Revision History:
Rev. 0.6
2004-06
Previous Revision:
Rev. 0.5
2004-04
Page
All
Subjects (major changes since last revision)
Added production variants with “H” instead of “L” in product type
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Template: mp_a4_v2.3_2004-01-14.fm
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
1.2
1.3
2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
4.1
4.2
I
DD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical Characteristics & AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5
6
7
8
Data Sheet
5
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
Preliminary
Double-Data-Rate-Two SDRAM Micro-DIMM
DDR2 MDIMM
HYS64T32000[H/K/L]M–[3.7/5]–A
HYS64T64020[H/K/L]M–[3.7/5]–A
1
Overview
This chapter gives an overview of the Double-Data-Rate-Two SDRAM Micro-DIMM product family and describes
its main characteristics.
1.1
Features
•
214-pin PC2-4200 and PC2-3200 DDR2 SDRAM
memory modules for use as main memory when
installed in systems such as mobile personal
computers.
32M × 64 and 64M × 64 module organisation and
32M × 16 chip organisation
JEDEC standard Double-Data-Rate-Two
Synchronous DRAMs (DDR2 SDRAM) with a single
+ 1.8 V (± 0.1 V) power supply
Built with 512Mb DDR2 SDRAMs in P-TFBGA-84-2
chipsize packages
•
•
•
Burst Refresh, Distributed Refresh and Self Refresh
All inputs and outputs SSTL_1.8 compatible
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
•
•
•
•
Serial Presence Detect with E2PROM
Micro-DIMM Dimensions (nominal) : 30 mm high,
54.0 mm wide
•
•
Based on JEDEC standard reference layouts Raw
Card “A” & “B”
2-piece type Mezzanine Socket with 0,4 mm
contact centers
•
•
Programmable CAS Latencies (3, 4 and 5), Burst
Length (8 & 4) and Burst Type
Table 1
Performance
Product Type Speed Code
Speed Grade
–3.7
PC2–4200 4–4–4
fCK5 266
–5
Units
—
PC2–3200 3–3–3
max. Clock Frequency
@CL5
@CL4
@CL3
200
200
200
15
MHz
MHz
MHz
ns
fCK4 266
fCK3 200
tRCD 15
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
tRP
tRAS 45
tRC 60
15
15
ns
45
ns
60
ns
1.2
Description
The
INFINEON
HYS64T[3200/6402]0[H/K/L]M– The memory array is designed with 512Mb Double-
[3.7/5]–A module family are low profile Unbuffered Data-Rate-Two (DDR2) Synchronous DRAMs.
Micro-DIMM modules “MDIMMs” with 30,0 mm height Decoupling capacitors are mounted on the PCB board.
based on DDR2 technology. DIMMs are available as
The DIMMs feature serial presence detect based on a
32M × 64 and 64M × 64 organisation and density, serial E2PROM device using the 2-pin I2C protocol. The
intended for mounting into 214-pin mezzanine first 128 bytes are programmed with configuration data
connector sockets.
and are write protected; the second 128 bytes are
available to the customer.
Data Sheet
6
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Overview
Preliminary
Table 2
Ordering Information
Product Type
Compliance Code
Description
SDRAM
Technology
HYS64T64020KM-3.7-A 512MB 2Rx16 PC2-4200M-444-11-A0 two ranks 512 MByte DIMM 512 Mbit (×16)
HYS64T32000KM-3.7-A 256MB 1Rx16 PC2-4200M-444-11-B0 one rank 256 MByte DIMM
HYS64T64020KM-5-A
HYS64T32000KM-5-A
512MB 2Rx16 PC2-3200M-333-11-A0 two ranks 512 MByte DIMM
256MB 1Rx16 PC2-3200M-333-11-B0 one rank 256 MByte DIMM
HYS64T64020HM-3.7-A 512MB 2Rx16 PC2-4200M-444-11-A0 two ranks 512 MByte DIMM 512 Mbit (×16)
HYS64T64020LM-3.7-A 512MB 2Rx16 PC2-4200M-444-11-A0 two ranks 512 MByte DIMM
HYS64T32000HM-3.7-A 256MB 1Rx16 PC2-4200M-444-11-B0 one rank 256 MByte DIMM
HYS64T32000LM-3.7-A 256MB 1Rx16 PC2-4200M-444-11-B0 one rank 256 MByte DIMM
HYS64T64020HM-5-A
HYS64T64020LM-5-A
HYS64T32000HM-5-A
HYS64T32000LM-5-A
512MB 2Rx16 PC2-3200M-333-11-A0 two ranks 512 MByte DIMM
512MB 2Rx16 PC2-3200M-333-11-A0 two ranks 512 MByte DIMM
256MB 1Rx16 PC2-3200M-333-11-B0 one rank 256 MByte DIMM
256MB 1Rx16 PC2-3200M-333-11-B0 one rank 256 MByte DIMM
The Compliance Code is printed on the module label All product types end with a place code, designating the
and provides technical details to the user, e. g. "512MB silicon die revision. Example: HYS72T64000KM–5–A,
2R×16 PC2-4200M-444-11-A0" where "512MB" tells indicating Rev. A dies are used for DDR2 SDRAM
the density in megabytes, "2R ×16" means 2 ranks on components. For all INFINEON DDR2 module and
module built of ×16 components, "PC2-4200M" means component nomenclature see Chapter 8 of this data
DDR2 Micro-DIMM with 4.26 GB/s module bandwidth, sheet.
"444-11" means CAS latency of 4, RCD1) latency of 4,
and RP2) latency of 4 using JEDEC SPD revision 1.1,
and “A0” means JEDEC raw card A revision 0.
Table 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
# of
SDRAMs
# of row/bank/column bits
Raw
Card
256 MByte 32M × 64
512 MByte 64M × 64
1
2
4
8
13/2/10
13/2/10
B
A
Table 4
Components on Modules1)
Product Type
DRAM Components
HYB18T512160AF2)
DRAM Density
512 Mbit
DRAM Organisation
HYS64T32000HM2)
32M × 16
HYS64T32000LM2)
HYS64T32000KM
HYB18T512160AC
HYB18T512160AF2)
512 Mbit
512 Mbit
32M × 16
32M × 16
HYS64T64020HM2)
HYS64T64020LM2)
HYS64T64020KM
HYB18T512160AC
512 Mbit
32M × 16
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
2) Green Product
1) RCD: Row Column Delay
2) RP: Row Precharge
Data Sheet
7
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Overview
Preliminary
1.3 Pin Configuration
The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in Table 5 (214 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin
numbering is depicted in Figure 1.
Table 5
Pin#
Pin Configuration of MDIMM
Name
Pin
Type
Buffer
Type
Function
Clock Signals
122
194
123
195
43
CK0
CK1
CK0
CK1
CKE0
CKE1
NC
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Signals 1:0
I
I
Complement Clock Signals 1:0
I
I
Clock Enables
Note: 2-rank module
Note: 1-rank module
147
I
NC
Control Signals
165
62
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-rank module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
NC
NC
163
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
60
56
Address Signals
55
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address 1:0
Address Inputs 9:0
162
161
159
52
A1
A2
158
51
A3
A4
50
A5
157
48
A6
A7
155
154
54
A8
A9
A10
AP
A11
A12
Address Input 10/Autoprecharge
47
Address Input 11
Address Input 12
153
Data Sheet
8
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Overview
Preliminary
Table 5
Pin#
Pin Configuration of MDIMM
Name
Pin
Type
Buffer
Type
Function
Data Signals
3
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
4
DQ1
9
DQ2
10
DQ3
109
110
114
115
12
DQ4
DQ5
DQ6
DQ7
DQ8
13
DQ9
21
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
22
117
118
125
126
24
25
30
31
128
129
133
134
33
34
38
39
136
137
142
143
67
68
73
74
174
175
179
Data Sheet
9
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Overview
Preliminary
Table 5
Pin#
Pin Configuration of MDIMM
Name
Pin
Type
Buffer
Type
Function
180
76
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
77
81
82
182
183
188
189
84
85
92
93
191
192
200
201
95
96
101
102
203
204
208
209
112
120
131
36
Data Masks 7:0
Note: See block diagram for corresponding
DQ M signals
DM1
I
DM2
I
DM3
I
177
79
DM4
I
DM5
I
90
DM6
I
206
DM7
I
Data Sheet
10
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Overview
Preliminary
Table 5
Pin#
Pin Configuration of MDIMM
Name
Pin
Type
Buffer
Type
Function
7
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobes 7:0
Note: See block diagram for corresponding
DQS signals
6
19
18
28
27
140
139
71
70
186
185
198
197
99
98
EEPROM
105
SCL
SDA
SA0
SA1
I
CMOS
OD
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
104
I/O
211
I
I
CMOS
CMOS
SPD Address 1:0
213
Power Supplies
1
VREF
AI
–
–
I/O Reference Voltage
Power Supply
42, 45, 49, 53, 57, 61, 64, 146, 149, VDD
PWR
152, 156, 160, 164, 168, 171
107
VDDSPD
PWR
GND
–
–
EEPROM Power Supply
Ground Plane
2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, VSS
35, 37, 40, 66, 69, 72, 75, 78, 80, 83,
86, 89, 91, 94, 97, 100, 103, 108,
111, 113, 116, 119, 121, 124, 127,
130, 132, 135, 138, 141, 144, 173,
176, 178, 181, 184, 187, 190, 193,
196, 205, 199, 202, 207, 210
Other Pins
166
63
ODT0
On-Die Termination Control 1:0
Note: 2-rank module
ODT1
NC
Note: 1-rank module
15, 16, 41, 44, 46, 58, 59, 65, 87, 88, NC
106, 145, 148, 150, 151, 167, 169,
170, 172, 212, 214
NC
–
Not connected
Note: Pins not connected on Infineon
MDIMMs
Data Sheet
11
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Overview
Preliminary
Table 6
Abbreviations for Pin Type
Description
Abbreviation
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
Table 7
Abbreviation
SSTL
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_1.8)
CMOS Levels
CMOS
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Data Sheet
12
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Overview
Preliminary
VREF
DQ0
VSS
VSS
- Pin 001
- Pin 003
- Pin 005
- Pin 007
- Pin 009
- Pin 011
- Pin 013
- Pin 015
- Pin 017
Pin 108 -
Pin 110 -
Pin 112 -
Pin 114 -
Pin 116 -
Pin 118 -
Pin 120 -
Pin 122 -
Pin 124 -
Pin 126 -
Pin 128 -
Pin 130 -
Pin 132 -
Pin 134 -
Pin 136 -
Pin 138 -
Pin 140 -
Pin 142 -
Pin 144 -
Pin 146 -
Pin 148 -
Pin 150 -
Pin 152 -
Pin 154 -
Pin 156 -
Pin 158 -
Pin 160 -
Pin 162 -
Pin 164 -
Pin 166 -
Pin 168 -
Pin 170 -
Pin 172 -
Pin 174 -
Pin 176 -
Pin 178 -
Pin 180 -
Pin 182 -
Pin 184 -
Pin 186 -
Pin 188 -
Pin 190 -
Pin 192 -
Pin 194 -
Pin 196 -
Pin 198 -
Pin 200 -
Pin 202 -
Pin 204 -
Pin 206 -
Pin 208 -
Pin 210 -
Pin 212 -
Pin 214 -
V
SS - Pin 002
Pin 109 -
DQ4
DQ5
DM0
DQ6
VSS
DQ1 - Pin 004
Pin 111 - VSS
Pin 113 - VSS
Pin 115 - DQ7
Pin 117 - DQ12
Pin 119 - VSS
Pin 121 - VSS
Pin 123 - CK0
Pin 125 - DQ14
Pin 127 - VSS
Pin 129 - DQ21
Pin 131 - DM2
Pin 133 - DQ22
Pin 135 - VSS
Pin 137 - DQ29
Pin 139 - DQS3
Pin 141 - VSS
Pin 143 - DQ31
DQS0
- Pin 006
DQS0
DQ2
VSS
V
SS - Pin 008
DQ3 - Pin 010
DQ8 - Pin 012
DQ13
DM1
CK0
VSS
DQ9
NC
V
SS - Pin 014
NC - Pin 016
VSS
DQS1 - Pin 018
DQS1
DQ10
VSS
DQ15
DQ20
VSS
Pin 019
-
V
SS - Pin 020
- Pin 021
- Pin 023
- Pin 025
- Pin 027
- Pin 029
- Pin 031
- Pin 033
- Pin 035
- Pin 037
- Pin 039
- Pin 041
- Pin 043
- Pin 045
- Pin 047
- Pin 049
- Pin 051
- Pin 053
- Pin 055
- Pin 057
- Pin 059
- Pin 061
- Pin 063
- Pin 065
- Pin 067
- Pin 069
- Pin 071
- Pin 073
- Pin 075
- Pin 077
- Pin 079
- Pin 081
- Pin 083
- Pin 085
- Pin 087
- Pin 089
- Pin 091
- Pin 093
- Pin 095
- Pin 097
- Pin 099
- Pin 101
- Pin 103
- Pin 105
- Pin 107
DQ11 Pin 022
-
DQ16 Pin 024
-
DQ17
DQS2
VSS
VSS
VSS Pin 026
-
DQ23
DQ28
VSS
DQS2 Pin 028
-
DQ18 Pin 030
-
DQ19
DQ24
VSS
VSS Pin 032
-
DQS3
DQ30
VSS
DQ25 Pin 034
-
DM3 Pin 036
-
DQ26 Pin 038
-
VSS Pin 040
VSS
NC
Pin 145 -
DQ27
NC
VDD
Pin 147 - CKE1
Pin 149 - VDD
Pin 151 - NC
Pin 153 - A12
Pin 155 - A8
-
NC
VDD Pin 042
-
CKE0
VDD
NC
NC Pin 044
-
VDD
NC/BA2 Pin 046
-
A11
A9
A7 Pin 048
-
VDD
VDD
A5 Pin 050
Pin 157 - A6
-
A4
A3
A2 Pin 052
Pin 159 - A1
-
VDD
VDD
A10/AP Pin 054
Pin 161 - A0
-
BA0
BA1
VDD
WE Pin 056
Pin 163 - RAS
Pin 165 - S0
-
VDD
NC Pin 058
-
NC
ODT0
VDD
CAS Pin 060
Pin 167 - NC
Pin 169 - NC
Pin 171 - VDD
Pin 173 - VSS
Pin 175 - DQ37
Pin 177 - DM4
Pin 179 - DQ38
Pin 181 - VSS
Pin 183 - DQ45
Pin 185 - DQS5
Pin 187 - VSS
Pin 189 - DQ47
Pin 191 - DQ52
Pin 193 - VSS
Pin 195 - CK1
Pin 197 - DQS6
Pin 199 - VSS
Pin 201 - DQS5
Pin 203 - DQ60
Pin 205 - VSS
Pin 207 - VSS
Pin 209 - DQ63
Pin 211 - SA0
Pin 213 - SA1
-
VDD
S1 Pin 062
-
ODT1
NC
NC
VDD Pin 064
-
NC
VSS Pin 066
-
DQ32
VSS
DQ36
VSS
DQ33 Pin 068
-
DQS4 Pin 070
-
DQS4
DQ34
VSS
VSS
VSS Pin 072
-
DQ39
DQ44
VSS
DQ35 Pin 074
-
DQ40 Pin 076
-
DQ41
DM5
DQ42
VSS
VSS Pin 078
-
DQS5
DQ46
VSS
VSS Pin 080
-
DQ43 Pin 082
-
DQ48 Pin 084
-
DQ49
NC
DQ53
CK1
VSS
VSS Pin 086
-
NC Pin 088
-
VSS
DM6 Pin 090
-
VSS
DQS6
DQ54
VSS
DQ50 Pin 092
-
DQ51
DQ56
VSS
VSS Pin 094
-
DQ57 Pin 096
-
DQ61
DM7
DQ62
VSS
DQS7 Pin 098
-
DQS7
DQ58
VSS
VSS Pin 100
-
DQ59 Pin 102
-
SDA Pin 104
-
SCL
VDDSPD
NC
NC Pin 106
-
NC
Figure 1
Pin Configuration for Two-Piece Mezzanine Socket on MDIMM (214 pins)
Data Sheet
13
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Overview
Preliminary
Table 8
Symbol
Input/Output Functional Description
Type
Polarity Function
CK[1:0],
CK[1:0]
I
Cross
point
The system clock inputs. All address and command lines are sampled on the
cross point of the rising edge of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
CKE[1:0]
S[1:0]
I
I
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down Mode
or the Self Refresh Mode.
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and
disables the command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations continue. Rank 0
is selected by S0; Rank 1 is selected by S1.
RAS, CAS, I
WE
Active
Low
When sampled at the cross point of the rising edge of CK,and falling edge of CK,
RAS, CAS and WE define the operation to be executed by the SDRAM.
BA[1:0]
I
I
—
Selects internal SDRAM memory bank
ODT[1:0]
Active
High
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR2 SDRAM mode register.
A[9:0],
A10/AP,
A[12:11]
I
—
During a Bank Activate command cycle, defines the row address when sampled
at the crosspoint of the rising edge of CK and falling edge of CK. During a Read
or Write command cycle, defines the column address when sampled at the cross
point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA[1:0] to
control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA[1:0] inputs. If AP is low, then BA[1:0] are used to
define which bank to precharge.
DQ[63:0]
DM[7:0]
I/O
I
—
Data Input/Output pins
Active
High
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is low but blocks
the write operation if it is high. In Read mode, DM lines have no effect.
DQS[7:0], I/O
DQS[7:0]
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In
Write mode, the data strobe is sourced by the controller and is centered in the
data window. In Read mode the data strobe is sourced by the DDR2 SDRAM
and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to VSS through a 20 Ω to 10 kΩ resistor
and DDR2 SDRAM mode registers programmed appropriately.
VDD,
Supply
—
—
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
V
DDSPD, VSS
SDA
I/O
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from SDA to to VDDSPD on the motherboard to act
as a pull-up.
SCL
I
I
—
—
This signal is used to clock data into and out of the SPD EEPROM.
Address pins used to select the Serial Presence Detect base address.
SA[1:0]
Data Sheet
14
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Block Diagrams
Preliminary
2
Block Diagrams
VDD,SPD
BA0 - BA1: SDRAMs D0 - D7
A0 - An: SDRAMs D0 - D7
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
BA0 - BA1
A0 - An
RAS
V
DD: SPD EEPROM E0
V
DD/VDDQ
V
/VDDQ: SDRAMs D0 - D7
VRDEDF: SDRAMs D0 - D7
VREF
CAS
VSS
WE
VSS: SDRAMs D0 - D7
CKE0
CKE1
ODT0
ODT1
CK0
CKE0: SDRAMs D0 - D3
CKE1: SDRAMs D4 - D7
ODT0: SDRAMs D0 - D3
ODT1: SDRAMs D4 - D7
E0
SCL
SCL
SDA
A0
SDA
SA0
SA1
A1
4 loads
4 loads
CK0
A2
CK1
WP
CK1
S0
S1
Vss
CS
D0
D4
D2
D6
CS
CS
CS
DM0
DQS0
DQS0
DQ0
LDM
LDM
DM4
LDM
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM5
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM1
DQS1
DQS1
DQ8
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ9
I/O9
I/O9
I/O9
I/O9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D1
D5
D3
D7
CS
CS
CS
CS
DM2
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3
LDM
LDM
DM6
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM7
LDM
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O9
I/O9
I/O9
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
MPBT0010
Figure 2
Block Diagram Raw Card A (x64, 2 Ranks, x16)
Notes
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
1. DQ, DQS, DM resistors are 22 Ω ±5 %
Data Sheet
15
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Block Diagrams
Preliminary
BA0 - BA1
A0 - An
RAS
BA0 - BA1: SDRAMs D0 - D3
VDD,SPD
V
DD: SPD EEPROM E0
A0 - An: SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
CAS: SDRAMs D0 - D3
WE: SDRAMs D0 - D3
VSS: SDRAMs D0 - D3
V
DD/VDDQ
V
/VDDQ: SDRAMs D0 - D3
VRDEDF: SDRAMs D0 - D3
VREF
VSS
CAS
WE
VSS: SDRAMs D0 - D3
VSS
CKE0
CKE: SDRAMs D0 - D3
ODT: SDRAMs D0 - D3
ODT0
S0
D2
D0
CK0
CK0
CK1
CK1
DM0
DQS0
DQS0
DQ0
LDM CS
DM4
LDM CS
LDQS
LDQS
I/O 0
2 loads
2 loads
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM5
DQ1
DQ2
I/O 1
E0
I/O 2
SCL
SDA
SA0
SA1
SCL
DQ3
I/O 3
SDA
A0
DQ4
I/O 4
DQ5
I/O 5
A1
DQ6
I/O 6
A2
DQ7
I/O 7
WP
DM1
UDM
UDQS
UDQS
I/O8
DQS1
DQS1
DQ8
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vss
DQ9
I/O9
I/O9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D1
D3
DM2
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3
LDM CS
LDQS
LDQS
I/O 0
DM6
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM7
LDM CS
LDQS
LDQS
I/O 0
I/O 1
I/O 1
I/O 2
I/O 2
I/O 3
I/O 3
I/O 4
I/O 4
I/O 5
I/O 5
I/O 6
I/O 6
I/O 7
I/O 7
UDM
UDQS
UDQS
I/O8
UDM
UDQS
UDQS
I/O8
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O9
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
MPBT0020
Figure 3
Notes
Block Diagram Raw Card B (x64, 1 Rank, x16)
3. Load matching Capacitors on BA0 - BA1, A0 - An,
RAS, CAS, WE, with 8 pF ± 0.5pF
1. DQ, DQS, DM resistors are 22 Ω ±5 %
2. S0, BAn, An, RAS, CAS, WE, ODTO, CKEO
resistors are 3 Ω ±5 %
Data Sheet
16
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Electrical Characteristics
Preliminary
3
Electrical Characteristics
3.1
Operating Conditions
Table 9
Absolute Maximum Ratings
Parameter
Symbol
Values
Min.
– 0.5
– 1.0
– 0.5
5
Unit
Note/Test
Condition
Max.
2.3
2.3
2.3
95
1)
1)
1)
1)
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
VIN, VOUT
VDD
V
V
V
%
VDDQ
Storage Humidity (without condensation) HSTG
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
Table 10
Operating Conditions
Parameter
Symbol
Values
min.
0
Unit
Notes
max.
+65
+95
+100
69
Operating temperature (ambient)
DRAM Case Temperature
TOPR
TCASE
TSTG
°C
°C
°C
kPa
%
1)2)3)4)
5)
0
Storage Temperature
– 50
105
10
Barometric Pressure (operating & storage)
Operating Humidity (relative)
HOPR
90
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85 °C Case Temperature before initiating Self-Refresh operation.
5) Up to 3000 m.
Table 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
min.
Unit
Notes
nom.
max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
VDD
1.7
1.8
1.9
V
V
V
V
V
V
—
1)
VDDQ
1.7
1.8
1.9
2)
VREF
0.49 × VDDQ
1.7
0.5 × VDDQ
0.51 × VDDQ
3.6
VDDSPD
VIH (DC)
VIL (DC)
—
—
—
VREF + 0.125
– 0.30
VDDQ + 0.3
VREF – 0.125
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ
.
Data Sheet
17
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
IDD Specifications and Conditions
Preliminary
4
IDD Specifications and Conditions
Table 12
I
DD Measurement Conditions1)2)
Parameter
Symbol
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.
,
tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2N
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.
;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.
;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
IDD5D
t
CK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
18
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
IDD Specifications and Conditions
Preliminary
Table 12
I
DD Measurement Conditions1)2) (cont’d)
Parameter
Symbol
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 °C
max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) For details and notes see the relevant INFINEON component data sheet
Table 13
IDD Specification
Product Type
Unit
Notes
Organization
256 MB
1 Rank
×64
Max.
280
300
16
256 MB
1 Rank
×64
Max.
320
360
16
512 MB
2 Ranks
×64
Max.
296
316
32
512 MB
2 Ranks
×64
Max.
336
376
32
Symbol
IDD0
1)2)
1)2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
3)
3)
3)
3)
3)
3)
1)
1)
1)
1)
1)
1)
IDD2P
IDD2N
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
128
100
52
160
120
64
256
200
104
40
320
240
128
40
20
20
140
340
360
480
24
160
400
440
520
24
280
356
376
496
40
320
416
456
536
40
1)2)
1)2)
1)2)
3)
3)
1)
1)
16
16
32
32
1)2)
IDD7
840
880
856
896
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
2) For 2-rank modules only: The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) For 2-rank modules only: Both ranks are in the same IDD mode
Data Sheet
19
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
IDD Specifications and Conditions
Preliminary
4.1 IDD Test Conditions
For testing the IDD parameters, the timing parameters as in Table 14 are used.
Table 14
IDD Measurement Test Condition
Symbol
Parameter
-3.7
-5
Unit
PC2-4200-4-4-4 PC2-3200-3-3-3
CAS Latency
CLmin
tCKmin
tRCDmin
tRCmin
4
3
tCK
ns
ns
ns
Clock Cycle Time
3.75
15
60
5
Active to Read or Write delay
15
60
Active to Active / Auto-Refresh command
period
Active bank A to Active bank B command
delay
tRRDmin
10
10
ns
Active to Precharge Command
Precharge Command Period
tRASmin
tRPmin
45
45
ns
ns
ns
15
15
Auto-Refresh to Active / Auto-Refresh
command period
tRFCmin
105
105
Average periodic Refresh interval
tREFI
7.8
7.8
µs
4.2
ODT (On Die Termination) Current
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A[6,2] in the EMRS(1) a
“weak” or “strong” termination can be selected. The
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving “0” or
“1”, as long a ODT is enabled during a given period of
time.
Table 15
ODT current per terminated pin
Parameter
Symbol min.
typ.
max. Unit
EMRS(1) State
Enabled ODT current per DQ
IODTO
5
6
7.5
mA/DQ A6 = 0, A2 = 1
ODT is HIGH; Data Bus inputs are FLOATING
2.5
10
5
3
3.75 mA/DQ A6 = 1, A2 = 0
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
IODTT
12
6
15
mA/DQ A6 = 0, A2 = 1
mA/DQ A6 = 1, A2 = 0
7.5
Note:For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
20
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Electrical Characteristics & AC Timings
Preliminary
5
Electrical Characteristics & AC Timings
Table 16
AC Timing - Absolute Specifications −5/−3.71)
Symbol −3.7
Parameter
−5
Unit Notes
PC2-4200M
PC2-3200M
Min.
−600
2
Min.
-500
2
Max.
+500
—
Max.
+600
—
DQ output access time from CK/CK tAC
CAS A to CAS B Command Period tCCD
ps
tCK
tCK
CK, CK high-level width
Clock cycle time
tCH
0.45
5000
3750
3
0.55
8000
8000
—
0.45
5000
5000
3
0.55
8000
8000
—
2)
tCK3
tCK4
tCKE
ps
3)
ps
CKE minimum high and low pulse
width
tCK
CK, CK low-level width
tCL
0.45
0.55
—
0.45
0.55
—
tCK
tCK
Auto precharge write recovery +
precharge time
tDAL
WR + tRP
WR + tRP
Minimum time clocks remain ON
tDELAY
tIS + tCK + tIH
—
tIS + tCK+ tIH
—
ns
after CKE asynchronously drops low
DQ and DM input hold time
tDH
225
—
—
275
—
—
ps
DQ and DM input pulse width (each tDIPW
0.35
0.35
tCK
input)
DQS output access time from CK/CK tDQSCK
−450
+450
−500
+500
ps
DQS input low (high) pulse width
(write cycle)
tDQSL,H 0.35
—
0.35
—
tCK
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSQ
—
300
—
350
ps
Write command to 1st DQS latching tDQSS
WL - 0.25
WL + 0.25 WL − 0.25 WL + 0.25 tCK
transition
DQ and DM input setup time
tDS
100
0.2
—
—
150
0.2
—
—
ps
DQS falling edge hold time from CLK tDSH
tCK
(write cycle)
DQS falling edge to CLK setup time tDSS
0.2
—
0.2
—
tCK
(write cycle)
Clock Half Period
tHP
min. (tCL, tCH)
min. (tCL, tCH)
tCK
Data-out high-impedance time from tHZ
—
tACmax
—
tACmax
ps
CK/CK
Address and control input hold time tIH
375
0.6
—
—
475
0.6
—
—
ps
Control and Addr. input pulse width tIPW
tCK
(each input)
Address and control input setup time tIS
250
—
350
—
ps
ps
ps
tCK
DQ low-impedance from CK / CK
DQS low-impedance from CK / CK
tLZ(DQ)
2×tACmin
tACmax
tACmax
—
2×tACmin
tACmin
2
tACmax
tACmax
—
tLZ(DQS) tACmin
Mode register set command cycle
time
tMRD
2
OCD drive mode output delay
tOIT
0
12
0
12
ns
Data Sheet
21
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Electrical Characteristics & AC Timings
Preliminary
Table 16
AC Timing - Absolute Specifications −5/−3.71)
Symbol −3.7
Parameter
−5
Unit Notes
PC2-4200M
PC2-3200M
Min.
tHP−tQHS
—
Max.
—
Min.
tHP−tQHS
—
Max.
—
Data Output hold time from DQS
Data hold skew factor
tQH
tCK
ps
ns
ns
tQHS
tRAS
tRC
400
70000
—
450
70000
—
Active to Precharge command
45
45
Active to Active/Auto-refresh
command period
60
60
Active to Read or Write delay (with
and without Auto-Precharge) delay
tRCD
tREFI
15
—
15
—
ns
4)
Average Periodic Refresh Interval
—
7.8
3.9
—
—
7.8
3.9
—
µs
5)
—
—
µs
Auto-refresh to Active/Auto-refresh tRFC
105
105
ns
command period
Precharge command period
Read preamble
tRP
15
—
15
—
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
10
1.1
0.60
—
Read postamble
Active bank A to Active bank B
command
Internal read to precharge command tRTP
7.5
—
7.5
—
ns
delay
Write preamble
tWPRE
tWPST
tWR
0.25
0.40
15
—
0.25
0.40
15
—
tCK
tCK
ns
Write postamble
Write recovery time
0.60
—
0.60
—
Internal write to read command delay tWTR
7.5
2
—
10
—
ns
Exit power down to any valid
command
tXARD
—
2
—
tCK
(other than NOP or Deselect)
Exit active power-down mode to read tXARDS
command (slew exit, lower power)
6 − AL
—
—
6 − AL
—
—
tCK
tCK
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
2
Exit Self-Refresh to non-read
command
tXSNR
t
RFC + 10
—
—
t
RFC + 10
—
—
ns
Exit Self-Refresh to read command tXSRD
200
200
tCK
1) For details and notes see the relevant INFINEON component datasheet
2) CL = 3
3) CL = 4 & 5
4) 0 °C ≤ TCASE ≤ 85 °C
5) 85 °C < TCASE ≤ 95 °C
Data Sheet
22
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Electrical Characteristics & AC Timings
Preliminary
Table 17
ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
Min.
2
Max.
Unit
tCK
ns
tAOND
tAON
ODT turn-on delay
ODT turn-on
2
tAC(min)
tAC(max) + 1 ns
tAONPD
ODT turn-on (Power-Down
Modes)
t
AC(min) + 2 ns
2 tCK + tAC(max) + 1 ns
ns
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
2.5
2.5
tCK
ns
ns
tAC(min)
tAC(max) + 0.6 ns
tAOFPD
ODT turn-off delay (Power-Down tAC(min) + 2 ns
2.5 tCK + tAC(max) + 1 ns
Modes)
tANPD
tAXPD
ODT to Power Down Mode Entry 3
Latency
—
—
tCK
tCK
ODT Power Down Exit Latency
8
Data Sheet
23
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
SPD Codes
Preliminary
6
SPD Codes
Table 18
SPD Codes for PC2-4200M and PC2-3200M
Product Type
Organization
512 MByte
×64
256 MByte
×64
512 MB
256 MB
×64
×64
2 Ranks (×16)
1 Rank (×16)
2 Ranks (×16)
1 Rank (×16)
Label Code
PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333
Rev 1.1 Rev 1.1 Rev 1.1 Rev 1.1
HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX
Jedec SPD Revision
Byte# Description
0
Programmed SPD Bytes in
80
08
08
80
08
08
80
08
08
80
08
08
80
08
08
80
08
08
80
08
08
80
08
08
80
08
08
80
08
08
80
08
08
80
08
08
E2PROM
1
Total number of Bytes in
E2PROM
2
Memory Type (DDR = 07h)
Number of Row Addresses
3
0D 0D 0D 0D 0D 0D 0D 0D 0D 0D 0D 0D
4
Number of Column Addresses 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A
5
Number of DIMM Ranks
Data Width
61
40
00
05
61
40
00
05
61
40
00
05
60
40
00
05
60
40
00
05
60
40
00
05
61
40
00
05
61
40
00
05
50
60
61
40
00
05
50
60
60
40
00
05
50
60
60
40
00
05
50
60
60
40
00
05
50
60
6
7
not used
8
Interface Voltage Levels
9
t
CK @ CLmax (Byte 18) [ns]
AC SDRAM @ CLmax (Byte
3D 3D 3D 3D 3D 3D 50
10
t
50
50
50
50
50
50
60
18) [ns]
11
Error Correction Support (non- 00
/ ECC)
00
00
00
00
00
00
00
00
00
00
00
12
13
14
15
16
17
Refresh Rate/Type
82
10
82
10
00
00
82
10
00
00
82
10
00
00
82
10
00
00
82
10
00
00
82
10
00
00
82
10
00
00
82
10
00
00
82
10
00
00
82
10
00
00
82
10
00
00
Primary SDRAM Width
Error Checking SDRAM Width 00
not used
00
Burst Length Supported
0C 0C 0C 0C 0C 0C 0C 0C 0C 0C 0C 0C
Number of Banks on SDRAM 04
Device
04
04
04
04
04
04
04
04
04
04
04
18
19
20
21
CAS Latency
38
00
08
00
38
00
08
00
38
00
08
00
38
00
08
00
38
00
08
00
38
00
08
00
38
00
08
00
38
00
08
00
38
00
08
00
38
00
08
00
38
00
08
00
38
00
08
00
not used
DIMM Type Information
DIMM Attributes
Data Sheet
24
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
SPD Codes
Preliminary
Table 18
SPD Codes for PC2-4200M and PC2-3200M
Product Type
Organization
512 MByte
×64
256 MByte
×64
512 MB
256 MB
×64
×64
2 Ranks (×16)
1 Rank (×16)
2 Ranks (×16)
1 Rank (×16)
Label Code
PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333
Rev 1.1 Rev 1.1 Rev 1.1 Rev 1.1
HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX
Jedec SPD Revision
Byte# Description
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Component Attributes
01
01
01
01
01
01
01
01
50
60
50
60
01
50
60
50
60
01
50
60
50
60
01
50
60
50
60
01
50
60
50
60
t
t
t
t
t
t
t
t
CK @ CLmax -1 (Byte 18) [ns] 3D 3D 3D 3D 3D 3D 50
AC SDRAM @ CLmax -1 [ns]
50
50
50
60
50
50
60
50
50
60
50
50
60
50
50
60
60
50
60
CK @ CLmax -2 (Byte 18) [ns] 50
AC SDRAM @ CLmax -2 [ns]
RPmin [ns]
60
3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C
28 28 28 28 28 28 28 28 28 28 28 28
RRDmin [ns]
RCDmin [ns]
3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
RASmin [ns]
Module Density per Rank
tAS, tCS [ns]
40
25
37
10
22
40
25
37
10
22
40
25
37
10
22
40
25
37
10
22
40
25
37
10
22
40
25
37
10
22
40
35
47
15
27
40
35
47
15
27
40
35
47
15
27
40
35
47
15
27
40
35
47
15
27
40
35
47
15
27
tAH, tCH [ns]
tDS [ns]
tDH [ns]
tWR [ns]
tWTR [ns]
tRTP [ns]
3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C
1E 1E 1E 1E 1E 1E 28 28 28 28 28 28
1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E
Analysis Characteristics
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
t
t
t
t
t
t
RC and tRFC extension
RCmin [ns]
3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C
RFCmin [ns]
69
80
69
80
69
80
69
80
69
80
69
80
69
80
69
80
23
69
80
23
69
80
23
69
80
23
69
80
23
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
1E 1E 1E 1E 1E 1E 23
28
00
28
00
53
72
52
28
00
53
72
52
28
00
53
72
52
28
00
53
72
52
28
00
53
72
52
2D 2D 2D 2D 2D 2D
PLL Relock Time
00
51
72
42
00
51
72
42
00
51
72
42
00
51
72
42
00
51
72
42
00
51
72
42
Tc(max) Delta / DT4R4W Delta 53
Psi(T-A) DRAM
DT0
72
52
Data Sheet
25
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
SPD Codes
Preliminary
Table 18
SPD Codes for PC2-4200M and PC2-3200M
Product Type
Organization
512 MByte
×64
256 MByte
×64
512 MB
256 MB
×64
×64
2 Ranks (×16)
1 Rank (×16)
2 Ranks (×16)
1 Rank (×16)
Label Code
PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333
Rev 1.1 Rev 1.1 Rev 1.1 Rev 1.1
HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX
2B 2B 2B 2B 2B 2B 23 23 23 23 23 23
Jedec SPD Revision
Byte# Description
50
DT2N (UDIMM) or DT2Q
(RDIMM)
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
DT2P
1D 1D 1D 1D 1D 1D 1D 1D 1D 1D 1D 1D
1D 1D 1D 1D 1D 1D 19 19 19 19 19 19
1C 1C 1C 1C 1C 1C
16 16 16 16 16 16
2E 2E 2E 2E 2E 2E
DT3N
DT3Pfast
23
16
36
23
16
36
23
16
36
23
16
36
23
16
36
23
16
36
DT3Pslow
DT4R / DT4R4W Sign
DT5B
1C 1C 1C 1C 1C 1C 1A 1A 1A 1A 1A 1A
DT7
30
00
00
00
00
11
30
00
00
00
00
11
30
00
00
00
00
11
30
00
00
00
00
11
30
00
00
00
00
11
30
00
00
00
00
11
2D 2D 2D 2D 2D 2D
Psi(ca) PLL
Psi(ca) REG
DTPLL
00
00
00
00
11
00
00
00
00
11
12
00
00
00
00
11
12
00
00
00
00
11
11
00
00
00
00
11
11
00
00
00
00
11
11
DTREG / Toggle Rate
SPD Revision
Checksum of Byte 0-62
C0 C0 C0 BF BF BF 12
JEDEC ID Code of Infineon (1) C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1
JEDEC ID Code of Infineon (2) 00
JEDEC ID Code of Infineon (3) 00
JEDEC ID Code of Infineon (4) 00
JEDEC ID Code of Infineon (5) 00
JEDEC ID Code of Infineon (6) 00
JEDEC ID Code of Infineon (7) 00
JEDEC ID Code of Infineon (8) 00
Module Manufacturer Location xx
00
00
00
00
00
00
00
xx
36
34
54
36
00
00
00
00
00
00
00
xx
36
34
54
36
00
00
00
00
00
00
00
xx
36
34
54
33
00
00
00
00
00
00
00
xx
36
34
54
33
00
00
00
00
00
00
00
xx
36
34
54
33
00
00
00
00
00
00
00
xx
36
34
54
36
00
00
00
00
00
00
00
xx
36
34
54
36
00
00
00
00
00
00
00
xx
36
34
54
36
00
00
00
00
00
00
00
xx
00
00
00
00
00
00
00
xx
00
00
00
00
00
00
00
xx
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
36
34
54
36
36
34
54
33
36
34
54
33
36
34
54
33
Data Sheet
26
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
SPD Codes
Preliminary
Table 18
SPD Codes for PC2-4200M and PC2-3200M
Product Type
Organization
512 MByte
×64
256 MByte
×64
512 MB
256 MB
×64
×64
2 Ranks (×16)
1 Rank (×16)
2 Ranks (×16)
1 Rank (×16)
Label Code
PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333
Rev 1.1 Rev 1.1 Rev 1.1 Rev 1.1
HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX
Jedec SPD Revision
Byte# Description
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Product Type, Char 5
34
30
32
30
34
30
32
30
34
30
32
30
32
30
30
30
32
30
30
30
32
30
30
30
34
30
32
30
34
30
32
30
34
30
32
30
32
30
30
30
32
30
30
30
32
30
30
30
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
4C 4B 48
4C 4B 48
4C 4B 48
4C 4B 48
4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D
33
33
33
33
33
33
35
35
41
20
20
20
20
20
20
0x
xx
xx
35
41
20
20
20
20
20
20
0x
xx
xx
35
41
20
20
20
20
20
20
0x
xx
xx
35
41
20
20
20
20
20
20
0x
xx
xx
35
41
20
20
20
20
20
20
0x
xx
xx
2E 2E 2E 2E 2E 2E 41
37
41
20
20
20
20
0x
37
41
20
20
20
20
0x
xx
xx
37
41
20
20
20
20
0x
xx
xx
37
41
20
20
20
20
0x
xx
xx
37
41
20
20
20
20
0x
xx
xx
37
41
20
20
20
20
0x
xx
xx
20
20
20
20
20
20
0x
xx
xx
Test Program Revision Code xx
Module Manufacturing Date
Year
xx
94
Module Manufacturing Date
Week
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
95
96
97
98
Module Serial Number (1)
Module Serial Number (2)
Module Serial Number (3)
Module Serial Number (4)
Not used
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
99 -
127
128- BLANK
255
FF FF FF FF FF FF FF FF FF FF FF FF
Data Sheet
27
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Package Outlines
Preliminary
7
Package Outlines
3.8 MAX.
1.65-0.25
±0.15
54
B
0.1
C
±0.03
0.62
C
A
0.1
±0.08
0.8
(44.72)
±0.02
43.38
106 x 0.4 = 42.4
M
M
D
0.1 C B
B
0.4
A
A
1
107
214
B
108
Detail of contacts
A-A
B-B
±0.02
1.3
M
M
E
0.1 A B
Contact Area
0.4
±0.02
0.26
0.06 C D E 107x
Burnished, no burr allowed
GLD09638
Figure 4
PCB Raw Card A Component Placement L-DIM-214-1
Data Sheet
32
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Package Outlines
Preliminary
2.34 MAX.
1.65-0.25
±0.15
54
B
0.1
C
±0.03
0.62
C
A
0.1
±0.08
0.8
(44.72)
±0.02
43.38
106 x 0.4 = 42.4
M
M
D
0.1 C B
B
0.4
A
A
107
214
1
B
108
Detail of contacts
A-A
B-B
±0.02
1.3
M
M
E
0.1 A B
Contact Area
0.4
±0.02
0.26
0.06 C D E 107x
Burnished, no burr allowed
GLD09668
Figure 5
PCB Raw Card B Component Placement L-DIM-214-2
Data Sheet
33
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Preliminary
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon’s nomenclature uses simple coding combined with some propriatory coding. Table 20 provides examples
for module and component product type number as well as the field number. The detailed field description together
with possible values and coding explanation is listed for modules in Table 21 and for components in Table 22.
Table 20
Nomenclature Fields and Examples
Field Number
Example for
1
2
3
T
T
4
5
6
7
0
0
8
9
10
–5
–5
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
64
512
0
2
K
A
M
C
–A
16
1) Multiplying “Memory Density per I/O” with “Module Data
Width” and dividing by 8 for Non-ECC and 9 for ECC
modules gives the overall module memory density in
MBytes as listed in column “Coding”.
Table 21
DDR2 DIMM Nomenclature
Values Coding
Field Description
1
INFINEON
HYS
Constant
Modul Prefix
2
Module Data
Width [bit]
64
72
T
Non-ECC
ECC
Table 22
DDR2 DRAM Nomenclature
Values Coding
Field Description
3
4
DRAM
Technology
DDR2
1
INFINEON
HYB
Constant
Component Prefix
Memory Density
per I/O [Mbit];
32
256 MByte
512 MByte
1 GByte
2
3
4
Interface Voltage [V] 18
DRAM Technology
SSTL1.8
DDR2
256 Mbit
512 Mbit
1 Gbit
2 Gbit
×4
64
T
Module Density1)
128
256
0 .. 9
Component Density 256
2 GByte
[Mbit]
512
5
6
Raw Card
Generation
look up table
1G
2G
Number of Module 0, 2, 4 1, 2, 4
Ranks
5+6 Number of I/Os
40
80
16
×8
7
8
Product Variations 0 .. 9
look up table
×16
Package,
A .. Z
look up table
7
8
Product Variations 0 .. 9
look up table
First
Lead-Free Status
Die Revision
A
B
C
9
Module Type
S
SO-DIMM
Second
M
Micro-DIMM
Registered
Unbuffered
PC2–4200 4–4–4
PC2–3200 3–3–3
First
9
Package,
FBGA,
lead-containing
R
Lead-Free Status
U
F
FBGA, lead-free
DDR2-533
10
11
Speed Grade
Die Revision
–3.7
–5
–A
–B
10
11
Speed Grade
–3.7
–5
DDR2-400
N/A for Components
Second
Data Sheet
34
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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