HYB25D512400BC-5 [INFINEON]

512Mbit Double Data Rate SDRAM; 512Mbit的双数据速率SDRAM
HYB25D512400BC-5
型号: HYB25D512400BC-5
厂家: Infineon    Infineon
描述:

512Mbit Double Data Rate SDRAM
512Mbit的双数据速率SDRAM

存储 内存集成电路 动态存储器 双倍数据速率 时钟
文件: 总90页 (文件大小:3133K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Data Sheet, Rev. 1.2, June 2004  
HYB25D512[40/80/16]0B[C/T]  
HYB25D512[40/80/16]0B[E/F]  
512Mbit Double Data Rate SDRAM  
DDR SDRAM  
Memory Products  
N e v e r s t o p t h i n k i n g .  
Edition 2004-06  
Published by Infineon Technologies AG,  
St.-Martin-Strasse 53,  
81669 München, Germany  
© Infineon Technologies AG 2004.  
All Rights Reserved.  
Attention please!  
The information herein is given to describe certain components and shall not be considered as a guarantee of  
characteristics.  
Terms of delivery and rights to technical change reserved.  
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding  
circuits, descriptions and charts stated herein.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest  
Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in  
question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the express written  
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure  
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support  
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may  
be endangered.  
Data Sheet, Rev. 1.2, June 2004  
HYB25D512[40/80/16]0B[C/T]  
HYB25D512[40/80/16]0B[E/F]  
512Mbit Double Data Rate SDRAM  
DDR SDRAM  
Memory Products  
N e v e r s t o p t h i n k i n g .  
HYB25D512[40/80/16]0B[C/T], HYB25D512[40/80/16]0B[E/F],  
Revision History:  
Rev. 1.2  
2004-06  
Previous Version:  
Rev. 1.1  
2004-06  
Page  
1
Subjects (major changes since last revision)  
Editorial Change  
67  
Added AC Timing Table  
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Template: mp_a4_v1.0_2003-04-25.fm  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Table of Contents  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3
3.1  
3.2  
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Pre charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
3.2.1  
3.2.2  
3.2.3  
3.2.4  
3.3  
3.3.1  
3.3.2  
3.4  
3.5  
3.5.1  
3.5.2  
3.5.3  
3.5.4  
3.5.5  
3.5.6  
3.6  
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
4.1  
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
5
Normal Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Weak Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67  
5.1  
5.2  
5.2.1  
IDD Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
6
7
8
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
System Characteristics for DDR SDRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88  
Data Sheet  
5
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
List of Figures  
Figure 1  
Figure 2  
Figure 3  
Figure 4  
Figure 5  
Figure 6  
Figure 7  
Figure 8  
Figure 9  
Pin Configuration P-TFBGA-60-9 Top View, see the balls throught the package . . . . . . . . . . . . . 16  
Pin Configuration P-TSOPII-66-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Block Diagram 512Mbit 128 Mbit ×4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Block Diagram 512Mbit 64 Mbit ×8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Block Diagram 512Mbit 32 Mbit ×16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Required CAS Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
t
RCD and tRRD Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Figure 10 Read Burst: CAS Latencies (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 11 Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . 34  
Figure 12 Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 13 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . 36  
Figure 14 Terminating a Read Burst: CAS Latencies (Burst Length = 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Figure 15 Read to Write: CAS Latencies (Burst Length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Figure 16 Read to Precharge: CAS Latencies (Burst Length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Figure 17 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Figure 18 Write Burst (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Figure 19 Write to Write (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Figure 20 Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Figure 21 Random Write Cycles (Burst Length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Figure 22 Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . 46  
Figure 23 Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8). . . . . . . . . . . . . . . . . . . . . . . . . . 47  
Figure 24 Write to Read: Minimum DQSS, Odd Number of Data, Interupting . . . . . . . . . . . . . . . . . . . . . . . . 48  
Figure 25 Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8) . . . . . . . . . . . . 49  
Figure 26 Write to Precharge: Non-Interrupting (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
Figure 27 Write to Precharge: Interrupting (Burst Length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
Figure 28 Write to Precharge: Minimum DQSS, Odd Number of Data, Interrupting. . . . . . . . . . . . . . . . . . . . 52  
Figure 29 Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8) . . . . . . . . . 53  
Figure 30 Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
Figure 31 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
Figure 32 Clock frequency change in pre charge power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Figure 33 Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
Figure 34 Normal Strength Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Figure 35 Normal Strength Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Figure 36 Weak Strength Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65  
Figure 37 Weak Strength Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65  
Figure 38 AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67  
Figure 39 Data Input (Write), Timing Burst Length = 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
Figure 40 Data Output (Read), Timing Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
Figure 41 Initialize and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
Figure 42 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
Figure 43 Auto Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
Figure 44 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
Figure 45 Read without Auto Precharge (Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78  
Figure 46 Read with Auto Pre charge (Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79  
Figure 47 Bank Read Access (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80  
Figure 48 Write without Auto Precharge (Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
Figure 49 Write with Auto Pre charge (Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82  
Figure 50 Bank Write Access (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83  
Figure 51 Write DM Operation (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84  
Figure 52 Pullup slew rate test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
Figure 53 Pulldown slew rate test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
Data Sheet  
6
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Figure 54 Package Outline of P-TFBGA-60-[9/22] (green/non-green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88  
Figure 55 Package Outline of P-TSOPII-66-1 (Lead-Free/Lead-Containing) . . . . . . . . . . . . . . . . . . . . . . . . . 89  
Data Sheet  
7
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
List of Tables  
Table 1  
Table 2  
Table 3  
Table 4  
Table 5  
Table 6  
Table 7  
Table 9  
Table 8  
Table 11  
Table 10  
Table 12  
Table 13  
Table 14  
Table 15  
Table 15  
Table 17  
Table 16  
Table 18  
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Input/Output Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . 56  
Truth Table 2: Clock Enable (CKE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . 58  
Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
Electrical Characteristics and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Pull-down and Pull-up Process Variations and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64  
Normal Strength Pull-down and Pull-up Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64  
Weak Strength Driver Pull-down and Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66  
Figure 38 AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100 . . . . . . . . . . . . . . . . . . . . 67  
Table 19  
Table 20  
Table 21  
Table 22  
Table 23  
Table 24  
Table 25  
Table 26  
Table 27  
Table 28  
I
I
DD Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70  
DD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71  
Input Slew Rate for DQ, DQS, and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85  
Input Setup & Hold Time Derating for Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85  
Input/Output Setup and Hold TIme Derating for Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85  
Input/Output Setup and Hold Derating for Rise/Fall Delta Slew Rate. . . . . . . . . . . . . . . . . . . . . . . 85  
Output Slew Rate Characteristrics (×4, ×8 Devices only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86  
Output Slew Rate Characteristics (×16 Devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86  
Output Slew Rate Matching Ratio Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86  
TFBGA Common Package Properties (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88  
Data Sheet  
8
Rev. 1.2, 2004-06  
512Mbit Double Data Rate SDRAM  
DDR SDRAM  
HYB25D512[40/80/16]0B[C/T]  
HYB25D512[40/80/16]0B[E/F]  
1
Overview  
1.1  
Features  
Double data rate architecture: two data transfers per clock cycle  
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the  
receiver  
DQS is edge-aligned with data for reads and is center-aligned with data for writes  
Differential clock inputs (CK and CK)  
Four internal banks for concurrent operation  
Data mask (DM) for write data  
DLL aligns DQ and DQS transitions with CK transitions  
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS  
Burst Lengths: 2, 4, or 8  
CAS Latency: (1.5), 2, 2.5, 3  
Auto Pre charge option for each burst access  
Auto Refresh and Self Refresh Modes  
7.8 µs Maximum Average Periodic Refresh Interval  
2.5 V (SSTL_2 compatible) I/O  
V
V
DDQ = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400  
DD = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400  
P-TFBGA-60 and P-TSOPII-66 package  
Table 1  
Performance  
Product Type Speed Code  
Speed Grade  
-5  
-6  
-7  
Unit  
DDR400B  
200  
DDR333B  
166  
DDR266A  
143  
max. Clock Frequency  
@CL3  
@CL2.5  
@CL2  
fCK3  
MHz  
MHz  
MHz  
fCK2.5  
fCK2  
166  
166  
143  
133  
133  
133  
Data Sheet  
9
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Overview  
1.2  
Description  
The 512Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing  
536,870,912 bits. It is internally configured as a quad-bank DRAM.  
The 512Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.  
The double data rate architecture is essentially a 2n pre fetch architecture with an interface designed to transfer  
two data words per clock cycle at the I/O pins. A single read or write access for the 512Mbit Double Data Rate  
SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and  
two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.  
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.  
DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS  
is edge-aligned with data for Reads and center-aligned with data for Writes.  
The 512Mbit Double Data Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going  
HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are  
registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is  
referenced to both edges of DQS, as well as to both edges of CK.  
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and  
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration  
of an Active command, which is then followed by a Read or Write command. The address bits registered  
coincident with the Active command are used to select the bank and row to be accessed. The address bits  
registered coincident with the Read or Write command are used to select the bank and the starting column location  
for the burst access.  
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto  
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst  
access.  
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation,  
thereby providing high effective bandwidth by hiding row precharge and activation time.  
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the  
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.  
Note:The functionality described and the timing specifications included in this data sheet are for the DLL Enabled  
mode of operation.  
Table 2  
Ordering Information  
Part Number1)  
Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed  
Package  
Latencies  
(MHz) Latencies  
(MHz)  
HYB25D512800BT–5  
HYB25D512160BT–5  
HYB25D512400BT–6  
HYB25D512800BT–6  
HYB25D512160BT–6  
HYB25D512400BT–7  
HYB25D512400BC–5  
HYB25D512800BC–5  
HYB25D512160BC–5  
HYB25D512400BC–6  
HYB25D512800BC–6  
HYB25D512160BC–6  
×8  
3.0-3-3  
200  
166  
2.5-3-3  
2-3-3  
133  
DDR400B P-TSOPII-66  
×16  
×4  
2.5-3-3  
133  
DDR333  
×8  
×16  
×4  
142  
200  
×4  
3.0-3-3  
2.5-3-3  
2.5-3-3  
2-3-3  
133  
133  
DDR400B P-TFBGA-60  
DDR333  
×8  
×16  
×4  
166  
×8  
×16  
Data Sheet  
10  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Overview  
Table 2  
Ordering Information (cont’d)  
Part Number1)  
Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed  
Package  
Latencies  
(MHz) Latencies  
(MHz)  
HYB25D512400BF–5  
HYB25D512160BF–5  
HYB25D512400BF–6  
HYB25D512800BF–6  
HYB25D512160BF–6  
HYB25D512400BF–5  
HYB25D512800BE–5  
HYB25D512160BE–5  
HYB25D512400BE–6  
HYB25D512800BE–6  
HYB25D512160BE–6  
HYB25D512400BE–7  
×4  
3.0-3-3  
200  
166  
2.5-3-3  
2-3-3  
166  
DDR400B P-TFBGA-60  
×16  
×4  
2.5-3-3  
3.0-3-3  
2.5-3-3  
133  
166  
133  
DDR333  
×8  
×16  
×4  
200  
166  
143  
2.5-3-3  
2-3-3  
DDR400B P-TSOPII-66  
DDR333  
×8  
×16  
×4  
×8  
×16  
×4  
DDR266A  
1) HYB: designator for memory components  
25D: DDR SDRAMs at VDDQ = 2.5 V  
512: 512-Mbit density  
400/800/160: Product variations x4, ×8 and ×16  
B: Die revision B  
C/F/E/T: Package type FBGA and TSOP  
Data Sheet  
11  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
2
Pin Configuration  
The pin configuration of a DDR SDRAM is listed by function in Table 3 (60 pins). The abbreviations used in the  
Pin#/Buffer# column are explained in Table 4 and Table 5 respectively. The pin numbering for FBGA is depicted  
in Figure 1 and that of the TSOP package in Figure 2  
Table 3  
Pin Configuration of DDR SDRAM  
Ball#/Pin#  
Name  
Pin  
Type  
Buffer  
Type  
Function  
Clock Signals  
G2, 45  
CK  
I
I
I
SSTL  
SSTL  
SSTL  
Clock Signal  
G3, 46  
CK  
Complementary Clock Signal  
Clock Enable Rank  
H3, 44  
CKE  
Control Signals  
H7, 23  
G8, 22  
G7, 21  
H8, 24  
RAS  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Row Address Strobe  
Column Address Strobe  
Write Enable  
CAS  
WE  
CS  
Chip Select  
Address Signals  
J8, 26  
J7, 27  
K7, 29  
L8, 30  
L7, 31  
M8, 32  
M2, 35  
L3, 36  
L2, 37  
K3, 38  
K2, 39  
J3, 40  
K8, 28  
BA0  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Bank Address Bus 2:0  
Address Bus 11:0  
BA1  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
AP  
A11  
A12  
J2, 41  
H2, 42  
Address Signal 12  
Note:256 Mbit or larger dies  
Note:128 Mbit or smaller dies  
Address Signal 13  
NC  
NC  
I
F9, 17  
A13  
SSTL  
Note:1 Gbit based dies  
Note:512 Mbit or smaller dies  
NC  
NC  
Data Sheet  
12  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
Table 3  
Pin Configuration of DDR SDRAM  
Ball#/Pin#  
Name  
Pin  
Type  
Buffer  
Type  
Function  
Data Signals ×4 organization  
B7, 5  
DQ0  
DQ1  
DQ2  
DQ3  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
Data Signal 3:0  
D7, 11  
D3, 56  
B3, 62  
Data Strobe ×4 organisation  
E3, 51 DQS I/O  
Data Mask ×4 organization  
F3, 47 DM  
Data Signals ×8 organization  
SSTL  
SSTL  
Data Strobe  
Data Mask  
I
A8, 2  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Signal 7:0  
B7, 5  
C7, 8  
D7, 11  
D3, 56  
C3, 59  
B3, 62  
A2, 65  
Data Strobe ×8 organisation  
E3, 51 DQS I/O  
Data Mask ×8 organization  
F3, 47 DM  
Data Signals ×16 organization  
SSTL  
SSTL  
Data Strobe  
Data Mask  
I
A8, 2  
DQ0  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Signal 15:0  
B9, 4  
DQ1  
B7, 5  
DQ2  
C9, 7  
DQ3  
C7, 8  
DQ4  
D9, 10  
D7, 11  
E9, 13  
E1, 54  
D3, 56  
D1, 57  
C3, 59  
C1, 60  
B3, 62  
B1, 63  
A2, 65  
DQ5  
DQ6  
DQ7  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
Data Sheet  
13  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
Table 3  
Pin Configuration of DDR SDRAM  
Ball#/Pin#  
Name  
Pin  
Type  
Buffer  
Type  
Function  
Data Strobe ×16 organization  
E3, 51  
UDQS  
I/O  
SSTL  
SSTL  
Data Strobe Upper Byte  
Data Strobe Lower Byte  
E7, 16  
LDQS  
I/O  
Data Mask ×16 organization  
F3, 47  
F7, 20  
UDM  
LDM  
I
I
SSTL  
SSTL  
Data Mask Upper Byte  
Data Mask Lower Byte  
Power Supplies  
F1, 49  
VREF  
AI  
I/O Reference Voltage  
A9, B2, C8,  
D2, E8, 3, 9,  
15, 55, 61  
VDDQ  
PWR  
I/O Driver Power Supply  
A7, F8, M3,  
M7, 1, 18, 33  
VDD  
PWR  
PWR  
Power Supply  
Power Supply  
A1, B8, C2,  
D8, E2, 6, 12,  
52, 58, 64  
VSSQ  
F2, 34  
VSS  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
PWR  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
Power Supply  
Not Connected  
A2, 65  
Not Connected  
Note:×4 organization  
Not Connected  
A8, 2  
Note:×4 organization  
Not Connected  
B1, 63  
B9, 4  
Note:×8 and ×4 organisation  
Not Connected  
Note:×8 and ×4 organization  
Not Connected  
C1, 60  
C3, 59  
C7, 8  
Note:×8 and ×4 organization  
Not Connected  
Note:×4 organization  
Not Connected  
Note:×4 organization  
Not Connected  
C9, 7  
Note:×8 and ×4 organization  
Not Connected  
D1, 57  
D9, 10  
E1, 54  
Note:×8 and ×4 organization  
Not Connected  
Note:×8 and ×4 organization  
Not Connected  
Note:×8 and ×4 organization  
Data Sheet  
14  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
Table 3  
Pin Configuration of DDR SDRAM  
Ball#/Pin#  
Name  
Pin  
Type  
Buffer  
Type  
Function  
E7, 16  
E9, 13  
F7, 20  
NC  
NC  
NC  
NC  
NC  
Not Connected  
Note:×8 and ×4 organization  
Not Connected  
NC  
NC  
Note:×8 and ×4 organization  
Not Connected  
Note:×8 and ×4 organization  
Not Connected  
F9, 14, 17, 19, NC  
25,43, 50, 53  
Note:×168 and ×4 organization  
Table 4  
Abbreviations for Pin Type  
Description  
Abbreviation  
I
Standard input-only pin. Digital levels.  
O
Output. Digital levels.  
I/O is a bidirectional input/output signal.  
Input. Analog levels.  
Power  
I/O  
AI  
PWR  
GND  
NC  
Ground  
Not Connected  
Table 5  
Abbreviation  
SSTL  
Abbreviations for Buffer Type  
Description  
Serial Stub Terminated Logic (SSTL2)  
Low Voltage CMOS  
CMOS Levels  
LV-CMOS  
CMOS  
OD  
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and  
allows multiple devices to share as a wire-OR.  
Data Sheet  
15  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
ꢂꢂꢈ  
ꢂꢂ  
ꢅꢅ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢂꢂ  
ꢅꢅ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢅꢈꢔ  
ꢅꢈꢆ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢅꢈꢖ  
ꢊꢋꢀꢋ  
ꢅꢈꢐ  
ꢅꢈꢂ  
ꢅꢃ  
ꢅꢈꢆ  
ꢊꢋꢀꢋ  
ꢅꢈꢏ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢗꢍ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢅꢈꢇ  
ꢅꢈꢕ  
ꢅꢈꢒ  
ꢅꢈꢂ  
ꢅꢃ  
ꢅꢈꢏ  
ꢅꢈꢐ  
ꢅꢈꢖ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢗꢍ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢂꢂꢈ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢂꢂ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢅꢅꢈ  
ꢅꢅ  
ꢂꢂꢈ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢂꢂ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢅꢅꢈ  
ꢅꢅ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢌꢍꢎ  
ꢌꢍꢎ  
ꢊꢀꢚꢁꢏꢖ  
ꢊꢀꢚꢁꢏꢖ  
ꢀꢉ  
ꢀꢉ  
ꢀꢁꢂ  
ꢀꢂ  
ꢀꢉ  
ꢀꢉ  
ꢀꢁꢂ  
ꢀꢂ  
ꢊꢀ,ꢁꢏꢐ ꢀꢉꢍ  
ꢌꢁꢂ  
ꢘꢁꢏ  
ꢊꢀ,ꢁꢏꢐ ꢀꢉꢍ  
ꢌꢁꢂ  
ꢘꢁꢏ  
ꢁꢏꢏ  
ꢁꢑ  
ꢁꢓ  
ꢁꢔ  
ꢘꢁꢆ  
ꢁꢏꢏ  
ꢁꢑ  
ꢁꢓ  
ꢁꢔ  
ꢘꢁꢆ  
ꢁꢆ ꢁꢏꢆꢙꢁꢄ  
ꢁꢆ ꢁꢏꢆꢙꢁꢄ  
ꢁꢇ  
ꢁꢕ  
ꢁꢐ  
ꢁꢏ  
ꢁꢖ  
ꢁꢇ  
ꢁꢕ  
ꢁꢐ  
ꢁꢏ  
ꢁꢖ  
ꢂꢂ  
ꢅꢅ  
ꢂꢂ  
ꢅꢅ  
ꢀꢁꢂꢃ  
ꢀꢁꢄꢃ  
ꢁꢒ  
ꢁꢒ  
ꢂꢂꢈ  
ꢂꢂ  
ꢅꢅ  
ꢅꢅꢈ  
ꢅꢈꢏꢕ  
ꢅꢈꢆ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢅꢈꢏꢒ  
ꢅꢈꢏꢐ  
ꢅꢈꢏꢆ  
ꢅꢈꢏꢖ  
ꢅꢈꢏꢏ  
ꢅꢈꢓ  
ꢅꢈꢐ  
ꢅꢈꢒ  
ꢅꢈꢇ  
ꢞꢅꢈꢂ  
ꢞꢅꢃ  
ꢗꢍ  
ꢅꢈꢏ  
ꢅꢈꢖ  
ꢂꢂꢈ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢂꢂ  
ꢅꢅꢈ  
ꢂꢂꢈ  
ꢅꢅꢈ  
ꢅꢅ  
ꢅꢈꢕ  
ꢅꢈꢑ  
 ꢅꢈꢂ  
 ꢅꢃ  
ꢀꢉ  
ꢅꢈꢔ  
ꢌꢍꢎ  
ꢊꢀꢚꢁꢏꢖ  
ꢀꢉ  
ꢀꢁꢂ  
ꢀꢂ  
ꢊꢀ,ꢁꢏꢐ ꢀꢉꢍ  
ꢌꢁꢂ  
ꢘꢁꢏ  
ꢁꢏꢏ  
ꢁꢑ  
ꢁꢓ  
ꢁꢔ  
ꢘꢁꢆ  
ꢁꢆ ꢁꢏꢆꢙꢁꢄ  
ꢁꢇ  
ꢁꢕ  
ꢁꢐ  
ꢁꢏ  
ꢁꢖ  
ꢂꢂ  
ꢅꢅ  
ꢀꢁꢅꢆꢃ  
ꢁꢒ  
ꢃꢄꢄꢅꢆꢆꢇꢆ  
Figure 1  
Pin Configuration P-TFBGA-60-9 Top View, see the balls throught the package  
Data Sheet  
16  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
ꢇꢒ!ꢃ"!#!ꢒ  
ꢖꢐ!ꢃ"!#!ꢑ  
ꢏꢇ!ꢃ"!#!ꢏꢇ  
ꢅꢅ  
ꢊꢋꢀꢋ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢆ  
ꢂꢂꢈ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢏ  
ꢂꢂꢈ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢅꢅ  
ꢅꢈꢆ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢏ  
ꢂꢂꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢐ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢖ  
ꢂꢂꢈ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢅꢅ  
ꢅꢈꢆ  
ꢅꢅꢈ  
ꢅꢈꢏ  
ꢅꢈꢐ  
ꢂꢂꢈ  
ꢅꢈꢖ  
ꢅꢈꢒ  
ꢅꢅꢈ  
ꢅꢈꢕ  
ꢅꢈꢇ  
ꢂꢂꢈ  
ꢅꢈꢔ  
ꢊꢋꢀꢋ  
ꢅꢅꢈ  
ꢞꢅꢈꢂ  
ꢇꢇ  
ꢇꢕ  
ꢇꢒ  
ꢇꢖ  
ꢇꢐ  
ꢇꢏ  
ꢇꢆ  
ꢕꢓ  
ꢕꢑ  
ꢕꢔ  
ꢕꢇ  
ꢕꢕ  
ꢕꢒ  
ꢕꢖ  
ꢕꢐ  
ꢕꢏ  
ꢕꢆ  
ꢒꢓ  
ꢒꢑ  
ꢒꢔ  
ꢒꢇ  
ꢒꢕ  
ꢒꢒ  
ꢒꢖ  
ꢒꢐ  
ꢒꢏ  
ꢒꢆ  
ꢖꢓ  
ꢖꢑ  
ꢖꢔ  
ꢖꢇ  
ꢖꢕ  
ꢖꢒ  
ꢂꢂ  
ꢂꢂ  
ꢂꢂ  
ꢅꢈꢏꢕ  
ꢂꢂꢈ  
ꢅꢈꢏꢒ  
ꢅꢈꢏꢖ  
ꢅꢅꢈ  
ꢅꢈꢏꢐ  
ꢅꢈꢏꢏ  
ꢂꢂꢈ  
ꢅꢈꢏꢆ  
ꢅꢈꢓ  
ꢅꢅꢈ  
ꢅꢈꢑ  
ꢊꢋꢀꢋ  
ꢂꢂꢈ  
 ꢅꢈꢂ  
ꢊꢋꢀꢋ  
ꢌꢍꢎ  
ꢂꢂ  
ꢅꢈꢔ  
ꢂꢂꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢇ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢕ  
ꢂꢂꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢒ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢂꢂꢈ  
ꢅꢈꢂ  
ꢊꢋꢀꢋ  
ꢌꢍꢎ  
ꢂꢂ  
ꢊꢋꢀꢋ  
ꢂꢂꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢖ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢂꢂꢈ  
ꢊꢋꢀꢋ  
ꢅꢈꢐ  
ꢅꢅꢈ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢂꢂꢈ  
ꢅꢈꢂ  
ꢊꢋꢀꢋ  
ꢌꢍꢎ  
ꢂꢂ  
ꢏꢆ  
ꢏꢏ  
ꢏꢐ  
ꢏꢖ  
ꢏꢒ  
ꢏꢕ  
ꢏꢇ  
ꢏꢔ  
ꢏꢑ  
ꢏꢓ  
ꢐꢆ  
ꢐꢏ  
ꢐꢐ  
ꢐꢖ  
ꢐꢒ  
ꢐꢕ  
ꢐꢇ  
ꢐꢔ  
ꢐꢑ  
ꢐꢓ  
ꢖꢆ  
ꢖꢏ  
ꢖꢐ  
ꢖꢖ  
ꢊꢋꢀꢋꢚꢁꢏꢖ ꢊꢋꢀꢋꢚꢁꢏꢖ ꢊꢋꢀꢋꢚꢁꢏꢖ  
ꢅꢅ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢗꢍ  
ꢅꢅ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢗꢍ  
ꢅꢅ  
ꢊꢋꢀꢋ  
ꢞꢅꢃ  
ꢗꢍ  
 ꢅꢃ  
ꢀꢉ  
ꢅꢃ  
ꢅꢃ  
ꢀꢉ  
ꢀꢉ  
ꢀꢁꢂ  
ꢌꢁꢂ  
ꢀꢂ  
ꢀꢁꢂ  
ꢌꢁꢂ  
ꢀꢂ  
ꢀꢁꢂ  
ꢌꢁꢂ  
ꢀꢂ  
ꢀꢉ  
ꢀꢉ  
ꢀꢉ  
ꢀꢉꢍ  
ꢊꢋꢀꢋ  
ꢀꢉꢍ  
ꢊꢋꢀꢋ  
ꢀꢉꢍ  
ꢊꢋꢀꢋ  
ꢊꢋꢀꢋ  
ꢘꢁꢆ  
ꢘꢁꢏ  
ꢊꢋꢀꢋ  
ꢘꢁꢆ  
ꢘꢁꢏ  
ꢊꢋꢀꢋ  
ꢘꢁꢆ  
ꢘꢁꢏ  
ꢊꢋꢀꢋꢚꢁꢏꢐ ꢊꢋꢀꢋꢚꢁꢏꢐ ꢊꢋꢀꢋꢚꢁꢏꢐ  
ꢁꢏꢏ  
ꢁꢓ  
ꢁꢑ  
ꢁꢔ  
ꢁꢇ  
ꢁꢕ  
ꢁꢒ  
ꢂꢂ  
ꢁꢏꢏ  
ꢁꢓ  
ꢁꢑ  
ꢁꢔ  
ꢁꢇ  
ꢁꢕ  
ꢁꢒ  
ꢂꢂ  
ꢁꢏꢏ  
ꢁꢓ  
ꢁꢑ  
ꢁꢔ  
ꢁꢇ  
ꢁꢕ  
ꢁꢒ  
ꢂꢂ  
ꢁꢏꢆꢙꢁꢄ ꢁꢏꢆꢙꢁꢄ ꢁꢏꢆꢙꢁꢄ  
ꢁꢆ  
ꢁꢏ  
ꢁꢆ  
ꢁꢏ  
ꢁꢆ  
ꢁꢏ  
ꢁꢐ  
ꢁꢐ  
ꢁꢐ  
ꢁꢖ  
ꢁꢖ  
ꢁꢖ  
ꢅꢅ  
ꢅꢅ  
ꢅꢅ  
ꢃꢄꢄꢅꢆꢆꢔꢆ  
Figure 2  
Pin Configuration P-TSOPII-66-1  
Data Sheet  
17  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
Table 6  
Symbol  
CK, CK  
Input/Output Functional Description  
Type  
Function  
Input  
Clock: CK and CK are differential clock inputs. All address and control input  
signals are sampled on the crossing of the positive edge of CK and negative  
edge of CK. Output (read) data is referenced to the crossings of CK and CK  
(both directions of crossing).  
CKE  
Input  
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock  
signals and device input buffers and output drivers. Taking CKE Low provides  
Precharge Power-Down and Self Refresh operation (all banks idle), or Active  
Power-Down (row Active in any bank). CKE is synchronous for power down  
entry and exit, and for self refresh entry. CKE is asynchronous for self refresh  
exit. CKE must be maintained high throughout read and write accesses. Input  
buffers, excluding CK, CK and CKE are disabled during power-down. Input  
buffers, excluding CKE, are disabled during self refresh. CKE is an SSTL_2  
input, but will detect an LVCMOS LOW level after VDD is applied on first power  
up. After VREF has become stable during the power on and initialization  
sequence, it must be mantained for proper operation of the CKE receiver. For  
proper self-refresh entry and exit, VREF must be mantained to this input.  
CS  
Input  
Chip Select: All commands are masked when CS is registered HIGH. CS  
provides for external bank selection on systems with multiple banks. CS is  
considered part of the command code. The standard pinout includes one CS  
pin.  
RAS, CAS, WE Input  
Command Inputs: RAS, CAS and WE (along with CS) define the command  
being entered.  
DM  
Input  
Input  
Input  
Input Data Mask: DM is an input mask signal for write data. Input data is  
masked when DM is sampled HIGH coincident with that input data during a  
Write access. DM is sampled on both edges of DQS. Although DM pins are  
input only, the DM loading matches the DQ and DQS loading.  
BA0, BA1  
A0 - A12  
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read,  
Write or Precharge command is being applied. BA0 and BA1 also determines  
if the mode register or extended mode register is to be accessed during a  
MRS or EMRS cycle.  
Address Inputs: Provide the row address for Active commands, and the  
column address and Auto Precharge bit for Read/Write commands, to select  
one location out of the memory array in the respective bank. A10 is sampled  
during a Precharge command to determine whether the Precharge applies to  
one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be  
precharged, the bank is selected by BA0, BA1. The address inputs also  
provide the op-code during a Mode Register Set command.  
DQ  
Input/Output  
Input/Output  
Data Input/Output: Data bus.  
DQS  
Data Strobe: Output with read data, input with write data. Edge-aligned with  
read data, centered in write data. Used to capture write data.  
N.C.  
VDDQ  
VSSQ  
VDD  
No Connect: No internal electrical connection is present.  
DQ Power Supply: 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400  
DQ Ground  
Supply  
Supply  
Supply  
Supply  
Supply  
Power Supply: 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400  
Ground  
VSS  
VREF  
SSTL_2 Reference Voltage: (VDDQ/2)  
Data Sheet  
18  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
Drivers  
Receivers  
Read Latch  
Bank0  
Row-Address Latch  
& Decoder  
Bank Control Logic  
Row-Address MUX  
Refresh Counter  
Address Register  
Figure 3  
Block Diagram 512Mbit 128 Mbit ×4  
Data Sheet  
19  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
Drivers  
Receivers  
Read Latch  
Bank0  
Row-Address Latch  
& Decoder  
Bank Control Logic  
Row-Address MUX  
Refresh Counter  
Address Register  
Figure 4  
Block Diagram 512Mbit 64 Mbit ×8  
Data Sheet  
20  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Pin Configuration  
Drivers  
Receivers  
Read Latch  
Bank0  
Row-Address Latch  
& Decoder  
Bank Control Logic  
Row-Address MUX  
Refresh Counter  
Address Register  
Figure 5  
Block Diagram 512Mbit 32 Mbit ×16  
Data Sheet  
21  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3
Functional Description  
The 512Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing  
536,870,912 bits. The 512Mbit Double Data Rate SDRAM is internally configured as a quad-bank DRAM.  
The 512Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.  
The double-data-rate architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer  
two data words per clock cycle at the I/O pins. A single read or write access for the 512Mbit Double Data Rate  
SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two  
corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.  
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and  
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration  
of an Active command, which is then followed by a Read or Write command. The address bits registered  
coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the  
bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used  
to select the starting column location for the burst access.  
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information  
covering device initialization, register definition, command descriptions and device operation.  
3.1  
Initialization  
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than  
those specified may result in undefined operation. The following criteria must be met:  
No power sequencing is specified during power up or power down given the following criteria:  
V
V
DD and VDDQ are driven from a single power converter output  
TT meets the specification  
A minimum resistance of 42 limits the input current from the VTT supply into any pin and VREF tracks VDDQ/2  
or the following relationship must be followed:  
V
V
V
DDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V  
TT is driven after or with VDDQ such that VTT < VDDQ + 0.3 V  
REF is driven after or with VDDQ such that VREF < VDDQ + 0.3 V  
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read  
access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM  
requires a 200 µs delay prior to applying an executable command.  
Once the 200 µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be  
brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode  
Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode  
Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating  
parameters. 200 clock cycles are required between the DLL reset and any executable command. During the  
200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a  
Precharge ALL command should be applied, placing the device in the “all banks idle” state.  
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set  
command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without  
resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.  
Data Sheet  
22  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.2  
Mode Register Definition  
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes  
the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is  
programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information  
until it is programmed again or the device loses power (except for bit A8, which is self-clearing).  
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-  
A6 specify the CAS latency, and A7-A12 specify the operating mode.  
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before  
initiating the subsequent operation. Violating either of these requirements results in unspecified operation.  
MR  
Mode Register Definition  
(BA[1:0] = 00B)  
A8 A7 A6  
BA1  
BA0  
A12  
A11  
A10  
A9  
A5  
A4  
A3  
A2  
A1  
A0  
0
0
MODE  
CL  
BT  
BL  
reg. addr  
w
w
w
w
Field Bits Type Description  
BL  
[2:0]  
w
Burst Length  
Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1.  
Note:All other bit combinations are RESERVED.  
001 2  
010 4  
011 8  
BT  
CL  
3
w
w
Burst Type  
See Table 7 for internal address sequence of low order address bits; see Chapter 3.2.2.  
0
1
Sequential  
Interleaved  
[6:4]  
CAS Latency  
Number of full clocks from read command to first data valid window; see Chapter 3.2.3.  
Note:All other bit combinations are RESERVED.  
010 2  
011 3  
101 (1.5 Optional, not covered by this data sheet)  
110 2.5  
MODE [12:7] w  
Operating Mode  
See Chapter 3.2.4.  
Note:All other bit combinations are RESERVED.  
000000 Normal Operation without DLL Reset  
000010 DLL Reset  
3.2.1  
Burst Length  
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The  
burst length determines the maximum number of column locations that can be accessed for a given Read or Write  
command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.  
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.  
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All  
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is  
Data Sheet  
23  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst  
length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column  
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the  
starting location within the block. The programmed burst length applies to both Read and Write bursts.  
3.2.2  
Burst Type  
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the  
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the  
burst type and the starting column address, as shown in Table 7.  
Table 7  
Burst Definition  
Burst  
Starting Column Address  
Order of Accesses Within a Burst  
Length  
A2  
A1  
A0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential  
Type = Interleaved  
0-1  
2
0-1  
1-0  
1-0  
4
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3  
0-1-2-3  
1-2-3-0  
1-0-3-2  
2-3-0-1  
2-3-0-1  
3-0-1-2  
3-2-1-0  
8
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7  
1-2-3-4-5-6-7-0  
2-3-4-5-6-7-0-1  
3-4-5-6-7-0-1-2  
4-5-6-7-0-1-2-3  
5-6-7-0-1-2-3-4  
6-7-0-1-2-3-4-5  
7-0-1-2-3-4-5-6  
0-1-2-3-4-5-6-7  
1-0-3-2-5-4-7-6  
2-3-0-1-6-7-4-5  
3-2-1-0-7-6-5-4  
4-5-6-7-0-1-2-3  
5-4-7-6-1-0-3-2  
6-7-4-5-2-3-0-1  
7-6-5-4-3-2-1-0  
Notes  
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.  
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the  
block.  
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within  
the block.  
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps  
within the block.  
3.2.3  
Read Latency  
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and  
the availability of the first burst of output data. The latency can be programmed 2, 2.5 and 3 clocks. CAS latency  
of 1.5 is an optional feature on this device.  
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally  
coincident with clock edge n + m.  
Reserved states should not be used as unknown operation or incompatibility with future versions may result.  
Data Sheet  
24  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.2.4  
Operating Mode  
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero,  
and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with  
bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register  
Set command issued to reset the DLL should always be followed by a Mode Register Set command to select  
normal operating mode.  
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and  
reserved states should not be used as unknown operation or incompatibility with future versions may result.  
CAS Latency = 2, BL = 4  
CK  
CK  
Read  
NOP  
NOP  
NOP  
NOP  
NOP  
Command  
CL=2  
DQS  
DQ  
CAS Latency = 2.5, BL = 4  
CK  
CK  
Read  
NOP  
NOP  
NOP  
NOP  
NOP  
Command  
CL=2.5  
DQS  
DQ  
Shown with nominal tAC, tDQSCK, and tDQSQ  
.
Don’t Care  
Figure 6  
Required CAS Latencies  
Data Sheet  
25  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.3  
Extended Mode Register  
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional  
functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled  
via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the  
Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed  
again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the  
controller must wait the specified time before initiating any subsequent operation. Violating either of these  
requirements result in unspecified operation.  
EMR  
Extended Mode Register Definition  
(BA[1:0] = 01B)  
BA1  
BA0  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
0
1
MODE  
DS  
DLL  
reg. addr  
w
w
w
Field  
DLL  
Bits  
Type  
Description  
DLL Status  
0
w
See Chapter 3.3.1.  
0
1
Enabled  
Disabled  
DS  
1
w
w
Drive Strength  
See Chapter 3.3.2, Chapter 5 and Chapter 5.1.  
0
1
Normal  
Weak  
MODE  
[12:2]  
Operating Mode  
Note:All other bit combinations are RESERVED.  
0
Normal Operation  
3.3.1  
DLL Enable/Disable  
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon  
returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is  
automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self  
refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command can be  
issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon exit of self  
refresh operation.  
3.3.2  
Output Drive Strength  
The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version  
supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during  
mode register set. I-V curves for the normal and weak drive strength are included in this document.  
Data Sheet  
26  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.4  
Commands  
Deselect  
The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is  
effectively deselected. Operations already in progress are not affected.  
No Operation (NOP)  
The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted  
commands from being registered during idle or wait states. Operations already in progress are not affected.  
Mode Register Set  
The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in Chapter 3.2.  
The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A  
subsequent executable command cannot be issued until tMRD is met.  
Active  
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value  
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row  
remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that  
bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before  
opening a different row in the same bank.  
Read  
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1  
inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don’t care] for x16, [i = 9,  
j = don’t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on input A10  
determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is  
precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent  
accesses.  
Write  
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1  
inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where  
[i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto  
Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write  
burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on  
the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a  
given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high,  
the corresponding data inputs are ignored, and a Write is not executed to that byte/column location.  
Pre charge  
The Pre charge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all  
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge  
command is issued. Input A10 determines whether one or all banks are to be pre charged, and in the case where  
only one bank is to be pre charged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t  
Care”. Once a bank has been pre charged, it is in the idle state and must be activated prior to any Read or Write  
commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that  
bank, or if the previously open row is already in the process of pre charging.  
Data Sheet  
27  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Auto Pre charge  
Auto Pre charge is a feature which performs the same individual-bank precharge functions described above, but  
without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction  
with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write  
command is automatically performed upon completion of the Read or Write burst. Auto Pre charge is non  
persistent in that it is either enabled or disabled for each individual Read or Write command. Auto Pre charge  
ensures that the pre charge is initiated at the earliest valid stage within a burst. The user must not issue another  
command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit Pre charge  
command was issued at the earliest possible time, as described for each burst type in Chapter 3.5.  
Burst Terminate  
The Burst Terminate command is used to truncate read bursts (with Auto Pre charge disabled). The most recently  
registered Read command prior to the Burst Terminate command is truncated, as shown in Chapter 3.5.  
Auto Refresh  
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR)  
Refresh in previous DRAM types. This command is non persistent, so it must be issued each time a refresh is  
required.  
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care”  
during an Auto Refresh command. The 512Mbit Double Data Rate SDRAM requires Auto Refresh cycles at an  
average periodic interval of 7.8 µs (maximum).  
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh  
interval is provided. A maximum of eight Auto Refresh commands can be posted in the system, meaning that the  
maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is  
9 × 7.8 µs (70.2 µs). This maximum absolute interval is short enough to allow for DLL updates internal to the DDR  
SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC between updates.  
Self Refresh  
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is  
powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self  
Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is  
automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh  
(200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are  
“Don’t Care” during Self Refresh operation. Since CKE is an SSTL_2 input , VREF must be maintained during SELF  
REFRESH.  
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE  
returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is  
required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and  
DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.  
Data Sheet  
28  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Table 8  
Truth Table 1a: Commands  
Name (Function)  
CS RAS CAS WE Address MNE  
Notes  
1)2)  
Deselect (NOP)  
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
NOP  
NOP  
1)2)  
1)3)  
1)4)  
1)4)  
1)5)  
1)6)  
1)7)8)  
1)9)  
No Operation (NOP)  
Active (Select Bank And Activate Row)  
Read (Select Bank And Column, And Start Read Burst)  
Write (Select Bank And Column, And Start Write Burst)  
Burst Terminate  
Bank/Row ACT  
Bank/Col Read  
Bank/Col Write  
H
H
H
L
L
H
H
L
L
X
BST  
Precharge (Deactivate Row In Bank Or Banks)  
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)  
Mode Register Set  
L
Code  
X
PRE  
L
H
L
AR/SR  
L
L
Op-Code MRS  
1) CKE is HIGH for all commands shown except Self Refresh.  
V
REF must be maintained during Self Refresh operation  
2) Deselect and NOP are functionally interchangeable.  
3) BA0-BA1 provide bank address and A0-A12 provide row address.  
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for ×16, i = 9 for ×8 and 9, 11 for ×4);  
A10 HIGH enables the Auto Precharge feature (non persistent), A10 LOW disables the Auto Precharge feature.  
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read  
bursts with Auto Precharge enabled or for write bursts.  
6) A10 LOW: BA0, BA1 determine which bank is precharged.  
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.  
7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW.  
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.  
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1,  
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to  
be written to the selected Mode Register).  
Table 9  
Truth Table 1b: DM Operation  
Name (Function)  
Write Enable  
DM  
L
DQs  
Valid  
X
Notes  
1)  
1)  
Write Inhibit  
H
1) Used to mask write data; provided coincident with the corresponding data.  
Data Sheet  
29  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.5  
Operations  
3.5.1  
Bank/Row Activation  
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must  
be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see  
Figure 7), which decode and select both the bank and the row to be activated. After opening a row (issuing an  
Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A  
subsequent Active command to a different row in the same bank can only be issued after the previous active row  
has been “closed” (precharged). The minimum time interval between successive Active commands to the same  
bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being  
accessed, which results in a reduction of total row-access overhead. The minimum time interval between  
successive Active commands to different banks is defined by tRRD  
.
CK  
CK  
HIGH  
CKE  
CS  
RAS  
CAS  
WE  
RA = row address.  
BA = bank address.  
RA  
BA  
A0-A12  
BA0, BA1  
Don’t Care  
Figure 7  
Activating a Specific Row in a Specific Bank  
CK  
CK  
RD/WR  
ACT  
NOP  
ACT  
NOP  
NOP  
NOP  
NOP  
Command  
A0-A12  
ROW  
BA x  
ROW  
BA y  
COL  
BA y  
BA0, BA1  
tRRD  
tRCD  
Don’t Care  
Figure 8  
t
RCD and tRRD Definition  
Data Sheet  
30  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.5.2  
Reads  
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are  
initiated with a Read command, as shown on Figure 9.  
The starting column and bank addresses are provided with the Read command and Auto Precharge is either  
enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge  
at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the  
following illustrations, Auto Precharge is disabled.  
During Read bursts, the valid data-out element from the starting column address is available following the CAS  
latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or  
negative clock edge (i.e. at the next crossing of CK and CK). Figure 10 shows general timing for each supported  
CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is  
known as the read preamble; the low state coincident with the last data-out element is known as the read post  
amble. Upon completion of a burst, assuming no other commands have been initiated, the DQs goes High-Z. Data  
from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In  
either case, a continuous flow of data can be maintained. The first data element from the new burst follows either  
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.  
The new Read command should be issued x cycles after the first Read command, where x equals the number of  
desired data element pairs (pairs are required by the 2n pre fetch architecture). This is shown on Figure 11. A  
Read command can be initiated on any clock cycle following a previous Read command. Nonconsecutive Read  
data is illustrated on Figure 12. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)  
within a page (or pages) can be performed as shown on Figure 13.  
Data from any Read burst may be truncated with a Burst Terminate command, as shown on Figure 14. The Burst  
Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles  
after the Read command, where x equals the number of desired data element pairs.  
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If  
truncation is necessary, the Burst Terminate command must be used, as shown on Figure 15. The example is  
shown for tDQSS(min). The tDQSS(max) case, not shown here, has a longer bus idle time. tDQSS(min) and tDQSS(max) are  
defined in Chapter 3.5.3.  
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto  
Precharge was not activated). The Precharge command should be issued x cycles after the Read command,  
where x equals the number of desired data element pairs (pairs are required by the 2n prefect architecture). This  
is shown on Figure 16 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent  
command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden  
during the access of the last data elements.  
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as  
described above) provides the same operation that would result from the same Read burst with Auto Precharge  
enabled. The disadvantage of the Precharge command is that it requires that the command and address busses  
be available at the appropriate time to issue the command. The advantage of the Precharge command is that it  
can be used to truncate bursts.  
Data Sheet  
31  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
CK  
CK  
HIGH  
CKE  
CS  
RAS  
CAS  
WE  
x4: A0-A9, A11  
x8: A0-A9  
CA  
x16: A0-A8  
EN AP  
A10  
DIS AP  
BA  
CA = column address  
BA = bank address  
EN AP = enable Auto Precharge  
DIS AP = disable Auto Precharge  
BA0, BA1  
Don’t Care  
Figure 9  
Read Command  
Data Sheet  
32  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
CAS Latency = 2  
CK  
CK  
Read  
NOP  
NOP  
NOP  
NOP  
NOP  
Command  
Address  
BA a,COL n  
CL=2  
DQS  
DQ  
DOa-n  
CAS Latency = 2.5  
CK  
CK  
Read  
NOP  
NOP  
NOP  
NOP  
NOP  
Command  
Address  
BA a,COL n  
CL=2.5  
DQS  
DQ  
DOa-n  
Don’t Care  
DO a-n = data out from bank a, column n.  
3 subsequent elements of data out appear in the programmed order following DO a-n.  
Shown with nominal tAC, tDQSCK, and tDQSQ  
.
Figure 10 Read Burst: CAS Latencies (Burst Length = 4)  
Data Sheet  
33  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
CAS Latency = 2  
CK  
CK  
Read  
NOP  
Read  
NOP  
NOP  
NOP  
Command  
Address  
BAa, COL n  
BAa, COL b  
CL=2  
DQS  
DQ  
DOa-b  
DOa-n  
CAS Latency = 2.5  
CK  
CK  
Read  
NOP  
Read  
NOP  
NOP  
NOP  
Command  
Address  
BAa, COL n  
BAa,COL b  
CL=2.5  
DQS  
DQ  
DOa- n  
DOa- b  
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).  
When burst length = 4, the bursts are concatenated.  
When burst length = 8, the second burst interrupts the first.  
Don’t Care  
3 subsequent elements of data out appear in the programmed order following DO a-n.  
3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.  
Shown with nominal tAC, tDQSCK, and tDQSQ  
.
Figure 11 Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)  
Data Sheet  
34  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
CAS Latency = 2  
CK  
CK  
Read  
NOP  
NOP  
Read  
NOP  
NOP  
Command  
Address  
BAa, COL n  
BAa, COL b  
CL=2  
DQS  
DQ  
DO a-n  
DOa- b  
CAS Latency = 2.5  
CK  
CK  
Read  
NOP  
NOP  
Read  
NOP  
NOP  
NOP  
Command  
Address  
BAa, COL n  
BAa, COL b  
CL=2.5  
DQS  
DQ  
DO a-n  
DOa- b  
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).  
3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).  
Shown with nominal tAC, tDQSCK, and tDQSQ  
.
Don’t Care  
Figure 12 Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)  
Data Sheet  
35  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
CAS Latency = 2  
CK  
CK  
Read  
Read  
BAa, COL x  
CL=2  
Read  
Read  
NOP  
NOP  
Command  
Address  
BAa, COL n  
BAa, COL b  
BAa, COL g  
DQS  
DQ  
DOa-n  
DOa-n’  
DOa-x  
DOa-x’  
DOa-b  
DOa-b’  
DOa-g  
CAS Latency = 2.5  
CK  
CK  
Read  
Read  
Read  
Read  
NOP  
NOP  
Command  
Address  
BAa, COL n  
BAa, COL x  
BAa, COL b  
BAa, COL g  
CL=2.5  
DQS  
DQ  
DOa-n  
DOa-n’  
DOa-x  
DOa-x’  
DOa-b  
DOa-b’  
DO a-n, etc. = data out from bank a, column n etc.  
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).  
Don’t Care  
Reads are to active rows in any banks.  
Shown with nominal tAC, tDQSCK, and tDQSQ  
.
Figure 13 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)  
Data Sheet  
36  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
CAS Latency = 2  
CK  
CK  
Read  
NOP  
BST  
NOP  
NOP  
NOP  
Command  
Address  
BAa, COL n  
CL=2  
DQS  
DQ  
DOa-n  
No further output data after this point.  
DQS tristated.  
CAS Latency = 2.5  
CK  
CK  
Read  
NOP  
BST  
NOP  
NOP  
NOP  
Command  
Address  
BAa, COL n  
CL=2.5  
DQS  
DQ  
DOa-n  
No further output data after this point.  
DQS tristated.  
DO a-n = data out from bank a, column n.  
Cases shown are bursts of 8 terminated after 4 data elements.  
3 subsequent elements of data out appear in the programmed order following DO a-n.  
Shown with nominal tAC, tDQSCK, and tDQSQ  
Don’t Care  
.
Figure 14 Terminating a Read Burst: CAS Latencies (Burst Length = 8)  
Data Sheet  
37  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
CAS Latency = 2  
CK  
CK  
Read  
BST  
NOP  
Write  
NOP  
NOP  
Command  
Address  
BAa, COL n  
BAa, COL b  
CL=2  
tDQSS (min)  
DQS  
DQ  
DI a-b  
DOa-n  
DM  
CAS Latency = 2.5  
CK  
CK  
Read  
BST  
NOP  
NOP  
Write  
NOP  
Command  
Address  
BAa, COL n  
BAa, COL b  
CL=2.5  
tDQSS (min)  
DQS  
DQ  
DOa-n  
Dla-b  
DM  
DO a-n = data out from bank a, column n  
.
DI a-b = data in to bank a, column b  
1 subsequent elements of data out appear in the programmed order following DO a-n.  
Data In elements are applied following Dl a-b in the programmed order, according to burst length.  
Shown with nominal tAC, tDQSCK, and tDQSQ  
.
Don’t Care  
Figure 15 Read to Write: CAS Latencies (Burst Length = 4 or 8)  
Data Sheet  
38  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
CAS Latency = 2  
CK  
CK  
Read  
NOP  
PRE  
NOP  
NOP  
ACT  
Command  
tRP  
BA a or all  
BA a, COL n  
BA a, ROW  
Address  
CL=2  
DQS  
DQ  
DOa-n  
CAS Latency = 2.5  
CK  
CK  
Read  
NOP  
PRE  
NOP  
NOP  
ACT  
Command  
tRP  
BA a or all  
BA a, COL n  
BA a, ROW  
Address  
CL=2.5  
DQS  
DQ  
DOa-n  
DO a-n = data out from bank a, column n.  
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.  
3 subsequent elements of data out appear in the programmed order following DO a-n.  
Shown with nominal tAC, tDQSCK, and tDQSQ  
.
Don’t Care  
Figure 16 Read to Precharge: CAS Latencies (Burst Length = 4 or 8)  
Data Sheet  
39  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.5.3  
Writes  
Write bursts are initiated with a Write command, as shown in Figure 17.  
The starting column and bank addresses are provided with the Write command, and Auto Precharge is either  
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the  
completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is  
disabled.  
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write  
command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS  
between the Write command and the first rising edge is known as the write preamble; the Low state on DQS  
following the last data-in element is known as the write post amble. The time between the Write command and the  
first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one  
clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS(min) and  
t
DQSS(max)). Figure 18 shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming  
no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored.  
Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case,  
a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge  
of clock following the previous Write command. The first data element from the new burst is applied after either  
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.  
The new Write command should be issued x cycles after the first Write command, where x equals the number of  
desired data element pairs (pairs are required by the 2n pre fetch architecture). Figure 19 shows concatenated  
bursts of 4. An example of non-consecutive Writes is shown in Figure 20. Full-speed random write accesses  
within a page or pages can be performed as shown in Figure 21. Data for any Write burst may be followed by a  
subsequent Read command. To follow a Write without truncating the write burst, tWTR (Write to Read) should be  
met as shown in Figure 22.  
Data for any Write burst may be truncated by a subsequent Read command, as shown in Figure 23 to Figure 25.  
Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any  
subsequent data-in must be masked with DM, as shown in the diagrams noted previously.  
Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without  
truncating the write burst, tWR should be met as shown in Figure 26.  
Data for any Write burst may be truncated by a subsequent Precharge command, as shown in Figure 27 to  
Figure 29. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array,  
and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent  
command to the same bank cannot be issued until tRP is met.  
In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as  
described above) provides the same operation that would result from the same burst with Auto Precharge. The  
disadvantage of the Precharge command is that it requires that the command and address busses be available at  
the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to  
truncate bursts.  
Data Sheet  
40  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
CK  
CK  
HIGH  
CKE  
CS  
RAS  
CAS  
WE  
x4: A0-A9, A11  
x8: A0-A9  
CA  
x16: A0-A8  
EN AP  
A10  
DIS AP  
BA  
CA = column address  
BA = bank address  
EN AP = enable Auto Precharge  
DIS AP = disable Auto Precharge  
BA0, BA1  
Don’t Care  
Figure 17 Write Command  
Data Sheet  
41  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Maximum DQSS  
T1  
T2  
T3  
T4  
CK  
CK  
Write  
NOP  
NOP  
NOP  
Command  
Address  
BA a, COL b  
tDQSS (max)  
DQS  
DQ  
Dla-b  
DM  
Minimum DQSS  
T4  
T1  
T2  
T3  
CK  
CK  
Write  
NOP  
NOP  
NOP  
Command  
Address  
BA a, COL b  
tDQSS (min)  
DQS  
DQ  
Dla-b  
DM  
DI a-b = data in for bank a, column b.  
3 subsequent elements of data in are applied in the programmed order following DI a-b.  
A non-interrupted burst is shown.  
A10 is Low with the Write command (Auto Precharge is disabled).  
Don’t Care  
Figure 18 Write Burst (Burst Length = 4)  
Data Sheet  
42  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Maximum DQSS  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
Write  
NOP  
NOP  
NOP  
Command  
Address  
BAa, COL b  
BAa, COL n  
tDQSS (max)  
DQS  
DQ  
DI a-b  
DI a-n  
DM  
Minimum DQSS  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
Write  
NOP  
NOP  
NOP  
Command  
Address  
BA, COL b  
BA, COL n  
tDQSS (min)  
DQS  
DQ  
DI a-b  
DI a-n  
DM  
DI a-b = data in for bank a, column b, etc.  
3 subsequent elements of data in are applied in the programmed order following DI a-b.  
3 subsequent elements of data in are applied in the programmed order following DI a-n.  
A non-interrupted burst is shown.  
Don’t Care  
Each Write command may be to any bank.  
Figure 19 Write to Write (Burst Length = 4)  
Data Sheet  
43  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
T1  
T2  
T3  
T4  
T5  
CK  
CK  
Write  
NOP  
NOP  
Write  
NOP  
Command  
Address  
BAa, COL b  
BAa, COL n  
tDQSS (max)  
DQS  
DQ  
DI a-b  
DI a-n  
DM  
DI a-b, etc. = data in for bank a, column b, etc.  
3 subsequent elements of data in are applied in the programmed order following DI a-b.  
3 subsequent elements of data in are applied in the programmed order following DI a-n.  
A non-interrupted burst is shown.  
Don’t Care  
Each Write command may be to any bank.  
Figure 20 Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4)  
Data Sheet  
44  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Maximum DQSS  
T1  
T2  
T3  
T4  
T5  
CK  
CK  
Write  
Write  
Write  
Write  
Write  
Command  
Address  
BAa, COL b  
BAa, COL x  
BAa, COL n  
BAa, COL a  
BAa, COL g  
tDQSS (max)  
DQS  
DQ  
DI a-b  
DI a-b’  
DI a-x  
DI a-x’  
DI a-n  
DI a-n’  
DI a-a  
DI a-a’  
DM  
Minimum DQSS  
T5  
T1  
T2  
T3  
T4  
CK  
CK  
Write  
Write  
Write  
Write  
Write  
Command  
Address  
BAa, COL b  
BAa, COL x  
BAa, COL n  
BAa, COL a  
BAa, COL g  
tDQSS (min)  
DQS  
DQ  
DI a-g  
DI a-b  
DI a-b’  
DI a-x  
DI a-x’  
DI a-n  
DI a-n’  
DI a-a  
DI a-a’  
DM  
DI a-b, etc. = data in for bank a, column b, etc.  
b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).  
Each Write command may be to any bank.  
Don’t Care  
Figure 21 Random Write Cycles (Burst Length = 2, 4 or 8)  
Data Sheet  
45  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Maximum DQSS  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
Read  
NOP  
Command  
tWTR  
BAa, COL b  
BAa, COL n  
Address  
CL = 2  
tDQSS (max)  
DQS  
DQ  
DI a-b  
DM  
Minimum DQSS  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
Read  
NOP  
Command  
tWTR  
BAa, COL n  
BAa, COL b  
Address  
CL = 2  
tDQSS (min)  
DQS  
DQ  
DI a-b  
DM  
DI a-b = data in for bank a, column b.  
3 subsequent elements of data in are applied in the programmed order following DI a-b.  
A non-interrupted burst is shown.  
t
WTR is referenced from the first positive CK edge after the last data in pair.  
A10 is Low with the Write command (Auto Precharge is disabled).  
The Read and Write commands may be to any bank.  
Don’t Care  
Figure 22 Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)  
Data Sheet  
46  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Maximum DQSS  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
Read  
NOP  
Command  
tWTR  
BAa, COL n  
BAa, COL b  
Address  
CL = 2  
tDQSS (max)  
DQS  
DQ  
DIa- b  
1
1
DM  
Minimum DQSS  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
Read  
NOP  
Command  
tWTR  
BAa, COL n  
BAa, COL b  
Address  
CL = 2  
tDQSS (min)  
DQS  
DQ  
DI a-b  
1
1
DM  
DI a-b = data in for bank a, column b.  
An interrupted burst is shown, 4 data elements are written.  
3 subsequent elements of data in are applied in the programmed order following DI a-b.  
tWTR is referenced from the first positive CK edge after the last data in pair.  
The Read command masks the last 2 data elements in the burst.  
A10 is Low with the Write command (Auto Precharge is disabled).  
The Read and Write commands are not necessarily to the same bank.  
1 = These bits are incorrectly written into the memory array if DM is low.  
Don’t Care  
Figure 23 Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)  
Data Sheet  
47  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Minimum DQSS, Odd Number of Data (3-bit Write),Interrupting (CAS Latency = 2; Burst Length = 8)  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
Read  
NOP  
Command  
tWTR  
BAa, COL n  
BAa, COL b  
Address  
CL = 2  
tDQSS (min)  
DQS  
DQ  
DI a-b  
1
2
2
DM  
DI a-b = data in for bank a, column b.  
An interrupted burst is shown, 3 data elements are written.  
2 subsequent elements of data in are applied in the programmed order following DI a-b.  
tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)  
The Read command masks the last 2 data elements in the burst.  
A10 is Low with the Write command (Auto Precharge is disabled).  
The Read and Write commands are not necessarily to the same bank.  
1 = This bit is correctly written into the memory array if DM is low.  
2 = These bits are incorrectly written into the memory array if DM is low.  
Don’t Care  
Figure 24 Write to Read: Minimum DQSS, Odd Number of Data, Interupting  
Data Sheet  
48  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
Read  
NOP  
Command  
tWTR  
BAa, COL n  
BAa, COL b  
Address  
CL = 2  
tDQSS (nom)  
DQS  
DQ  
DI a-b  
DM  
1
1
DI a-b = data in for bank a, column b.  
An interrupted burst is shown, 4 data elements are written.  
3 subsequent elements of data in are applied in the programmed order following DI a-b.  
tWTR is referenced from the first positive CK edge after the last desired data in pair.  
The Read command masks the last 2 data elements in the burst.  
A10 is Low with the Write command (Auto Precharge is disabled).  
The Read and Write commands are not necessarily to the same bank.  
1 = These bits are incorrectly written into the memory array if DM is low.  
Don’t Care  
Figure 25 Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)  
Data Sheet  
49  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Maximum DQSS  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
NOP  
PRE  
Command  
tWR  
BA (a or all)  
BA a, COL b  
Address  
tRP  
tDQSS (max)  
DQS  
DQ  
DI a-b  
DM  
Minimum DQSS  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
NOP  
tWR  
PRE  
Command  
BA (a or all)  
BA a, COL b  
Address  
tRP  
tDQSS (min)  
DQS  
DQ  
DI a-b  
DM  
DI a-b = data in for bank a, column b.  
3 subsequent elements of data in are applied in the programmed order following DI a-b.  
A non-interrupted burst is shown.  
tWR is referenced from the first positive CK edge after the last data in pair.  
Don’t Care  
A10 is Low with the Write command (Auto Precharge is disabled).  
Figure 26 Write to Precharge: Non-Interrupting (Burst Length = 4)  
Data Sheet  
50  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Maximum DQSS  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
PRE  
NOP  
Command  
tWR  
BA (a or all)  
BA a, COL b  
Address  
tRP  
tDQSS (max)  
2
DQS  
DQ  
DI a-b  
1
1
3
3
DM  
Minimum DQSS  
T5 T6  
T1  
T2  
T3  
T4  
CK  
CK  
Write  
NOP  
NOP  
NOP  
tWR  
PRE  
NOP  
Command  
BA a, COL b  
BA (a or all)  
Address  
tRP  
tDQSS (min)  
2
DQS  
DQ  
DI a-b  
3
3
1
1
DM  
DI a-b = data in for bank a, column b.  
An interrupted burst is shown, 2 data elements are written.  
1 subsequent element of data in is applied in the programmed order following DI a-b.  
tWR is referenced from the first positive CK edge after the last desired data in pair.  
The Precharge command masks the last 2 data elements in the burst, for burst length = 8.  
A10 is Low with the Write command (Auto Precharge is disabled).  
1 = Can be don't care for programmed burst length of 4.  
2 = For programmed burst length of 4, DQS becomes don't care at this point.  
3 = These bits are incorrectly written into the memory array if DM is low.  
Don’t Care  
Figure 27 Write to Precharge: Interrupting (Burst Length = 4 or 8)  
Data Sheet  
51  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (Burst Length = 4 or 8)  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
PRE  
NOP  
Command  
tWR  
BA a, COL b  
BA (a or all)  
Address  
tRP  
tDQSS (min)  
2
DQS  
DQ  
DI a-b  
1
1
3
4
4
DM  
DI a-b = data in for bank a, column b.  
An interrupted burst is shown, 1 data element is written.  
tWR is referenced from the first positive CK edge after the last desired data in pair.  
The Precharge command masks the last 2 data elements in the burst.  
A10 is Low with the Write command (Auto Precharge is disabled).  
1 = Can be don't care for programmed burst length of 4.  
2 = For programmed burst length of 4, DQS becomes don't care at this point.  
3 = This bit is correctly written into the memory array if DM is low.  
4 = These bits are incorrectly written into the memory array if DM is low.  
Don’t Care  
Figure 28 Write to Precharge: Minimum DQSS, Odd Number of Data, Interrupting  
Data Sheet  
52  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
T1  
T2  
T3  
T4  
T5  
T6  
CK  
CK  
Write  
NOP  
NOP  
NOP  
PRE  
NOP  
Command  
tWR  
BA a, COL b  
BA (a or all)  
Address  
tRP  
tDQSS (nom)  
2
DQS  
DQ  
DI a-b  
3
3
1
1
DM  
DI a-b = Data In for bank a, column b.  
An interrupted burst is shown, 2 data elements are written.  
1 subsequent element of data in is applied in the programmed order following DI a-b.  
WR is referenced from the first positive CK edge after the last desired data in pair.  
t
The Precharge command masks the last 2 data elements in the burst.  
A10 is Low with the Write command (Auto Precharge is disabled).  
1 = Can be don't care for programmed burst length of 4.  
2 = For programmed burst length of 4, DQS becomes don't care at this point.  
3 = These bits are incorrectly written into the memory array if DM is low.  
Don’t Care  
Figure 29 Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8)  
Data Sheet  
53  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.5.4  
Pre charge  
The Pre charge command is used to deactivate the open row in a particular bank or the open row in all banks. The  
bank(s) will be available for a subsequent row access some specified time (tRP) after the Pre charge command is  
issued. Input A10 determines whether one or all banks are to be pre charged, and in the case where only one bank  
is to be pre charged, inputs BA0, BA1 select the bank. When all banks are to be pre charged, inputs BA0, BA1 are  
treated as “Don’t Care”. Once a bank has been pre charged, it is in the idle state and must be activated prior to  
any Read or Write commands being issued to that bank.  
CK  
CK  
HIGH  
CKE  
CS  
RAS  
CAS  
WE  
A0-A9, A11, A12  
All Banks  
A10  
One Bank  
BA  
BA0, BA1  
BA = bank address  
(if A10 is Low, otherwise Don’t Care).  
Don’t Care  
Figure 30 Precharge Command  
Data Sheet  
54  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.5.5  
Power-Down  
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs  
when all banks are idle, this mode is referred to as pre charge power-down; if power-down occurs when there is  
a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the  
input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for  
maximum power savings, the user has the option of disabling the DLL prior to entering Power-down. In that case,  
the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a Read command can  
be issued. In power-down mode, CKE Low and a stable clock signal must be maintained at the inputs of the DDR  
SDRAM, and all other input signals are “Don’t Care”. However, power-down duration is limited by the refresh  
requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled  
power-down mode.  
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect  
command). A valid, executable command may be applied one clock cycle later.  
CK  
CK  
tIS  
tIS  
CKE  
Command  
VALID  
NOP  
VALID  
NOP  
No column  
access in  
progress  
Exit  
power down  
mode  
Don’t Care  
Enter Power Down mode  
(Burst Read or Write operation  
must not be in progress)  
Figure 31 Power Down  
Data Sheet  
55  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Table 10  
Current State CKE n-1  
Previous Current  
Truth Table 2: Clock Enable (CKE)  
CKEn  
Command n  
Action n  
Notes  
Cycle  
Cycle  
1)  
2)  
Self Refresh  
Self Refresh  
Power Down  
Power Down  
All Banks Idle  
All Banks Idle  
L
L
L
X
Maintain Self-Refresh  
Exit Self-Refresh  
H
L
Deselect or NOP  
X
L
Maintain Power-Down  
Exit Power-Down  
L
H
L
Deselect or NOP  
Deselect or NOP  
AUTO REFRESH  
Deselect or NOP  
See Table 11  
H
H
Precharge Power-Down Entry –  
L
Self Refresh Entry  
Bank(s) Active H  
H
L
Active Power-Down Entry  
H
1) VREF must be maintained during Self Refresh operation  
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A  
minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.  
Note:  
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.  
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.  
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.  
4. All states and sequences not shown are illegal or reserved.  
Table 11  
Truth Table 3: Current State Bank n - Command to Bank n (same bank)  
Current State CS RAS CAS WE Command  
Action  
Notes  
1)2)3)4)5)6)  
Any  
Idle  
H
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
Deselect  
NOP. Continue previous operation.  
1) to 6)  
1) to 6)  
1) to 7)  
1) to 7)  
No Operation  
Active  
NOP. Continue previous operation.  
Select and activate row  
L
AUTO REFRESH  
L
L
MODE  
REGISTER SET  
1) to 6), 8)  
1) to 6), 8)  
1) to 6), 9)  
1) to 6), 8)  
Row Active  
L
L
L
L
H
H
L
L
L
H
L
H
L
Read  
Select column and start Read burst  
Select column and start Write burst  
Deactivate row in bank(s)  
Write  
L
Precharge  
Read  
Read (Auto  
Precharge  
Disabled)  
H
H
Select column and start new Read  
burst  
1) to 6), 9)  
L
L
L
H
H
L
L
Precharge  
Truncate Read burst, start  
Precharge  
1) to 6), 10)  
H
BURST  
BURST TERMINATE  
TERMINATE  
1) to 6), 8), 11)  
1) to 6), 8)  
Write (Auto  
Precharge  
Disabled)  
L
L
L
H
H
L
L
L
H
H
L
L
Read  
Select column and start Read burst  
Select column and start Write burst  
Truncate Write burst, start Precharge  
Write  
1) to 6), 9), 11)  
Precharge  
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 10 and after tXSNR/tXSRD has been met (if the  
previous state was self refresh).  
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are  
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.  
Data Sheet  
56  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3) Current state definitions:  
Idle: The bank has been precharged, and tRP has been met.  
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register  
accesses are in progress.  
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.  
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.  
4) The following states must not be interrupted by a command issued to the same bank.  
Pre charging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in  
the idle state.  
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in  
the “row active” state.  
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when  
t
RP has been met. Once tRP is met, the bank is in the idle state.  
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when  
RP has been met. Once tRP is met, the bank is in the idle state.  
t
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring  
during these states. Allowable commands to the other bank are determined by its current state and according to Table 12.  
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied  
on each positive clock edge during these states.  
Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR  
SDRAM is in the “all banks idle” state.  
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met.  
Once tMRD is met, the DDR SDRAM is in the “all banks idle” state.  
Pre charging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks  
is in the idle state.  
6) All states and sequences not shown are illegal or reserved.  
7) Not bank-specific; requires that all banks are idle.  
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads  
or Writes with Auto Precharge disabled.  
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for pre charging.  
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.  
11) Requires appropriate DM masking.  
Data Sheet  
57  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
Table 12  
Truth Table 4: Current State Bank n - Command to Bank m (different bank)  
Current State  
CS RAS CAS WE Command  
Action  
Notes  
1)2)3)4)5)6)  
Any  
H
L
X
H
X
X
H
X
X
H
X
Deselect  
NOP. Continue previous operation.  
1) to 6)  
1) to 6)  
No Operation  
NOP. Continue previous operation.  
Idle  
X
Any Command  
Otherwise Allowed  
to Bank m  
1) to 6)  
1) to 7)  
1) to 7)  
1) to 6)  
1) to 6)  
1) to 7)  
Row Activating,  
Active, or Pre  
charging  
L
L
L
L
L
L
L
H
L
H
H
L
Active  
Read  
Select and activate row  
Select column and start Read burst  
Select column and start Write burst  
H
H
L
L
Write  
H
H
L
L
Precharge  
Active  
Read  
Read (Auto  
Precharge  
Disabled)  
L
H
H
Select and activate row  
H
Select column and start new Read  
burst  
1) to 6)  
1) to 6)  
1) to 8)  
1) to 7)  
L
L
L
L
L
H
H
L
L
Precharge  
Active  
Write (Auto  
Precharge  
Disabled)  
L
H
H
L
Select and activate row  
H
H
Read  
Select column and start Read burst  
L
Write  
Select column and start new Write  
burst  
1) to 6)  
L
L
L
H
H
H
L
L
Precharge  
Active  
1) to 6)  
Read (With Auto L  
H
H
Select and activate row  
1) to 7), 9)  
Precharge)  
L
Read  
Select column and start new Read  
burst  
1) to 7), 9), 10)  
1) to 6)  
L
L
H
L
L
L
Write  
Select column and start Write burst  
H
H
L
L
Precharge  
Active  
Read  
1) to 6)  
Write (With Auto L  
L
H
H
L
Select and activate row  
Select column and start Read burst  
1) to 7), 9)  
1) to 7), 9)  
Precharge)  
L
H
H
L
L
L
Write  
Select column and start new Write  
burst  
1) to 6)  
L
H
L
Precharge  
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 10: Clock Enable (CKE) and after tXSNR/tXSRD  
has been met (if the previous state was self refresh).  
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands  
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is  
allowable). Exceptions are covered in the notes below.  
3) Current state definitions:  
Idle: The bank has been precharged, and tRP has been met.  
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register  
accesses are in progress.  
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.  
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.  
Read with Auto Precharge Enabled: See 10)  
Write with Auto Precharge Enabled: See 10)  
.
.
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.  
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state  
only.  
6) All states and sequences not shown are illegal or reserved.  
Data Sheet  
58  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads  
or Writes with Auto Precharge disabled.  
8) Requires appropriate DM masking.  
9) Concurrent Auto Precharge:  
This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is  
enabled any command may follow to the other banks as long as that command does not interrupt the read or write data  
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The  
minimum delay from a read or write command with auto precharge enable, to a command to a different banks is  
summarized in Table 13.  
10) A Write command may be applied after the completion of data output.  
Table 13  
Truth Table 5: Concurrent Auto Precharge  
From Command  
To Command (different bank)  
Minimum Delay with Concurrent  
Auto Precharge Support  
Unit  
WRITE w/AP  
Read or Read w/AP  
Write to Write w/AP  
Precharge or Activate  
Read or Read w/AP  
Write or Write w/AP  
Precharge or Activate  
1 + (BL/2) + RU(tWTR/tCK)1)  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
BL/2  
1
Read w/AP  
BL/2  
RU(CL)1) + BL/2  
1
1) RU means rounded to the next integer  
3.5.6  
Input Clock Frequency Change  
DDR SDRAM Input clock frequency cannot be changed during normal operation. Clock frequency change is only  
permitted during Self Refresh or during Power Down. In the latter case the following conditions must be met:  
DDR SDRAM must be in pre charged mode with CKE at logic Low level. After a minimum of 2 clocks after CKE  
goes LOW, the clock frequency may change to any frequency between minimum and maximum operating  
frequeny specified for the particular speed grade. During an input clock frequency change, CKE must be held  
LOW. Once the input clock frequency is changed, a stable clock must be provided to DRAM before pre charge  
power down mode may be exited. The DLL must be RESET via EMRS after pre charge power down exit. An  
additional MRS command may need to be issued to appropriately set CL etc.. After the DLL relock time, the DRAM  
is ready to operate with the new clock frequency.  
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Figure 32 Clock frequency change in pre charge power down mode  
Data Sheet  
59  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Functional Description  
3.6  
Simplified State Diagram  
Power  
Applied  
Power  
On  
Self  
Refresh  
Precharge  
PREALL  
REFS  
REFSX  
MRS  
EMRS  
Auto  
Refresh  
MRS  
REFA  
Idle  
CKEL  
CKEH  
Active  
Power  
Down  
ACT  
Precharge  
Power  
Down  
CKEH  
CKEL  
Write  
Burst Stop  
Row  
Active  
Read  
Write A  
Read A  
Write  
Read  
Read  
Read A  
Write A  
Read  
A
PRE  
Write  
A
Read  
A
PRE  
PRE  
Precharge  
PREALL  
PRE  
Automatic Sequence  
Command Sequence  
PREALL = Precharge All Banks  
MRS = Mode Register Set  
EMRS = Extended Mode Register Set  
REFS = Enter Self Refresh  
REFSX = Exit Self Refresh  
REFA = Auto Refresh  
CKEL = Enter Power Down  
CKEH = Exit Power Down  
ACT = Active  
Write A = Write with Autoprecharge  
Read A = Read with Autoprecharge  
PRE = Precharge  
Figure 33 Simplified State Diagram  
Data Sheet  
60  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Electrical Characteristics  
4
Electrical Characteristics  
4.1  
Operating Conditions  
Table 14  
Parameter  
Absolute Maximum Ratings  
Symbol  
Values  
typ.  
Unit Note/ Test  
Condition  
min.  
VIN, VOUT –0.5  
max.  
Voltage on I/O pins relative to VSS  
VDDQ  
+
V
0.5  
Voltage on inputs relative to VSS  
Voltage on VDD supply relative to VSS  
Voltage on VDDQ supply relative to VSS  
Operating temperature (ambient)  
Storage temperature (plastic)  
VIN  
–1  
–1  
–1  
0
+3.6  
+3.6  
+3.6  
+70  
+150  
V
VDD  
VDDQ  
TA  
V
V
°C  
°C  
W
mA  
TSTG  
PD  
-55  
Power dissipation (per SDRAM component)  
Short circuit output current  
1
IOUT  
50  
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This  
is a stress rating only, and functional operation should be restricted to recommended operation  
conditions. Exposure to absolute maximum rating conditions for extended periods of time may  
affect device reliability and exceeding only one of the values may cause irreversible damage to  
the integrated circuit.  
Table 15  
Input and Output Capacitances  
Symbol  
Parameter  
Values  
Typ.  
Unit  
Note/  
Test Condition  
Min.  
1.5  
2.0  
Max.  
2.5  
1)  
Input Capacitance: CK, CK  
Delta Input Capacitance  
CI1  
pF  
pF  
pF  
pF  
pF  
pF  
TSOPII  
1)  
3.0  
TFBGA  
1)  
CdI1  
CI2  
0.25  
2.5  
1)  
Input Capacitance:  
All other input-only pins  
1.5  
2.0  
TFBGA  
1)  
3.0  
TSOPII  
1)  
Delta Input Capacitance:  
All other input-only pins  
CdIO  
0.5  
TFBGA 1)2)  
Input/Output Capacitance: DQ, DQS, DM CIO  
3.5  
4.0  
4.5  
5.0  
0.5  
pF  
pF  
pF  
1)2)  
TSOPII  
1)  
Delta Input/Output Capacitance:  
DQ, DQS, DM  
CdIO  
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz,  
TA = 25 °C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.  
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace  
matching at the board level.  
Data Sheet  
61  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Electrical Characteristics  
Electrical Characteristics and DC Operating Conditions  
1)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note/Test Condition  
Min.  
2.3  
2.5  
2.3  
2.5  
0
Max.  
Device Supply Voltage  
Device Supply Voltage  
Output Supply Voltage  
Output Supply Voltage  
VDD  
2.5  
2.6  
2.5  
2.6  
2.7  
2.7  
2.7  
2.7  
0
V
V
V
V
V
fCK 166 MHz  
fCK > 166 MHz  
fCK 166 MHz  
fCK > 166 MHz  
2)  
VDD  
3)  
VDDQ  
VDDQ  
2)3)  
Supply Voltage, I/O Supply VSS  
,
Voltage  
VSSQ  
4)  
5)  
Input Reference Voltage  
VREF  
0.49 ×  
VDDQ  
0.5 ×  
VDDQ  
0.51 ×  
VDDQ  
V
I/O Termination Voltage  
(System)  
VTT  
VREF – 0.04  
VREF + 0.04 V  
6)  
6)  
6)  
Input High (Logic1) Voltage VIH(DC) VREF + 0.15  
Input Low (Logic0) Voltage VIL(DC) –0.3  
VDDQ + 0.3 V  
VREF – 0.15 V  
VDDQ + 0.3 V  
Input Voltage Level,  
CK and CK Inputs  
VIN(DC) –0.3  
6)7)  
8)  
Input Differential Voltage, VID(DC) 0.36  
CK and CK Inputs  
VDDQ + 0.6 V  
VI-Matching Pull-up  
Current to Pull-down  
Current  
VI  
0.71  
–2  
1.4  
2
Ratio  
Input Leakage Current  
II  
µA Any input 0 V VIN VDD;  
All other pins not under test  
9)  
= 0 V  
Output Leakage Current  
IOZ  
IOH  
IOL  
–5  
5
µA DQs are disabled;  
9)  
0 V VOUT VDDQ  
Output High Current,  
Normal Strength Driver  
–16.2  
mA VOUT = 1.95 V  
Output Low  
16.2  
mA VOUT = 0.35 V  
Current, Normal Strength  
Driver  
1) 0 °C TA 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);  
2) DDR400 conditions apply for all clock frequencies above 166 MHz  
3) Under all conditions, VDDQ must be less than or equal to VDD  
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ  
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal  
.
.
to VREF, and must track variations in the DC level of VREF  
.
6) Inputs are not recognized as valid until VREF stabilizes.  
7) VID is the magnitude of the difference between the input level on CK and the input level on CK.  
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire  
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the  
maximum difference between pull-up and pull-down drivers due to process variation.  
9) Values are shown per pin.  
Data Sheet  
62  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
5
Normal Strength Pull-down and Pull-up Characteristics  
1. The nominal pull-down V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the  
inner bounding lines of the V-I curve.  
2. The full variation in driver pull-down current from minimum to maximum process, temperature, and voltage lie  
within the outer bounding lines of the V-I curve.  
3. The nominal pull-up V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner  
bounding lines of the V-I curve.  
4. The full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie  
within the outer bounding lines of the V-I curve.  
5. The full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7,  
for device drain to source voltages from 0.1 to 1.0.  
6. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain  
to source voltages from 0.1 to 1.0 V.  
140  
Maximum  
120  
100  
Nominal High  
80  
60  
40  
Nominal Low  
Minimum  
20  
0
0
0.5  
1
1.5  
2
2.5  
VDDQ - VOUT (V)  
Figure 34 Normal Strength Pull-down Characteristics  
0
-20  
-40  
-60  
-80  
Minimum  
Nominal Low  
-100  
-120  
-140  
-160  
Nominal High  
Maximum  
0
0.5  
1
1.5  
2
2.5  
VDDQ - VOUT (V)  
Figure 35 Normal Strength Pull-up Characteristics  
Data Sheet  
63  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
Table 16  
Normal Strength Pull-down and Pull-up Currents  
Pulldown Current (mA)  
Voltage (V)  
Pullup Current (mA)  
Nominal  
Low  
Nominal  
High  
min.  
max.  
Nominal  
Low  
Nominal  
High  
min.  
max.  
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
1.7  
1.8  
1.9  
2.0  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
6.0  
6.8  
4.6  
9.6  
-6.1  
-7.6  
-4.6  
-10.0  
12.2  
18.1  
24.1  
29.8  
34.6  
39.4  
43.7  
47.5  
51.3  
54.1  
56.2  
57.9  
59.3  
60.1  
60.5  
61.0  
61.5  
62.0  
62.5  
62.9  
63.3  
63.8  
64.1  
64.6  
64.8  
65.0  
13.5  
20.1  
26.6  
33.0  
39.1  
44.2  
49.8  
55.2  
60.3  
65.2  
69.9  
74.2  
78.4  
82.3  
85.9  
89.1  
92.2  
95.3  
97.2  
99.1  
100.9  
101.9  
102.8  
103.8  
104.6  
105.4  
9.2  
18.2  
-12.2  
-18.1  
-24.0  
-29.8  
-34.3  
-38.1  
-41.1  
-43.8  
-46.0  
-47.8  
-49.2  
-50.0  
-50.5  
-50.7  
-51.0  
-51.1  
-51.3  
-51.5  
-51.6  
-51.8  
-52.0  
-52.2  
-52.3  
-52.5  
-52.7  
-52.8  
-14.5  
-21.2  
-27.7  
-34.1  
-40.5  
-46.9  
-53.1  
-59.4  
-65.5  
-71.6  
-77.6  
-83.6  
-89.7  
-95.5  
-101.3  
-107.1  
-112.4  
-118.7  
-124.0  
-129.3  
-134.6  
-139.9  
-145.2  
-150.5  
-155.3  
-160.1  
-9.2  
-20.0  
13.8  
18.4  
23.0  
27.7  
32.2  
36.8  
39.6  
42.6  
44.8  
46.2  
47.1  
47.4  
47.7  
48.0  
48.4  
48.9  
49.1  
49.4  
49.6  
49.8  
49.9  
50.0  
50.2  
50.4  
50.5  
26.0  
-13.8  
-18.4  
-23.0  
-27.7  
-32.2  
-36.0  
-38.2  
-38.7  
-39.0  
-39.2  
-39.4  
-39.6  
-39.9  
-40.1  
-40.2  
-40.3  
-40.4  
-40.5  
-40.6  
-40.7  
-40.8  
-40.9  
-41.0  
-41.1  
-41.2  
-29.8  
33.9  
-38.8  
41.8  
-46.8  
49.4  
-54.4  
56.8  
-61.8  
63.2  
-69.5  
69.9  
-77.3  
76.3  
-85.2  
82.5  
-93.0  
88.3  
-100.6  
-108.1  
-115.5  
-123.0  
-130.4  
-136.7  
-144.2  
-150.5  
-156.9  
-163.2  
-169.6  
-176.0  
-181.3  
-187.6  
-192.9  
-198.2  
93.8  
99.1  
103.8  
108.4  
112.1  
115.9  
119.6  
123.3  
126.5  
129.5  
132.4  
135.0  
137.3  
139.2  
140.8  
Table 17  
Pull-down and Pull-up Process Variations and Conditions  
Parameter  
Nominal  
25 °C  
Minimum  
Maximum  
Operating Temperature  
VDD/VDDQ  
0 °C  
70 °C  
2.5 V  
2.3 V  
2.7 V  
Data Sheet  
64  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
5.1  
Weak Strength Pull-down and Pull-up Characteristics  
1. The weak pull-down V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner  
bounding lines of the V-I curve.  
2. The weak pull-up V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner  
bounding lines of the V-I curve.  
3. The full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie  
within the outer bounding lines of the V-I curve.  
4. The full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7,  
for device drain to source voltages from 0.1 to 1.0.  
5. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain  
to source voltages from 0.1 to 1.0 V.  
80  
Maximum  
70  
60  
50  
40  
30  
20  
10  
0
Typical high  
Typical low  
Minimum  
0,0  
0,5  
1,0  
1,5  
Vout [V]  
2,0  
2,5  
Figure 36 Weak Strength Pull-down Characteristics  
0,0  
0,0  
0,5  
1,0  
1,5  
2,0  
2,5  
-10,0  
-20,0  
-30,0  
-40,0  
-50,0  
-60,0  
-70,0  
-80,0  
Minimum  
Typical low  
Typical high  
Maximum  
Vout [V]  
Figure 37 Weak Strength Pull-up Characteristics  
Data Sheet  
65  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
Table 18  
Weak Strength Driver Pull-down and Pull-up Characteristics  
Pulldown Current (mA) Pullup Current (mA)  
Voltage (V)  
Nominal  
Low  
Nominal  
High  
min.  
max.  
Nominal  
Low  
Nominal  
High  
min.  
max.  
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
1.7  
1.8  
1.9  
2.0  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
3.4  
3.8  
2.6  
5.0  
-3.5  
-4.3  
-2.6  
-5.0  
6.9  
7.6  
5.2  
9.9  
-6.9  
-8.2  
-5.2  
-9.9  
10.3  
13.6  
16.9  
19.6  
22.3  
24.7  
26.9  
29.0  
30.6  
31.8  
32.8  
33.5  
34.0  
34.3  
34.5  
34.8  
35.1  
35.4  
35.6  
35.8  
36.1  
36.3  
36.5  
36.7  
36.8  
11.4  
15.1  
18.7  
22.1  
25.0  
28.2  
31.3  
34.1  
36.9  
39.5  
42.0  
44.4  
46.6  
48.6  
50.5  
52.2  
53.9  
55.0  
56.1  
57.1  
57.7  
58.2  
58.7  
59.2  
59.6  
7.8  
14.6  
19.2  
23.6  
28.0  
32.2  
35.8  
39.5  
43.2  
46.7  
50.0  
53.1  
56.1  
58.7  
61.4  
63.5  
65.6  
67.7  
69.8  
71.6  
73.3  
74.9  
76.4  
77.7  
78.8  
79.7  
-10.3  
-13.6  
-16.9  
-19.4  
-21.5  
-23.3  
-24.8  
-26.0  
-27.1  
-27.8  
-28.3  
-28.6  
-28.7  
-28.9  
-28.9  
-29.0  
-29.2  
-29.2  
-29.3  
-29.5  
-29.5  
-29.6  
-29.7  
-29.8  
-29.9  
-12.0  
-15.7  
-19.3  
-22.9  
-26.5  
-30.1  
-33.6  
-37.1  
-40.3  
-43.1  
-45.8  
-48.4  
-50.7  
-52.9  
-55.0  
-56.8  
-58.7  
-60.0  
-61.2  
-62.4  
-63.1  
-63.8  
-64.4  
-65.1  
-65.8  
-7.8  
-14.6  
-19.2  
-23.6  
-28.0  
-32.2  
-35.8  
-39.5  
-43.2  
-46.7  
-50.0  
-53.1  
-56.1  
-58.7  
-61.4  
-63.5  
-65.6  
-67.7  
-69.8  
-71.6  
-73.3  
-74.9  
-76.4  
-77.7  
-78.8  
-79.7  
10.4  
13.0  
15.7  
18.2  
20.8  
22.4  
24.1  
25.4  
26.2  
26.6  
26.8  
27.0  
27.2  
27.4  
27.7  
27.8  
28.0  
28.1  
28.2  
28.3  
28.3  
28.4  
28.5  
28.6  
-10.4  
-13.0  
-15.7  
-18.2  
-20.4  
-21.6  
-21.9  
-22.1  
-22.2  
-22.3  
-22.4  
-22.6  
-22.7  
-22.7  
-22.8  
-22.9  
-22.9  
-23.0  
-23.0  
-23.1  
-23.2  
-23.2  
-23.3  
-23.3  
Data Sheet  
66  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
5.2  
AC Characteristics  
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating  
Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.)  
Note:  
1. All voltages referenced to VSS  
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/  
supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage  
range specified.  
3. Figure 38 represents the timing reference load used in defining the relevant timing parameters of the part. It  
is not intended to be either a precise representation of the typical system environment nor a depiction of the  
actual load presented by a production tester. System designers will use IBIS or other simulation tools to  
correlate the timing reference load to a system environment. Manufacturers will correlate to their production  
test conditions (generally a coaxial transmission line terminated at the tester electronics).  
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is  
still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for  
the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/  
ns in the range between VIL(AC) and VIH(AC)  
.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively  
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal  
does not ring back above (below) the DC input LOW (HIGH) level).  
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR  
SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the  
latest JEDEC specification for DDR components.  
VTT  
50 Ω  
Output  
Timing Reference Point  
(VOUT  
)
30 pF  
Figure 38 AC Output Load Circuit Diagram / Timing Reference Load  
AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100  
Parameter  
Symbol –5  
DDR400B  
–6  
–7  
Unit  
Note/ Test  
Condition  
DDR333  
DDR266A  
1)  
Min. Max.  
Min. Max. Min.  
Max.  
2)3)4)5)  
2)3)4)5)  
DQ output access time from CK/ tAC  
CK  
–0.5 +0.5  
–0.7 +0.7  
–0.75 +0.75  
ns  
ns  
DQS output access time from CK/ tDQSCK –0.5 +0.5  
–0.6 +0.6  
–0.75 +0.75  
CK  
2)3)4)5)  
2)3)4)5)  
CK high-level width  
CK low-level width  
tCH  
tCL  
0.45 0.55  
0.45 0.55  
0.45 0.55  
0.45 0.55  
0.45  
0.45  
0.55  
0.55  
tCK  
tCK  
Data Sheet  
67  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100  
Parameter  
Symbol –5  
DDR400B  
–6  
–7  
Unit  
Note/ Test  
Condition  
DDR333  
DDR266A  
1)  
Min. Max.  
Min. Max. Min.  
Max.  
2)3)4)5)  
Clock Half Period  
Clock cycle time  
tHP  
tCK  
min. (tCL, tCH  
)
min. (tCL  
tCH  
,
min. (tCL, tCH  
)
ns  
ns  
ns  
ns  
)
5
12  
12  
12  
6
12  
12  
12  
7
7
12  
12  
CL = 3.0  
2)3)4)5)  
6
6
CL = 2.5  
2)3)4)5)  
7.5  
7.5  
7.5  
12  
CL = 2.0  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)6)  
DQ and DM input hold time  
DQ and DM input setup time  
tDH  
tDS  
0.4  
0.4  
2.2  
0.45  
0.45  
2.2  
0.5  
0.5  
2.2  
ns  
ns  
ns  
Control and Addr. input pulse  
width (each input)  
tIPW  
2)3)4)5)6)  
2)3)4)5)7)  
2)3)4)5)7)  
2)3)4)5)  
DQ and DM input pulse width  
(each input)  
tDIPW  
tHZ  
1.75  
1.75  
1.75  
ns  
ns  
ns  
tCK  
ns  
ns  
ns  
ns  
Data-out high-impedance time  
from CK/CK  
+0.7  
–0.7 +0.7  
–0.7 +0.7  
0.75 1.25  
+0.75  
Data-out low-impedance time  
from CK/CK  
tLZ  
–0.7 +0.7  
0.72 1.25  
–0.75 +0.75  
st  
Write command to 1 DQS  
tDQSS  
tDQSQ  
0.75  
1.25  
+0.5  
0.5  
latching transition  
DQS-DQ skew (DQS and  
associated DQ signals)  
+0.40  
+0.40  
+0.50  
+0.50  
+0.40  
+0.45  
+0.50  
+0.55  
TFBGA  
2)3)4)5)  
TSOPII  
2)3)4)5)  
Data hold skew factor  
tQHS  
TFBGA  
+0.75  
+0.75  
2)3)4)5)  
TSOPII  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
DQ/DQS output hold time  
tQH  
tHP tQHS  
ns  
DQS input low (high) pulse width tDQSL,H 0.35  
(write cycle)  
0.35  
0.2  
0.2  
2
0.35  
0.2  
0.2  
2
tCK  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
DQS falling edge to CK setup  
time (write cycle)  
tDSS  
0.2  
0.2  
2
tCK  
tCK  
tCK  
DQS falling edge hold time from tDSH  
CK (write cycle)  
Mode register set command cycle tMRD  
time  
2)3)4)5)8)  
2)3)4)5)9)  
2)3)4)5)  
Write preamble setup time  
Write postamble  
tWPRES  
tWPST  
tWPRE  
0
0
0
ns  
0.40 0.60  
0.25  
0.40 0.60  
0.25  
0.40  
0.25  
0.60  
tCK  
tCK  
Write preamble  
Data Sheet  
68  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100  
Parameter  
Symbol –5  
DDR400B  
Min. Max.  
–6  
–7  
Unit  
Note/ Test  
Condition  
DDR333  
DDR266A  
1)  
Min. Max. Min.  
Max.  
Address and control input setup tIS  
time  
0.6  
0.7  
0.6  
0.7  
0.9  
1.1  
0.75  
1.1  
0.9  
1.0  
0.9  
1.0  
ns  
ns  
ns  
ns  
fast slew  
rate  
3)4)5)6)10)  
0.8  
slow slew  
rate  
3)4)5)6)10)  
Address and control input hold  
time  
tIH  
0.75  
0.8  
fast slew  
rate  
3)4)5)6)10)  
1.1  
slow slew  
rate  
3)4)5)6)10)  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
Read preamble  
tRPRE  
tRPST  
tRAS  
tRC  
0.9  
0.9  
1.1  
tCK  
tCK  
Read postamble  
0.40 0.60  
0.40 0.60  
70E+3 42  
0.40  
0.60  
Active to Precharge command  
40  
55  
70E+3 45  
120E+3 ns  
Active to Active/Auto-refresh  
command period  
60  
65  
ns  
2)3)4)5)  
Auto-refresh to Active/Auto-  
refresh command period  
tRFC  
70  
72  
75  
ns  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
Active to Read or Write delay  
Precharge command period  
Active to Autoprecharge delay  
tRCD  
tRP  
tRAP  
tRRD  
15  
15  
18  
18  
20  
20  
ns  
ns  
ns  
ns  
t
or t  
RASmin  
RCD  
Active bank A to Active bank B  
command  
10  
12  
15  
15  
2)3)4)5)  
Write recovery time  
tWR  
15  
15  
ns  
2)3)4)5)11)  
Auto precharge write recovery + tDAL  
tCK  
precharge time  
2)3)4)5)  
Internal write to read command tWTR  
delay  
2
7.8  
1
7.8  
1
7.8  
tCK  
ns  
2)3)4)5)  
Exit self-refresh to non-read  
command  
tXSNR  
tXSRD  
tREFI  
75  
200  
75  
200  
75  
200  
2)3)4)5)  
Exit self-refresh to read  
command  
tCK  
µs  
2)3)4)5)12)  
Average Periodic Refresh  
Interval  
1) 0 °C TA 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V  
(DDR400)  
2) Input slew rate 1 V/ns for DDR400, DDR333  
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference  
level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns.  
4) Inputs are not recognized as valid until VREF stabilizes.  
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT  
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.  
Data Sheet  
69  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred  
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).  
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.  
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were  
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,  
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS  
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but  
system performance (bus turnaround) degrades accordingly.  
10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/  
ns, measured between VIH(ac) and VIL(ac)  
.
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock  
cycle time.  
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.  
Table 19  
IDD Conditions  
Parameter  
Symbol  
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN  
;
IDD0  
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once  
every two clock cycles.  
Operating Current: one bank; active/read/precharge; Burst = 4;  
IDD1  
Refer to the following page for detailed test conditions.  
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VILMAX; tCK  
tCKMIN  
=
IDD2P  
IDD2F  
Precharge Floating Standby Current: CS VIHMIN, all banks idle;  
CKE VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF  
for DQ, DQS and DM.  
Precharge Quiet Standby Current:  
IDD2Q  
CS VIHMIN, all banks idle; CKE VIHMIN; tCK = tCKMIN, address and other control inputs stable  
at VIHMIN or VILMAX; VIN = VREF for DQ, DQS and DM.  
Active Power-Down Standby Current: one bank active; power-down mode;  
CKE VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.  
IDD3P  
IDD3N  
Active Standby Current: one bank active; CS VIHMIN; CKE VIHMIN; tRC = tRASMAX; tCK = tCKMIN  
;
DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per  
clock cycle.  
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs IDD4R  
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200  
and DDR266A, CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA  
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs IDD4W  
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200  
and DDR266A, CL = 3 for DDR333; tCK = tCKMIN  
Auto-Refresh Current: tRC = tRFCMIN, burst refresh  
IDD5  
IDD6  
IDD7  
Self-Refresh Current: CKE 0.2 V; external clock on; tCK = tCKMIN  
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for  
detailed test conditions.  
Data Sheet  
70  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
Table 20  
IDD Specification  
–7  
1)  
–6  
–5  
Unit  
Note/Test Condition  
DDR266A  
DDR333  
DDR400B  
Symbol  
Typ.  
65  
Max.  
78  
Typ.  
75  
Max.  
90  
Typ.  
80  
Max.  
2)3)  
IDD0  
100  
120  
110  
140  
4
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
×4/×8  
3)  
80  
95  
90  
110  
100  
125  
4
100  
90  
×16  
3)  
IDD1  
75  
90  
85  
×4/×8  
3)  
90  
110  
4
105  
1.6  
25  
115  
1.7  
30  
×16  
3)  
3)  
3)  
3)  
IDD2P  
IDD2F  
IDD2Q  
IDD3P  
IDD3N  
1.5  
20  
24  
30  
36  
15  
21  
17  
24  
19  
26  
9
13  
11  
15  
12  
16  
3)  
3)  
3)  
29  
35  
35  
41  
39  
47  
×4/×8  
3)  
31  
37  
37  
44  
42  
50  
×16  
IDD4R  
IDD4W  
67  
78  
77  
90  
85  
100  
145  
105  
150  
245  
5.2  
310  
340  
×4/×8  
3)  
85  
100  
83  
105  
81  
125  
95  
120  
90  
×16  
71  
×4/×8  
3)  
90  
105  
205  
5.1  
243  
255  
110  
185  
2.7  
234  
255  
130  
220  
5.2  
279  
310  
125  
205  
2.8  
260  
285  
×16  
3)4)  
IDD5  
IDD6  
IDD7  
170  
2.6  
204  
215  
3)  
3)  
×4/×8  
3)  
×16  
1) Test conditions for typical values: VDD = 2.5 V (DDR266, DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for  
maximum values: VDD = 2.7 V, TA = 10 °C  
2) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for  
DDR333, and 200 MHz for DDR400.  
3) Input slew rate = 1 V/ns.  
4) Enables on-chip refresh and address counters.  
Data Sheet  
71  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Normal Strength Pull-down and Pull-up Characteristics  
5.2.1  
IDD Current Measurement Conditions  
IDD1: Operating Current: One Bank Operation  
1. Only one bank is accessed with tRCMIN. Burst Mode, Address and Control inputs on NOP edge are changing  
once per clock cycle. IOUT = 0 mA.  
2. Timing patterns  
a) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, CL = 2, BL = 4, tRCD = 3 × tCK, tRC = 9 × tCK, tRAS = 5 × tCK  
Setup: A0 N N R0 N P0 N N N  
Read: A0 N N R0 N P0 N NN - repeat the same timing with random address changing  
50% of data changing at every burst  
b) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, CL = 2.5, BL = 4, tRCD = 3 × tCK, tRC = 9 × tCK, tRAS = 5 × tCK  
Setup: A0 N N R0 N P0 N N N  
Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing  
50% of data changing at every burst  
c) DDR400 (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRCD = 3 × tCK, tRC = 11 × tCK, tRAS = 8 × tCK  
Setup: A0 N N R0 N N N N P0 N N  
Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing  
50% of data changing at every burst  
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP  
IDD7: Operating Current: Four Bank Operation  
1. Four banks are being interleaved with tRCMIN. Burst Mode, Address and Control inputs on NOP edge are not  
changing. IOUT = 0 mA.  
2. Timing patterns  
a) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, CL = 2, BL = 4, tRRD = 2 × tCK, tRCD = 3 × tCK  
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3  
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing  
50% of data changing at every burst  
b) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, CL = 2.5, BL = 4, tRRD = 2 × tCK, tRCD = 3 × tCK  
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3  
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing  
50% of data changing at every burst  
c) DDR400 (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRCD = 3 × tCK, tRC = 11 × tCK, tRAS = 8 × tCK  
Setup: A0 N N R0 N N N N P0 N N  
Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing  
50% of data changing at every burst  
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP  
Data Sheet  
72  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
6
Timing Diagrams  
tDQSL  
tDQSH  
DQS  
DQ  
tDH  
tDS  
DI n  
tDH  
tDS  
DM  
DI n = Data In for column n.  
3 subsequent elements of data in are applied in programmed order following DI n.  
Don’t Care  
Figure 39 Data Input (Write), Timing Burst Length = 4  
DQS  
tDQSQ max  
tQH  
DQ  
tQH (Data output hold time from DQS)  
t
DQSQ and tQH are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration.  
.
tDQSQ and tQH both apply to each of the four relevant edges of DQS.  
tDQSQ max. is used to determine the worst case setup time for controller data capture.  
t
QH is used to determine the worst case hold time for controller data capture.  
Figure 40 Data Output (Read), Timing Burst Length = 4  
Data Sheet  
73  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 41 Initialize and Mode Register Sets  
Data Sheet  
74  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 42 Power Down Mode  
Data Sheet  
75  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 43 Auto Refresh Mode  
Data Sheet  
76  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 44 Self Refresh Mode  
Data Sheet  
77  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 45 Read without Auto Precharge (Burst Length = 4)  
Data Sheet  
78  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 46 Read with Auto Pre charge (Burst Length = 4)  
Data Sheet  
79  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 47 Bank Read Access (Burst Length = 4)  
Data Sheet  
80  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 48 Write without Auto Precharge (Burst Length = 4)  
Data Sheet  
81  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 49 Write with Auto Pre charge (Burst Length = 4)  
Data Sheet  
82  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 50 Bank Write Access (Burst Length = 4)  
Data Sheet  
83  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Timing Diagrams  
Figure 51 Write DM Operation (Burst Length = 4)  
Data Sheet  
84  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
System Characteristics for DDR SDRAMs  
7
System Characteristics for DDR SDRAMs  
The following specification parameters are required in systems using DDR400, DDR333 & DDR266 devices to  
ensure proper system performance. These characteristics are for system simulation purposes and are guaranteed  
by design.  
Table 21  
Input Slew Rate for DQ, DQS, and DM  
AC Characteristics  
Parameter  
Symbol  
DDR400  
Min. Max. Min. Max. Min. Max.  
0.5 4.0 0.5 4.0  
DDR333  
DDR266  
Units Notes  
1)2)  
DM/DQS inout slew rate measured berween DCSLEW 0.5 4.0  
IH(DC), VIL (DC), and VIL(DC), VIH (DC)  
V/ns  
V
1) Pullup slew rate is characterized under the test conditions as shown in Figure 52.  
2) DQS, DM, amd DQ input slew rate is specified to prevent doble clocking of data and preserve setup and hold times. Signal  
transitions through the DC region must be monotonic.  
Table 22  
Input Setup & Hold Time Derating for Slew Rate  
Input Slew Rate  
0.5 V/ns  
tIS  
0
tIH  
0
Units  
ps  
Notes  
1)  
0.4 V/ns  
+50  
+100  
0
ps  
0.3 V/ns  
0
ps  
1) A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as  
shown in Table 22. The input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to  
VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. Aderating factor applies to speed bins DDR200,  
DDR266, and DDR333.  
Table 23  
Input/Output Setup and Hold TIme Derating for Slew Rate  
I/O Input Slew Rate  
0.5 ns/V  
tDS  
0
tDH  
Units  
ps  
Notes  
1)  
0
0.4 ns/V  
+75  
+100  
+75  
+100  
ps  
0.3 ns/V  
ps  
1) Table 23 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew  
rate is based on the lesser of the AV – AC slew rate and the DC – DC slew rate. The input slew rate is based  
on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), and similarly for rising  
transitions. A derating factor applies to speed bins DDR200, DDR266 and DDR333.  
Table 24  
Input/Output Setup and Hold Derating for Rise/Fall Delta Slew Rate  
Delta Slew Rate  
±0.0 ns/V  
tDS  
0
tDH  
Units  
ps  
Notes  
1)  
0
±0.25 ns/V  
±0.5 ns/V  
+50  
+100  
+50  
+100  
ps  
ps  
1) A derating factor will be used to increase tDS and tDH in the case where DQ, DM and DQS slew rates differ, as shown in  
Tables 15 & 16. Input slew rate is based on the larger of AC – AC delta rise, fall rate and DC – DC delta rise, fall rate. Input  
slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for  
rising transitions.  
The delta rise/fall rate is calculated as:{1/(Slew Rate1)} – {1/(Slew Rate2)}  
For example: If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is –0.5 ns/V. Using the  
table given, this would result in the need for an increase in tDS and tDH of 100 ps. A derating factor applies to speed bins  
DDR200, DDR266, and DDR333.  
Data Sheet  
85  
Rev. 1.2, 2004-06  
08122003-RMYD-6BJP  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
System Characteristics for DDR SDRAMs  
Table 25  
Output Slew Rate Characteristrics (×4, ×8 Devices only)  
Slew Rate Characteristic  
Pullup Slew Rate  
Pulldown Slew Rate  
Typical Range (V/ns) Minumum (V/ns)  
Maximum (V/ns) Notes  
1)2)3)4)5)6)  
1.2 – 2.5  
1.2 – 2.5  
1.0  
1.0  
4.5  
2)3)4)5)5)7)2)2)  
4.5  
1) Pullup slew rate is characterized under the test conditions as shown in Figure 52  
2) Pullup slew rate is measured between (VDDQ/2 – 320 mV ± 250 mV)  
Pulldown slew rate is measured between (VDDQ/2 + 320 mV ± 250 mV)  
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one  
output switching.  
Example: For typical slew rate, DQ0 is switching  
For minimum slew rate, all DQ bits are switchiung worst case pattern  
For maximum slew rate, only one DQ is switching from either high to low, or low to high.  
the remainig DQ bits remain the same as previous state.  
3) Evaluation conditions  
Typical: 25 °C (T Ambient), VDDQ = nominal, typical process  
Minimum: 70 °C (T Ambient), VDDQ = minimum, slow – slow process  
Maximum: 0 °C (T Ambient), VDDQ = maximum, fast – fast process  
4) Verified under typical conditions for qualification purposes.  
5) TSOP II package devices only.  
6) Only intended for operation up to 266 Mbps per pin.  
7) Pulldown slew rate is measured under the test conditions shown in Figure 53.  
Table 26  
Output Slew Rate Characteristics (×16 Devices only)  
Slew Rate Characteristic  
Pullup Slew Rate  
Typical Range (V/ns)  
1.2 – 2.5  
Minimum (V/ns)  
Maximum(V/ns)  
Notes  
1)2)3)4)5)6)  
0.7  
0.7  
5.0  
5.0  
7)  
Pulldown Slew Rate  
1.2 – 2.5  
1) Pullup slew rate is characterizted under the test conditions as shown in Figure 52  
2) Pullup slew rate is measured between (VDDQ/2 – 320 mV ± 250 mV)  
Pulldown slew rate is measured between (VDDQ/2 + 320 mV ± 250mV)  
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one  
output switching.  
Example: For typical slew rate, DQ0 is switching  
For minimum slew rate, all DQ bits are switchiung worst case pattern  
For maximum slew rate, only one DQ is switching from either high to low, or low to high.  
the remainig DQ bits remain the same as previous state.  
3) Evaluation conditions  
Typical: 25 °C (T Ambient), VDDQ = nominal, typical process  
Minimum: 70 °C (T Ambient), VDDQ = minimum, slow – slow process  
Maximum: 0 °C (T Ambient), VDDQ = maximum, fast – fast process  
4) Verified under typical conditions for qualification purposes.  
5) TSOP II package devices only.  
6) Only intended for operation up to 266 Mbps per pin.  
7) Pulldown slew rate is measured under the test conditions shown in Figure 53.  
Table 27  
Output Slew Rate Matching Ratio Characteristics  
Slew Rate Characteristic  
Parameter  
DDR266A  
Min.  
DDR266B  
Min.  
DDR200  
Min.  
Notes  
Max.  
Max.  
Max.  
1) 2)  
Output SLew Rate Matching  
Ratio (Pullup to Pulldown)  
0.71  
1.4  
Data Sheet  
86  
Rev. 1.2, 2004-06  
08122003-RMYD-6BJP  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
System Characteristics for DDR SDRAMs  
1) The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire  
temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown  
drivers due to process variation.  
2) DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal  
transitions through the DC region must be monotonic  
VDDQ  
50 Ω  
Output  
Test point  
MPBD1990  
Figure 52 Pullup slew rate test load  
Test point  
Output  
50 Ω  
VSSQ  
MPBD2000  
Figure 53 Pulldown slew rate test load  
Data Sheet  
87  
Rev. 1.2, 2004-06  
08122003-RMYD-6BJP  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Package Outlines  
8
Package Outlines  
There are two package types used for this product family each in lead-free and lead-containing assembly:  
P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package  
Table 28  
TFBGA Common Package Properties (non-green/green)  
Description  
Ball Size  
Size  
Units  
mm  
0.460  
0.350  
0.450  
Recommended Landing Pad  
Recommended Solder Mask  
mm  
mm  
P-TSOPII: Plastic Thin Small Outline Package Type II  
12  
11 x 1 = 11  
1
0.18 MAX.  
0.2  
2)  
B
2)  
4)  
3)  
1) 5)  
A
0.1  
C
0.1  
C
60x  
ø0.15  
ø0.08  
±0.05  
ø0.46  
M
M
A B  
C SEATING PLANE  
C
1) Dummy Pads without Ball  
2) Middle of Packages Edges  
3) Package Orientation Mark A1  
4) Bad Unit Marking (BUM)  
5) Die Sort Fiducial  
GPA09554  
Figure 54 Package Outline of P-TFBGA-60-[9/22] (green/non-green)  
Data Sheet  
88  
Rev. 1.2, 2004-06  
HYB25D512[40/16/80]0B[E/F/C/T]  
512Mbit Double Data Rate SDRAM  
Package Outlines  
Gage Plane  
±0.13  
10.16  
±0.1  
±0.2  
0.65 Basic  
0.5  
+0.1  
0.805 REF  
0.1  
Seating Plane  
0.35  
-0.05  
11.76  
±0.13  
22.22  
Lead 1  
GPX09261  
Figure 55 Package Outline of P-TSOPII-66-1 (green/non-green)  
Data Sheet  
89  
Rev. 1.2, 2004-06  
w w w . i n f i n e o n . c o m  
Published by Infineon Technologies AG  

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