HYB25D256400CC-6_技术文档

Data Sheet, Rev. 1.6, Dec. 2004

HYB25D256[40/80/16]0CE(L)

HYB25D256[40/80/16]0C[T/C/F]

256 Mbit Double-Data-Rate SDRAM

Memory Products

N e v e r s t o p t h i n k i n g .

Edition 2004-12

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

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For further information on technology, delivery terms and conditions and prices please contact your nearest

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Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Data Sheet, Rev. 1.6, Dec. 2004

HYB25D256[40/80/16]0CE(L)

HYB25D256[40/80/16]0C[T/C/F]

256 Mbit Double-Data-Rate SDRAM

Memory Products

N e v e r s t o p t h i n k i n g .

HYB25D256[40/80/16]0CE(L), HYB25D256[40/80/16]0C[T/C/F]

Revision History:

Rev. 1.6

2004-12

Previous Version:

Rev. 1.5

2004-11

19,20,21

editorial change

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Template: mp_a4_v1.0_2003-04-25.fm

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1

1.2

2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.1

3.2

3.2.1

3.2.2

3.2.3

3.2.4

3.3

3.3.1

3.3.2

3.4

3.5

3.5.1

3.5.2

3.5.3

3.5.4

3.5.5

3.5.6

3.6

4

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Normal Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Weak Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.1

4.2

4.3

4.4

4.5

I

_DDCurrent Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Write Command: Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Read Command: Data Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Initialization and Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Power: Power Down Mode Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Refresh: Auto Refresh Mode Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Refresh: Self Refresh Mode Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Read: Without Auto Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Read: With Auto Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Read: Bank Read Access Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Write: Without Auto Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Write: With Auto Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Write: Bank Write Access Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Write: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

5.11

5.12

5.13

6

7

System Characteristics for DDR SDRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Data Sheet

5

Rev. 1.6, 2004-12

08012003-8754-PAQX

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

List of Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Pin Configuration P-TFBGA-60-9 Top View, see the balls throught the package . . . . . . . . . . . . . 17

Pin Configuration P-TSOPII-66-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block Diagram 16 Mbit × 4 I/O × 4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Diagram 8 Mbit × 8 I/O × 4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Block Diagram 4 Mbit × 16 I/O × 4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Required CAS Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

t

_RCDand t_RRDDefinition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 10 Read Burst: CAS Latencies (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11 Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 12 Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 14 Terminating a Read Burst: CAS Latencies (Burst Length = 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 15 Read to Write: CAS Latencies (Burst Length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 16 Read to Precharge: CAS Latencies (Burst Length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 17 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18 Write Burst (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19 Write to Write (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 20 Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 21 Random Write Cycles (Burst Length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 22 Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . 47

Figure 23 Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8). . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 24 Write to Read: Min. DQSS, Odd Number of Data (3-bit Write), Interrupting (CL2; BL8) . . . . . . . . 49

Figure 25 Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8) . . . . . . . . . . . . 50

Figure 26 Write to Precharge: Non-Interrupting (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 27 Write to Precharge: Interrupting (Burst Length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 28 Write to Precharge: Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (BL 4 or 8). 53

Figure 29 Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8) . . . . . . . . . 54

Figure 30 Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 31 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 32 Clock frequency change in pre charge power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 33 Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 34 Normal Strength Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 35 Normal Strength Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 36 Weak Strength Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 37 Weak Strength Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 38 AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 39 Data Input (Write), Timing Burst Length = 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 40 Data Output (Read), Timing Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 41 Initialize and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 42 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 43 Auto Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 44 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 45 Read without Auto Precharge (Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 46 Read with Auto Precharge (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 47 Bank Read Access (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 48 Write without Auto Precharge (Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 49 Write with Auto Precharge (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 50 Bank Write Access (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 51 Write DM Operation (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 52 Pullup slew rate test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 53 Pulldown slew rate test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Data Sheet

6

Rev. 1.6, 2004-12

08012003-8754-PAQX

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

List of Figures

Figure 54 Package Outline of P-TFBGA-60-12 (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 55 Package Outline of P-TSOPII-66-1 (non-green/green). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Data Sheet

7

Rev. 1.6, 2004-12

08012003-8754-PAQX

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

List of Tables

Table 1

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information for Lead Containing Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ordering Information for Lead free (RoHS Compliant) Products . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . 57

Truth Table 2: Clock Enable (CKE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . 59

Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Electrical Characteristics and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Evaluation Conditions for I/O Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Normal Strength Pull-down and Pull-up Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Weak Strength Driver Pull-down and Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

AC Timing - Absolute Specifications for PC3200 and PC2700 . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

AC Timing - Absolute Specifications for PC2700 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 9

Table 8

Table 11

Table 10

Table 12

Table 13

Table 14

Table 15

Table 16

Table 18

Table 17

Table 19

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

Table 26

Table 27

Table 28

Table 29

Table 30

Table 31

Table 32

I

_DDConditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

_DDSpecification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Input Slew Rate for DQ, DQS, and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Input Setup & Hold Time Derating for Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Input/Output Setup and Hold TIme Derating for Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Input/Output Setup and Hold Derating for Rise/Fall Delta Slew Rate. . . . . . . . . . . . . . . . . . . . . . . 90

Output Slew Rate Characteristrics (×4, ×8 Devices only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Output Slew Rate Characteristics (×16 Devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Output Slew Rate Matching Ratio Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

TFBGA Common Package Properties (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Data Sheet

8

Rev. 1.6, 2004-12

08012003-8754-PAQX

256 Mbit Double-Data-Rate SDRAM

DDR SDRAM

HYB25D256[40/80/16]0CE(L)

HYB25D256[40/80/16]0C[T/C/F]

1

Overview

1.1

Features

•

Double data rate architecture: two data transfers per clock cycle

•

Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the

receiver

•

DQS is edge-aligned with data for reads and is center-aligned with data for writes

Differential clock inputs (CK and CK)

Four internal banks for concurrent operation

Data mask (DM) for write data

DLL aligns DQ and DQS transitions with CK transitions

Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

Burst Lengths: 2, 4, or 8

CAS Latency: 1.5 (DDR200 only), 2, 2.5, 3

Auto Precharge option for each burst access

Auto Refresh and Self Refresh Modes

RAS-lockout supported t_RAP=t_RCD

7.8 µs Maximum Average Periodic Refresh Interval

2.5 V (SSTL_2 compatible) I/O

V

_DDQ= 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); V_DDQ= 2.6 V ± 0.1 V (DDR400)

_DD= 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); V_DD= 2.6 V ± 0.1 V (DDR400)

P-TFBGA-60-12 package with 3 depopulated rows (8 × 12 mm²)

P-TSOPII-66 package

Lead- and halogene-free = green product

Table 1

Performance

Part Number Speed Code

Speed Grade

–5

–6

–7

Unit

—

MHz

Component

Module

@CL3

@CL2.5

@CL2

DDR400B

PC3200-3033

DDR333

PC2700–2533

166

133

DDR266A

PC2100-2033

—

143

133

max. Clock Frequency

f_CK3200

f_CK2.5166

f_CK2133

Data Sheet

9

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Overview

1.2

Description

The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing

268,435,456 bits. It is internally configured as a quad-bank DRAM.

The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer

two data words per clock cycle at the I/O pins.

A

single read or write access for the

256 Mbit Double-Data-Rate SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at

the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.

DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS

is edge-aligned with data for Reads and center-aligned with data for Writes.

The 256 Mbit Double-Data-Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going

HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are

registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both edges of CK.Read and write accesses to the DDR SDRAM

are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a

programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a

Read or Write command. The address bits registered coincident with the Active command are used to select the

bank and row to be accessed. The address bits registered coincident with the Read or Write command are used

to select the bank and the starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto

Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst

access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent

operation, thereby providing high effective bandwidth by hiding row precharge and activation time.

An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the

JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.

Note:The functionality described and the timing specifications included in this data sheet are for the DLL Enabled

mode of operation.

Table 2

Ordering Information for Lead Containing Products

Product Type²⁾

Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed

Package

Latencies

(MHz) Latencies

(MHz)

HYB25D256800CT–5

HYB25D256160CT–5

HYB25D256800CT–6

×8

×16

×8

3-3-3

200

2.5-3-3

166

DDR400B P-TSOPII-66

2.5-3-3

166

2-3-3

133

DDR333

HYB25D256800CT(L)–6 ×8

HYB25D256160CT–6

HYB25D256400CT–7

HYB25D256400CC–5

HYB25D256800CC–5

HYB25D256160CC–5

HYB25D256400CC–6

HYB25D256800CC–6

HYB25D256160CC–6

×16

×4

×8

×16

×4

×8

143

200

DDR266A

DDR400B P-TFBGA-60

3-3-3

2.5-3-3

2-3-3

166

133

2.5-3-3

166

DDR333

×16

Data Sheet

10

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Overview

Table 3

Ordering Information for Lead free (RoHS¹⁾Compliant) Products

Product Type²⁾

Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed

Package

Latencies

(MHz) Latencies

(MHz)

HYB25D256800CE–5A

HYB25D256160CE–5A

HYB25D256800CE–5

HYB25D256160CE–5

HYB25D256800CE–6

×8

×16

×8

×16

×8

2.5-3-3

200

166

2-3-3

133

DDR400A P-TSOPII-66

3-3-3

2.5-3-3

2-3-3

166

133

DDR400B

DDR333

2.5-3-3

HYB25D256800CE(L)–6 ×8

HYB25D256160CE–6

HYB25D256400CE–7

HYB25D256800CF–6

×16

×4

×8

143

166

DDR266A

DDR333

2.5-3-3

2-3-3

133

P-TFBGA-60

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic

equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January

2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and

polybrominated biphenyl ethers.

2) HYB: designator for memory components

25D: DDR SDRAMs at V_DDQ= 2.5 V

256: 256-Mbit density

400/800/160: Product variations ×4, ×8 and ×16

C: Die revision C

L: low power (available on request)

T/E/F/C: Package type TSOP(contains Lead), TSOP(Lead & Halone free), FBGA(Lead & Halone free) and FBGA (contains

Lead)

Data Sheet

11

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

2

Pin Configuration

The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the

Pin#/Buffer# column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted

in Figure 1 and that of the TSOP package in Figure 2

Table 4

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Buffer

Function

Type

Clock Signals

G2, 45

CK

I

SSTL

Clock Signal

Note:CK and CK are differential clock inputs. All address and

control input signals are sampled on the crossing of the

positive edge of CK and negative edge of CK. Output (read)

data is referenced to the crossings of CK and CK (both

directions of crossing).

G3, 46

H3, 44

CK

CKE

I

SSTL

Complementary Clock Signal

Clock Enable Rank

Note:CKE HIGH activates, and CKE Low deactivates, internal

clock signals and device input buffers and output drivers.

Taking CKE Low provides Precharge Power-Down and Self

Refresh operation (all banks idle), or Active Power-Down

(row Active in any bank). CKE is synchronous for power

down entry and exit, and for self refresh entry. CKE is

asynchronous for self refresh exit. CKE must be maintained

high throughout read and write accesses. Input buffers,

excluding CK, CK and CKE are disabled during power-

down. Input buffers, excluding CKE, are disabled during self

refresh. CKE is an SSTL_2 input, but will detect an

LVCMOS LOW level after V_DDis applied on first power up.

After V_REFhas become stable during the power on and

initialization sequence, it must be mantained for proper

operation of the CKE receiver. For proper self-refresh entry

and exit, V_REFmust be mantained to this input.

Control Signals

H7, 23

G8, 22

G7, 21

H8, 24

RAS

I

SSTL

Row Address Strobe

Column Address Strobe

Write Enable

CAS

WE

CS

Chip Select

Note:All commands are masked when CS is registered HIGH. CS

provides for external bank selection on systems with

multiple banks. CS is considered part of the command code.

The standard pinout includes one CS pin.

Address Signals

J8, 26

J7, 27

BA0

BA1

I

SSTL

Bank Address Bus 2:0

Note:BA0 and BA1 define to which bank an Active, Read, Write

or Precharge command is being applied. BA0 and BA1 also

determines if the mode register or extended mode register

is to be accessed during a MRS or EMRS cycle.

Data Sheet

12

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

Table 4

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Buffer

Function

Type

K7, 29

L8, 30

L7, 31

M8, 32

M2, 35

L3, 36

L2, 37

K3, 38

K2, 39

J3, 40

K8, 28

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

AP

A11

A12

I

SSTL

Address Bus 11:0

Note:Provide the row address for Active commands, and the

column address and Auto Precharge bit for Read/Write

commands, to select one location out of the memory array

in the respective bank. A10 is sampled during a Precharge

command to determine whether the Precharge applies to

one bank (A10 LOW) or all banks (A10 HIGH). If only one

bank is to be precharged, the bank is selected by BA0, BA1.

The address inputs also provide the op-code during a Mode

Register Set command.

J2, 41

H2, 42

Address Signal 12

Note:256 Mbit or larger dies

Note:128 Mbit or smaller dies

Address Signal 13

NC

A13

NC

I

—

SSTL

F9, 17

Note:1 Gbit based dies

NC

—

Note:512 Mbit or smaller dies

Data Signals ×4 organization

B7, 5

DQ0

DQ1

DQ2

DQ3

I/O

SSTL

Data Signal 3:0

D7, 11

D3, 56

B3, 62

Data Strobe ×4 organisation

E3, 51 DQS I/O

SSTL

Data Strobe

Note:Output with read data, input with write data. Edge-aligned

with read data, centered in write data. Used to capture write

data.

Data Mask ×4 organization

F3, 47

DM

I

SSTL

Data Mask:

Note:DM is an input mask signal for write data. Input data is

masked when DM is sampled HIGH coincident with that

input data during a Write access. DM is sampled on both

edges of DQS. Although DM pins are input only, the DM

loading matches the DQ and DQS loading.

Data Sheet

13

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

Table 4

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Buffer

Function

Type

Data Signals ×8 organization

A8, 2

B7, 5

C7, 8

D7, 11

D3, 56

C3, 59

B3, 62

A2, 65

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O

SSTL

Data Signal 7:0

Data Strobe ×8 organisation

E3, 51 DQS I/O

SSTL

Data Strobe

Note:Output with read data, input with write data. Edge-aligned

with read data, centered in write data. Used to capture write

data.

Data Mask ×8 organization

F3, 47 DM

I

SSTL

Data Mask

Note:DM is an input mask signal for write data. Input data is

masked when DM is sampled HIGH coincident with that

input data during a Write access. DM is sampled on both

edges of DQS. Although DM pins are input only, the DM

loading matches the DQ and DQS loading.

Data Signals ×16 organization

A8, 2

B9, 4

B7, 5

C9, 7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O

SSTL

Data Signal 15:0

C7, 8

D9, 10

D7, 11

E9, 13

E1, 54

D3, 56

D1, 57

C3, 59

C1, 60

B3, 62

B1, 63

A2, 65

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

Data Strobe ×16 organization

E3, 51

E7, 16

UDQS

LDQS

I/O

SSTL

Data Strobe Upper Byte

Data Strobe Lower Byte

Data Mask ×16 organization

Data Sheet

14

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

Table 4

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Buffer

Function

Type

F3, 47

F7, 20

UDM

LDM

I

SSTL

Data Mask Upper Byte

Data Mask Lower Byte

Power Supplies

F1, 49

V_REF

V_DDQ

AI

PWR

—

I/O Reference Voltage

I/O Driver Power Supply

A9, B2, C8,

D2, E8, 3, 9,

15, 55, 61

A7, F8, M3,

V_DD

PWR

—

Power Supply

M7, 1, 18, 33

A1, B8, C2,

D8, E2, 6, 12,

52, 58, 64

V_SSQ

F2, 34

Not Connected

A2, 65

V_SS

NC

PWR

NC

—

Power Supply

Not Connected

Note:×4 organization

Not Connected

Note:×4 organization

Not Connected

Note:×8 and ×4 organisation

Not Connected

Note:×8 and ×4 organization

Not Connected

Note:×8 and ×4 organization

Not Connected

Note:×4 organization

Not Connected

Note:×4 organization

Not Connected

Note:×8 and ×4 organization

Not Connected

Note:×8 and ×4 organization

Not Connected

Note:×8 and ×4 organization

Not Connected

A8, 2

B1, 63

B9, 4

C1, 60

C3, 59

C7, 8

C9, 7

D1, 57

D9, 10

E1, 54

E7, 16

E9, 13

F7, 20

Note:×8 and ×4 organization

Not Connected

Note:×8 and ×4 organization

Not Connected

Note:×8 and ×4 organization

Not Connected

Note:×8 and ×4 organization

Data Sheet

15

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

Table 4

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Buffer

Function

Type

F9, 14, 17, 19, NC

25,43, 50, 53

NC

—

Not Connected

Note:×16,×8 and ×4 organization

Table 5

Abbreviation

Abbreviations for Pin Type

Description

I

Standard input-only pin. Digital levels.

O

I/O

AI

PWR

GND

NC

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

Ground

Not Connected

Table 6

Abbreviation

SSTL

LV-CMOS

CMOS

OD

Abbreviations for Buffer Type

Description

Serial Stub Terminated Logic (SSTL2)

Low Voltage CMOS

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tristate, and

allows multiple devices to share as a wire-OR.

Data Sheet

16

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

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ꢎ

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ꢜ

ꢝ

ꢛ

ꢜ

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ꢀꢂ

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ꢀꢁꢂ

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ꢁꢏꢏ

ꢁꢑ

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ꢘꢁꢆ

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ꢁꢑ

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ꢁꢔ

ꢘꢁꢆ

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ꢁꢒ

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ꢐ

ꢖ

ꢒ

ꢕ

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ꢑ

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ꢀ_ꢅꢅ

ꢀ_ꢅꢅꢈ

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ꢅꢈꢆ

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ꢀ_ꢂꢂꢈ

ꢘ

ꢅꢈꢏꢒ

ꢅꢈꢏꢐ

ꢅꢈꢏꢆ

ꢅꢈꢏꢖ

ꢅꢈꢏꢏ

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ꢅꢈꢐ

ꢅꢈꢒ

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ꢞꢅꢈꢂ

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ꢅꢈꢏ

ꢅꢈꢖ

ꢀ_ꢂꢂꢈ

ꢀ_ꢅꢅꢈ

ꢀ_ꢂꢂꢈ

ꢀ_ꢂꢂ

ꢀ_ꢅꢅꢈ

ꢀ_ꢂꢂꢈ

ꢀ_ꢅꢅꢈ

ꢀ_ꢅꢅ

ꢀ

ꢅ

ꢅꢈꢕ

ꢍ

ꢅꢈꢑ

ꢟꢅꢈꢂ

ꢟꢅꢃ

ꢀꢉ

ꢅꢈꢔ

ꢀ_ꢌꢍꢎ

ꢎ

ꢊꢀꢚꢁꢏꢖ

ꢛ

ꢜ

ꢀꢉ

ꢀꢁꢂ

ꢀꢂ

ꢊꢀ,ꢁꢏꢐ ꢀꢉꢍ

ꢌꢁꢂ

ꢘꢁꢏ

ꢝ

ꢁꢏꢏ

ꢁꢑ

ꢁꢓ

ꢁꢔ

ꢘꢁꢆ

ꢉ

ꢁꢆ ꢁꢏꢆꢙꢁꢄ

ꢞ

ꢁꢇ

ꢁꢕ

ꢁꢐ

ꢁꢏ

ꢁꢖ

ꢀ_ꢂꢂ

ꢀ_ꢅꢅ

ꢃ

ꢀꢁꢅꢆꢃ

ꢁꢒ

ꢃꢄꢄꢅꢆꢆꢇꢆ

Figure 1

Pin Configuration P-TFBGA-60-9 Top View, see the balls throught the package

Data Sheet

17

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

ꢇꢒꢠꢃꢡꢠꢢꢠꢒ

ꢖꢐꢠꢃꢡꢠꢢꢠꢑ

ꢏꢇꢠꢃꢡꢠꢢꢠꢏꢇ

ꢀ_ꢅꢅ

ꢊꢋꢀꢋ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢅꢈꢆ

ꢀ_ꢂꢂꢈ

ꢊꢋꢀꢋ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢅꢈꢏ

ꢀ_ꢂꢂꢈ

ꢊꢋꢀꢋ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢀ_ꢅꢅ

ꢅꢈꢆ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢅꢈꢏ

ꢀ_ꢂꢂꢈ

ꢊꢋꢀꢋ

ꢅꢈꢐ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢅꢈꢖ

ꢀ_ꢂꢂꢈ

ꢊꢋꢀꢋ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢀ_ꢅꢅ

ꢅꢈꢆ

ꢀ_ꢅꢅꢈ

ꢅꢈꢏ

ꢅꢈꢐ

ꢀ_ꢂꢂꢈ

ꢅꢈꢖ

ꢅꢈꢒ

ꢀ_ꢅꢅꢈ

ꢅꢈꢕ

ꢅꢈꢇ

ꢀ_ꢂꢂꢈ

ꢅꢈꢔ

ꢊꢋꢀꢋ

ꢀ_ꢅꢅꢈ

ꢞꢅꢈꢂ

ꢏ

ꢇꢇ

ꢇꢕ

ꢇꢒ

ꢇꢖ

ꢇꢐ

ꢇꢏ

ꢇꢆ

ꢕꢓ

ꢕꢑ

ꢕꢔ

ꢕꢇ

ꢕꢕ

ꢕꢒ

ꢕꢖ

ꢕꢐ

ꢕꢏ

ꢕꢆ

ꢒꢓ

ꢒꢑ

ꢒꢔ

ꢒꢇ

ꢒꢕ

ꢒꢒ

ꢒꢖ

ꢒꢐ

ꢒꢏ

ꢒꢆ

ꢖꢓ

ꢖꢑ

ꢖꢔ

ꢖꢇ

ꢖꢕ

ꢖꢒ

ꢀ_ꢂꢂ

ꢐ

ꢅꢈꢏꢕ

ꢀ_ꢂꢂꢈ

ꢅꢈꢏꢒ

ꢅꢈꢏꢖ

ꢀ_ꢅꢅꢈ

ꢅꢈꢏꢐ

ꢅꢈꢏꢏ

ꢀ_ꢂꢂꢈ

ꢅꢈꢏꢆ

ꢅꢈꢓ

ꢀ_ꢅꢅꢈ

ꢅꢈꢑ

ꢊꢋꢀꢋ

ꢀ_ꢂꢂꢈ

ꢟꢅꢈꢂ

ꢊꢋꢀꢋ

ꢀ_ꢌꢍꢎ

ꢀ_ꢂꢂ

ꢅꢈꢔ

ꢀ_ꢂꢂꢈ

ꢊꢋꢀꢋ

ꢅꢈꢇ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢅꢈꢕ

ꢀ_ꢂꢂꢈ

ꢊꢋꢀꢋ

ꢅꢈꢒ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢀ_ꢂꢂꢈ

ꢅꢈꢂ

ꢊꢋꢀꢋ

ꢀ_ꢌꢍꢎ

ꢀ_ꢂꢂ

ꢊꢋꢀꢋ

ꢀ_ꢂꢂꢈ

ꢊꢋꢀꢋ

ꢅꢈꢖ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢀ_ꢂꢂꢈ

ꢊꢋꢀꢋ

ꢅꢈꢐ

ꢀ_ꢅꢅꢈ

ꢊꢋꢀꢋ

ꢀ_ꢂꢂꢈ

ꢅꢈꢂ

ꢊꢋꢀꢋ

ꢀ_ꢌꢍꢎ

ꢀ_ꢂꢂ

ꢖ

ꢒ

ꢕ

ꢇ

ꢔ

ꢑ

ꢓ

ꢏꢆ

ꢏꢏ

ꢏꢐ

ꢏꢖ

ꢏꢒ

ꢏꢕ

ꢏꢇ

ꢏꢔ

ꢏꢑ

ꢏꢓ

ꢐꢆ

ꢐꢏ

ꢐꢐ

ꢐꢖ

ꢐꢒ

ꢐꢕ

ꢐꢇ

ꢐꢔ

ꢐꢑ

ꢐꢓ

ꢖꢆ

ꢖꢏ

ꢖꢐ

ꢖꢖ

ꢊꢋꢀꢋꢚꢁꢏꢖ ꢊꢋꢀꢋꢚꢁꢏꢖ ꢊꢋꢀꢋꢚꢁꢏꢖ

ꢀ_ꢅꢅ

ꢊꢋꢀꢋ

ꢗꢍ

ꢀ_ꢅꢅ

ꢊꢋꢀꢋ

ꢗꢍ

ꢀ_ꢅꢅ

ꢊꢋꢀꢋ

ꢞꢅꢃ

ꢗꢍ

ꢟꢅꢃ

ꢀꢉ

ꢅꢃ

ꢀꢉ

ꢀꢁꢂ

ꢌꢁꢂ

ꢀꢂ

ꢀꢁꢂ

ꢌꢁꢂ

ꢀꢂ

ꢀꢁꢂ

ꢌꢁꢂ

ꢀꢂ

ꢀꢉ

ꢀꢉꢍ

ꢊꢋꢀꢋ

ꢀꢉꢍ

ꢊꢋꢀꢋ

ꢀꢉꢍ

ꢊꢋꢀꢋ

ꢘꢁꢆ

ꢘꢁꢏ

ꢊꢋꢀꢋ

ꢘꢁꢆ

ꢘꢁꢏ

ꢊꢋꢀꢋ

ꢘꢁꢆ

ꢘꢁꢏ

ꢊꢋꢀꢋꢚꢁꢏꢐ ꢊꢋꢀꢋꢚꢁꢏꢐ ꢊꢋꢀꢋꢚꢁꢏꢐ

ꢁꢏꢏ

ꢁꢓ

ꢁꢑ

ꢁꢔ

ꢁꢇ

ꢁꢕ

ꢁꢒ

ꢀ_ꢂꢂ

ꢁꢏꢏ

ꢁꢓ

ꢁꢑ

ꢁꢔ

ꢁꢇ

ꢁꢕ

ꢁꢒ

ꢀ_ꢂꢂ

ꢁꢏꢏ

ꢁꢓ

ꢁꢑ

ꢁꢔ

ꢁꢇ

ꢁꢕ

ꢁꢒ

ꢀ_ꢂꢂ

ꢁꢏꢆꢙꢁꢄ ꢁꢏꢆꢙꢁꢄ ꢁꢏꢆꢙꢁꢄ

ꢁꢆ

ꢁꢏ

ꢁꢆ

ꢁꢏ

ꢁꢆ

ꢁꢏ

ꢁꢐ

ꢁꢖ

ꢀ_ꢅꢅ

ꢃꢄꢄꢅꢆꢆꢔꢆ

Figure 2

Pin Configuration P-TSOPII-66-1

Data Sheet

18

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

Drivers

Receivers

Read Latch

Bank0

Row-Address Latch

& Decoder

Bank Control Logic

Refresh Counter

Row-Address MUX

Address Register

Figure 3

Block Diagram 16 Mbit × 4 I/O × 4 Internal Memory Banks

Data Sheet

19

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

Drivers

Receivers

Read Latch

Bank0

Row-Address Latch

& Decoder

Bank Control Logic

Refresh Counter

Row-Address MUX

Address Register

Figure 4

Block Diagram 8 Mbit × 8 I/O × 4 Internal Memory Banks

Data Sheet

20

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

Drivers

Receivers

Read Latch

Bank0

Row-Address Latch

& Decoder

Bank Control Logic

Refresh Counter

Row-Address MUX

Address Register

Figure 5

Block Diagram 4 Mbit × 16 I/O × 4 Internal Memory Banks

Data Sheet

21

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3

Functional Description

The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing

268,435,456 bits. The 256 Mbit Double-Data-Rate SDRAM is internally configured as a quad-bank DRAM.

The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer

two data words per clock cycle at the I/O pins.

A

single read or write access for the

256 Mbit Double-Data-Rate SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal

DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration

of an Active command, which is then followed by a Read or Write command. The address bits registered

coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the

bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used

to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information

covering device initialization, register definition, command descriptions and device operation.

3.1

Initialization

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation. The following criteria must be met:

No power sequencing is specified during power up or power down given the following criteria:

•

V

_DDand V_DDQare driven from a single power converter output

V

_TTmeets the specification

A minimum resistance of 42 Ω limits the input current from the V_TTsupply into any pin and V_REFtracks V_DDQ/2

or the following relationship must be followed:

•

V

_DDQis driven after or with V_DDsuch that V_DDQ< V_DD+ 0.3 V

_TTis driven after or with V_DDQsuch that V_TT< V_DDQ+ 0.3 V

_REFis driven after or with V_DDQsuch that V_REF< V_DDQ+ 0.3 V

The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read

access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM

requires a 200 µs delay prior to applying an executable command.

Once the 200 µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be

brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode

Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode

Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating

parameters. 200 clock cycles are required between the DLL reset and any executable command. During the

200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a

Precharge ALL command should be applied, placing the device in the “all banks idle” state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set

command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without

resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

Data Sheet

22

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.2

Mode Register Definition

The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes

the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is

programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information

until it is programmed again or the device loses power (except for bit A8, which is self-clearing).

Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-

A6 specify the CAS latency, and A7-A12 specify the operating mode.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before

initiating the subsequent operation. Violating either of these requirements results in unspecified operation.

MR

Mode Register Definition

(BA[1:0] = 00_B)

A8 A7 A6

BA1

BA0

A12

A11

A10

A9

A5

A4

A3

A2

A1

A0

0

OPERATING MODE

CL

BT

BL

reg. addr

w

Field

BL

Bits

[2:0]

Type¹⁾Description

w Burst Length

Number of sequential bits per DQ related to one read/write command; see

Chapter 3.2.1.

Note: All other bit combinations are RESERVED.

001 2

010 4

011 8

BT

CL

3

Burst Type

See Table 7 for internal address sequence of low order address bits; see

Chapter 3.2.2.

0

1

Sequential

Interleaved

[6:4]

CAS Latency

Number of full clocks from read command to first data valid window; see Chapter 3.2.3.

Note: All other bit combinations are RESERVED.

010 2

011 3

101 1.5

Note:DDR200 components only

110 2.5

MODE [12:7]

Operating Mode

See Chapter 3.2.4.

Note: All other bit combinations are RESERVED.

000000 Normal Operation without DLL Reset

000010 Normal Operation with DLL Reset

1) w = write only register bit

Data Sheet

23

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.2.1

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The

burst length determines the maximum number of column locations that can be accessed for a given Read or Write

command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is

reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst

length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column

address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the

starting location within the block. The programmed burst length applies to both Read and Write bursts.

3.2.2

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the

burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the

burst type and the starting column address, as shown in Table 7.

Table 7

Burst Definition

Burst

Starting Column Address

Order of Accesses Within a Burst

Length

A2

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Type = Sequential

Type = Interleaved

0-1

2

4

0-1

1-0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

1-0

0-1-2-3

1-0-3-2

2-3-0-1

0

1

0

1

0

1

3-2-1-0

8

0

1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

Notes

1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.

2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the

block.

3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within

the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps

within the block.

Data Sheet

24

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.2.3

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and

the availability of the first burst of output data. The latency can be programmed 2, 2.5 and 3 clocks. CAS latency

of 1.5 is supported for DDR200 components only.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally

coincident with clock edge n + m (see Figure 6).

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

3.2.4

Operating Mode

The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero,

and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with

bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register

Set command issued to reset the DLL should always be followed by a Mode Register Set command to select

normal operating mode.

All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and

reserved states should not be used as unknown operation or incompatibility with future versions may result.

CAS Latency = 2, BL = 4

CK

Read

NOP

Command

CL=2

DQS

DQ

CAS Latency = 2.5, BL = 4

CK

Read

NOP

Command

CL=2.5

DQS

DQ

Shown with nominal t_AC, t_DQSCK, and t_DQSQ

.

Don’t Care

Figure 6

Required CAS Latencies

Data Sheet

25

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.3

Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional

functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled

via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the

Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed

again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the

controller must wait the specified time before initiating any subsequent operation. Violating either of these

requirements result in unspecified operation.

EMR

Extended Mode Register Definition

(BA[1:0] = 01_B)

A8 A7 A6

BA1

BA0

A12

A11

A10

A9

A5

A4

A3

A2

A1

A0

0

1

Operating Mode

DS

DLL

reg. addr

w

Field

DLL

Bits

0

Type¹⁾

w

Description

DLL Status

See Chapter 3.3.1.

0

1

Enabled

Disabled

DS

1

Drive Strength

See Chapter 3.3.2, Chapter 4.2 and Chapter 4.3.

0

1

Normal

Weak

MODE

[12:2]

Operating Mode

Note:All other bit combinations are RESERVED.

00000000000Normal Operation

1) w = write only register bit

3.3.1

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon

returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is

automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self

refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command can be

issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon exit of self

refresh operation.

3.3.2

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version

supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during

mode register set. I-V curves for the normal and weak drive strength are included in this document.

Data Sheet

26

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.4

Commands

Deselect

The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is

effectively deselected. Operations already in progress are not affected.

No Operation (NOP)

The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted

commands from being registered during idle or wait states. Operations already in progress are not affected.

Mode Register Set

The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in Chapter 3.2.

The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A

subsequent executable command cannot be issued until t_MRDis met.

Active

The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value

on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row

remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that

bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before

opening a different row in the same bank.

Read

The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1

inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don’t care] for x16, [i = 9,

j = don’t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on input A10

determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is

precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent

accesses.

Write

The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1

inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where

[i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto

Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write

burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on

the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a

given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high,

the corresponding data inputs are ignored, and a Write is not executed to that byte/column location.

Precharge

The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all

banks. The bank(s) will be available for a subsequent row access a specified time (t_RP) after the Precharge

command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where

only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t

Care”. Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write

commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that

bank, or if the previously open row is already in the process of precharging.

Data Sheet

27

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Auto Precharge

Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but

without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction

with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write

command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent

in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that

the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to

the same bank until the precharge (t_RP) is completed. This is determined as if an explicit Precharge command was

issued at the earliest possible time, as described for each burst type in Chapter 3.5.

Burst Terminate

The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most recently

registered Read command prior to the Burst Terminate command is truncated, as shown in Chapter 3.5.

Auto Refresh

Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR)

Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is

required.

The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care”

during an Auto Refresh command. The 256 Mbit Double-Data-Rate SDRAM requires Auto Refresh cycles at an

average periodic interval of 7.8 µs (maximum).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh

interval is provided. A maximum of eight Auto Refresh commands can be posted in the system, meaning that the

maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is

9 × 7.8 µs (70.2 µs). This maximum absolute interval is short enough to allow for DLL updates internal to the

DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in t_ACbetween updates.

Self Refresh

The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self

Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is

automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh

(200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are

“Don’t Care” during Self Refresh operation.Since CKE is an SSTL_2 input , V_REFmust be maintained during SELF

REFRESH.

The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE

returning high. Once CKE is high, the SDRAM must have NOP commands issued for t_XSNRbecause time is

required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and

DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.

Data Sheet

28

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Table 8

Truth Table 1a: Commands

Name (Function)

Deselect (NOP)

No Operation (NOP)

Active (Select Bank And Activate Row)

Read (Select Bank And Column, And Start Read Burst)

Write (Select Bank And Column, And Start Write Burst)

Burst Terminate

Precharge (Deactivate Row In Bank Or Banks)

Auto Refresh Or Self Refresh (Enter Self Refresh Mode)

Mode Register Set

CS RAS CAS WE Address MNE

Notes

1)2)

H

L

X

H

L

H

L

X

H

L

X

H

L

H

L

X

NOP

1)2)

1)3)

1)4)

1)5)

1)6)

1)7)8)

1)9)

Bank/Row ACT

Bank/Col Read

Bank/Col Write

X

Code

X

L

H

L

BST

PRE

AR/SR

L

Op-Code MRS

1) CKE is HIGH for all commands shown except Self Refresh.

V

_REFmust be maintained during Self Refresh operation

2) Deselect and NOP are functionally interchangeable.

3) BA0-BA1 provide bank address and A0-A12 provide row address.

4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4);

A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.

5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read

bursts with Auto Precharge enabled or for write bursts.

6) A10 LOW: BA0, BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.

7) This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW.

8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.

9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1,

BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to

be written to the selected Mode Register).

Table 9

Truth Table 1b: DM Operation

Name (Function)

Write Enable

Write Inhibit

DM

L

H

DQs

Valid

X

Notes

1)

1) Used to mask write data; provided coincident with the corresponding data.

Data Sheet

29

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.5

Operations

3.5.1

Bank/Row Activation

Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must

be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see

Figure 7), which decode and select both the bank and the row to be activated. After opening a row (issuing an

Active command), a Read or Write command may be issued to that row, subject to the t_RCDspecification. A

subsequent Active command to a different row in the same bank can only be issued after the previous active row

has been “closed” (precharged). The minimum time interval between successive Active commands to the same

bank is defined by t_RC. A subsequent Active command to another bank can be issued while the first bank is being

accessed, which results in a reduction of total row-access overhead. The minimum time interval between

successive Active commands to different banks is defined by t_RRD

.

CK

HIGH

CKE

CS

RAS

CAS

WE

RA = row address.

BA = bank address.

RA

BA

A0-A12

BA0, BA1

Don’t Care

Figure 7

Activating a Specific Row in a Specific Bank

CK

RD/WR

ACT

NOP

ACT

NOP

Command

A0-A12

ROW

BA x

ROW

BA y

COL

BA y

BA0, BA1

t_RRD

t_RCD

Don’t Care

Figure 8

t

_RCDand t_RRDDefinition

Data Sheet

30

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.5.2

Reads

Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are

initiated with a Read command, as shown on Figure 9.

The starting column and bank addresses are provided with the Read command and Auto Precharge is either

enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge

at the completion of the burst, provided t_RAShas been satisfied. For the generic Read commands used in the

following illustrations, Auto Precharge is disabled.

Data Sheet

31

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

During Read bursts, the valid data-out element from the starting column address is available following the CAS

latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or

negative clock edge (i.e. at the next crossing of CK and CK). Figure 10 shows general timing for each supported

CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is

known as the read preamble; the low state coincident with the last data-out element is known as the read

postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs goes High-Z.

Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command.

In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either

the last element of a completed burst or the last desired data element of a longer burst which is being truncated.

The new Read command should be issued x cycles after the first Read command, where x equals the number of

desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Figure 11. A

Read command can be initiated on any clock cycle following a previous Read command. Nonconsecutive Read

data is illustrated on Figure 12. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)

within a page (or pages) can be performed as shown on Figure 13.Data from any Read burst may be truncated

with a Burst Terminate command, as shown on Figure 14. The Burst Terminate latency is equal to the read (CAS)

latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where x equals

the number of desired data element pairs.

Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If

truncation is necessary, the Burst Terminate command must be used, as shown on Figure 15. The example is

shown for t_DQSS(min). The t_DQSS(max)case, not shown here, has a longer bus idle time. t_DQSS(min)and t_DQSS(max)are

defined in Chapter 3.5.3.

A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto

Precharge was not activated). The Precharge command should be issued x cycles after the Read command,

where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This

is shown on Figure 16 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent

command to the same bank cannot be issued until t_RPis met. Note that part of the row precharge time is hidden

during the access of the last data elements.

In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as

described above) provides the same operation that would result from the same Read burst with Auto Precharge

enabled. The disadvantage of the Precharge command is that it requires that the command and address busses

be available at the appropriate time to issue the command. The advantage of the Precharge command is that it

can be used to truncate bursts.

Data Sheet

32

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

CK

HIGH

CKE

CS

RAS

CAS

WE

x4: A0-A9, A11

x8: A0-A9

CA

x16: A0-A8

EN AP

A10

DIS AP

BA

CA = column address

BA = bank address

BA0, BA1

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharge

Don’t Care

Figure 9

Read Command

Data Sheet

33

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

CAS Latency = 2

CK

Read

NOP

Command

Address

BA a,COL n

CL=2

DQS

DQ

DOa-n

CAS Latency = 2.5

CK

Read

NOP

Command

Address

BA a,COL n

CL=2.5

DQS

DQ

DOa-n

Don’t Care

DO a-n = data out from bank a, column n.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal t_AC, t_DQSCK, and t_DQSQ

.

Figure 10 Read Burst: CAS Latencies (Burst Length = 4)

Data Sheet

34

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

CAS Latency = 2

CK

Read

NOP

Read

NOP

Command

Address

BAa, COL n

BAa, COL b

CL=2

DQS

DQ

DOa-b

DOa-n

CAS Latency = 2.5

CK

Read

NOP

Read

NOP

Command

Address

BAa, COL n

BAa,COL b

CL=2.5

DQS

DQ

DOa- n

DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

When burst length = 4, the bursts are concatenated.

Don’t Care

When burst length = 8, the second burst interrupts the first.

3 subsequent elements of data out appear in the programmed order following DO a-n.

3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.

Shown with nominal t_AC, t_DQSCK, and t_DQSQ

.

Figure 11 Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)

Data Sheet

35

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

CAS Latency = 2

CK

Read

NOP

Read

NOP

Command

Address

BAa, COL n

BAa, COL b

CL=2

DQS

DQ

DO a-n

DOa- b

CAS Latency = 2.5

CK

Read

NOP

Read

BAa, COL b

NOP

Command

Address

BAa, COL n

CL=2.5

DQS

DQ

DO a-n

DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).

Shown with nominal t_AC, t_DQSCK, and t_DQSQ

.

Don’t Care

Figure 12 Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)

Data Sheet

36

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

CAS Latency = 2

CK

Read

BAa, COL x

CL=2

Read

NOP

Command

Address

BAa, COL n

BAa, COL b

BAa, COL g

DQS

DQ

DOa-n

DOa-n’

DOa-x

DOa-x’

DOa-b

DOa-b’

DOa-g

CAS Latency = 2.5

CK

Read

NOP

Command

Address

BAa, COL n

BAa, COL x

BAa, COL b

BAa, COL g

CL=2.5

DQS

DQ

DOa-n

DOa-n’

DOa-x

DOa-x’

DOa-b

DOa-b’

DO a-n, etc. = data out from bank a, column n etc.

Don’t Care

n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).

Reads are to active rows in any banks.

Shown with nominal t_AC, t_DQSCK, and t_DQSQ

.

Figure 13 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)

Data Sheet

37

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

CAS Latency = 2

CK

Read

NOP

BST

NOP

Command

Address

BAa, COL n

CL=2

DQS

DQ

DOa-n

No further output data after this point.

DQS tristated.

CAS Latency = 2.5

CK

Read

NOP

BST

NOP

Command

Address

BAa, COL n

CL=2.5

DQS

DQ

DOa-n

No further output data after this point.

DQS tristated.

DO a-n = data out from bank a, column n.

Cases shown are bursts of 8 terminated after 4 data elements.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal t_AC, t_DQSCK, and t_DQSQ

Don’t Care

.

Figure 14 Terminating a Read Burst: CAS Latencies (Burst Length = 8)

Data Sheet

38

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

CAS Latency = 2

CK

Read

BST

NOP

Write

NOP

Command

Address

BAa, COL n

BAa, COL b

CL=2

t_DQSS(min)

DQS

DQ

DI a-b

DOa-n

DM

CAS Latency = 2.5

CK

Read

BST

NOP

Write

NOP

Command

Address

BAa, COL n

BAa, COL b

CL=2.5

t_DQSS(min)

DQS

DQ

DOa-n

Dla-b

DM

DO a-n = data out from bank a, column n

.

DI a-b = data in to bank a, column b

1 subsequent elements of data out appear in the programmed order following DO a-n.

Data In elements are applied following Dl a-b in the programmed order, according to burst length.

Shown with nominal t_AC, t_DQSCK, and t_DQSQ

.

Don’t Care

Figure 15 Read to Write: CAS Latencies (Burst Length = 4 or 8)

Data Sheet

39

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

CAS Latency = 2

CK

Read

NOP

PRE

NOP

ACT

Command

t_RP

BA a or all

BA a, COL n

BA a, ROW

Address

CL=2

DQS

DQ

DOa-n

CAS Latency = 2.5

CK

Read

NOP

PRE

NOP

ACT

Command

t_RP

BA a or all

BA a, COL n

BA a, ROW

Address

CL=2.5

DQS

DQ

DOa-n

DO a-n = data out from bank a, column n.

Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal t_AC, t_DQSCK, and t_DQSQ

.

Don’t Care

Figure 16 Read to Precharge: CAS Latencies (Burst Length = 4 or 8)

Data Sheet

40

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.5.3

Writes

Write bursts are initiated with a Write command, as shown in Figure 17.

The starting column and bank addresses are provided with the Write command, and Auto Precharge is either

enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the

completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is

disabled.

During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write

command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS

between the Write command and the first rising edge is known as the write preamble; the Low state on DQS

following the last data-in element is known as the write postamble. The time between the Write command and the

first corresponding rising edge of DQS (t_DQSS) is specified with a relatively wide range (from 75% to 125% of one

clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. t_DQSS(min)and

t

_DQSS(max)). Figure 18 shows the two extremes of t_DQSSfor a burst of four. Upon completion of a burst, assuming

no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored.

Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case,

a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge

of clock following the previous Write command. The first data element from the new burst is applied after either

the last element of a completed burst or the last desired data element of a longer burst which is being truncated.

The new Write command should be issued x cycles after the first Write command, where x equals the number of

desired data element pairs (pairs are required by the 2n prefetch architecture). Figure 19 shows concatenated

bursts of 4. An example of non-consecutive Writes is shown in Figure 20. Full-speed random write accesses

within a page or pages can be performed as shown in Figure 21. Data for any Write burst may be followed by a

subsequent Read command. To follow a Write without truncating the write burst, t_WTR(Write to Read) should be

met as shown in Figure 22.

Data for any Write burst may be truncated by a subsequent Read command, as shown in Figure 23 to Figure 25.

Note that only the data-in pairs that are registered prior to the t_WTRperiod are written to the internal array, and any

subsequent data-in must be masked with DM, as shown in the diagrams noted previously.

Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without

truncating the write burst, t_WRshould be met as shown in Figure 26.

Data for any Write burst may be truncated by a subsequent Precharge command, as shown in Figure 27 to

Figure 29. Note that only the data-in pairs that are registered prior to the t_WRperiod are written to the internal array,

and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent

command to the same bank cannot be issued until t_RPis met.

In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as

described above) provides the same operation that would result from the same burst with Auto Precharge. The

disadvantage of the Precharge command is that it requires that the command and address busses be available at

the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to

truncate bursts.

Data Sheet

41

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

CK

HIGH

CKE

CS

RAS

CAS

WE

x4: A0-A9, A11

x8: A0-A9

CA

x16: A0-A8

EN AP

A10

DIS AP

BA

CA = column address

BA = bank address

BA0, BA1

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharge

Don’t Care

Figure 17 Write Command

Data Sheet

42

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Maximum DQSS

T1

T2

T3

T4

CK

Write

NOP

Command

Address

BA a, COL b

t_DQSS(max)

DQS

DQ

Dla-b

DM

Minimum DQSS

T4

T1

T2

T3

CK

Write

NOP

Command

Address

BA a, COL b

t_DQSS(min)

DQS

DQ

Dla-b

DM

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

A10 is Low with the Write command (Auto Precharge is disabled).

Don’t Care

Figure 18 Write Burst (Burst Length = 4)

Data Sheet

43

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Maximum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Write

NOP

Command

Address

BAa, COL b

BAa, COL n

t_DQSS(max)

DQS

DQ

DI a-b

DI a-n

DM

Minimum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Write

NOP

Command

Address

BA, COL b

BA, COL n

t_DQSS(min)

DQS

DQ

DI a-b

DI a-n

DM

DI a-b = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Don’t Care

Each Write command may be to any bank.

Figure 19 Write to Write (Burst Length = 4)

Data Sheet

44

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

T1

T2

T3

T4

T5

CK

Write

NOP

Write

NOP

Command

Address

BAa, COL b

BAa, COL n

t_DQSS(max)

DQS

DQ

DI a-b

DI a-n

DM

DI a-b, etc. = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Don’t Care

Each Write command may be to any bank.

Figure 20 Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4)

Data Sheet

45

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Maximum DQSS

T1

T2

T3

T4

T5

CK

Write

BAa, COL x

Write

BAa, COL n

Write

BAa, COL a

Write

BAa, COL g

Command

Address

BAa, COL b

t_DQSS(max)

DQS

DQ

DI a-b

DI a-b’

DI a-x

DI a-x’

DI a-n

DI a-n’

DI a-a

DI a-a’

DM

Minimum DQSS

T5

T1

T2

T3

T4

CK

Write

BAa, COL x

Write

BAa, COL n

Write

BAa, COL a

Write

Command

Address

BAa, COL b

BAa, COL g

t_DQSS(min)

DQS

DQ

DI a-g

DI a-b

DI a-b’

DI a-x

DI a-x’

DI a-n

DI a-n’

DI a-a

DI a-a’

DM

DI a-b, etc. = data in for bank a, column b, etc.

b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).

Each Write command may be to any bank.

Don’t Care

Figure 21 Random Write Cycles (Burst Length = 2, 4 or 8)

Data Sheet

46

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Maximum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t_WTR

BAa, COL b

BAa, COL n

Address

CL = 2

t_DQSS(max)

DQS

DQ

DI a-b

DM

Minimum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t_WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t_DQSS(min)

DQS

DQ

DI a-b

DM

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

t

_WTRis referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).

Don’t Care

The Read and Write commands may be to any bank.

Figure 22 Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)

Data Sheet

47

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Maximum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t_WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t_DQSS(max)

DQS

DQ

DIa- b

1

DM

Minimum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t_WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t_DQSS(min)

DQS

DQ

DI a-b

1

DM

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

t_WTRis referenced from the first positive CK edge after the last data in pair.

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

1 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

Figure 23 Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)

Data Sheet

48

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t_WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t_DQSS(min)

DQS

DQ

DI a-b

1

2

DM

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 3 data elements are written.

2 subsequent elements of data in are applied in the programmed order following DI a-b.

t_WTRis referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

1 = This bit is correctly written into the memory array if DM is low.

Don’t Care

2 = These bits are incorrectly written into the memory array if DM is low.

Figure 24 Write to Read: Min. DQSS, Odd Number of Data (3-bit Write), Interrupting (CL2; BL8)

Data Sheet

49

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

T1

T2

T3

T4

T5

T6

CK

Write

NOP

Read

NOP

Command

t_WTR

BAa, COL n

BAa, COL b

Address

CL = 2

t_DQSS(nom)

DQS

DQ

DI a-b

DM

1

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

t_WTRis referenced from the first positive CK edge after the last desired data in pair.

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

1 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

Figure 25 Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)

Data Sheet

50

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Maximum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

PRE

Command

t_WR

BA (a or all)

BA a, COL b

Address

t_RP

t_DQSS(max)

DQS

DQ

DI a-b

DM

Minimum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

t_WR

PRE

Command

BA (a or all)

BA a, COL b

Address

t_RP

t_DQSS(min)

DQS

DQ

DI a-b

DM

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

t_WRis referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).

Don’t Care

Figure 26 Write to Precharge: Non-Interrupting (Burst Length = 4)

Data Sheet

51

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Maximum DQSS

T1

T2

T3

T4

T5

T6

CK

Write

NOP

PRE

NOP

Command

t_WR

BA (a or all)

BA a, COL b

Address

t_RP

t_DQSS(max)

2

DQS

DQ

DI a-b

1

3

DM

Minimum DQSS

T5 T6

T1

T2

T3

T4

CK

Write

NOP

t_WR

PRE

NOP

Command

BA a, COL b

BA (a or all)

Address

t_RP

t_DQSS(min)

2

DQS

DQ

DI a-b

3

1

DM

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

t_WRis referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst, for burst length = 8.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

3 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

Figure 27 Write to Precharge: Interrupting (Burst Length = 4 or 8)

Data Sheet

52

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

T1

T2

T3

T4

T5

T6

CK

Write

NOP

PRE

NOP

Command

t_WR

BA a, COL b

BA (a or all)

Address

t_RP

t_DQSS(min)

2

DQS

DQ

DI a-b

1

3

4

DM

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 1 data element is written.

t_WRis referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

3 = This bit is correctly written into the memory array if DM is low.

4 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

Figure 28 Write to Precharge: Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (BL 4 or 8)

Data Sheet

53

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

T1

T2

T3

T4

T5

T6

CK

Write

NOP

PRE

NOP

Command

t_WR

BA a, COL b

BA (a or all)

Address

t_RP

t_DQSS(nom)

2

DQS

DQ

DI a-b

3

1

DM

DI a-b = Data In for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

_WRis referenced from the first positive CK edge after the last desired data in pair.

t

The Precharge command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

3 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

Figure 29 Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8)

Data Sheet

54

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.5.4

Precharge

The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The

bank(s) will be available for a subsequent row access some specified time (t_RP) after the Precharge command is

issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank

is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are

treated as “Don’t Care”. Once a bank has been precharged, it is in the idle state and must be activated prior to any

Read or Write commands being issued to that bank.

CK

HIGH

CKE

CS

RAS

CAS

WE

A0-A9, A11, A12

All Banks

A10

One Bank

BA

BA0, BA1

BA = bank address

(if A10 is Low, otherwise Don’t Care).

Don’t Care

Figure 30 Precharge Command

Data Sheet

55

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.5.5

Power-Down

Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs

when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a

row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input

and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum

power savings, the user has the option of disabling the DLL prior to entering Power-down. In that case, the DLL

must be enabled after exiting power-down, and 200 clock cycles must occur before a Read command can be

issued. In power-down mode, CKE Low and a stable clock signal must be maintained at the inputs of the

DDR SDRAM, and all other input signals are “Don’t Care”. However, power-down duration is limited by the refresh

requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled

power-down mode.

The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect

command). A valid, executable command may be applied one clock cycle later.

CK

t_IS

CKE

Command

VALID

NOP

VALID

NOP

No column

access in

progress

Exit

power down

mode

Don’t Care

Enter Power Down mode

(Burst Read or Write operation

must not be in progress)

Figure 31 Power Down

Data Sheet

56

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Table 10

Truth Table 2: Clock Enable (CKE)

Current State CKE n-1

CKEn

Command n

Action n

Notes

Previous Current

Cycle

L

H

Cycle

L

H

L

H

L

H

1)

2)

Self Refresh

Power Down

All Banks Idle

X

Maintain Self-Refresh

Exit Self-Refresh

Maintain Power-Down

Exit Power-Down

Deselect or NOP

X

–

Deselect or NOP

AUTO REFRESH

Deselect or NOP

See Table 11

Precharge Power-Down Entry –

Self Refresh Entry

Active Power-Down Entry

–

Bank(s) Active H

H

1) V_REFmust be maintained during Self Refresh operation

2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t_XSNR) period. A

minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

Note:

1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.

4. All states and sequences not shown are illegal or reserved.

Table 11

Truth Table 3: Current State Bank n - Command to Bank n (same bank)

Current State CS RAS CAS WE Command

Action

Notes

1)2)3)4)5)6)

Any

Idle

H

L

X

H

L

X

H

L

X

H

L

Deselect

No Operation

Active

NOP. Continue previous operation.

Select and activate row

–

1) to 6)

1) to 7)

AUTO REFRESH

L

MODE

REGISTER SET

1) to 6), 8)

1) to 6), 9)

1) to 6), 8)

Row Active

L

H

L

H

L

H

L

Read

Write

Precharge

Read

Select column and start Read burst

Select column and start Write burst

Deactivate row in bank(s)

Read (Auto

Precharge

Disabled)

H

Select column and start new Read

burst

1) to 6), 9)

L

H

L

Precharge

Truncate Read burst, start

Precharge

BURST TERMINATE

1) to 6), 10)

H

BURST

TERMINATE

1) to 6), 8), 11)

1) to 6), 8)

Write (Auto

Precharge

Disabled)

L

H

L

H

L

Read

Write

Precharge

Select column and start Read burst

Select column and start Write burst

Truncate Write burst, start Precharge

1) to 6), 9), 11)

1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 10 and after t_XSNR/t_XSRDhas been met (if the

previous state was self refresh).

2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are

those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

Data Sheet

57

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3) Current state definitions:

Idle: The bank has been precharged, and t_RPhas been met.

Row Active: A row in the bank has been activated, and t_RCDhas been met. No data bursts/accesses and no register

accesses are in progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4) The following states must not be interrupted by a command issued to the same bank.

Precharging: Starts with registration of a Precharge command and ends when t_RPis met. Once t_RPis met, the bank is in

the idle state.

Row Activating: Starts with registration of an Active command and ends when t_RCDis met. Once t_RCDis met, the bank is in

the “row active” state.

Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when

t

_RPhas been met. Once t_RPis met, the bank is in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when

t

_RPhas been met. Once t_RPis met, the bank is in the idle state.

Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring

during these states. Allowable commands to the other bank are determined by its current state and according to Table 12.

5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied

on each positive clock edge during these states.

Refreshing: Starts with registration of an Auto Refresh command and ends when t_RFCis met. Once t_RFCis met, the

DDR SDRAM is in the “all banks idle” state.

Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t_MRDhas been met.

Once t_MRDis met, the DDR SDRAM is in the “all banks idle” state.

Precharging All: Starts with registration of a Precharge All command and ends when t_RPis met. Once t_RPis met, all banks

is in the idle state.

6) All states and sequences not shown are illegal or reserved.

7) Not bank-specific; requires that all banks are idle.

8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads

or Writes with Auto Precharge disabled.

9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.

10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.

11) Requires appropriate DM masking.

Data Sheet

58

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

Table 12

Truth Table 4: Current State Bank n - Command to Bank m (different bank)

Current State

Any

CS RAS CAS WE Command

Action

Notes

1)2)3)4)5)6)

H

X

H

X

H

X

H

X

Deselect

NOP. Continue previous operation.

–

1) to 6)

L

No Operation

Idle

X

Any Command

Otherwise Allowed

to Bank m

1) to 6)

1) to 7)

1) to 6)

1) to 7)

Row Activating,

Active, or

L

H

L

H

L

H

L

H

Active

Read

Write

Precharge

Active

Read

Select and activate row

Select column and start Read burst

Select column and start Write burst

–

H

L

H

Precharging

Read (Auto

Precharge

Disabled)

Select and activate row

Select column and start new Read

burst

–

1) to 6)

1) to 8)

1) to 7)

L

H

L

Precharge

Active

Read

Write (Auto

Precharge

Disabled)

H

L

Select and activate row

Select column and start Read burst

L

Write

Select column and start new Write

burst

–

1) to 6)

L

H

L

H

Precharge

Active

Read

1) to 6)

Read (With Auto L

Select and activate row

1) to 7), 9)

Precharge)

L

Select column and start new Read

burst

1) to 7), 9), 10)

1) to 6)

L

H

L

H

L

H

L

Write

Select column and start Write burst

–

Select and activate row

Select column and start Read burst

H

L

Precharge

Active

Read

1) to 6)

Write (With Auto L

1) to 7), 9)

Precharge)

L

Write

Select column and start new Write

burst

–

1) to 6)

L

H

L

Precharge

1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 10: Clock Enable (CKE) and after t_XSNR/t_XSRD

has been met (if the previous state was self refresh).

2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands

shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is

allowable). Exceptions are covered in the notes below.

3) Current state definitions:

Idle: The bank has been precharged, and t_RPhas been met.

Row Active: A row in the bank has been activated, and t_RCDhas been met. No data bursts/accesses and no register

accesses are in progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enabled: See ¹⁰⁾

.

Write with Auto Precharge Enabled: See ¹⁰⁾

4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.

5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state

only.

6) All states and sequences not shown are illegal or reserved.

Data Sheet

59

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads

or Writes with Auto Precharge disabled.

8) Requires appropriate DM masking.

9) Concurrent Auto Precharge:

This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is

enabled any command may follow to the other banks as long as that command does not interrupt the read or write data

transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The

minimum delay from a read or write command with auto precharge enable, to a command to a different banks is

summarized in Table 13.

10) A Write command may be applied after the completion of data output.

Table 13

Truth Table 5: Concurrent Auto Precharge

From Command

To Command (different bank)

Minimum Delay with Concurrent

Auto Precharge Support

Unit

WRITE w/AP

Read or Read w/AP

Write to Write w/AP

Precharge or Activate

Read or Read w/AP

Write or Write w/AP

Precharge or Activate

1 + (BL/2) + t_WTR

BL/2

1

BL/2

CL (rounded up) + BL/2

1

t_CK

Read w/AP

3.5.6

Input Clock Frequency Change

DDR SDRAM Input clock frequency cannot be changed during normal operation. Clock frequency change is only

permitted during Self Refresh or during Power Down. In the latter case the following conditions must be met:

DDR SDRAM must be in pre charged mode with CKE at logic Low level. After a minimum of 2 clocks after CKE

goes LOW, the clock frequency may change to any frequency between minimum and maximum operating

frequeny specified for the particular speed grade. During an input clock frequency change, CKE must be held

LOW. Once the input clock frequency is changed, a stable clock must be provided to DRAM before pre charge

power down mode may be exited. The DLL must be RESET via EMRS after pre charge power down exit. An

additional MRS command may need to be issued to appropriately set CL etc.. After the DLL relock time, the DRAM

is ready to operate with the new clock frequency.

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ꢃ353'6'ꢠꢐꢠ72%789

:;<63:;4ꢠꢡ;=%:

7>15?35?ꢠ=:;<6;5%*

Figure 32 Clock frequency change in pre charge power down mode

Data Sheet

60

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Functional Description

3.6

Simplified State Diagram

Power

Applied

Power

On

Self

Precharge

PREALL

Refresh

REFS

REFSX

MRS

EMRS

Auto

Refresh

MRS

REFA

Idle

CKEL

CKEH

Active

Power

Down

ACT

Precharge

Power

Down

CKEH

CKEL

Write

Burst Stop

Read

Row

Active

Read

Write A

Read A

Write

Read

Read A

Write A

Read

A

PRE

Write

Read

A

PRE

Precharge

PREALL

PRE

Automatic Sequence

Command Sequence

PREALL = Precharge All Banks

MRS = Mode Register Set

EMRS = Extended Mode Register Set

REFS = Enter Self Refresh

REFSX = Exit Self Refresh

REFA = Auto Refresh

CKEL = Enter Power Down

CKEH = Exit Power Down

ACT = Active

Write A = Write with Autoprecharge

Read A = Read with Autoprecharge

PRE = Precharge

Figure 33 Simplified State Diagram

Data Sheet

61

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

4

Electrical Characteristics

4.1

Operating Conditions

Table 14

Absolute Maximum Ratings

Parameter

Symbol

Values

Unit Note/ Test Condition

min. typ. max.

Voltage on I/O pins relative to V_SS

Voltage on inputs relative to V_SS

Voltage on V_DDsupply relative to V_SS

Voltage on V_DDQsupply relative to V_SS

Operating temperature (ambient)

Storage temperature (plastic)

V_IN, V_OUT–0.5 –

V_DDQ+0.5 V

–

V_IN

–1

0

–

+3.6

+70

+150

–

V

°C

W

mA

V_DD

V_DDQ

T_A

T_STG

P_D

I_OUT

-55

–

1.5

50

Power dissipation (per SDRAM component)

Short circuit output current

–

Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This

is a stress rating only, and functional operation should be restricted to recommended operation

conditions. Exposure to absolute maximum rating conditions for extended periods of time may

affect device reliability and exceeding only one of the values may cause irreversible damage to

the integrated circuit.

Table 15

Parameter

Input and Output Capacitances

Symbol

Values

Typ.

—

Unit

Note/

Test Condition

Min.

1.5

2.0

—

1.5

2.0

—

Max.

2.5

3.0

0.25

2.5

3.0

1)

Input Capacitance: CK, CK

C_I1

pF

P-TFBGA-60-12

1)

P-TSOPII-66

1)

Delta Input Capacitance

C_dI1

C_I2

Input Capacitance:

P-TFBGA-60-12

1)

All other input-only pins

P-TSOPII-66

1)

Delta Input Capacitance:

All other input-only pins

C_dIO

0.5

Input/Output Capacitance: DQ, DQS, DM C_IO

3.5

—

4.5

pF

P-T₁F₎₂B₎GA-60-12

1)2)

4.0

—

5.0

0.5

pF

P-TSOPII-66

1)

Delta Input/Output Capacitance:

DQ, DQS, DM

C_dIO

1) These values are not subject to production test - verified by design/characterization and are tested on a sample base only.

VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 ×C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins

are tied to ground.

2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace

matching at the board level.

Data Sheet

62

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

Table 16

Parameter

Electrical Characteristics and DC Operating Conditions

1)

Symbol

Values

Typ.

2.5

2.6

2.5

2.6

Unit Note/Test Condition

Min.

2.3

2.5

2.3

2.5

0

Max.

2.7

0

Device Supply Voltage

Output Supply Voltage

V_DD

V_DDQ

V

f_CK≤ 166 MHz

f_CK> 166 MHz

f_CK≤ 166 MHz

f_CK> 166 MHz

—

2)

3)

2)3)

Supply Voltage, I/O Supply V_SS

,

Voltage

V_SSQ

V_REF

4)

5)

Input Reference Voltage

0.49 ×

V_DDQ

0.5 ×

V_DDQ

0.51 ×

V

V_DDQ

V_REF+ 0.04 V

I/O Termination Voltage

(System)

Input High (Logic1) Voltage V_IH(DC)V_REF+ 0.15

Input Low (Logic0) Voltage V_IL(DC)–0.3

V_TT

V_REF– 0.04

8)

V_DDQ+ 0.3 V

V_REF– 0.15 V

V_DDQ+ 0.3 V

Input Voltage Level,

V_IN(DC)–0.3

CK and CK Inputs

8)6)

7)

Input Differential Voltage, V_ID(DC)0.36

V_DDQ+ 0.6 V

CK and CK Inputs

VI-Matching Pull-up

Current to Pull-down

Current

VI

0.71

1.4

—

Ratio

Input Leakage Current

I_I

–2

2

µA Any input 0 V ≤ V_IN≤ V_DD;

All other pins not under test

8)9)

= 0 V

Output Leakage Current

I_OZ

I_OH

I_OL

–5

5

µA DQs are disabled;

0 V ≤ V_OUT≤ V_DDQ

Output High Current,

—

–16.2

—

mA V_OUT= 1.95 V

mA V_OUT= 0.35 V

Normal Strength Driver

Output Low

16.2

Current, Normal Strength

Driver

1) 0 °C ≤ T_A≤ 70 °C

2) DDR400 conditions apply for all clock frequencies above 166 MHz

3) Under all conditions, V_DDQmust be less than or equal to V_DD

4) Peak to peak AC noise on V_REFmay not exceed ± 2% V_{REF (DC)}. V_REFis also expected to track noise variations in V_DDQ

5) V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal

to V_REF, and must track variations in the DC level of V_REF

.

6) V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire

temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the

maximum difference between pull-up and pull-down drivers due to process variation.

8) Inputs are not recognized as valid until V_REFstabilizes.

9) Values are shown per component

Data Sheet

63

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

4.2

Normal Strength Pull-down and Pull-up Characteristics

1. The nominal pull-down V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve.

2. The full variation in driver pull-down current from minimum to maximum process, temperature, and voltage lie

within the outer bounding lines of the V-I curve.

3. The nominal pull-up V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner

bounding lines of the V-I curve.

4. The full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie

within the outer bounding lines of the V-I curve.

5. The full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7,

for device drain to source voltages from 0.1 to 1.0.

6. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain

to source voltages from 0.1 to 1.0 V.

140

Maximum

120

100

Nominal High

80

60

40

Nominal Low

Minimum

20

0

0.5

1

1.5

2

2.5

V_DDQ- V_OUT(V)

Figure 34 Normal Strength Pull-down Characteristics

0

-20

-40

-60

-80

Minimum

Nominal Low

-100

-120

-140

-160

Nominal High

Maximum

0

0.5

1

1.5

2

2.5

V_DDQ- V_OUT(V)

Figure 35 Normal Strength Pull-up Characteristics

Data Sheet

64

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

Table 17

Voltage (V)

Normal Strength Pull-down and Pull-up Currents

Pulldown Current (mA)

Pullup Current (mA)

Nominal

Min.

Max.

Nominal

High

Min.

Max.

Low

High

Low

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

6.0

6.8

4.6

9.2

9.6

18.2

26.0

33.9

41.8

49.4

56.8

63.2

69.9

76.3

82.5

88.3

93.8

99.1

103.8

108.4

112.1

115.9

119.6

123.3

126.5

129.5

132.4

135.0

137.3

139.2

140.8

-6.1

-7.6

-14.5

-21.2

-27.7

-34.1

-40.5

-46.9

-53.1

-59.4

-65.5

-71.6

-77.6

-83.6

-89.7

-95.5

-101.3

-107.1

-112.4

-118.7

-124.0

-129.3

-134.6

-139.9

-145.2

-150.5

-155.3

-160.1

-4.6

-9.2

-10.0

-20.0

-29.8

-38.8

-46.8

-54.4

-61.8

-69.5

12.2

18.1

24.1

29.8

34.6

39.4

43.7

47.5

51.3

54.1

56.2

57.9

59.3

60.1

60.5

61.0

61.5

62.0

62.5

62.9

63.3

63.8

64.1

64.6

64.8

65.0

13.5

20.1

26.6

33.0

39.1

44.2

49.8

55.2

60.3

65.2

69.9

74.2

78.4

82.3

85.9

89.1

92.2

95.3

97.2

99.1

100.9

101.9

102.8

103.8

104.6

105.4

-12.2

-18.1

-24.0

-29.8

-34.3

-38.1

-41.1

-43.8

-46.0

-47.8

-49.2

-50.0

-50.5

-50.7

-51.0

-51.1

-51.3

-51.5

-51.6

-51.8

-52.0

-52.2

-52.3

-52.5

-52.7

-52.8

13.8

18.4

23.0

27.7

32.2

36.8

39.6

42.6

44.8

46.2

47.1

47.4

47.7

48.0

48.4

48.9

49.1

49.4

49.6

49.8

49.9

50.0

50.2

50.4

50.5

-13.8

-18.4

-23.0

-27.7

-32.2

-36.0

-38.2

-38.7

-39.0

-39.2

-39.4

-39.6

-39.9

-40.1

-40.2

-40.3

-40.4

-40.5

-40.6

-40.7

-40.8

-40.9

-41.0

-41.1

-41.2

-77.3

-85.2

-93.0

-100.6

-108.1

-115.5

-123.0

-130.4

-136.7

-144.2

-150.5

-156.9

-163.2

-169.6

-176.0

-181.3

-187.6

-192.9

-198.2

Table 18

Parameter

Evaluation Conditions for I/O Driver Characteristics

Nominal

Minimum

Maximum

Operating Temperature

V_DD/V_DDQ

Process Corner

25 °C

2.5 V

typical

0 °C

2.3 V

slow-slow

70 °C

2.7 V

fast-fast

Data Sheet

65

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

4.3

Weak Strength Pull-down and Pull-up Characteristics

1. The weak pull-down V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner

bounding lines of the V-I curve.

2. The weak pull-up V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner

bounding lines of the V-I curve.

3. The full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie

within the outer bounding lines of the V-I curve.

4. The full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7,

for device drain to source voltages from 0.1 to 1.0.

5. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain

to source voltages from 0.1 to 1.0 V.

80

Maximu

70

60

50

40

30

20

10

0

Tpicalhi

Tpicallo

Minimu

0,0

0,5

1,0

1,5

2,0

2,5

out

Figure 36 Weak Strength Pull-down Characteristics

0,0

0,5

1,0

1,5

2,0

2,5

-10,0

Minimu

-20,0

-30,0

-40,0

-50,0

-60,0

-70,0

-80,0

Typicallo

Typicalhig

Maximu

out[

Figure 37 Weak Strength Pull-up Characteristics

Data Sheet

66

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

Table 19

Voltage (V)

Weak Strength Driver Pull-down and Pull-up Characteristics

Pulldown Current (mA) Pullup Current (mA)

Nominal

Min.

Max.

Nominal

Min.

Max.

Low

High

Low

High

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

3.4

6.9

3.8

7.6

2.6

5.2

7.8

5.0

9.9

-3.5

-6.9

-4.3

-8.2

-2.6

-5.2

-7.8

-5.0

-9.9

10.3

13.6

16.9

19.6

22.3

24.7

26.9

29.0

30.6

31.8

32.8

33.5

34.0

34.3

34.5

34.8

35.1

35.4

35.6

35.8

36.1

36.3

36.5

36.7

36.8

11.4

15.1

18.7

22.1

25.0

28.2

31.3

34.1

36.9

39.5

42.0

44.4

46.6

48.6

50.5

52.2

53.9

55.0

56.1

57.1

57.7

58.2

58.7

59.2

59.6

14.6

19.2

23.6

28.0

32.2

35.8

39.5

43.2

46.7

50.0

53.1

56.1

58.7

61.4

63.5

65.6

67.7

69.8

71.6

73.3

74.9

76.4

77.7

78.8

79.7

-10.3

-13.6

-16.9

-19.4

-21.5

-23.3

-24.8

-26.0

-27.1

-27.8

-28.3

-28.6

-28.7

-28.9

-29.0

-29.2

-29.3

-29.5

-29.6

-29.7

-29.8

-29.9

-12.0

-15.7

-19.3

-22.9

-26.5

-30.1

-33.6

-37.1

-40.3

-43.1

-45.8

-48.4

-50.7

-52.9

-55.0

-56.8

-58.7

-60.0

-61.2

-62.4

-63.1

-63.8

-64.4

-65.1

-65.8

-14.6

-19.2

-23.6

-28.0

-32.2

-35.8

-39.5

-43.2

-46.7

-50.0

-53.1

-56.1

-58.7

-61.4

-63.5

-65.6

-67.7

-69.8

-71.6

-73.3

-74.9

-76.4

-77.7

-78.8

-79.7

10.4

13.0

15.7

18.2

20.8

22.4

24.1

25.4

26.2

26.6

26.8

27.0

27.2

27.4

27.7

27.8

28.0

28.1

28.2

28.3

28.4

28.5

28.6

-10.4

-13.0

-15.7

-18.2

-20.4

-21.6

-21.9

-22.1

-22.2

-22.3

-22.4

-22.6

-22.7

-22.8

-22.9

-23.0

-23.1

-23.2

-23.3

Data Sheet

67

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

4.4

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating

Conditions, I_DDSpecifications and Conditions, and Electrical Characteristics and AC Timing.)

Notes

1. All voltages referenced to V_SS

.

2. Tests for AC timing, I_DD, and electrical, AC and DC characteristics, may be conducted at nominal reference/

supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage

range specified.

3. Figure 38 represents the timing reference load used in defining the relevant timing parameters of the part. It

is not intended to be either a precise representation of the typical system environment nor a depiction of the

actual load presented by a production tester. System designers will use IBIS or other simulation tools to

correlate the timing reference load to a system environment. Manufacturers will correlate to their production

test conditions (generally a coaxial transmission line terminated at the tester electronics).

4. AC timing and I_DDtests may use a V_ILto V_IHswing of up to 1.5 V in the test environment, but input timing is

still referenced to V_REF(or to the crossing point for CK, CK), and parameter specifications are guaranteed for

the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/

ns in the range between V_IL(AC)and V_IH(AC)

.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively

switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal

does not ring back above (below) the DC input LOW (HIGH) level).

6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR

SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the

latest JEDEC specification for DDR components.

V_TT

50 Ω

Output

Timing Reference Point

(V_OUT

)

30 pF

Figure 38 AC Output Load Circuit Diagram / Timing Reference Load

Data Sheet

68

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

1)

Table 20

AC Operating Conditions

Parameter

Symbol

Values

Max.

Unit Note/

Test

Min.

Condition

2)3)

Input High (Logic 1) Voltage, DQ, DQS and DM Signals V_IH(AC)V_REF+ 0.31 —

Input Low (Logic 0) Voltage, DQ, DQS and DM Signals V_IL(AC)

Input Differential Voltage, CK and CK Inputs

Input Closing Point Voltage, CK and CK Inputs

V

2)3)

—

V_REF– 0.31 V

V_DDQ+ 0.6 V

2)3)4)

2)3)5)

V_ID(AC)0.7

V_IX(AC)0.5 × V_DDQ0.5 × V_DDQ

V

– 0.2 + 0.2

1) V_DDQ= 2.5 V ± 0.2 V, V_DD= +2.5 V ± 0.2 V (DDR200 - DDR333); V_DDQ= 2.6 V ± 0.1 V, V_DD= +2.6 V ± 0.1 V (DDR400);

0 °C ≤ T_A≤ 70 °C

2) Input slew rate = 1 V/ns.

3) Inputs are not recognized as valid until V_REFstabilizes.

4) V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

5) The value of V_IXis expected to equal 0.5 × V_DDQof the transmitting device and must track variations in the DC level of the

same.

Table 21

AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter

Symbol –5

DDR400B

–6

DDR333

Min.

Unit Note/ Test

Condition

1)

Min.

Max.

+0.5

Max.

+0.7

2)3)4)5)

DQ output access time from

CK/CK

CK high-level width

Clock cycle time

t_AC

–0.5

–0.7

ns

2)3)4)5)

t_CH

t_CK

0.45

5

0.55

8

0.45

6

0.55

12

t_CK

ns

CL = 3.0

2)3)4)5)

6

12

6

12

CL = 2.5

2)3)4)5)

7.5

0.45

12

7.5

0.45

12

CL = 2.0

2)3)4)5)

CK low-level width

t_CL

0.55

t_CK

2)3)4)5)6)

Auto precharge write recovery t_DAL

(t_WR/t_CK)+(t_RP/t_CK)

+ precharge time

2)3)4)5)

DQ and DM input hold time

t_DH

0.4

1.75

—

0.45

1.75

—

ns

2)3)4)5)6)

DQ and DM input pulse width t_DIPW

(each input)

2)3)4)5)

DQS output access time from t_DQSCK–0.6

+0.6

—

–0.6

0.35

—

+0.6

—

ns

CK/CK

DQS input low (high) pulse

t_DQSL,H0.35

t_CK

width (write cycle)

DQS-DQ skew (DQS and

associated DQ signals)

t_DQSQ

—

+0.40

1.25

—

+0.40 ns

+0.45 ns

TFBGA

2)3)4)5)

—

TSOPII

2)3)4)5)

st

2)3)4)5)

Write command to 1 DQS

t_DQSS

0.72

0.4

0.75

0.45

1.25

—

t_CK

latching transition

2)3)4)5)

DQ and DM input setup time t_DS

ns

Data Sheet

69

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

Table 21

AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter

Symbol –5

DDR400B

–6

Unit Note/ Test

Condition

1)

DDR333

Min.

0.2

Min.

Max.

—

Max.

—

2)3)4)5)

DQS falling edge hold time

from CK (write cycle)

t_DSH

0.2

t_CK

2)3)4)5)

DQS falling edge to CK setup t_DSS

0.2

—

0.2

—

t_CK

time (write cycle)

2)3)4)5)

Clock Half Period

t_HP

min. (t_CL, t_CH) —

—

min. (t_CL, t_CH) —

ns

2)3)4)5)7)

Data-out high-impedance time t_HZ

+0.7

–0.7

0.75

0.8

+0.7

from CK/CK

Address and control input hold t_IH

0.6

0.7

2.2

0.6

0.7

–0.7

2

—

ns

fast slew rate

3)4)5)6)8)

time

—

slow slew

3)4)5)6)8)

rate

2)3)4)5)9)

Control and Addr. input pulse t_IPW

—

2.2

width (each input)

Address and control input

t_IS

—

0.75

0.8

fast slew rate

3)4)5)6)8)

setup time

—

slow slew

3)4)5)6)8)

rate

2)3)4)5)7)

2)3)4)5)

Data-out low-impedance time t_LZ

+0.70

—

–0.70

2

+0.70 ns

from CK/CK

Mode register set command

t_MRD

—

t_CK

cycle time

DQ/DQS output hold time

Data hold skew factor

t_QH

t_QHS

t_HP–t_QHS

—

+0.50

t_HP–t_QHS

—

ns

+0.50 ns

TFBGA

2)3)4)5)

—

+0.50

—

+0.55 ns

TSOPII

2)3)4)5)

Active to Autoprecharge delay t_RAP

Active to Precharge command t_RAS

t_RCD

40

55

—

t_RCD

—

ns

70E+3 42

—

70E+3 ns

—

Active to Active/Auto-refresh

t_RC

60

ns

command period

2)3)4)5)

Active to Read or Write delay t_RCD

15

—

7.8

18

—

7.8

ns

µs

2)3)4)5)8)

Average Periodic Refresh

t_REFI

Interval

2)3)4)5)

Auto-refresh to Active/Auto-

refresh command period

t_RFC

70

—

72

—

ns

2)3)4)5)

Precharge command period

Read preamble

Read postamble

t_RP

t_RPRE

t_RPST

15

—

18

—

ns

0.9

0.40

10

1.1

0.60

—

0.9

0.40

12

1.1

0.60

—

t_CK

ns

Active bank A to Active bank B t_RRD

command

2)3)4)5)

Write preamble

t_WPRE

0.25

0

—

0.25

0

—

t_CK

ns

2)3)4)5)10)

Write preamble setup time

t_WPRES

Data Sheet

70

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

Table 21

AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter

Symbol –5

DDR400B

–6

Unit Note/ Test

Condition

1)

DDR333

Min.

0.40

15

Min.

0.40

15

Max.

0.60

—

Max.

0.60

—

2)3)4)5)11)

Write postamble

Write recovery time

t_WPST

t_WR

t_CK

ns

t_CK

2)3)4)5)

Internal write to read command t_WTR

2

—

1

—

delay

2)3)4)5)

Exit self-refresh to non-read

t_XSNR

t_XSRD

75

—

75

—

ns

command

2)3)4)5)

Exit self-refresh to read

command

200

t_CK

1) 0 °C ≤ T_A≤ 70 °C; V_DDQ= 2.5 V ± 0.2 V, V_DD= +2.5 V ± 0.2 V (DDR333); V_DDQ= 2.6 V ± 0.1 V, V_DD= +2.6 V ± 0.1 V

(DDR400)

2) Input slew rate ≥ 1 V/ns for DDR400, DDR333

3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference

level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.

4) Inputs are not recognized as valid until V_REFstabilizes.

5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT

.

6) For each of the terms, if not already an integer, round to the next highest integer. t_CKis equal to the actual system clock

cycle time.

7) t_HZand t_LZtransitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/

ns, measured between V_IH(ac)and V_IL(ac)

.

9) These parameters guarantee device timing, but they are not necessarily tested on each device.

10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge.

A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were

previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,

DQS could be HIGH, LOW at this time, depending on t_DQSS

.

11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but

system performance (bus turnaround) degrades accordingly.

Table 22

AC Timing - Absolute Specifications for PC2700

Parameter

Symbol –7

DDR266A

Min.

Unit Note/Test

Condition

1)

Max.

+0.75

0.55

12

2)3)4)5)

DQ output access time from CK/CK

CK high-level width

Clock cycle time

t_AC

t_CH

t_CK

–0.75

0.45

7.5

ns

t_CK

2)3)4)5)

3)4)5)

ns

t_CK

CL = 3.0

CL = 2.5

2)3)4)5)

7.5

CL = 2.0

2)3)4)5)

CK low-level width

t_CL

0.45

0.55

2)3)4)5)6)

Auto precharge write recovery + precharge t_DAL

(t_WR/t_CK)+(t_RP/t_CK) —

time

2)3)4)5)

DQ and DM input hold time

DQ and DM input pulse width (each input)

t_DH

t_DIPW

0.5

1.75

—

ns

2)3)4)5)6)

Data Sheet

71

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

Table 22 AC Timing - Absolute Specifications for PC2700 (cont’d)

Parameter

Symbol –7

DDR266A

Unit Note/Test

Condition

1)

Min.

t_DQSCK–0.75

DQS input low (high) pulse width (write cycle) t_DQSL,H0.35

Max.

+0.75

—

2)3)4)5)

DQS output access time from CK/CK

ns

t_CK

2)3)4)5)

DQS-DQ skew (DQS and associated DQ

t_DQSQ

—

+0.5

1.25

—

ns

t_CK

ns

t_CK

FBGA

2)3)4)5)

signals)

TSOPII

st

2)3)4)5)

Write command to 1 DQS latching transition t_DQSS0.75

2)3)4)5)

DQ and DM input setup time

t_DS

t_DSH

0.5

0.2

DQS falling edge hold time from CK (write

—

cycle)

2)3)4)5)

DQS falling edge to CK setup time (write

cycle)

Clock Half Period

Data-out high-impedance time from CK/CK t_HZ

Address and control input hold time

t_DSS

t_HP

0.2

—

t_CK

2)3)4)5)

min. (t_CL, t_CH

–0.75

0.9

)

—

+0.75

—

ns

2)3)4)5)7)

t_IH

fast slew rate

3)4)5)6)8)

1.0

2.2

0.9

1.0

—

ns

slow slew rate

3)4)5)6)8)

2)3)4)5)9)

Control and Addr. input pulse width (each

input)

Address and control input setup time

t_IPW

t_IS

fast slew rate

3)4)5)6)8)

slow slew rate

3)4)5)6)8)

2)3)4)5)7)

2)3)4)5)

Data-out low-impedance time from CK/CK t_LZ

–0.75

2

t_HP– t_QHS

—

t_RCD

45

+0.75

—

ns

t_CK

ns

Mode register set command cycle time

t_MRD

DQ/DQS output hold time

t_QH

2)3)4)5)

Data hold skew factor

t_QHS

0.75

—

120E+3 ns

—

FBGA

2)3)4)5)

TSOPII

2)3)4)5)

Active to Read w/AP delay

Active to Precharge command

t_RAP

t_RAS

t_RC

Active to Active/Auto-refresh command

65

ns

period

2)3)4)5)

Active to Read or Write delay

Average Periodic Refresh Interval

t_RCD

t_REFI

t_RFC

20

7.8

75

—

ns

µs

ns

2)3)4)5)10)

2)3)4)5)

Auto-refresh to Active/Auto-refresh

command period

2)3)4)5)

2)3)4)5)11)

Precharge command period

Read preamble

Read postamble

Active bank A to Active bank B command

Write preamble

Write preamble setup time

t_RP

t_RPRE0.9

t_RPST

t_RRD

t_WPRE0.25

20

—

ns

1.1

0.6

—

t_CK

ns

t_CK

ns

0.4

15

t_WPRES

0

Data Sheet

72

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

Table 22

Parameter

AC Timing - Absolute Specifications for PC2700 (cont’d)

Symbol –7

DDR266A

Unit Note/Test

Condition

1)

Min.

0.4

15

1

75

Max.

—

2)3)4)5)12)

Write postamble

Write recovery time

Internal write to read command delay

Exit self-refresh to non-read command

Exit self-refresh to read command

t_WPST

t_WR

t_WTR

t_XSNR

t_XSRD

t_CK

ns

t_CK

ns

2)3)4)5)

—

2)3)4)5)13)

2)3)4)5)

200

—

t_CK

1) V_DDQ= 2.5 V ± 0.2 V, V_DD= +2.5 V ± 0.2 V ; 0 °C ≤ T_A≤ 70 °C

2) Input slew rate ≥ 1 V/ns

3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference

level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.

4) Inputs are not recognized as valid until V_REFstabilizes.

5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT

.

6) For each of the terms, if not already an integer, round to the next highest integer. t_CKis equal to the actual system clock

cycle time.

7) t_HZand t_LZtransitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/

ns, measured between V_IH(ac)and V_IL(ac)

.

9) These parameters guarantee device timing, but they are not necessarily tested on each device.

10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.

A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were

previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,

DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS

.

12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but

system performance (bus turnaround) degrades accordingly.

13) In all circumstances, t_XSNRcan be satisfied using t_XSNR= t_RFC,min+ 1 × t_CK

Data Sheet

73

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

Table 23

I_DDConditions

Parameter

Symbol

Operating Current: one bank; active/ precharge; t_RC= t_RCMIN; t_CK= t_CKMIN

;

I_DD0

DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once

every two clock cycles.

Operating Current: one bank; active/read/precharge; Burst = 4;

I_DD1

Refer to the following page for detailed test conditions.

Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ V_ILMAX; t_CK

=

I_DD2P

I_DD2F

t_CKMIN

Precharge Floating Standby Current: CS ≥ V_IHMIN, all banks idle;

CKE ≥ V_IHMIN; t_CK= t_CKMIN, address and other control inputs changing once per clock cycle, V_IN= V_REF

for DQ, DQS and DM.

Precharge Quiet Standby Current:

I_DD2Q

CS ≥ V_IHMIN, all banks idle; CKE ≥ V_IHMIN; t_CK= t_CKMIN, address and other control inputs stable

at ≥ V_IHMINor ≤ V_ILMAX; V_IN= V_REFfor DQ, DQS and DM.

Active Power-Down Standby Current: one bank active; power-down mode;

CKE ≤ V_ILMAX; t_CK= t_CKMIN; V_IN= V_REFfor DQ, DQS and DM.

I_DD3P

I_DD3N

Active Standby Current: one bank active; CS ≥ V_IHMIN; CKE ≥ V_IHMIN; t_RC= t_RASMAX; t_CK= t_CKMIN

;

DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per

clock cycle.

Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs

changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200

and DDR266A, CL = 3 for DDR333; t_CK= t_CKMIN; I_OUT= 0 mA

I_DD4R

Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs I_DD4W

changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200

and DDR266A, CL = 3 for DDR333; t_CK= t_CKMIN

Auto-Refresh Current: t_RC= t_RFCMIN, burst refresh

Self-Refresh Current: CKE ≤ 0.2 V; external clock on; t_CK= t_CKMIN

I_DD5

I_DD6

I_DD7

Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for

detailed test conditions.

Data Sheet

74

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

Table 24

Symbol –5

I_DDSpecification

1)

–6

–7

Unit Note/Test Condition

DDR400B

Typ.

DDR333

Typ.

60

65

70

80

4

25

17

11

32

36

70

85

75

90

DDR266A

Typ.

50

55

65

70

3

20

15

9

28

30

60

70

65

75

Max.

90

100

110

5

36

28

18

45

Max.

75

85

95

5

30

24

15

38

45

85

100

90

110

160

2.8

1.1

215

Max.

65

75

85

4

24

21

13

36

40

70

85

75

90

2)3)

3)

I_DD0

I_DD1

70

75

80

95

4

30

20

13

38

43

85

100

90

100

140

1.4

mA ×4/×8

mA ×16

mA ×4/×8

3)

mA ×16

3)

I_DD2P

I_DD2F

I_DD2Q

I_DD3P

I_DD3N

mA

3)

mA

3)

54

mA ×16

3)

I_DD4R

I_DD4W

100

120

105

130

190

2.8

—

mA ×4/×8

3)

mA ×16

mA ×4/×8

3)

mA ×16

3)

I_DD5

I_DD6

120

1.4

1.0

180

100

1.4

—

140

2.8

—

170

mA

4)

mA

5)

—

210

mA low power

3)

I_DD7

250

mA ×4/×8

3)

mA ×16

1) Test conditions for typical values: V_DD= 2.5 V (DDR333), V_DD= 2.6 V (DDR400), T_A= 25 °C, test conditions for maximum

values: V_DD= 2.7 V, T_A= 10 °C

2) I_DDspecifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for

DDR333, and 200 MHz for DDR400.

3) Input slew rate = 1 V/ns.

4) Enables on-chip refresh and address counters.

5) Low power available on request

4.5

I_DDCurrent Measurement Conditions

Legend: A = Activate, R = Read, RA = Read with Autoprecharge, P = Precharge, N = NOP or DESELECT

I_DD1: Operating Current: One Bank Operation

1. General test condition

a) Only one bank is accessed with t_RC,MIN

.

b) Burst Mode, Address and Control inputs are changing once per NOP and DESELECT cycle.

c) 50% of data changing at every transfer

d) I_OUT= 0 mA.

2. Timing patterns

a) DDR266A (133 MHz, CL = 2): t_CK= 7.5 ns, BL = 4, t_RCD= 3 × t_CK, t_RC= 9 × t_CK, t_RAS= 5 × t_CK

Setup: A0 N N R0 N P0 N N N

Read: A0 N N R0 N P0 N NN - repeat the same timing with random address changing

Data Sheet

75

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Electrical Characteristics

b) DDR333B (166 MHz, CL = 2.5): t_CK= 6 ns, BL = 4, t_RCD= 3 × t_CK, t_RC= 9 × t_CK, t_RAS= 5 × t_CK

Setup: A0 N N R0 N P0 N N N

Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing

c) DDR400B (200 MHz, CL = 3): t_CK= 5 ns, BL = 4, t_RCD= 3 × t_CK, t_RC= 11 × t_CK, t_RAS= 8 × t_CK

Setup:A0 N N R0 N N N N P0 N N

Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address changing

I_DD7: Operating Current: Four Bank Operation

1. General test condition

a) Four banks are being interleaved with t_RCMIN

.

b) Burst Mode, Address and Control inputs on NOP edge are not changing.

c) 50% of data changing at every transfer

d) I_OUT= 0 mA.

2. Timing patterns

a) DDR266A (133 MHz, CL = 2): t_CK= 7.5 ns, BL = 4, t_RRD= 2 × t_CK, t_RCD= 3 × t_CK, t_RAS= 5 × t_CK

Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3

Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing

b) DDR333B (166 MHz, CL = 2.5): t_CK= 6 ns, BL = 4, t_RRD= 2 × t_CK, t_RCD= 3 × t_CK, t_RAS= 5 × t_CK

Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3

Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing

c) DDR400B (200 MHz, CL = 3): t_CK= 5 ns, BL = 4, t_RRD= 2 × t_CK, t_RCD= 3 *× t_CK, t_RAS= 8 × t_CK

Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N

Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing with random address

Data Sheet

76

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5

Timing Diagrams

The timing diagrams in this chapter give an overview of possible and recommended command sequences.

5.1

Write Command: Data Input Timing

Figure 39 shows DQS versus DQ and DM Timing during write burst.

t_DQSL

t_DQSH

DQS

t_DH

t_DS

DI n

DQ

t_DH

t_DS

DM

DI n = Data In for column n.

Don’t Care

3 subsequent elements of data in are applied in programmed order following DI n.

Figure 39 Data Input (Write), Timing Burst Length = 4

Data Sheet

77

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.2

Read Command: Data Output Timing

Figure 40 shows DQS versus DQ Timing during read burst.

DQS

t_{DQSQ max}

t_QH

DQ

t_QH(Data output hold time from DQS)

t

_DQSQand t_QHare only shown once and are shown referenced to different edges of DQS, only for clarify of illustration.

.

t_DQSQand t_QHboth apply to each of the four relevant edges of DQS.

t_{DQSQ max.}is used to determine the worst case setup time for controller data capture.

t

_QHis used to determine the worst case hold time for controller data capture.

Figure 40 Data Output (Read), Timing Burst Length = 4

Data Sheet

78

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.3

Initialization and Mode Register Set Command

Figure 41 shows the timing diagram for initialization and Mode Register Sets.

Figure 41 Initialize and Mode Register Sets

Data Sheet

79

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.4

Power: Power Down Mode Command

Figure 42 shows the timing diagram for Power Down Mode.

Figure 42 Power Down Mode

Data Sheet

80

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.5

Refresh: Auto Refresh Mode Command

Figure 43 shows the timing diagram for Auto Refresh Mode.

Figure 43 Auto Refresh Mode

Data Sheet

81

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.6

Refresh: Self Refresh Mode Command

Figure 44 shows the timing diagram for Self Refresh Mode.

Figure 44 Self Refresh Mode

Data Sheet

82

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.7

Read: Without Auto Precharge Command

Figure 45 shows the timing diagram for Read without Auto Precharge.

Figure 45 Read without Auto Precharge (Burst Length = 4)

Data Sheet

83

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.8

Read: With Auto Precharge Command

Figure 46 shows the timing diagram for Read with Auto Precharge.

Figure 46 Read with Auto Precharge (Burst Length = 4)

Data Sheet

84

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.9

Read: Bank Read Access Command

Figure 47 shows the timing diagram for Read Bank Read Access.

Figure 47 Bank Read Access (Burst Length = 4)

Data Sheet

85

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.10

Write: Without Auto Precharge Command

Figure 48 shows the timing diagram for Write without Auto Precharge.

Figure 48 Write without Auto Precharge (Burst Length = 4)

Data Sheet

86

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.11

Write: With Auto Precharge Command

Figure 49 shows the timing diagram for Write with Auto Precharge.

Figure 49 Write with Auto Precharge (Burst Length = 4)

Data Sheet

87

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.12

Write: Bank Write Access Command

Figure 50 shows the timing diagram for Bank Write Access.

Figure 50 Bank Write Access (Burst Length = 4)

Data Sheet

88

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Timing Diagrams

5.13

Write: DM Operation

Figure 51 shows the timing diagram for DM Operation.

Figure 51 Write DM Operation (Burst Length = 4)

Data Sheet

89

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

System Characteristics for DDR SDRAMs

6

System Characteristics for DDR SDRAMs

The following specification parameters are required in systems using DDR400, DDR333 & DDR266 devices to

ensure proper system performance. These characteristics are for system simulation purposes and are not subject

to production test - verified by design/characterization.

Table 25

Input Slew Rate for DQ, DQS, and DM

AC Characteristics

Parameter

Symbol

DDR400

Min. Max. Min. Max. Min. Max.

0.5 4.0 0.5 4.0

DDR333

DDR266

Units Notes

1)2)

DM/DQS inout slew rate measured berween DCSLEW 0.5 4.0

V/ns

V

_IH(DC), V_{IL (DC)}, and V_IL(DC), V_{IH (DC)}

1) Pullup slew rate is characterized under the test conditions as shown in Figure 52.

2) DQS, DM, amd DQ input slew rate is specified to prevent doble clocking of data and preserve setup and hold times. Signal

transitions through the DC region must be monotonic.

Table 26

Input Setup & Hold Time Derating for Slew Rate

Input Slew Rate

0.5 V/ns

∆t_IS

0

t_IH

0

Units

ps

Notes

1)

0.4 V/ns

0.3 V/ns

+50

+100

0

ps

1) A derating factor will be used to increase t_ISand t_IHin the case where the input slew rate is below 0.5 V/ns as shown in

Table 26. The input slew rate is based on the lesser of the slew rates determined by either V_IH(AC) to V_IL(AC) or V_IH(DC)

to V_IL(DC), similarly for rising transitions. Aderating factor applies to speed bins DDR200, DDR266, and DDR333.

Table 27

Input/Output Setup and Hold TIme Derating for Slew Rate

I/O Input Slew Rate

0.5 ns/V

∆t_DS

0

t_DH

0

Units

ps

Notes

1)

0.4 ns/V

0.3 ns/V

+75

+100

+75

+100

ps

1) Table 27 is used to increase t_DSand t_DHin the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based

on the lesser of the AV – AC slew rate and the DC – DC slew rate. The input slew rate is based on the lesser of the slew

rates determined by either V_IH(AC) to V_IL(AC) or V_IH(DC) to V_IL(DC), and similarly for rising transitions. A derating factor

applies to speed bins DDR200, DDR266 and DDR333.

Table 28

Input/Output Setup and Hold Derating for Rise/Fall Delta Slew Rate

Delta Slew Rate

±0.0 ns/V

∆t_DS

0

t_DH

0

Units

ps

Notes

1)

±0.25 ns/V

±0.5 ns/V

+50

+100

+50

+100

ps

1) A derating factor will be used to increase t_DSand t_DHin the case where DQ, DM and DQS slew rates differ, as shown in

Figure 27 & Figure 28. Input slew rate is based on the larger of AC – AC delta rise, fall rate and DC – DC delta rise, fall

rate. Input slew rate is based on the lesser of the slew rates determined by either V_IH(AC) to V_IL(AC) or V_IH(DC) to V_IL

(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as:{1/(Slew Rate1)} – {1/(Slew Rate2)}

For example: If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is –0.5 ns/V. Using the

table given, this would result in the need for an increase in t_DSand t_DHof 100 ps. A derating factor applies to speed bins

DDR200, DDR266, and DDR333.

Data Sheet

90

Rev. 1.6, 2004-12

08012003-8754-PAQX

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

System Characteristics for DDR SDRAMs

Table 29

Output Slew Rate Characteristrics (×4, ×8 Devices only)

Slew Rate Characteristic

Pullup Slew Rate

Pulldown Slew Rate

Typical Range (V/ns) Minimum (V/ns)

Maximum (V/ns) Notes

1)2)3)4)5)6)

1.2 – 2.5

1.0

4.5

2)3)4)5)7)

1.2 – 2.5

1.0

4.5

Table 30

Output Slew Rate Characteristics (×16 Devices only)

Slew Rate Characteristic

Pullup Slew Rate

Pulldown Slew Rate

Typical Range (V/ns)

1.2 – 2.5

Minimum (V/ns)

0.7

Maximum(V/ns)

5.0

Notes

1)2)3)4)5)6)

2)3)4)5)7)

1) Pullup slew rate is characterizted under the test conditions as shown in Figure 52

2) Pullup slew rate is measured between (V_DDQ/2 – 320 mV ± 250 mV)

Pulldown slew rate is measured between (V_DDQ/2 + 320 mV ± 250mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one

output switching.Example: For typical slew rate, DQ0 is switching.For minimum slew rate, all DQ bits are switchiung worst

case pattern. For maximum slew rate, only one DQ is switching from either high to low, or low to high the remainig DQ bits

remain the same as previous state.

3) Evaluation conditions: Typical: 25 °C (T Ambient), V_DDQ= nominal, typical process.Minimum: 70 °C (T Ambient), V_DDQ

=

minimum, slow – slow process. Maximum: 0 °C (T Ambient), V_DDQ= maximum, fast – fast process

4) Verified under typical conditions for qualification purposes.

5) TSOP II package devices only.

6) Only intended for operation up to 266 Mbps per pin.

7) Pulldown slew rate is measured under the test conditions shown in Figure 53.

Table 31

Output Slew Rate Matching Ratio Characteristics

Slew Rate Characteristic

Parameter

Output SLew Rate Matching Ratio (Pullup to Pulldown) —

DDR266A DDR266B DDR200

Min. Max. Min. Max. Min.

Notes

Max.

1.4

1) 2)

—

0.71

1) The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire

temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown

drivers due to process variation.

2) DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.

Signal transitions through the DC region must be monotonic

ꢀ_ꢁꢁꢂ

ꢕꢆꢠ

.6+F6+

(;9+ꢠF%35+

ꢃꢄꢘꢅꢏꢓꢓꢆ

Figure 52 Pullup slew rate test load

(;9+ꢠF%35+

.6+F6+

ꢕꢆꢠ

ꢀ_ꢃꢃꢂ

ꢃꢄꢘꢅꢐꢆꢆꢆ

Figure 53 Pulldown slew rate test load

Data Sheet

91

Rev. 1.6, 2004-12

08012003-8754-PAQX

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Package Outlines

7

Package Outlines

There are two package types used for this product family each in lead-free and lead-containing assembly:

P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package

•

Table 32

TFBGA Common Package Properties (non-green/green)

Description

Ball Size

Recommended Landing Pad

Recommended Solder Mask

Size

Units

mm

0.460

0.350

0.450

mm

12

11 x 1 = 11

0.18 MAX.

1

0.2

5)

B

0.05²⁾

5)

1)

3)

4)

A

0.1

C

0.1

C

60x

ø0.15

ø0.08

±0.05

ø0.46

M

A B

C SEATING PLANE

C

1.5 ²⁾

4.25

1) A1 Marking Ballside

2) A1 Marking Chipside

3) Dummy Pads without Ball

4) Bad Unit Marking (BUM)

5) Middle of Packages Edges

GPA09555

Figure 54 Package Outline of P-TFBGA-60-12 (non-green/green)

Data Sheet

92

Rev. 1.6, 2004-12

HYB25D256[16/40/80]0C[E/C/F/T](L)

256 Mbit Double-Data-Rate SDRAM

Package Outlines

•

P-TSOPII: Plastic Thin Small Outline Package Type II

Gage Plane

±0.13

10.16

±0.1

±0.2

0.65 Basic

0.5

+0.1

0.805 REF

0.1

Seating Plane

0.35

-0.05

11.76

±0.13

22.22

Lead 1

GPX09261

Figure 55 Package Outline of P-TSOPII-66-1 (non-green/green)

Data Sheet

93

Rev. 1.6, 2004-12

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	HYB25D256400CC-6
厂家：	Infineon
描述：	256 Mbit Double Data Rate SDRAM 256兆双倍数据速率SDRAM 内存集成电路动态存储器双倍数据速率时钟
文件：	总94页 (文件大小：3259K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYB25D256400CC-6 [INFINEON]

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