HYB18T256400AF-3.7_技术文档

Data Sheet, Rev. 1.1, Sep. 2004

HYB18T256400AF

HYB18T256800AF

HYB18T256160AF

256-Mbit Double-Data-Rate-Two SDRAM

DDR2 SDRAM

RoHS Compliant Products

Memory Products

N e v e r s t o p t h i n k i n g .

The information in this document is subject to change without notice.

Edition 2004-09

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Data Sheet, Rev. 1.1, Sep. 2004

HYB18T256400AF

HYB18T256800AF

HYB18T256160AF

256-Mbit Double-Data-Rate-Two SDRAM

DDR2 SDRAM

RoHS Compliant Products

Memory Products

N e v e r s t o p t h i n k i n g .

HYB18T256[40/80/16]0AF–[3.7/5]

Revision History:

2004-09

Rev. 1.1

Previous Version:

2004-04-30 (V1.01)

Page

all

Subjects (major changes since last revision)

Document contains final currents

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Document contains green products only

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HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

256 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.1

1.2

1.3

1.4

1.5

1.6

2

2.1

2.2

2.2.1

2.2.2

2.2.2.1

2.2.3

2.2.3.1

2.2.3.2

2.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Programming the Mode Register and Extended Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DDR2 SDRAM Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DDR2 SDRAM Extended Mode Register Set (EMRS(1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

EMR(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EMR(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Off-Chip Driver (OCD) Impedance Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Bank Activate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Read and Write Commands and Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Posted CAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Write Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Burst Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Read Operation Followed by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Write followed by Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Auto-Precharge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Read with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Write with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Read or Write to Precharge Command Spacing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Concurrent Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Auto-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Self-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Deselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Asynchronous CKE LOW Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2.4

2.5

2.6

2.6.1

2.6.2

2.6.3

2.6.4

2.6.5

2.6.6

2.7

2.7.1

2.7.2

2.8

2.8.1

2.8.2

2.8.3

2.8.4

2.9

2.9.1

2.9.2

2.10

2.11

2.11.1

2.11.2

2.12

2.13

3

4

Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Default Output V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Calibrated Output Driver V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1

5.2

5.3

5.4

5.4.1

Data Sheet

5

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Table of Contents

5.5

5.6

5.7

Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Power & Ground Clamp V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6

6.1

6.2

I

_DDSpecifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

_DDTest Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

I

On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

8

8.1

8.2

AC Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Reference Load for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Slew Rate Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Input Slew Rate - Differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Input and Data Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Definition for Input Setup (t_IS) and Hold Time (t_IH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Definition for Data Setup (t_DS) and Hold Time (t_DH), differential Data Strobes . . . . . . . . . . . . . . . . 89

Definition for Data Setup (t_DS1) and Hold Time (t_DH1), Single-Ended Data Strobes . . . . . . . . . . . . . 90

Slew Rate Definition for Input and Data Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Setup (t_IS) and Hold (t_IH) Time Derating Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8.2.1

8.2.2

8.3

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

9

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10

DDR2 Component Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Data Sheet

6

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

1

Overview

This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its

main characteristics.

1.1

Features

The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:

•

1.8 V ± 0.1 V Power Supply

•

Commands entered on each positive clock edge,

data and data mask are referenced to both edges of

DQS

1.8 V ± 0.1 V (SSTL_18) compatible I/O

DRAM organisations with 4, 8 and 16 data

in/outputs

Double Data Rate architecture: two data transfers

per clock cycle, four internal banks for concurrent

operation

•

Data masks (DM) for write data

Posted CAS by programmable additive latency for

better command and data bus efficiency

Off-Chip-Driver impedance adjustment (OCD) and

On-Die-Termination (ODT) for better signal quality.

Auto-Precharge operation for read and write bursts

Auto-Refresh, Self-Refresh and power saving

Power-Down modes

Average Refresh Period 7.8 µs at a T_CASElower

than 85 °C, 3.9 µs between 85 °C and 95 °C

Normal and Weak Strength Data-Output Drivers

1K page size

•

CAS Latency: 3, 4 and 5

Burst Length: 4 and 8

•

Differential clock inputs (CK and CK)

Bi-directional, differential data strobes (DQS and

DQS) are transmitted / received with data. Edge

aligned with read data and center-aligned with write

data.

DLL aligns DQ and DQS transitions with clock

DQS can be disabled for single-ended data strobe

operation

•

Packages:

P-TFBGA-60 for ×4 & ×8 components

P-TFBGA-84 for ×16 components

•

RoHS Compliant Products¹⁾

Table 1

High Performance

Product Type Speed Code

Speed Grade

–3.7

DDR2–533 4–4–4

f_CK5266

–5

Unit

—

DDR2–400 3–3–3

max. Clock Frequency

@CL5

@CL4

@CL3

200

15

MHz

ns

f_CK4266

f_CK3200

t_RCD15

min. RAS-CAS-Delay

min. Row Precharge Time

min. Row Active Time

min. Row Cycle Time

t_RP

t_RAS45

t_RC60

15

ns

40

ns

55

ns

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic

equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January

2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and

polybrominated biphenyl ethers.

Data Sheet

7

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

1.2

Description

The 256-Mb DDR2 DRAM is a high-speed Double- All of the control and address inputs are synchronized

Data-Rate-2 CMOS Synchronous DRAM device with a pair of externally supplied differential clocks.

containing 268,435,456 bits and internally configured Inputs are latched at the cross point of differential

as a quad-bank DRAM. The 256-Mb device is clocks (CK rising and CK falling). All I/Os are

organized as either 16 Mbit × 4 I/O × 4 banks, 8 Mbit × 8 synchronized with a single ended DQS or differential

I/O × 4 banks or 4 Mbit × 16 I/O × 4 banks chip. These DQS-DQS pair in a source synchronous fashion.

synchronous devices achieve high speed transfer rates

starting at 400 Mb/sec/pin for general applications. See

bank address information in a RAS-CAS multiplexing

Table 1 for performance figures.

A 15 bit address bus is used to convey row, column and

style.

The device is designed to comply with all DDR2 DRAM

key features:

The DDR2 device operates with a 1.8 V ± 0.1 V power

supply. An Auto-Refresh and Self-Refresh mode is

provided along with various power-saving power-down

modes.

1. posted CAS with additive latency,

2. write latency = read latency - 1,

The functionality described and the timing

specifications included in this data sheet are for the

DLL Enabled mode of operation.

3. normal and weak strength data-output driver,

4. Off-Chip Driver (OCD) impedance adjustment

5. On-Die Termination (ODT) function.

The DDR2 SDRAM is available in P-TFBGA package.

1.3

Ordering Information

Table 2

Ordering information for RoHS Compliant Products

Org. Speed

CAS¹⁾-RCD²⁾-RP³⁾Clock CAS¹⁾-RCD²⁾-RP³⁾Clock Package

Part Number

(MHz)

Latencies

HYB18T256400AF–5 ×4

HYB18T256800AF–5 ×8

HYB18T256160AF–5 ×16

HYB18T256400AF–3.7 ×4

HYB18T256800AF–3.7 ×8

HYB18T256160AF–3.7 ×16

DDR2–400 3–3–3

200

—

P-TFBGA-60

P-TFBGA-84

P-TFBGA-60

DDR2–533 4–4–4

266

3–3–3

200

P-TFBGA-84

1) CAS: Column Adress Strobe

2) RCD: Row Column Delay

3) RP: Row Precharge

Note:For product nomenclature see Chapter 10 of this data sheet

Data Sheet

8

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

1.4

Pin Configuration

The pin configuration of a DDR2 SDRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer

Type columns are explained in Table 4 and Table 5 respectively. The pin numbering for the FBGA package is

depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16.

Table 3

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Type

Buffer

Type

Function

Clock Signals ×4/×8 organizations

E8

F8

CK

I

SSTL

Clock Signal CK, Complementary Clock Signal CK

Note:CK and CK are differential system clock inputs. All address

and control inputs are sampled on the crossing of the

positive edge of CK and negative edge of CK. Output (read)

data is referenced to the crossing of CK and CK (both

direction of crossing)

F2

CKE

I

SSTL

Clock Enable

Note:CKE HIGH activates and CKE LOW deactivates internal

clock signals and device input buffers and output drivers.

Taking CKE LOW provides Precharge Power-Down and

Self-Refresh operation (all banks idle), or Active Power-

Down (row Active in any bank). CKE is synchronous for

power down entry and exit and for self-refresh entry. Input

buffers excluding CKE are disabled during self-refresh.

CKE is used asynchronously to detect self-refresh exit

condition. Self-refresh termination itself is synchronous.

After V_REFhas become stable during power-on and

initialisation sequence, it must be maintained for proper

operation of the CKE receiver. For proper self-refresh entry

and exit, V_REFmust be maintained to this input. CKE must

be maintained HIGH throughout read and write accesses.

Input buffers, excluding CK, CK, ODT and CKE are disabled

during power-down

Clock Signals ×16 organization

J8

CK

I

SSTL

Clock Signal CK, Complementary Clock Signal CK

Clock Enable

K8

K2

CK

CKE

Control Signals ×4/×8 organizations

F7

G7

F3

RAS

CAS

WE

I

SSTL

Row Address Strobe (RAS), Column Address Strobe (CAS),

Write Enable (WE)

Note:RAS, CAS and WE (along with CS) define the command

being entered.

G8

CS

I

SSTL

Chip Select

Note:All command are masked when CS is registered HIGH. CS

provides for external rank selection on systems with

multiple memory ranks. CS is considered part of the

command code.

Control Signals ×16 organization

Data Sheet

9

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

Table 3

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Type

Buffer

Type

Function

K7

L7

K3

L8

RAS

CAS

WE

I

SSTL

Row Address Strobe (RAS), Column Address Strobe (CAS),

Write Enable (WE)

CS

Chip Select

Address Signals ×4/×8 organizations

G2

G3

BA0

BA1

I

SSTL

Bank Address Bus 1:0

Note:BAn define to which bank an Activate, Read, Write or

Precharge command is being applied. BAn also determines

if the mode register or extended mode register is to be

accessed during a MRS or EMRS(1) cycle

H8

H3

H7

J2

A0

I

SSTL

Address Signal 12:0, Address Signal 10/Autoprecharge

Note:Provides the row address for Activate commands and the

column address and Auto-Precharge bit A10 (=AP) for

Read/Write commands to select one location out of the

memory array in the respective bank. A10(=AP) is sampled

during a Precharge command to determine whether the

Precharge applies to one bank (A10=LOW) or all banks

(A10=HIGH). If only one bank is to be precharged, the bank

is selected by BAn. The address inputs also provide the op-

code during Mode Register Set commands.

A1

A2

A3

J8

A4

J3

A5

J7

A6

K2

K8

K3

H2

A7

A8

A9

A10

AP

A11

A12

A13

K7

L2

L8

Address Signal 13

Note:512 Mbit components

Note:256 Mbit components

NC

–

Address Signals ×16 organization

L2

L3

L1

BA0

BA1

NC

I

SSTL

–

Bank Address Bus 1:0

I

–

Data Sheet

10

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

Table 3

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Type

Buffer

Type

Function

M8

M3

M7

N2

N8

N3

N7

P2

P8

P3

M2

A0

I

SSTL

Address Signal 12:0, Address Signal 10/Autoprecharge

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

AP

A11

A12

P7

R2

Data Signals ×4/×8 organizations

C8

C2

D7

D3

DQ0

DQ1

DQ2

DQ3

I/O

SSTL

Data Signal 3:0

Note:Bi-directional data bus. DQ[3:0] for ×4 components, DQ[7:0]

for ×8 components

Data Signals ×8 organization

D1

D9

B1

B9

DQ4

DQ5

DQ6

DQ7

I/O

SSTL

Data Signal 7:4

Data Signals ×16 organization

Data Sheet

11

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

Table 3

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Type

Buffer

Type

Function

G8

G2

H7

H3

H1

H9

F1

F9

C8

C2

D7

D3

D1

D9

B1

B9

DQ0

I/O

SSTL

Data Signal 15:0

Note:Bi-directional data bus. DQ[15:0] for ×16 components

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

Data Strobe ×4/×8 organisations

B7

A8

DQS

I/O

SSTL

Data Strobe

Note:Output with read data, input with write data. Edge aligned

with read data, centered with write data. For the ×16, LDQS

corresponds to the data on DQ[7:0]; UDQS corresponds to

the data on DQ[15:8]. The datastrobes DQS, LDQS, UDQS

may be used in single ended mode or paired with the

optional complementary signals DQS, LDQS, UDQS to

provide differential pair signaling to the system during both

reads and writes. An EMRS(1) control bit enables or

disables the complementary data strobe signals

Data Strobe ×8 organisations

B3

A2

RDQS

I

SSTL

Read Data Strobe

Data Strobe ×16 organization

B7

UDQS

I/O

SSTL

Data Strobe Upper Byte

A8

UDQS

I/O

F7

E8

LDQS

I/O

SSTL

Data Strobe Lower Byte

Data Mask ×4/×8 organizations

Data Sheet

12

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

Table 3

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Type

Buffer

Type

Function

B3

DM

I

SSTL

Data Mask

Note:DM is an input mask signal for write data. Input data is

masked when DM is sampled HIGH coincident with that

input data during a Write access. DM is sampled on both

edges of DQS. Although DM pins are input only, the DM

loading matches the DQ and DQS loading. LDM and UDM

are the input mask signals for x16 components and control

the lower or upper bytes. For x8 components the data mask

function is disabled, when RDQS / RQDS are enabled by

EMRS(1) command.

Data Mask ×16 organization

B3

F3

UDM

LDM

I

SSTL

Data Mask Upper Byte

Data Mask Lower Byte

Power Supplies ×4/×8/×16 organizations

A9,C1,C3,C7, V_DDQ

PWR

–

I/O Driver Power Supply

C9

A1

V_DD

PWR

–

Power Supply

A7,B2,B8,D2, V_SSQ

D8

A3,E3

V_SS

PWR

–

Power Supply

Power Supplies ×4/×8 organizations

E2

V_REF

V_DDL

V_DD

AI

–

I/O Reference Voltage

Power Supply

E1

PWR

E9,H9,L1

E7

Power Supply

V_SSDL

V_SS

Power Supply

J1,K9

Power Supply

Power Supplies ×16 organization

J2

V_REF

V_DDQ

AI

–

I/O Reference Voltage

E9, G1, G3,

G7, G9

PWR

I/O Driver Power Supply

J1

V_DDL

PWR

–

Power Supply

E1, J9, M9, R1 V_DD

E7, F2, F8, H2, V_SSQ

H8

J7

V_SSDL

V_SS

PWR

–

Power Supply

J3,N1,P9

Not Connected ×4/×8 organizations

G1, L3,L7, L8 NC

NC

–

Not Connected

Note:No internal electrical connection is present

Not Connected ×4 organization

A2, B1, B9,

D1, D9

NC

–

Not Connected

Not Connected ×16 organization

Data Sheet

13

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

Table 3

Pin Configuration of DDR SDRAM

Ball#/Pin#

Name

Type

Buffer

Type

Function

A2, E2, L1, R3, NC

R7, R8

NC

–

Not Connected

Other Pins ×4/×8 organizations

F9 ODT

I

SSTL

On-Die Termination Control

Note:ODT (registered HIGH) enables termination resistance

internal to the DDR2 SDRAM. When enabled, ODT is

applied to each DQ, DQS, DQS and DM signal for ×4 and

DQ, DQS, DQS, RDQS, RDQS and DM for ×8

configurations. For ×16 configuration ODT is applied to

each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM

signal. The ODT pin will be ignored if the Extended Mode

Register (EMRS(1)) is programmed to disable ODT.

Other Pins ×16 organization

K9

ODT

I

SSTL

On-Die Termination Control

Table 4

Abbreviations for Pin Type

Description

Abbreviation

I

Standard input-only pin. Digital levels.

O

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

I/O

AI

PWR

GND

NC

Ground

Not Connected

Table 5

Abbreviation

SSTL

Abbreviations for Buffer Type

Description

Serial Stub Terminated Logic (SSTL_18)

Low Voltage CMOS

LV-CMOS

CMOS

OD

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tristate, and

allows multiple devices to share as a wire-OR.

Data Sheet

14

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

1

2

3

4

5

6

7

8

9

A

V_DD

V_SS

V_SSQ

V_DDQ

NC

DQS

V_SSQ

B

C

D

E

F

G

H

J

NC

DM

DQS

NC

V_DDQ

DQ1

DQ0

V_SSQ

NC

DQ3

DQ2

V_SSDL

RAS

CAS

A2

NC

V_DDL

V_REF

V_SS

V_DD

CK

CKE

BA0

A10/AP

A3

WE

BA1

A1

ODT

NC

CS

V_DD

A0

V_SS

A5

A6

A4

V_SS

K

L

A7

A9

A11

NC

A8

V_DD

A12

NC

NC/A13

MPPT0020

Figure 1

Notes

Pin Configuration for ×4 components, P-TFBGA-60 (top view)

1. V_DDLand V_SSDLare power and ground for the 2. Ball position L8 is A13 for 512-Mbit and is Not

DLL.They are connected on the device to V_DD, and

Connected on 256-Mbit

V_SS

Data Sheet

15

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

1

2

3

4

5

6

7

8

9

A

V_DD

V_SS

V_SSQ

V_DDQ

NC/RDQS

DQS

V_SSQ

B

C

D

E

F

G

H

J

DQ6

DM/RDQS

DQS

DQ7

V_DDQ

DQ1

DQ0

V_SSQ

DQ4

DQ3

DQ2

V_SSDL

RAS

CAS

A2

DQ5

V_DDL

V_REF

V_SS

V_DD

CK

CKE

BA0

A10/AP

A3

WE

BA1

A1

ODT

NC

CS

V_DD

A0

V_SS

A5

A6

A4

V_SS

K

L

A7

A9

A11

NC

A8

V_DD

A12

NC

NC/A13

MPPT0090

Figure 2

Notes

Pin Configuration for ×8 components, P-TFBGA-60 (top view)

1. RDQS / RDQS are enabled by EMRS(1) command. 4. V_DDLand V_SSDLare power and ground for the DLL.

2. If RDQS / RDQS is enabled, the DM function is

They are connected on the device to V_DDand V_SS.

5. Ball position L8 is A13 for 512-Mbit and is Not

Connected on 256-Mbit.

disabled

3. When enabled, RDQS & RDQS are used as strobe

signals during reads.

Data Sheet

16

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

1

2

3

4

5

A

B

C

D

E

F

6

7

8

9

V_DD

NC

V_SS

V_SSQ

V_DDQ

UDQS

V_SSQ

DQ14

UDM

UDQS

DQ15

V_DDQ

DQ9

DQ8

V_SSQ

DQ12

DQ11

DQ10

DQ13

V_DD

V_SS

V_SSQ

V_DDQ

NC

LDQS

V_SSQ

DQ6

LDM

LDQS

DQ7

V_DDQ

G

H

J

DQ1

DQ0

V_SSQ

DQ4

DQ3

DQ2

VSSDL

RAS

CAS

A2

DQ5

V_DDL

V_REF

V_SS

V_DD

CK

CS

A0

A4

A8

NC

K

L

CKE

BA0

A10/AP

A3

WE

BA1

A1

ODT

NC

V_DD

M

N

P

R

V_SS

A5

A6

V_SS

A7

A9

A11

NC

V_DD

A12

NC

MPPT0120

Figure 3

Notes

Pin Configuration for ×16 components, P-TFBGA-84 (top view)

1. UDQS/UDQS is data strobe for DQ[15:8], 3. V_DDLand V_DDSLare power and ground for the DLL.

LDQS/LDQS is data strobe for DQ[7:0]

2. LDM is the data mask signal for DQ[7:0], UDM is the

data mask signal for DQ[15:8]

They are connected on the device to V_DDand V_SS.

Data Sheet

17

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

1.5

256 Mbit DDR2 Addressing

Table 6

256 Mbit DDR2 Addressing

Configuration

Number of Banks

Bank Address

Auto-Precharge

Row Address

64 Mb x 4

4

32 Mb x 8

4

16 Mb x 16

4

Note

BA[0:1]

A10 / AP

A[12:0]

A11, A[9:0]

BA[0:1]

A10 / AP

A[12:0]

A[9:0]

10

BA[0:1]

A10 / AP

A[12:0]

A[8:0]

10

Column Address

1)

2)

3)

Number of Column Address Bits 11

Number of I/Os

4

8

16

Page Size [Bytes]

1024 (1K)

1) Refered to as ’colbits’

2) Refered to as ’org’

org

8

PageSize = 2^colbits

×

[Bytes]

--------

3)

Data Sheet

18

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

1.6

Block Diagrams

ODT Control

Receivers

Drivers

Read Latch

Row-Address MUX

Refresh Counter

Address Register

MPBT0280

Figure 4

Notes

Block Diagram 16 Mbit × 4 I/O × 4 Internal Memory Banks

device; it does not represent an actual circuit

implementation.

3. LDM, UDM is a unidirectional signal (input only), but

is internally loaded to match the load of the

bidirectional LDQS and UDQS signals.

1. 64Mb × 4 Organisation with 13 Row, 2 Bank and 11

Column External Adresses

2. This Functional Block Diagram is intended to

facilitate user understanding of the operation of the

Data Sheet

19

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

ODT Control

Receivers

Drivers

Read Latch

Row-Address MUX

Refresh Counter

Address Register

MPBT0270

Figure 5

Notes

Block Diagram 8 Mbit × 8 I/O × 4 Internal Memory Banks

device; it does not represent an actual circuit

implementation.

3. LDM, UDM is a unidirectional signal (input only), but

is internally loaded to match the load of the

bidirectional LDQS and UDQS signals.

1. 32Mb × 8 Organisation with 13 Row, 2 Bank and 10

Column External Adresses

2. This Functional Block Diagram is intended to

facilitate user understanding of the operation of the

Data Sheet

20

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Overview

ODT Control

Receivers

Drivers

Read Latch

Row-Address MUX

Refresh Counter

Address Register

MPBT0260

Figure 6

Notes

Block Diagram 4 Mbit × 16 I/O × 4 Internal Memory Banks

device; it does not represent an actual circuit

implementation.

3. LDM, UDM is a unidirectional signal (input only), but

is internally loaded to match the load of the

bidirectional LDQS and UDQS signals.

1. 16Mb × 16 Organisation with 13 Row, 2 Bank and 9

Column External Adresses

2. This Functional Block Diagram is intended to

facilitate user understanding of the operation of the

Data Sheet

21

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2

Functional Description

2.1

Simplified State Diagram

Auto

Refreshing

CKEL

Initialization

Sequence

Self

Refresh

t_RFC

CKEL

PD_entry

CKEH

MRS

Setting

MRS or

EMRS

Precharge

PD

Idle

t_MRD

Activating

t_RCD

RL + BL/2 + t_RTP

Reading_AP

WL + BL/2 + WR

Writing_AP

t_RP

Precharging

Write

Read

Writing

Reading

CKEL

PD_entry

CKEH

Automatic Sequence

Command Sequence

Bank

Active

Active PD

MPFT0010

Figure 7

Simplified State Diagram

Note:This Simplified State Diagram is intended to

provide a floorplan of the possible state

bank, enabling / disabling on-die termination,

Power-Down entry / exit - among other things -

are not captured in full detail.

transitions and the commands to control them. In

particular situations involving more than one

Data Sheet

22

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.2

Basic Functionality

Read and write accesses to the DDR2 SDRAM are The address bits registered coincident with the Read or

burst oriented; accesses start at a selected location Write command are used to select the starting column

and continue for the burst length of four or eight in a location for the burst access and to determine if the

programmed sequence.

Auto-Precharge command is to be issued.

Accesses begin with the registration of an Activate Prior to normal operation, the DDR2 SDRAM must be

command, which is followed by a Read or Write initialized. The following sections provide detailed

command. The address bits registered coincident with information covering device initialization, register

the activate command are used to select the bank and definition, command description and device operation.

row to be accessed.

2.2.1

Power On and Initialization

DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation.

Power-up and Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1. Apply power and attempt to maintain CKE below

0.2 × V_DDQand ODT at a low state (all other inputs

may be undefined). To guarantee ODT off, V_REF

must be valid and a low level must be applied to the

ODT pin. Maximum power up interval for V_DD/ V_DDQ

is specified as 10.0 ms. The power interval is

defined as the amount of time it takes for V_DD/ V_DDQ

to power-up from 0 V to 1.8 V ± 100 mV. At least

one of these two sets of conditions must be met:

3. Apply NOP or Deselect commands and take CKE

high.

4. Continue NOP or Deselect Commands for 400 ns,

then issue a Precharge All command.

5. Issue EMRS(2) command.

6. Issue EMRS(3) command.

7. Issue EMRS(1) command to enable DLL.

8. Issue a MRS command for “DLL reset”.

9. Issue Precharge-all command.

– V_DD, V_DDLand V_DDQare driven from a single 10. Issue 2 or more Auto-refresh commands.

power converter output, AND

– V_TTis limited to 0.95 V max, AND

– V_REFtracks V_DDQ/2

11. Issue the final MRS command to turn the DLL on

and to set the necessary operating parameter.

12. At least 200 clocks after step 8, issue EMRS(1)

commands to either execute the OCD calibration or

select the OCD default. Issue the final EMRS(1)

command to exit OCD calibration mode and set the

necessary operating parameters.

or

– Apply V_DDbefore or at the same time as V_DDQ

.

– Apply V_DDQbefore or at the same time as V_TT

V_REF

&

.

13. The DDR2 SDRAM is now ready for normal

operation.

2. Start clock (CK, CK) and maintain stable power and

clock condition for a minimum of 200 µs.

Data Sheet

23

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

CK, CK

CKE

ODT "low"

Follow OCD

tMRS

tRP

tMRS

tRP

tRFC

tMRS

400 ns

tMRS

flowchart

PRE

ALL

PRE

ALL

2nd Auto

refresh

1st Auto

refresh

Any

Command

EMRS(1)

OCD

EMRS(1)

OCD

NOP

EMRS(2)

EMRS(3)

EMRS(1)

MRS

min. 200 cycles to lock the DLL

Extended

Mode

Register(1) Set

with DLL enable

Mode

Register

Set with

OCD Drive(1)

or

OCD

calibration

Set w/o

DLL reset

OCD default

mode exit

Figure 8

Initialization Sequence after Power Up

2.2.2

Programming the Mode Register and Extended Mode Registers

For application flexibility, burst length, burst type, CAS All banks must be in a precharged state and CKE must

latency, DLL reset function, write recovery time (WR) be high at least one cycle before the Mode Register Set

are user defined variables and must be programmed Command can be issued. Either MRS or EMRS

with

a

Mode Register Set (MRS) command. Commands are activated by the low signals of CS,

Additionally, DLL disable function, additive CAS RAS, CAS and WE at the positive edge of the clock.

latency, driver impedance, On Die Termination (ODT),

When bank addresses are 0, the DDR2 SDRAM

single-ended strobe and Off Chip Driver impedance

enables the MRS command. When the bank addresses

adjustment (OCD) are also user defined variables and

BA0 is 1 and BA1 0, the DDR2 SDRAM enables the

must be programmed with an Extended Mode Register

EMRS(1) command.

Set (EMRS) command.

The address input data during this cycle defines the

Contents of the Mode Register (MR) or Extended Mode

parameters to be set as shown in the MRS and EMRS

Registers (EMR(1, 2, 3)) can be altered by re-executing

the MRS and EMRS Commands. If the user chooses to

modify only a subset of the MR or EMR variables, all

MRS, EMRS and DLL Reset do not affect array

variables must be redefined when the MRS or EMRS

contents, which means reinitialization including those

commands are issued.

tables. A new command may be issued after the mode

register set command cycle time (t_MRD).

can be executed any time after power-up without

After initial power up, all MRS and EMRS Commands

affecting array contents.

must be issued before read or write cycles may begin.

2.2.2.1

DDR2 SDRAM Mode Register Set (MRS)

The mode register stores the data for controlling the and clock cycle requirements during normal operation

various operating modes of DDR2 SDRAM. It programs as long as all banks are in the precharged state. The

CAS latency, burst length, burst sequence, test mode, mode register is divided into various fields depending

DLL reset, Write Recovery (WR) and various vendor on functionality.

specific options to make DDR2 SDRAM useful for

various applications.

Burst length is defined by A[2:0] with options of 4 and 8

bit burst length. Burst address sequence type is defined

The default value of the mode register is not defined, by A3 and CAS latency is defined by A[6:4]. A7 is used

therefore the mode register must be written after for test mode and must be set to 0 for normal DRAM

power-up for proper operation. The mode register is operation. A8 is used for DLL reset. A[11:9] are used for

written by asserting low on CS, RAS, CAS, WE, write recovery time (WR) definition for Auto-Precharge

BA[0:1], while controlling the state of address pins mode. With address bit A12 two Power-Down modes

A[12:0]. The DDR2 SDRAM should be in all bank can be selected, a “standard mode” and a “low-power”

precharged (idle) mode with CKE already high prior to Power-Down mode, where the DLL is disabled.

writing into the mode register. The mode register set Address bit A13 and all “higher” address bits have to

command cycle time (t_MRD) is required to complete the be set to 0 for compatibility with other DDR2 memory

write operation to the mode register. The mode register products with higher memory densities.

contents can be changed using the same command

Data Sheet

24

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

MR

Mode Register Definition

(BA[2:0] = 000_B)

BA2 BA1 BA0 A13 A12 A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

0¹⁾

0

0²⁾

PD

WR

DLL

TM

CL

BT

BL

w

reg. addr

w

1) BA2 is not available on 256 and 512 Mbit components

2) A13 is not available for 256 Mbit and x16 512 Mbit configuration

Field Bits Type¹⁾Description

BL

BT

CL

[2:0]

w

Burst Length

010 4

011 8

3

Burst Type

0

1

Sequential

Interleaved

[6:4]

CAS Latency

Note: All other bit combinations are illegal.

010 2 ²⁾

011 3

100 4

101 5

TM

7

8

w

Test Mode

0

1

Normal mode

Vendor specific test mode

DLL

DLL Reset

0

No

1

Yes

WR [11:9] w

Write Recovery³⁾

Note: All other bit combinations are illegal.

001 2

010 3

011 4

100 5

101 6

PD

12

w

Active Power-Down Mode Select

0

1

Fast exit

Slow exit

1) w = write only register bits

2) CAS Latency 2 is optional for Jedec compliant devices. This option is implemented in this device but is neither tested nor

guaranteed.

3) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t_WR(in ns)

by t_CK(in ns) and rounding up to the next integer:

WR[cycles] ≥ t_WR(ns) / t_CK(ns)

The mode register must be programmed to fulfill the minimum requirement for the analogue t_WRtiming. W_R.MINis

determined by t_CK.MAXand W_R.MAXis determined by t_CK.MIN

.

Data Sheet

25

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.2.3

DDR2 SDRAM Extended Mode Register Set (EMRS(1))

The Extended Mode Register EMR(1) stores the data BA0, while controlling the state of the address pins. The

for enabling or disabling the DLL, output driver DDR2 SDRAM should be in all bank precharge with

strength, additive latency, OCD program, ODT, DQS CKE already high prior to writing into the extended

and output buffers disable, RQDS and RDQS enable. mode register. The mode register set command cycle

The default value of the extended mode register time (t_MRD) must be satisfied to complete the write

EMR(1) is not defined, therefore the extended mode operation to the EMR(1). Mode register contents can

register must be written after power-up for proper be changed using the same command and clock cycle

operation. The extended mode register is written by requirements during normal operation as long as all

asserting low on CS, RAS, CAS, WE, BA1 and high on banks are in precharge state.

EMR(1)

Extended Mode Register Definition

(BA[2:0] = 001_B)

A9 A8 A7

BA2 BA1 BA0 A13 A12 A11 A10

A6

A5

A4

A3

A2

A1

A0

0¹⁾

0

1

0²⁾

Q_offRDQS DQS

OCD Program

Rtt

AL

Rtt

DIC DLL

reg. addr

w

1) BA2 is not available on 256 and 512 Mbit components

2) A13 is not available for 256 Mbit and x16 512 Mbit configuration.

Field

DLL

Bits Type¹⁾Description

0

w

DLL Enable

0

1

Enable

Disable

DIC

R_TT

1

Off-chip Driver Impedance Control

0

1

Normal (Driver Size = 100%)

Weak (Driver Size = 60%)

2,6

Nominal Termination Resistance of ODT

00 ∞ (ODT disabled)

01 75 Ohm

10 150 Ohm

11 50 Ohm

AL

[5:3]

w

Additive Latency

Note: All other bit combinations are illegal.

000 0

001 1

010 2

011 3

100 4

OCD

Program

[9:7]

10

w

Off-Chip Driver Calibration Program

000 OCD calibration mode exit, maintain setting

001 Drive (1)

010 Drive (0)

100 Adjust mode

111 OCD calibration default

DQS

Complement Data Strobe (DQS Output)

0

1

Enable

Disable

Data Sheet

26

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

Field

Bits Type¹⁾Description (cont’d)

RDQS

11

w

Read Data Strobe Output (RDQS, RDQS)

0

1

Disable

Enable

Qoff

12

w

Output Disable

0

1

Output buffers enabled

Output buffers disabled

1) w = write only register bits

A0 is used for DLL enable or disable. A1 is used for Address bit A12 have to be set to 0 for normal

enabling half-strength data-output driver. A2 and A6 operation. With A12 set to 1 the SDRAM outputs are

enables On-Die termination (ODT) and sets the Rtt disabled and in Hi-Z. 1 on BA0 and 0 for BA1 have to

value. A[5:3] are used for additive latency settings and be set to access the EMRS(1). A13 and all “higher”

A[9:7] enables the OCD impedance adjustment mode. address bits have to be set to 0 for compatibility with

A10 enables or disables the differential DQS and other DDR2 memory products with higher memory

RDQS signals, A11 disables or enables RDQS. densities. Refer to EMR(1).

Single-ended and Differential Data Strobe Signals

Table 7 lists all possible combinations for DQS, DQS, If RDQS is enabled in ×8 components, the DM function

RDQS, RQDS which can be programmed by A[11:10] is disabled. RDQS is active for reads and don’t care for

address bits in EMRS. RDQS and RDQS are available writes.

in ×8 components only.

Table 7

EMRS(1)

A11

Single-ended and Differential Data Strobe Signals

Strobe Function Matrix

Signaling

A10

RDQS/DM

RDQS

DQS

(RDQS Enable) (DQS Enable)

0 (Disable)

1 (Enable)

0 (Enable)

1 (Disable)

0 (Enable)

1 (Disable)

DM

Hi-Z

DQS

Hi-Z

DQS

Hi-Z

differential DQS signals

single-ended DQS signals

differential DQS signals

single-ended DQS signals

DM

Hi-Z

RDQS

Hi-Z

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL Any time the DLL is reset, 200 clock cycles must occur

enable is required during power up initialization, and before a Read command can be issued to allow time for

upon returning to normal operation after having the DLL the internal clock to be synchronized with the external

disabled. The DLL is automatically disabled when clock. Failing to wait for synchronization to occur may

entering Self-Refresh operation and is automatically re- result in a violation of the t_ACor t_DQSCKparameters.

enabled and reset upon exit of Self-Refresh operation.

Output Disable (Qoff)

Under normal operation, the DRAM outputs are DRAM outputs allows users to measure I_DDcurrents

enabled during Read operation for driving data (Qoff bit during Read operations, without including the output

in the EMR(1) is set to 0). When the Qoff bit is set to 1, buffer current and external load currents.

the DRAM outputs will be disabled. Disabling the

Data Sheet

27

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.2.3.1

EMR(2)

The Extended Mode Registers EMR(2) and EMR(3) with CKE already high prior to writing into the extended

are reserved for future use and must be programmed mode register. The mode register set command cycle

when setting the mode register during initialization.

time (t_MRD) must be satisfied to complete the write

operation to the EMR(2). Mode register contents can

be changed using the same command and clock cycle

requirements during normal operation as long as all

banks are in precharge state.

The extended mode register EMR(2) is written by

asserting LOW on CS, RAS, CAS, WE, BA0 and HIGH

on BA1, while controlling the states of the address pins.

The DDR2 SDRAM should be in all bank precharge

EMR(2) Programming

Extended Mode Register Definition

(BA[2:0] = 010_B)

A9 A8 A7

BA2 BA1 BA0 A13 A12 A11 A10

A6

A5

A4

A3

A2

A1

A0

0¹⁾

1

0

0²⁾³⁾

reg.addr

1) BA2 is not available on 256 and 512 Mbit components

2) A13 is not available for 256 Mbit and x16 512 Mbit configuration.

3) Must be programmed to “0”

2.2.3.2

EMR(3)

The Extended Mode Register EMR(3) is reserved for initialization. The EMRS(3) is written by asserting low

future use and all bits except BA0 and BA1 must be on CS, RAS, CAS, WE, BA2 and high on BA0 and BA1,

programmed to 0 when setting the mode register during while controlling the state of the address pins.

EMR(3) Programming

Extended Mode Register Definition

(BA[2:0] = 011_B)

A9 A8 A7

BA2 BA1 BA0 A13 A12 A11 A10

A6

A5

A4

A3

A2

A1

A0

0¹⁾

1

0²⁾³⁾

reg. addr

1) BA2 is not available on 256 and 512 Mbit components

2) A13 is not available for 256 Mbit and x16 512 Mbit configuration

3) Must be programmed to “0”

Data Sheet

28

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.3

Off-Chip Driver (OCD) Impedance Adjustment

DDR2 SDRAM supports driver calibration feature and command being issued. MRS should be set before

the flow chart below is an example of the sequence. entering OCD impedance adjustment and On Die

Every calibration mode command should be followed Termination (ODT) should be carefully controlled

by “OCD calibration mode exit” before any other depending on system environment.

Start

EMRS: OCD calibration mode exit

EMRS: Drive (1)

DQ & DQS High; DQS Low

EMRS: Drive (0)

DQ & DQS Low; DQS High

ALL OK

Test

Need Calibration

EMRS: OCD calibration mode exit

EMRS:

Enter Adjust Mode

EMRS:

Enter Adjust Mode

BL = 4 code input to all DQs

Inc, Dec or NOP

BL = 4 code input to all DQs

Inc, Dec or NOP

EMRS: OCD calibration mode exit

End

MPFT0020

Figure 9

OCD Impedance Adjustment Flow Chart

Note:MR should be set before entering OCD impedance adjustment and ODT should be carefully controlled

depending on system environment

Data Sheet

29

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

Extended Mode Register Set for OCD impedance adjustment

OCD impedance adjustment can be done using the temperature and voltage conditions. Output driver

following EMRS(1) mode. In drive mode all outputs are characteristics for OCD calibration default are specified

driven out by DDR2 SDRAM and drive of RDQS is in the following table. OCD applies only to normal full

dependent on EMR(1) bit enabling RDQS operation. In strength output drive setting defined by EMR(1) and if

Drive(1)mode, all DQ, DQS (and RDQS) signals are half strength is set, OCD default driver characteristics

driven HIGH and all DQS (and RDQS) signals are are not applicable. When OCD calibration adjust mode

driven LOW. InDrive(0) mode, all DQ, DQS (and is used, OCD default output driver characteristics are

RDQS) signals are driven LOW and all DQS (and not applicable. After OCD calibration is completed or

RDQS) signals are driven HIGH. In adjust mode, BL = driver strength is set to default, subsequent EMRS(1)

4 of operation code data must be used. In case of OCD commands not intended to adjust OCD characteristics

calibration default, output driver characteristics have a must specify A[9:7] as’000’ in order to maintain the

nominal impedance value of 18 Ohms during nominal default or calibrated value.

Table 8

Off Chip Driver Program

A9

0

A8

A7

0

Operation

0

1

0

1

OCD calibration mode exit

0

1

Drive(1) DQ, DQS, (RDQS) high and DQS (RDQS) low

Drive(0) DQ, DQS, (RDQS) low and DQS (RDQS) high

Adjust mode

0

1

0

1

OCD calibration default

OCD impedance adjust

To adjust output driver impedance, controllers must simultaneously and after OCD calibration, all DQs of a

issue the ADJUST EMRS(1) command along with a 4 given DDR2 SDRAM will be adjusted to the same driver

bit burst code to DDR2 SDRAM as in the following strength setting. The maximum step count for

table. For this operation, Burst Length has to be set to adjustment is 16 and when the limit is reached, further

BL = 4 via MRS command before activating OCD and increment or decrement code has no effect. The default

controllers must drive the burst code to all DQs at the setting may be any step within the maximum step count

same time. DT0 in the table means all DQ bits at bit range. When Adjust mode command is issued, AL from

time 0, DT1 at bit time 1, and so forth. The driver output previously set value must be applied.

impedance is adjusted for all DDR2 SDRAM DQs

Table 9

Off-Chip-Driver Adjust Program

4 bit burst code inputs to all DQs

Operation

D_T0

0

D_T1

0

D_T2

0

D_T3

0

Pull-up driver strength

NOP (no operation)

Increase by 1 step

Decrease by 1 step

NOP

Pull-down driver strength

NOP (no operation)

NOP

0

1

0

1

0

NOP

0

1

0

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

1

0

NOP

0

1

0

1

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

0

1

0

1

0

1

0

1

0

Other Combinations

Data Sheet

Illegal

30

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

For proper operation of adjust mode, WL = RL - 1 = sequential or interleave). Burst length of 4 have to be

AL + CL - 1 clocks and t_DS/ t_DHshould be met as shown programmed in the MRS for OCD impedance

in Figure 10. Input data pattern for adjustment, DT[0:3] adjustment.

is fixed and not affected by MRS addressing mode (i.e.

CK, CK

CMD

NOP

EMRS(1)

NOP

EMRS(1)

NOP

WL

tWR

DQS

DQS_in

tDS tDH

DQ_in

DM

DT2

DT3

DT0

DT1

OCD1

OCD calibration

mode exit

OCD adjust mode

Figure 10 Timing Diagram Adjust Mode

Drive Mode

Both Drive(1) and Drive(0) are used for controllers to driven out t_OITafter “enter drive mode” command and all

measure DDR2 SDRAM Driver impedance before OCD output drivers are turned-off t_OITafter “OCD calibration

impedance adjustment. In this mode, all outputs are mode exit” command. See Figure 11.

CK, CK

CMD

NOP

EMRS(1)

tOIT

NOP

EMRS(1)

tOIT

NOP

DQS_in

DQ_in

DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0

DQS high for Drive(1)

DQS high for Drive(0)

OCD calibration

mode exit

Enter Drive Mode

Figure 11 Timing Diagram Drive Mode

Data Sheet

31

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.4

On-Die Termination (ODT)

On-Die Termination (ODT) is a new feature on DDR2 only when enabled in the EMRS(1) by address bit

components that allows a DRAM to turn on/off termi- A10 = 0.

nation resistance for each DQ, DQS, DQS, DM for ×4

and DQ, DQS, DQS, DM, RDQS (DM/RDQS share the

same pin) and RDQS for ×8 configuration via the ODT

control pin. DQS and RDQS are only terminated when

tance for any or all DRAM devices.

enabled by EMR(1).

The ODT feature is designed to improve signal integrity

of the memory channel by allowing the DRAM

controller to independently turn on/off termination resis-

The ODT function can be used for all active and

standby modes. ODT is turned off and not supported in

Self-Refresh mode.

For ×16 configuration ODT is applied to each DQ,

UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via

the ODT control pin. UDQS and LDQS are terminated

VDDQ

sw2

sw3

sw1

Rval2

Rval3

Rval1

DRAM

Input

Buffer

Input

Rval2

sw2

Rval3

sw3

Rval1

sw1

ODT_funct2

VSSQ

Figure 12 Functional Representation of ODT

Switch 1, 2 or 3 are enabled by the ODT pin. Selection Target: Rval1 = Rval2 = 2 × Rtt

between 1, 2 or 3 is determined by “Rtt (nominal)” in

EMRS(1) address bits A6 & A2.

The ODT pin will be ignored if the Extended Mode

Register (EMRS(1)) is programmed to disable ODT.

Data Sheet

32

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

ODT Truth Tables

The ODT Truth Table shows which of the input pins are organisations (×4, ×8 and ×16). To activate termination

terminated depending on the state of address bit A10 of any of these pins, the ODT function has to be

and A11 in the EMRS(1) for all three device enabled in the EMRS(1) by address bits A6 and A2.

Table 10

Input Pin

ODT Truth Table

EMRS(1)

Address Bit A10

Address Bit A11

x4 components

DQ[3:0]

DQS

X

0

DQS

X

DM

X

x8 components

DQ[7:0]

DQS

X

0

DQS

X

1

0

RDQS

X

0

RDQS

DM

X

x16 components

DQ[7:0]

DQ[15:8]

LDQS

X

0

LDQS

X

UDQS

X

0

UDQS

LDM

X

UDM

Note:X = don’t care; 0 = bit set to low; 1 = bit set to high

ODT timing modes

Depending on the operating mode asynchronous or

synchronous ODT timings apply.

•

Slow Exit Active Power Down Mode (with MRS bit

A12 is set to “1”)

Precharge Power Down Mode

Asynchronous ODT timings (t_AOFPD, t_AONPD) apply when

the on-die DLL is disabled.

Synchronous ODT timings (t_AOND, t_AOFD, t_AON, t_AOF

)

apply for all other modes.

These modes are:

Data Sheet

33

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T1

T3

T4

T5

T6

T7

T8

T0

T2

CK, CK

CKE

t

IS

t

IS

ODT

tAOND (2 tck)

tAOFD (2.5 tck)

Rtt

DQ

tAON(min)

tAOF(min)

tAOF(max)

tAON(max)

ODT01

Figure 13 ODT Timing for Active and Standby (Idle) Modes (Synchronous ODT timings)

Notes

1. Synchronous ODT timings apply for Active Mode

and Standby Mode with CKE HIGH and for the

“Fast Exit” Active Power Down Mode (MRS bit A12

to turn on. ODT turn on time max. (t_AON.MAX) is when

the ODT resistance is fully on. Both are measured

from t_A

.

OND

set to “0”). In all these modes the on-die DLL is 3. ODT turn off time min. (t_AOF.MIN) is when the device

enabled.

starts to turn off the ODT resistance.ODT turn off

2. ODT turn-on time (t_AON.MIN) is when the device

leaves high impedance and ODT resistance begins

time max. (t_AOF.MAX) is when the bus is in high

impedance. Both are measured from t_AOFD

.

T

1

T

3

T

4

T

5

T

6

T

7

T

8

T

0

T

2

CK, CK

CKE

"low"

t

IS

ODT

DQ

t

IS

tAOFPDmax

tAOFPDmin

Rtt

tAONPD,min

tAONPD,max

ODT02

Figure 14 ODT Timing for Precharge Power-Down and Active Power-Down Mode (with slow exit)

(Asynchronous ODT timings)

Note:Asynchronous ODT timings apply for Precharge Power-Down Mode and “Slow Exit” Active Power Down

Mode (MRS bit A12 set to “1”), where the on-die DLL is disabled in this mode of operation.

Data Sheet

34

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

ODT timing mode switch

When entering the Power Down Modes “Slow Exit” Active Power Down and Precharge Power Down two additional

timing parameters (t_ANPDand t_AXPD) define if synchronous or asynchronous ODT timings have to be applied.

Mode entry

As long as the timing parameter t_ANPD.MINis satisfied can be applied. If t_ANPD.MINis not satisfied,

when ODT is turned on or off before entering these asynchronous timing parameters apply.

power-down modes, synchronous timing parameters

T-5

T-4

T-3

T-2

T-1

T0

T1

T2

CK, CK

CKE

tANPD (3 tck)

t_IS

ODT turn-off, tANPD >= 3 tck :

t

IS

ODT

Synchronous

timings apply

RTT

tAOFD

ODT turn-off, tANPD <3 tck :

ODT

Asynchronous

timings apply

RTT

tAOFPDmax

ODT turn-on, tANPD >= 3 tck :

t_IS

tAOND

ODT

Synchronous

timings apply

RTT

t

IS

ODT turn-on, tANPD < 3 tck :

tAONPDmax

Asynchronous

timings apply

ODT

RTT

ODT03

Figure 15 ODT Mode Entry Timing Diagram

Data Sheet

35

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

Mode exit

As long as the timing parameter t_AXPD.MINis satisfied applied. If t_AXPD.MINis not satisfied, asynchronous timing

when ODT is turned on or off after exiting these power- parameters apply.

down modes, synchronous timing parameters can be

T0

T1

T5

T6

T7

T8

T9

T10

CK,

CK

t_IS

tAXPD

CKE

t_IS

ODT turn-off, tAXPD >= tAXPDmin:

ODT

Synchronous

timings apply

Rtt

tAOFD

ODT turn-off, tAXPD < tAXPDmin:

t_IS

ODT

Asynchronous

timings apply

Rtt

tAOFPDmax

ODT turn-on, tAXPD >= tAXPDmin:

Synchronous

timings apply

t_IS

ODT

Rtt

tAOND

t_IS

ODT turn-on, tAXPD < tAXPDmin:

ODT

Asynchronous

timings apply

Rtt

tAONPDmax

ODT04

Figure 16 ODT Mode Exit Timing Diagram

Data Sheet

36

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.5

Bank Activate Command

The Bank Activate command is issued by holding CAS latency must be programmed into the device to delay

and WE HIGH with CS and RAS LOW at the rising edge the R/W command which is internally issued to the

of the clock. The bank addresses BA[1:0] are used to device. The additive latency value must be chosen to

select the desired bank. The row addresses A0 through assure t_RCD.MINis satisfied. Additive latencies of 0, 1, 2,

A12 are used to determine which row to activate in the 3 and 4 are supported. Once a bank has been activated

selected bank for ×4 and ×8 organized components. it must be precharged before another Bank Activate

For ×16 components row addresses A0 through A12 command can be applied to the same bank. The bank

have to be applied. The Bank Activate command must active and precharge times are defined as t_RASand t_RP,

be applied before any Read or Write operation can be respectively. The minimum time interval between

executed. Immediately after the bank active command, successive Bank Activate commands to the same bank

the DDR2 SDRAM can accept a read or write command is determined by t_RC. The minimum time interval

(with or without Auto-Precharge) on the following clock between Bank Active commands to different banks is

cycle. If a R/W command is issued to a bank that has t_RRD

.

not satisfied the t_RCD.MINspecification, then additive

T0

T1

T2

T3

T4

Tn

Tn+1

Tn+2

Tn+3

CK, CK

Internal RAS-CAS delay tRCDmin.

Bank A

Row Addr.

Bank A

Col. Addr.

Bank B

Row Addr.

Bank B

Col. Addr.

Bank A

Addr.

Bank B

Addr.

Bank A

Row Addr.

NOP

Address

Bank A to Bank B delay tRRD.

additive latency AL=2

Read A

Begins

Posted CAS

Bank A

Activate Read A

Posted CAS

Read B

Bank B

Activate

Bank A

Precharge

Bank B Bank A

Precharge Activate

NOP

Command

tRAS Row Active Time (Bank A)

tCCD

tRP Row Precharge Time (Bank A)

tRC Row Cycle Time (Bank A)

ACT

Figure 17 Bank Activate Command Cycle: t_RCD= 3, AL = 2, t_RP= 3, t_RRD= 2

Data Sheet

37

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.6

Read and Write Commands and Access Modes

After a bank has been activated, a read or write cycle Command (CA[11, 9:0]). The second, third and fourth

can be executed. This is accomplished by setting RAS access will also occur within this segment, however,

HIGH, CS and CAS LOW at the clock’s rising edge. WE the burst order is a function of the starting address, and

must also be defined at this time to determine whether the burst sequence.

the access cycle is a read operation (WE HIGH) or a

write operation (WE LOW). The DDR2 SDRAM

page length of 512 is divided into 64 uniquely

provides a wide variety of fast access modes. A single

In case of a 8-bit burst operation (burst length = 8) the

addressable segments (8-bits × 16 I/O each). The 8-bit

burst operation will occur entirely within one of the 64

Read or Write Command will initiate a serial read or

write operation on successive clock cycles at data rates

segments (defined by CA[7:0]) beginning with the

of up to 533 Mb/sec/pin for main memory. The

column address supplied to the device during the Read

boundary of the burst cycle is restricted to specific

or Write Command (CA[11, 9:0]).

segments of the page length.

A new burst access must not interrupt the previous 4 bit

burst operation in case of BL = 4 setting. Therefore the

minimum CAS to CAS delay (t_CCD) is a minimum of 2

clocks for read or write cycles.

For example, the 16Mbit × 16 chip has a page size of

1024 kByte which corresponds to a page length of 512

bits (defined by CA[11, 9:0]).

In case of a 4-bit burst operation (burst length = 4) the

For 8 bit burst operation (BL = 8) the minimum CAS to

page length of 512 is divided into 128 uniquely

CAS delay (t_CCD) is 4 clocks for read or write cycles.

addressable segments (4-bits × 16 I/O each). The 4-bit

Burst interruption is allowed with 8 bit burst operation.

burst operation will occur entirely within one of the 128

For details see Chapter 2.6.6.

segments (defined by CA[8:0]) starting with the column

address supplied to the device during the Read or Write

T0

T1

T2

T3

T4

T5

T6

T7

T12

CK, C K

CM D

N O P

tCCD

N O P

R E A D

B

N O P

R E A D

C

R E A D A

N O P

tCCD

DQ S,

DQ S

Dout A0 Dout A1

Dout A2 Dout A3 Dout B0 Dout B1

Dout B2 Dout B3 Dout C0 Dout C1

Dout C2 Dout C3

DQ

RB

Figure 18 Read Burst Timing Example: (CL = 3, AL = 0, RL = 3, BL = 4)

2.6.1

Posted CAS

Posted CAS operation is supported to make command latency (CL). Therefore if a user chooses to issue a

and data bus efficient for sustainable bandwidths in Read/Write command before the t_RCD.MIN, then AL

DDR2 SDRAM. In this operation, the DDR2 SDRAM greater than 0 must be written into the EMR(1). The

allows a Read or Write command to be issued Write Latency (WL) is always defined as RL - 1 (Read

immediately after the bank activate command (or any Latency -1) where Read Latency is defined as the sum

time during the RAS to CAS delay time, t_RCDperiod). of Additive Latency plus CAS latency (RL=AL+CL). If a

The command is held for the time of the Additive user chooses to issue a Read command after the

Latency (AL) before it is issued inside the device. The t_RCD.MINperiod, the Read Latency is also defined as

Read Latency (RL) is the sum of AL and the CAS RL = AL + CL.

Data Sheet

38

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

1

0

2

3

4

5

6

7

8

9

10 11

CK, CK

WL = RL -1 = 4

Activate Read

Bank A Bank A

Write

Bank A

CMD

AL = 2

CL = 3

DQS,

DQS

tRCD

RL = AL + CL = 5

DQ

Dout0Dout1 Dout2Dout3

Din0 Din1 Din2 Din3

PostCAS

Figure 19 Activate to Read Timing Example: Read followed by a write to the same bank, Activate to Read

delay < t_RCD.MIN: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4

1

0

2

3

4

5

6

7

8

9

10 11 12

CK, CK

WL = RL -1 = 4

Write

Bank A

Activate Read

Bank A Bank A

CMD

AL = 2

CL = 3

DQS,

DQS

tRCD

RL = AL + CL = 5

DQ

Dout0 Dout1Dout2 Dout3 Dout4 Dout5 Dout6 Dout7

Din0 Din1 Din2 Din3

PostCAS3

Figure 20 Read to Write Timing Example: Read followed by a write to the same bank, Activate to Read

delay < t_RCD.MIN: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8

0

1

2

3

4

5

6

7

8

9

10

11

CK, CK

CMD

AL = 0

Activate

Bank A

Read

Bank A

Write

Bank A

CL = 3

WL = RL -1 = 2

DQS,

DQS

tRCD

RL = AL + CL = 3

DQ

Dout0

Dout1

Dout2

Dout3

Din0

Din1

Din2

Din3

PostCAS2

Figure 21 Read to Write Timing Example: Read followed by a write to the same bank, Activate to Read

delay = t_RCD.MIN: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4

Data Sheet

39

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

1

0

2

3

4

5

6

7

8

9

10 11 12 13

CK, CK

WL = 3

Write

Bank A

Activate

Bank A

Read

Bank A

CMD

tRCD > tRCDmin.

DQS,

DQS

RL = 4

DQ

PostCAS5

Figure 22 Read to Write Timing Example: Read followed by a write to the same bank, Activate to Read

delay > t_RCD.MIN: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4

2.6.2

Burst Mode Operation

Burst mode operation is used to provide a constant flow the MR. The burst type, either sequential or

of data to memory locations (write cycle), or from interleaved, is programmable and defined by the

memory locations (read cycle). The parameters that address bit 3 (A3) of the MR. Seamless burst read or

define how the burst mode will operate are burst write operations are supported. Interruption of a burst

sequence and burst length. The DDR2 SDRAM read or write operation is prohibited, when burst length

supports 4 bit and 8 bit burst modes only. For 8 bit burst = 4 is programmed. For burst interruption of a read or

mode, full interleave address ordering is supported, write burst when burst length = 8 is used, see the

however, sequential address ordering is nibble based Chapter 2.6.6. A Burst Stop command is not supported

for ease of implementation. The burst length is on DDR2 SDRAM devices.

programmable and defined by the addresses A[2:0] of

Table 11

Burst Length and Sequence

Burst Length

Starting Address

(A2 A1 A0)

Sequential Addressing

(decimal)

Interleave Addressing

(decimal)

4

0 0 0

0 0 1

0 1 0

0 1 1

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

8

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

Notes

1. Page size for all 256 Mbit components is 1 kByte

2. Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR or DDR

components

Data Sheet

40

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.6.3

Read Command

The Read command is initiated by having CS and CAS onto the data bus. The first bit of the burst is

LOW while holding RAS and WE HIGH at the rising synchronized with the rising edge of the data strobe

edge of the clock. The address inputs determine the (DQS). Each subsequent data-out appears on the DQ

starting column address for the burst. The delay from pin in phase with the DQS signal in a source

the start of the command until the data from the first cell synchronous manner. The RL is equal to an additive

appears on the outputs is equal to the value of the read latency (AL) plus CAS latency (CL). The CL is defined

latency (RL). The data strobe output (DQS) is driven by the Mode Register Set (MRS). The AL is defined by

LOW one clock cycle before valid data (DQ) is driven the Extended Mode Register Set (EMRS(1)).

t

CK

CH

CL

CLK

CLK, CLK

t

DQS

DQSCK

t

AC

DQS,

DQS

t

RPST

Dout

t

RPRE

t

HZ

LZ

DQ

Dout

t

DQSQmax

t

DQSQmax

t

QH

DO-Read

Figure 23 Basic Read Timing Diagram

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Posted CAS

READ A

NOP

<= t DQSCK

DQS,

DQS

AL = 2

CL = 3

RL = 5

DQ

Dout A0

Dout A1

Dout A2

Dout A3

BRead523

Figure 24 Burst Operation Example 1: RL = 5 (AL = 2, CL = 3, BL = 4)

Data Sheet

41

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, C K

N O P

R E A D A

N O P

CMD

<= tD Q S C K

DQ S,

DQ S

C L =

R L =

3

DQ's

Dout A0 Dout A1

Dout A2 Dout A3

Dout A4 Dout A5

Dout A6 Dout A7

BRead303

Figure 25 Read Operation Example 2: RL = 3 (AL = 0, CL = 3, BL = 8)

T0

T1

T3

T4

T5

T6

T7

T8

T9

CK, C K

CM D

P osted C A S

W R ITE A

P osted C A S

R E A D A

N O P

BL/2 + 2

DQ S,

DQ S

WL = RL - 1 = 4

RL = 5

DQ

Dout A0 Dout A1

Dout A2 Dout A3

Din A0

Din A1

Din A2

Din A3

BRBW514

Figure 26 Read followed by Write Example: RL = 5, WL = (RL-1) = 4, BL = 4

The minimum time from the read command to the write command is defined by a read-to-write turn-around time,

which is BL/2 + 2 clocks.

Data Sheet

42

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Posted CAS

READ B

Posted CAS

READ A

NOP

DQS,

DQS

AL = 2

CL = 3

RL = 5

DQ

Dout A0

Dout A1

Dout A2

Dout A3

Dout B0

Dout B1

Dout B2

Dout B3

SBR523

Figure 27 Seamless Read Operation Example 1: RL = 5, AL = 2, CL = 3, BL = 4

The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This

operation is allowed regardless of same or different banks as long as the banks are activated.

T9

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Posted CAS

READ A

Posted CAS

READ B

NOP

DQS,

DQS

CL = 3

RL = 3

DQ

Dout A0

Dout A1

Dout A2

Dout A3

Dout A4

Dout A5

Dout A6

Dout A7

Dout B0

Dout B1

Dout B2

Dout B3

Dout B4

SBR_BL8

Figure 28 Seamless Read Operation Example 2: RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)

The seamless, non interrupting 8-bit read operation is supported by enabling a read command at every BL/2

number of clocks. This operation is allowed regardless of same or different banks as long as the banks are

activated.

Data Sheet

43

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.6.4

Write Command

The Write command is initiated by having CS, CAS and successive edges of the DQS until the burst length is

WE LOW while holding RAS HIGH at the rising edge of completed. When the burst has finished, any additional

the clock. The address inputs determine the starting data supplied to the DQ pins will be ignored. The DQ

column address. Write latency (WL) is defined by a signal is ignored after the burst write operation is

read latency (RL) minus one and is equal to (AL + CL – complete. The time from the completion of the burst

1). A data strobe signal (DQS) has to be driven LOW write to bank precharge is named “write recovery time”

(preamble) a time t_WPREprior to the WL. The first data (t_WR) and is the time needed to store the write data into

bit of the burst cycle must be applied to the DQ pins at the memory array. t_WRis an analog timing parameter

the first rising edge of the DQS following the preamble. (see Chapter 5) and is not the programmed value for

The t_DQSSspecification must be satisfied for write WR in the MRS.

cycles. The subsequent burst bit data are issued on

t _DQSH

DQS

tDQSL

DQS,

DQS

t

t WPRE

WPST

Din

t

DS

t _DH

Figure 29 Basic Write Timing

T0

T1

T2

T3

T4

T5

T6

T7

T9

CK, CK

CMD

Posted CAS

WRITE A

NOP

Precharge

<= t DQSS

Completion of

the Burst Write

DQS,

DQS

tWR

WL = RL-1 = 4

DQ

DIN A0

DIN A1 DIN A2 DIN A3

BW543

Figure 30 Write Operation Example 1: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4

Data Sheet

44

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T9

CK, CK

CMD

Bank A

Activate

Posted CAS

WRITE A

NOP

Precharge

NOP

Completion of

the Burst Write

<= t DQSS

DQS,

DQS

tRP

tWR

WL = RL-1 = 2

DQ

DIN A0

DIN A1 DIN A2 DIN A3

BW322

Figure 31 Write Operation Example 2: RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK, CK

CMD

Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6

Posted CAS

READ A

NOP

DQS,

DQS

CL=3

AL=2

tWTR

WL = RL - 1 = 4

DQ

DIN A0 DIN A1 DIN A2 DIN A3

RL=5

BWBR

Figure 32 Write followed by Read Example: RL = 5 (AL = 2, CL = 3), WL = 4, t_WTR= 2, BL = 4

The minimum number of clocks from the write command to the read command is (CL - 1) +BL/2 + t_WTR, where t_WTR

is the write-to-read turn-around time t_WTRexpressed in clock cycles. The t_WTRis not a write recovery time (t_WR) but

the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.

Data Sheet

45

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Posted CAS

WRITE A

Posted CAS

WRITE B

NOP

DQS,

DQS

WL = RL - 1 = 4

DQ

DIN B0

DIN A0

DIN B1 DIN B2 DIN B3

DIN A1 DIN A2 DIN A3

SBR

Figure 33 Seamless Write Operation Example 1: RL = 5, WL = 4, BL = 4

The seamless write operation is supported by enabling a write command every BL/2 number of clocks. This

operation is allowed regardless of same or different banks as long as the banks are activated.

T0

T1

T2

T3

T4

T5

T6

T7

T8

, CK

D

NOP

WRITE A

NOP

WRITE B

S,

S

WL = RL - 1 = 2

Q

DIN B4

DIN B5 DIN B6 DIN B7

DIN B0

DIN B1 DIN B2 DIN B3

DIN A0

DIN A1 DIN A2 DIN A3

DIN A4

DIN A5 DIN A6 DIN A7

SBW_BL8

Figure 34 Seamless Write Operation Example 2: RL = 3, WL = 2, BL = 8, non interrupting

The seamless write operation is supported by enabling a write command at every BL/2 number of clocks. This

operation is allowed regardless of same or different banks as long as the banks are activated.

Data Sheet

46

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.6.5

Write Data Mask

One write data mask input (DM) for ×4 and ×8 insure matched system timing. Data mask is not used

components and two write data mask inputs (LDM, during read cycles. If DM is HIGH during a write burst

UDM) for ×16 components are supported on DDR2 coincident with the write data, the write data bit is not

SDRAM’s, consistent with the implementation on DDR written to the memory. For ×8 components the DM

SDRAM’s. It has identical timings on write operations function is disabled, when RDQS / RDQS are enabled

as the data bits, and though used in a uni-directional by EMRS(1).

manner, is internally loaded identically to data bits to

t

DQSL

DQS

DQSH

DQS,

DQS

t

WPRE

Din

WPST

DQ

DM

Din

t

DS

DH

don't care

Figure 35 Write Data Mask Timing

T0

T1

T2

T3

T4

T5

T6

T7

T9

CK, C K

CM D

B ank A

A ctivate

N O P

W R ITE A

N O P

P recharge

N O P

<= tDQSS

DQ S,

DQ S

WL = RL-1 = 2

tR P

tW R

DQ

DM

DIN A0

DIN A1 DIN A2 DIN A3

DM

Figure 36 Write Operation with Data Mask Example: RL = 3 (AL = 0, CL = 3), WL = 2, t_WR= 3, BL = 4

Data Sheet

47

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.6.6

Burst Interruption

Interruption of a read or write burst is prohibited for 6. Read or Write burst with Auto-Precharge enabled is

burst length of 4 and only allowed for burst length of 8

under the following conditions:

not allowed to be interrupted.

7. Read burst interruption is allowed by a Read with

Auto-Precharge command.

8. Write burst interruption is allowed by a Write with

Auto-Precharge command.

1. A Read Burst can only be interrupted by another

Read command. Read burst interruption by a Write

or Precharge Command is prohibited.

9. All command timings are referenced to burst length

set in the mode register. They are not referenced to

the actual burst. For example, Minimum Read to

Precharge timing is AL + BL/2 where BL is the burst

length set in the mode register and not the actual

burst (which is shorter because of interrupt).

Minimum Write to Precharge timing is WL + BL/ 2 +

2. A Write Burst can only be interrupted by another

Write command. Write burst interruption by a Read

or Precharge Command is prohibited.

3. Read burst interrupt must occur exactly two clocks

after the previous Read command. Any other Read

burst interrupt timings are prohibited.

4. Write burst interrupt must occur exactly two clocks

after the previous Write command. Any other Read

burst interrupt timings are prohibited.

5. Read or Write burst interruption is allowed to any

bank inside the DDR2 SDRAM.

t

_WR, where t_WRstarts with the rising clock after the

un-interrupted burst end and not from the end of the

actual burst end.

T0

T1

T2

T3

T4

T5

T6

T7

T8

C K, CK

CM D

N O P

R E A D

B

N O P

R E A D

A

N O P

DQ S,

DQ S

D Q

Dout A0 Dout A1

Dout A2 Dout A3 Dout B0 Dout B1

Dout B2 Dout B3 Dout B4 Dout B5

Dout B6 Dout B7

RBI

Figure 37 Read Interrupt Timing Example 1: (CL = 3, AL = 0, RL = 3, BL = 8)

Data Sheet

48

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CM D

N O P

W R IT E

A

N O P

W R ITE

B

N O P

DQ S,

DQ S

D Q

Din A0

Din A1

Din A2

Din A3

Din B0

Din B1

Din B2

Din B3

Dout B4 Din B5

Din B6

Din B7

WBI

Figure 38 Write Interrupt Timing Example 2: (CL = 3, AL = 0, WL = 2, BL = 8)

2.7

Precharge Command

The Precharge Command is used to precharge or close The Pre-charge Command can be used to precharge

a bank that has been activated. The Precharge each bank independently or all banks simultaneously. 3

Command is triggered when CS, RAS and WE are address bits A10, BA[1:0] are used to define which

LOW and CAS is HIGH at the rising edge of the clock. bank to precharge when the command is issued.

Table 12

Bank Selection for Precharge by Address Bits

A10

0

BA1

BA0

Precharge Bank(s)

Bank 0 only

Bank 1 only

Bank 2 only

Bank 3 only

all banks

0

1

0

1

0

1

Don’t Care

Note:The bank address assignment is the same for activating and precharging a specific bank.

Data Sheet

49

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.7.1

Read Operation Followed by a Precharge

The following rules apply as long as the t_RTPtiming clocks” after a Read Command, as long as the

parameter - Internal Read to Precharge Command minimum t_RAStiming is satisfied.

delay time - is less or equal two clocks, which is the

case for operating frequencies less or equal 266 Mhz

same bank if the following two conditions are satisfied

(DDR2 400 and 533 speed sorts).

A new bank active command may be issued to the

simultaneously:

Minimum Read to Precharge command spacing to the

same bank = AL + BL/2 clocks. For the earliest possible

precharge, the Precharge command may be issued on

the rising edge which is “Additive Latency (AL) + BL/2

1. The RAS precharge time (t_RP) has been satisfied

from the clock at which the precharge begins.

2. The RAS cycle time (t_RC.MIN) from the previous bank

activation has been satisfied.

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank A

Activate

Posted CAS

READ A

NOP

AL + BL/2 clks

NOP

Precharge

NOP

tRP

DQS,

DQS

AL = 1

CL = 3

RL = 4

DQ

Dout A0

Dout A1

Dout A2

Dout A3

>=tRAS

CL = 3

>=tRC

>=tRTP

BR-P413

Figure 39 Read Operation Followed by Precharge Example 1:

RL = 4 (AL = 1, CL = 3), BL = 4, t_RTP≤ 2 clocks

Data Sheet

50

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Posted CAS

READ A

Bank A

Activate

NOP

AL + BL/2 clks

NOP

Precharge

NOP

tRP

DQS,

DQS

AL = 1

CL = 3

RL = 4

DQ

Dout A0

Dout A1

Dout A2

Dout A3

Dout A4

Dout A5

Dout A6

Dout A7

>=tRAS

CL = 3

>=tRC

>=tRTP

BR-P413(8)

first 4-bit prefetch

second 4-bit prefetch

Figure 40 Read Operation Followed by Precharge Example 2:

RL = 4 (AL = 1, CL = 3), BL = 8, t_RTP≤ 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank A

Activate

Posted CAS

READ A

NOP

tRP

NOP

Precharge

AL + BL/2 clks

DQS,

DQS

AL = 2

RL = 5

CL = 3

DQ

Dout A0

Dout A1

Dout A2

Dout A3

>=tRAS

CL = 3

>=tRC

>=tRTP

BR-P523

Figure 41 Read Operation Followed by Precharge Example 3:

RL = 5 (AL = 2, CL = 3), BL = 4, t_RTP≤ 2 clocks

Data Sheet

51

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Bank A

Activate

Posted CAS

READ A

Precharge

A

NOP

tRP

NOP

AL + BL/2 clocks

DQS,

DQS

AL = 2

RL = 6

CL = 4

DQ

Dout A0

Dout A1

Dout A2

Dout A3

>=tRAS

CL = 4

>=tRC

>=tRTP

BR-P624

Figure 42 Read Operation Followed by Precharge Example 4:

RL = 6, (AL = 2, CL = 4), BL = 4, t_RTP≤ 2 clocks

2.7.2

Write followed by Precharge

Minimum Write to Precharge command spacing to the to the Precharge command. No Precharge command

same bank = WL + BL/2 + t_WR. For write cycles, a delay should be issued prior to the t_WRdelay, as DDR2

must be satisfied from the completion of the last burst SDRAM does not support any burst interrupt by a

write cycle until the Precharge command can be Precharge command. t_WRis an analog timing

issued. This delay is known as a write recovery time parameter (see Chapter 7) and is not the programmed

(t_WR) referenced from the completion of the burst write value WR in the MR.

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CMD

Precharge

A

Posted CAS

WRITE A

NOP

Completion of

the Burst Write

DQS,

DQS

tWR

WL = 3

DQ

DIN A0

DIN A1 DIN A2 DIN A3

BW-P3

Figure 43 Write followed by Precharge Example 1: WL = (RL - 1) = 3, BL = 4, t_WR= 3

Data Sheet

52

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T9

CK, CK

CMD

Precharge

A

Posted CAS

WRITE A

NOP

Completion of

the Burst Write

DQS,

DQS

tWR

WL = 4

DQ

DIN A0

DIN A1 DIN A2 DIN A3

BW-P4

Figure 44 Write followed by Precharge Example 2: WL = (RL - 1) = 4, BL = 4, t_WR= 3

2.8

Auto-Precharge Operation

Before a new row in an active bank can be opened, the internally on the rising edge which is CAS Latency (CL)

active bank must be precharged using either the Pre- clock cycles before the end of the read burst. Auto-

charge Command or the Auto-Precharge function. Precharge is also implemented for Write Commands.

When a Read or a Write Command is given to the The Precharge operation engaged by the Auto-

DDR2 SDRAM, the CAS timing accepts one extra Precharge command will not begin until the last data of

address, column address A10, to allow the active bank the write burst sequence is properly stored in the

to automatically begin precharge at the earliest memory array. This feature allows the precharge

possible moment during the burst read or write cycle. If operation to be partially or completely hidden during

A10 is LOW when the Read or Write Command is burst read cycles (dependent upon CAS Latency) thus

issued, then normal Read or Write burst operation is improving system performance for random data

executed and the bank remains active at the access. The RAS lockout circuit internally delays the

completion of the burst sequence. If A10 is HIGH when Precharge operation until the array restore operation

the Read or Write Command is issued, then the Auto- has been completed so that the Auto-Precharge

Precharge function is enabled. During Auto-Precharge, command may be issued with any read or write

a Read Command will execute as normal with the command.

exception that the active bank will begin to precharge

2.8.1

Read with Auto-Precharge

If A10 is 1 when a Read Command is issued, the Read becomes AL + t_RTP+ t_RP. For BL = 8 the time from Read

with Auto-Precharge function is engaged. The DDR2 with Auto-Precharge to the next Activate command is

SDRAM starts an Auto-Precharge operation on the AL + 2 + t_RTP+ t_RP. Note that (t_RTP+ t_RP) has to be

rising edge which is (AL + BL/2) cycles later from the rounded up to the next integer value. In any event

Read with AP command if t_RAS.MINand t_RTPare internal precharge does not start earlier than two clocks

satisfied. If t_RAS.MINis not satisfied at the edge, the start after the last 4-bit prefetch.

point of Auto-Precharge operation will be delayed until

A new bank active command may be issued to the

same bank if the following two conditions are satisfied

simultaneously:

t

_RAS,minis satisfied. If t_RTP.MINis not satisfied at the edge,

the start point of Auto-Precharge operation will be

delayed until t_RTP.MINis satisfied.

1. The RAS precharge time (t_RP) has been satisfied

from the clock at which the Auto-Precharge begins.

2. The RAS cycle time (t_RC) from the previous bank

activation has been satisfied.

In case the internal precharge is pushed out by t_RTP, t_RP

starts at the point where the internal precharge

happens (not at the next rising clock edge after this

event). So for BL = 4 the minimum time from Read with

Auto-Precharge to the next Activate command

Data Sheet

53

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, C K

CM D

B ank

A ctivate

P osted C A S

R E A D w /A P

N O P

A10 ="high"

Auto-Precharge Begins

AL + BL/2

DQ S,

DQ S

AL = 2

CL = 3

tRP

RL = 5

DQ

Dout A0 Dout A1

Dout A2 Dout A3

tRAS

tRCmin.

BR-AP5231

Figure 45 Read with Auto-Precharge Example 1, followed by an Activation to the Same Bank (t_RCLimit):

RL = 5 (AL = 2, CL = 3), BL = 4, t_RTP≤ 2 clocks

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, CK

CM D

B ank

A ctivate

P osted C A S

R E A D w /A P

N O P

A10 ="high"

Auto-Precharge Begins

tRAS(min)

DQ S,

DQ S

AL = 2

CL = 3

tRP

RL = 5

DQ

Dout A0 Dout A1

Dout A2 Dout A3

tRC

BR-AP5232

Figure 46 Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank (t_RASLimit):

RL = 5 (AL = 2, CL = 3), BL = 4, t_RTP≤ 2 clocks

Data Sheet

54

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK, C K

CM D

B ank

A ctivate

P osted C A S

R E A D w /A P

N O P

A10 ="high"

AL + BL/2

tRP

Auto-Precharge Begins

DQ S,

DQ S

AL = 1

CL = 3

RL = 4

DQ

Dout A4 Dout A5

Dout A2 Dout A3

Dout A6 Dout A7

Dout A0 Dout A1

>= tRTP

BR-AP413(8)2

second 4-bit prefetch

first 4-bit prefetch

Figure 47 Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank:

RL = 4 (AL = 1, CL = 3), BL = 8, t_RTP≤ 2 clocks

Data Sheet

55

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.8.2

Write with Auto-Precharge

If A10 is HIGH when a Write Command is issued, the 1. The last data-in to bank activate delay time (t_DAL

Write with Auto-Precharge function is engaged. The WR + t_RP) has been satisfied.

DDR2 SDRAM automatically begins precharge 2. The RAS cycle time (t_RC) from the previous bank

=

operation after the completion of the write burst plus the

write recovery time delay (WR), programmed in the

MRS register, as long as t_RASis satisfied. The bank

undergoing Auto-Precharge from the completion of the

write burst may be reactivated if the following two

conditions are satisfied.

activation has been satisfied.

In DDR2 SDRAM’s the write recovery time delay (WR)

has to be programmed into the MRS mode register. As

long as the analog t_WRtiming parameter is not violated,

WR can be programmed between 2 and 6 clock cycles.

Minimum Write to Activate command spacing to the

same bank = WL + BL/2 + t_DAL

.

T0

T1

T2

T3

T4

T5

T6

T7

CK, C K

CM D

W R ITE

w /A P

B ank A

A ctivate

N O P

A10 ="high"

Completion of the Burst Write

Auto-Precharge Begins

DQ S,

DQ S

WR

tRP

WL = RL-1 = 2

tDAL

DQ

DIN A0

DIN A1 DIN A2 DIN A3

tRCmin.

>=tRASmin.

BW-AP223

Figure 48 Write with Auto-Precharge Example 1 (t_RCLimit): WL = 2, t_DAL= 6 (WR = 3, t_RP= 3), BL = 4

T0

T3

T4

T5

T6

T7

T8

T12

T9

CK, C K

CM D

P osted C A S

W R ITE w /A P

B ank A

A ctivate

N O P

Completion of the Burst Write

A10 ="high"

Auto-Precharge Begins

DQ S,

DQ S

tRP

WR

tDAL

WL = RL-1 = 4

DQ

DIN A0

DIN A1 DIN A2 DIN A3

>=tRC

>=tRAS

BW-AP423

Figure 49 Write with Auto-Precharge Example 2 (WR + t_RPLimit): WL = 4, t_DAL= 6 (WR = 3, t_RP= 3), BL = 4

Data Sheet

56

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.8.3

Read or Write to Precharge Command Spacing Summary

The following table summarizes the minimum Write w/AP to the Precharge commands to the same

command delays between Read, Read w/AP, Write, banks and Precharge-All commands.

Table 13

Minimum Command Delays

From Command

To Command

Minimum Delay between “From Unit Note

Command” to “To Command”

1)2)

READ

PRECHARGE (to same banks as

READ)

AL + BL/2 + max(t_RTP, 2) - 2×t_CK

t_CK

1)2)

PRECHARGE-ALL

AL + BL/2 + max(t_RTP, 2) - 2×t_CK

t_CK

READ w/AP

WRITE

PRECHARGE (to same banks as

READ w/AP)

1)2)

2)

PRECHARGE-ALL

AL + BL/2 + max(t_RTP, 2) - 2×t_CK

WL + BL/2 + t_WR

t_CK

PRECHARGE (to same banks as

WRITE)

2)

PRECHARGE-ALL

WL + BL/2 + t_WR

t_CK

WRITE w/AP

PRECHARGE

PRECHARGE (to same banks as

WRITE w/AP)

WL + BL/2 + WR

2)

PRECHARGE-ALL

WL + BL/2 + WR

1

t_CK

PRECHARGE (to same banks as

PRECHARGE)

2)

PRECHARGE-ALL

1

t_CK

PRECHARGE-ALL PRECHARGE

PRECHARGE-ALL

1) RU{t_RTP(ns) / t_CK(ns)} must be used, where RU stands for “Round Up”

2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge-

^{all, issued to that bank. The precharge period is satisfied after}t_RP, depending on the latest precharge command issued to that bank

Data Sheet

57

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.8.4

Concurrent Auto-Precharge

DDR2 devices support the “Concurrent Auto- The minimum delay from a Read or Write command

Precharge” feature. A Read with Auto-Precharge with Auto-Precharge enabled, to a command to a

enabled, or a Write with Auto-Precharge enabled, may different bank, is summarized in Table 14. As defined,

be followed by any command to the other bank, as long the WL = RL - 1 for DDR2 devices which allows the

as that command does not interrupt the read or write command gap and corresponding data gaps to be

data transfer, and all other related limitations (e.g. minimized.

contention between Read data and Write data must be

avoided externally and on the internal data bus).

Table 14

Command Delay Table

From Command To Command (different bank, Minimum Delay with Concurrent Auto- Unit

Note

non-interrupting command)

Read or Read w/AP

Write or Write w/AP

Precharge Support

WRITE w/AP

Read w/AP

(CL -1) + (BL/2) + t_WTR

t_CK

BL/2

1)

Precharge or Activate

Read or Read w/AP

Write or Write w/AP

1

BL/2

BL/2 + 2

1

Precharge or Activate

1) This rule only applies to a selective Precharge command to another bank, a Precharge-All command is illegal

2.9

Refresh

DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval. The necessary refresh can be generated

in one of two ways: by explicit Auto-Refresh commands or by an internally timed Self-Refresh mode.

2.9.1

Auto-Refresh Command

Auto-Refresh is used during normal operation of the external address bus is required once this cycle has

DDR2 SDRAM’s. This command is non persistent, so it started.

must be issued each time a refresh is required. The

When the refresh cycle has completed, all banks of the

refresh addressing is generated by the internal refresh

SDRAM will be in the precharged (idle) state. A delay

controller. This makes the address bits ”don’t care”

between the Auto-Refresh Command and the next

during an Auto-Refresh command. The DDR2 SDRAM

Activate Command or subsequent Auto-Refresh

requires Auto-Refresh cycles at an average periodic

Command must be greater than or equal to the Auto-

interval of t_REFI.MAX

.

Refresh cycle time (t_RFC).

When CS, RAS and CAS are held LOW and WE HIGH To allow for improved efficiency in scheduling and

at the rising edge of the clock, the chip enters the Auto- switching between tasks, some flexibility in the

Refresh mode. All banks of the SDRAM must be absolute refresh interval is provided. A maximum of

precharged and idle for a minimum of the precharge eight Auto-Refresh commands can be posted to any

time (t_RP) before the Auto-Refresh Command can be given DDR2 SDRAM, meaning that the maximum

applied. An internal address counter supplies the absolute interval between any Auto-Refresh command

addresses during the refresh cycle. No control of the and the next Auto-Refresh command is 9 × t_REFI

.

Data Sheet

58

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

CK, CK

"high"

CKE

> = t

RFC

RP

RFC

A U TO

R E FR E S H

A U TO

R E FR E S H

CMD

N O P

A N Y

P recharge

N O P

AR

Figure 50 Auto Refresh Timing

2.9.2

Self-Refresh Command

The Self-Refresh command can be used to retain data, clock after Self-Refresh entry is registered, however,

even if the rest of the system is powered down. When the clock must be restarted and stable before the

in the Self-Refresh mode, the DDR2 SDRAM retains device can exit Self-Refresh operation.

data without external clocking. The DDR2 SDRAM

device has a built-in timer to accommodate Self-

sequence of commands. First, the clock must be stable

Refresh operation. The Self-Refresh Command is

defined by having CS, RAS, CAS and CKE held LOW

with WE HIGH at the rising edge of the clock. The

device must be in idle state and ODT must be turned off

the device to allow for any internal refresh in progress.

before issuing Self Refresh command, by either driving

ODT pin LOW or using EMRS(1) command. Once the

command is registered, CKE must be held LOW to

keep the device in Self-Refresh mode. The DLL is

automatically disabled upon entering Self Refresh and

is automatically enabled upon exiting Self Refresh.

When the DDR2 SDRAM has entered Self-Refresh

The procedure for exiting Self Refresh requires a

prior to CKE going back HIGH. Once Self-Refresh Exit

command is registered, a delay of at least t_XSNRmust

be satisfied before a valid command can be issued to

CKE must remain HIGH for the entire Self-Refresh exit

period t_XSRDfor proper operation. Upon exit from Self

Refresh, the DDR2 SDRAM can be put back into Self

Refresh mode after t_XSNRexpires. NOP or deselect

commands must be registered on each positive clock

edge during the Self-Refresh exit interval t_XSNR. ODT

should be turned off during t_XSNR

.

mode all of the external control signals, except CKE,

are “don’t care”. The DRAM initiates a minimum of one

Auto Refresh command internally within t_CKEperiod

once it enters Self Refresh mode. The clock is internally

disabled during Self-Refresh Operation to save power.

The minimum time that the DDR2 SDRAM must remain

in Self Refresh mode is t_CKE. The user may change the

external clock frequency or halt the external clock one

The use of Self Refresh mode introduces the possibility

that an internally timed refresh event can be missed

when CKE is raised for exit from Self Refresh mode.

Upon exit from Self Refresh, the DDR2 SDRAM

requires a minimum of one extra auto refresh command

before it is put back into Self Refresh Mode.

Data Sheet

59

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T4

T0

T5

Tm

Tr

T1

T2

T3

Tn

CK/CK

CKE

tRP

tis

>=tXSRD

tCKE

tis

tAOFD

>= tXSNR

ODT

CMD

Read

Command

Self Refresh

Entry

Non-Read

Command

NOP

CK/CK may

be halted

CK/CK must

be stable

Figure 51 Self Refresh Timing

Notes

1. Device must be in the “All banks idle” state before 3. t_XSNRhas to be satisfied for any command except a

entering Self Refresh mode. Read or a Read with Auto-Precharge command

2. t_XSRD(≥ 200 t_CK) has to be satisfied for a Read or a 4. Since CKE is an SSTL input, V_REFmust be

Read with Auto-Precharge command. maintained during Self Refresh.

2.10

Power-Down

Power-down is synchronously entered when CKE is For Active Power-down two different power saving

registered LOW, along with NOP or Deselect modes can be selected within the MRS register,

command. CKE is not allowed to go LOW while mode address bit A12. When A12 is set to LOW this mode is

register or extended mode register command time, or referred as “standard active power-down mode” and a

read or write operation is in progress. CKE is allowed to fast power-down exit timing defined by the t_XARDtiming

go LOW while any other operation such as row parameter can be used. When A12 is set to HIGH this

activation, Precharge, Auto-Precharge or Auto-Refresh mode is referred as a power saving “low power active

is in progress, but power-down I_DDspecification will not power-down mode”. This mode takes longer to exit

be applied until finishing those operations.

from the power-down mode and the t_XARDStiming

parameter has to be satisfied.

The DLL should be in a locked state when power-down

is entered. Otherwise DLL should be reset after exiting Entering power-down deactivates the input and output

power-down mode for proper read operation. DRAM buffers, excluding CK, CK, ODT and CKE. Also the DLL

design guarantees it’s DLL in a locked state with any is disabled upon entering Precharge Power-down or

CKE intensive operations as long as DRAM controller slow exit active power-down, but the DLL is kept

complies with DRAM specifications.

enabled during fast exit active power-down. In power-

down mode, CKE LOW and a stable clock signal must

be maintained at the inputs of the DDR2 SDRAM, and

all other input signals are “Don’t Care”. Power-down

duration is limited by 9 times t_REFIof the device.

If power-down occurs when all banks are precharged,

this mode is referred to as Precharge Power-down; if

power-down occurs when there is a row active in any

bank, this mode is referred to as Active Power-down.

Data Sheet

60

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

Power-Down Entry

Active Power-down mode can be entered after an Active Power-down mode entry is prohibited as long as

Activate command. Precharge Power-down mode can a Write Burst and the internal write recovery is in

be entered after a Precharge, Precharge-All or internal progress. In case of a write command, active power-

precharge command. It is also allowed to enter power- down mode entry is allowed when WL + BL/2 + t_WTRis

mode after an Auto-Refresh command or MRS / satisfied.

EMRS(1) command when t_MRDis satisfied.

In case of a write command with Auto-Precharge,

Active Power-down mode entry is prohibited as long as Power-down mode entry is allowed after the internal

a Read Burst is in progress, meaning CKE should be precharge command has been executed, which is WL

kept HIGH until the burst operation is finished. + BL/2 + WR starting from the write with Auto-

Therefore Active Power-Down mode entry after a Read Precharge command. In this case the DDR2 SDRAM

or Read with Auto-Precharge command is allowed after enters the Precharge Power-down mode.

RL + BL/2 is satisfied.

Power-Down Exit

The power-down state is synchronously exited when applied with power-down exit latency, t_XP, t_XARDor

CKE is registered HIGH (along with a NOP or Deselect

t_XARDS, after CKE goes HIGH. Power-down exit

command). A valid, executable command can be latencies are defined in Table 42.

T0

T1

T2

Tn

Tn+1

Tn+2

CK, CK

V alid

C om m and

CM D

CKE

N O P

Activate

N O P

tIS

tXARD or

tXARDS *)

Act.PD 0

Active

Power-Down

Exit

Active

Power-Down

Entry

Figure 52 Active Power-Down Mode Entry and Exit after an Activate Command

Note:Active Power-Down mode exit timing t_XARD(“fast exit”) or t_XARDS(“slow exit”) depends on the programmed

state in the MR, address bit A12.

Data Sheet

61

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

Tn

Tn+1

T0

T1

T2

T3

T4

T5

T6

T7

T8

Tn+2

CK, CK

V alid

C om m and

R E A D

R EA D w /A P

CM D

C KE

N O P

tIS

RL + BL/2

tIS

D Q S,

D Q S

CL = 3

RL = 4

tXARD or

tXARDS *)

AL = 1

DQ

Dout A0 Dout A1

Dout A2 Dout A3

Active

Power-Down

Entry

Active

Power-Down

Exit

Act.PD 1

Figure 53 Active Power-Down Mode Entry and Exit Example after a Read Command:

RL = 4 (AL = 1, CL =3), BL = 4

Note:Active Power-Down mode exit timing t_XARD(“fast exit”) or t_XARDS(“slow exit”) depends on the programmed

state in the MR, address bit A12.

Tn

Tn+1

T0

T1

T2

T3

T4

T5

T6

T7

Tn+2

C K, CK

V alid

C om m and

CM D

C KE

N O P

W RITE

N O P

tIS

WL + BL/2 + tWTR

tIS

D Q S,

D Q S

WL = RL - 1 = 2

tWTR

tXARD or

tXARDS *)

D Q

DIN A0

DIN A1 DIN A2 DIN A3

Active

Power-Down

Entry

Active

Power-Down

Exit

Act.PD 2

Figure 54 Active Power-Down Mode Entry and Exit Example after a Write Command:

WL = 2, t_WTR= 2, BL = 4

Note:Active Power-Down mode exit timing t_XARD(“fast exit”) or t_XARDS(“slow exit”) depends on the programmed

state in the MR, address bit A12.

Data Sheet

62

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

Tn

Tn+1

T0

T1

T2

T3

T4

T5

T6

T7

Tn+2

CK, CK

V alid

C om m and

W R ITE

w /A P

C M D

CKE

N O P

WL + BL/2 + WR

tIS

D Q S,

D Q S

WL = RL - 1 = 2

WR

tXARD or

tXARDS *)

D Q

DIN A0

DIN A1 DIN A2 DIN A3

Active

Power-Down

Entry

Active

Power-Down

Exit

Act.PD 3

Figure 55 Active Power-Down Mode Entry and Exit Example after a Write Command with AP:

WL = 2, WR = 3, BL = 4

Note:Active Power-Down mode exit timing t_XARD(“fast exit”) or t_XARDS(“slow exit”) depends on the programmed

state in the MR, address bit A12. WR is the programmed value in the MRS mode register.

T0

T1

T2

T3

Tn

Tn+1

Tn+2

CK, CK

Valid

Command

CMD

CKE

NOP

Precharge

NOP

tIS

tXP

tRP

Precharge

Power-Down

Entry

Precharge

Power-Down

Exit

Figure 56 Precharge Power Down Mode Entry and Exit

Note:"Precharge" may be an external command or an internal precharge following Write with AP.

Data Sheet

63

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

T0

T1

T2

T3

T4

Tn

CK, CK

tRFC

Valid

Command

Auto

Refresh

CM D

CKE

tXP

tis

CKE can go low one clock after an Auto-Refresh command

ARPD

When tRFC expires the DRAM is in Precharge Power-Down Mode

Figure 57 Auto-Refresh command to Power-Down entry

T0

T1

T2

T3

T4

T5

T6

T7

CK, CK

MRS or

EMRS

CM D

CKE

t

MRD

Enters Precharge Power-Down Mode

MRS_PD

Figure 58 MRS, EMRS command to Power-Down entry

Data Sheet

64

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.11

Other Commands

2.11.1

No Operation Command

The No Operation Command (NOP) should be used in registered when CS is LOW with RAS, CAS, and WE

cases when the SDRAM is in a idle or a wait state. The held HIGH at the rising edge of the clock. A No

purpose of the No Operation Command is to prevent Operation Command will not terminate a previous

the SDRAM from registering any unwanted commands operation that is still executing, such as a burst read or

between operations. A No Operation Command is write cycle.

2.11.2

Deselect Command

The Deselect Command performs the same function as when CS is brought HIGH, the RAS, CAS, and WE

a No Operation Command. Deselect Command occurs signals become don’t care.

2.12

Input Clock Frequency Change

During operation the DRAM input clock frequency can cycles after t_RPand t_AOFDhave been satisfied the input

be changed under the following conditions:

clock frequency can be changed. A stable new clock

frequency has to be provided, before CKE can be

changed to a HIGH logic level again. After t_XPhas been

satisfied a DLL RESET command via EMRS(1) has to

be issued. During the following DLL re-lock period of

200 clock cycles, ODT must remain off. After the DLL-

re-lock period the DRAM is ready to operate with the

new clock frequency.

•

During Self-Refresh operation

DRAM is in Precharge Power-down mode and ODT

is completely turned off.

In the Precharge Power-down mode the DDR2-

SDRAM has to be in Precharged Power-down mode

and idle. ODT must be already turned off and CKE must

be at a logic LOW state. After a minimum of two clock

Ty+2

Tz

Ty+3

T0

T1

T2

T3

T4

Tx

Tx+1

Ty

Ty+1

CK, C K

D LL

R E SET

Valid

C om m and

C M D

CKE

N O P

tRP

tAOFD

tXP

200 clocks

Minimum 2 clocks

required before

changing the frequency

Frequency Change

occurs here

Stable new clock

before power-down exit

ODT is off during

DLL RESET

Frequ.Ch.

Figure 59 Input Frequency Change Example during Precharge Power-Down mode

Data Sheet

65

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Functional Description

2.13

Asynchronous CKE LOW Reset Event

In a given system, Asynchronous Reset event can occurs, the memory controller must satisfy a time delay

occur at any time without prior knowledge. In this (t_DELAY) before turning off the clocks. Stable clocks must

situation, memory controller is forced to drop CKE exist at the input of DRAM before CKE is raised HIGH

asynchronously LOW, immediately interrupting any again. The DRAM must be fully re-initialized as

valid operation. DRAM requires CKE to be maintained described the initialization sequence (Chapter 2.2.1,

HIGH for all valid operations as defined in this data step 4 through 13). DRAM is ready for normal operation

sheet. If CKE asynchronously drops LOW during any after the initialization sequence. See Chapter 7 for

valid operation, the DRAM is not guaranteed to

preserve the contents of the memory array. If this event

t_DELAYspecification.

stable clocks

CK, CK

tdelay

CKE

CKE drops low due to an

asynchronous reset event

Clocks can be turned off after

this point

Figure 60 Asynchronous Low Reset Event

Data Sheet

66

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Truth Tables

3

Truth Tables

Command Truth Table

CKE

Table 15

Function

CS RAS CAS WE BA0 A[12:11] A10 A[9:0] Note¹⁾²⁾³⁾

BA1

Previous Current

Cycle

4)5)

(Extended) Mode

Register Set

H

L

BA

OP Code

4)

Auto-Refresh

H

L

H

L

H

L

H

X

H

L

X

4)6)

4)6)7)

Self-Refresh Entry

Self-Refresh Exit

L

H

X

H

L

X

H

L

4)5)

Single Bank Precharge H

H

BA

X

L

X

4)

Precharge all Banks

Bank Activate

Write

H

L

H

4)5)

L

H

L

BA

Row Address

4)5)8)

H

Column

L

Column

Write with Auto-

Precharge

L

H

4)5)8)

Read

H

L

H

L

H

BA

Column

L

Column

Read with Auto-

Precharge

H

4)

No Operation

H

X

L

H

X

H

X

H

X

H

X

H

X

H

X

H

X

4)

Device Deselect

Power Down Entry

H

L

4)9)

Power Down Exit

L

H

L

X

1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

2) “X” means “H or L (but a defined logic level)”.

3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must

be powered down and then restarted through the specified initialization sequence before normal operation can continue.

4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.

5) Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BAx selects an (Extended) Mode

Register.

6) V_REFmust be maintained during Self Refresh operation.

7) Self Refresh Exit is asynchronous.

8) Burst reads or writes at BL = 4 cannot be terminated. See Chapter 2.6.6 for details.

9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the

refresh requirements outlined in Chapter 2.7

Data Sheet

67

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Truth Tables

Table 16

Current State¹⁾CKE

Previous Cycle⁶⁾Current Cycle⁶⁾

Clock Enable (CKE) Truth Table for Synchronous Transitions

Command (N)^{2) 3)}Action (N)²⁾

Note⁴⁾⁵⁾

RAS, CAS, WE, CS

(N-1)

(N)

7)8)11)

Power-Down

Self Refresh

L

H

L

X

Maintain Power-Down

7)9)10)11)

8)11)12)

H

L

DESELECT or NOP Power-Down Exit

X

Maintain Self Refresh

9)12)13)14)

7)9)10)11)15)

H

L

DESELECT or NOP Self Refresh Exit

Bank(s)

Active

DESELECT or NOP Active Power-Down Entry

9)10)11)15)

All Banks Idle

H

L

DESELECT or NOP Precharge Power-Down

Entry

7)11)14)16)

17)

L

AUTOREFRESH

Self Refresh Entry

Any State other H

than

H

Refer to the Command Truth Table

listed above

1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.

2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)

3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

See Chapter 2.4.

4) CKE must be maintained HIGH while the device is in OCD calibration mode.

5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must

be powered down and then restarted through the specified initialization sequence before normal operation can continue.

6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.

7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by

the refresh requirements

8) “X” means “don’t care (including floating around V_REF)” in Self Refresh and Power Down. However ODT must be driven

HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).

9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.

11) t_CKE.MINof 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid

input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not

transition from its valid level during the time period of t_IS+ 2×t_CKE+ t_IH.

12) V_REFmust be maintained during Self Refresh operation.

13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR

period. Read commands may be issued only after t_XSRD(200 clocks) is satisfied.

14) Valid commands for Self Refresh Exit are NOP and DESELCT only.

15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations,

Precharge or Refresh operations are in progress. See Chapter 2.10 and Chapter 2.9.2 for a detailed list of restrictions.

16) Self Refresh mode can only be entered from the All Banks Idle state.

17) Must be a legal command as defined in the Command Truth Table.

Table 17

Data Mask (DM) Truth Table

Name (Function)

Write Enable

DM

L

DQs

Valid

X

Note

1)

Write Inhibit

H

1) Used to mask write data; provided coincident with the corresponding data.

Data Sheet

68

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Absolute Maximum Ratings

4

Absolute Maximum Ratings

Table 18

Symbol

V_DD

Absolute Maximum Ratings

Parameter

Rating

Unit

V

Note

1)

Voltage on V_DDpin relative to V_SS

Voltage on V_DDQpin relative to V_SS

Voltage on VDDL pin relative to V_SS

Voltage on any pin relative to V_SS

Storage Temperature

–1.0 to +2.3

–0.5 to +2.3

–55 to +100

1)

V_DDQ

V

1)

V_DDL

V

1)

V_IN, V_OUT

T_STG

V

1)2)

°C

1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.

Data Sheet

69

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

5

Electrical Characteristics

Table 19

Symbol

T_OPER

DRAM Component Operating Temperature Range

Parameter

Rating

Unit

^oC

Note

1)2)3)4)

Operating Temperature

0 to 95

1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.

2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation,

the DRAM case temperature must be maintained between 0 - 95 ^oC under all other specification parameters.

3) Above 85 ^oC case temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs.

4) Self-Refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the DRAM is below

85^oC case temperature before initiating self-refresh operation.

5.1

DC Characteristics

Table 20

Symbol

Recommended DC Operating Conditions (SSTL_18)

Parameter

Rating

Min.

Unit

Note

Typ.

1.8

Max.

1.9

1)

V_DD

Supply Voltage

1.7

V

1)

V_DDDL

V_DDQ

V_REF

V_TT

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.7

1.8

1.9

1)

1.7

1.8

1.9

2)3)

4)

0.49 × V_DDQ

0.5 × V_DDQ

V_REF

0.51 × V_DDQ

V

_REF– 0.04

V_REF+ 0.04

1) V_DDQtracks with V_DD, V_DDDLtracks with V_DD. AC parameters are measured with V_DD, V_DDQand V_DDDLtied together.

2) The value of V_REFmay be selected by the user to provide optimum noise margin in the system. Typically the value of V_REFis

expected to be about 0.5 × V_DDQof the transmitting device and V_REFis expected to track variations in V_DDQ

3) Peak to peak ac noise on V_REFmay not exceed ± 2% V_REF(dc)

.

4) V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal

to V_REF, and must track variations in die dc level of V_REF

.

Table 21

ODT DC Electrical Characteristics

Parameter / Condition

Symbol

Min.

Nom.

Max.

Unit

Note

1)

Termination resistor impedance value for

EMRS(1)[A6,A2] = [0,1]; 75 Ohm

Rtt1_(eff)

60

75

90

Ω

1)

2)

Termination resistor impedance value for

EMRS(1)[A6,A2] =[1,0]; 150 Ohm

Rtt2_(eff)

Rtt3_(eff)

delta V_M

120

40

150

50

180

Ω

%

Termination resistor impedance value for

EMRS(1)(A6,A2)=[1,1]; 50 Ohm

60

Deviation of V_Mwith respect to V_DDQ/ 2

–6.00

—

+ 6.00

1) Measurement Definition for Rtt(eff): Apply V_IH(ac)and V_IL(ac)to test pin separately, then measure current I(V_IHac) and I(V_ILac

respectively. Rtt(eff) = (V_IH(ac)– V_IL(ac)) /(I(V_IHac) – I(V_ILac)).

)

2) Measurement Definition for V_M: Turn ODT on and measure voltage (V_M) at test pin (midpoint) with no load:

delta V_M= ((2 x V_M/ V_DDQ) – 1) x 100%

Data Sheet

70

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

Table 22

Symbol

I_IL

Input and Output Leakage Currents

Parameter / Condition

Min.

–2

Max.

+2

Unit

µA

Note

1)

Input Leakage Current; any input 0 V < V_IN< V_DD

Output Leakage Current; 0 V < V_OUT< V_DDQ

2)

I_OL

–5

+5

µA

1) all other pins not under test = 0 V

2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off

5.2

DC & AC Characteristics

DDR2 SDRAM pin timing are specified for either single relative to the rising or falling edges of DQS crossing at

ended or differential mode depending on the setting of _REF. In differential mode, these timing relationships

V

the EMRS(1) “Enable DQS” mode bit; timing are measured relative to the crosspoint of DQS and its

advantages of differential mode are realized in system complement, DQS. This distinction in timing methods is

design. The method by which the DDR2 SDRAM pin verified by design and characterization but not subject

timing are measured is mode dependent. In single to production test. In single ended mode, the DQS (and

ended mode, timing relationships are measured RDQS) signals are internally disabled and don’t care.

Table 23

Symbol

V_IH(dc)

DC & AC Logic Input Levels

Parameter

Min.

Max.

Unit

V

DC input logic high

DC input low

V

_REF+ 0.125

V

_DDQ+ 0.3

_REF– 0.125

V_IL(dc)

–0.3

V

V_IH(ac)

AC input logic high

AC input low

V

_REF+ 0.250

—

V

V_IL(ac)

—

V

_REF– 0.250

V

Table 24

Symbol

V_REF

Single-ended AC Input Test Conditions

Condition

Value

Unit

V

Note

1)

Input reference voltage

0.5 x V_DDQ

1.0

1)

V_SWING.MAX

SLEW

Input signal maximum peak to peak swing

Input signal minimum Slew Rate

V

2)3)

1.0

V / ns

1) Input waveform timing is referenced to the input signal crossing through the V_REFlevel applied to the device under test.

2) The input signal minimum Slew Rate is to be maintained over the range from V_IH(ac).MINto V_REFfor rising edges and the

range from V_REFto V_IL(ac).MAXfor falling edges as shown in Figure 61

3) AC timings are referenced with input waveforms switching from V_IL(ac)to V_IH(ac)on the positive transitions and V_IH(ac)to

V

_IL(ac)on the negative transitions.

Data Sheet

71

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

Start of Falling Edge Input Timing

Start of Rising Edge Input Timing

V

DDQ

.MIN

IH (ac)

IH (dc) .MIN

REF

V

SWING.MAX

V

.MAX

IL (dc)

IL (ac) .MAX

SS

V

delta TF

V

delta TR

- V

V

REF

IL (ac).MAX

IH(ac).MIN - REF

Falling Slew =

Rising Slew =

delta TR

delta TF

Figure 61 Single-ended AC Input Test Conditions Diagram

Table 25

Symbol

V_IN(dc)

Differential DC and AC Input and Output Logic Levels

Parameter

Min.

Max.

Unit

—

V

Note

1)

DC input signal voltage

DC differential input voltage

AC differential input voltage

–0.3

V

_DDQ+ 0.3

2)

3)

4)

V_ID(dc)

0.25

_DDQ+ 0.6

V_ID(ac

0.5

)

V_IX(ac)

AC differential cross point input

voltage

0.5 × V_DDQ– 0.175

0.5 × V_DDQ+ 0.175

V

5)

V_OX(ac)

AC differential cross point output

voltage

0.5 × V_DDQ– 0.125

0.5 × V_DDQ+ 0.125

V

1) V_IN(dc)specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.

2) V_ID(dc)specifies the input differential voltage V_TR– V_CPrequired for switching. The minimum value is equal to V_IH(dc)– V_IL(dc)

3) V_ID(ac)specifies the input differential voltage V_TR– V_CPrequired for switching. The minimum value is equal to V_IH(ac)– V_IL(ac)

.

4) The value of V_IX(ac)is expected to equal 0.5 × V_DDQof the transmitting device and V_IX(ac)is expected to track variations in

_DDQ. V_IX(ac)indicates the voltage at which differential input signals must cross.

V

5) The value of V_OX(ac)is expected to equal 0.5 × V_DDQof the transmitting device and V_OX(ac)is expected to track variations in

V

_DDQ. V_OX(ac)indicates the voltage at which differential input signals must cross.

VDDQ

VSSQ

VTR

Crossing Point

VID

VIX or VOX

VCP

SSTL18_3

Figure 62 Differential DC and AC Input and Output Logic Levels Diagram

Data Sheet

72

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

5.3

Output Buffer Characteristics

Table 26

Symbol

I_OH

SSTL_18 Output DC Current Drive

Parameter

SSTL_18

–13.4

Unit

mA

Note

1)2)

Output Minimum Source DC Current

Output Minimum Sink DC Current

2)3)

I_OL

13.4

1) V_DDQ= 1.7 V; V_OUT= 1.42 V. (V_OUT–V_DDQ) / I_OHmust be less than 21 Ohm for values of V_OUTbetween V_DDQand

_DDQ– 280 mV.

V

2) The values of I_OH(dc)and I_OL(dc)are based on the conditions given in ¹⁾and ³⁾. They are used to test drive current capability

to ensure V_IH.MIN. plus a noise margin and V_IL.MAXminus a noise margin are delivered to an SSTL_18 receiver. The actual

current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient

current for measurement.

3) V_DDQ= 1.7 V; V_OUT= 280 mV. V_OUT/ I_OLmust be less than 21 Ohm for values of V_OUTbetween 0 V and 280 mV.

Table 27

Symbol

V_OH

SSTL_18 Output AC Test Conditions

Parameter

SSTL_18

Unit

V

Note

1)

Minimum Required Output Pull-up

Maximum Required Output Pull-down

Output Timing Measurement Reference Level

V_TT+ 0.603

V_TT– 0.603

0.5 × V_DDQ

1)

V_OL

V

V_OTR

V

1) SSTL_18 test load for V_OHand _VOLis different from the referenced load described in Chapter 8.1. The SSTL_18 test load

has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into V_TT. The SSTL_18 definition assumes that

± 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an

additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to V_TT, at the ouput

device (13.4 mA × 45 Ohm = 603 mV).

Table 28

OCD Default Characteristics

Description

Symbol

Min.

12.6

0

Nominal

Max.

23.4

4

Unit

Note

1)2)

—

Output Impedance

18

—

Ohms

1)2)3)

4)

Pull-up / Pull down mismatch

Output Impedance step size

for OCD calibration

0

1.5

1)5)6)7)8)

S_OUT

Output Slew Rate

1.5

—

5.0

V / ns

1) V_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V

2) Impedance measurement condition for output source dc current: V_DDQ= 1.7 V, V_OUT= 1420 mV;

(V_OUT–V_DDQ) / I must be less than 23.4 ohms for values of V_OUTbetween V_DDQand V_DDQ– 280 mV. Impedance

measurement ^Oc^Hondition for output sink dc current: V_DDQ= 1.7 V; V_OUT= –280 mV; V_OUT/ I_OLmust be less than

23.4 Ohms for values of V_OUTbetween 0 V and 280 mV.

3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.

4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process

parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved

if the OCD impedance is 18 ± 0.75 Ohms under nominal conditions.

5) Slew Rates according to Chapter 8.2.1 V_IL(ac)to V_IH(ac)with the load specified in Figure 67.

6) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as

measured from AC to AC. This is verified by design and characterization but not subject to production test.

7) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included

in t_DQSQand t_QHSspecification.

8) DRAM output Slew Rate specification applies to 400 and 533 MT/s speed bins.

Data Sheet

73

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

5.4

Default Output V-I Characteristics

DDR2 SDRAM output driver characteristics are defined show the driver characteristics graphically and the

for full strength default operation as selected by the tables show the same data suitable for input into

EMRS(1) bits A[9:7] =’111’. Figure 63 and Figure 64 simulation tools.

Table 29

Full Strength Default Pull-up Driver Characteristics

Pull-up Driver Current [mA]

Voltage (V)

Min.¹⁾

Nominal Default low²⁾Nominal Default high²⁾Max.³⁾

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

–8.5

–11.1

–16.0

–20.3

–24.0

–27.2

–29.8

–31.9

–33.4

–34.6

–35.5

–36.2

–36.8

–37.2

–37.7

–38.0

–38.4

–38.6

—

–11.8

–17.0

–22.2

–27.5

–32.4

–36.9

–40.8

–44.5

–47.7

–50.4

–52.5

–54.2

–55.9

–57.1

–58.4

–59.6

–60.8

—

–15.9

–23.8

–31.8

–39.7

–47.7

–55.0

–62.3

–69.4

–75.3

–80.5

–84.6

–87.7

–90.8

–92.9

–94.9

–97.0

–99.1

–101.1

–12.1

–14.7

–16.4

–17.8

–18.6

–19.0

–19.3

–19.7

–19.9

–20.0

–20.1

–20.2

–20.3

–20.4

–20.6

—

1) The driver characteristics evaluation conditions are Minimum 95 ^°C (T_CASE), V_DDQ= 1.7 V, slow–slow process

2) The driver characteristics evaluation conditions are Nominal Default 25 ^°C (T_CASE), V_DDQ= 1.8 V, typical process

3) The driver characteristics evaluation conditions are Maximum 0 °C (T_CASE). V_DDQ= 1.9 V, fast–fast process

Data Sheet

74

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

0

-20

-40

Minimum

Nominal Default Low

Nominal Default High

Maximum

-60

-80

-100

-120

0

0,2

0,4

0,6

0,8

1

1,2

1,4

1,6

1,8

2

VDDQ to VOUT (V)

Figure 63 Full Strength Default Pull-up Driver Diagram

Table 30

Full Strength Default Pull–down Driver Characteristics

Pull-down Driver Current [mA]

Voltage (V)

Min.¹⁾

Nominal Default low²⁾Nominal Default high²⁾Max.³⁾

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

8.5

11.3

16.5

21.2

25.0

28.3

30.9

33.0

34.5

35.5

36.1

36.6

36.9

37.1

37.4

37.6

37.7

37.9

—

11.8

16.8

22.1

27.6

32.4

36.9

40.9

44.6

47.7

50.4

52.6

54.2

55.9

57.1

58.4

59.6

60.9

—

15.9

23.8

31.8

39.7

47.7

55.0

62.3

69.4

75.3

80.5

84.6

87.7

90.8

92.9

94.9

97.0

99.1

101.1

12.1

14.7

16.4

17.8

18.6

19.0

19.3

19.7

19.9

20.0

20.1

20.2

20.3

20.4

20.6

—

1) The driver characteristics evaluation conditions are Minimum 95 ^oC (T_CASE), V_DDQ= 1.7 V, slow-slow process,

2) The driver characteristics evaluation conditions are Nominal Default 25 ^oC (T_CASE), V_DDQ= 1.8 V, typical process,

3) The driver characteristics evaluation conditions are Maximum 0 ^oC (T_CASE). V_DDQ= 1.9 V, fast-fast process

Data Sheet

75

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

T

120

100

80

60

40

20

0

Minimum

Nominal Default Low

Nominal Default High

Maximum

0

0,2 0,4 0,6 0,8

1

1,2 1,4 1,6 1,8

2

VOUT to VSSQ (V)

Figure 64 Full Strength Default Pull–down Driver Diagram

5.4.1

Calibrated Output Driver V-I Characteristics

DDR2 SDRAM output driver characteristics are defined looking at one DQ only. If the calibration procedure is

for full strength calibrated operation as selected by the used, it is possible to cause the device to operate

procedure outlined in the Off-Chip Driver (OCD) outside the bounds of the default device characteristics

Impedance Adjustment. The Table 31 and Table 32 tables and figure. In such a situation, the timing

show the data in tabular format suitable for input into parameters in the specification cannot be guaranteed.

simulation tools. The nominal points represent a device It is solely up to the system application to ensure that

at exactly 18 ohms. The nominal low and nominal high the device is calibrated between the minimum and

values represent the range that can be achieved with a maximum default values at all times. If this can’t be

maximum 1.5 ohms step size with no calibration error guaranteed by the system calibration procedure, re-

at the exact nominal conditions only (i.e. perfect calibration policy and uncertainty with DQ to DQ

calibration procedure, 1.5 ohm maximum step size variation, it is recommended that only the default

guaranteed by specification). Real system calibration values to be used. The nominal maximum and

error needs to be added to these values. It must be minimum values represent the change in impedance

understood that these V-I curves are represented here from nominal LOW and HIGH as a result of voltage and

or in supplier IBIS models need to be adjusted to a temperature change from the nominal condition to the

wider range as a result of any system calibration error. maximum and minimum conditions. If calibrated at an

Since this is a system specific phenomena, it cannot be extreme condition, the amount of variation could be as

quantified here. The values in the calibrated tables much as from the nominal minimum to the nominal

represent just the DRAM portion of uncertainty while maximum or vice versa.

Data Sheet

76

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

Table 31

Full Strength Calibrated Pull-down Driver Characteristics

Voltage (V)

Calibrated Pull-down Driver Current [mA]

Nominal Minimum¹⁾Nominal Low²⁾Nominal³⁾

Nominal High²⁾Nominal

(17.25 Ohms)

(21 Ohms)

(18.75 Ohms)

(18 ohms)

Maximum⁴⁾

(15 Ohms)

0.2

0.3

0.4

9.5

10.7

16.0

21.0

11.5

16.6

21.6

11.8

17.4

23.0

13.3

20.0

27.0

14.3

18.7

1) The driver characteristics evaluation conditions are Nominal Minimum 95 ^oC (T_CASE). V_DDQ= 1.7 V, any process

o

2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 C (T_CASE), V_DDQ= 1.8V, any

process

3) The driver characteristics evaluation conditions are Nominal 25 ^oC (T_CASE), V_DDQ= 1.8 V, typical process

4) The driver characteristics evaluation conditions are Nominal Maximum 0 ^oC (T_CASE), V_DDQ= 1.9 V, any process

Table 32

Full Strength Calibrated Pull-up Driver Characteristics

Calibrated Pull-up Driver Current [mA]

Voltage (V)

Nominal

Nominal Low²⁾

(18.75 Ohms)

Nominal

Nominal High²⁾Nominal

(17.25 Ohms)

Minimum¹⁾

(21 Ohms)

(18 ohms)³⁾

Maximum⁴⁾

(15 Ohms)

0.2

0.3

0.4

–9.5

–10.7

–16.0

–21.0

–11.4

–16.5

–21.2

–11.8

–17.4

–23.0

–13.3

–20.0

–27.0

–14.3

–18.3

1) The driver characteristics evaluation conditions are Nominal Minimum 95 ^oC (T_CASE). V_DDQ= 1.7 V, any process

o

2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 C (T_CASE), V_DDQ= 1.8V, any

process

3) The driver characteristics evaluation conditions are Nominal 25 ^oC (T_CASE), V_DDQ= 1.8 V, typical process

4) The driver characteristics evaluation conditions are Nominal Maximum 0 ^oC (T_CASE), V_DDQ= 1.9 V, any process

5.5

Input / Output Capacitance

Table 33

Symbol

CCK

Input / Output Capacitance

Parameter

Min.

1.0

—

Max.

2.0

Unit

pF

Input capacitance, CK and CK

Input capacitance delta, CK and CK

Input capacitance, all other input-only pins

Input capacitance delta, all other input-only pins

CDCK

CI

0.25

2.0

pF

1.0

—

pF

CDI

0.25

4.0

pF

CIO

Input/output capacitance,

2.5

pF

DQ, DM, DQS, DQS, RDQS, RDQS

CDIO

Input/output capacitance delta,

—

0.5

pF

DQ, DM, DQS, DQS, RDQS, RDQS

Data Sheet

77

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

5.6

Power & Ground Clamp V-I Characteristics

Power and Ground clamps are provided on address The V-I characteristics for pins with clamps is shown in

(A[12:0], BA[1:0]), RAS, CAS, CS, WE, and ODT pins. Table 34.

Table 34

Power & Ground Clamp V-I Characteristics

Voltage across clamp (V)

Minimum Power Clamp

Current (mA)

Minimum Ground Clamp Current (mA)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

0

0.1

1.0

2.5

4.7

6.8

9.1

11.0

13.5

16.0

18.2

21.0

0.1

1.0

2.5

4.7

6.8

9.1

11.0

13.5

16.0

18.2

21.0

Data Sheet

78

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

5.7

Overshoot and Undershoot Specification

Table 35

AC Overshoot / Undershoot Specification for Address and Control Pins

Parameter

DDR2–400

0.9

DDR2–533

Unit

V

Maximum peak amplitude allowed for overshoot area

Maximum peak amplitude allowed for undershoot area

Maximum overshoot area above V_DD

Maximum undershoot area below V_SS

0.9

V

0.75

0.56

V.ns

0.75

Maximum Amplitude

Overshoot Area

VDD

VSS

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 65 AC Overshoot / Undershoot Diagram for Address and Control Pins

Table 36

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins

Parameter

DDR2–400 DDR2–533

Unit

V

Maximum peak amplitude allowed for overshoot area

Maximum peak amplitude allowed for undershoot area

Maximum overshoot area above V_DDQ

Maximum undershoot area below V_SSQ

0.9

V

0.38

0.28

V.ns

Maximum Amplitude

Overshoot Area

VDDQ

VSSQ

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 66 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins

Data Sheet

79

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

I_DDSpecifications and Conditions

6

I_DDSpecifications and Conditions

Table 37

I_DDMeasurement Conditions

Parameter

Symbol Note

1)2)3)4)5)6)

Operating Current - One bank Active - Precharge

_CK= t_CK(IDD), t_RC= t_RC(IDD), t_RAS= t_RAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid

I_DD0

t

commands. Address and control inputs are switching; Databus inputs are switching^.

1)2)3)4)5)6)

Operating Current - One bank Active - Read - Precharge

I_DD1

I

_OUT= 0 mA, BL = 4, t_CK= t_CK(IDD), t_RC= t_RC(IDD), t_RAS= t_RAS.MIN(IDD), t_RCD= t_RCD(IDD), AL = 0,

CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control

inputs are switching; Databus inputs are switching.

1)2)3)4)5)6)

Precharge Power-Down Current

All banks idle; CKE is LOW; t_CK= t_CK(IDD);Other control and address inputs are stable; Data

bus inputs are floating^.

I_DD2P

Precharge Standby Current

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK(IDD); Other control and address inputs are

switching, Data bus inputs are switching.

I_DD2N

Precharge Quiet Standby Current

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK(IDD); Other control and address inputs are

stable, Data bus inputs are floating.

I_DD2Q

I_DD3P(0)

I_DD3P(1)

I_DD3N

Active Power-Down Current

All banks open; t_CK= t_CK(IDD), CKE is LOW; Other control and address inputs are stable; Data

bus inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).

Active Power-Down Current

All banks open; t_CK= t_CK(IDD), CKE is LOW; Other control and address inputs are stable, Data

bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);

Active Standby Current

All banks open; t_CK= t_CK(IDD); t_RAS= t_RAS.MAX(IDD), t_RP= t_RP(IDD); CKE is HIGH, CS is HIGH

between valid commands. Address inputs are switching; Data Bus inputs are switching;

Operating Current

I_DD4R

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_(IDD)

;

t

_CK= t_CK(IDD); t_RAS= t_{RAS.MAX.(IDD)}, t_RP= t_RP(IDD); CKE is HIGH, CS is HIGH between valid

commands. Address inputs are switching; Data Bus inputs are switching; I_OUT= 0 mA.

1)2)3)4)5)6)

Operating Current

I_DD4W

I_DD5B

I_DD5D

Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_(IDD)

;

t

_CK= t_CK(IDD); t_RAS= t_RAS.MAX(IDD), t_RP= t_RP(IDD); CKE is HIGH, CS is HIGH between valid

commands. Address inputs are switching; Data Bus inputs are switching;

Burst Refresh Current

t

_CK= t_CK(IDD), Refresh command every t_RFC= t_RFC(IDD)interval, CKE is HIGH, CS is HIGH

between valid commands, Other control and address inputs are switching, Data bus inputs

are switching.

Distributed Refresh Current

t

_CK= t_CK(IDD), Refresh command every t_REFI= 7.8 µs interval, CKE is LOW and CS is HIGH

between valid commands, Other control and address inputs are switching, Data bus inputs

are switching.

Data Sheet

80

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

I_DDSpecifications and Conditions

Table 37

I_DDMeasurement Conditions

Parameter

Symbol Note

1)2)3)4)5)6)

Self-Refresh Current

I_DD6

CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are

floating, Data bus inputs are floating.

1)2)3)4)5)6)7)

All Bank Interleave Read Current

I_DD7

1. All banks interleaving reads, I_OUT= 0 mA; BL = 4, CL=CL_(IDD), AL = t_RCD(IDD)-1 × t_CK(IDD)

;

t_CK= t_CK(IDD), t_RC= t_RC(IDD), t_RRD= t_RRD(IDD); CKE is HIGH, CS is HIGH between valid

commands. Address bus inputs are stable during deselects; Data bus is switching.

2. Timing pattern:

– DDR2-400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D

– DDR2-533: A0 RA0 D A1 RA1 A2 RA2 A3 RA3 D D D D D

1) V_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V

2) I_DDspecifications are tested after the device is properly initialized.

3) I_DDparameter are specified with ODT disabled.

4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.

5) Definitions for I_DD

low is defined as V_IN≤ V_IL(ac).MAX

high is defined as V_IN≥ V_IH(ac).MIN

:

;

stable is defined as inputs are stable at a HIGH or LOW level;

floating is defined as inputs are V_REF= V_DDQ/ 2;

switching is defined as: Inputs are changing between high and low every other clock (once per two clocks) for

address and control signals, and inputs changing between high and low every other clock (once per clock)

for DQ signals not including mask or strobes.

6) Timing parameter minimum and maximum values for I_DDcurrent measurements are defined in Table 38.

7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT

Table 38

I_DDSpecification

Product Type Speed Code

–3.7

–5

Unit

Notes

Speed Grade

Symbol

I_DD0

DDR2–533

DDR2–400

Max.

55

60

35

4

Max.

50

55

28

4

mA

I_DD1

I_DD2N

I_DD2P

1)

I_DD2Q

25

20

1)

I_DD3N

I_DD3P

35

16

4

30

13

4

mA

1)2)

1)3)

I_DD4R

I_DD4W

70

80

85

100

85

6

60

70

90

80

6

×4/×8

×16

×4/×8

×16

1)

I_DD5B

I_DD5D

1)

Data Sheet

81

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

I_DDSpecifications and Conditions

Table 38

I_DDSpecification

Product Type Speed Code

–3.7

–5

Unit

Notes

Speed Grade

Symbol

I_DD6

DDR2–533

DDR2–400

Max.

1)4)

4

mA

I_DD7

135

150

125

140

mA

×4/×8

×16

1) I_DD6: 0 ≤ T_CASE≤ 85 ^oC

2) MRS(12)=0

3) MRS(12)=1

4) standard products

Data Sheet

82

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

I_DDSpecifications and Conditions

6.1

I_DDTest Conditions

For testing the I_DDparameters, the following timing parameters are used:

Table 39

I_DDMeasurement Test Condition

Parameter

Symbol

-3.7

-5

Unit

Note

DDR2–533 4–4–4 DDR2–400 3–3–3

CAS Latency

CL_(IDD)

t_CK(IDD)

t_RCD(IDD)

4

3

t_CK

ns

Clock Cycle Time

3.75

15

60

5

Active to Read or Write delay

15

55

Active to Active / Auto-Refresh command t_RC(IDD)

period

1)

2)

Active bank A to Active bank B command t_RRD(IDD)

delay

7.5

10

7.5

10

ns

Active to Precharge Command

t_RAS.MIN(IDD)45

40

t_RAS.MAX(IDD)70000

70000

15

Precharge Command Period

t_RP.MIN

15

75

Auto-Refresh to Active / Auto-Refresh

command period

t_RFC(IDD)

75

1) ×4 & ×8 (1 kB page size)

2) ×16 (2 kB page size); not on 256M component

6.2

On Die Termination (ODT) Current

The ODT function adds additional current consumption current consumption for any terminated input pin

to the DDR2 SDRAM when enabled by the EMRS(1). depends on whether the input pin is in tri-state or

Depending on address bits A6 & A2 in the EMRS(1) a driving “0” or “1”, as long a ODT is enabled during a

“weak” or “strong” termination can be selected. The given period of time.. See Table 40

.

Table 40

ODT current per terminated input pin

ODT Current

EMRS(1) State

A6 = 0, A2 = 1

A6 = 1, A2 = 0

A6 = 1, A2 = 1

A6 = 0, A2 = 1

A6 = 1, A2 = 0

Min. Typ.

Max. Unit

Enabled ODT current per DQ

added I_DDQcurrent for ODT enabled;

ODT is HIGH; Data Bus inputs are floating

I_ODTO

5

6

7.5

mA/DQ

2.5

7.5

10

5

3

3.75

9

11.25 mA/DQ

Active ODT current per DQ

I_ODTT

12

6

15

mA/DQ

added I_DDQcurrent for ODT enabled;

ODT is HIGH; worst case of Data Bus inputs are

stable or switching.

7.5

22.5

15

18

Note:For power consumption calculations the ODT duty cycle has to be taken into account

Data Sheet

83

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

7

Electrical Characteristics

Table 41

Speed Grade Definition Speed Bins

Speed Grade

DDR2–533C

–3.7

DDR2–400B

–5

Unit

Note

IFX Sort Name

CAS-RCD-RP latencies

Parameter

4–4–4

3–3–3

t_CK

—

ns

Symbol

t_CK

Min.

5

Max.

Min.

5

Max.

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

8

@ CL = 4

@ CL = 5

t_CK

3.75

45

8

5

8

t_CK

8

5

8

RAS-CAS-Delay

Row Precharge Time

Row Active Time

Row Cycle Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

40

55

15

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other

Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the

“Reference Load for Timing Measurements” according to Chapter 8.1 only.

2) The CK CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,

RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals

other than CK/CK, DQS / DQS, RDQS / RDQS is defined in Chapter 8.3.

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT. See section 8 for the reference load for timing measurements.

5) t_RAS(max)is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

Table 42

Timing Parameter by Speed Grade - DDR2-400 & DDR2-533

Parameter

Symbol

–3.7

–5

Unit Note

1)2)3)4)5)6)

DDR2–533 4–4–4

DDR2–400 3–3–3

Min.

Max.

Min.

Max.

DQ output access time from CK / t_AC

–500

+500

–600

+600

ps

CK

CAS A to CAS B command

period

t_CCD

2

—

2

—

t_CK

CK, CK high-level width

t_CH

0.45

3

0.55

—

0.45

3

0.55

—

t_CK

CKE minimum high and low

pulse width

t_CKE

CK, CK low-level width

t_CL

0.45

0.55

—

0.45

0.55

—

t_CK

7)

8)

Auto-Precharge write recovery + t_DAL

WR + t_RP

precharge time

Minimum time clocks remain ON t_DELAY

after CKE asynchronously drops

LOW

t_IS+ t_CK

t_IH

+

––

t_IS+ t_CK

t_IH

+

—

ns

9)

DQ and DM input hold time

(differential data strobe)

t_DH(base) 225

t_DH1(base) –25

––

—

275

25

––

—

ps

DQ and DM input hold time

(single ended data strobe)

Data Sheet

84

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

Table 42

Timing Parameter by Speed Grade - DDR2-400 & DDR2-533

Parameter

Symbol

–3.7

–5

Unit Note

1)2)3)4)5)6)

DDR2–533 4–4–4

DDR2–400 3–3–3

Min.

Max.

Min.

Max.

DQ and DM input pulse width

(each input)

t_DIPW

0.35

—

0.35

—

t_CK

ps

t_CK

ps

DQS output access time from CK t_DQSCK

/ CK

–450

0.35

—

+450

—

–500

0.35

—

+500

—

DQS input low (high) pulse width t_DQSL,H

(write cycle)

10)

DQS-DQ skew (for DQS &

associated DQ signals)

t_DQSQ

t_DQSS

t_DS(base) 100

_DS1(base) –25

300

350

Write command to 1st DQS

latching transition

WL – 0.25 WL + 0.25 WL – 0.25 WL + 0.25 t_CK

9)

DQ and DM input setup time

(differential data strobe)

—

150

25

—

ps

t_CK

DQ and DM input setup time

(single ended data strobe)

t

DQS falling edge hold time from t_DSH

CK (write cycle)

0.2

DQS falling edge to CK setup

time (write cycle)

t_DSS

t_FAW

11)12)

13)12)

14)

Four Activate Window period

37.5

50

—

37.5

50

—

ns

Clock half period

t_HP

t_HZ

MIN. (t_CL,t_CH)

t_AC.MAX

MIN. (t_CL,t_CH)

15)

Data-out high-impedance time

from CK / CK

—

t_AC.MAX

ps

t_CK

9)

Address and control input hold

time

t_IH(base) 375

—

475

0.6

—

Address and control input pulse t_IPW

0.6

width

(each input)

9)

Address and control input setup t_IS(base) 250

time

—

350

—

ps

t_CK

ns

15)

DQ low-impedance time from CK t_LZ(DQ)

2 × t_AC.MINt_AC.MAX

/ CK

DQS low-impedance from CK / t_LZ(DQS)

t_AC.MIN

t_AC.MAX

t_AC.MIN

t_AC.MAX

CK

Mode register set command

cycle time

t_MRD

t_OIT

2

—

2

—

OCD drive mode output delay

0

12

0

12

Data output hold time from DQS t_QH

t

_HP– t_QHS

—

t

_HPQ– t_QHS

—

Data hold skew factor

t_QHS

—

75

400

7.8

3.9

—

75

450

7.8

3.9

—

ps

µs

ns

16)17)

16)18)

19)

Average periodic refresh Interval t_REFI

Auto-Refresh to Active/Auto-

Refresh command period

t_RFC

Data Sheet

85

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

Table 42

Timing Parameter by Speed Grade - DDR2-400 & DDR2-533

Parameter

Symbol

–3.7

–5

Unit Note

1)2)3)4)5)6)

DDR2–533 4–4–4

DDR2–400 3–3–3

Min.

0.9

Max.

1.1

0.60

—

Min.

0.9

Max.

1.1

0.60

—

15)

Read preamble

Read postamble

t_RPRE

t_RPST

t_CK

ns

15)

0.40

7.5

0.40

7.5

11)20)

13)20)

Active bank A to Active bank B t_RRD

command period

10

—

10

—

Internal Read to Precharge

command delay

t_RTP

7.5

—

7.5

—

Write preamble

Write postamble

t_WPRE

t_WPST

t_WR

0.25

0.40

15

—

0.25

0.40

15

—

t_CK

ns

21)

0.60

—

0.60

—

Write recovery time for write

without Auto-Precharge

Write recovery time for write with WR

Auto-Precharge

t

_WR/t_CK

t

_WR/t_CK

t_CK

ns

22)

23)

Internal Write to Read command t_WTR

delay

7.5

2

—

10

2

—

Exit power down to any valid

command

t_XARD

t_CK

(other than NOP or Deselect)

23)

Exit active power-down mode to t_XARDS

Read command (slow exit, lower

power)

6 – AL

2

—

6 – AL

2

—

t_CK

Exit precharge power-down to

any valid command (other than

NOP or Deselect)

t_XP

t_CK

Exit Self-Refresh to non-Read

command

t_XSNR

t_XSRD

t

_RFC+10

—

t

_RFC+10

—

ns

Exit Self-Refresh to Read

command

200

t_CK

1) V_DDQ= 1.8V ± 0.1V; V_DD= 1.8V ± 0.1 V. See notes ^3)4)5)6)

2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be

powered down and then restarted through the specified initialization sequence before normal operation can continue.

3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other

Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1

= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.

4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.

The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode;

The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined in Chapter 8.3 of this data

sheet.

5) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

6) The output timing reference voltage level is V_TT. See Chapter 8 for the reference load for timing measurements.

7) For each of the terms, if not already an integer, round to the next highest integer. t_CKrefers to the application clock period.

WR refers to the WR parameter stored in the MR.

8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock

frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.

Data Sheet

86

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Electrical Characteristics

9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8

10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as

output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.

11) ×4 & ×8 (1k page size)

12) 8 bank device Sequential Activation Restriction. No more than 4 banks may be activated in a rolling t_FAWwindow.

13) ×16 (2k page size), not on 256 Mbit component

14) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.

this value can be greater than the minimum specification limits for t_CLand t_CH).

15) The t_HZ, t_RPSTand t_LZ, t_RPREparameters are referenced to a specific voltage level, which specify when the device output is

no longer driving (t_HZ, t_RPST), or begins driving (t_LZ, t_RPRE). t_HZand t_LZtransitions occur in the same access time windows

as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.

16) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range

between 85 ^°C and 95 ^°C.

17) 0 ≤ T_CASE≤ 85 ^°C

18) 85 ^°C < T_CASE≤ 95 ^°C

19) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.

20) The t_RRDtiming parameter depends on the page size of the DRAM organization. See Chapter 1.5

21) The maximum limit for the t_WPSTparameter is not a device limit. The device operates with a greater value for this parameter,

but system performance (bus turnaround) degrades accordingly.

22) Minimum t_WTRis two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.

23) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard

active power-down mode” (MR, A12 = “0”) a fast power-down exit timing t_XARDcan be used. In “low active power-down

mode” (MR, A12 =”1”) a slow power-down exit timing t_XARDShas to be satisfied.

Table 43

ODT AC Electrical Characteristics and Operating Conditions

Symbol Parameter / Condition

Min.

2

Max.

Unit

t_CK

Note

t_AOND

t_AON

ODT turn-on delay

2

1)

ODT turn-on

t_AC.MIN

t

_AC.MAX+ 1 ns

ns

t_AONPD

t_AOFD

t_AOF

ODT turn-on (Power-Down Modes)

ODT turn-off delay

t

_AC.MIN+ 2 ns 2 t_CK+ t_AC.MAX+ 1 ns ns

2.5

_AC.MAX+ 0.6 ns

t_CK

2)

ODT turn-off

t_AC.MIN

t

ns

t_AOFPD

t_ANPD

t_AXPD

ODT turn-off (Power-Down Modes)

t_AC.MIN+ 2 ns 2.5 t_CK+ t_AC.MAX+ 1 ns ns

ODT to Power Down Mode Entry Latency 3

ODT Power Down Exit Latency

—

t_CK

8

1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time

max is when the ODT resistance is fully on. Both are measure from t_AOND

2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in

high impedance. Both are measured from t_AOFD

.

Note:For product nomenclature see Chapter 10 of this data sheet

Data Sheet

87

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

AC Timing Measurement Conditions

8

AC Timing Measurement Conditions

8.1

Reference Load for Timing Measurements

Figure 67 represents the timing reference load used in transmission line terminated at the tester electronics.

defining the relevant timing parameters of the device. It This reference load is also used for output Slew Rate

is not intended to either a precise representation of the characterization. The output timing reference voltage

typical system environment nor a depiction of the actual level for single ended signals is the crosspoint with V_TT.

load presented by a production tester. System

The output timing reference voltage level for differential

designers should use IBIS or other simulation tools to

signals is the crosspoint of the true (e.g. DQS) and the

correlate the timing reference load to a system

complement (e.g. DQS) signal.

environment. Manufacturers correlate to their

production test conditions, generally

a

coaxial

VDDQ

DQ

DQS

RDQS

CK, CK

DUT

V

_TT= V_DDQ/ 2

25 Ohm

Timing Reference Points

Figure 67 Reference Load for Timing Measurements

8.2

Slew Rate Measurement Conditions

Output Slew Rate

8.2.1

For DQ and single ended DQS signals output Slew DQS – DQS = + 500 mV. Output Slew Rate is defined

Rate for falling and rising edges is measured between with the reference load according to Figure 67 and

V

_TT– 250 mV and V_TT+ 250 mV.

verified by design and characterization, but not subject

to production test.

For differential signals (DQS / DQS) output Slew Rate

is measured between DQS - DQS = –500 mV and

8.2.2

Input Slew Rate - Differential signals

Input Slew Rate for differential signals (CK / CK, DQS / from CK – CK = +250 mV to CK – CK = –500mV for

DQS, RDQS / RDQS) for rising edges are measured falling edges.

from CK - CK = –250 mV to CK – CK = +500 mV and

Data Sheet

88

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

AC Timing Measurement Conditions

8.3

Input and Data Setup and Hold Time

Definition for Input Setup (t_IS) and Hold Time (t_IH)

8.3.1

Address and control input setup time (t_IS) is referenced (t_IH) is referenced from the input signal crossing at the

from the input signal crossing at the V_IH(ac)level for a V_IL(dc)level for a rising signal and V_IH(dc)for a falling

rising signal and V_IL(ac)for a falling signal applied to the signal applied to the device under test.

device under test. Address and control input hold time

.

CK

t

IS

IH

IS IH

V

DDQ

IH(ac)

IH(dc)

REF

min

max

IL(dc)

IL(ac)

SS

Figure 68 Input Setup and Hold Time

8.3.2

Definition for Data Setup (t_DS) and Hold Time (t_DH), differential Data Strobes

Data input setup time (t_DS) with differential data strobe differential data strobe enabled MR[bit10]=0, is

enabled MR[bit10]=0, is referenced from the input referenced from the input signal crossing at the V_IL(dc)

signal crossing at the V_IH(ac)level to the differential data level to the differential data strobe crosspoint for a

strobe crosspoint for a rising signal, and from the input rising signal and V_IH(dc)to the differential data strobe

signal crossing at the V_IL(ac)level to the differential data crosspoint for a falling signal applied to the device

strobe crosspoint for a falling signal applied to the under test.

device under test.

DQS/DQS signals must be monotonic between

V

_IL(dc).MAXand V_IH(dc.MIN

.

V

_IL(dc).MAXand V_IH(dc).MIN. Data input hold time (t_DH) with

DQS

t

DS DH

V_DDQ

V_IH(ac)

V_IH(dc)

V_REF

min

V_IL(dc)

V_IL(ac)

V_SS

max

Figure 69 Data Setup and Hold Time (Differential Data Strobes)

Data Sheet

89

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

AC Timing Measurement Conditions

8.3.3

Definition for Data Setup (t_DS1) and Hold Time (t_DH1), Single-Ended Data Strobes

Data input setup time (t_DS1) with single-ended data input signal crossing at the V_IH(dc)level to the single-

strobe enabled MR[bit10]=1, is referenced from the ended data strobe crossing V_IH/L(ac)at the end of its

input signal crossing at the V_IH(ac)level to the single- transition for a rising signal and from the input signal

ended data strobe crossing V_IH/L(dc)at the start of its crossing at the V_IL(dc)level to the single-ended data

transition for a rising signal, and from the input signal strobe crossing V_IH/L(ac)at the end of its transition for a

crossing at the V_IL(ac)level to the single-ended data falling signal applied to the device under test.

strobe crossing V_IH/L(dc)at the start of its transition for a

falling signal applied to the device under test.

The DQS signal must be monotonic between V_IL(dc.MAX

and V_IH(dc).MIN

.

Data input hold time (_tDH1) with single-ended data

strobe enabled MR[bit10]=1, is referenced from the

V_DDQ

V_IH(ac)

V_IH(dc)

V_REF

min

DQS

V_IL(dc)

V_IL(ac)

V_SS

max

t

DS

t

DS

t

DH

V_DDQ

V_IH(ac)

V_IH(dc)

V_REF

min

DQ

V_IL(dc)

V_IL(ac)

V_SS

max

Figure 70 Data Setup and Hold Time (Single Ended Data Strobes)

Data Sheet

90

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

AC Timing Measurement Conditions

8.3.4

Slew Rate Definition for Input and Data Setup and Hold Times

Setup (t_IS& t_DS) nominal Slew Rate for a rising signal is level is used for derating value.(see Figure 72) Hold

defined as the Slew Rate between the last crossing of (t_IH& t_DH) nominal Slew Rate for a rising signal is

V

_REF(dc)and the first crossing of V_IH(ac).MIN. Setup (t_IS& defined as the Slew Rate between the last crossing of

t_DS) nominal Slew Rate for a falling signal is defined as V_IL(dc).MAXand the first crossing of V_REF(dc). Hold (t_IH

&

the Slew Rate between the last crossing of V_REF(dc)and t_DH) nominal Slew Rate for a falling signal is defined as

the first crossing of V_IL(ac).MAX. If the actual signal is the Slew Rate between the last crossing of V_IH(dc).MIN

always earlier than the nominal Slew Rate line between and the first crossing of V_REF(dc). If the actual signal is

shaded ‘V_REF(dc)to ac region’, use nominal Slew Rate always later than the nominal Slew Rate line between

for derating value (see Figure 71). If the actual signal shaded ‘dc to V_REFregion’, use nominal Slew Rate for

is later than the nominal Slew Rate line anywhere derating value (see Figure 71). If the actual signal is

between shaded ‘V_REF(dc)to ac region’, the Slew Rate of earlier than the actual signal from the dc level to V_REF

a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 72)

.

CK, CK for tIS and tIH

DQS, DQS for tDS and tDH

t_IS

t_DS

t_IH

t_DH

t

IH

t

DS

IS

t

DH

V

DDQ

min

IH(ac)

VREF to ac

region

V

min

IH(dc)

dc to VREF

region

V

REF

dc to VREF

region

V

IL(dc)^max

VREF to ac

region

V

IL(ac)^max

V

SS

Delta TFS

Delta TRH Delta TRS

Delta TFH

VREF(dc) - VIL(ac)max

Delta TFS

falling signal

rising signal

Setup Slew Rate =

VIH(ac)min - VREF(dc)

Delta TRS

VREF(dc) - VIL(dc)max

Delta TRH

rising signal

falling signal

Hold Slew Rate

=

VIH(dc)min - VREF(dc)

Delta TFH

Figure 71 Slew Rate Definition Nominal

Data Sheet

91

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

AC Timing Measurement Conditions

CK, CK for tIS and tIH

DQS, DQS for tDS and tDH

t

IH

IS

IS IH

t

DH

DS

DS DH

V

DDQ

min

IH(ac)

IH(dc)

VREF to ac

region

dc to Vref

region

V

REF

dc to Vref

region

V

max

IL(dc)

IL(ac)

VREF to ac

region

V

SS

Delta TFH

Delta TFS

Delta TRH Delta TRS

tangent line

nominal line

tangent line [VREF(dc) - VIL(ac)max]

Delta TFS

falling

signal

Setup Slew Rate =

tangent line [VIH(ac)min - VREF(dc)]

Delta TRS

rising

signal

tangent line [VREF(dc) - VIL(dc)max]

Delta TRH

rising

signal

Hold Slew Rate

=

tangent line [VIH(dc)min - VREF(dc)]

Delta TFH

falling

signal

Figure 72 Slew Rate Definition Tangent

Data Sheet

92

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

AC Timing Measurement Conditions

8.3.5

Setup (t_IS) and Hold (t_IH) Time Derating Tables

1. For all input signals the total input setup time and

input hold time required is calculated by adding the

data sheet value to the derating value respectively.

Example: t_IS(total setup tine) = t_IS(base) + ∆ t_IS

2. For slow Slew Rate the total setup time might be

negative (i.e. a valid input signal will not have

reached V_IH(ac)/ V_IL(ac)at the time of the rising clock)

a valid input signal is still required to complete the

transition and reach V_IH(ac)/ V_IL(ac). For Slew Rates

in between the values listed in the next tables, the

derating values may be obtained by linear

interpolation. These values are not subject to

production test. They are verified only by design

and characterization.

Table 44

Input Setup (t_IS) and Hold (t_IH) Time Derating Values

Command / Address

Slew Rate (V/ns)

Unit

Note

CK, CK Differential Slew Rate

2.0 V/ns

∆ t_IS

1.5 V/ns

∆ t_IS

1.0 V/ns

∆ t_IS

∆ t_IH

+94

+89

+83

+75

+45

+21

0

∆ t_IH

+124

+119

+113

+105

+75

∆ t_IH

+154

+149

+143

+135

+105

+81

1)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.25

0.2

0.15

0.1

+187

+179

+167

+150

+125

+83

+217

+209

+197

+180

+155

+113

+30

+247

+239

+227

+210

+185

+143

+60

ps

+51

0

+30

+60

–11

–14

+19

+16

+49

+46

–25

–31

+5

–1

+35

+29

–43

–54

–13

–24

+17

+6

–67

–83

–37

–53

–7

–23

–110

–175

–285

–350

–525

–800

–1450

–125

–188

–292

–375

–500

–708

–1125

–80

–95

–50

–65

–145

–255

–320

–495

–770

–1420

–158

–262

–345

–470

–678

–1095

–115

–225

–290

–465

–740

–1390

–128

–232

–315

–440

–648

–1065

1) For all input signals t_IS(total) = t_IS(base) + ∆t_ISand t_IH(total) = t_IH(base) + ∆t_IH

Data Sheet

93

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

AC Timing Measurement Conditions

Table 45

Data Setup (t_DS) and Hold Time (t_DH) Derating Values for Differential DQS/DQS¹⁾²⁾

DQS, DQS Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns

1.0 V/ns

0.8 V/ns

∆

t_DS

t_DHt_DS

t_DHt_DSt_DHt_DSt_DHt_DSt_DHt_DS

t_DHt_DS

t_DH

2.0 +125 +45 +125 +45 +125 +45 —

—

–11

1.5 +83 +21 +83 +21 +83 +21 +95 +33 —

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0

+12 +12 +24 +24 —

—

–11 –14 –11 –14 +1 –2 +13 +10 +25 +22 —

—

–25 –31 –13 –19 –1 –7 +11 +5 +23 +17

—

–31 –42 –19 –30 –7 –18 +5

–6

+17 +6

—

–43 –49 –31 –47 –19 –35 –7

–23 +5

—

–74 –89 –62 –77 –50 –65 –38 –53

–127 –140 –115 –128 –103 –116

—

1) All units in ps.

2) For all input signals t_DS(total) = t_DS(base) + ∆t_DSand t_DH(total) = t_DH(base) + ∆t_DH

Table 46

DQS Single-ended Slew Rate

2.0 V/ns 1.5 V/ns 1.0 V/ns

Data Setup (t_DS) and Hold Time (t_DH) Derating Values for Single Ended DQS¹⁾²⁾³⁾

0.9 V/ns 0.8 V/ns 0.7 V/ns 0.6 V/ns

0.5 V/ns

0.4 V/ns

∆

t_D1

t_DH1t_DS1t_DH1t_DS1t_DH1t_DS1t_DH1t_DS1t_DH1t_DS1t_DH1t_DS1t_DH1t_DS1t_DH1t_DS1t_DH1

2.0 +125 +45 +125 +45 +125 +45 -

-

1.5 +83

1.0 0

0.9 -

0.8 -

0.7 -

0.6 -

0.5 -

0.4 -

+21 +83 +21 +83 +21 +95 +33 -

-

0

-

0

+12 +12 +24 +24 -

-

-11

-14 -11

-14 +1 -2

+13 +10 +25 +22 -

-

-25

-31 -13 -19 -1

-7

+11 +5 +23 +17

-18 +5 -6

-43 -49 -31 -47 -19 -35 -7

-

-31 -42 -19 -30 -7

+17 +6

-

-23 +5

-11

-

-74 -89 -62 -77 -50 -65 -38 -53

-127 -140 -115 -128 -103 -116

-

1) All units in ps.

2) For all input signals t_DS1(total) = t_DS1(base) + ∆t_DS1and t_DH1(total) = t_DH1(base) + ∆t_DH1

3) For slow Slew Rate the total setup time might be negative (i.e. a valid input signal will not have reached V_IH(ac)/ V_IL(ac)at

the time of the rising DQS) a valid input signal is still required to complete the transition and reach V_IH(ac)/ V_IL(ac). For Slew

Rates in between the values listed in the table, the derating values may be obtained by linear interpolation. These values

are not subject to production test. They are verified only by design and characterization.

Data Sheet

94

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Package Dimensions

9

Package Dimensions

10.5

11 x 0.8 = 8.8

0.8

0.18 MAX.

0.2

2)

B

2)

1)

5)

4) 3)

A

0.1

C

0.1

C

60x

ø0.15

ø0.08

±0.05

ø0.46

M

SEATING PLANE

C

A B

C

1) Dummy pads without ball

2) Middle of packages edges

3) Package orientation mark A1

4) Bad unit marking (BUM)

5) Die sort fiducial

Figure 73 Package Pinout PG-TFBGA-60 (top view)

Data Sheet

95

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

Package Dimensions

12.5

14 x 0.8 = 11.2

0.8

0.18 MAX.

0.2

2)

B

2)

1) 5)

4)

3)

A

0.1

C

0.1

C

84x

ø0.15

ø0.08

±0.05

ø0.46

M

A B

SEATING PLANE

C

M

1) Dummy pads without ball

2) Middle of packages edges

3) Package orientation mark A1

4) Bad unit marking (BUM)

5) Die sort fiducial

Figure 74 Package Outline PG-TFBGA-84 (top view)

Data Sheet

96

Rev. 1.1, 2004-09

09112003-LZPT-I17F

HYB18T256[40/80/16]0AF–[3.7/5]

256-Mbit Double-Data-Rate-Two SDRAM

DDR2 Component Nomenclature

10

DDR2 Component Nomenclature

Table 47

Nomenclature Fields and Examples

Field Number

Example for

1

2

3

4

5

6

7

8

9

10

11

DDR2 DRAM

HYB

18

T

256

16

0

A

C

–5

Table 48

Field

1

DDR2 DRAM Nomenclature

Description

Values

Coding

INFINEON

HYB

Constant

Component Prefix

2

3

4

Interface Voltage [V]

DRAM Technology

18

T

SSTL1.8

DDR2

256 Mbit

512 Mbit

1 Gbit

2 Gbit

×4

Component Density [Mbit]

256

512

1G

2G

40

80

16

0 .. 9

A

5+6

Number of I/Os

×8

×16

7

8

Product Variations

Die Revision

look up table

First

B

Second

9

Package,

C

FBGA,

Lead-Free Status

lead-containing

F

FBGA, lead-free

DDR2-533

10

11

Speed Grade

–3.7

–5

DDR2-400

N/A for Components

Data Sheet

97

Rev. 1.1, 2004-09

09112003-LZPT-I17F

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	HYB18T256400AF-3.7
厂家：	Infineon
描述：	DDR DRAM, 64MX4, 0.5ns, CMOS, PBGA60, GREEN, PLASTIC, TFBGA-60 时钟动态存储器双倍数据速率内存集成电路
文件：	总98页 (文件大小：1724K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYB18T256400AF-3.7 [INFINEON]

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