ERJ-3EKF5761V [INFINEON]
16A Highly Integrated SupIRBuck Single-Input Voltage, Synchronous Buck Regulator; 16A高集成度的SupIRBuck单一输入电压同步降压稳压器
| 型号： | ERJ-3EKF5761V |
| 厂家： | 
Infineon |
| 描述： | 16A Highly Integrated SupIRBuck Single-Input Voltage, Synchronous Buck Regulator |
| 文件： | 总49页 (文件大小：2965K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16A Highly Integrated SupIRBuck®
Single-Input Voltage, Synchronous Buck Regulator
IR3448
FEATURES
DESCRIPTION
The IR3448 SupIRBuck® is an easy-to-use, fully
integrated and highly efficient DC/DC regulator. The
onboard PWM controller and MOSFETs make IR3448
a space-efficient solution, providing accurate power
delivery for low output voltage and high current
applications.
Single 5V to 21V application
Wide Input Voltage Range from 1.5V to 21V with
external Vcc
Output Voltage Range: 0.6V to 0.86*PVin
0.5% accurate Reference Voltage
Enhanced line/load regulation with Feed-Forward
Programmable Switching Frequency up to 1.5MHz
Internal Digital Soft-Start
IR3448 is
a
versatile regulator which offers
Enable input with Voltage Monitoring Capability
programmability of switching frequency and current
limit while operating in wide input and output voltage
range.
Remote Sense Amplifier with True Differential
Voltage Sensing
Thermally compensated current limit and Hiccup
Mode Over Current Protection
The switching frequency is programmable from 300
kHz to 1.5MHz for an optimum solution.
Smart LDO to enhance efficiency
External synchronization with Smooth Clocking
Dedicated output voltage sensing for power good
indication and overvoltage protection which
remains active even when Enable is low.
It also features important protection functions, such as
Over Voltage Protection (OVP), Pre-Bias startup,
hiccup current limit and thermal shutdown to give
required system level security in the event of fault
conditions.
Enhanced Pre-Bias Start up
Body Braking to improve transient
Integrated MOSFET drivers and Bootstrap diode
Thermal Shut Down
Post Package trimmed rising edge dead-time
Programmable Power Good Output
Small Size 5mm x 6mm PQFN
APPLICATIONS
Operating Junction Temp: -40oC<Tj<125oC
Lead-free, Halogen-free, and RoHS Compliant
Server Application
Distributed Point of Load Power Architectures
Set Top Box Application
Power Supplies
ORDERING INFORMATION
Base Part
Standard Pack
Quantity
Orderable Part
Number
Package Type
Form
Number
IR3448
IR3448
PQFN 5mm x 6mm
PQFN 5mm x 6mm
Tape and Reel
Tape and Reel
750
IR3448MTR1PBF
IR3448MTRPBF
4000
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August 01, 2013
IR3448
BASIC APPLICATION
Figure 1: IR3448 Basic Application Circuit
Figure 2: Efficiency [Vin=12V, Fsw=600kHz]
PIN DIAGRAM
5mm X 6mm POWER QFN
Top View
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IR3448
FUNCTIONAL BLOCK DIAGRAM
Vin
Smart
LDO
VCC
VCC
THERMAL
SHUTDOWN
TSD
DCM
LGnd
UVcc
FAULT
CONTROL
UVcc
OC
POR
OV
Comp
CByp
VREF
0.6V
+
+
Boot
PVin
SW
E/A
FAULT
-
FB
FB
HDrv
LDrv
VREF
UVcc
DRIVER
OVER
VOLTAGE
+
POR
Vsns
BODY
BREAKING
CONTROL
HDin
LDin
CLK
Intl_SS
PVin
DIGITAL
SOFT
START
POR
FAULT
PGnd
SSOK
ZERO CROSSING
COMPARATOR
ZC
OC
UVEN
Enable
UVEN
UVcc
CONTROL
LOGIC
POR
POR
OVER CURRENT
OCset
-
+
RS-
RS+
VREF
FB
DCM
Rt/Sync
RSo
PGD
Figure 3: IR3448 Simplified Block Diagram
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IR3448
PIN DESCRIPTIONS
PIN #
1
PIN NAME
PVin
PIN DESCRIPTION
Input voltage for power stage. Bypass capacitors between PVin and
PGND should be connected very close to this pin and PGND; also forms
input to feedforward block
2
3
Boot
Supply voltage for high side driver
Enable
Enable pin to turning on and off the IC.
Use an external resistor from this pin to LGND to set the switching
frequency, very close to the pin. This pin can also be used for external
synchronization.
4
Rt/Sync
Current Limit setpoint. This pin allows the trip point to be set to one of
three possible settings by either floating this pin, tying it to VCC or tying it
to PGnd.
5
6
OCset
Vsns
Sense pin for OVP and PGood
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator or to the output of the remote sense amplifier, via
resistor divider to set the output voltage and provide feedback to the
error amplifier.
7
FB
Output of error amplifier. An external resistor and capacitor network is
typically connected from this pin to FB to provide loop compensation.
8
9
COMP
RSo
Remote Sense Amplifier Output
Power ground. This pin should be connected to the system’s power
ground plane. Bypass capacitors between PVin and PGND should be
connected very close to PVIN pin (pin 1) and this pin.
10, 26, 27,
29
PGND
11
12
13
LGND
RS-
Signal ground for internal reference and control circuitry.
Remote Sense Amplifier input. Connect to ground at the load.
Remote Sense Amplifier input. Connect to output at the load.
RS+
Bypassing capacitor for internal reference voltage. A capacitor between
100pF and 180pF should be connected between this pin and LGnd.
14
Cbyp
NC
15, 19, 28,
30, 31, 33
No connection.
Power Good status pin. Output is open drain. Connect a pull up resistor
from this pin to VCC.
16
17
18
PGD
Vin
Input Voltage for LDO.
Bias Voltage for IC and driver section, output of LDO. Add a minimum of
4.7uF bypass cap from this pin to PGnd.
VCC/LDO_out
20, 21, 22,
23, 24, 25,
32
SW
Switch node. This pin is connected to the output inductor.
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IR3448
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin
-0.3V to 25V
Vin
-0.3V to 25V
VCC
SW
BOOT
-0.3V to 8V (Note 1)
-0.3V to 25V (DC), -4V to 25V (AC, 100ns)
-0.3V to 33V
BOOT to SW
Input/Output pins
-0.3V to VCC + 0.3V (Note 2)
-0.3V to 3.9V
RS+, RS-, RSo, PGD, Enable, OCset
PGND to LGND, RS- to LGND
Junction Temperature Range
Storage Temperature Range
-0.3V to 8V (Note 1)
-0.3V to + 0.3V
-40°C to 150°C
-55°C to 150°C
Class A
Machine Model
ESD
Human Body Model
Class 1C
Charged Device Model
Class III
Moisture Sensitivity level
RoHS Compliant
JEDEC Level 3 @ 260°C
Yes
Note:
1. VCC must not exceed 7.5V for Junction Temperature between -10°C and -40°C.
2. Must not exceed 8V.
THERMAL INFORMATION
Thermal Resistance, Junction to Case Top (θJC_TOP
Thermal Resistance, Junction to PCB (pin 29) (θJB)
)
32 °C/W
2.98 °C/W
15.4 °C/W
Thermal Resistance, Junction to Ambient (θJA) (Note 3)
Note:
3. Thermal resistance (θJA) is measured with components mounted on a high effective thermal conductivity
test board.
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IR3448
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
SYMBOL
UNITS
DEFINITION
Input Bus Voltage *
MIN
1.5
5.0
4.5
4.5
0.6
0
MAX
21
PVin
Vin
Supply Voltage
21
VCC
Supply Voltage **
Supply Voltage
7.5
V
Boot to SW
7.5
VO
IO
Output Voltage
0.86 * PVin
±16
Output Current
A
Fs
TJ
Switching Frequency
Junction Temperature
300
-40
1500
125
kHz
°C
*
**
SW node must not exceed 25V
When VCC is connected to an externally regulated supply, also connect Vin.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specification apply over, 1.5V < PVin < 21V, 4.5V< VCC < 7.5V, 0oC < TJ <
125oC.
Typical values are specified at TA = 25oC.
PARAMETER
Power Loss
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Vin = PVin = 12V, VO = 1.2V,
IO = 16A, Fs = 600kHz,
Power Loss
PLOSS
1.94
W
L=0.400uH, TA = 25°C, Note 4
MOSFET Rds(on)
Top Switch
Rds(on)_Top
Rds(on)_Bot
VBoot – VSW = 6.8V, ID = 16A, Tj
= 25°C
6.6
2.2
8.5
2.9
mΩ
Bottom Switch
VCC =6.8V, ID = 16A, Tj = 25°C
Reference Voltage
Feedback Voltage
Accuracy
VFB
0.6
V
0°C < Tj < 105°C
-0.5
-1
+0.5
+1
%
-40°C < Tj < 125°C
Supply Current
Vin Supply Current
(Standby)
Iin(Standby)
Iin(Dyn)
Icc(Standby)
Icc(Dyn)
Vin=21V, Enable low, No
Switching
300
300
425
40
µA
mA
µA
Vin Supply Current (Dyn)
Vin=21V, Enable high, Fs =
600kHz
VCC Supply Current
(Standby)
Enable low, VCC=7V, No
Switching
425
40
VCC Supply Current
(Dyn)
Enable high, VCC=7V, Fs =
600kHz
mA
Under Voltage Lockout
VCC–Start–Threshold
VCC–Stop–Threshold
VCC_UVLO_Start
VCC_UVLO_Stop
VCC Rising Trip Level
VCC Falling Trip Level
4.0
3.8
4.2
3.9
4.4
4.2
V
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IR3448
PARAMETER
SYMBOL
Enable_UVLO_Start
Enable_UVLO_Stop
Ien
CONDITIONS
Supply ramping up
MIN
1.14
0.9
TYP
MAX
1.36
1.06
1
UNIT
Enable–Start–Threshold
Enable–Stop–Threshold
Enable leakage current
1.2
1.0
V
Supply ramping down
Enable=3.3V
µA
V
Oscillator
Rt Voltage
1
Rt=80.6k
Rt=39.2k
Rt=15k
270
540
300
600
1500
330
660
Frequency Range
FS
kHz
1350
1650
PVin=6.8V, PVin(max) slew
rate=1V/us Note 4
1.02
1.8
PVin=12V, PVin(max) slew
rate=1V/us Note 4
Ramp Amplitude
Vramp
Vp-p
PVin=16V, PVin(max) slew
rate=1V/us Note 4
2.4
Ramp Offset
Ramp (os)
Tmin (ctrl)
Note 4
0.16
V
ns
Min Pulse Width
Fixed Off Time
Note 4
50
Note 4
200
200
230
ns
Max Duty Cycle
Dmax
Fs=300kHz, PVin=Vin=12V
Note 4
86
270
100
3
%
Sync Frequency Range
Sync Pulse Duration
Sync Level Threshold
1650
0.6
kHz
ns
High
Low
V
Error Amplifier
Input Offset Voltage
Input Bias Current
Sink Current
Vos_Cbyp
IFb(E/A)
Isink(E/A)
Isource(E/A)
SR
VFb – VREF, VREF = 0.6V
-1.5
-0.5
0.4
4
+1.5
+0.5
1.2
11
%
µA
0.85
7.5
12
mA
mA
V / µs
MHz
dB
Source Current
Slew Rate
Note 4
Note 4
Note 4
7
20
Gain-Bandwidth Product
DC Gain
GBWP
20
30
40
Gain
100
1.7
110
2
120
2.3
100
1.2
Maximum Output Voltage Vmax(E/A)
V
Minimum Output Voltage
Common Mode Voltage
Vmin(E/A)
Vcm_Vp
mV
V
Note 4
0
3
Remote Sense Differential Amplifier
Unity Gain Bandwidth
DC Gain
BW_RS
Note 4
6.4
110
0
9
MHz
dB
Gain_RS
Offset_RS
Note 4
Offset Voltage
VREF=0.6V, 0°C < Tj < 85°C
VREF=0.6V, -40°C < Tj < 125°C
-1.5
-2
1.5
2
mV
mV
Source Current
Sink Current
Slew Rate
Isource_RS
Isink_RS
3
13
1
20
2
mA
0.4
2
mA
Slew_RS
Note 4, Cload = 100pF
4
8
V / µs
7
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IR3448
PARAMETER
RS+ input impedance
RS- input impedance
Maximum Voltage
SYMBOL
Rin_RS+
CONDITIONS
MIN
TYP
MAX
UNIT
kohm
kohm
V
45
63
63
1
85
Rin_RS-
Vmax_RS
Min_RS
Note 4
V(VCC) – V(RSo)
0.5
1.5
Minimum Voltage
50
mV
Internal Digital Soft Start
Soft Start Clock
Clk_SS
Note 4
Note 4
180
0.3
200
0.4
220
0.5
kHz
Soft Start Ramp Rate
Ramp(SS_Start)
mV /
µs
Bootstrap Diode
Forward Voltage
I(Boot) = 30mA
360
520
960
1
mV
µA
Switch Node
SW Leakage Current
Internal Regulator (VCC/LDO)
Output Voltage
lsw
SW = 0V, Enable = 0V
VCC
Vin(min) = 7.2V, Io=0-30mA,
Cload = 2.2uF, DCM=0
6.3
4
6.8
4.4
7.1
4.8
0.7
V
Vin(min) = 7.2V, Io=0-30mA,
Cload = 2.2uF, DCM=1
VCC dropout
VCC_drop
Vin = 7V, Io=70 mA, Cload =
2.2uF
V
mA
s
Short Circuit Current
Ishort
Note 4
Note 4
70
Zero-crossing
Comparator Delay
256 /
Fs
Tdly_zc
Zero-crossing
Comparator Offset
Vos_zc
0
mV
%
Body Braking
BB Threshold
BB_threshold
Fb > Vref, Sw duty cycle, Note 3
0
FAULTS
Power Good
Power Good low upper
threshold
VPG_low(upper)
VPG_low(upper)_Dly
VPG_high(lower)
Vsns Rising
%
VREF
115
1.5
120
2.5
95
125
3.5
Power Good low Upper
Threshold Falling delay
Vsns > VPG_low(upper)
Vsns Rising
µs
Power Good high lower
threshold
%
VREF
Power Good high Lower
Threshold Rising Delay
VPG_high(lower)_Dly Vsns rising
1.28
90
ms
Power Good low lower
threshold
VPG_low(lower)
VPG_low(lower)_Dly
PG (voltage)
Vsns falling
%
VREF
Power Good low lower
Threshold Falling delay
Vsns < VPG_low(lower)
IPGood = -5mA
101
115
150
199
0.5
µs
V
PGood Voltage Low
Over Voltage Protection (OVP)
OVP Trip Threshold OVP (trip)
%
VREF
Vsns Rising
120
125
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IR3448
PARAMETER
SYMBOL
OVP (delay)
CONDITIONS
Vsns rising
MIN
TYP
MAX
UNIT
OVP Fault Prop Delay
1.5
2.5
3.5
µs
Over-Current Protection
OC Trip Current
ITRIP
OCSet=VCC, VCC = 6.8V, TJ =
25°C
18.9
14.8
10.8
21
23.1
18.2
14.2
A
A
OCSet=floating, VCC = 6.8V, TJ
= 25°C
16.5
OCSet=PGnd, VCC =6.8V, TJ =
25°C
12.5
A
Hiccup blanking time
Thermal Shutdown
Thermal Shutdown
Hysteresis
Tblk_Hiccup
Note 4
20.48
ms
Note 4
Note 4
145
20
°C
°C
Notes:
4. Guaranteed by design but not tested in production.
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IR3448
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = 12V, VCC = Internal LDO, Io=0-16A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the
losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves.
The table below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (uH)
0.4
P/N
DCR (mΩ)
0.29
59PR9875N (Vitec)
1.2
0.4
59PR9875N (Vitec)
0.29
1.8
3.3
5.0
0.47
0.88
1.0
7443330047 (Wurth Elektronik)
MPC1040LR88C (NEC/Tokin)
7443330100 (Wurth Elektronik)
0.8
2.3
1.35
10
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IR3448
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, Vin = VCC = 5V, Io=0-16A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of
the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table
below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (uH)
0.4
P/N
DCR (mΩ)
0.29
59PR9875N (Vitec)
1.2
0.4
59PR9875N (Vitec)
0.29
1.8
3.3
5.0
0.47
0.88
1.0
7443330047 (Wurth Elektronik)
MPC1040LR88C (NEC/Tokin)
7443330100 (Wurth Elektronik)
0.8
2.3
1.35
11
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IR3448
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = VCC = 5V, Io=0-16A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the
inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table
below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (uH)
P/N
DCR (mΩ)
0.29
0.3
0.3
0.4
59PR9874N (Vitec)
59PR9874N (Vitec)
59PR9875N (Vitec)
1.2
1.8
0.29
0.29
12
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IR3448
RDSON OF MOSFETS OVER TEMPERATURE
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IR3448
TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
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IR3448
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IR3448
THEORY OF OPERATION
set thresholds. Normal operation resumes once VCC
and Enable rise above their thresholds.
DESCRIPTION
The IR3448 uses a PWM voltage mode control
scheme with external compensation to provide good
noise immunity and maximum flexibility in selecting
inductor values and capacitor types.
The POR (Power On Ready) signal is generated when
all these signals reach the valid logic level (see
system block diagram). When the POR is asserted the
soft start sequence starts (see soft start section).
The switching frequency is programmable from
300kHz to 1.5MHz and provides the capability of
optimizing the design in terms of size and
performance.
ENABLE
The Enable features another level of flexibility for
startup. The Enable has precise threshold which is
internally monitored by Under-Voltage Lockout
(UVLO) circuit. Therefore, the IR3448 will turn on only
when the voltage at the Enable pin exceeds this
threshold, typically, 1.2V.
IR3448 provides precisely regulated output voltage
programmed via two external resistors from 0.6V to
0.86*PVin.
The IR3448 operates with an internal bias supply
(LDO) which is connected to the VCC pin. This allows
operation with single supply. The bias voltage is
variable according to load condition. If the output load
current is less than half of the peak-to-peak inductor
current, a lower bias voltage, 4.4V, is used as the
internal gate drive voltage; otherwise, a higher
voltage, 6.8V, is used.
If the input to the Enable pin is derived from the bus
voltage by a suitably programmed resistive divider, it
can be ensured that the IR3448 does not turn on until
the bus voltage reaches the desired level Figure 4.
Only after the bus voltage reaches or exceeds this
level and voltage at the Enable pin exceeds its
threshold, IR3448 will be enabled. Therefore, in
addition to being a logic input pin to enable the
IR3448, the Enable feature, with its precise threshold,
also allows the user to implement an Under-Voltage
Lockout for the bus voltage (PVin). It can help prevent
the IR3448 from regulating at low PVin voltages that
can cause excessive input current.
This feature helps the converter to reduce power
losses. The device can also be operated with an
external supply from 4.5V to 7.5V, allowing an
extended operating input voltage (PVin) range from
1.0V to 21V. For using the internal LDO supply, the
Vin pin should be connected to PVin pin. If an external
supply is used, it should be connected to VCC pin and
the Vin pin should be shorted to VCC pin.
The device utilizes the on-resistance of the low side
MOSFET (synchronous Mosfet) as current sense
element. This method enhances the converter’s
efficiency and reduces cost by eliminating the need for
external current sense resistor.
IR3448 includes two low Rds(on) MOSFETs using IR’s
HEXFET technology. These are specifically designed
for high efficiency applications.
UNDER-VOLTAGE LOCKOUT AND POR
Figure 4: Normal Start up, device turns on when the
bus voltage reaches 10.2V
The under-voltage lockout circuit monitors the voltage
of VCC pin and the Enable input. It assures that the
MOSFET driver outputs remain in the off state
whenever either of these two signals drops below the
A resistor divider is used at EN pin from PVin to turn
on the device at 10.2V.
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IR3448
...
...
HDRv
LDRv
...
...
...
...
PVin=Vin
Vcc
87.5%
12.5%
16
25%
...
...
...
...
End of
PB
16
> 1.2V
EN
Intl_SS
Vo
Figure 7: Pre-Bias startup pulses
SOFT-START
IR3448 has an internal digital soft-start to control the
output voltage rise and to limit the current surge at the
start-up. To ensure correct start-up, the soft-start
sequence initiates when the Enable and VCC rise
above their UVLO thresholds and generate the Power
On Ready (POR) signal. The internal soft-start
(Intl_SS) signal linearly rises with the rate of 0.4mV/µs
from 0V to 1.5V. Figure 8 shows the waveforms
during soft start. The normal Vout startup time is fixed,
and is equal to:
Figure 5: Recommended startup for Normal operation
Figure 5 shows the recommended startup sequence
for the typical operation of IR3448 with Enable used
as logic input.
PRE-BIAS STARTUP
IR3448 is able to start up into pre-charged output,
which prevents oscillation and disturbances of the
output voltage.
0.75V 0.15V
0.4mV / S
1.5mS
Tstart
(1)
The output starts in asynchronous fashion and keeps
the synchronous MOSFET (Sync FET) off until the
first gate signal for control MOSFET (Ctrl FET) is
generated. Figure 6 shows a typical Pre-Bias condition
at start up. The sync FET always starts with a narrow
pulse width (12.5% of a switching period) and
gradually increases its duty cycle with a step of 12.5%
until it reaches the steady state value. The number of
these startup pulses for each step is 16 and it’s
internally programmed. Figure 7 shows the series of
16x8 startup pulses.
During the soft start the over-current protection (OCP)
and over-voltage protection (OVP) is enabled to
protect the device for any short circuit or over voltage
condition.
POR
3.0V
1.5V
0.75V
[V]
Vo
0.15V
Intl_SS
Pre-Bias
Voltage
Vout
[Time]
t
t
2
t
3
1
Figure 6: Pre-Bias startup
Figure 8: Theoretical operation waveforms during
soft-start
OPERATING FREQUENCY
The switching frequency can be programmed between
300kHz – 1500kHz by connecting an external resistor
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IR3448
from Rt pin to LGnd. Table 1 tabulates the oscillator
frequency versus Rt.
current is sampled approximately 40nS after the start
of the downward slope of the inductor current. When
the sampled current is higher than the OC Limit, an
OC event is detected.
Table 1: Switching Frequency(Fs) vs. External
Resistor(Rt)
When an Over Current event is detected, the
converter enters hiccup mode. Hiccup mode is
performed by latching the OC signal and pulling the
Intl_SS signal to ground for 20.48 mS (typ.). OC
signal clears after the completion of hiccup mode and
the converter attempts to return to the nominal output
voltage using a soft start sequence. The converter will
repeat hiccup mode and attempt to recover until the
overload or short circuit condition is removed.
Freq
Rt (Kꢀ)
(KHz)
80.6
60.4
48.7
39.2
34
300
400
500
600
700
29.4
26.1
23.2
21
19.1
17.4
16.2
15
800
900
Because the IR3448 uses valley current sensing, the
actual DC output current limit will be greater than OC
limit. The DC output current is approximately half of
peak to peak inductor ripple current above selected
OC limit. OC Limit, inductor value, input voltage,
output voltage and switching frequency are used to
calculate the DC output current limit for the converter.
Equation (2) to determine the approximate DC output
current limit.
1000
1100
1200
1300
1400
1500
SHUTDOWN
i
2
IR3448 can be shutdown by pulling the Enable pin
below its 1.0V threshold. During shutdown the high
side and the low side drivers are turned off.
IOCP ILIMIT
(2)
IOCP
ILIMIT
∆i
= DC current limit hiccup point
= Current Limit Valley Point
= Inductor ripple current
OVER CURRENT PROTECTION
The Over Current (OC) protection is performed by
sensing the inductor current through the RDS(on) of the
Synchronous MOSFET. This method enhances the
converter’s efficiency, reduces cost by eliminating a
current sense resistor and any layout related noise
issues. The Over Current (OC) limit can be set to one
of three possible settings by floating the OCset pin, by
pulling up the OCset pin to VCC, or pulling down the
OCset pin to PGnd. The current limit scheme in the
IR3448 uses an internal temperature compensated
current source to achieve an almost constant OC limit
over temperature.
Over Current Protection circuit senses the inductor
current flowing through the Synchronous MOSFET.
To help minimize false tripping due to noise and
transients, inductor current is sampled for about 30 nS
on the downward inductor current slope approximately
12.5% of the switching period before the inductor
current valley. However, if the Synchronous MOSFET
is on for less than 12.5% of the switching period, the
Figure 9: Timing Diagram for Current Limit Hiccup
THERMAL SHUTDOWN
Temperature sensing is provided inside IR3448. The
trip threshold is typically 145oC. When trip threshold is
exceeded, thermal shutdown turns off both MOSFETs
and resets the internal soft start.
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IR3448
Automatic restart is initiated when the sensed
temperature drops within the operating range. There
is a 20oC hysteresis in the thermal shutdown
threshold.
Resistor Divider
RS+ RSo
+
+
FB
-
Vout
RSA
RS-
(< VCC-1.5V)
REMOTE VOLTAGE SENSING
-
True differential remote sensing in the feedback loop
is critical to high current applications where the output
voltage across the load may differ from the output
voltage measured locally across an output capacitor
at the output inductor, and to applications that require
die voltage sensing.
Figure 10: General Remote Sense Configuration
The RS+ and RS- pins of the IR3448 form the inputs
to a remote sense differential amplifier (RSA) with
high speed, low input offset and low input bias current
which ensure accurate voltage sensing and fast
transient response in such applications.
The input range for the differential amplifier is limited
to 1.5V below the VCC rail. Note that IR3448
incorporates a smart LDO which switches the VCC rail
voltage depending on the loading. When determining
the input range assume the part is in light load and
using the lower VCC rail voltage.
Figure 11: Remote Sense Configuration for Vout less
than VCC-1.5V
EXTERNAL SYNCHRONIZATION
IR3448 incorporates an internal phase lock loop (PLL)
circuit which enables synchronization of the internal
oscillator to an external clock. This function is
important to avoid sub-harmonic oscillations due to
beat frequency for embedded systems when multiple
point-of-load (POL) regulators are used. A multi-
function pin, Rt/Sync, is used to connect the external
clock. If the external clock is present before the
converter turns on, Rt/Sync pin can be connected to
the external clock signal solely and no other resistor is
needed. If the external clock is applied after the
converter turns on, or the converter switching
frequency needs to toggle between the external clock
frequency and the internal free-running frequency, an
external resistor from Rt/Sync pin to LGnd is required
to set the free-running frequency.
There are two remote sense configurations that are
usually implemented. Figure 10 shows a general
remote sense (RS) configuration. This configuration
allows the RSA to monitor output voltages above
VCC. A resistor divider is placed in between the
output and the RSA to provide a lower input voltage to
the RSA inputs. Typically, the resistor divider is
calculated to provide VREF (0.6V) across the RSA
inputs which is then outputted to RSo. The input
impedance of the RSA is 63 KOhms typically and
should be accounted for when determining values for
the resistor divider. To account for the input
impedance, assume a 63 KOhm resistor in parallel to
the lower resistor in the divider network.
The
compensation is then designed for 0.6V to match the
RSo value.
When an external clock is applied to Rt/Sync pin after
the converter runs in steady state with its free-running
Low voltage applications can use the second remote
sense configuration. When the output voltage range
is within the RSA input specifications, no resistor
divider is needed in between the converter output and
RSA. The second configuration is shown in Figure
11. The RSA is used as a unity gain buffer and
compensation is determined normally.
frequency,
a
transition from the free-running
frequency to the external clock frequency will happen.
This transition is to gradually make the actual
switching frequency equal to the external clock
frequency, no matter which one is higher. When the
external clock signal is removed from Rt/Sync pin, the
switching frequency is also changed to free-running
gradually. In order to minimize the impact from these
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IR3448
transitions to output voltage, a diode is recommended
to add between the external clock and Rt/Sync pin.
Figure 12 shows the timing diagram of these
transitions.
An internal circuit is used to change the PWM ramp
slope according to the clock frequency applied on
Rt/Sync pin. Even though the frequency of the
external synchronization clock can vary in a wide
range, the PLL circuit keeps the ramp amplitude
constant, requiring no adjustment of the loop
compensation. PVin variation also affects the ramp
amplitude, which will be discussed separately in Feed-
Forward section.
Figure 13: Timing Diagram for Feed-Forward (F.F.)
Function
SMART LOW DROPOUT REGULATOR (LDO)
IR3448 has an integrated low dropout (LDO) regulator
which can provide gate drive voltage for both drivers.
In order to improve overall efficiency over the whole
load range, LDO voltage is set to 6.8V (typ.) at mid- or
heavy load condition to reduce Rds(on) and thus
MOSFET conduction loss; and it is reduced to 4.4V
(typ.) at light load condition to reduce gate drive loss.
Synchronize to the
external clock
Free Running
Frequency
Returntofree-
running freq
...
SW
Gradually change
Gradually change
Fs1
SYNC
Fs1
...
The smart LDO selects its output voltage according to
the load condition by sensing the inductor current (IL).
At light load condition, the inductor current can fall
below zero as shown in Figure 14. A zero crossing
comparator is used to detect when the inductor
current falls below zero at the LDrv Falling Edge. If the
comparator detects zero crossing events for 256
consecutive switching cycles, the smart LDO reduces
its output to 4.4V. The LDO voltage will remain low
until a zero crossing is not detected. Once a zero
crossing is not detected, the counter is reset and LDO
voltage returns to 6.8V. Figure 14 shows the timing
diagram. Whenever the device turns on, LDO always
starts with 6.8V, then goes to 4.4V / 6.8V depending
upon the load condition. However, if only Vin is
applied with Enable low, the LDO output is 4.4V.
Fs2
Figure 12: Timing Diagram for Synchronization
to the external clock (Fs1>Fs2 or Fs1<Fs2)
FEED-FORWARD
Feed-Forward (F.F.) is an important feature, because
it can keep the converter stable and preserve its load
transient performance when PVin varies. The PWM
ramp amplitude (Vramp) is proportionally changed
with PVin to maintain PVin/Vramp almost constant
throughout PVin variation range (as shown in Figure
13). The PWM ramp amplitude is adjusted to 0.15 of
PVin. Thus, the control loop bandwidth and phase
margin can be maintained constant. Feed-forward
function can also minimize impact on output voltage
from fast PVin change. F.F. is disabled when
PVin<6.2V and the PWM ramp is typically 0.9V. For
PVin<6.2V, PVin voltage should be accounted for
when calculating control loop parameters.
Figure 14: Time Diagram for Smart LDO
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IR3448
Users can configure the IR3448 to use a single supply
or dual supplies. Depending on the configuration used
the PVin, Vin and VCC pins are connected differently.
Below several configurations are shown.
In an
internally biased configuration, the LDO draws from
the Vin pin and provides a gate drive voltage, as
shown in Figure 15. By connecting Vin and PVin
together as shown in the Figure 16, IR3448 is an
internally biased single supply configuration that runs
off a single supply.
Figure 17: Externally Biased Configuration
IR3448 can also use an external supply to provide
gate drive voltage for the drivers instead of the
internal LDO. To use an external bias, connected Vin
and VCC to the external bias. PVin can use a
separate rail as shown in Figure 17 or run off the
same rail as Vin and VCC.
When the Vin voltage is below 6.8V, the internal LDO
enters the dropout mode at medium and heavy load.
The dropout voltage increases with the switching
frequency. Figure 18 shows the LDO voltage for
600kHz and 1000kHz switching frequency.
Figure 15: Internally Biased Configuration
Figure 18: LDO_Out Voltage in dropout mode
CBYP
Figure 16: Internally Biased Single Supply
Configuration
This pin reflects the internal reference voltage which is
used by the error amplifier to set the output voltage. In
most operating conditions this pin is only connected to
an external bypass capacitor and it is left floating. A
minimum 100pF ceramic capacitor is required from
stability point of view
POWER GOOD OUTPUT
IR3448 continually monitors the output voltage via the
sense pin (Vsns) voltage. The Vsns voltage is an input
to the window comparator with upper and lower
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IR3448
threshold of OVP(trip) and VPG_high(lower)
respectively. PGood signal is high whenever Vsns
voltage is within the PGood comparator window
thresholds. Hysteresis has been applied to the lower
threshold, PGood signal goes low when Vsns drops
below VPG_low(lower) instead of VPG_high(lower).
The PGood pin is open drain and it needs to be
externally pulled high. High state indicates that output
is in regulation. Figure 19 show the timing diagram of
the PGood signal. Vsns signal is also used by OVP
comparator for detecting output over voltage
condition. PGood signal is low when Enable is low.
Figure 20: Timing Diagram for OVP in non-tracking
mode
BODY BRAKINGTM
The Body Braking feature of the IR3448 allows
improved transient response for step-down load
transients. A severe step-down load transient would
cause an overshoot in the output voltage and drive the
Comp pin voltage down until control saturation occurs
demanding 0% duty cycle and the PWM input to the
Control FET driver is kept OFF. When the first such
skipped pulse occurs, the IR3448 enters Body Braking
mode, wherein the Sync FET also turned OFF. The
inductor current then decays by freewheeling through
the body diode of the Sync FET. Thus, with Body
Braking, the forward voltage drop of the body diode
provides and additional voltage to discharge the
inductor current faster to the light load value as shown
in equation (3) and equation (4) below:
Figure 19: PGood Timing Diagram
OVER-VOLTAGE PROTECTION (OVP)
Over-voltage protection in IR3448 is achieved by
comparing sense pin voltage Vsns to a pre-set
threshold. When Vsns exceeds the over voltage
threshold, an over voltage trip signal asserts after 2.5
uS (typ.) delay. The high side drive signal HDrv is
latched off immediately and PGood flags are set low.
The low side drive signal is kept on until the Vsns
voltage drops below the threshold. HDrv remains
latched off until a reset is performed by cycling VCC.
OVP is active when enable is high or low.
diL
dt
Vo VD
, with body braking
(3)
(4)
L
diL
dt
Vo
, without body braking
L
Vsns voltage is set by the voltage divider connected to
the output and it can be programmed externally.
Figure 20 shows the timing diagram for OVP.
IL
= Inductor current
VD
= Forward voltage drop of the body diode of
the Sync FET.
Vo
L
= output voltage
= Inductor value
The Body Braking mechanism is kept OFF during pre-
bias operation. Also, in the event of an extremely
severe load step-down transient causing OVP, the
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IR3448
Body Brake is overridden by the OVP latch, which
turns on the Sync FET.
0.6V
PVin Fs
12V / S
50nS
MINIMUM ON TIME CONSIDERATIONS
Therefore, at the maximum recommended input
voltage 21V and minimum output voltage, the
The minimum ON time is the shortest amount of time
for Ctrl FET to be reliably turned on. This is very
critical parameter for low duty cycle, high frequency
applications. Conventional approach limits the pulse
width to prevent noise, jitter and pulse skipping. This
results to lower closed loop bandwidth.
converter should be designed at
a
switching
frequency that does not exceed 571 kHz. Conversely,
for operation at the maximum recommended
operating frequency (1.5 MHz) and minimum output
voltage (0.6V). The input voltage (PVin) should not
exceed 8V, otherwise pulse skipping may happen.
IR has developed a proprietary scheme to improve
and enhance minimum pulse width which utilizes the
benefits of voltage mode control scheme with higher
switching frequency, wider conversion ratio and higher
closed loop bandwidth, the latter results in reduction
of output capacitors. Any design or application using
IR3448 must ensure operation with a pulse width that
is higher than the minimum on-time. This is necessary
for the circuit to operate without jitter and pulse-
skipping, which can cause high inductor current ripple
and high output voltage ripple.
MAXIMUM DUTY RATIO
A certain off-time is specified for IR3448. This
provides an upper limit on the operating duty ratio at
any given switching frequency. The off-time remains
at a relatively fixed ratio to switching period in low and
mid frequency range, while in high frequency range
this ratio increases, thus the lower the maximum duty
ratio at which IR3448 can operate. Figure 21 shows a
plot of the maximum duty ratio vs. the switching
frequency with built in input voltage feed forward
mechanism.
Vout
Fs PVin Fs
D
ton
(5)
In any application that uses IR3448, the following
condition must be satisfied:
ton(min) ton
(6)
(7)
Vout
ton(min)
PVin Fs
Vout
PVin Fs
(8)
ton(min)
The minimum output voltage is limited by the
reference voltage and hence Vout(min)
Therefore, for Vout(min) = 0.6V,
=
0.6V.
Vout
PVin Fs
ton(min)
(9)
Figure 21: Maximum duty cycle vs. switching
frequency
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IR3448
TYPICAL OPERATING WAVEFORM
DESIGN EXAMPLE
Output Voltage Programming
Output voltage is programmed by reference voltage
and external voltage divider. The FB pin is the
inverting input of the error amplifier, which is internally
referenced to VREF. The divider ratio is set to equal
VREF at the FB pin when the output is at its desired
value. When an external resistor divider is connected
to the output as shown in Figure 23, the output
voltage is defined by using the following equation:
The following example is a typical application for
IR3448. The application circuit is shown in Figure 28.
Vin = PVin = 12V
Fs = 600kHz
Vo = 1.2V
Io = 16A
Ripple Voltage = ± 1% * Vo
∆Vo = ± 4% * Vo (for 30% load transient)
R
5
Vo Vref 1
(12)
(13)
R6
Enabling the IR3448
As explained earlier, the precise threshold of the
Enable lends itself well to implementation of a UVLO
for the Bus Voltage as shown in Figure 22.
Vref
Vo Vref
R6 R5
For the calculated values of R5 and R6, see feedback
compensation section.
Figure 22: Using Enable pin for UVLO implementation
For a typical Enable threshold of VEN = 1.2 V
Figure 23: Typical application of the IR3448 for
programming the output voltage
R2
PVin(min)
VEN 1.2
(10)
(11)
R1 R2
Bootstrap Capacitor Selection
VEN
To drive the Control FET, it is necessary to supply a
gate voltage at least 4V greater than the voltage at the
SW pin, which is connected to the source of the
Control FET. This is achieved by using a bootstrap
configuration, which comprises the internal bootstrap
diode and an external bootstrap capacitor (C1). The
operation of the circuit is as follows: When the sync
FET is turned on, the capacitor node connected to SW
is pulled down to ground. The capacitor charges
towards Vcc through the internal bootstrap diode
(Figure 24), which has a forward voltage drop VD. The
voltage Vc across the bootstrap capacitor C1 is
approximately given as:
R2 R1
PVin(min) VEN
For PVin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a
good choice.
Programming the frequency
For Fs = 600 kHz, select Rt = 39.2 Kꢀ, using Table 1.
Vc Vcc VD
(14)
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IR3448
When the control FET turns on in the next cycle, the
capacitor node connected to SW rises to the bus
voltage Vin. However, if the value of C1 is
appropriately chosen, the voltage Vc across C1
remains approximately unchanged and the voltage at
the Boot pin becomes:
Ceramic capacitors are recommended due to their
peak current capabilities. They also feature low ESR
and ESL at higher frequency which enables better
efficiency. For this application, it is advisable to have
5x22uF,
25V
ceramic
capacitors,
GRM31CR61E226KE15L from Murata. In addition to
these, although not mandatory, a 1x330uF, 25V SMD
capacitor EEV-FK1E331P from Panasonic may also
be used as a bulk capacitor and is recommended if
the input power supply is not located close to the
converter.
VBoot Vin Vcc VD
(15)
Inductor Selection
Inductors are selected based on output power,
operating frequency and efficiency requirements. A
low inductor value causes large ripple current,
resulting in the smaller size, faster response to a load
transient but may also result in reduced efficiency and
high output noise. Generally, the selection of the
inductor value can be reduced to the desired
maximum ripple current in the inductor (∆i). The
optimum point is usually found between 20% and 50%
ripple of the output current. For the buck converter,
the inductor value for the desired operating ripple
current can be determined using the following relation:
Figure 24: Bootstrap circuit to generate Vc voltage
A bootstrap capacitor of value 0.1uF is suitable for
most applications.
i
t
1
Vin Vo L ;t D
Fs
Input Capacitor Selection
Vo
Vin Vo
(18)
The ripple currents generated during the on time of
the control FETs should be provided by the input
capacitor. The RMS value of this ripple for each
channel is expressed by:
L
Vin i Fs
Where:
Vin = Maximum input voltage
V0 = Output Voltage
∆i = Inductor Ripple Current
Fs = Switching Frequency
IRMS Io D
1 D
(16)
(17)
Vo
D
Vin
∆
D
= On time for Control FET
= Duty Cycle
t
Where:
D is the Duty Cycle
If ∆i ≈ 30%*Io, then the inductor is calculated to be
0.375μH. Select L=0.400μH, 59PR9875N, from Vitec
which provides an inductor suitable for this
application.
IRMS is the RMS value of the input capacitor
current.
Io is the output current.
Io=16A and D = 0.1, the IRMS = 4.8A.
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IR3448
transfer function with the highest 0 dB crossing
frequency and adequate phase margin (greater than
45o).
Output Capacitor Selection
The voltage ripple and transient requirements
determine the output capacitors type and values. The
criterion is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent Series
Inductance (ESL) are other contributing components.
These components can be described as:
The output LC filter introduces a double pole, -
40dB/decade gain slope above its corner resonant
frequency, and a total phase lag of 180o. The resonant
frequency of the LC filter is expressed as follows:
1
FLC
Vo Vo Vo Vo(C)
ESR
ESL
2 Lo Co
(20)
V0(ESR) IL ESR
Figure 25 shows gain and phase of the LC filter. Since
we already have 180o phase shift from the output filter
alone, the system runs the risk of being unstable.
V V
L
IL
o
in
V0(ESL)
V0(C)
ESL
(19)
Phase
Gain
8Co Fs
00
0dB
Where:
-40dB/Decade
Frequency
∆V0 = Output Voltage Ripple
∆IL = Inductor Ripple Current
-900
-1800
Since the output capacitor has a major role in the
overall performance of the converter and determines
the result of transient response, selection of the
capacitor is critical. The IR3448 can perform well with
all types of capacitors.
Frequency
FLC
FLC
Figure 25: Gain and Phase of LC filter
The IR3448 uses a voltage-type error amplifier with
high-gain and high-bandwidth. The output of the
amplifier is available for DC gain control and AC
phase compensation.
As a rule, the capacitor must have low enough ESR to
meet output ripple and load transient requirements.
The goal for this design is to meet the voltage ripple
requirement in the smallest possible capacitor size.
Therefore it is advisable to select ceramic capacitors
due to their low ESR and ESL and small size. Six of
The error amplifier can be compensated either in type
II or type III compensation. Local feedback with Type
II compensation is shown in Figure 26.
TDK
C2012X5R0J476M
(47uF/0805/X5R/6.3V)
capacitors is a good choice.
This method requires that the output capacitor have
enough ESR to satisfy stability requirements. If the
output capacitor’s ESR generates a zero at 5kHz to
50kHz, the zero generates acceptable phase margin
and the Type II compensator can be used.
It is also recommended to use a 0.1µF ceramic
capacitor at the output for high frequency filtering.
Feedback Compensation
The ESR zero of the output capacitor is expressed as
follows:
The IR3448 is a voltage mode controller. The control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast
transient response and accurate output regulation, a
compensation circuit is necessary. The goal of the
compensation network is to provide a closed-loop
1
FESR
(21)
2 ESRCo
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IR3448
VOUT
Use the following equation to calculate R3:
Z IN
CPOLE
C3
Vramp Fo FESR R5
Vin FL2C
R3
R3
(26)
R5
Z f
Where:
Vin = Maximum Input Voltage
osc = Amplitude of the oscillator Ramp Voltage
Fb
E/A
Ve
R6
Comp
V
VREF
Fo = Crossover Frequency
Gain(dB)
FESR = Zero Frequency of the Output Capacitor
H(s) dB
FLC = Resonant Frequency of the Output Filter
β
= (RS+ - RS-) / Vo
R5 = Feedback Resistor
Frequency
FPOLE
FZ
To cancel one of the LC filter poles, place the zero
before the LC filter resonant frequency pole:
Figure 26: Type II compensation network and its
asymptotic gain plot
FZ 75% FLC
1
The transfer function (Ve/Vout) is given by:
FZ 0.75
(27)
2 Lo Co
Z f
Ve
1 sR3C3
H(s)
(22)
Use equation (24), (25) and (26) to calculate C3.
Vout
ZIN
sR5C3
One more capacitor is sometimes added in parallel
with C3 and R3. This introduces one more pole which
is mainly used to suppress the switching noise.
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a
gain and zero, expressed by:
The additional pole is given by:
R3
H(s)
(23)
(24)
R5
1
Fp
(28)
C3 CPOLE
C3 CPOLE
2
1
Fz
2 R3 C3
The pole sets to one half of the switching frequency
First select the desired zero-crossover frequency (Fo):
(25)
which results in the capacitor CPOLE
:
Fo FESR and Fo (1/5 ~1/10) Fs
1
1
CPOLE
(29)
1
R3 FS
R3 FS
C3
For a general unconditional stable solution for any
type of output capacitors with a wide range of ESR
values, we use a local feedback with a type III
compensation
network.
The
typically
used
compensation network for voltage-mode controller is
shown in Figure 27.
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IR3448
VOUT
R5
1
ZIN
FZ1
FZ 2
(34)
(35)
C2
C3
2 R3 C3
C4
R4
R3
1
1
2 C4
R3 R5
2 C4 R5
Zf
Cross over frequency is expressed as:
Fb
Ve
E A
/
R6
Comp
Vin
1
Fo R3 C4
Vramp 2 Lo Co
V
REF
(36)
Gain (dB)
Based on the frequency of the zero generated by the
output capacitor and its ESR, relative to the crossover
frequency, the compensation type can be different.
Table 2 shows the compensation types for relative
locations of the crossover frequency.
|H(s)| dB
Frequency
F
F
F
F
P3
P2
Z1
Z2
Table 2: Different types of compensators
Figure 27: Type III Compensation network and its
asymptotic gain plot
Compensator
Type
Typical Output
Capacitor
FESR vs FO
Again, the transfer function is given by:
FLC < FESR < FO <
FS/2
Type II
Type III
Electrolytic
Z f
Ve
H(s)
SP Cap,
Ceramic
FLC < FO < FESR
Vout
ZIN
By replacing Zin and Zf, according to Figure 27, the
transfer function can be expressed as:
The higher the crossover frequency is, the potentially
faster the load transient response will be. However,
the crossover frequency should be low enough to
allow attenuation of switching noise. Typically, the
control loop bandwidth or crossover frequency (Fo) is
selected such that:
1 sR3C3
1 sC4
R4 R5
H(s)
C2 C3
C2 C3
sR5
C2 C3
1 sR
1 sR C4
3
4
F
1/5 ~1/10 *F
o
s
(30)
The DC gain should be large enough to provide high
DC-regulation accuracy. The phase margin should be
greater than 45o for overall stability.
The compensation network has three poles and two
zeros and they are expressed as follows:
The specifications for designing channel 1:
Vin = 12V
FP1 0
FP2
(31)
1
Vo = 1.2V
(32)
(33)
2 R4 C4
Vramp= 1.8V (This is a function of Vin, pls. see
Feed-Forward section)
Vref = 0.6V
1
1
FP3
2 R3 C2
C2 C3
C2 C3
β
= (RS+ - RS-) / Vo (This assumes the resistor
divider placed between Vout and the RSA
scales down the output voltage to Vref. If the
RSA is not used or Vout is connected directly
2 R3
28
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© 2013 International Rectifier
August 01, 2013
IR3448
to the RSA, β = 1. Please refer to the Remote
Sensing Amplifier section)
Lo = 0.400 µH
2 Fo Lo Co Vosc
C4 Vin
R3
; R3 = 2.57 kꢀ,
Co = 6 x 47µF, ESR≈3mꢀ each
Select: R3 = 2 kꢀ
It must be noted here that the value of the
capacitance used in the compensator design must be
the small signal value. For instance, the small signal
capacitance of the 47µF capacitor used in this design
is 25µF at 1.2 V DC bias and 600 kHz frequency. It is
this value that must be used for all computations
related to the compensation. The small signal value
may be obtained from the manufacturer’s datasheets,
design tools or SPICE models. Alternatively, they may
also be inferred from measuring the power stage
transfer function of the converter and measuring the
double pole frequency FLC and using equation (20) to
compute the small signal Co.
1
C3
; C3 = 10.1 nF,
2 FZ1 R3
Select: C3 = 10 nF
1
C2
; C2 = 206.4 pF,
2 FP3 R3
Select: C2 = 220 pF
These result to:
Calculate R4, R5 and R6:
FLC = 20.55 kHz
F
ESR = 1.87 MHz
1
Fs/2 = 300 kHz
R4
; R4 = 88.8 ꢀ,
Select crossover frequency F0=100 kHz
2 C4 FP2
Since FLC<F0<Fs/2<FESR, Type III is selected to place
the pole and zeros.
Select R4 = 88.7 ꢀ
1
Detailed calculation of compensation Type III:
R5
; R5 = 5.89 kꢀ,
2 C4 FZ 2
Select R5 = 5.76 kꢀ
Vref
Desired Phase Margin Θ = 76°
1 sin
1 sin
FZ 2 Fo
12.3 kHz
814.4 kHz
R6
R5 ; R6 = 5.89 kꢀ,
Vo Vref
1 sin
1 sin
FP2 F
o
Select R6 = 5.76 kꢀ
If (β x Vo) equals Vref, R6 is not used.
Select:
Setting the Power Good Threshold
FZ1 0.5 FZ 2 6.14 kHz and
In this design IR3448, the PGood outer limits are set
at 95% and 120% of VREF. PGood signal is asserted
1.3ms after Vsns voltage reaches 0.95*0.6V=0.57V
(Figure 28). As long as the Vsns voltage is between
the threshold ranges, Enable is high, and no fault
happens, the PGood remains high.
FP3 0.5 F 300 kHz
s
Select C4 = 2.2nF.
Calculate R3, C3 and C2:
The following formula can be used to set the PGood
threshold. Vout (PGood_TH can be taken as 95% of Vout.
)
Choose Rsns1=5.76 Kꢀ.
29
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© 2013 International Rectifier
August 01, 2013
IR3448
Vout_OVP = 1.44 V
V
out(PGood _ TH )
Rsns2
1 Rsns1
(37)
0.95VREF
Selecting Power Good Pull-Up Resistor
The PGood is an open drain output and require pull
up resistors to VCC. The value of the pull-up resistors
should limit the current flowing into the PGood pin to
less than 5mA. A typical value used is 10kꢀ.
Rsns2 = 5.76 kꢀ, Select 5.76 kꢀ.
OVP comparator also uses Vsns signal for Over-
Voltage detection. With above values for Rsns2 and
Rsns1, OVP trip point (Vout_OVP) is
Rsns1 Rsns2
Rsns1
Vout_ OVP VREF 1.2
(38)
30
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© 2013 International Rectifier
August 01, 2013
IR3448
TYPICAL APPLICATION
INTERNALLY BIASED SINGLE SUPPLY
Vin
Ren2
49.9 K
Cpvin1
330uF
Cpvin2
5 x 22uF
Cpvin3
0.1uF
Ren1
7.5 K
Rboot
2
Cboot
0.1uF
En
PVin
Boot
Vo
Co1
0.1 uF
SW
Vin
Lo
0.4uH
Rsns2
5.76 K
Rsns1
5.76 K
Cvin
1uF
Cout
6 x 47uF
VSNS
Vcc
RS+
RS-
Cvcc
10uF
Rpg
10 K
IR3448
OCselect
PGood
CByp
PGood
RSo
Rbode
20
Comp
FB
Cc3
Cc2
10nF
Rc2
2 K
Cc1
2200pF
Rc1
220pF
Rt/Sync
Rfb2
Cbyp
100pF
5.76 K
AGND
PGND
88.7
Rt
39.2 K
Rfb1
5.76 K
Figure 28: Application circuit for a 12V to 1.2V, 16A Point of Load Converter Using the Internal LDO
Suggested Bill of Material for application circuit 12V to 1.2V
Part Reference
Qty
Value
Description
Manufacturer
Part Number
Cpvin1
1
330uF
SMD, electrolytic, 25V, 20%
Panasonic
EEV-FK1E331P
Cpvin2
Cref
Cvin
Cvcc
5
1
1
1
3
1
1
1
6
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
10nF
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
0805, 6.3V, X5R, 20%
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
TDK
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H103KA01D
GRM1885C1H221JA01D
C2012X5R0J476M
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
220pF
47uF
Cout1
11 x 7.2 x 7.5mm,
DCR=0.29mꢀ
L0
1
0.400uH
Vitec
59PR9875N
Rbode
Rboot
Rc1
Rc2
Ren1
1
1
1
1
1
1
20
2
88.7
2K
7.5K
49.9K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 5%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF20R0V
ERJ-3GEYJ2R0V
ERJ-3EKF88R7V
ERJ-3EKF2001V
ERJ-3EKF7501V
ERJ-3EKF4992V
Ren2
Rfb1 Rfb2
Rsns1Rsns1
Rt
4
5.76K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF5761V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
ERJ-3EKF3922V
ERJ-3EKF1002V
Rpg
International
Rectifier
U1
1
IR3448
PQFN 5x6mm
IR3448MPBF
31
www.irf.com
© 2013 International Rectifier
August 01, 2013
IR3448
EXTERNALLY BIASED DUAL SUPPLIES
Figure 29: Application circuit for a 12V to 1.2V, 13A Point of Load Converter using external 5V VCC
Suggested Bill of Material for application circuit 12V to 1.2V using external 5V VCC
Part Reference
Qty
Value
Description
Manufacturer
Part Number
Cpvin1
1
330uF
SMD, electrolytic, 25V, 20%
Panasonic
EEV-FK1E331P
Cpvin2
Cref
Cvin
Cvcc
5
1
1
1
3
1
1
1
6
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
10nF
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
TDK
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H103KA01D
GRM1885C1H201JA01D
C2012X5R0J476M
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
200pF
47uF
Cout1
0805, 6.3V, X5R, 20%
11 x 7.2 x 7.5mm,
DCR=0.29mꢀ
L0
1
0.400uH
Vitec
59PR9875N
Rbode
Rboot
Rc1
Rc2
Ren1
1
1
1
1
1
1
20
2
39.2
2.49K
7.5K
49.9K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 5%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF20R0V
ERJ-3GEYJ2R0V
ERJ-3EKF39R2V
ERJ-3EKF2491V
ERJ-3EKF7501V
ERJ-3EKF4992V
Ren2
Rfb1 Rfb2
Rsns1Rsns1
Rt
4
5.36K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF5361V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
ERJ-3EKF3922V
ERJ-3EKF1002V
Rpg
International
Rectifier
U1
1
IR3448
PQFN 5x6mm
IR3448MPBF
August 01, 2013
32
www.irf.com
© 2013 International Rectifier
IR3448
EXTERNALLY BIASED SINGLE SUPPLY
Vin
Ren2
41.2 K
Cpvin1
330uF
Cpvin2
7 x 22uF
Cpvin3
0.1uF
Ren1
21 K
Rboot
2
0.1uF
En
PVin
Boot
Vo
Co1
0.1 uF
SW
VSNS
RS+
Vin
Lo
0.3uH
Rsns2
7.5 K
Rsns1
7.5 K
Cvin
1uF
Cout
6 x 47 uF
Vcc
Cvcc
10uF
Rpg
10 K
IR3448
RS-
OCselect
PGood
CByp
PGood
RSo
Rbode
20
Comp
FB
Cc3
160pF
Cc2
10nF
Rc2
3 K
Cc1
2200pF
Rc1
Rt/Sync
Rfb2
7.5 K
Cbyp
100pF
AGND
PGND
57.6
Rt
Rfb1
7.5 K
39.2 K
Figure 30: Application circuit for a 5V to 1.2V, 13A Point of Load Converter
Suggested bill of material for application circuit 5V to 1.2V
Part Reference
Qty
Value
Description
Manufacturer
Part Number
Cpvin1
1
330uF
SMD, electrolytic, 25V, 20%
Panasonic
EEV-FK1E331P
Cpvin2
Cref
Cvin
Cvcc
7
1
1
1
3
1
1
1
6
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
10nF
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
0805, 6.3V, X5R, 20%
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
TDK
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H103KA01D
GRM1885C1H161JA01D
C2012X5R0J476M
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
160pF
47uF
Cout1
11 x 7.2 x 7.5mm,
DCR=0.29mꢀ
L0
1
0.300uH
Vitec
59PR9874N
Rbode
Rboot
Rc1
Rc2
Ren1
1
1
1
1
1
1
20
2
57.6
3K
21K
41.2K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 5%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF20R0V
ERJ-3GEYJ2R0V
ERJ-3EKF57R6V
ERJ-3EKF3001V
ERJ-3EKF2102V
ERJ-3EKF4122V
Ren2
Rfb1 Rfb2
Rsns1Rsns1
Rt
4
7.5K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF7501V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
ERJ-3EKF3922V
ERJ-3EKF1002V
Rpg
International
Rectifier
U1
1
IR3448
PQFN 5x6mm
IR3448MPBF
August 01, 2013
33
www.irf.com
© 2013 International Rectifier
IR3448
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=0-16A, Room Temperature, No Air Flow
Figure 31: Startup with full load, Enable Signal
Figure 32: Startup with full load, VCC signal
CH1:Vin, CH2:Vout, CH3:PGood, CH4:Enable
CH1:Vin, CH2:Vout, CH3:PGood, CH4:VCC
Figure 33: Vout Startup with Pre-Bias, 1.05V
Figure 34: Recovery from Hiccup
CH2:Vout, CH3:PGood
CH2:Vout, CH3:PGood, CH4:Iout
Figure 35: Inductor Switch Node at full load
Figure 36: Output Voltage Ripple at full load
CH2:SW
CH1:Vout
34
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© 2013 International Rectifier
August 01, 2013
IR3448
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=1.6A-6.4A, Fs=600kHz, Room Temperature, No air flow
Figure 37: Vout Transient Response, 1.6A to 6.4A step at 2.5A/uSec
CH2:Vout, CH4:Iout
35
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© 2013 International Rectifier
August 01, 2013
IR3448
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=11.2A-16A, Fs=600kHz, Room Temperature, No air flow
Figure 38: Vout Transient Response, 11.2A to 16A step at 2.5A/uSec
CH2:Vout, CH4:Iout
36
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© 2013 International Rectifier
August 01, 2013
IR3448
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=16A, Fs=600kHz, Room Temperature, No air flow
Figure 39: Bode Plot with 16A load: Fo=106 kHz, Phase Margin=55.5 Degrees
37
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© 2013 International Rectifier
August 01, 2013
IR3448
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=0-16A, Fs=600kHz, Room Temperature, No air flow
Figure 40: Efficiency versus load current
Figure 41: Power Loss versus load current
38
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© 2013 International Rectifier
August 01, 2013
IR3448
LAYOUT RECOMMENDATIONS
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to perform
with less than expected results.
pins. It is important to place the feedback components
including feedback resistors and compensation
components close to Fb and Comp pins.
In a multilayer PCB use at least one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are referenced.
The goal is to localize the high current path to a
separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at
a single point. It is recommended to place all the
compensation parts over the analog ground plane in
top layer.
Make the connections for the power components in
the top layer with wide, copper filled areas or
polygons. In general, it is desirable to make proper
use of power planes and polygons for power
distribution and heat dissipation.
The inductor, input capacitors, output capacitors and
the IR3448 should be as close to each other as
possible. This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly at the
PVin pin of IR3448.
The Power QFN is a thermally enhanced package.
Based on thermal performance it is recommended to
use at least a 6-layers PCB. To effectively remove
heat from the device the exposed pad should be
connected to the ground plane using vias. Figure
42a-f illustrates the implementation of the layout
guidelines outlined above, on the IR3448 6-layer
demo board.
The feedback part of the system should be kept away
from the inductor and other noise sources.
The critical bypass components such as capacitors for
PVin, Vin and VCC should be close to their respective
- Ground path between
VIN- and VOUT- should
be minimized with
maximum copper
-
Vout
- Bypass caps should be
placed as close as
PVin
possible to their
connecting pins
- Filled vias placed
under PGND and PVin
pads to help thermal
performance.
- Compensation parts
should be placed
as close as possible
to the Comp pins
- SW node copper is
kept only at the top
layer to minimize the
switching noise
- Single point connection
AGND
PGND
between AGND &
PGND, should be placed
near the part and kept
away from noise sources
Figure 42a: IRDC3448 Demo board Layout Considerations – Top Layer
39
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© 2013 International Rectifier
August 01, 2013
IR3448
Vout
PGND
Figure 42b: IRDC3448 Demo board Layout Considerations – Bottom Layer
PGND
Figure 42c: IRDC3448 Demo board Layout Considerations – Mid Layer 1
Vout
PGND
Figure 42d: IRDC3448 Demo board Layout Considerations – Mid Layer 2
40
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© 2013 International Rectifier
August 01, 2013
IR3448
-Feedback and Vsns traces
routing should be kept away from
noise sources
Vout
PGND
Remote Sense Traces
- tap output where voltage value is
critical.
- Avoid noisy areas and noise coupling.
- RS+ and RS- lines near each other.
- Minimize trace resistance.
Figure 42e: IRDC3448 Demo board Layout Considerations – Mid Layer 3
PGND
Figure 42f: IRDC3448 Demo board Layout Considerations – Mid Layer 4
41
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© 2013 International Rectifier
August 01, 2013
IR3448
PCB METAL AND COMPONENT PLACEMENT
Evaluations have shown that the best overall
performance is achieved using the substrate/PCB
layout as shown in following figures. PQFN devices
should be placed to an accuracy of 0.050mm on both
X and Y axes. Self-centering behavior is highly
dependent on solders and processes, and
experiments should be run to confirm the limits of self-
centering on specific processes. For further
information, please refer to “SupIRBuck® Multi-Chip
Module (MCM) Power Quad Flat No-Lead (PQFN)
Board Mounting Application Note.” (AN1132)
PCB PAD SIZES (DETAIL 1)
PCB PAD SIZES (DETAIL 2)
42
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© 2013 International Rectifier
August 01, 2013
IR3448
PCB PAD SPACING (DETAIL 1)
PCB PAD SPACING (DETAIL 2)
43
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© 2013 International Rectifier
August 01, 2013
IR3448
SOLDER RESIST
IR recommends that the larger Power or Land
However, for the smaller Signal type leads
around the edge of the device, IR
recommends that these are Non Solder Mask
Defined or Copper Defined.
Area pads are Solder Mask Defined (SMD).
This allows the underlying Copper traces to be
as large as possible, which helps in terms of
current carrying capability and device cooling
capability.
When using NSMD pads, the Solder Resist
Window should be larger than the Copper Pad
by at least 0.025mm on each edge, (i.e.
0.05mm in X & Y), in order to accommodate
any layer to layer misalignment.
When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on
each edge) than the Solder Mask window, in
order to accommodate any layer to layer
misalignment. (i.e. 0.1mm in X & Y).
Ensure that the solder resist in-between the
smaller signal lead areas are at least 0.15mm
wide, due to the high x/y aspect ratio of the
solder mask strip.
SOLDER MASK DESIGN
PAD SIZES (DETAIL 1)
SOLDER MASK DESIGN
PAD SIZES (DETAIL 2)
44
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© 2013 International Rectifier
August 01, 2013
IR3448
SOLDER MASK DESIGN
PAD SPACING (DETAIL 1)
SOLDER MASK DESIGN
PAD SPACING (DETAIL 2)
45
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© 2013 International Rectifier
August 01, 2013
IR3448
STENCIL DESIGN
Stencils for PQFN can be used with
Evaluations have shown that the best overall
performance is achieved using the stencil
design shown in following figure. This design
for a stencil thickness of 0.127mm (0.005”).
The reduction should be adjusted for stencils
of other thicknesses.
thicknesses of 0.100-0.250mm (0.004-0.010”).
Stencils thinner than 0.100mm are unsuitable
because they deposit insufficient solder paste
to make good solder joints with the ground
pad; high reductions sometimes create similar
problems. Stencils in the range of 0.125mm-
0.200mm
(0.005-0.008”),
with
suitable
reductions, give best results.
SOLDER PASTE STENCIL
PAD SIZES (DETAIL 1)
SOLDER PASTE STENCIL
PAD SIZES (DETAIL 2)
46
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© 2013 International Rectifier
August 01, 2013
IR3448
SOLDER PASTE STENCIL
PAD SPACING (DETAIL 1)
SOLDER PASTE STENCIL
PAD SPACING (DETAIL 2)
MARKING INFORMATION
Figure 43: Marking Information
47
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© 2013 International Rectifier
August 01, 2013
IR3448
PACKAGING INFORMATION
48
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© 2013 International Rectifier
August 01, 2013
IR3448
ENVIRONMENTAL QUALIFICATIONS
Industrial
Qualification Level
Moisture Sensitivity Level
PQFN
MSL3
Class A
<200V
Machine Model
(JESD22-A115A)
Class 1C
Human Body Model
(JESD22-A114F)
ESD
1000V to <2000V
Class III
Charged Device Model
(JESD22-C101D)
500V to ≤1000V
Yes
RoHS Compliant
Data and specifications subject to change without notice.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
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August 01, 2013
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