CYT2B65CADQ0AZSGS [INFINEON]
TRAVEO™ T2G CYT2B6 Series;型号: | CYT2B65CADQ0AZSGS |
厂家: | Infineon |
描述: | TRAVEO™ T2G CYT2B6 Series |
文件: | 总162页 (文件大小:1183K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CYT2B6
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
General description
CYT2B6 is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as body control units.
CYT2B6 has an Arm® Cortex®-M4 CPU for primary processing and an Arm® Cortex®-M0+ CPU for peripheral and
security processing. These devices contain embedded peripherals supporting Controller Area Network with
Flexible Data rate (CAN FD), and Local Interconnect Network (LIN). TRAVEO™ T2G devices are manufactured on
an advanced 40-nm process. CYT2B6 incorporates a low-power flash memory, multiple high-performance analog
and digital peripherals, and enables the creation of a secure computing platform.
Features
• Dual CPU subsystem
- 80-MHz (max) 32-bit Arm® Cortex®-M4F CPU with
• Single-cycle multiply
• Single-precision floating point unit (FPU)
• Memory protection unit (MPU)
- 80-MHz (max) 32-bit Arm® Cortex®-M0+ CPU with
• Single-cycle multiply
• Memory protection unit
- Inter-processor communication in hardware
- Three DMA controllers
• Peripheral DMA controller #0 (P-DMA0) with 54 channels
• Peripheral DMA controller #1 (P-DMA1) with 26 channels
• Memory DMA controller #0 (M-DMA0) with 2 channels
• Integrated memories
- 576 KB of code-flash with an additional 64 KB of work-flash
• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it
• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
• Flash programming through SWD/JTAG interface
- 64 KB of SRAM with selectable retention granularity
• Crypto engine[1]
- Supports enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
• Using digital signature verification
• Using fast secure boot
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES[2]: 64-bit blocks, 64-bit key
- Vector unit[2] supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic
Curve (ECC)
- SHA-1/2/3[2]: SHA-512, SHA-256, SHA-160 with variable length input data
- CRC[2]: supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo random number generator (PRNG)
- Galois/Counter Mode (GCM)
Notes
1. The Crypto engine features are available on select MPNs.
2. This feature is not available in “eSHE only” parts; for more information, refer to Ordering information.
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
002-25756 Rev. *C
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Features
• Functional safety for ASIL-B
- Memory protection unit (MPU)
- Shared memory protection unit (SMPU)
- Peripheral protection unit (PPU)
- Watchdog timer (WDT)
- Multi-counter watchdog timer (MCWDT)
- Low-voltage detector (LVD)
- Brown-out detector (BOD)
- Overvoltage detection (OVD)
- Clock supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash)
• Low-power 2.7-V to 5.5-V operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power
management
- Configurable options for robust BOD
• Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA
• One threshold level (1.1 V) for BOD on VCCD
• Wakeup support
- A GPIO pin to wakeup from Hibernate mode
- Up to 78 GPIO pins to wakeup from Sleep modes
- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
• Clock sources
- Internal main oscillator (IMO)
- Internal low-speed oscillator (ILO)
- External crystal oscillator (ECO)
- Watch crystal oscillator (WCO)
- Phase-locked loop (PLL)
- Frequency-locked loop (FLL)
• Communication interfaces
- Up to four CAN FD channels
• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and
transceivers
• Compliant to ISO 11898-1:2015
• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD
• ISO 16845:2015 certificate available
- Up to six runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI,
or UART
- Up to five independent LIN channels
• LIN protocol compliant with ISO 17987
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Features
• Timers
- Up to 50 16-bit and two 32-bit timer/counter pulse-width modulator (TCPWM) blocks
• Up to four 16-bit counters for motor control
• Up to 46 16-bit counters and two 32-bit counters for regular operations
• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PW-
M_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes
- Up to 11 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep
• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,
and so on)
• Real time clock (RTC)
- Year/Month/Date, Day-of-week, Hour:Minute:Second fields
- 12- and 24-hour formats
- Automatic leap-year correction
• I/O
- Up to 78 programmable I/Os
- Two I/O types
• GPIO Standard (GPIO_STD)
• GPIO Enhanced (GPIO_ENH)
• Regulators
- Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply
- Two types of regulators
• DeepSleep
• Core internal
• Programmable analog
- Three SAR A/D converters with up to 35 external channels (32 I/Os + 3 I/Os for motor control)
• ADC0 supports 11 logical channels, with 11 + 1 physical connections
• ADC1 supports 13 logical channels, with 13 + 1 physical connections
• ADC2 supports 8 logical channels, with 8 + 1 physical connections
• Any external channel can be connected to any logical channel in the respective SAR
- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps
- Each ADC also supports up to six internal analog inputs like
• Bandgap reference to establish absolute voltage levels
• Calibrated diode for junction temperature calculations
• Two AMUXBUS inputs and two direct connections to monitor supply levels
- Each ADC supports addressing of external multiplexers
- Each ADC has a sequencer supporting autonomous scanning of configured channels
- Synchronized sampling of all ADCs for motor-sense applications
• Smart I/O
- Up to three Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os
- Up to 16 I/Os (GPIO_STD) supported
• Debug interface
- JTAG controller and interface compliant to IEEE-1149.1-2001
- Arm® SWD (serial wire debug) port
- Supports Arm® Embedded Trace Macrocell (ETM) Trace
• Data trace using SWD
• Instruction and data trace using JTAG
Datasheet
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Based on Arm® Cortex®-M4 dual
Features
• Compatible with industry-standard tools
- GHS/MULTI or IAR EWARM for code development and debugging
• Packages
- 64-LQFP, 10 × 10 × 1.7 mm (max), 0.5-mm lead pitch
- 80-LQFP, 12 × 12 × 1.7 mm (max), 0.5-mm lead pitch
- 100-LQFP, 14 × 14 × 1.7 mm (max), 0.5-mm lead pitch
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents...............................................................................................................................5
1 Features list ...................................................................................................................................6
1.1 Communication peripheral instance list ...............................................................................................................8
2 Blocks and functionality..................................................................................................................9
Block diagram...................................................................................................................................9
3 Functional description ..................................................................................................................10
3.1 CPU subsystem .....................................................................................................................................................10
3.2 System resources..................................................................................................................................................11
3.3 Peripherals ............................................................................................................................................................13
3.4 I/Os.........................................................................................................................................................................17
4 CYT2B6 address map .....................................................................................................................19
5 Flash base address map.................................................................................................................21
6 Peripheral I/O map........................................................................................................................22
7 CYT2B6 clock diagram ...................................................................................................................24
8 CYT2B6 CPU start-up sequence ......................................................................................................25
9 Pin assignment .............................................................................................................................26
10 High-speed I/O matrix connections...............................................................................................32
11 Package pin list and alternate functions .......................................................................................33
12 Power pin assignments................................................................................................................35
13 Alternate function pin assignments ..............................................................................................36
14 Pin mux descriptions...................................................................................................................39
15 Interrupts and wake-up assignments............................................................................................41
16 Core interrupt types....................................................................................................................50
17 Trigger multiplexer .....................................................................................................................51
18 Triggers group inputs ..................................................................................................................52
19 Triggers group outputs................................................................................................................63
20 Triggers one-to-one.....................................................................................................................64
21 Peripheral clocks ........................................................................................................................67
22 Faults.........................................................................................................................................69
23 Peripheral protection unit fixed structure pairs.............................................................................72
24 Bus masters................................................................................................................................80
25 Miscellaneous configuration ........................................................................................................81
26 Development support..................................................................................................................82
26.1 Documentation ...................................................................................................................................................82
26.2 Tools ....................................................................................................................................................................82
27 Electrical specifications...............................................................................................................83
27.1 Absolute maximum ratings ................................................................................................................................83
27.2 Device-level specifications .................................................................................................................................87
27.3 DC specifications.................................................................................................................................................88
27.4 Reset specifications ............................................................................................................................................92
27.5 I/O ........................................................................................................................................................................93
27.6 Analog peripherals............................................................................................................................................100
27.7 AC specifications...............................................................................................................................................105
27.8 Digital peripherals.............................................................................................................................................106
27.9 Memory..............................................................................................................................................................116
27.10 System resources............................................................................................................................................118
27.11 Debug ..............................................................................................................................................................129
27.12 Clock specifications ........................................................................................................................................131
28 Ordering information ................................................................................................................ 139
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Table of contents
28.1 Part number nomenclature..............................................................................................................................140
29 Packaging ................................................................................................................................ 142
30 Appendix.................................................................................................................................. 146
30.1 Bootloading or End-of-line Programming.......................................................................................................146
30.2 External IP revisions..........................................................................................................................................147
31 Acronyms ................................................................................................................................. 148
32 Errata ...................................................................................................................................... 150
Revision history ............................................................................................................................ 159
Revision history change log............................................................................................................ 160
Datasheet
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Features list
1
Features list
Table 1-1
CYT2B6 feature list for all packages
Packages
80-LQFP
Features
64-LQFP
100-LQFP
CPU
Core
32-bit Arm® Cortex®-M4F CPU and 32-bit Arm® Cortex®-M0+ CPU
Functional safety
Operating voltage
Core voltage
ASIL-B
2.7 V to 5.5 V
1.05 V to 1.15 V
Arm® Cortex®-M4 80 MHz (max) and Arm® Cortex®-M0+ 80 MHz (max),
related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on)
Operating frequency
MPU, PPU
Supported
FPU
Single precision (32-bit)
DSP-MUL/DIV/MAC
Memory
Supported by Arm® Cortex®-M4F CPU
Code-flash
Work-flash
SRAM (configurable for retention)
ROM
576 KB (448 KB + 128 KB)
64 KB (48 KB + 16 KB)
64 KB
32 KB
Communication interfaces
CAN 0 (CAN FD: Up to 8 Mbps)
CAN 1 (CAN FD: Up to 8 Mbps)
CAN RAM
2 ch
1 ch
2 ch
24 KB per instance (2 ch), 48 KB in total
Serial communication block
(SCB/UART)
6 ch
Serial communication block (SCB/I2C)
Serial communication block (SCB/SPI)
LIN0
5 ch
3 ch
6 ch
6 ch
5 ch
Timers
RTC
1 ch
4 ch
46 ch
2 ch
63
TCPWM (16-bit) (Motor Control)
TCPWM (16-bit)
TCPWM (32-bit)
External interrupts
Analog
49
78
3 Units (SAR0/11, SAR1/13, SAR2/8 logical channels)
22 external channels 28 external channels
32 external channels
12-bit, 1 Msps SAR ADC
(SAR0 8 ch, SAR1 7 ch,
SAR2 7 ch)
(SAR0 10 ch,
(SAR0 11 ch, SAR1 13 ch,
SAR2 8 ch)
SAR1 10 ch, SAR2 8 ch)
18 ch (6 per ADC) Internal sampling
Motor control input
3 ch (synchronous sampling of one channel on each of the 3 ADCs)
Security
Datasheet
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Based on Arm® Cortex®-M4 dual
Features list
Table 1-1
CYT2B6 feature list for all packages (continued)
Features
Packages
80-LQFP
64-LQFP
100-LQFP
Flash security (program/work read
protection)
Supported
Flash chip erase enable
eSHE
Configurable
By separate firmware[3]
System
P-DMA0 with 54 channels (16 general purpose), P-DMA1 with 26
channels (8 general purpose), and M-DMA0 with 2 channels
DMA controller
Internal main oscillator
Internal low-speed oscillator
PLL
8 MHz
32.768 kHz (nominal)
Input frequency: 3.988 to 33.34 MHz, PLL output frequency: up to 80 MHz
Input frequency: 0.25 to 80 MHz, FLL output frequency: up to
80 MHz
FLL
Watchdog timer and multi-counter
watchdog timer
Supported
Clock supervisor
Cyclic wakeup from DeepSleep
GPIO_STD
Supported
Supported
45
59
74
GPIO_ENH
4
3 blocks,
9 I/Os
3 blocks,
14 I/Os
3 blocks,
16 I/Os
Smart I/O (Blocks)
Low-voltage detect
Maximum ambient temperature
Debug interface
Two, 26 selectable levels
105 °C for S-grade and 125 °C for E-grade
SWD/JTAG
Debug trace
Arm® Cortex® -M4 ETB size of 8 KB, Arm® Cortex®-M0+ MTB size of 4 KB
Note
3. Enhanced Secure Hardware Extension (eSHE) is enabled by third-party firmware.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Features list
1.1
Communication peripheral instance list
The following table lists the instances supported under each package for communication peripherals, based on
the minimum pins needed for the functionality.
Table 1-2
Module
CAN0
Peripheral instance list
64-LQFP
80-LQFP
100-LQFP
Minimum pin functions
TX, RX
TX, RX
0/1
0/1
0/1
0/1
0/1
CAN1
0
LIN0
0/1/2/3/4
0/1/3/4/5/7
0/3/4/5/7
0/3/4
0/1/2/3/4
0/1/2/3/4
TX, RX
TX, RX
SCB/UART
SCB/I2C
SCB/SPI
0/1/3/4/5/7
0/1/3/4/5/7
0/1/3/4/5/7
0/1/3/4/5/7
0/1/3/4/5/7
0/1/3/4/5/7
SCL, SDA
MISO, MOSI, SCK, SELECT0
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Blocks and functionality
2
Blocks and functionality
Block diagram
CPU Subsystem
CYT2B6
MXS40-HT
SWJ/ETM/ITM/CTI
SWJ/MTB/CTI
eCT Flash
576 KB Code Flash +
64 KB Work Flash
CRYPTO
AES, SHA, CRC,
TRNG, RSA,
ECC
ASIL-B
SRAM0
64 KB
ROM
32 KB
Arm®
Cortex®-M4
80 MHz
Arm®
Cortex®-M0+
80 MHz
8 KB $
8 KB $
System Resources
SRAM Controller
Initiator/MMIO
ROM Controller
FPU, NVIC, MPU
MUL, NVIC, MPU
Flash Controller
Power
Sleep Control
POR
OVD
BOD
LVD
System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)
Peripheral Interconnect (MMIO, PPU)
REF
PWRSYS-HT
LDO
PCLK
Clock
Clock Control
Prog.
Analog
2xILO
WDT
ECO
CSV
IMO
FLL
SAR
ADC
(12-bit)
1xPLL
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
x3
Analog DFT
SARMUX
32 ch
WCO
RTC
Power Modes
Active/Sleep
LowePowerActive/Sleep
High Speed I/O Matrix, Smart I/O, Boundary Scan
3x Smart I/O
DeepSleep
Up to 74x GPIO_STD, 4x GPIO_ENH
Hibernate
I/O Subsystem
The Block diagram shows the CYT2B6 architecture, giving a simplified view of the interconnection between
subsystems and blocks. CYT2B6 has four major subsystems: CPU, system resources, peripherals, and I/O[4, 5]. The
color-coding shows the lowest power mode where the particular block is still functional.
CYT2B6 provides extensive support for programming, testing, debugging, and tracing of both hardware and
firmware.
Debug-on-chip functionality enables in-system debugging using the production device. It does not require
special interfaces, debugging pods, simulators, or emulators.
The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS.
The debug circuits are enabled by default.
CYT2B6 provides a high level of security with robust flash protection and the ability to disable features such as
debug.
Additionally, each device interface can be permanently disabled for applications concerned with phishing
attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash
programming sequences. All programming, debug, and test interfaces are disabled when maximum device
security is enabled.
Notes
4. GPIO_STD supporting 2.7 V to 5.5 V VDDIO range.
5. GPIO_ENH supporting 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages.
Datasheet
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Functional description
3
Functional description
CPU subsystem
CPU
3.1
3.1.1
The CYT2B6 CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU and a 32-bit Arm® Cortex®-M4F
CPU with MPU, and single-precision FPU. This subsystem also includes P-/M-DMA controllers, a cryptographic
accelerator, 576 KB of code-flash, 64 KB of work-flash, 64 KB of SRAM, and 32 KB of ROM.
The Cortex®-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following
completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,
SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by
an inter-processor communication (IPC) mechanism using hardware semaphores.
3.1.2
DMA controllers
CYT2B6 has three DMA controllers: P-DMA0 with 16 general-purpose and 38 dedicated channels, P-DMA1 with 8
general-purpose and 18 dedicated channels, and M-DMA0 with two channels. P-DMA is used for
peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of
channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.
General-purpose channels have a rich interconnect matrix including P-DMA cross triggering, which enables
demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)
to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high
memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each
channel. They support independent accesses to peripherals using the AHB multi-layer bus.
3.1.3
Flash
CYT2B6 has 576 KB (448 KB with a 32-KB sector size, and 128 KB with an 8-KB sector size) of code-flash with an
additional work-flash of up to 64 KB (48 KB with 2-KB sector size, and 16 KB with 128-B sectors size). Work-flash
is optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW)
operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support
dual-bank operation for over-the-air (OTA) programming.
3.1.4
SRAM
CYT2B6 has 64 KB of SRAM. The SRAM0 controller provides DeepSleep retention in 32-KB increments.
3.1.5
ROM
CYT2B6 has 32-KB ROM that contains boot and configuration routines. This ROM enables secure boot and authen-
tication of user flash to guarantee a secure system.
3.1.6
Cryptography accelerator for security
The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy
check, pseudo random number generation, true random number generation, galois/counter mode, and a vector
unit to support asymmetric key cryptography such as RSA and ECC.
Depending on the part number, this block is either completely or partially available or not available at all. See
Ordering information for more details.
Datasheet
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Functional description
3.2
System resources
Power system
3.2.1
The power system ensures that the supply voltage levels meet the requirements of each power mode, and
provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip
reset during the initial power ramp.
Three BOD circuits monitor the external supply voltages (VDDD, VDDA, VCCD). The BOD on VDDD and VCCD are initially
enabled and cannot be disabled. The BOD on VDDA is initially disabled and can be enabled by the user. For the
external supplies VDDD and VDDA, BOD circuits are software configurable with two settings; a 2.7-V minimum
voltage that is robust for all internal signaling and a 3.0-V minimum voltage, which is also robust for all I/O
specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety measure and is not a
robust detector.
Three overvoltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA, VCCD), and
overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD and
VDDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage. Two voltage-detection circuits are
provided to monitor the external supply voltage (VDDD) for falling and rising levels, each configurable for one of
the 26 selectable levels.
All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic.
The BOD and OVD circuits on VDDA can be configured to generate either a reset or a fault.
3.2.2
Regulators
CYT2B6 contains two regulators that provide power to the low-voltage core transistors: DeepSleep and core
internal. These regulators accept a 2.7–5.5-V VDDD supply and provide a low-noise 1.1-V supply to various parts
of the device. These regulators are automatically enabled and disabled by hardware and firmware when
switching between power modes. The core internal and core external regulators operate in active mode, and
provide power to the CPU subsystem and associated peripherals.
3.2.2.1
DeepSleep
The DeepSleep regulator is used to maintain power to a small number of blocks when in DeepSleep mode. These
blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other configuration
memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal regulator is
disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is disabled.
3.2.2.2
Core internal
The core internal regulator supports load currents up to 150 mA, and is operational during device start-up (boot
process) and in Active/Sleep modes.
3.2.3
Clock system
The CYT2B6 clock system provides clocks to all subsystems that require them, and glitch-free switching between
different clock sources. In addition, the clock system ensures that no metastable conditions occur.
The clock system for CYT2B6 consists of the 8-MHz IMO, two ILOs, three watchdog timers, a PLL, an FLL, five clock
supervisors (CSV), a 3.988- to 33.34 MHz ECO, and a 32.768-kHz WCO.
The clock system supports two main clock domains: CLK_HF and CLK_LF.
• CLK_HFx are the Active mode clocks. Each can use any of the high-frequency clock sources including IMO,
EXT_CLK, ECO, FLL, or PLL
• CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The
reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
Table 3-1
Name
CLK_HF Destinations
Description
CLK_HF0
CLK_HF1
CPUSS clocks, PERI, and AHB infrastructure
Event Generator, also available in HSIOM as an output
3.2.3.1
IMO clock source
The IMO is the frequency reference in CYT2B6 when no external reference is available or enabled. The IMO
operates at a frequency of around 8 MHz.
3.2.3.2
ILO clock source
An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in
DeepSleep mode. There are two ILOs to ensure clock supervisor (CSV) capability in DeepSleep mode. ILO-driven
counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock super-
vision.
3.2.3.3
PLL and FLL
A PLL or FLL may be used to generate high-speed clocks from the IMO, the ECO, or EXT_CLK. The FLL provides a
much faster lock than the PLL (5 µs instead of 35 µs) in exchange for a small amount (±2%) of frequency error[6]
.
3.2.3.4
Clock supervisor (CSV)
Each CSV allows one clock (reference) to supervise the behavior of another clock (monitored). Each CSV has
counters for both the monitored and reference clocks. Parameters for each counter determine the frequency of
the reference clock as well as the upper and lower frequency limits of the monitored clock. If the frequency range
comparator detects a stopped clock or a clock outside the specified frequency range, an abnormal state is
signaled and either a reset or an interrupt is generated.
3.2.3.5
EXT_CLK
One of the two GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be
used as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.
3.2.3.6
ECO
The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.
It supports fundamental mode (non-overtone) quartz crystals, in the range of 3.988 to 33.34 MHz. When used in
conjunction with the PLL, it generates CPU and peripheral clocks up to device’s maximum frequency. ECO
accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the
available I/O functions.
3.2.3.7
WCO
The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external
32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock
reference for CLK_LF, which is the clock source for the MCWDT and RTC.
Note
6. Operation of reference-timed peripherals (like a UART) with an FLL-based reference is not recommended due the allowed frequency
error.
Datasheet
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002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.2.4
Reset
CYT2B6 can be reset from a variety of sources, including software. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT, software reset,
fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and allows software
to determine the cause of the reset. An XRES_L pin is available for external reset.
3.2.5
Watchdog timers
CYT2B6 has one watchdog timer (WDT) and two multi-counter watchdog timers (MCWDT).
The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from
Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT
timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause
register.
An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are
only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used
separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.
3.2.6
Power modes
CYT2B6 has the following power modes:
• Active – all peripherals are available
• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are
available, but with limited capability
• Sleep – all peripherals except the CPUs are available
• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are
available, but with limited capability
• DeepSleep – only peripherals which work with CLK_LF are available
• Hibernate – the device and I/O states are frozen, and the device resets on wakeup
3.3
Peripherals
3.3.1
Peripheral clock dividers
Integer and fractional clock dividers are provided for peripheral and timing purposes.
Table 3-2 Clock dividers
Divider
Count
32
16
Description
div_8
div_16
div_24_5
Integer divider, 8 bits
Integer divider, 16 bits
8
Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)
3.3.2
Peripheral protection unit
The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU,
P-/M-DMA, Crypto, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on the
bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address
range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).
Datasheet
14
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.3.3
12-bit SAR ADC
CYT2B6 contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to 26.67 MHz and provide a 12-bit result
in 26 clock cycles.
The references for all three SAR ADCs come from a dedicated pair of inputs: VREFH and VREFL[7]
.
CYT2B6 devices support up to 53 logical ADC channels, and external inputs from up to 35 I/Os. Each ADC also
supports six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC
and package type) are listed in Table 1-1.
Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with
zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1
Msps whether it is for a single channel or distributed over several channels). The sequencer switching is
controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the
appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates
subsequent conversions for repetitive or group conversions without CPU intervention.
Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32
GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal
signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports
synchronous sampling of one motor-sense channel on each of the three ADCs.
CYT2B6 has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be
sampled by one ADC at a time. Software post processing is required to convert the temperature sensor reading
into kelvin or Celsius values.
To accommodate signals with varying source impedances and frequencies, it is possible to have different sample
times programmed for each channel. Each ADC also supports range comparison, which allows fast detection of
out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate
the measurement for out-of-range values.
The ADCs are not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input
reference voltage VREFH range is 2.7 V to VDDA and VREFL is VSSA
.
3.3.4
Timer/counter/PWM (TCPWM) block
The TCPWM block consists of 16-bit (50 channels) and 32-bit (two channels) counters with a user-programmable
period. Four of the 16-bit counters include extra features to support motor control operations. Each TCPWM
counter contains a capture register to record the count at the time of an event, a period register (used to either
stop or auto-reload the counter when its count is equal to the period register), and compare registers to generate
signals that are used as PWM duty-cycle outputs.
Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,
PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.
In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with
features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead
times for PWM output signals.
The TCPWM block also provides true and complement outputs, with programmable offset between them, to
allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the
PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems
when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time
for software intervention).
Note
7. VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting the measurements. VREF_L, when properly connected, reduces
or removes the impact of IR drops in the VSSIO and VSSA paths from measurements.
Datasheet
15
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.3.5
Serial communication blocks (SCB)
CYT2B6 contains up to six serial communication blocks, each configurable to support I2C, UART, or SPI.
3.3.5.1
I2C interface
An SCB can be configured to implement a full I2C master (capable of multi-master arbitration) or slave interface.
Each SCB configured for I2C can operate at speeds of up to 1 Mbps (Fast-mode Plus[8]) and has flexible buffering
options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB supports FIFO buffering
for receive and transmit data, which, by increasing the time for the CPU to read the data, reduces the need for
clock stretching. The2I2C interface is compatible with Standard, Fast-mode, and Fast-mode Plus devices as
specified in the NXP I C-bus specification and user manual (UM10204). The I2C-bus I/O is implemented with GPIO
in open-drain modes[9, 10]
.
3.3.5.2
UART interface
When configured as a UART, each SCB provides a full-featured UART with maximum signaling rate determined
by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and
SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit multi-
processor mode that allows the addressing of peripherals connected over common Rx and Tx lines. Common
UART functions such as parity, number of stop bits, break detect, and frame error are supported. FIFO buffering
of transmit and receive data allows greater CPU service latencies to be tolerated.
The LIN protocol is supported by the UART. LIN is based on a single-master multi-slave topology. There is one
master node and multiple slave nodes on the LIN bus. The SCB UART supports only LIN slave functionality.
Compared to the dedicated LIN blocks, an SCB/UART used for LIN requires a higher level of software interaction
and increased CPU load.
3.3.5.3
SPI interface
The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start
pulse that is used to synchronize SPI-based Codecs), and National Microwire (a half-duplex form of SPI). The SPI
interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports EZSPI[11]
mode.
SCB0 supports the following additional features:
• Operable as a slave in DeepSleep mode
• I2C slave EZ (EZI2C[12]) mode with up to 256-B data buffer for multi-byte communication without CPU
intervention
• I2C slave externally-clocked operations
• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention
Notes
8. I/Os drive level does not support the full bus capacitance in Fast-mode Plus speeds.
9. This is not 100% compliant with the I2C-bus specification; I/Os are not over-voltage tolerant, do not support the 20-mA sink require-
ment of Fast-mode Plus, and violate the leakage specification when no power is applied.
10.Only Port 0 with the slew rate control enabled meets the minimum fall time requirement.
11.The Easy SPI (EZSPI) protocol is based on the Motorola SPI operating in any mode (0, 1, 2, or 3). It allows communication between
master and slave reduces the need for CPU intervention.
12.The Easy I2C (EZI2C) protocol is a unique communication scheme built on top of the I2C protocol by Infineon. It uses a meta protocol
around the standard I2C protocol to communicate to an I2C slave using indexed memory transfers. This reduces the need for CPU
intervention.
Datasheet
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.3.6
CAN FD
CYT2B6 supports two CAN FD controller blocks, each supporting up to two CAN FD channels. All CAN FD
controllers are compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also
implements the time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2)
completely in hardware.
All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx handler
manages message acceptance filtering, transfer of received messages from the CAN core to a message RAM, and
provides receive-message status. The Tx handler is responsible for the transfer of transmit messages from the
message RAM, to the CAN core, and provides transmit-message status.
3.3.7
Local interconnect network (LIN)
CYT2B6 contains up to five LIN channels. Each channel supports transmission/reception of data following the LIN
protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a 3-pin
interface (including an enable function) and supports master and slave functionality. Each channel also supports
classic and enhanced checksum, along with break detection during message reception and wake-up signaling.
Break detection, sync field, checksum calculations, and error interrupts are handled in hardware.
3.3.8
One-time-programmable (OTP) eFuse
CYT2B6 contains a 1024-bit OTP eFuse memory that can be used to store and access a unique and unalterable
identifier or serial number for each device. eFuses are also used to control the device life-cycle (manufacturing,
programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits, 192 are available
for user purposes.
3.3.9
Event generator
The event generator supports generation of interrupts and triggers in Active mode and interrupts in DeepSleep
mode. The event generators are used to trigger a specific device operation (execution of an interrupt handler, a
SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from DeepSleep mode. They provide
CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions, thus reducing
overall power consumption and processing overhead.
3.3.10
Trigger multiplexer
CYT2B6 supports connecting various peripherals using trigger signals. Triggers are used to inform a peripheral of
the occurrence of an event or change of state. These triggers are used to affect or initiate some action in other
peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers
provide active logic functionality and are typically supported in Active mode.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.4
I/Os
CYT2B6 has up to 78 programmable I/Os.
The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on, and
reset, the I/Os are forced to the High-Z state. During the Hibernate mode, the I/Os are frozen.
Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service
routine (ISR) associated with it.
I/O port power source mapping is listed in Table 3-3. The associated supply determines the VOH, VOL, VIH, and VIL
levels when configured for CMOS and Automotive thresholds.
Table 3-3
I/O port power source
Supply
Ports
VDDD
VDDIO_1
VDDIO_2
P0, P2, P3, P5, P17, P18, P19, P21, P22, P23
P6, P7, P8[13]
P11, P12, P13, P14
Note
13.The I/Os in VDDIO_1 domain are referred to the VDDD domain in 64-LQFP package.
Datasheet
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002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.4.1
Port nomenclature
Px.y describes a particular bit “y” available within an I/O port “x.”
For example, P4.2 reads “port 4, bit 2”.
Each I/O implements the following:
• Programmable drive mode
- High impedance
- Resistive pull-up
- Resistive pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up or pull-down
- Weak pull-up or pull-down
CYT2B6 has two types of programmable I/Os: GPIO standard and GPIO Enhanced.
3.4.2
GPIO Standard (GPIO_STD)
Supports standard automotive signaling across the 2.7-V to 5.5-V VDDIO range. GPIO Standard I/Os have multiple
configurable drive levels, drive modes, and selectable input levels.
3.4.3
GPIO Enhanced (GPIO_ENH)
Supports extended functionality automotive signaling across the 2.7-V to 5.5-V VDDIO range with higher currents
at lower voltages (full I2C timing support, slew-rate control).
Both GPIO_STD and GPIO_ENH implement the following:
• Configurable input threshold (CMOS, TTL, or Automotive)
• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)
• Analog input mode (input and output buffers disabled)
3.4.4
Smart I/O
Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals
coming into the chip. CYT2B6 has three Smart I/O blocks. Operation can be synchronous or asynchronous and
the blocks operate in all device power modes except for the Hibernate mode.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
CYT2B6 address map
4
CYT2B6 address map
The CYT2B6 microcontroller supports the memory spaces shown in Figure 4-1.
• 576 KB (448 KB + 128 KB) of code-flash, used in the single- or dual-bank mode based on the associated bit in the
flash control register
- Single-bank mode - 576 KB
- Dual-bank mode - 288 KB per bank
• 64 KB (48 KB + 16 KB) of work-flash, used in the single- or dual-bank mode based on the associated bit in the
flash control register
- Single-bank mode - 64 KB
- Dual-bank mode - 32 KB per bank
• 64 KB of SRAM (First 2 KB is reserved for internal usage)
• 32 KB of secure ROM
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
CYT2B6 address map
0xFFFF FFFF
ARM System
Space
CPU & Debug Registers
0xE000 0000
0x43FF FFFF
Reserved
Peripheral
Mainly used for on-chip peripherals
e.g., AHB or APB Peripherals
Interconnect or
Memory map
0x4000 0000
Reserved
Reserved
Reserved
Alternate Flash
Supervisory Region
0x1780 7FFF
0x1780 0000
Used to store manufacture specific
data like flash protection settings, trim
settings, device addresses, serial numbers,
calibration data, etc.
Flash Supervisory
Region
0x1700 7FFF
0x1700 0000
0x1400 FFFF
16 KB
(128 B Small Sectors)
0x1400 C000
0x1400 BFFF
Work flash used for long
term data retention
Work flash
48 KB
(2 KB Large Sectors)
0x1400 0000
0x1008 FFFF
Reserved
128 KB
(8 KB Small Sectors)
0x1007 0000
0x1006 FFFF
Mainly used for user program code
Code flash
448 KB
(32 KB Large Sectors)
0x1000 0000
0x0800 FFFF
Reserved
62 KB
General purpose RAM,
mainly used for data
SRAM0
ROM
0x0800 0800
0x0800 0000
2 KB
Secured Boot ROM to set user specified
protection levels, trim and configuration
data, code authentication, jump to user mode etc.
Reserved
0x0000 7FFF
0x0000 0000
32 KB
Figure 4-1
CYT2B6 address map[14, 15]
Notes
14.The size representation is not up to scale.
15.First 2 KB of SRAM is reserved, not available for users. User must keep the power of first 32KB block of SRAM0 in enabled or retained
in all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Flash base address map
5
Flash base address map
Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions
along with their respective base addresses.
Table 5-1
Code-flash Address Mapping in Single Bank Mode
Code-flash Size Large Sectors Small Sectors
Large Sector Base Address Small Sector Base Address
(KB)
(LS)
(SS)
576
32 KB × 14
8 KB × 16
0x1000 0000
0x1007 0000
Table 5-2
Work-flash Address Mapping in Single Bank Mode
Work-flash Size
(KB)
Large Sectors Small Sectors Large Sector Base Address Small Sector Base Address
64
2 KB × 24
128 B × 128
0x1400 0000
0x1400 C000
Table 5-3
Code-flash Address Mapping in Dual Bank Mode (Mapping A)
Second
Half
Second
First Half First Half
Code-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
Half SS
Base
LS Base
Address
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
576
32 KB × 7
8 KB × 8
32 KB × 7
8 KB × 8
0x1000
0000
0x1003
8000
0x1200
0000
0x1203
8000
Table 5-4
Code-flash Address Mapping in Dual Bank Mode (Mapping B)
Second
Half
Second
Half SS
Base
First Half First Half
Code-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
LS Base
Address
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
576
32 KB × 7
8 KB × 8
32 KB × 7
8 KB × 8
0x1200
0000
0x1203
8000
0x1000
0000
0x1003
8000
Table 5-5
Work-flash Address Mapping in Dual Bank Mode (Mapping A)
Second
Half
Second
Half SS
Base
First Half First Half
Work-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
LS Base
Address
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
64
2 KB × 12 128 B × 64 2 KB × 12 128 B × 64
0x1400
0000
0x1400
6000
0x1500
0000
0x1500
6000
Table 5-6
Work-flash Address Mapping in Dual Bank Mode (Mapping B)
Second
Half
Second
Half SS
Base
First Half First Half
Work-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
LS Base
Address
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
64
2 KB × 12 128 B × 64 2 KB × 12 128 B × 64
0x1500
0000
0x1500
6000
0x1400
0000
0x1400
6000
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral I/O map
6
Peripheral I/O map
Table 6-1
Section
CYT2B6 peripheral I/O map
Description
Base Address Instances Instance Size Group Slave
Peripheral interconnect
Peripheral group (0, 1, 2, 3, 5, 6, 9)
Peripheral trigger group
Peripheral 1:1 trigger group
0x4000 0000
0x4000 4000
0x4000 8000
0x4000 C000
7
11
11
0x20
0x400
0x400
PERI
0
0
Peripheral interconnect, master interface 0x4001 0000
PERI_MS PERI Programmable PPU
PERI Fixed PPU
0x4001 0000
0x4001 0800
0x4010 0000
0x4020 0000
0x4021 0000
0x4021 0000
0x4022 0000
0x4022 0000
0x4022 1000
0x4023 0000
6[16]
458
0x40
0x40
0
1
Crypto
CPUSS
Cryptography component
CPU subsystem (CPUSS)
Fault structure subsystem
Fault structures
1
2
0
0
FAULT
2
1
4
0x100
Inter process communication
IPC structures
IPC
8
8
0x20
0x20
2
2
IPC interrupt structures
Protection
Shared memory protection unit struc-
tures
Memory protection unit structures
PROT
0x4023 2000
16
16
0x40
2
2
3
4
0x4023 4000
0x4024 0000
0x400
FLASHC Flash controller
System Resources Subsystem Core
0x4026 0000
Registers
Clock Supervision High Frequency
Clock Supervision Reference Frequency
Clock Supervision Low Frequency
Clock Supervision Internal Low Frequency 0x4026 1730
Multi Counter WDT
Free Running WDT
SRSS Backup Domain/RTC
Backup Register
P-DMA0 Controller
P-DMA0 channel structures
P-DMA1 Controller
P-DMA1 channel structures
M-DMA0 Controller
M-DMA0 channels
eFUSE Customer Data (192 bits)
High-Speed I/O Matrix (HSIOM)
0x4026 1400
0x4026 1710
0x4026 1720
3
1
1
1
2
1
0x10
SRSS
2
5
0x4026 8000
0x4026 C000
0x4027 0000
0x4027 1000
0x4028 0000
0x4028 8000
0x4029 0000
0x4029 8000
0x402A 0000
0x402A 1000
0x402C 0868
0x4030 0000
0x100
BACKUP
P-DMA
2
2
2
2
6
7
8
9
4
0x04
0x40
0x40
54
26
M-DMA
2
6
0x100
0x04
0x10
eFUSE
HSIOM
Note
2
3
10
0
17
16.These six Programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the
device specific TRM to know more about the configuration of these programmable PPUs.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral I/O map
Table 6-1
Section
GPIO
CYT2B6 peripheral I/O map (continued)
Description
Base Address Instances Instance Size Group Slave
GPIO port control/configuration
Programmable I/O configuration
SMARTIO port configuration
Timer/Counter/PWM 0 (TCPWM0)
TCPWM0 Group #0 (16-bit)
TCPWM0 Group #1 (16-bit, Motor control) 0x4038 8000
TCPWM0 Group #2 (32-bit)
Event generator 0 (EVTGEN0)
Event generator 0 comparator structures 0x403F 0800
Local Interconnect Network 0 (LIN0)
LIN0 Channels
CAN0 controller
Message RAM CAN0
CAN1 controller
0x4031 0000
0x4032 0000
0x4032 0C00
0x4038 0000
0x4038 0000
17
0x80
3
1
SMARTIO
3
2
3
0x100
46
4
2
0x80
0x80
0x80
TCPWM
3
3
0x4039 0000
0x403F 0000
EVTGEN
LIN
3
5
5
5
4
0
1
2
11
0x20
0x4050 0000
0x4050 8000
0x4052 0000
0x4053 0000
0x4054 0000
0x4055 0000
5
2
0x100
0x200
0x5FFF
0x200
0x5FFF
TTCANFD
SCB
2
6
Message RAM CAN1
0-7
[NA
2, 6]
Serial Communications Block
(SPI/UART/I2C)
0x4060 0000
0x10000
6
Programmable Analog Subsystem
(PASS0)
0x4090 0000
SAR0 channel controller
SAR1 channel controller
SAR2 channel controller
SAR0 channel structures
SAR1 channel structures
SAR2 channel structures
0x4090 0000
0x4090 1000
0x4090 2000
0x4090 0800
0x4090 1800
0x4090 2800
PASS0
SAR
9
0
11
13
8
0x40
0x40
0x40
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
CYT2B6 clock diagram
7
CYT2B6 clock diagram
IMO
EXT_CLK
ECO
WCO
ILO0
ILO1
LEGEND 1:
LEGEND 2:
ECO
Prescaler
LS
LS
LS
Active Domain
DeepSleep Domain
Hibernate Domain
LS
MUX
LS
MUX
MUX
MUX
MUX
MUX
MUX
FLL
MUX
PLL
MUX
MUX
Relationship of Monitored Clock
and Reference Clock
CLK_ILO0
WDT
RTC
MUX
CLK_BAK
Monitored Clock
CSV
CLK_
PATH0
CLK_
PATH1
CLK_
PATH2
CLK_
PATH3
CLK_REF_HF
CLK_LF
Reference Clock
CLK_ILO0
CSV
MCWDT
MUX
MUX
MUX
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
CSV
CLK_ILO0
CSV
CLK_LF
CSV
CSV
CSV
CLK_HF2
CLK_REF_HF
Event Generator
CLK_HF1
CLK_HF0
ROM/SRAM/FLASH
Divider
(1-256)
Divider
(1-256)
CM4
CLK_FAST
CLK_SLOW
CLK_PERI
CPUSS Fast Infrastructure
Divider
(1-256)
CM0+
CPUSS Slow Infrastructure
P-DMA / M-DMA
CRYPTO
PERI
SRSS
Divider
(1-256)
EFUSE
CLK_GR3
CLK_GR5
Divider
(1-256)
IOSS
TCPWM
CAN FD
LIN
Divider
(1-256)
CLK_GR6
CLK_GR9
SCB[*]
SCB[0]
Serial interface clock
Divider
(1-256)
SAR ADC
PCLK_SMARTIOx_CLOCK
PCLK_TCPWM_CLOCKSx
CPUSS(Trace Clock)
PCLK_CANFDx_CLOCK_CAN
PCLK_LIN_CLOCK_CH_ENx
Peripheral
Clock Dividers
PCLK_SCBx_CLOCK
PCLK_PASS_CLOCK_SARx
PCLK_CPUSS_CLOCK_TRACE_IN
Figure 7-1
CYT2B6 clock diagram
Datasheet
25
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
CYT2B6 CPU start-up sequence
8
CYT2B6 CPU start-up sequence
The start-up sequence is described in the following steps:
1. System Reset (@0x0000 0000)
2. CM0+ executes ROM boot (@0x0000 0004)
i. Applies trims
ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory
flash
iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it
3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000)
i. Debug pins are configured as per the SWD/JTAG spec[17]
ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash
(@0x1000 0000)
iii.CM0+ branches to its Reset handler
4. CM0+ starts execution
i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)
ii. Sets CM4_VECTOR_TABLE_BASE (@0x0000 0200) to the location of CM4 vector table mentioned in flash
(specified in CM4 linker definition file)
iii.Releases CM4 from reset
iv.Continues execution of CM0+ user application
5. CM4 executes directly from either code-flash or SRAM
i. CM4 branches to its Reset handler
ii. Continues execution of CM4 user application
Note
17.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, refer
to Table 11-1 for pin assignments.
Datasheet
26
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
9
Pin assignment
VSSD
P0.0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P17.2
P17.1
P17.0
P14.3
P14.2
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
2
P0.1
3
P0.2
4
P0.3
5
P2.0
6
P2.1
7
P2.2
8
P2.3
9
P3.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P3.1
VDDD
VSSD
P5.0
100-LQFP
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
VDDD
VDDIO_1
Figure 9-1
100-LQFP pin assignment
Datasheet
27
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
VSSD
PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA (1)/SCB0_MISO/LIN1_RX P0.0
PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL (1)/SCB0_MOSI/LIN1_TX P0.1
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/LIN1_EN/CAN0_1_TX P0.2
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX P0.3
PWM_7/TC_7_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA (0)/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1
PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/SCB7_RTS/SCB7_SCL (0)/SCB0_SEL3/SCB7_CLK/LIN0_EN/TRIG_IN[4] P2.2
PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/SCB7_CTS/SCB7_SEL0/TRIG_IN[5] P2.3
PWM_1/TC_1_TR0/TRIG_DBG[0] P3.0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDD
2
P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/TRACE_DATA_3/ADC[2]_7
P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/SCB1_SEL3/TRACE_DATA_2/ADC[2]_6
P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5
P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4
P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3
P18.2 PWM_55/TC_55_TR0/SCB1_RTS/SCB1_SCL/SCB1_CLK/ADC[2]_2
P18.1 PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/FAULT_OUT_1/ADC[2]_1
P18.0 PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P17.2 PWM_H_2_N
PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/TRIG_DBG[1] P3.1
P17.1 PWM_H_2/CAN1_1_RX
VDDD
P17.0 CAN1_1_TX
100-LQFP
VSSD
P14.3 PWM_51/PWM_50_N/TC_51_TR0/TC_50_TR1/ADC[1]_23
P14.2 PWM_50/PWM_49_N/TC_50_TR0/TC_49_TR1/ADC[1]_22
P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/CAN1_0_RX
P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/CAN1_0_TX
P13.7 PWM_47/TC_47_TR0/TRIG_IN[23]
PWM_9/TC_9_TR0 P5.0
PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1 P5.1
PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1 P5.2
PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1 P5.3
PWM_M_0/TC_M_0_TR0/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0 P6.0
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1 P6.1
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/ADC[0]_2 P6.2
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4 P6.4
PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5 P6.5
VDDD
P13.6 PWM_46_N/TC_46_TR1/SCB3_SEL3/TRIG_IN[22]
P13.5 PWM_46/TC_46_TR0/SCB3_SEL2/ADC[1]_17
P13.4 PWM_45_N/TC_45_TR1/SCB3_SEL1/ADC[1]_16
P13.3 PWM_45/TC_45_TR0/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15
P13.2 PWM_44_N/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14
P13.1 PWM_44/TC_44_TR0/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13
P13.0 EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12
VSSD
VDDIO_1
Figure 9-2
100-LQFP pin assignment with alternate functions
Datasheet
28
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
VSSD
P0.0
1
2
P0.1
3
P0.2
4
P0.3
5
P2.0
6
P2.1
7
P2.2
8
P2.3
9
P5.0
10
11
12
13
14
15
16
17
18
19
20
80-LQFP
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
VDDIO_1
Figure 9-3
80-LQFP pin assignment
Datasheet
29
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
VSSD
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDDD
2
P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/TRACE_DATA_3/ADC[2]_7
P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/SCB1_SEL3/TRACE_DATA_2/ADC[2]_6
P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5
P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4
P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3
P18.2 PWM_55/TC_55_TR0/SCB1_RTS/SCB1_SCL/SCB1_CLK/ADC[2]_2
P18.1 PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/FAULT_OUT_1/ADC[2]_1
P18.0 PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0
P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/CAN1_0_RX
P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/CAN1_0_TX
P13.7 PWM_47/TC_47_TR0/TRIG_IN[23]
PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA (1)/SCB0_MISO/LIN1_RX P0.0
PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL (1)/SCB0_MOSI/LIN1_TX P0.1
3
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/LIN1_EN/CAN0_1_TX P0.2
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX P0.3
4
5
PWM_7/TC_7_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA (0)/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1
PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/SCB7_RTS/SCB7_SCL (0)/SCB0_SEL3/SCB7_CLK/LIN0_EN/TRIG_IN[4] P2.2
6
7
8
9
PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/SCB7_CTS/SCB7_SEL0/TRIG_IN[5] P2.3
PWM_9/TC_9_TR0 P5.0
10
11
12
13
14
15
16
17
18
19
20
80-LQFP
PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1 P5.1
PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1 P5.2
P13.6 PWM_46_N/TC_46_TR1/SCB3_SEL3/TRIG_IN[22]
PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1 P5.3
PWM_M_0/TC_M_0_TR0/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0 P6.0
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1 P6.1
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/ADC[0]_2 P6.2
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4 P6.4
PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5 P6.5
VDDIO_1
P13.5 PWM_46/TC_46_TR0/SCB3_SEL2/ADC[1]_17
P13.4 PWM_45_N/TC_45_TR1/SCB3_SEL1/ADC[1]_16
P13.3 PWM_45/TC_45_TR0/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15
P13.2 PWM_44_N/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14
P13.1 PWM_44/TC_44_TR0/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13
P13.0 EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12
VSSD
Figure 9-4
80-LQFP pin assignment with alternate functions
Datasheet
30
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.1
P18.0
P14.2
P14.1
P14.0
P13.3
P13.2
P13.1
P13.0
VSSD
P0.0
P0.1
P0.2
P0.3
P2.0
P2.1
1
2
3
4
5
6
P5.0
P5.1
7
8
64-LQFP
9
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
10
11
12
13
14
15
16
P6.6
VDDD
Figure 9-5
64-LQFP pin assignment
Datasheet
31
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDD
1
2
3
4
5
6
PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA (1)/SCB0_MISO/LIN1_RX P0.0
PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL (1)/SCB0_MOSI/LIN1_TX P0.1
P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/TRACE_DATA_3/ADC[2]_7
P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/SCB1_SEL3/TRACE_DATA_2/ADC[2]_6
P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5
P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/LIN1_EN/CAN0_1_TX P0.2
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX P0.3
PWM_7/TC_7_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA (0)/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1
P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3
P18.1 PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/FAULT_OUT_1/ADC[2]_1
P18.0 PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0
P14.2 PWM_50/PWM_49_N/TC_50_TR0/TC_49_TR1/ADC[1]_22
P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/CAN1_0_RX
P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/CAN1_0_TX
P13.3 PWM_45/TC_45_TR0/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15
P13.2 PWM_44_N/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14
P13.1 PWM_44/TC_44_TR0/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13
P13.0 EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12
7
8
PWM_9/TC_9_TR0 P5.0
PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1 P5.1
64-LQFP
9
PWM_M_0/TC_M_0_TR0/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0 P6.0
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1 P6.1
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/ADC[0]_2 P6.2
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4 P6.4
10
11
12
13
14
PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5 P6.5
15
16
PWM_2_N/TC_2_TR1/SCB4_SEL3/TRIG_IN[8] P6.6
VDDD
VSSD
Figure 9-6
64-LQFP pin assignment with alternate functions
Datasheet
32
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
High-speed I/O matrix connections
10
High-speed I/O matrix connections
Table 10-1
HSIOM connections reference
Name
Number
0
Description
HSIOM_SEL_GPIO
HSIOM_SEL_GPIO_DSI
HSIOM_SEL_DSI_DSI
HSIOM_SEL_DSI_GPIO
HSIOM_SEL_AMUXA
HSIOM_SEL_AMUXB
HSIOM_SEL_AMUXA_DSI
HSIOM_SEL_AMUXB_DSI
HSIOM_SEL_ACT_0
HSIOM_SEL_ACT_1
HSIOM_SEL_ACT_2
HSIOM_SEL_ACT_3
HSIOM_SEL_DS_0
HSIOM_SEL_DS_1
HSIOM_SEL_DS_2
HSIOM_SEL_DS_3
HSIOM_SEL_ACT_4
HSIOM_SEL_ACT_5
HSIOM_SEL_ACT_6
HSIOM_SEL_ACT_7
HSIOM_SEL_ACT_8
HSIOM_SEL_ACT_9
HSIOM_SEL_ACT_10
HSIOM_SEL_ACT_11
HSIOM_SEL_ACT_12
HSIOM_SEL_ACT_13
HSIOM_SEL_ACT_14
HSIOM_SEL_ACT_15
HSIOM_SEL_DS_4
HSIOM_SEL_DS_5
HSIOM_SEL_DS_6
HSIOM_SEL_DS_7
GPIO controls 'out'
Reserved
1
2
3
4
5
6
7
8
9
Active functionality 0
Active functionality 1
Active functionality 2
Active functionality 3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DeepSleep functionality 0
DeepSleep functionality 1
DeepSleep functionality 2
DeepSleep functionality 3
Active functionality 4
Active functionality 5
Active functionality 6
Active functionality 7
Active functionality 8
Active functionality 9
Active functionality 10
Active functionality 11
Active functionality 12
Active functionality 13
Active functionality 14
Active functionality 15
DeepSleep functionality 4
DeepSleep functionality 5
DeepSleep functionality 6
DeepSleep functionality 7
Datasheet
33
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Package pin list and alternate functions
11
Package pin list and alternate functions
Most pins have alternate functionality, as specified in Table 11-1.
Port 11 has the following additional features,
• Ability to pass full-level analog signals to the SAR without clipping to VDDD in cases where VDDD < VDDA
• Ability to simultaneously capture all three ADC signals with highest priority (ADC[0:2]_M)
• Lower noise, for the most sensitive sensors
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O[21]
Package
Name HCon#0[18] 100-LQFP 80-LQFP 64-LQFP HCon#14
DeepSleep mapping[20]
HCon#29
HCon#30
DS #2
Analog/HV
SMART I/O
I/O Type
Pin
Pin
Pin
DS #0[19]
DS #1
P0.0
P0.1
P0.2
P0.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P5.0
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P8.0
P8.1
P8.2
GPIO_ENH
2
2
1
SCB0_MISO
SCB0_MOSI
SCB0_CLK
SCB0_SEL0
SCB0_SEL1
SCB0_SEL2
SCB0_SEL3
GPIO_ENH
GPIO_ENH
GPIO_ENH
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
3
4
3
4
2
3
SCB0_SCL
SCB0_SDA
5
5
4
6
6
5
SWJ_TRSTN
7
7
6
8
8
NA
NA
NA
NA
7
9
9
10
11
14
15
16
17
18
19
20
21
22
23
NA
29
30
31
32
33
34
35
36
37
NA
NA
10
11
12
13
14
15
16
17
18
19
NA
22
23
24
25
NA
NA
26
27
28
8
NA
NA
9
ADC[0]_0
ADC[0]_1
ADC[0]_2
ADC[0]_3
ADC[0]_4
ADC[0]_5
10
11
12
13
14
15
18
19
20
NA
NA
NA
21
22
NA
ADC[0]_8
ADC[0]_9
ADC[0]_11
ADC[0]_12
ADC[0]_17
Notes
18.HCon refers to High Speed I/O matrix connection reference as per Table 10-1.
19.DeepSleep ordering (DS #0, DS #1, DS #2) does not have any impact on choosing any alternate functions; the HSIOM module handles
the individual alternate function assignment.
20.All port pin functions available in DeepSleep mode are also available in Active mode.
21.Refer to Table 14-1 for more information on pin multiplexer abbreviations used.
Datasheet
34
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Package pin list and alternate functions
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O[21]
Package
Name HCon#0[18] 100-LQFP 80-LQFP 64-LQFP HCon#14
DeepSleep mapping[20]
HCon#29
HCon#30
DS #2
Analog/HV
SMART I/O
I/O Type
GPIO_STD
GPIO_STD
Pin
38
Pin
29
Pin
23
DS #0[19]
DS #1
P11.0
P11.1
P11.2
P12.0
P12.1
P12.2
P12.3
P12.4
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
P14.0
P14.1
P14.2
P14.3
P17.0
P17.1
P17.2
P18.0
P18.1
P18.2
P18.3
P18.4
P18.5
P18.6
P18.7
P19.0
P19.1
P19.2
P19.3
P21.0
P21.1
P21.2
P21.3
P21.5
P22.0
ADC[0]_M
ADC[1]_M
ADC[2]_M
ADC[1]_4
ADC[1]_5
ADC[1]_6
ADC[1]_7
ADC[1]_8
39
30
24
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
40
45
46
47
48
49
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
77
78
79
80
81
82
83
84
90
91
31
36
37
38
39
NA
42
43
44
45
46
47
48
49
50
51
NA
NA
NA
NA
NA
52
53
54
55
56
57
58
59
62
63
NA
NA
64
65
66
67
NA
73
25
30
31
NA
NA
NA
34
35
36
37
NA
NA
NA
NA
38
39
40
NA
NA
NA
NA
41
42
NA
43
44
45
46
47
NA
NA
NA
NA
50
51
52
53
NA
59
SMARTIO12_0
SMARTIO12_1
SMARTIO12_2
SMARTIO12_3
SMARTIO12_4
SMARTIO13_0
SMARTIO13_1
SMARTIO13_2
SMARTIO13_3
SMARTIO13_4
SMARTIO13_5
SMARTIO13_6
SMARTIO13_7
SMARTIO14_0
SMARTIO14_1
SMARTIO14_2
ADC[1]_12
ADC[1]_13
ADC[1]_14
ADC[1]_15
ADC[1]_16
ADC[1]_17
ADC[1]_22
ADC[1]_23
ADC[2]_0
ADC[2]_1
ADC[2]_2
ADC[2]_3
ADC[2]_4
ADC[2]_5
ADC[2]_6
ADC[2]_7
[22]
WCO_IN
[22]
WCO_OUT
[22]
ECO_IN
ECO_OUT
[22]
Notes
22.I/O pins that support an oscillator function (WCO or ECO) must be configured for high-impedance if the oscillator is enabled.
23.This I/O has increased leakage to ground when the VDDD supply is below the POR threshold.
Datasheet
35
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Power pin assignments
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O[21]
Package
Name HCon#0[18] 100-LQFP 80-LQFP 64-LQFP HCon#14
DeepSleep mapping[20]
HCon#29
HCon#30
DS #2
Analog/HV
SMART I/O
I/O Type
GPIO_STD
GPIO_STD
Pin
92
Pin
74
Pin
NA
DS #0[19]
DS #1
P22.1
P22.2
P22.3
P23.3
P23.4
93
NA
NA
GPIO_STD
GPIO_STD
GPIO_STD
94
95
96
NA
75
76
NA
60
61
SWJ_SWO_
TDO
P23.5
P23.6
P23.7
GPIO_STD
GPIO_STD
GPIO_STD
97
98
99
77
78
79
62
63
64
SWJ_SWCLK_TCLK
SWJ_SWDIO_TMS
SWJ_SWDOE_TDI
HIBERNATE_WAKEUP[1]
12
Power pin assignments
Table 12-1
Power pin assignments
Packages
Name
Remarks
64-LQFP
80-LQFP
100-LQFP
VDDD
VSSD
55, 48, 16
80, 69, 60
100, 86, 75, 24, 12 Main digital supply
57, 56, 49, 33, 17 71, 70, 61, 41, 88, 87, 76, 51, 27, 26, Main digital ground
21, 1
20
13, 1
25
VDDIO_1
VDDIO_2
VCCD[24]
NA
32
58
I/O supply for analog I/Os (except analog
I/Os on VDDA
)
40
72
50
I/O supply for analog I/Os (except analog
I/Os on VDDA), P11
89, 28
Main regulated supply. Driven by LDO
regulator
VREFH
VREFL
VDDA
VSSA
XRES_L
29
26
28
27
54
35
32
34
33
68
44
41
43
42
85
High reference voltage for SAR ADCs
Low reference voltage for SAR ADCs
Main analog supply for SAR ADCs
Main analog ground
Active LOW external reset input
Note
24.The VCCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure 27-2).
Datasheet
36
002-25756 Rev. *C
2022-10-07
13
Alternate function pin assignments
Table 13-1
Alternate pin functions in Active mode
Active mapping
HCon#17
Name
HCon#8[25]
ACT #0[26]
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
HCon#21
ACT #9
HCon#26
ACT #14
HCon#27
ACT #15
ACT #1
ACT #2
ACT #3
ACT #5
ACT #8
P0.0 PWM0_18
P0.1 PWM0_17
P0.2 PWM0_14
P0.3 PWM0_13
P2.0 PWM0_7
P2.1 PWM0_6
P2.2 PWM0_5
P2.3 PWM0_4
P3.0 PWM0_1
P3.1 PWM0_0
P5.0 PWM0_9
P5.1 PWM0_10
P5.2 PWM0_11
P5.3 PWM0_12
P6.0 PWM0_M_0
P6.1 PWM0_0
P6.2 PWM0_M_1
P6.3 PWM0_1
P6.4 PWM0_M_2
P6.5 PWM0_2
P6.6
PWM0_22_N
TC0_18_TR0
TC0_22_TR1
SCB0_RX
SCB0_TX
SCB0_RTS
SCB0_CTS
SCB7_RX
SCB7_TX
SCB7_RTS
SCB7_CTS
SCB7_SDA (1)
LIN1_RX
PWM0_18_N
PWM0_17_N
PWM0_14_N
TC0_17_TR0
TC0_14_TR0
TC0_13_TR0
TC0_7_TR0
TC0_6_TR0
TC0_5_TR0
TC0_4_TR0
TC0_1_TR0
TC0_0_TR0
TC0_9_TR0
TC0_10_TR0
TC0_11_TR0
TC0_12_TR0
TC0_M_0_TR0
TC0_0_TR0
TC0_M_1_TR0
TC0_1_TR0
TC0_M_2_TR0
TC0_2_TR0
TC0_18_TR1
TC0_17_TR1
TC0_14_TR1
SCB7_SCL (1)
LIN1_TX
LIN1_EN
CAN0_1_TX
CAN0_1_RX
CAN0_0_TX
CAN0_0_RX
SCB7_MISO
SCB7_MOSI
SCB7_CLK
SCB7_SEL0
LIN0_RX
LIN0_TX
LIN0_EN
TRIG_IN[2]
TRIG_IN[3]
TRIG_IN[4]
TRIG_IN[5]
PWM0_7_N
PWM0_6_N
PWM0_5_N
TC0_7_TR1
TC0_6_TR1
TC0_5_TR1
SCB7_SDA (0)
SCB7_SCL (0)
TRIG_DBG[0]
TRIG_DBG[1]
PWM0_1_N
TC0_1_TR1
PWM0_9_N
PWM0_10_N
PWM0_11_N
TC0_9_TR1
TC0_10_TR1
TC0_11_TR1
SCB4_RX
SCB4_TX
SCB4_RTS
SCB4_CTS
SCB4_MISO
SCB4_MOSI
SCB4_CLK
SCB4_SEL0
SCB4_SEL1
SCB4_SEL2
SCB4_SEL3
SCB5_MISO
SCB5_MOSI
SCB5_CLK
LIN3_RX
LIN3_TX
LIN3_EN
LIN4_RX
LIN4_TX
LIN4_EN
PWM0_M_0_N
PWM0_0_N
TC0_M_0_TR1
TC0_0_TR1
SCB4_SDA
SCB4_SCL
PWM0_M_1_N
PWM0_1_N
TC0_M_1_TR1
TC0_1_TR1
CAL_SUP_NZ
PWM0_M_2_N
PWM0_2_N
TC0_M_2_TR1
TC0_2_TR1
TRIG_IN[8]
P7.0 PWM0_M_4
P7.1 PWM0_15
P7.2
TC0_M_4_TR0
TC0_15_TR0
SCB5_RX
SCB5_TX
SCB5_RTS
LIN4_RX
LIN4_TX
LIN4_EN
PWM0_M_4_N
PWM0_15_N
TC0_M_4_TR1
TC0_15_TR1
SCB5_SDA
SCB5_SCL
Notes
25.High Speed I/O matrix connection (HCon) reference as per Table 10-1.
26.Active Mode ordering (ACT#0, ACT#1, and so on) does not have any impact on configuring alternate functions; the HSIOM module handles the alternate function assignments.
27.Refer to Table 14-1 for more information on pin multiplexer abbreviations used.
28.For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group "n".
Table 13-1
Alternate pin functions in Active mode (continued)
Active mapping
HCon#17
Name
HCon#8[25]
ACT #0[26]
HCon#9
ACT #1
HCon#10
HCon#11
ACT #3
HCon#16
ACT #4
HCon#18
ACT #6
HCon#19
HCon#20
ACT #8
HCon#21
ACT #9
HCon#26
ACT #14
HCon#27
ACT #15
ACT #2
ACT #5
ACT #7
P7.3 PWM0_16
P7.4
TC0_16_TR0
SCB5_CTS
SCB5_SEL0
PWM0_16_N
TC0_16_TR1
SCB5_SEL1
SCB5_SEL2
P7.5 PWM0_17
P8.0 PWM0_19
P8.1 PWM0_20
P8.2 PWM0_21
P11.0
TC0_17_TR0
TC0_19_TR0
TC0_20_TR0
TC0_21_TR0
LIN2_RX
LIN2_TX
LIN2_EN
CAN0_0_TX
CAN0_0_RX
PWM0_19_N
PWM0_20_N
TC0_19_TR1
TC0_20_TR1
TRIG_IN[14]
TRIG_IN[15]
P11.1
P11.2
P12.0 PWM0_36
P12.1 PWM0_37
P12.2 PWM0_38
P12.3 PWM0_39
P12.4 PWM0_40
P13.0
TC0_36_TR0
TC0_37_TR0
TC0_38_TR0
TC0_39_TR0
TC0_40_TR0
TRIG_IN[20]
TRIG_IN[21]
PWM0_36_N
PWM0_37_N
PWM0_38_N
PWM0_39_N
TC0_36_TR1
TC0_37_TR1
TC0_38_TR1
TC0_39_TR1
EXT_MUX[1]_EN
EXT_MUX[1]_0
EXT_MUX[1]_1
EXT_MUX[2]_0
EXT_MUX[2]_1
EXT_MUX[2]_2
EXT_MUX[2]_EN
SCB3_RX
SCB3_MISO
SCB3_MOSI
SCB3_CLK
SCB3_SEL0
SCB3_SEL1
SCB3_SEL2
SCB3_SEL3
P13.1 PWM0_44
P13.2
TC0_44_TR0
TC0_45_TR0
TC0_46_TR0
SCB3_TX
SCB3_RTS
SCB3_CTS
SCB3_SDA
SCB3_SCL
PWM0_44_N
PWM0_45_N
PWM0_46_N
TC0_44_TR1
TC0_45_TR1
TC0_46_TR1
P13.3 PWM0_45
P13.4
P13.5 PWM0_46
P13.6
TRIG_IN[22]
TRIG_IN[23]
P13.7 PWM0_47
P14.0 PWM0_48
P14.1 PWM0_49
P14.2 PWM0_50
P14.3 PWM0_51
P17.0
TC0_47_TR0
TC0_48_TR0
TC0_49_TR0
TC0_50_TR0
TC0_51_TR0
PWM0_47_N
PWM0_48_N
PWM0_49_N
PWM0_50_N
TC0_47_TR1
TC0_48_TR1
TC0_49_TR1
TC0_50_TR1
CAN1_0_TX
CAN1_0_RX
CAN1_1_TX
CAN1_1_RX
P17.1
PWM0_H_2
P17.2
PWM0_H_2_N
PWM0_H_0
P18.0
SCB1_RX
SCB1_TX
SCB1_MISO
SCB1_MOSI
FAULT_OUT_0
FAULT_OUT_1
P18.1
PWM0_H_0_N
SCB1_SDA
Table 13-1
Alternate pin functions in Active mode (continued)
Active mapping
HCon#17
Name
HCon#8[25]
ACT #0[26]
HCon#9
ACT #1
HCon#10
HCon#11
ACT #3
HCon#16
ACT #4
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
ACT #9
HCon#26
ACT #14
HCon#27
ACT #15
ACT #2
ACT #5
P18.2 PWM0_55
P18.3 PWM0_54
P18.4 PWM0_53
P18.5 PWM0_52
P18.6 PWM0_51
P18.7 PWM0_50
P19.0
TC0_55_TR0
SCB1_RTS
SCB1_CTS
SCB1_SCL
SCB1_CLK
PWM0_55_N
PWM0_54_N
PWM0_53_N
PWM0_52_N
PWM0_51_N
PWM0_50_N
TC0_54_TR0
TC0_53_TR0
TC0_52_TR0
TC0_51_TR0
TC0_50_TR0
TC0_55_TR1
TC0_54_TR1
TC0_53_TR1
TC0_52_TR1
TC0_51_TR1
TC0_50_TR1
SCB1_SEL0
SCB1_SEL1
SCB1_SEL2
SCB1_SEL3
TRACE_CLOCK
TRACE_DATA_0
TRACE_DATA_1
TRACE_DATA_2
TRACE_DATA_3
FAULT_OUT_2
FAULT_OUT_3
PWM0_H_2
PWM0_H_2_N
TC0_H_0_TR0
TC0_H_0_TR1
P19.1 PWM0_26
P19.2
TC0_26_TR0
PWM0_26_N
TC0_26_TR1
TRIG_IN[28]
TRIG_IN[29]
P19.3
P21.0 PWM0_42
P21.1 PWM0_41
P21.2 PWM0_40
P21.3 PWM0_39
P21.5 PWM0_37
P22.0 PWM0_34
P22.1 PWM0_33
P22.2
TC0_42_TR0
TC0_41_TR0
TC0_40_TR0
TC0_39_TR0
TC0_37_TR0
TC0_34_TR0
TC0_33_TR0
PWM0_42_N
PWM0_41_N
PWM0_40_N
TC0_42_TR1
TC0_41_TR1
TC0_40_TR1
EXT_CLK
TRIG_DBG[1]
CAN1_1_TX
CAN1_1_RX
PWM0_34_N
PWM0_33_N
TC0_34_TR1
TC0_33_TR1
P22.3
P23.3
TRIG_IN[30]
TRIG_IN[31]
FAULT_OUT_3
TRIG_DBG[0]
P23.4 PWM0_25
P23.5 PWM0_24
P23.6 PWM0_23
P23.7 PWM0_22
TC0_25_TR0
TC0_24_TR0
TC0_23_TR0
TC0_22_TR0
PWM0_25_N
PWM0_24_N
PWM0_23_N
TC0_25_TR1
TC0_24_TR1
TC0_23_TR1
EXT_CLK
CAL_SUP_NZ
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin mux descriptions
14
Pin mux descriptions
Table 14-1
Pin mux descriptions
Sl.
Pin
Module
Description
No.
1
2
3
4
5
6
7
8
9
PWMx_y
PWMx_y_N
TCPWM
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR line
out, x-TCPWM block, y-counter number
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR
complementary line out (N), x-TCPWM block, y-counter number
TCPWM 16-bit PWM with motor control line out, x-TCPWM block,
y-counter number
TCPWM 16-bit PWM with motor control complementary line out (N),
x-TCPWM block, y-counter number
TCPWM 32-bit PWM, PWM_DT and PWM_PR line out, x-TCPWM
block, y-counter number
TCPWM 32-bit PWM, PWM_DT and PWM_PR complementary line out
(N), x-TCPWM block, y-counter number
TCPWM 16-bit dedicated counter input triggers, x-TCPWM block,
y-counter number, z-trigger number
TCPWM 16-bit dedicated counter input triggers with motor control,
x-TCPWM block, y-counter number, z-trigger number
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM
PWMx_M_y
PWMx_M_y_N
PWMx_H_y
PWMx_H_y_N
TCx_y_TRz
TCx_M_y_TRz
TCx_H_y_TRz
TCPWM 32-bit dedicated counter input triggers, x-TCPWM block,
y-counter number, z-trigger number
10 SCBx_RX
SCB
UART Receive, x-SCB block
11 SCBx_TX
SCB
UART Transmit, x-SCB block
12 SCBx_RTS
13 SCBx_CTS
14 SCBx_SDA
15 SCBx_SCL
16 SCBx_MISO
17 SCBx_MOSI
18 SCBx_CLK
19 SCBx_SELy
20 LINx_RX
SCB
SCB
SCB
SCB
SCB
SCB
SCB
SCB
UART Request to Send (Handshake), x-SCB block
UART Clear to Send (Handshake), x-SCB block
I2C Data line, x-SCB block
I2C Clock line, x-SCB block
SPI Master Input Slave Output, x-SCB block
SPI Master Output Slave Input, x-SCB block
SPI Serial Clock, x-SCB block
SPI Slave Select, x-SCB block, y-select line
LIN Receive line, x-LIN block
LIN
21 LINx_TX
LIN
LIN Transmit line, x-LIN block
22 LINx_EN
LIN
LIN Enable line, x-LIN block
23 CANx_y_TX
24 CANx_y_RX
25 CAL_SUP_NZ
26 FAULT_OUT_x
27 TRACE_DATA_x
28 TRACE_CLOCK
29 RTC_CAL
CANFD
CANFD
CPUSS
SRSS
SRSS
SRSS
CAN Transmit line, x-CAN block, y-channel number
CAN Receive line, x-CAN block, y-channel number
ETAS Calibration support line
Fault output line x-0 to 3
Trace dataout line x-0 to 3
Trace clock line
SRSS RTC RTC calibration clock input
30 SWJ_TRSTN
31 SWJ_SWO_TDO
SRSS
SRSS
JTAG Test reset line (Active low)
JTAG Test data output/SWO (Serial Wire Output)
Datasheet
40
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin mux descriptions
Table 14-1
Pin mux descriptions (continued)
Sl.
Pin
Module
Description
No.
32 SWJ_SWCLK_TCLK
33 SWJ_SWDIO_TMS
34 SWJ_SWDOE_TDI
SRSS
SRSS
SRSS
SRSS
JTAG Test clock/SWD clock (Serial Wire Clock)
JTAG Test mode select/SWD data (Serial Wire Data Input/Output)
JTAG Test data input
35 HIBER-
Hibernate wakeup line x-0 to 1
NATE_WAKEUP[x]
36 ADC[x]_y
37 ADC[x]_M
38 EXT_MUX[x]_y
39 EXT_MUX[x]_EN
PASS SAR SAR, channel, x-SAR number, y-channel number
PASS SAR SAR motor control input, x-SAR number
PASS SAR External SAR MUX inputs, x-MUX number, y-MUX input 0 to 2
PASS SAR External SAR MUX enable line
Datasheet
41
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
15
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources
Source Power Mode
Interrupt
Description
0
1
2
3
4
5
6
7
cpuss_interrupts_ipc_0_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #0
cpuss_interrupts_ipc_1_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #1
cpuss_interrupts_ipc_2_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #2
cpuss_interrupts_ipc_3_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #3
cpuss_interrupts_ipc_4_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #4
cpuss_interrupts_ipc_5_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #5
cpuss_interrupts_ipc_6_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #6
cpuss_interrupts_ipc_7_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #7
cpuss_interrupts_-
8
9
DeepSleep CPUSS Fault Structure #0 Interrupt
fault_0_IRQn
cpuss_interrupts_-
DeepSleep CPUSS Fault Structure #1 Interrupt
fault_1_IRQn
cpuss_interrupts_-
10
DeepSleep CPUSS Fault Structure #2 Interrupt
fault_2_IRQn
cpuss_interrupts_-
11
12
13
DeepSleep CPUSS Fault Structure #3 Interrupt
fault_3_IRQn
srss_interrupt_backup_IRQn
srss_inter-
rupt_mcwdt_0_IRQn
DeepSleep BACKUP domain Interrupt
DeepSleep Multi Counter Watchdog Timer #0 interrupt
srss_inter-
rupt_mcwdt_1_IRQn
14
DeepSleep Multi Counter Watchdog Timer #1 interrupt
15
16
17
srss_interrupt_wdt_IRQn
srss_interrupt_IRQn
scb_0_interrupt_IRQn
DeepSleep Hardware Watchdog Timer interrupt
DeepSleep Other combined Interrupts for SRSS (LVD, CLKCAL)
DeepSleep SCB0 interrupt (DeepSleep capable)
evtgen_0_interrupt_dps-
lp_IRQn
ioss_interrupt_vdd_IRQn
18
19
20
DeepSleep Event gen DeepSleep domain interrupt
I/O Supply (VDDIO, VDDA, VDDD) state change
DeepSleep
Interrupt
ioss_interrupt_gpio_IRQn
Consolidated Interrupt for GPIO_STD and
DeepSleep
GPIO_ENH, All Ports
21
23
24
26
27
28
29
32
33
34
35
ioss_interrupts_gpio_0_IRQn
ioss_interrupts_gpio_2_IRQn
ioss_interrupts_gpio_3_IRQn
ioss_interrupts_gpio_5_IRQn
ioss_interrupts_gpio_6_IRQn
ioss_interrupts_gpio_7_IRQn
ioss_interrupts_gpio_8_IRQn
ioss_interrupts_gpio_11_IRQn DeepSleep GPIO_STD Port #11 Interrupt
ioss_interrupts_gpio_12_IRQn DeepSleep GPIO_STD Port #12 Interrupt
ioss_interrupts_gpio_13_IRQn DeepSleep GPIO_STD Port #13 Interrupt
ioss_interrupts_gpio_14_IRQn DeepSleep GPIO_STD Port #14 Interrupt
DeepSleep GPIO_ENH Port #0 Interrupt
DeepSleep GPIO_STD Port #2 Interrupt
DeepSleep GPIO_STD Port #3 Interrupt
DeepSleep GPIO_STD Port #5 Interrupt
DeepSleep GPIO_STD Port #6 Interrupt
DeepSleep GPIO_STD Port #7 Interrupt
DeepSleep GPIO_STD Port #8 Interrupt
Datasheet
42
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Source Power Mode Description
Interrupt
38
39
40
42
43
44
45
46
ioss_interrupts_gpio_17_IRQn DeepSleep GPIO_STD Port #17 Interrupt
ioss_interrupts_gpio_18_IRQn DeepSleep GPIO_STD Port #18 Interrupt
ioss_interrupts_gpio_19_IRQn DeepSleep GPIO_STD Port #19 Interrupt
ioss_interrupts_gpio_21_IRQn DeepSleep GPIO_STD Port #21 Interrupt
ioss_interrupts_gpio_22_IRQn DeepSleep GPIO_STD Port #22 Interrupt
ioss_interrupts_gpio_23_IRQn DeepSleep GPIO_STD Port #23 Interrupt
cpuss_interrupt_crypto_IRQn
cpuss_interrupt_fm_IRQn
Active
Active
Crypto Accelerator Interrupt
Flash Macro Interrupt
cpuss_interrupts_cm4_f-
p_IRQn
cpuss_interrupts_cm0_c-
ti_0_IRQn
cpuss_interrupts_cm0_c-
ti_1_IRQn
cpuss_interrupts_cm4_c-
ti_0_IRQn
47
48
49
50
Active
Active
Active
Active
CM4 Floating Point operation fault
CM0+ CTI (Cross Trigger Interface) #0
CM0+ CTI #1
CM4 CTI #0
cpuss_interrupts_cm4_c-
ti_1_IRQn
evtgen_0_interrupt_IRQn
canfd_0_interrupt0_IRQn
51
52
53
Active
Active
Active
CM4 CTI #1
Event gen Active domain interrupt
CAN0, Consolidated Interrupt #0 for all three
channels
canfd_0_interrupt1_IRQn
canfd_1_interrupt0_IRQn
canfd_1_interrupt1_IRQn
CAN0, Consolidated Interrupt #1 for all three
channels
CAN1, Consolidated Interrupt #0 for all three
channels
CAN1, Consolidated Interrupt #1 for all three
channels
54
55
56
Active
Active
Active
57
58
60
61
63
64
66
67
69
70
71
72
73
77
79
canfd_0_interrupts0_0_IRQn
canfd_0_interrupts0_1_IRQn
canfd_0_interrupts1_0_IRQn
canfd_0_interrupts1_1_IRQn
canfd_1_interrupts0_0_IRQn
canfd_1_interrupts0_1_IRQn
canfd_1_interrupts1_0_IRQn
canfd_1_interrupts1_1_IRQn
lin_0_interrupts_0_IRQn
lin_0_interrupts_1_IRQn
lin_0_interrupts_2_IRQn
lin_0_interrupts_3_IRQn
lin_0_interrupts_4_IRQn
scb_1_interrupt_IRQn
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
CAN0, Interrupt #0, Channel #0
CAN0, Interrupt #0, Channel #1
CAN0, Interrupt #1, Channel #0
CAN0, Interrupt #1, Channel #1
CAN1, Interrupt #0, Channel #0
CAN1, Interrupt #0, Channel #1
CAN1, Interrupt #1, Channel #0
CAN1, Interrupt #1, Channel #1
LIN0, Channel #0 Interrupt
LIN0, Channel #1 Interrupt
LIN0, Channel #2 Interrupt
LIN0, Channel #3 Interrupt
LIN0, Channel #4 Interrupt
SCB1 Interrupt
scb_3_interrupt_IRQn
SCB3 Interrupt
Datasheet
43
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power Mode
Active
Description
80
81
83
scb_4_interrupt_IRQn
scb_5_interrupt_IRQn
scb_7_interrupt_IRQn
SCB4 Interrupt
SCB5 Interrupt
SCB7 Interrupt
Active
Active
pass_0_inter-
84
85
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
SAR0, Logical Channel #0 Interrupt
SAR0, Logical Channel #1 Interrupt
SAR0, Logical Channel #2 Interrupt
SAR0, Logical Channel #3 Interrupt
SAR0, Logical Channel #4 Interrupt
SAR0, Logical Channel #5 Interrupt
SAR0, Logical Channel #8 Interrupt
SAR0, Logical Channel #9 Interrupt
SAR0, Logical Channel #11 Interrupt
SAR0, Logical Channel #12 Interrupt
SAR0, Logical Channel #17 Interrupt
SAR1, Logical Channel #4 Interrupt
SAR1, Logical Channel #5 Interrupt
SAR1, Logical Channel #6 Interrupt
SAR1, Logical Channel #7 Interrupt
SAR1, Logical Channel #8 Interrupt
SAR1, Logical Channel #12 Interrupt
SAR1, Logical Channel #13 Interrupt
SAR1, Logical Channel #14 Interrupt
SAR1, Logical Channel #15 Interrupt
SAR1, Logical Channel #16 Interrupt
rupts_sar_0_IRQn
pass_0_inter-
rupts_sar_1_IRQn
pass_0_inter-
rupts_sar_2_IRQn
pass_0_inter-
rupts_sar_3_IRQn
pass_0_inter-
rupts_sar_4_IRQn
pass_0_inter-
rupts_sar_5_IRQn
pass_0_inter-
rupts_sar_8_IRQn
pass_0_inter-
rupts_sar_9_IRQn
pass_0_inter-
rupts_sar_11_IRQn
pass_0_inter-
rupts_sar_12_IRQn
pass_0_inter-
rupts_sar_17_IRQn
pass_0_inter-
rupts_sar_36_IRQn
pass_0_inter-
rupts_sar_37_IRQn
pass_0_inter-
rupts_sar_38_IRQn
pass_0_inter-
rupts_sar_39_IRQn
pass_0_inter-
rupts_sar_40_IRQn
pass_0_inter-
rupts_sar_44_IRQn
86
87
88
89
92
93
95
96
101
112
113
114
115
116
120
121
122
123
124
pass_0_inter-
rupts_sar_45_IRQn
pass_0_inter-
rupts_sar_46_IRQn
pass_0_inter-
rupts_sar_47_IRQn
pass_0_inter-
rupts_sar_48_IRQn
Datasheet
44
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1
Interrupt
Peripheral interrupt assignments and wake-up sources (continued)
Source
Power Mode
Description
pass_0_inter-
125
130
131
140
141
142
143
144
145
146
147
148
149
152
153
154
155
156
157
158
159
160
161
Active
SAR1, Logical Channel #17 Interrupt
rupts_sar_49_IRQn
pass_0_inter-
rupts_sar_54_IRQn
pass_0_inter-
rupts_sar_55_IRQn
pass_0_inter-
rupts_sar_64_IRQn
pass_0_inter-
rupts_sar_65_IRQn
pass_0_inter-
rupts_sar_66_IRQn
pass_0_inter-
rupts_sar_67_IRQn
pass_0_inter-
rupts_sar_68_IRQn
pass_0_inter-
rupts_sar_69_IRQn
pass_0_inter-
rupts_sar_70_IRQn
pass_0_inter-
rupts_sar_71_IRQn
cpuss_interrupts_d-
mac_0_IRQn
cpuss_interrupts_d-
mac_1_IRQn
cpuss_inter-
rupts_dw0_0_IRQn
cpuss_inter-
rupts_dw0_1_IRQn
cpuss_inter-
rupts_dw0_2_IRQn
cpuss_inter-
rupts_dw0_3_IRQn
cpuss_inter-
rupts_dw0_4_IRQn
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
SAR1, Logical Channel #22 Interrupt
SAR1, Logical Channel #23 Interrupt
SAR2, Logical Channel #0 Interrupt
SAR2, Logical Channel #1 Interrupt
SAR2, Logical Channel #2 Interrupt
SAR2, Logical Channel #3 Interrupt
SAR2, Logical Channel #4 Interrupt
SAR2, Logical Channel #5 Interrupt
SAR2, Logical Channel #6 Interrupt
SAR2, Logical Channel #7 Interrupt
CPUSS M-DMA0, Channel #0 Interrupt
CPUSS M-DMA0, Channel #1 Interrupt
CPUSS P-DMA0, Channel #0 Interrupt
CPUSS P-DMA0, Channel #1 Interrupt
CPUSS P-DMA0, Channel #2 Interrupt
CPUSS P-DMA0, Channel #3 Interrupt
CPUSS P-DMA0, Channel #4 Interrupt
CPUSS P-DMA0, Channel #5 Interrupt
CPUSS P-DMA0, Channel #6 Interrupt
CPUSS P-DMA0, Channel #7 Interrupt
CPUSS P-DMA0, Channel #8 Interrupt
CPUSS P-DMA0, Channel #9 Interrupt
cpuss_inter-
rupts_dw0_5_IRQn
cpuss_inter-
rupts_dw0_6_IRQn
cpuss_inter-
rupts_dw0_7_IRQn
cpuss_inter-
rupts_dw0_8_IRQn
cpuss_inter-
rupts_dw0_9_IRQn
Datasheet
45
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1
Interrupt
Peripheral interrupt assignments and wake-up sources (continued)
Source
Power Mode
Description
cpuss_inter-
162
163
164
165
166
167
168
169
170
171
172
173
177
178
179
180
181
182
185
186
188
189
194
Active
CPUSS P-DMA0, Channel #10 Interrupt
rupts_dw0_10_IRQn
cpuss_inter-
rupts_dw0_11_IRQn
cpuss_inter-
rupts_dw0_12_IRQn
cpuss_inter-
rupts_dw0_13_IRQn
cpuss_inter-
rupts_dw0_14_IRQn
cpuss_inter-
rupts_dw0_15_IRQn
cpuss_inter-
rupts_dw0_16_IRQn
cpuss_inter-
rupts_dw0_17_IRQn
cpuss_inter-
rupts_dw0_18_IRQn
cpuss_inter-
rupts_dw0_19_IRQn
cpuss_inter-
rupts_dw0_20_IRQn
cpuss_inter-
rupts_dw0_21_IRQn
cpuss_inter-
rupts_dw0_25_IRQn
cpuss_inter-
rupts_dw0_26_IRQn
cpuss_inter-
rupts_dw0_27_IRQn
cpuss_inter-
rupts_dw0_28_IRQn
cpuss_inter-
rupts_dw0_29_IRQn
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
CPUSS P-DMA0, Channel #11 Interrupt
CPUSS P-DMA0, Channel #12 Interrupt
CPUSS P-DMA0, Channel #13 Interrupt
CPUSS P-DMA0, Channel #14 Interrupt
CPUSS P-DMA0, Channel #15 Interrupt
CPUSS P-DMA0, Channel #16 Interrupt
CPUSS P-DMA0, Channel #17 Interrupt
CPUSS P-DMA0, Channel #18 Interrupt
CPUSS P-DMA0, Channel #19 Interrupt
CPUSS P-DMA0, Channel #20 Interrupt
CPUSS P-DMA0, Channel #21 Interrupt
CPUSS P-DMA0, Channel #25 Interrupt
CPUSS P-DMA0, Channel #26 Interrupt
CPUSS P-DMA0, Channel #27 Interrupt
CPUSS P-DMA0, Channel #28 Interrupt
CPUSS P-DMA0, Channel #29 Interrupt
CPUSS P-DMA0, Channel #30 Interrupt
CPUSS P-DMA0, Channel #33 Interrupt
CPUSS P-DMA0, Channel #34 Interrupt
CPUSS P-DMA0, Channel #36 Interrupt
CPUSS P-DMA0, Channel #37 Interrupt
CPUSS P-DMA0, Channel #42 Interrupt
cpuss_inter-
rupts_dw0_30_IRQn
cpuss_inter-
rupts_dw0_33_IRQn
cpuss_inter-
rupts_dw0_34_IRQn
cpuss_inter-
rupts_dw0_36_IRQn
cpuss_inter-
rupts_dw0_37_IRQn
cpuss_inter-
rupts_dw0_42_IRQn
Datasheet
46
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1
Interrupt
Peripheral interrupt assignments and wake-up sources (continued)
Source
Power Mode
Description
cpuss_inter-
205
206
207
208
209
213
214
215
216
217
218
223
224
233
234
235
236
237
238
239
240
241
242
Active
CPUSS P-DMA0, Channel #53 Interrupt
rupts_dw0_53_IRQn
cpuss_inter-
rupts_dw0_54_IRQn
cpuss_inter-
rupts_dw0_55_IRQn
cpuss_inter-
rupts_dw0_56_IRQn
cpuss_inter-
rupts_dw0_57_IRQn
cpuss_inter-
rupts_dw0_61_IRQn
cpuss_inter-
rupts_dw0_62_IRQn
cpuss_inter-
rupts_dw0_63_IRQn
cpuss_inter-
rupts_dw0_64_IRQn
cpuss_inter-
rupts_dw0_65_IRQn
cpuss_inter-
rupts_dw0_66_IRQn
cpuss_inter-
rupts_dw0_71_IRQn
cpuss_inter-
rupts_dw0_72_IRQn
cpuss_inter-
rupts_dw0_81_IRQn
cpuss_inter-
rupts_dw0_82_IRQn
cpuss_inter-
rupts_dw0_83_IRQn
cpuss_inter-
rupts_dw0_84_IRQn
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
CPUSS P-DMA0, Channel #54 Interrupt
CPUSS P-DMA0, Channel #55 Interrupt
CPUSS P-DMA0, Channel #56 Interrupt
CPUSS P-DMA0, Channel #57 Interrupt
CPUSS P-DMA0, Channel #61 Interrupt
CPUSS P-DMA0, Channel #62 Interrupt
CPUSS P-DMA0, Channel #63 Interrupt
CPUSS P-DMA0, Channel #64 Interrupt
CPUSS P-DMA0, Channel #65 Interrupt
CPUSS P-DMA0, Channel #66 Interrupt
CPUSS P-DMA0, Channel #71 Interrupt
CPUSS P-DMA0, Channel #72 Interrupt
CPUSS P-DMA0, Channel #81 Interrupt
CPUSS P-DMA0, Channel #82 Interrupt
CPUSS P-DMA0, Channel #83 Interrupt
CPUSS P-DMA0, Channel #84 Interrupt
CPUSS P-DMA0, Channel #85 Interrupt
CPUSS P-DMA0, Channel #86 Interrupt
CPUSS P-DMA0, Channel #87 Interrupt
CPUSS P-DMA0, Channel #88 Interrupt
CPUSS P-DMA1, Channel #0 Interrupt
CPUSS P-DMA1, Channel #1 Interrupt
cpuss_inter-
rupts_dw0_85_IRQn
cpuss_inter-
rupts_dw0_86_IRQn
cpuss_inter-
rupts_dw0_87_IRQn
cpuss_inter-
rupts_dw0_88_IRQn
cpuss_inter-
rupts_dw1_0_IRQn
cpuss_inter-
rupts_dw1_1_IRQn
Datasheet
47
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1
Interrupt
Peripheral interrupt assignments and wake-up sources (continued)
Source
Power Mode
Description
cpuss_inter-
243
244
245
246
247
248
249
250
251
252
255
256
257
258
259
260
263
264
265
266
267
268
269
Active
CPUSS P-DMA1, Channel #2 Interrupt
rupts_dw1_2_IRQn
cpuss_inter-
rupts_dw1_3_IRQn
cpuss_inter-
rupts_dw1_4_IRQn
cpuss_inter-
rupts_dw1_5_IRQn
cpuss_inter-
rupts_dw1_6_IRQn
cpuss_inter-
rupts_dw1_7_IRQn
cpuss_inter-
rupts_dw1_8_IRQn
cpuss_inter-
rupts_dw1_9_IRQn
cpuss_inter-
rupts_dw1_10_IRQn
cpuss_inter-
rupts_dw1_11_IRQn
cpuss_inter-
rupts_dw1_14_IRQn
cpuss_inter-
rupts_dw1_15_IRQn
cpuss_inter-
rupts_dw1_16_IRQn
cpuss_inter-
rupts_dw1_17_IRQn
cpuss_inter-
rupts_dw1_18_IRQn
cpuss_inter-
rupts_dw1_19_IRQn
cpuss_inter-
rupts_dw1_22_IRQn
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
CPUSS P-DMA1, Channel #3 Interrupt
CPUSS P-DMA1, Channel #4 Interrupt
CPUSS P-DMA1, Channel #5 Interrupt
CPUSS P-DMA1, Channel #6 Interrupt
CPUSS P-DMA1, Channel #7 Interrupt
CPUSS P-DMA1, Channel #8 Interrupt
CPUSS P-DMA1, Channel #9 Interrupt
CPUSS P-DMA1, Channel #10 Interrupt
CPUSS P-DMA1, Channel #11 Interrupt
CPUSS P-DMA1, Channel #14 Interrupt
CPUSS P-DMA1, Channel #15 Interrupt
CPUSS P-DMA1, Channel #16 Interrupt
CPUSS P-DMA1, Channel #17 Interrupt
CPUSS P-DMA1, Channel #18 Interrupt
CPUSS P-DMA1, Channel #19 Interrupt
CPUSS P-DMA1, Channel #22 Interrupt
CPUSS P-DMA1, Channel #23 Interrupt
CPUSS P-DMA1, Channel #24 Interrupt
CPUSS P-DMA1, Channel #25 Interrupt
CPUSS P-DMA1, Channel #26 Interrupt
CPUSS P-DMA1, Channel #27 Interrupt
CPUSS P-DMA1, Channel #28 Interrupt
cpuss_inter-
rupts_dw1_23_IRQn
cpuss_inter-
rupts_dw1_24_IRQn
cpuss_inter-
rupts_dw1_25_IRQn
cpuss_inter-
rupts_dw1_26_IRQn
cpuss_inter-
rupts_dw1_27_IRQn
cpuss_inter-
rupts_dw1_28_IRQn
Datasheet
48
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1
Interrupt
Peripheral interrupt assignments and wake-up sources (continued)
Source
Power Mode
Description
cpuss_inter-
rupts_dw1_29_IRQn
270
Active
CPUSS P-DMA1, Channel #29 Interrupt
274
275
276
278
279
280
281
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
307
308
310
311
312
313
314
315
316
318
319
320
321
tcpwm_0_interrupts_0_IRQn
tcpwm_0_interrupts_1_IRQn
tcpwm_0_interrupts_2_IRQn
tcpwm_0_interrupts_4_IRQn
tcpwm_0_interrupts_5_IRQn
tcpwm_0_interrupts_6_IRQn
tcpwm_0_interrupts_7_IRQn
tcpwm_0_interrupts_9_IRQn
tcpwm_0_interrupts_10_IRQn
tcpwm_0_interrupts_11_IRQn
tcpwm_0_interrupts_12_IRQn
tcpwm_0_interrupts_13_IRQn
tcpwm_0_interrupts_14_IRQn
tcpwm_0_interrupts_15_IRQn
tcpwm_0_interrupts_16_IRQn
tcpwm_0_interrupts_17_IRQn
tcpwm_0_interrupts_18_IRQn
tcpwm_0_interrupts_19_IRQn
tcpwm_0_interrupts_20_IRQn
tcpwm_0_interrupts_21_IRQn
tcpwm_0_interrupts_22_IRQn
tcpwm_0_interrupts_23_IRQn
tcpwm_0_interrupts_24_IRQn
tcpwm_0_interrupts_25_IRQn
tcpwm_0_interrupts_26_IRQn
tcpwm_0_interrupts_33_IRQn
tcpwm_0_interrupts_34_IRQn
tcpwm_0_interrupts_36_IRQn
tcpwm_0_interrupts_37_IRQn
tcpwm_0_interrupts_38_IRQn
tcpwm_0_interrupts_39_IRQn
tcpwm_0_interrupts_40_IRQn
tcpwm_0_interrupts_41_IRQn
tcpwm_0_interrupts_42_IRQn
tcpwm_0_interrupts_44_IRQn
tcpwm_0_interrupts_45_IRQn
tcpwm_0_interrupts_46_IRQn
tcpwm_0_interrupts_47_IRQn
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
TCPWM0 Group #0, Counter #0 Interrupt
TCPWM0 Group #0, Counter #1 Interrupt
TCPWM0 Group #0, Counter #2 Interrupt
TCPWM0 Group #0, Counter #4 Interrupt
TCPWM0 Group #0, Counter #5 Interrupt
TCPWM0 Group #0, Counter #6 Interrupt
TCPWM0 Group #0, Counter #7 Interrupt
TCPWM0 Group #0, Counter #9 Interrupt
TCPWM0 Group #0, Counter #10 Interrupt
TCPWM0 Group #0, Counter #11 Interrupt
TCPWM0 Group #0, Counter #12 Interrupt
TCPWM0 Group #0, Counter #13 Interrupt
TCPWM0 Group #0, Counter #14 Interrupt
TCPWM0 Group #0, Counter #15 Interrupt
TCPWM0 Group #0, Counter #16 Interrupt
TCPWM0 Group #0, Counter #17 Interrupt
TCPWM0 Group #0, Counter #18 Interrupt
TCPWM0 Group #0, Counter #19 Interrupt
TCPWM0 Group #0, Counter #20 Interrupt
TCPWM0 Group #0, Counter #21 Interrupt
TCPWM0 Group #0, Counter #22 Interrupt
TCPWM0 Group #0, Counter #23 Interrupt
TCPWM0 Group #0, Counter #24 Interrupt
TCPWM0 Group #0, Counter #25 Interrupt
TCPWM0 Group #0, Counter #26 Interrupt
TCPWM0 Group #0, Counter #33 Interrupt
TCPWM0 Group #0, Counter #34 Interrupt
TCPWM0 Group #0, Counter #36 Interrupt
TCPWM0 Group #0, Counter #37 Interrupt
TCPWM0 Group #0, Counter #38 Interrupt
TCPWM0 Group #0, Counter #39 Interrupt
TCPWM0 Group #0, Counter #40 Interrupt
TCPWM0 Group #0, Counter #41 Interrupt
TCPWM0 Group #0, Counter #42 Interrupt
TCPWM0 Group #0, Counter #44 Interrupt
TCPWM0 Group #0, Counter #45 Interrupt
TCPWM0 Group #0, Counter #46 Interrupt
TCPWM0 Group #0, Counter #47 Interrupt
Datasheet
49
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1
Interrupt
322
Peripheral interrupt assignments and wake-up sources (continued)
Source
Power Mode
Active
Description
tcpwm_0_interrupts_48_IRQn
tcpwm_0_interrupts_49_IRQn
tcpwm_0_interrupts_50_IRQn
tcpwm_0_interrupts_51_IRQn
tcpwm_0_interrupts_52_IRQn
tcpwm_0_interrupts_53_IRQn
tcpwm_0_interrupts_54_IRQn
tcpwm_0_interrupts_55_IRQn
TCPWM0 Group #0, Counter #48 Interrupt
TCPWM0 Group #0, Counter #49 Interrupt
TCPWM0 Group #0, Counter #50 Interrupt
TCPWM0 Group #0, Counter #51 Interrupt
TCPWM0 Group #0, Counter #52 Interrupt
TCPWM0 Group #0, Counter #53 Interrupt
TCPWM0 Group #0, Counter #54 Interrupt
TCPWM0 Group #0, Counter #55 Interrupt
323
324
325
326
327
328
329
Active
Active
Active
Active
Active
Active
Active
tcpwm_0_inter-
rupts_256_IRQn
tcpwm_0_inter-
rupts_257_IRQn
tcpwm_0_inter-
rupts_258_IRQn
tcpwm_0_inter-
rupts_260_IRQn
tcpwm_0_inter-
rupts_512_IRQn
tcpwm_0_inter-
rupts_514_IRQn
337
338
339
341
349
351
Active
Active
Active
Active
Active
Active
TCPWM0 Group #1, Counter #0 Interrupt
TCPWM0 Group #1, Counter #1 Interrupt
TCPWM0 Group #1, Counter #2 Interrupt
TCPWM0 Group #1, Counter #4 Interrupt
TCPWM0 Group #2, Counter #0 Interrupt
TCPWM0 Group #2, Counter #2 Interrupt
Datasheet
50
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Core interrupt types
16
Core interrupt types
Table 16-1
Core interrupt types
Source
Interrupt
Power mode
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
Active
Description
CPU User Interrupt #0
CPU User Interrupt #1
CPU User Interrupt #2
CPU User Interrupt #3
0
1
2
CPUIntIdx0_IRQn[29]
CPUIntIdx1_IRQn[29]
CPUIntIdx2_IRQn
CPUIntIdx3_IRQn
CPUIntIdx4_IRQn
CPUIntIdx5_IRQn
CPUIntIdx6_IRQn
CPUIntIdx7_IRQn
Internal0_IRQn
Internal1_IRQn
Internal2_IRQn
Internal3_IRQn
Internal4_IRQn
Internal5_IRQn
Internal6_IRQn
Internal7_IRQn
3
4
5
6
7
8
9
10
11
12
13
14
15
CPU User Interrupt #4
CPU User Interrupt #5
CPU User Interrupt #6
CPU User Interrupt #7
Internal Software Interrupt #0
Internal Software Interrupt #1
Internal Software Interrupt #2
Internal Software Interrupt #3
Internal Software Interrupt #4
Internal Software Interrupt #5
Internal Software Interrupt #6
Internal Software Interrupt #7
Active
Active
Active
Active
Active
Active
Active
Note
29.User interrupt cannot be used for CM0+ application, as it is used internally by system calls. Note, this does not impact CM4 application.
Datasheet
51
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Trigger multiplexer
17
Trigger multiplexer
Green numbers indicate mux group number
Orange numbers indicate 1:1 group number
16
16
8
P-DMA0: PDMA0_TR_OUT[0:15]
8
2
P-DMA1: PDMA1_TR_OUT[0:7]
8
6
4
P-DMA0: PDMA0_TR_IN[0:7]
0
2
M-DMA: MDMA_TR_OUT[0:1]
3:6
0:15
16
16
8
2
6
4
16
8
2
1
P-DMA1: PDMA1_TR_IN[0:7]
M-DMA: MDMA_TR_IN[0:1]
7:10
16:31
6
2
2
2
2
TCPWM[0]32: TCPWM_32_TR_OUT0{[0],[2]}
TCPWM[0]32: TCPWM_32_TR_OUT1{[0],[2]}
8
2
4
46
3
P-DMA0: PDMA0_TR_IN[8:15]
16
Mux #4 only
4
4
7
4
TCPWM[0]16M: TCPWM_16M_TR_OUT0{[0:2],[4]}
TCPWM[0]16M: TCPWM_16M_TR_OUT1{[0:2],[4]}
4
TCPWM[0]: TCPWM_ALL_CNT_TR_IN[0:15]
46
63
TCPWM[0]16: TCPWM_16_TR_OUT0{[0:2],[4:7],[9:26],[33:34],[36:42],[44:55]}
TCPWM[0]16: TCPWM_16_TR_OUT1{[0:2],[4:7],[9:26],[33:34],[36:42],[44:55]}
4
0
LIN[0]: LIN0_CMD_TR_IN{[0:2],[4]}
0:1,4:5,7,
13,20:24,33,
38:39,48:51
PASS[0]: PASS0_CH_TR_IN{[0:2],[4:5],[8:9],[11],[17]}
PASS[0]: PASS0_CH_TR_IN{[36:40],[49],[54:55]}
PASS[0]: PASS0_CH_TR_IN[68:71]
21
1
0:2
16
8
2
6
8
6
CPUSS: FAULT_TR_OUT[0:3]
CPUSS: CTI_TR_OUT[0:1]
3:10
11
5
TCPWM[0]: TCPWM_ALL_CNT_TR_IN[16:26]
18
32
6
11
EVTGEN[0]: EVTGEN_TR_OUT[0:10]
HSIOM: HSIOM_IO _INPUT[0:31]
12
16
32
4
32
9
6
PASS[0]: PASS_GEN_TR_IN{[0:5],[8:9],[11]}
6
3
0:2
2
6
6
PASS[0]: PASS_GEN_TR_OUT[0:5]
PASS[0]: PASS_CH_DONE_TR_OUT{[0:5],[8:9],[11:12],[17]}
PASS[0]: PASS_CH_DONE_TR_OUT{[36:40],[44:49],[54:55]}
PASS[0]: PASS_CH_DONE_TR_OUT[64:71]
P-DMA0:
32
32
2
3
PDMA0_TR_IN{[25:30],[33:34],[36:37],[42],[53:57],[61:66],
[71:72],[81:88]}
PASS[0]: PASS_CH_RANGEVIO_TR_OUT{[0],[4:5],[8:9],[11],[17]}
PASS[0]: PASS_CH_RANGEVIO_TR_OUT{[36:40],[49],[54:55]}
PASS[0]: PASS_CH_RANGEVIO_TR_OUT{[64],[68:71]}
20
2
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN{[0],[2]}
TCPWM[0]16:
TCPWM0_16_ONE_CNT_TR_IN[0:1],[4:5],[7],[13],[20:24],
[33],[38:39],[48:51]}
18
CAN[0:1]: CAN0_DBG_TR_OUT/CAN1_DBG_TR_OUT[0:1]
CAN[0:1]: CAN0_FIFO0_TR_OUT/CAN1_FIFO0_TR_OUT[0:1]
CAN[0:1]: CAN0_FIFO1_TR_OUT/CAN1_FIFO1_TR_OUT[0:1]
12
4
6
6
4
5
P-DMA0: PDMA0_TR_IN[16:21]
P-DMA1: PDMA1_TR_IN[24:29]
CAN[0]: CAN0_TT_TR_OUT[0:1]
CAN[1]: CAN1_TT_TR_OUT[0:1]
4
CAN[0]: CAN0_TT_TR_IN[0:1]
CAN[1]: CAN1_TT_TR_IN[0:1]
4
7
2
2
2
2
6
7
CAN[0]: CAN0_DBG_TR_ACK[0:1]
CAN[1]: CAN1_DBG_TR_ACK[0:1]
P-DMA0: PDMA0_TR_OUT{[16],[19]}
P-DMA1: PDMA1_TR_OUT{[24],[27]}
SCB{[0:1],[3:5],[7]}: SCB_TX_TR_OUT
SCB{[0:1],[3:5],[7]}: SCB_RX_TR_OUT
SCB{[0:1],[3:5],[7]}: SCB_I2C_SCL_TR_OUT
18
SCB_TX_TR_OUT, SCB_RX_TR_OUT
12
2
8
P-DMA1: PDMA1_TR_IN{[8:11],[14:19],[22:23]}
CPUSS: CTI_TR_IN[0:1]
245
P-DMA0*, SCB*, CANFD*, CPUSS*, TCPWM_TR_OUT0*
146
99
5
5
1
1
All Triggers
9
TCPWM[0]: TCPWM_DEBUG_FREEZE_TR_IN
PERI: PERI_DEBUG_FREEZE_TR_IN
8
1
3
PASS[0]: PASS_DEBUG_FREEZE_TR_IN
P-DMA1*, M-DMA*, PASS*, EVTGEN*, TCPWM_TR_OUT1*
SRSS: SRSS_WDT_DEBUG_FREEZE_TR_IN
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[0:1]
10
2
HSIOM: HSIOM_IO_OUTPUT[0:1]
Figure 17-1
Trigger multiplexer[30]
Note
30.The diagram shows only the TRIG_LABEL, final trigger formation is based on the formula TRIG_{PREFIX(IN/OUT)}_{MUX_x}_{TRIG_LA-
BEL} / TRIG_{PREFIX(IN_1TO1/OUT_1TO1)}_{x}_{TRIG_LABEL} and the below mentioned tables Table 18-1, Table 19-1, and
Table 20-1.
Datasheet
52
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
18
Triggers group inputs
Table 18-1
Trigger inputs
Trigger label
(TRIG_LABEL)
Input
Description
MUX Group 0: PDMA0_TR (P-DMA0_0_15 trigger multiplexer)
1:16[31]
PDMA0_TR_OUT[0:15]
Allow P-DMA0 to chain to itself, useful for triggering once per
row for 2D transfer
17:24
PDMA1_TR_OUT[0:7]
Cross connections from P-DMA1 to P-DMA0, Channels 0-7 are
used
25:26
29:32
33:34
35:38
39:54
MDMA_TR_OUT[0:1]
FAULT_TR_OUT[0:3]
CTI_TR_OUT[0:1]
EVTGEN_TR_OUT[3:6]
HSIOM_IO_INPUT[0:15]
Cross connections from M-DMA0 to P-DMA0
Allow faults to initiate data transfer for debug purposes
Trace events
EVTGEN triggers
I/O inputs
MUX Group 1: PDMA1_TR (P-DMA1 trigger multiplexer)
1:16
17:24
PDMA0_TR_OUT[0:15]
PDMA1_TR_OUT[0:7]
Allow P-DMA0 to trigger P-DMA1
Allow P-DMA1 to chain to itself, useful for triggering once per
row for 2D transfer
25:26
29:32
33:34
35:38
39:54
55:60
MDMA_TR_OUT[0:1]
FAULT_TR_OUT[0:3]
CTI_TR_OUT[0:1]
EVTGEN_TR_OUT[7:10]
HSIOM_IO_INPUT[16:31]
PASS_GEN_TR_OUT[0:5]
Allow M-DMA0 to trigger P-DMA0
Allow faults to initiate data transfer for debug purposes
Trace events
EVTGEN triggers
I/O inputs
PASS SAR events
MUX Group 2: MDMA (M-DMA0 trigger multiplexer)
1:2 MDMA_TR_OUT[0:1] Allow M-DMA0 to trigger itself
MUX Group 3: TCPWM_TO_PDMA0 (TCPWM0 to P-DMA0 trigger multiplexer)
1
3
TCPWM_32_TR_OUT0[0]
TCPWM_32_TR_OUT0[2]
32-bit TCPWM0 Group #2, Counter #0 counters
32-bit TCPWM0 Group #2, Counter #2 counters
5
6
7
9
TCPWM_16M_TR_OUT0[0] 16-bit Motor enhanced TCPWM0 Group #1, Counter #0 counters
TCPWM_16M_TR_OUT0[1] 16-bit Motor enhanced TCPWM0 Group #1, Counter #1 counters
TCPWM_16M_TR_OUT0[2] 16-bit Motor enhanced TCPWM0 Group #1, Counter #2 counters
TCPWM_16M_TR_OUT0[4] 16-bit Motor enhanced TCPWM0 Group #1, Counter #4 counters
17
18
19
21
22
23
24
TCPWM_16_TR_OUT0[0]
TCPWM_16_TR_OUT0[1]
TCPWM_16_TR_OUT0[2]
TCPWM_16_TR_OUT0[4]
TCPWM_16_TR_OUT0[5]
TCPWM_16_TR_OUT0[6]
TCPWM_16_TR_OUT0[7]
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #0, Counter #4
TCPWM0 Group #0, Counter #5
TCPWM0 Group #0, Counter #6
TCPWM0 Group #0, Counter #7
Note
31.“a:b” depicts a range starting from ‘a’ through ‘b’.
Datasheet
53
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
TCPWM0 Group #0, Counter #9
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
50
51
53
54
55
56
57
58
59
61
62
63
64
65
66
67
68
69
70
71
72
TCPWM_16_TR_OUT0[9]
TCPWM_16_TR_OUT0[10]
TCPWM_16_TR_OUT0[11]
TCPWM_16_TR_OUT0[12]
TCPWM_16_TR_OUT0[13]
TCPWM_16_TR_OUT0[14]
TCPWM_16_TR_OUT0[15]
TCPWM_16_TR_OUT0[16]
TCPWM_16_TR_OUT0[17]
TCPWM_16_TR_OUT0[18]
TCPWM_16_TR_OUT0[19]
TCPWM_16_TR_OUT0[20]
TCPWM_16_TR_OUT0[21]
TCPWM_16_TR_OUT0[22]
TCPWM_16_TR_OUT0[23]
TCPWM_16_TR_OUT0[24]
TCPWM_16_TR_OUT0[25]
TCPWM_16_TR_OUT0[26]
TCPWM_16_TR_OUT0[33]
TCPWM_16_TR_OUT0[34]
TCPWM_16_TR_OUT0[36]
TCPWM_16_TR_OUT0[37]
TCPWM_16_TR_OUT0[38]
TCPWM_16_TR_OUT0[39]
TCPWM_16_TR_OUT0[40]
TCPWM_16_TR_OUT0[41]
TCPWM_16_TR_OUT0[42]
TCPWM_16_TR_OUT0[44]
TCPWM_16_TR_OUT0[45]
TCPWM_16_TR_OUT0[46]
TCPWM_16_TR_OUT0[47]
TCPWM_16_TR_OUT0[48]
TCPWM_16_TR_OUT0[49]
TCPWM_16_TR_OUT0[50]
TCPWM_16_TR_OUT0[51]
TCPWM_16_TR_OUT0[52]
TCPWM_16_TR_OUT0[53]
TCPWM_16_TR_OUT0[54]
TCPWM_16_TR_OUT0[55]
TCPWM0 Group #0, Counter #10
TCPWM0 Group #0, Counter #11
TCPWM0 Group #0, Counter #12
TCPWM0 Group #0, Counter #13
TCPWM0 Group #0, Counter #14
TCPWM0 Group #0, Counter #15
TCPWM0 Group #0, Counter #16
TCPWM0 Group #0, Counter #17
TCPWM0 Group #0, Counter #18
TCPWM0 Group #0, Counter #19
TCPWM0 Group #0, Counter #20
TCPWM0 Group #0, Counter #21
TCPWM0 Group #0, Counter #22
TCPWM0 Group #0, Counter #23
TCPWM0 Group #0, Counter #24
TCPWM0 Group #0, Counter #25
TCPWM0 Group #0, Counter #26
TCPWM0 Group #0, Counter #33
TCPWM0 Group #0, Counter #34
TCPWM0 Group #0, Counter #36
TCPWM0 Group #0, Counter #37
TCPWM0 Group #0, Counter #38
TCPWM0 Group #0, Counter #39
TCPWM0 Group #0, Counter #40
TCPWM0 Group #0, Counter #41
TCPWM0 Group #0, Counter #42
TCPWM0 Group #0, Counter #44
TCPWM0 Group #0, Counter #45
TCPWM0 Group #0, Counter #46
TCPWM0 Group #0, Counter #47
TCPWM0 Group #0, Counter #48
TCPWM0 Group #0, Counter #49
TCPWM0 Group #0, Counter #50
TCPWM0 Group #0, Counter #51
TCPWM0 Group #0, Counter #52
TCPWM0 Group #0, Counter #53
TCPWM0 Group #0, Counter #54
TCPWM0 Group #0, Counter #55
Datasheet
54
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
CAN0, channel#0 TT Sync Outputs
CAN0, channel#1 TT Sync Outputs
CAN1, channel#0 TT Sync Outputs
CAN1, channel#1 TT Sync Outputs
80
81
83
84
CAN0_TT_TR_OUT[0]
CAN0_TT_TR_OUT[1]
CAN1_TT_TR_OUT[0]
CAN1_TT_TR_OUT[1]
MUX Group 4: TCPWM_OUT (TCPWM0 loop back multiplexer)
1
3
TCPWM_32_TR_OUT0[0]
TCPWM_32_TR_OUT0[2]
32-bit TCPWM0 Group #2, Counter #0 counters
32-bit TCPWM0 Group #2, Counter #2 counters
5
6
7
9
TCPWM_16M_TR_OUT0[0] 16-bit Motor enhanced TCPWM0 Group #1, Counter #0 counters
TCPWM_16M_TR_OUT0[1] 16-bit Motor enhanced TCPWM0 Group #1, Counter #1 counters
TCPWM_16M_TR_OUT0[2] 16-bit Motor enhanced TCPWM0 Group #1, Counter #2 counters
TCPWM_16M_TR_OUT0[4] 16-bit Motor enhanced TCPWM0 Group #1, Counter #4 counters
17
18
19
21
22
23
24
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
50
51
53
TCPWM_16_TR_OUT0[0]
TCPWM_16_TR_OUT0[1]
TCPWM_16_TR_OUT0[2]
TCPWM_16_TR_OUT0[4]
TCPWM_16_TR_OUT0[5]
TCPWM_16_TR_OUT0[6]
TCPWM_16_TR_OUT0[7]
TCPWM_16_TR_OUT0[9]
TCPWM_16_TR_OUT0[10]
TCPWM_16_TR_OUT0[11]
TCPWM_16_TR_OUT0[12]
TCPWM_16_TR_OUT0[13]
TCPWM_16_TR_OUT0[14]
TCPWM_16_TR_OUT0[15]
TCPWM_16_TR_OUT0[16]
TCPWM_16_TR_OUT0[17]
TCPWM_16_TR_OUT0[18]
TCPWM_16_TR_OUT0[19]
TCPWM_16_TR_OUT0[20]
TCPWM_16_TR_OUT0[21]
TCPWM_16_TR_OUT0[22]
TCPWM_16_TR_OUT0[23]
TCPWM_16_TR_OUT0[24]
TCPWM_16_TR_OUT0[25]
TCPWM_16_TR_OUT0[26]
TCPWM_16_TR_OUT0[33]
TCPWM_16_TR_OUT0[34]
TCPWM_16_TR_OUT0[36]
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #0, Counter #4
TCPWM0 Group #0, Counter #5
TCPWM0 Group #0, Counter #6
TCPWM0 Group #0, Counter #7
TCPWM0 Group #0, Counter #9
TCPWM0 Group #0, Counter #10
TCPWM0 Group #0, Counter #11
TCPWM0 Group #0, Counter #12
TCPWM0 Group #0, Counter #13
TCPWM0 Group #0, Counter #14
TCPWM0 Group #0, Counter #15
TCPWM0 Group #0, Counter #16
TCPWM0 Group #0, Counter #17
TCPWM0 Group #0, Counter #18
TCPWM0 Group #0, Counter #19
TCPWM0 Group #0, Counter #20
TCPWM0 Group #0, Counter #21
TCPWM0 Group #0, Counter #22
TCPWM0 Group #0, Counter #23
TCPWM0 Group #0, Counter #24
TCPWM0 Group #0, Counter #25
TCPWM0 Group #0, Counter #26
TCPWM0 Group #0, Counter #33
TCPWM0 Group #0, Counter #34
TCPWM0 Group #0, Counter #36
Datasheet
55
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
TCPWM0 Group #0, Counter #37
54
55
56
57
58
59
61
62
63
64
65
66
67
68
69
70
71
72
80
81
82
84
85
86
87
88
89
91
92
TCPWM_16_TR_OUT0[37]
TCPWM_16_TR_OUT0[38]
TCPWM_16_TR_OUT0[39]
TCPWM_16_TR_OUT0[40]
TCPWM_16_TR_OUT0[41]
TCPWM_16_TR_OUT0[42]
TCPWM_16_TR_OUT0[44]
TCPWM_16_TR_OUT0[45]
TCPWM_16_TR_OUT0[46]
TCPWM_16_TR_OUT0[47]
TCPWM_16_TR_OUT0[48]
TCPWM_16_TR_OUT0[49]
TCPWM_16_TR_OUT0[50]
TCPWM_16_TR_OUT0[51]
TCPWM_16_TR_OUT0[52]
TCPWM_16_TR_OUT0[53]
TCPWM_16_TR_OUT0[54]
TCPWM_16_TR_OUT0[55]
TCPWM_16_TR_OUT1[0]
TCPWM_16_TR_OUT1[1]
TCPWM_16_TR_OUT1[2]
TCPWM_16_TR_OUT1[4]
TCPWM_16_TR_OUT1[5]
TCPWM_16_TR_OUT1[6]
TCPWM_16_TR_OUT1[7]
CAN0_TT_TR_OUT[0]
TCPWM0 Group #0, Counter #38
TCPWM0 Group #0, Counter #39
TCPWM0 Group #0, Counter #40
TCPWM0 Group #0, Counter #41
TCPWM0 Group #0, Counter #42
TCPWM0 Group #0, Counter #44
TCPWM0 Group #0, Counter #45
TCPWM0 Group #0, Counter #46
TCPWM0 Group #0, Counter #47
TCPWM0 Group #0, Counter #48
TCPWM0 Group #0, Counter #49
TCPWM0 Group #0, Counter #50
TCPWM0 Group #0, Counter #51
TCPWM0 Group #0, Counter #52
TCPWM0 Group #0, Counter #53
TCPWM0 Group #0, Counter #54
TCPWM0 Group #0, Counter #55
TCPWM0 Group #1, Counter #0
TCPWM0 Group #1, Counter #1
TCPWM0 Group #1, Counter #2
TCPWM0 Group #1, Counter #4
TCPWM0 Group #1, Counter #5
TCPWM0 Group #1, Counter #6
TCPWM0 Group #1, Counter #7
CAN0, channel#0 TT Sync Outputs
CAN0, channel#1 TT Sync Outputs
CAN1, channel#0 TT Sync Outputs
CAN1, channel#1 TT Sync Outputs
CAN0_TT_TR_OUT[1]
CAN1_TT_TR_OUT[0]
CAN1_TT_TR_OUT[1]
MUX Group 5: TCPWM_IN (TCPWM0 Trigger Multiplexer)
1:16
17:24
25:26
29:30
31:34
35:40
41:72
73
PDMA0_TR_OUT[0:15]
PDMA1_TR_OUT[0:7]
MDMA_TR_OUT[0:1]
CTI_TR_OUT[0:1]
FAULT_TR_OUT[0:3]
PASS_GEN_TR_OUT[0:5]
HSIOM_IO_INPUT[0:31]
SCB_TX_TR_OUT[0]
SCB_RX_TR_OUT[0]
General-purpose P-DMA0 triggers
General-purpose P-DMA1 triggers
M-DMA0 triggers
Trace events
Fault events
PASS SAR events
I/O inputs
SCB0 TX trigger
SCB0 RX trigger
74
Datasheet
56
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
75
76
77
78
82
SCB_I2C_SCL_TR_OUT[0]
SCB_TX_TR_OUT[1]
SCB_RX_TR_OUT[1]
SCB_I2C_SCL_TR_OUT[1]
SCB_TX_TR_OUT[3]
SCB0 I2C trigger
SCB1 TX trigger
SCB1 RX trigger
SCB1 I2C trigger
SCB3 TX trigger
SCB3 RX trigger
SCB3 I2C trigger
SCB4 TX trigger
SCB4 RX trigger
SCB4 I2C trigger
SCB5 TX trigger
SCB5 RX trigger
SCB5 I2C trigger
SCB7 TX trigger
SCB7 RX trigger
SCB7 I2C trigger
CAN0 M-DMA0 events
83
84
85
86
87
88
89
90
SCB_RX_TR_OUT[3]
SCB_I2C_SCL_TR_OUT[3]
SCB_TX_TR_OUT[4]
SCB_RX_TR_OUT[4]
SCB_I2C_SCL_TR_OUT[4]
SCB_TX_TR_OUT[5]
SCB_RX_TR_OUT[5]
SCB_I2C_SCL_TR_OUT[5]
SCB_TX_TR_OUT[7]
SCB_RX_TR_OUT[7]
SCB_I2C_SCL_TR_OUT[7]
CAN0_DBG_TR_OUT[0:1]
CAN0_FIFO0_TR_OUT[0:1] CAN0 FIFO0 events
CAN0_FIFO1_TR_OUT[0:1] CAN0 FIFO1 events
CAN1_DBG_TR_OUT[0:1]
CAN1_FIFO0_TR_OUT[0:1] CAN1 FIFO0 events
CAN1_FIFO1_TR_OUT[0:1] CAN1 FIFO1 events
EVTGEN_TR_OUT[3:10]
94
95
96
97:98
100:101
103:104
106:107
109:110
112:113
115:122
CAN1 M-DMA0 events
EVTGEN triggers
MUX Group 6: PASS (PASS SAR trigger multiplexer)
1:16
17:18
19:22
23:25
26:31
32:63
64
PDMA0_TR_OUT[0:15]
CTI_TR_OUT[0:1]
FAULT_TR_OUT[0:3]
EVTGEN_TR_OUT[0:2]
PASS_GEN_TR_OUT[0:5]
HSIOM_IO_INPUT[0:31]
TCPWM_32_TR_OUT1[0]
TCPWM_32_TR_OUT1[2]
General-purpose P-DMA0 triggers
Trace events
Fault events
EVTGEN triggers
PASS SAR done signals
I/O inputs
32-bit TCPWM0 Group #2, Counter #0 counters
32-bit TCPWM0 Group #2, Counter #2 counters
66
68
69
70
72
TCPWM_16M_TR_OUT1[0] 16-bit Motor enhanced TCPWM0 Group #1, Counter #0 counters
TCPWM_16M_TR_OUT1[1] 16-bit Motor enhanced TCPWM0 Group #1, Counter #1 counters
TCPWM_16M_TR_OUT1[2] 16-bit Motor enhanced TCPWM0 Group #1, Counter #2 counters
TCPWM_16M_TR_OUT1[4] 16-bit Motor enhanced TCPWM0 Group #1, Counter #4 counters
MUX Group 7: CAN TT sync triggers
1:2
4:5
CAN0_TT_TR_OUT[0:1]
CAN1_TT_TR_OUT[0:1]
CAN0 TT Sync Outputs
CAN1 TT Sync Outputs
Datasheet
57
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
MUX Group 8: DebugMain (Debug Multiplexer)
1:5
6:10
TR_GROUP9_OUTPUT[0:4] Output from debug reduction multiplexer #1
TR_GROUP10_OUTPUT[0:4] Output from debug reduction multiplexer #2
MUX Group 9: DebugReduction1 (Debug Reduction #1)
1
PDMA0_TR_OUT[0]
PDMA0_TR_OUT[1]
PDMA0_TR_OUT[2]
PDMA0_TR_OUT[3]
PDMA0_TR_OUT[4]
PDMA0_TR_OUT[5]
PDMA0_TR_OUT[6]
PDMA0_TR_OUT[7]
PDMA0_TR_OUT[8]
PDMA0_TR_OUT[9]
PDMA0_TR_OUT[10]
PDMA0_TR_OUT[11]
PDMA0_TR_OUT[12]
PDMA0_TR_OUT[13]
PDMA0_TR_OUT[14]
PDMA0_TR_OUT[15]
PDMA0_TR_OUT[16]
PDMA0_TR_OUT[17]
PDMA0_TR_OUT[18]
PDMA0_TR_OUT[19]
PDMA0_TR_OUT[20]
PDMA0_TR_OUT[21]
PDMA0_TR_OUT[25]
PDMA0_TR_OUT[26]
PDMA0_TR_OUT[27]
PDMA0_TR_OUT[28]
PDMA0_TR_OUT[29]
PDMA0_TR_OUT[30]
PDMA0_TR_OUT[33]
PDMA0_TR_OUT[34]
PDMA0_TR_OUT[36]
PDMA0_TR_OUT[37]
PDMA0_TR_OUT[42]
PDMA0_TR_OUT[53]
PDMA0_TR_OUT[54]
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
26
27
28
29
30
31
34
35
37
38
43
54
55
Datasheet
58
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
56
57
58
62
63
PDMA0_TR_OUT[55]
PDMA0_TR_OUT[56]
PDMA0_TR_OUT[57]
PDMA0_TR_OUT[61]
PDMA0_TR_OUT[62]
PDMA0_TR_OUT[63]
PDMA0_TR_OUT[64]
PDMA0_TR_OUT[65]
PDMA0_TR_OUT[66]
PDMA0_TR_OUT[71]
PDMA0_TR_OUT[72]
PDMA0_TR_OUT[81]
PDMA0_TR_OUT[82]
PDMA0_TR_OUT[83]
PDMA0_TR_OUT[84]
PDMA0_TR_OUT[85]
PDMA0_TR_OUT[86]
PDMA0_TR_OUT[87]
PDMA0_TR_OUT[88]
SCB_TX_TR_OUT[0]
SCB_TX_TR_OUT[1]
SCB_TX_TR_OUT[3]
SCB_TX_TR_OUT[4]
SCB_TX_TR_OUT[5]
SCB_TX_TR_OUT[7]
SCB_RX_TR_OUT[0]
SCB_RX_TR_OUT[1]
SCB_RX_TR_OUT[3]
SCB_RX_TR_OUT[4]
SCB_RX_TR_OUT[5]
SCB_RX_TR_OUT[7]
SCB_I2C_SCL_TR_OUT[0]
SCB_I2C_SCL_TR_OUT[1]
SCB_I2C_SCL_TR_OUT[3]
SCB_I2C_SCL_TR_OUT[4]
SCB_I2C_SCL_TR_OUT[5]
SCB_I2C_SCL_TR_OUT[7]
CAN0_DBG_TR_OUT[0:1]
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
64
65
66
67
72
73
82
83
84
85
86
87
88
89
90
91
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
P-DMA0 triggers
SCB0 TTCAN tx Triggers
SCB1 TTCAN tx Triggers
SCB3 TTCAN tx Triggers
SCB4 TTCAN tx Triggers
SCB5 TTCAN tx Triggers
SCB7 TTCAN tx Triggers
SCB0 TTCAN rx Triggers
SCB1 TTCAN rx Triggers
SCB3 TTCAN rx Triggers
SCB4 TTCAN rx Triggers
SCB5 TTCAN rx Triggers
SCB7 TTCAN rx Triggers
SCB0 I2C triggers
SCB1 I2C triggers
SCB3 I2C triggers
SCB4 I2C triggers
SCB5 I2C triggers
SCB7 I2C triggers
CAN0 P-DMA
93
94
95
97
98
99
101
102
103
105
106
107
109
110
111
113
114:115
117:118
CAN0_FIFO0_TR_OUT[0:1] CAN0 FIFO0
Datasheet
59
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
120:121
123:124
126:127
129:130
132:133
135:136
138:139
140:143
144
CAN0_FIFO1_TR_OUT[0:1] CAN0 FIFO1
CAN0_TT_TR_OUT[0:1]
CAN1_DBG_TR_OUT[0:1]
CAN TT Sync Outputs
CAN1 P-DMA
CAN1_FIFO0_TR_OUT[0:1] CAN1 FIFO0
CAN1_FIFO1_TR_OUT[0:1] CAN1 FIFO1
CAN1_TT_TR_OUT[0:1]
CTI_TR_OUT[0:1]
FAULT_TR_OUT[0:3]
TCPWM_32_TR_OUT0[0]
TCPWM_32_TR_OUT0[2]
CAN TT Sync Outputs
Trace events
Fault events
32-bit TCPWM0 Group #2, Counter #0 counters
32-bit TCPWM0 Group #2, Counter #2 counters
146
148
149
150
152
TCPWM_16M_TR_OUT0[0] 16-bit Motor enhanced TCPWM0 Group #1, Counter #0 counters
TCPWM_16M_TR_OUT0[1] 16-bit Motor enhanced TCPWM0 Group #1, Counter #1 counters
TCPWM_16M_TR_OUT0[2] 16-bit Motor enhanced TCPWM0 Group #1, Counter #2 counters
TCPWM_16M_TR_OUT0[4] 16-bit Motor enhanced TCPWM0 Group #1, Counter #4 counters
160
161
162
164
165
166
167
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
TCPWM_16_TR_OUT0[0]
TCPWM_16_TR_OUT0[1]
TCPWM_16_TR_OUT0[2]
TCPWM_16_TR_OUT0[4]
TCPWM_16_TR_OUT0[5]
TCPWM_16_TR_OUT0[6]
TCPWM_16_TR_OUT0[7]
TCPWM_16_TR_OUT0[9]
TCPWM_16_TR_OUT0[10]
TCPWM_16_TR_OUT0[11]
TCPWM_16_TR_OUT0[12]
TCPWM_16_TR_OUT0[13]
TCPWM_16_TR_OUT0[14]
TCPWM_16_TR_OUT0[15]
TCPWM_16_TR_OUT0[16]
TCPWM_16_TR_OUT0[17]
TCPWM_16_TR_OUT0[18]
TCPWM_16_TR_OUT0[19]
TCPWM_16_TR_OUT0[20]
TCPWM_16_TR_OUT0[21]
TCPWM_16_TR_OUT0[22]
TCPWM_16_TR_OUT0[23]
TCPWM_16_TR_OUT0[24]
TCPWM_16_TR_OUT0[25]
TCPWM_16_TR_OUT0[26]
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #0, Counter #4
TCPWM0 Group #0, Counter #5
TCPWM0 Group #0, Counter #6
TCPWM0 Group #0, Counter #7
TCPWM0 Group #0, Counter #9
TCPWM0 Group #0, Counter #10
TCPWM0 Group #0, Counter #11
TCPWM0 Group #0, Counter #12
TCPWM0 Group #0, Counter #13
TCPWM0 Group #0, Counter #14
TCPWM0 Group #0, Counter #15
TCPWM0 Group #0, Counter #16
TCPWM0 Group #0, Counter #17
TCPWM0 Group #0, Counter #18
TCPWM0 Group #0, Counter #19
TCPWM0 Group #0, Counter #20
TCPWM0 Group #0, Counter #21
TCPWM0 Group #0, Counter #22
TCPWM0 Group #0, Counter #23
TCPWM0 Group #0, Counter #24
TCPWM0 Group #0, Counter #25
TCPWM0 Group #0, Counter #26
186
Datasheet
60
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
TCPWM0 Group #0, Counter #33
193
194
196
197
198
199
200
201
202
204
205
206
207
208
209
210
211
212
213
214
215
TCPWM_16_TR_OUT0[33]
TCPWM_16_TR_OUT0[34]
TCPWM_16_TR_OUT0[36]
TCPWM_16_TR_OUT0[37]
TCPWM_16_TR_OUT0[38]
TCPWM_16_TR_OUT0[39]
TCPWM_16_TR_OUT0[40]
TCPWM_16_TR_OUT0[41]
TCPWM_16_TR_OUT0[42]
TCPWM_16_TR_OUT0[44]
TCPWM_16_TR_OUT0[45]
TCPWM_16_TR_OUT0[46]
TCPWM_16_TR_OUT0[47]
TCPWM_16_TR_OUT0[48]
TCPWM_16_TR_OUT0[49]
TCPWM_16_TR_OUT0[50]
TCPWM_16_TR_OUT0[51]
TCPWM_16_TR_OUT0[52]
TCPWM_16_TR_OUT0[53]
TCPWM_16_TR_OUT0[54]
TCPWM_16_TR_OUT0[55]
TCPWM0 Group #0, Counter #34
TCPWM0 Group #0, Counter #36
TCPWM0 Group #0, Counter #37
TCPWM0 Group #0, Counter #38
TCPWM0 Group #0, Counter #39
TCPWM0 Group #0, Counter #40
TCPWM0 Group #0, Counter #41
TCPWM0 Group #0, Counter #42
TCPWM0 Group #0, Counter #44
TCPWM0 Group #0, Counter #45
TCPWM0 Group #0, Counter #46
TCPWM0 Group #0, Counter #47
TCPWM0 Group #0, Counter #48
TCPWM0 Group #0, Counter #49
TCPWM0 Group #0, Counter #50
TCPWM0 Group #0, Counter #51
TCPWM0 Group #0, Counter #52
TCPWM0 Group #0, Counter #53
TCPWM0 Group #0, Counter #54
TCPWM0 Group #0, Counter #55
MUX Group 10: DebugReduction2 (Debug Reduction #2)
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
PDMA1_TR_OUT[0]
PDMA1_TR_OUT[1]
PDMA1_TR_OUT[2]
PDMA1_TR_OUT[3]
PDMA1_TR_OUT[4]
PDMA1_TR_OUT[5]
PDMA1_TR_OUT[6]
PDMA1_TR_OUT[7]
PDMA1_TR_OUT[8]
PDMA1_TR_OUT[9]
PDMA1_TR_OUT[10]
PDMA1_TR_OUT[11]
PDMA1_TR_OUT[14]
PDMA1_TR_OUT[15]
PDMA1_TR_OUT[16]
PDMA1_TR_OUT[17]
PDMA1_TR_OUT[18]
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
Datasheet
61
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
20
23
24
25
26
27
28
29
30
34:35
38
40
42
43
44
46
54
55
56
58
59
60
61
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
PDMA1_TR_OUT[19]
PDMA1_TR_OUT[22]
PDMA1_TR_OUT[23]
PDMA1_TR_OUT[24]
PDMA1_TR_OUT[25]
PDMA1_TR_OUT[26]
PDMA1_TR_OUT[27]
PDMA1_TR_OUT[28]
PDMA1_TR_OUT[29]
MDMA_TR_OUT[0:1]
TCPWM_32_TR_OUT1[0]
TCPWM_32_TR_OUT1[2]
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit TCPWM0 counters
32-bit TCPWM0 counters
32-bit TCPWM0 counters
TCPWM_16M_TR_OUT1[0] 16-bit Motor enhanced TCPWM0 counters
TCPWM_16M_TR_OUT1[1] 16-bit Motor enhanced TCPWM0 counters
TCPWM_16M_TR_OUT1[2] 16-bit Motor enhanced TCPWM0 counters
TCPWM_16M_TR_OUT1[4] 16-bit Motor enhanced TCPWM0 counters
TCPWM_16_TR_OUT1[0]
TCPWM_16_TR_OUT1[1]
TCPWM_16_TR_OUT1[2]
TCPWM_16_TR_OUT1[4]
TCPWM_16_TR_OUT1[5]
TCPWM_16_TR_OUT1[6]
TCPWM_16_TR_OUT1[7]
TCPWM_16_TR_OUT1[9]
TCPWM_16_TR_OUT1[10]
TCPWM_16_TR_OUT1[11]
TCPWM_16_TR_OUT1[12]
TCPWM_16_TR_OUT1[13]
TCPWM_16_TR_OUT1[14]
TCPWM_16_TR_OUT1[15]
TCPWM_16_TR_OUT1[16]
TCPWM_16_TR_OUT1[17]
TCPWM_16_TR_OUT1[18]
TCPWM_16_TR_OUT1[19]
TCPWM_16_TR_OUT1[20]
TCPWM_16_TR_OUT1[21]
TCPWM_16_TR_OUT1[22]
TCPWM_16_TR_OUT1[23]
TCPWM_16_TR_OUT1[24]
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
Datasheet
62
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
Trigger inputs (continued)
Trigger label
(TRIG_LABEL)
Description
79
80
87
88
90
TCPWM_16_TR_OUT1[25]
TCPWM_16_TR_OUT1[26]
TCPWM_16_TR_OUT1[33]
TCPWM_16_TR_OUT1[34]
TCPWM_16_TR_OUT1[36]
TCPWM_16_TR_OUT1[37]
TCPWM_16_TR_OUT1[38]
TCPWM_16_TR_OUT1[39]
TCPWM_16_TR_OUT1[40]
TCPWM_16_TR_OUT1[41]
TCPWM_16_TR_OUT1[42]
TCPWM_16_TR_OUT1[44]
TCPWM_16_TR_OUT1[45]
TCPWM_16_TR_OUT1[46]
TCPWM_16_TR_OUT1[47]
TCPWM_16_TR_OUT1[48]
TCPWM_16_TR_OUT1[49]
TCPWM_16_TR_OUT1[50]
TCPWM_16_TR_OUT1[51]
TCPWM_16_TR_OUT1[52]
TCPWM_16_TR_OUT1[53]
TCPWM_16_TR_OUT1[54]
TCPWM_16_TR_OUT1[55]
PASS_GEN_TR_OUT[0:5]
EVTGEN_TR_OUT[0:10]
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
16-bit TCPWM0 counters
91
92
93
94
95
96
98
99
100
101
102
103
104
105
106
107
108
109
117:122
123:133
PASS SAR conversion complete events
EVTGEN Triggers
Datasheet
63
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group outputs
19
Triggers group outputs
Table 19-1
Trigger outputs
Output
MUX Group 0: PDMA0_TR (P-DMA0 trigger multiplexer)
0:7 PDMA0_TR_IN[0:7]
MUX Group 1: PDMA1_TR (P-DMA1 trigger multiplexer)
0:7 PDMA1_TR_IN[0:7]
MUX Group 2: MDMA (M-DMA0 trigger multiplexer)
0:1 MDMA_TR_IN[0:1]
MUX Group 3: TCPWM_TO_PDMA0 (TCPWM0 to P-DMA0 trigger multiplexer)
0:7 PDMA0_TR_IN[8:15]
MUX Group 4: TCPWM_OUT (TCPWM0 loop back multiplexer)
0:15 TCPWM_ALL_CNT_TR_IN[0:15]
MUX Group 5: TCPWM_IN (TCPWM0 Trigger Multiplexer)
0:10 TCPWM_ALL_CNT_TR_IN[16:26]
MUX Group 6: PASS (PASS SAR trigger multiplexer)
Trigger Label (TRIG_LABEL)
Description
Triggers to P-DMA0[0:7]
Triggers to P-DMA1[0:7]
Triggers to M-DMA0
Triggers to P-DMA0[8:15]
All counters trigger input
Triggers to TCPWM0
0
1
2
3
4
5
8
9
11
PASS_GEN_TR_IN[0]
PASS_GEN_TR_IN[1]
PASS_GEN_TR_IN[2]
PASS_GEN_TR_IN[3]
PASS_GEN_TR_IN[4]
PASS_GEN_TR_IN[5]
PASS_GEN_TR_IN[8]
PASS_GEN_TR_IN[9]
PASS_GEN_TR_IN[11]
Triggers to SAR ADCs
Triggers to SAR ADCs
Triggers to SAR ADCs
Triggers to SAR ADCs
Triggers to SAR ADCs
Triggers to SAR ADCs
Triggers to SAR ADCs
Triggers to SAR ADCs
Triggers to SAR ADCs
MUX Group 7: CANTT (CAN TT Sync)
0:1
3:4
CAN0_TT_TR_IN[0:1]
CAN1_TT_TR_IN[0:1]
CAN0 TT Sync Inputs
CAN1 TT Sync Inputs
MUX Group 8: DebugMain (Debug Multiplexer)
0:1
2:3
4
5
6
HSIOM_IO_OUTPUT[0:1]
CTI_TR_IN[0:1]
PERI_DEBUG_FREEZE_TR_IN
PASS_DEBUG_FREEZE_TR_IN
SRSS_WDT_DEBUG_FREEZE_TR_IN
SRSS_MCWDT_DEBUG_-
FREEZE_TR_IN[0:1]
To HSIOM as an output
To CPU Cross Trigger system
Signal to Freeze PERI operation
Signal to Freeze SAR ADC operation
Signal to Freeze WDT operation
Signal to Freeze MCWDT operation
7:8
9
TCPWM_DEBUG_FREEZE_TR_IN
Signal to Freeze TCPWM0 operation
To main debug multiplexer
MUX Group 9: DebugReduction1 (Debug Reduction #1)
0:4 TR_GROUP8_INPUT[1:5]
MUX Group 10: DebugReduction2 (Debug Reduction #2)
0:4
TR_GROUP8_INPUT[6:10]
To main debug multiplexer
Datasheet
64
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers one-to-one
20
Triggers one-to-one
Table 20-1
Triggers 1:1
Input
Trigger In
Trigger Out
Description
MUX Group 0: TCPWM0 to LIN0 Triggers
0
1
2
4
TCPWM0_16_TR_OUT0[0]
TCPWM0_16_TR_OUT0[1]
TCPWM0_16_TR_OUT0[2]
TCPWM0_16_TR_OUT0[4]
LIN0_CMD_TR_IN[0]
TCPWM0 (Group #0 Counter #00) to LIN0
TCPWM0 (Group #0 Counter #01) to LIN1
TCPWM0 (Group #0 Counter #02) to LIN2
TCPWM0 (Group #0 Counter #04) to LIN4
LIN0_CMD_TR_IN[1]
LIN0_CMD_TR_IN[2]
LIN0_CMD_TR_IN[4]
MUX Group 1: TCPWM0 to PASS SARx direct connect
0
1
TCPWM0_16M_TR_OUT1[0]
TCPWM0_16M_TR_OUT1[1]
TCPWM0_16M_TR_OUT1[2]
TCPWM0_16_TR_OUT1[0]
TCPWM0_16_TR_OUT1[1]
TCPWM0_16_TR_OUT1[4]
TCPWM0_16_TR_OUT1[5]
TCPWM0_16_TR_OUT1[7]
TCPWM0_16_TR_OUT1[13]
TCPWM0_16_TR_OUT1[20]
TCPWM0_16_TR_OUT1[21]
TCPWM0_16_TR_OUT1[22]
TCPWM0_16_TR_OUT1[23]
TCPWM0_16_TR_OUT1[24]
TCPWM0_16_TR_OUT1[33]
TCPWM0_16_TR_OUT1[38]
TCPWM0_16_TR_OUT1[39]
PASS0_CH_TR_IN[0]
PASS0_CH_TR_IN[1]
PASS0_CH_TR_IN[2]
PASS0_CH_TR_IN[4]
PASS0_CH_TR_IN[5]
PASS0_CH_TR_IN[8]
PASS0_CH_TR_IN[9]
PASS0_CH_TR_IN[11]
PASS0_CH_TR_IN[17]
PASS0_CH_TR_IN[36]
PASS0_CH_TR_IN[37]
PASS0_CH_TR_IN[38]
PASS0_CH_TR_IN[39]
PASS0_CH_TR_IN[40]
PASS0_CH_TR_IN[49]
PASS0_CH_TR_IN[54]
PASS0_CH_TR_IN[55]
PASS0_CH_TR_IN[68:71]
TCPWM0 Group #1 Counter #00 (PWM0_M_0) to SAR0 ch#0
TCPWM0 Group #1 Counter #03 (PWM0_M_3) to SAR0 ch#1
TCPWM0 Group #1 Counter #06 (PWM0_M_6) to SAR0 ch#2
TCPWM0 Group #0 Counter #00 (PWM0_0) to SAR0 ch#4
TCPWM0 Group #0 Counter #01 (PWM0_1) to SAR0 ch#5
TCPWM0 Group #0 Counter #04 (PWM0_4) to SAR0 ch#8
TCPWM0 Group #0 Counter #05 (PWM0_5) to SAR0 ch#9
TCPWM0 Group #0 Counter #07 (PWM0_7) to SAR0 ch#11
TCPWM0 Group #0 Counter #13 (PWM0_13) to SAR0 ch#17
TCPWM0 Group #0 Counter #20 (PWM0_20) to SAR1 ch#4
TCPWM0 Group #0 Counter #21 (PWM0_21) to SAR1 ch#5
TCPWM0 Group #0 Counter #22 (PWM0_22) to SAR1 ch#6
TCPWM0 Group #0 Counter #23 (PWM0_23) to SAR1 ch#7
TCPWM0 Group #0 Counter #24 (PWM0_24) to SAR1 ch#8
TCPWM0 Group #0 Counter #33 (PWM0_33) to SAR1 ch#17
TCPWM0 Group #0 Counter #38 (PWM0_38) to SAR1 ch#22
TCPWM0 Group #0 Counter #39 (PWM0_39) to SAR1 ch#23
2
4
5
8
9
11
17
28
29
30
31
32
41
46
47
60:63 TCPWM0_16_TR_OUT1[48:51]
TCPWM0 Group #0 Counter #48 through 51 (PWM0_48 to
PWM0_51) to SAR2 ch#4 through SAR2 ch#7
MUX Group 2: PASS SARx to P-DMA0 direct connect
0
1
PASS0_CH_DONE_TR_OUT[0]
PASS0_CH_DONE_TR_OUT[1]
PASS0_CH_DONE_TR_OUT[2]
PASS0_CH_DONE_TR_OUT[3]
PASS0_CH_DONE_TR_OUT[4]
PASS0_CH_DONE_TR_OUT[5]
PASS0_CH_DONE_TR_OUT[8]
PASS0_CH_DONE_TR_OUT[9]
PASS0_CH_DONE_TR_OUT[11]
PASS0_CH_DONE_TR_OUT[12]
PASS0_CH_DONE_TR_OUT[17]
PASS0_CH_DONE_TR_OUT[36]
PASS0_CH_DONE_TR_OUT[37]
PASS0_CH_DONE_TR_OUT[38]
PASS0_CH_DONE_TR_OUT[39]
PASS0_CH_DONE_TR_OUT[40]
PASS0_CH_DONE_TR_OUT[44]
PASS0_CH_DONE_TR_OUT[45]
PDMA0_TR_IN[25]
PDMA0_TR_IN[26]
PDMA0_TR_IN[27]
PDMA0_TR_IN[28]
PDMA0_TR_IN[29]
PDMA0_TR_IN[30]
PDMA0_TR_IN[33]
PDMA0_TR_IN[34]
PDMA0_TR_IN[36]
PDMA0_TR_IN[37]
PDMA0_TR_IN[42]
PDMA0_TR_IN[53]
PDMA0_TR_IN[54]
PDMA0_TR_IN[55]
PDMA0_TR_IN[56]
PDMA0_TR_IN[57]
PDMA0_TR_IN[61]
PDMA0_TR_IN[62]
PASS SAR0 ch#0 to P-DMA0 direct connect
PASS SAR0 ch#1 to P-DMA0 direct connect
PASS SAR0 ch#2 to P-DMA0 direct connect
PASS SAR0 ch#3 to P-DMA0 direct connect
PASS SAR0 ch#4 to P-DMA0 direct connect
PASS SAR0 ch#5 to P-DMA0 direct connect
PASS SAR0 ch#8 to P-DMA0 direct connect
PASS SAR0 ch#9 to P-DMA0 direct connect
PASS SAR0 ch#11 to P-DMA0 direct connect
PASS SAR0 ch#12 to P-DMA0 direct connect
PASS SAR0 ch#17 to P-DMA0 direct connect
PASS SAR1 ch#4 to P-DMA0 direct connect
PASS SAR1 ch#5 to P-DMA0 direct connect
PASS SAR1 ch#6 to P-DMA0 direct connect
PASS SAR1 ch#7 to P-DMA0 direct connect
PASS SAR1 ch#8 to P-DMA0 direct connect
PASS SAR1 ch#12 to P-DMA0 direct connect
PASS SAR1 ch#13 to P-DMA0 direct connect
2
3
4
5
8
9
11
12
17
28
29
30
31
32
36
37
Datasheet
65
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers one-to-one
Table 20-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
PDMA0_TR_IN[63]
Description
38
39
40
41
46
47
56
57
58
59
60
61
62
63
PASS0_CH_DONE_TR_OUT[46]
PASS0_CH_DONE_TR_OUT[47]
PASS SAR1 ch#14 to P-DMA0 direct connect
PASS SAR1 ch#15 to P-DMA0 direct connect
PASS SAR1 ch#16 to P-DMA0 direct connect
PASS SAR1 ch#17 to P-DMA0 direct connect
PASS SAR1 ch#22 to P-DMA0 direct connect
PASS SAR1 ch#23 to P-DMA0 direct connect
PASS SAR2 ch#0 to P-DMA0 direct connect
PASS SAR2 ch#1 to P-DMA0 direct connect
PASS SAR2 ch#2 to P-DMA0 direct connect
PASS SAR2 ch#3 to P-DMA0 direct connect
PASS SAR2 ch#4 to P-DMA0 direct connect
PASS SAR2 ch#5 to P-DMA0 direct connect
PASS SAR2 ch#6 to P-DMA0 direct connect
PASS SAR2 ch#7 to P-DMA0 direct connect
PDMA0_TR_IN[64]
PDMA0_TR_IN[65]
PDMA0_TR_IN[66]
PDMA0_TR_IN[71]
PDMA0_TR_IN[72]
PDMA0_TR_IN[81]
PDMA0_TR_IN[82]
PDMA0_TR_IN[83]
PDMA0_TR_IN[84]
PDMA0_TR_IN[85]
PDMA0_TR_IN[86]
PDMA0_TR_IN[87]
PDMA0_TR_IN[88]
PASS0_CH_DONE_TR_OUT[48]
PASS0_CH_DONE_TR_OUT[49]
PASS0_CH_DONE_TR_OUT[54]
PASS0_CH_DONE_TR_OUT[55]
PASS0_CH_DONE_TR_OUT[64]
PASS0_CH_DONE_TR_OUT[65]
PASS0_CH_DONE_TR_OUT[66]
PASS0_CH_DONE_TR_OUT[67]
PASS0_CH_DONE_TR_OUT[68]
PASS0_CH_DONE_TR_OUT[69]
PASS0_CH_DONE_TR_OUT[70]
PASS0_CH_DONE_TR_OUT[71]
MUX Group 3: PASS SARx to TCPWM0 direct connect
0
PASS0_CH_RANGEVIO_TR_OUT[0]
PASS0_CH_RANGEVIO_TR_OUT[4]
PASS0_CH_RANGEVIO_TR_OUT[5]
PASS0_CH_RANGEVIO_TR_OUT[8]
PASS0_CH_RANGEVIO_TR_OUT[9]
PASS0_CH_RANGEVIO_TR_OUT[11]
PASS0_CH_RANGEVIO_TR_OUT[17]
PASS0_CH_RANGEVIO_TR_OUT[36]
PASS0_CH_RANGEVIO_TR_OUT[37]
PASS0_CH_RANGEVIO_TR_OUT[38]
PASS0_CH_RANGEVIO_TR_OUT[39]
PASS0_CH_RANGEVIO_TR_OUT[40]
PASS0_CH_RANGEVIO_TR_OUT[49]
PASS0_CH_RANGEVIO_TR_OUT[54]
PASS0_CH_RANGEVIO_TR_OUT[55]
PASS0_CH_RANGEVIO_TR_OUT[64]
PASS0_CH_RANGEVIO_TR_OUT[68]
PASS0_CH_RANGEVIO_TR_OUT[69]
PASS0_CH_RANGEVIO_TR_OUT[70]
TCPWM0_16M_ONE_CNT_TR_IN[0] SAR0 ch#0[32], range violation to TCPWM0 Group #1 Counter
#00 trig=2
4
TCPWM0_16_ONE_CNT_TR_IN[0]
TCPWM0_16_ONE_CNT_TR_IN[1]
TCPWM0_16_ONE_CNT_TR_IN[4]
TCPWM0_16_ONE_CNT_TR_IN[5]
TCPWM0_16_ONE_CNT_TR_IN[7]
SAR0 ch#4, range violation to TCPWM0 Group #0 Counter #00
trig=2
5
SAR0 ch#5, range violation to TCPWM0 Group #0 Counter #01
trig=2
8
SAR0 ch#8, range violation to TCPWM0 Group #0 Counter #04
trig=2
9
SAR0 ch#9, range violation to TCPWM0 Group #0 Counter #05
trig=2
11
17
28
29
30
31
32
41
46
47
56
60
61
62
Note
SAR0 ch#11, range violation to TCPWM0 Group #0 Counter
#07 trig=2
TCPWM0_16_ONE_CNT_TR_IN[13] SAR0 ch#17, range violation to TCPWM0 Group #0 Counter
#13 trig=2
TCPWM0_16_ONE_CNT_TR_IN[20] SAR1 ch#4, range violation to TCPWM0 Group #0 Counter #20
trig=2
TCPWM0_16_ONE_CNT_TR_IN[21] SAR1 ch#5, range violation to TCPWM0 Group #0 Counter #21
trig=2
TCPWM0_16_ONE_CNT_TR_IN[22] SAR1 ch#6, range violation to TCPWM0 Group #0 Counter #22
trig=2
TCPWM0_16_ONE_CNT_TR_IN[23] SAR1 ch#7, range violation to TCPWM0 Group #0 Counter #23
trig=2
TCPWM0_16_ONE_CNT_TR_IN[24] SAR1 ch#8, range violation to TCPWM0 Group #0 Counter #24
trig=2
TCPWM0_16_ONE_CNT_TR_IN[33] SAR1 ch#17, range violation to TCPWM0 Group #0 Counter
#33 trig=2
TCPWM0_16_ONE_CNT_TR_IN[38] SAR1 ch#22, range violation to TCPWM0 Group #0 Counter
#38 trig=2
TCPWM0_16_ONE_CNT_TR_IN[39] SAR1 ch#23, range violation to TCPWM0 Group #0 Counter
#39 trig=2
TCPWM0_16M_ONE_CNT_TR_IN[2] SAR2 ch#0, range violation to TCPWM0 Group #1 Counter #02
trig=2
TCPWM0_16_ONE_CNT_TR_IN[48] SAR2 ch#4, range violation to TCPWM0 Group #0 Counter #48
trig=2
TCPWM0_16_ONE_CNT_TR_IN[49] SAR2 ch#5, range violation to TCPWM0 Group #0 Counter #49
trig=2
TCPWM0_16_ONE_CNT_TR_IN[50] SAR2 ch#6, range violation to TCPWM0 Group #0 Counter #50
trig=2
32.Each logical channel of SAR ADC[x] can be connected to any of the SAR ADC[x]_y external pin. (x = 0, or 1, or, 2 and y=0 to max 31)
Datasheet
66
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers one-to-one
Table 20-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
63
PASS0_CH_RANGEVIO_TR_OUT[71]
TCPWM0_16_ONE_CNT_TR_IN[51] SAR2 ch#7, range violation to TCPWM0 Group #0 Counter #51
trig=2
MUX Group 4: CAN0 to P-DMA0 Triggers
0
1
2
3
4
5
CAN0_DBG_TR_OUT[0]
CAN0_FIFO0_TR_OUT[0]
CAN0_FIFO1_TR_OUT[0]
CAN0_DBG_TR_OUT[1]
CAN0_FIFO0_TR_OUT[1]
CAN0_FIFO1_TR_OUT[1]
PDMA0_TR_IN[16]
PDMA0_TR_IN[17]
PDMA0_TR_IN[18]
PDMA0_TR_IN[19]
PDMA0_TR_IN[20]
PDMA0_TR_IN[21]
CAN0, Channel #0 P-DMA0 trigger
CAN0, Channel #0 FIFO0 trigger
CAN0, Channel #0 FIFO1 trigger
CAN0, Channel #1 P-DMA0 trigger
CAN0, Channel #1 FIFO0 trigger
CAN0, Channel #1 FIFO1 trigger
MUX Group 5: CAN1 to P-DMA1 triggers
0
1
2
3
4
5
CAN1_DBG_TR_OUT[0]
CAN1_FIFO0_TR_OUT[0]
CAN1_FIFO1_TR_OUT[0]
CAN1_DBG_TR_OUT[1]
CAN1_FIFO0_TR_OUT[1]
CAN1_FIFO1_TR_OUT[1]
PDMA1_TR_IN[24]
PDMA1_TR_IN[25]
PDMA1_TR_IN[26]
PDMA1_TR_IN[27]
PDMA1_TR_IN[28]
PDMA1_TR_IN[29]
CAN1, Channel #0 P-DMA01 trigger
CAN1, Channel #0 FIFO0 trigger
CAN1, Channel #0 FIFO1 trigger
CAN1, Channel #1 P-DMA1 trigger
CAN1, Channel #1 FIFO0 trigger
CAN1, Channel #1 FIFO1 trigger
MUX Group 6:Acknowledge triggers from P-DMA0 to CAN0
0
1
PDMA0_TR_OUT[16]
PDMA0_TR_OUT[19]
CAN0_DBG_TR_ACK[0]
CAN0_DBG_TR_ACK[1]
CAN0, Channel #0 P-DMA0 acknowledge
CAN0, Channel #1 P-DMA0 acknowledge
MUX Group 7: Acknowledge triggers from P-DMA1 to CAN1
0
1
PDMA1_TR_OUT[24]
PDMA1_TR_OUT[27]
CAN1_DBG_TR_ACK[0]
CAN1_DBG_TR_ACK[1]
CAN1, Channel #0 P-DMA1 acknowledge
CAN1, Channel #1 P-DMA1 acknowledge
MUX Group 8: SCBx to P-DMA1 Triggers
0
1
SCB0_TX_TR_OUT
SCB0_RX_TR_OUT
SCB1_TX_TR_OUT
SCB1_RX_TR_OUT
SCB3_TX_TR_OUT
SCB3_RX_TR_OUT
SCB4_TX_TR_OUT
SCB4_RX_TR_OUT
SCB5_TX_TR_OUT
SCB5_RX_TR_OUT
SCB7_TX_TR_OUT
SCB7_RX_TR_OUT
PDMA1_TR_IN[8]
PDMA1_TR_IN[9]
PDMA1_TR_IN[10]
PDMA1_TR_IN[11]
PDMA1_TR_IN[14]
PDMA1_TR_IN[15]
PDMA1_TR_IN[16]
PDMA1_TR_IN[17]
PDMA1_TR_IN[18]
PDMA1_TR_IN[19]
PDMA1_TR_IN[22]
PDMA1_TR_IN[23]
SCB0 TX to P-DMA1 Trigger
SCB0 RX to P-DMA1 Trigger
SCB1 TX to P-DMA1 Trigger
SCB1 RX to P-DMA1 Trigger
SCB3 TX to P-DMA1 Trigger
SCB3 RX to P-DMA1 Trigger
SCB4 TX to P-DMA1 Trigger
SCB4 RX to P-DMA1 Trigger
SCB5 TX to P-DMA1 Trigger
SCB5 RX to P-DMA1 Trigger
SCB7 TX to P-DMA1 Trigger
SCB7 RX to P-DMA1 Trigger
2
3
6
7
8
9
10
11
14
15
Datasheet
67
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral clocks
21
Peripheral clocks
Table 21-1
Peripheral clock assignments
Destination
Output
0
Description
PCLK_CPUSS_CLOCK_TRACE_IN
PCLK_SMARTIO12_CLOCK
PCLK_SMARTIO13_CLOCK
PCLK_SMARTIO14_CLOCK
PCLK_CANFD0_CLOCK_CAN0
PCLK_CANFD0_CLOCK_CAN1
PCLK_CANFD1_CLOCK_CAN0
PCLK_CANFD1_CLOCK_CAN1
PCLK_LIN0_CLOCK_CH_EN0
PCLK_LIN0_CLOCK_CH_EN1
PCLK_LIN0_CLOCK_CH_EN2
PCLK_LIN0_CLOCK_CH_EN3
PCLK_LIN0_CLOCK_CH_EN4
PCLK_SCB0_CLOCK
Trace clock
SMART I/O #12
SMART I/O #13
SMART I/O #14
CAN0, Channel #0
CAN0, Channel #1
CAN1, Channel #0
CAN1, Channel #1
LIN0, Channel #0
LIN0, Channel #1
LIN0, Channel #2
LIN0, Channel #3
LIN0, Channel #4
SCB0
SCB1
SCB3
SCB4
SCB5
SCB7
SAR0
SAR1
SAR2
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #0, Counter #4
TCPWM0 Group #0, Counter #5
TCPWM0 Group #0, Counter #6
TCPWM0 Group #0, Counter #7
TCPWM0 Group #0, Counter #9
TCPWM0 Group #0, Counter #10
TCPWM0 Group #0, Counter #11
TCPWM0 Group #0, Counter #12
TCPWM0 Group #0, Counter #13
TCPWM0 Group #0, Counter #14
TCPWM0 Group #0, Counter #15
TCPWM0 Group #0, Counter #16
TCPWM0 Group #0, Counter #17
1
2
3
6
7
9
10
12
13
14
15
16
20
21
23
24
25
27
28
29
30
31
32
33
35
36
37
38
40
41
42
43
44
45
46
47
48
PCLK_SCB1_CLOCK
PCLK_SCB3_CLOCK
PCLK_SCB4_CLOCK
PCLK_SCB5_CLOCK
PCLK_SCB7_CLOCK
PCLK_PASS0_CLOCK_SAR0
PCLK_PASS0_CLOCK_SAR1
PCLK_PASS0_CLOCK_SAR2
PCLK_TCPWM0_CLOCKS0
PCLK_TCPWM0_CLOCKS1
PCLK_TCPWM0_CLOCKS2
PCLK_TCPWM0_CLOCKS4
PCLK_TCPWM0_CLOCKS5
PCLK_TCPWM0_CLOCKS6
PCLK_TCPWM0_CLOCKS7
PCLK_TCPWM0_CLOCKS9
PCLK_TCPWM0_CLOCKS10
PCLK_TCPWM0_CLOCKS11
PCLK_TCPWM0_CLOCKS12
PCLK_TCPWM0_CLOCKS13
PCLK_TCPWM0_CLOCKS14
PCLK_TCPWM0_CLOCKS15
PCLK_TCPWM0_CLOCKS16
PCLK_TCPWM0_CLOCKS17
Datasheet
68
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral clocks
Table 21-1
Output
49
Peripheral clock assignments (continued)
Destination
Description
TCPWM0 Group #0, Counter #18
TCPWM0 Group #0, Counter #19
TCPWM0 Group #0, Counter #20
TCPWM0 Group #0, Counter #21
TCPWM0 Group #0, Counter #22
TCPWM0 Group #0, Counter #23
TCPWM0 Group #0, Counter #24
TCPWM0 Group #0, Counter #25
TCPWM0 Group #0, Counter #26
TCPWM0 Group #0, Counter #33
TCPWM0 Group #0, Counter #34
TCPWM0 Group #0, Counter #36
TCPWM0 Group #0, Counter #37
TCPWM0 Group #0, Counter #38
TCPWM0 Group #0, Counter #39
TCPWM0 Group #0, Counter #40
TCPWM0 Group #0, Counter #41
TCPWM0 Group #0, Counter #42
TCPWM0 Group #0, Counter #44
TCPWM0 Group #0, Counter #45
TCPWM0 Group #0, Counter #46
TCPWM0 Group #0, Counter #47
TCPWM0 Group #0, Counter #48
TCPWM0 Group #0, Counter #49
TCPWM0 Group #0, Counter #50
TCPWM0 Group #0, Counter #51
TCPWM0 Group #0, Counter #52
TCPWM0 Group #0, Counter #53
TCPWM0 Group #0, Counter #54
TCPWM0 Group #0, Counter #55
TCPWM0 Group #1, Counter #0
TCPWM0 Group #1, Counter #1
TCPWM0 Group #1, Counter #2
TCPWM0 Group #1, Counter #4
TCPWM0 Group #2, Counter #0
TCPWM0 Group #2, Counter #2
PCLK_TCPWM0_CLOCKS18
PCLK_TCPWM0_CLOCKS19
PCLK_TCPWM0_CLOCKS20
PCLK_TCPWM0_CLOCKS21
PCLK_TCPWM0_CLOCKS22
PCLK_TCPWM0_CLOCKS23
PCLK_TCPWM0_CLOCKS24
PCLK_TCPWM0_CLOCKS25
PCLK_TCPWM0_CLOCKS26
PCLK_TCPWM0_CLOCKS33
PCLK_TCPWM0_CLOCKS34
PCLK_TCPWM0_CLOCKS36
PCLK_TCPWM0_CLOCKS37
PCLK_TCPWM0_CLOCKS38
PCLK_TCPWM0_CLOCKS39
PCLK_TCPWM0_CLOCKS40
PCLK_TCPWM0_CLOCKS41
PCLK_TCPWM0_CLOCKS42
PCLK_TCPWM0_CLOCKS44
PCLK_TCPWM0_CLOCKS45
PCLK_TCPWM0_CLOCKS46
PCLK_TCPWM0_CLOCKS47
PCLK_TCPWM0_CLOCKS48
PCLK_TCPWM0_CLOCKS49
PCLK_TCPWM0_CLOCKS50
PCLK_TCPWM0_CLOCKS51
PCLK_TCPWM0_CLOCKS52
PCLK_TCPWM0_CLOCKS53
PCLK_TCPWM0_CLOCKS54
PCLK_TCPWM0_CLOCKS55
PCLK_TCPWM0_CLOCKS256
PCLK_TCPWM0_CLOCKS257
PCLK_TCPWM0_CLOCKS258
PCLK_TCPWM0_CLOCKS260
PCLK_TCPWM0_CLOCKS512
PCLK_TCPWM0_CLOCKS514
50
51
52
53
54
55
56
57
64
65
67
68
69
70
71
72
73
75
76
77
78
79
80
81
82
83
84
85
86
94
95
96
98
106
108
Datasheet
69
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Faults
22
Faults
Table 22-1
Fault assignments
Fault
Source
Description
CM0+ SMPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
0
CPUSS_MPU_VIO_0
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
1
2
CPUSS_MPU_VIO_1
Crypto SMPU violation. See CPUSS_MPU_VIO_0 description.
CPUSS_MPU_VIO_2
CPUSS_MPU_VIO_3
CPUSS_MPU_VIO_4
CPUSS_MPU_VIO_15
CPUSS_MPU_VIO_16
P-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
P-DMA1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
M-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Test Controller MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CM4 system bus AHB-Lite interface MPU violation. See CPUSS_MPU_VIO_0 description.
3
4
15
16
CM4 code bus AHB-Lite interface MPU violation for non flash controller accesses.
See CPUSS_MPU_VIO_0 description.
17
18
CPUSS_MPU_VIO_17
CPUSS_MPU_VIO_18
CM4 code bus AHB-Lite interface MPU violation for flash controller accesses.
See CPUSS_MPU_VIO_0 description.
Peripheral protection SRAM correctable ECC violation
DATA0[10:0]: Violating address.
26
27
PERI_PERI_C_ECC
PERI_PERI_NC_ECC
DATA1[7:0]: Syndrome of SRAM word.
Peripheral protection SRAM non-correctable ECC violation
CM0+ Peripheral Master Interface PPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
28
PERI_MS_VIO_0
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: master interface, PPU violation, “1': timeout detected, “2”: bus error,
other: undefined.
CM4 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
29
30
31
PERI_MS_VIO_1
PERI_MS_VIO_2
PERI_MS_VIO_3
P-DMA0 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
P-DMA1 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
Peripheral Group #0 violation.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
32
PERI_GROUP_VIO_0
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: decoder or peripheral bus error, other: undefined.
33
34
35
37
38
PERI_GROUP_VIO_1
PERI_GROUP_VIO_2
PERI_GROUP_VIO_3
PERI_GROUP_VIO_5
PERI_GROUP_VIO_6
Peripheral Group #1 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #2 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #3 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #5 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #6 violation. See PERI_GROUP_VIO_0 description.
Datasheet
70
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Faults
Table 22-1
Fault assignments (continued)
Fault
Source
Description
41
48
PERI_GROUP_VIO_9
CPUSS_FLASHC_MAIN_BUS_ERROR
Peripheral Group #9 violation. See PERI_GROUP_VIO_0 description.
Flash controller main flash bus error
FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive
32-bit system address.
FAULT_DATA1[11:8]: Master identifier.
Flash controller main flash correctable ECC violation
DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit
system address.
49
CPUSS_FLASHC_MAIN_C_ECC
DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00).
DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08).
DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10).
DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18).
Flash controller main flash non-correctable ECC violation.
See CPUSS_FLASHC_MAIN_C_ECC description.
50
51
CPUSS_FLASHC_MAIN_NC_ECC
Flash controller work-flash bus error.
CPUSS_FLASHC_WORK_BUS_ERROR
See CPUSS_FLASHC_MAIN_BUS_ERR description.
Flash controller work flash correctable ECC violation.
DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit
system address.
52
53
CPUSS_FLASHC_WORK_C_ECC
CPUSS_FLASHC_WORK_NC_ECC
DATA1[6:0]: Syndrome of 32-bit word.
Flash controller work-flash non-correctable ECC violation.
See CPUSS_FLASHC_WORK_C_ECC description.
Flash controller CM0+ cache correctable ECC violation.
DATA0[26:0]: Violating address.
DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0).
DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4).
DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8).
DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc).
54
CPUSS_FLASHC_CM0_CA_C_ECC
Flash controller CM0+ cache non-correctable ECC violation.
See CPUSS_FLASHC_CM0_CA_C_ECC description.
55
56
57
CPUSS_FLASHC_CM0_CA_NC_ECC
CPUSS_FLASHC_CM4_CA_C_ECC
CPUSS_FLASHC_CM4_CA_NC_ECC
Flash controller CM4 cache correctable ECC violation.
See CPUSS_FLASHC_CM0_CA_C_ECC description.
Flash controller CM4 cache non-correctable ECC violation.
See CPUSS_FLASHC_CM0_CA_C_ECC description.
System memory controller 0 correctable ECC violation:
DATA0[31:0]: Violating address.
58
59
CPUSS_RAMC0_C_ECC
CPUSS_RAMC0_NC_ECC
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
System memory controller 0 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
Crypto memory correctable ECC violation.
DATA0[31:0]: Violating address.
64
65
70
CPUSS_CRYPTO_C_ECC
CPUSS_CRYPTO_NC_ECC
CPUSS_DW0_C_ECC
DATA1[6:0]: Syndrome of Least Significant 32-bit SRAM.
DATA1[14:8]: Syndrome of Most Significant 32-bit SRAM.
Crypto memory non-correctable ECC violation.
See CPUSS_CRYPTO_C_ECC description.
P-DMA0 memory correctable ECC violation:
DATA0[11:0]: Violating DW SRAM address
(word address, assuming byte addressable).
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
P-DMA0 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
71
72
73
CPUSS_DW0_NC_ECC
CPUSS_DW1_C_ECC
CPUSS_DW1_NC_ECC
P-DMA1 memory correctable ECC violation.
See CPUSS_DW0_C_ECC description.
P-DMA1 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
Flash code storage SRAM memory correctable ECC violation:
DATA0[15:0]: Address location in the eCT Flash SRAM.
DATA1[6:0]: Syndrome of 32-bit SRAM word.
74
75
CPUSS_FM_SRAM_C_ECC
CPUSS_FM_SRAM_NC_ECC
Flash code storage SRAM memory non-correctable ECC violation:
See CPUSS_FM_SRAMC_C_ECC description.
CAN0 message buffer correctable ECC violation:
DATA0[15:0]: Violating address.
80
CANFD_0_CAN_C_ECC
DATA0[22:16]: ECC violating data[38:32] from MRAM.
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA1[31:0]: ECC violating data[31:0] from MRAM.
Datasheet
71
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Faults
Table 22-1
Fault assignments (continued)
Fault
Source
Description
CAN0 message buffer non-correctable ECC violation:
DATA0[15:0]: Violating address.
DATA0[22:16]: ECC violating data[38:32] from MRAM (not for Address Error).
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA0[30]: Write access, only possible for Address Error
81
CANFD_0_CAN_NC_ECC
DATA0[31]: Address Error: a CAN channel did an MRAM access above MRAM_SIZE
DATA1[31:0]: ECC violating data[31:0] from MRAM (not for Address Error).
CAN1 message buffer correctable ECC violation.
See CANFD_0_CAN_C_ECC description.
82
83
CANFD_1_CAN_C_ECC
CAN1 message buffer non-correctable ECC violation.
See CANFD_0_CAN_NC_ECC description.
CANFD_1_CAN_NC_ECC
Consolidated fault output for clock supervisors. Multiple CSV can detect a violation at the
same time.
DATA0[15:0]: CLK_HF* root CSV violation flags.
DATA0[24]: CLK_REF CSV violation flag (reference clock for CLK_HF CSVs)
DATA0[25]: CLK_LF CSV violation flag
90
91
SRSS_FAULT_CSV
DATA0[26]: CLK_HVILO CSV violation flag
Consolidated fault output for supply supervisors. Multiple CSV can detect a violation at the
same time.
DATA0[0]: BOD on VDDA
DATA[1]: OVD on VDDA
DATA[16]: LVD/HVD #1
DATA0[17]: LVD/HVD #2
SRSS_FAULT_SSV
Fault output for MCWDT0 (all sub-counters) Multiple counters can detect a violation at the
same time.
DATA0[0]: MCWDT sub counter 0 LOWER_LIMIT
DATA0[1]: MCWDT sub counter 0 UPPER_LIMIT
DATA0[2]: MCWDT sub counter 1 LOWER_LIMIT
DATA0[3]: MCWDT sub counter 1 UPPER_LIMIT
92
93
SRSS_FAULT_MCWDT0
SRSS_FAULT_MCWDT1
Fault output for MCWDT1 (all sub-counters).
See SRSS_FAULT_MCWDT0 description.
Datasheet
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002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral protection unit fixed structure pairs
23
Peripheral protection unit fixed structure pairs
Protection pair is a pair PPU structures, a master and a slave structure. The master structure protects the slave
structure, and the slave structure protects resources such as peripheral registers, or the peripheral itself.
Table 23-1
PPU fixed structure pairs
Pair no.
PPU fixed structure pair
Address
Size
Description
Peripheral Interconnect main
Peripheral interconnect secure
Peripheral Group #0 main
Peripheral Group #1 main
Peripheral Group #2 main
Peripheral Group #3 main
Peripheral Group #5 main
Peripheral Group #6 main
Peripheral Group #9 main
Peripheral trigger multiplexer
Crypto main
PERI_MS_PPU_FX_PERI_MAIN
PERI_MS_PPU_FX_PERI_SECURE
0x40000000
0x40002000
0x40004010
0x40004030
0x40004050
0x40004060
0x400040A0
0x400040C0
0x40004120
0x40008000
0x40100000
0x40101000
0x40102000
0x40102100
0x40102120
0x40108000
0x40200000
0x40201000
0x40202000
0x40208000
0x4020A000
0x40210000
0x40210100
0x40210200
0x40210300
0x40220000
0x40220020
0x40220040
0x40220060
0x40220080
0x402200A0
0x402200C0
0x402200E0
0x40221000
0x40221020
0x40221040
0x40221060
0x40221080
0x402210A0
0x402210C0
0x402210E0
0x00002000
0x00000004
0x00000004
0x00000004
0x00000004
0x00000020
0x00000020
0x00000020
0x00000020
0x00008000
0x00000400
0x00000800
0x00000100
0x00000004
0x00000004
0x00002000
0x00000400
0x00001000
0x00000200
0x00000800
0x00000800
0x00000100
0x00000100
0x00000100
0x00000100
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0
1
PERI_MS_PPU_FX_PERI_GR0_GROUP
PERI_MS_PPU_FX_PERI_GR1_GROUP
PERI_MS_PPU_FX_PERI_GR2_GROUP
PERI_MS_PPU_FX_PERI_GR3_GROUP
PERI_MS_PPU_FX_PERI_GR5_GROUP
PERI_MS_PPU_FX_PERI_GR6_GROUP
PERI_MS_PPU_FX_PERI_GR9_GROUP
PERI_MS_PPU_FX_PERI_TR
2
3
4
5
6
7
8
9
PERI_MS_PPU_FX_CRYPTO_MAIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Note
PERI_MS_PPU_FX_CRYPTO_CRYPTO
PERI_MS_PPU_FX_CRYPTO_BOOT
Crypto MMIO (Memory Mapped I/O)
Crypto boot
PERI_MS_PPU_FX_CRYPTO_KEY0
Crypto Key #0
PERI_MS_PPU_FX_CRYPTO_KEY1
Crypto Key #1
PERI_MS_PPU_FX_CRYPTO_BUF
Crypto buffer
PERI_MS_PPU_FX_CPUSS_CM4
CM4 CPU core
PERI_MS_PPU_FX_CPUSS_CM0
CM0+ CPU core
PERI_MS_PPU_FX_CPUSS_BOOT[33]
PERI_MS_PPU_FX_CPUSS_CM0_INT
PERI_MS_PPU_FX_CPUSS_CM4_INT
PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT2_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT3_MAIN
PERI_MS_PPU_FX_IPC_STRUCT0_IPC
PERI_MS_PPU_FX_IPC_STRUCT1_IPC
PERI_MS_PPU_FX_IPC_STRUCT2_IPC
PERI_MS_PPU_FX_IPC_STRUCT3_IPC
PERI_MS_PPU_FX_IPC_STRUCT4_IPC
PERI_MS_PPU_FX_IPC_STRUCT5_IPC
PERI_MS_PPU_FX_IPC_STRUCT6_IPC
PERI_MS_PPU_FX_IPC_STRUCT7_IPC
PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR
CPUSS boot
CPUSS CM0+ interrupts
CPUSS CM4 interrupts
CPUSS Fault Structure #0 main
CPUSS Fault Structure #1 main
CPUSS Fault Structure #2 main
CPUSS Fault Structure #3 main
CPUSS IPC Structure #0
CPUSS IPC Structure #1
CPUSS IPC Structure #2
CPUSS IPC Structure #3
CPUSS IPC Structure #4
CPUSS IPC Structure #5
CPUSS IPC Structure #6
CPUSS IPC Structure #7
CPUSS IPC Interrupt Structure #0
CPUSS IPC Interrupt Structure #1
CPUSS IPC Interrupt Structure #2
CPUSS IPC Interrupt Structure #3
CPUSS IPC Interrupt Structure #4
CPUSS IPC Interrupt Structure #5
CPUSS IPC Interrupt Structure #6
CPUSS IPC Interrupt Structure #7
33.Fixed PPU is configured inside the Boot and user is not allowed to change the attributes of this PPU.
Datasheet
73
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair no.
PPU fixed structure pair
Address
Size
Description
Peripheral protection SMPU main
Peripheral protection MPU #0 main
Peripheral protection MPU #14 main
Peripheral protection MPU #15 main
Flash controller main
Flash controller command
Flash controller tests
Flash controller CM0+
Flash controller CM4
Flash controller Crypto
Flash controller P-DMA0
Flash controller P-DMA1
Flash controller M-DMA0
Flash management
PERI_MS_PPU_FX_PROT_SMPU_MAIN
PERI_MS_PPU_FX_PROT_MPU0_MAIN
0x40230000
0x40234000
0x40237800
0x40237C00
0x40240000
0x40240008
0x40240200
0x40240400
0x40240480
0x40240500
0x40240580
0x40240600
0x40240680
0x4024F000
0x4024F400
0x4024F500
0x40260000
0x40261000
0x40262000
0x40268000
0x40268100
0x40268080
0x40268180
0x4026C000
0x4026C040
0x40270000
0x40280000
0x40290000
0x40280100
0x40290100
0x40288000
0x40288040
0x40288080
0x402880C0
0x40288100
0x40288140
0x40288180
0x402881C0
0x40288200
0x40288240
0x40288280
0x402882C0
0x40288300
0x40288340
0x40288380
0x402883C0
0x40288400
0x00000040
0x00000004
0x00000004
0x00000400
0x00000008
0x00000004
0x00000100
0x00000080
0x00000080
0x00000004
0x00000004
0x00000004
0x00000004
0x00000080
0x00000008
0x00000004
0x00000400
0x00001000
0x00002000
0x00000080
0x00000080
0x00000040
0x00000040
0x00000020
0x00000020
0x00010000
0x00000100
0x00000100
0x00000080
0x00000080
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
PERI_MS_PPU_FX_PROT_MPU14_MAIN
PERI_MS_PPU_FX_PROT_MPU15_MAIN
PERI_MS_PPU_FX_FLASHC_MAIN
PERI_MS_PPU_FX_FLASHC_CMD
PERI_MS_PPU_FX_FLASHC_DFT
PERI_MS_PPU_FX_FLASHC_CM0
PERI_MS_PPU_FX_FLASHC_CM4
PERI_MS_PPU_FX_FLASHC_CRYPTO
PERI_MS_PPU_FX_FLASHC_DW0
PERI_MS_PPU_FX_FLASHC_DW1
PERI_MS_PPU_FX_FLASHC_DMAC
PERI_MS_PPU_FX_FLASHC_FlashMgmt[33]
PERI_MS_PPU_FX_FLASHC_MainSafety
PERI_MS_PPU_FX_FLASHC_WorkSafety
PERI_MS_PPU_FX_SRSS_GENERAL
PERI_MS_PPU_FX_SRSS_MAIN
Flash controller code-flash safety
Flash controller work-flash safety
SRSS General
SRSS main
PERI_MS_PPU_FX_SRSS_SECURE
SRSS secure
PERI_MS_PPU_FX_MCWDT0_CONFIG
PERI_MS_PPU_FX_MCWDT1_CONFIG
PERI_MS_PPU_FX_MCWDT0_MAIN
PERI_MS_PPU_FX_MCWDT1_MAIN
PERI_MS_PPU_FX_WDT_CONFIG
MCWDT #0 configuration
MCWDT #1 configuration
MCWDT #0 main
MCWDT #1 main
System WDT configuration
System WDT main
PERI_MS_PPU_FX_WDT_MAIN
PERI_MS_PPU_FX_BACKUP_BACKUP
PERI_MS_PPU_FX_DW0_DW
SRSS backup
P-DMA0 main
PERI_MS_PPU_FX_DW1_DW
P-DMA1 main
PERI_MS_PPU_FX_DW0_DW_CRC
P-DMA0 CRC
PERI_MS_PPU_FX_DW1_DW_CRC
P-DMA1 CRC
PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH
P-DMA0 Channel #0
P-DMA0 Channel #1
P-DMA0 Channel #2
P-DMA0 Channel #3
P-DMA0 Channel #4
P-DMA0 Channel #5
P-DMA0 Channel #6
P-DMA0 Channel #7
P-DMA0 Channel #8
P-DMA0 Channel #9
P-DMA0 Channel #10
P-DMA0 Channel #11
P-DMA0 Channel #12
P-DMA0 Channel #13
P-DMA0 Channel #14
P-DMA0 Channel #15
P-DMA0 Channel #16
Datasheet
74
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair no.
PPU fixed structure pair
Address
Size
Description
P-DMA0 Channel #17
PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT30_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT33_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT34_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT36_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT37_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT42_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT53_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT54_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT55_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT56_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT57_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT61_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT62_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT63_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT64_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT65_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT66_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT71_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT72_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT81_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT82_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT83_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT84_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT85_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT86_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT87_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT88_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH
0x40288440
0x40288480
0x402884C0
0x40288500
0x40288540
0x40288640
0x40288680
0x402886C0
0x40288700
0x40288740
0x40288780
0x40288840
0x40288880
0x40288900
0x40288940
0x40288A80
0x40288D40
0x40288D80
0x40288DC0
0x40288E00
0x40288E40
0x40288F40
0x40288F80
0x40288FC0
0x40289000
0x40289040
0x40289080
0x402891C0
0x40289200
0x40289440
0x40289480
0x402894C0
0x40289500
0x40289540
0x40289580
0x402895C0
0x40289600
0x40298000
0x40298040
0x40298080
0x402980C0
0x40298100
0x40298140
0x40298180
0x402981C0
0x40298200
0x40298240
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
88
P-DMA0 Channel #18
P-DMA0 Channel #19
P-DMA0 Channel #20
P-DMA0 Channel #21
P-DMA0 Channel #25
P-DMA0 Channel #26
P-DMA0 Channel #27
P-DMA0 Channel #28
P-DMA0 Channel #29
P-DMA0 Channel #30
P-DMA0 Channel #33
P-DMA0 Channel #34
P-DMA0 Channel #36
P-DMA0 Channel #37
P-DMA0 Channel #42
P-DMA0 Channel #53
P-DMA0 Channel #54
P-DMA0 Channel #55
P-DMA0 Channel #56
P-DMA0 Channel #57
P-DMA0 Channel #61
P-DMA0 Channel #62
P-DMA0 Channel #63
P-DMA0 Channel #64
P-DMA0 Channel #65
P-DMA0 Channel #66
P-DMA0 Channel #71
P-DMA0 Channel #72
P-DMA0 Channel #81
P-DMA0 Channel #82
P-DMA0 Channel #83
P-DMA0 Channel #84
P-DMA0 Channel #85
P-DMA0 Channel #86
P-DMA0 Channel #87
P-DMA0 Channel #88
P-DMA1 Channel #0
P-DMA1 Channel #1
P-DMA1 Channel #2
P-DMA1 Channel #3
P-DMA1 Channel #4
P-DMA1 Channel #5
P-DMA1 Channel #6
P-DMA1 Channel #7
P-DMA1 Channel #8
P-DMA1 Channel #9
89
90
91
92
96
97
98
99
100
101
104
105
107
108
113
124
125
126
127
128
132
133
134
135
136
137
142
143
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
Datasheet
75
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair no.
PPU fixed structure pair
Address
Size
Description
P-DMA1 Channel #10
PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH
PERI_MS_PPU_FX_DMAC_TOP
0x40298280
0x402982C0
0x40298380
0x402983C0
0x40298400
0x40298440
0x40298480
0x402984C0
0x40298580
0x402985C0
0x40298600
0x40298640
0x40298680
0x402986C0
0x40298700
0x40298740
0x402A0000
0x402A1000
0x402A1100
0x402C0000
0x402C0800
0x402F0000
0x40300000
0x40300020
0x40300030
0x40300050
0x40300060
0x40300070
0x40300080
0x403000B0
0x403000C0
0x403000D0
0x403000E0
0x40300110
0x40300120
0x40300130
0x40300150
0x40300160
0x40300170
0x40302000
0x40302200
0x40302240
0x40310000
0x40310100
0x40310180
0x40310280
0x40310300
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000010
0x00000100
0x00000100
0x00000200
0x00000200
0x00001000
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000010
0x00000010
0x00000004
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
170
171
174
175
176
177
178
179
182
183
184
185
186
187
188
189
193
194
195
198
199
200
201
203
204
206
207
208
209
212
213
214
215
218
219
220
222
223
224
225
226
227
228
230
231
233
234
P-DMA1 Channel #11
P-DMA1 Channel #14
P-DMA1 Channel #15
P-DMA1 Channel #16
P-DMA1 Channel #17
P-DMA1 Channel #18
P-DMA1 Channel #19
P-DMA1 Channel #22
P-DMA1 Channel #23
P-DMA1 Channel #24
P-DMA1 Channel #25
P-DMA1 Channel #26
P-DMA1 Channel #27
P-DMA1 Channel #28
P-DMA1 Channel #29
M-DMA0 main
PERI_MS_PPU_FX_DMAC_CH0_CH
M-DMA0 Channel #0
M-DMA0 Channel #1
EFUSE control
PERI_MS_PPU_FX_DMAC_CH1_CH
PERI_MS_PPU_FX_EFUSE_CTL
PERI_MS_PPU_FX_EFUSE_DATA
EFUSE data
PERI_MS_PPU_FX_BIST
Built-in self test
PERI_MS_PPU_FX_HSIOM_PRT0_PRT
PERI_MS_PPU_FX_HSIOM_PRT2_PRT
PERI_MS_PPU_FX_HSIOM_PRT3_PRT
PERI_MS_PPU_FX_HSIOM_PRT5_PRT
PERI_MS_PPU_FX_HSIOM_PRT6_PRT
PERI_MS_PPU_FX_HSIOM_PRT7_PRT
PERI_MS_PPU_FX_HSIOM_PRT8_PRT
PERI_MS_PPU_FX_HSIOM_PRT11_PRT
PERI_MS_PPU_FX_HSIOM_PRT12_PRT
PERI_MS_PPU_FX_HSIOM_PRT13_PRT
PERI_MS_PPU_FX_HSIOM_PRT14_PRT
PERI_MS_PPU_FX_HSIOM_PRT17_PRT
PERI_MS_PPU_FX_HSIOM_PRT18_PRT
PERI_MS_PPU_FX_HSIOM_PRT19_PRT
PERI_MS_PPU_FX_HSIOM_PRT21_PRT
PERI_MS_PPU_FX_HSIOM_PRT22_PRT
PERI_MS_PPU_FX_HSIOM_PRT23_PRT
PERI_MS_PPU_FX_HSIOM_AMUX
HSIOm Port #0
HSIOm Port #2
HSIOm Port #3
HSIOm Port #5
HSIOm Port #6
HSIOm Port #7
HSIOm Port #8
HSIOm Port #11
HSIOm Port #12
HSIOm Port #13
HSIOm Port #14
HSIOm Port #17
HSIOm Port #18
HSIOm Port #19
HSIOm Port #21
HSIOm Port #22
HSIOm Port #23
HSIOm Analog multiplexer
HSIOm monitor
PERI_MS_PPU_FX_HSIOM_MON
PERI_MS_PPU_FX_HSIOM_ALTJTAG
PERI_MS_PPU_FX_GPIO_PRT0_PRT
PERI_MS_PPU_FX_GPIO_PRT2_PRT
PERI_MS_PPU_FX_GPIO_PRT3_PRT
PERI_MS_PPU_FX_GPIO_PRT5_PRT
PERI_MS_PPU_FX_GPIO_PRT6_PRT
HSIOm Alternate JTAG
GPIO_ENH Port #0
GPIO_STD Port #2
GPIO_STD Port #3
GPIO_STD Port #5
GPIO_STD Port #6
Datasheet
76
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair no.
PPU fixed structure pair
Address
Size
Description
GPIO_STD Port #7
PERI_MS_PPU_FX_GPIO_PRT7_PRT
PERI_MS_PPU_FX_GPIO_PRT8_PRT
0x40310380
0x40310400
0x40310580
0x40310600
0x40310680
0x40310700
0x40310880
0x40310900
0x40310980
0x40310A80
0x40310B00
0x40310B80
0x40310040
0x40310140
0x403101C0
0x403102C0
0x40310340
0x403103C0
0x40310440
0x403105C0
0x40310640
0x403106C0
0x40310740
0x403108C0
0x40310940
0x403109C0
0x40310AC0
0x40310B40
0x40310BC0
0x40314000
0x40315000
0x40320C00
0x40320D00
0x40320E00
0x40380000
0x40380080
0x40380100
0x40380200
0x40380280
0x40380300
0x40380380
0x40380480
0x40380500
0x40380580
0x40380600
0x40380680
0x40380700
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000040
0x00000008
0x00000100
0x00000100
0x00000100
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
235
236
239
240
241
242
245
246
247
249
250
251
252
254
255
257
258
259
260
263
264
265
266
269
270
271
273
274
275
276
277
278
279
280
283
284
285
287
288
289
290
292
293
294
295
296
297
GPIO_STD Port #8
PERI_MS_PPU_FX_GPIO_PRT11_PRT
PERI_MS_PPU_FX_GPIO_PRT12_PRT
PERI_MS_PPU_FX_GPIO_PRT13_PRT
PERI_MS_PPU_FX_GPIO_PRT14_PRT
PERI_MS_PPU_FX_GPIO_PRT17_PRT
PERI_MS_PPU_FX_GPIO_PRT18_PRT
PERI_MS_PPU_FX_GPIO_PRT19_PRT
PERI_MS_PPU_FX_GPIO_PRT21_PRT
PERI_MS_PPU_FX_GPIO_PRT22_PRT
PERI_MS_PPU_FX_GPIO_PRT23_PRT
PERI_MS_PPU_FX_GPIO_PRT0_CFG
GPIO_STD Port #11
GPIO_STD Port #12
GPIO_STD Port #13
GPIO_STD Port #14
GPIO_STD Port #17
GPIO_STD Port #18
GPIO_STD Port #19
GPIO_STD Port #21
GPIO_STD Port #22
GPIO_STD Port #23
GPIO_ENH Port #0 configuration
GPIO_STD Port #2 configuration
GPIO_STD Port #3 configuration
GPIO_STD Port #5 configuration
GPIO_STD Port #6 configuration
GPIO_STD Port #7 configuration
GPIO_STD Port #8 configuration
GPIO_STD Port #11 configuration
GPIO_STD Port #12 configuration
GPIO_STD Port #13 configuration
GPIO_STD Port #14 configuration
GPIO_STD Port #17 configuration
GPIO_STD Port #18 configuration
GPIO_STD Port #19 configuration
GPIO_STD Port #21 configuration
GPIO_STD Port #22 configuration
GPIO_STD Port #23 configuration
GPIO main
PERI_MS_PPU_FX_GPIO_PRT2_CFG
PERI_MS_PPU_FX_GPIO_PRT3_CFG
PERI_MS_PPU_FX_GPIO_PRT5_CFG
PERI_MS_PPU_FX_GPIO_PRT6_CFG
PERI_MS_PPU_FX_GPIO_PRT7_CFG
PERI_MS_PPU_FX_GPIO_PRT8_CFG
PERI_MS_PPU_FX_GPIO_PRT11_CFG
PERI_MS_PPU_FX_GPIO_PRT12_CFG
PERI_MS_PPU_FX_GPIO_PRT13_CFG
PERI_MS_PPU_FX_GPIO_PRT14_CFG
PERI_MS_PPU_FX_GPIO_PRT17_CFG
PERI_MS_PPU_FX_GPIO_PRT18_CFG
PERI_MS_PPU_FX_GPIO_PRT19_CFG
PERI_MS_PPU_FX_GPIO_PRT21_CFG
PERI_MS_PPU_FX_GPIO_PRT22_CFG
PERI_MS_PPU_FX_GPIO_PRT23_CFG
PERI_MS_PPU_FX_GPIO_GPIO
PERI_MS_PPU_FX_GPIO_TEST
GPIO test
PERI_MS_PPU_FX_SMARTIO_PRT12_PRT
PERI_MS_PPU_FX_SMARTIO_PRT13_PRT
PERI_MS_PPU_FX_SMARTIO_PRT14_PRT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT4_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT5_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT6_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT7_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT9_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT10_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT11_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT12_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT13_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT14_CNT
SMART I/O #12
SMART I/O #13
SMART I/O #14
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #0, Counter #4
TCPWM0 Group #0, Counter #5
TCPWM0 Group #0, Counter #6
TCPWM0 Group #0, Counter #7
TCPWM0 Group #0, Counter #9
TCPWM0 Group #0, Counter #10
TCPWM0 Group #0, Counter #11
TCPWM0 Group #0, Counter #12
TCPWM0 Group #0, Counter #13
TCPWM0 Group #0, Counter #14
Datasheet
77
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair no.
PPU fixed structure pair
Address
Size
Description
TCPWM0 Group #0, Counter #15
TCPWM0 Group #0, Counter #16
TCPWM0 Group #0, Counter #17
TCPWM0 Group #0, Counter #18
TCPWM0 Group #0, Counter #19
TCPWM0 Group #0, Counter #20
TCPWM0 Group #0, Counter #21
TCPWM0 Group #0, Counter #22
TCPWM0 Group #0, Counter #23
TCPWM0 Group #0, Counter #24
TCPWM0 Group #0, Counter #25
TCPWM0 Group #0, Counter #26
TCPWM0 Group #0, Counter #33
TCPWM0 Group #0, Counter #34
TCPWM0 Group #0, Counter #36
TCPWM0 Group #0, Counter #37
TCPWM0 Group #0, Counter #38
TCPWM0 Group #0, Counter #39
TCPWM0 Group #0, Counter #40
TCPWM0 Group #0, Counter #41
TCPWM0 Group #0, Counter #42
TCPWM0 Group #0, Counter #44
TCPWM0 Group #0, Counter #45
TCPWM0 Group #0, Counter #46
TCPWM0 Group #0, Counter #47
TCPWM0 Group #0, Counter #48
TCPWM0 Group #0, Counter #49
TCPWM0 Group #0, Counter #50
TCPWM0 Group #0, Counter #51
TCPWM0 Group #0, Counter #52
TCPWM0 Group #0, Counter #53
TCPWM0 Group #0, Counter #54
TCPWM0 Group #0, Counter #55
TCPWM0 Group #1, Counter #0
TCPWM0 Group #1, Counter #1
TCPWM0 Group #1, Counter #2
TCPWM0 Group #1, Counter #4
TCPWM0 Group #2, Counter #0
TCPWM0 Group #2, Counter #2
Event generator #0
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT15_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT16_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT17_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT18_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT19_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT20_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT21_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT22_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT23_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT24_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT25_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT26_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT33_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT34_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT36_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT37_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT38_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT39_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT40_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT41_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT42_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT44_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT45_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT46_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT47_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT48_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT49_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT50_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT51_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT52_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT53_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT54_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT55_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT2_CNT
PERI_MS_PPU_FX_EVTGEN0
0x40380780
0x40380800
0x40380880
0x40380900
0x40380980
0x40380A00
0x40380A80
0x40380B00
0x40380B80
0x40380C00
0x40380C80
0x40380D00
0x40381080
0x40381100
0x40381200
0x40381280
0x40381300
0x40381380
0x40381400
0x40381480
0x40381500
0x40381600
0x40381680
0x40381700
0x40381780
0x40381800
0x40381880
0x40381900
0x40381980
0x40381A00
0x40381A80
0x40381B00
0x40381B80
0x40388000
0x40388080
0x40388100
0x40388200
0x40390000
0x40390100
0x403F0000
0x40500000
0x40508000
0x40508100
0x40508200
0x40508300
0x40508400
0x40520000
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00001000
0x00000008
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00000200
298
299
300
301
302
303
304
305
306
307
308
309
316
317
319
320
321
322
323
324
325
327
328
329
330
331
332
333
334
335
336
337
338
346
347
348
350
358
360
362
363
364
365
366
367
368
372
PERI_MS_PPU_FX_LIN0_MAIN
LIN0, main
PERI_MS_PPU_FX_LIN0_CH0_CH
LIN0, Channel #0
PERI_MS_PPU_FX_LIN0_CH1_CH
LIN0, Channel #1
PERI_MS_PPU_FX_LIN0_CH2_CH
LIN0, Channel #2
PERI_MS_PPU_FX_LIN0_CH3_CH
LIN0, Channel #3
PERI_MS_PPU_FX_LIN0_CH4_CH
LIN0, Channel #4
PERI_MS_PPU_FX_CANFD0_CH0_CH
CAN0, Channel #0
Datasheet
78
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair no.
PPU fixed structure pair
Address
Size
Description
CAN0, Channel #1
PERI_MS_PPU_FX_CANFD0_CH1_CH
PERI_MS_PPU_FX_CANFD1_CH0_CH
0x40520200
0x40540000
0x40540200
0x40521000
0x40541000
0x40530000
0x40550000
0x40600000
0x40610000
0x40630000
0x40640000
0x40650000
0x40670000
0x40900000
0x40901000
0x40902000
0x40900800
0x40900840
0x40900880
0x409008C0
0x40900900
0x40900940
0x40900A00
0x40900A40
0x40900AC0
0x40900B00
0x40900C40
0x40901900
0x40901940
0x40901980
0x409019C0
0x40901A00
0x40901B00
0x40901B40
0x40901B80
0x40901BC0
0x40901C00
0x40901C40
0x40901D80
0x40901DC0
0x40902800
0x40902840
0x40902880
0x409028C0
0x40902900
0x40902940
0x40902980
0x00000200
0x00000200
0x00000200
0x00000100
0x00000100
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00000400
0x00000400
0x00000400
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
373
375
376
378
379
380
381
382
383
385
386
387
389
390
391
392
393
394
395
396
397
398
401
402
404
405
410
421
422
423
424
425
429
430
431
432
433
434
439
440
449
450
451
452
453
454
455
CAN1, Channel #0
CAN1, Channel #1
CAN0 main
PERI_MS_PPU_FX_CANFD1_CH1_CH
PERI_MS_PPU_FX_CANFD0_MAIN
PERI_MS_PPU_FX_CANFD1_MAIN
CAN1 main
PERI_MS_PPU_FX_CANFD0_BUF
CAN0 buffer
PERI_MS_PPU_FX_CANFD1_BUF
CAN1 buffer
PERI_MS_PPU_FX_SCB0
SCB0
PERI_MS_PPU_FX_SCB1
SCB1
PERI_MS_PPU_FX_SCB3
SCB3
PERI_MS_PPU_FX_SCB4
SCB4
PERI_MS_PPU_FX_SCB5
SCB5
PERI_MS_PPU_FX_SCB7
SCB7
PERI_MS_PPU_FX_PASS0_SAR0_SAR
PERI_MS_PPU_FX_PASS0_SAR1_SAR
PERI_MS_PPU_FX_PASS0_SAR2_SAR
PERI_MS_PPU_FX_PASS0_SAR0_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH6_CH
PASS SAR0
PASS SAR1
PASS SAR2
SAR0, Channel #0
SAR0, Channel #1
SAR0, Channel #2
SAR0, Channel #3
SAR0, Channel #4
SAR0, Channel #5
SAR0, Channel #8
SAR0, Channel #9
SAR0, Channel #11
SAR0, Channel #12
SAR0, Channel #17
SAR1, Channel #4
SAR1, Channel #5
SAR1, Channel #6
SAR1, Channel #7
SAR1, Channel #8
SAR1, Channel #12
SAR1, Channel #13
SAR1, Channel #14
SAR1, Channel #15
SAR1, Channel #16
SAR1, Channel #17
SAR1, Channel #22
SAR1, Channel #23
SAR2, Channel #0
SAR2, Channel #1
SAR2, Channel #2
SAR2, Channel #3
SAR2, Channel #4
SAR2, Channel #5
SAR2, Channel #6
Datasheet
79
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair no.
PPU fixed structure pair
Address
Size
Description
SAR2, Channel #7
PASS0 SAR main
PERI_MS_PPU_FX_PASS0_SAR2_CH7_CH
PERI_MS_PPU_FX_PASS0_TOP
0x409029C0
0x409F0000
0x00000040
0x00001000
456
457
Datasheet
80
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Bus masters
24
Bus masters
The Arbiter (part of flash controller) performs priority-based arbitration based on the master identifier. Each bus
master has a dedicated 4-bit master identifier. This master identifier is used for bus arbitration and IPC function-
ality.
Table 24-1
ID No.
Bus masters for access and protection control
Master ID
Description
Master ID for CM0+
Master ID for Crypto
0
1
2
3
4
CPUSS_MS_ID_CM0
CPUSS_MS_ID_CRYPTO
CPUSS_MS_ID_DW0
CPUSS_MS_ID_DW1
CPUSS_MS_ID_DMAC
Master ID for P-DMA 0
Master ID for P-DMA 1
Master ID for M-DMA0
Master ID for CM4
14 CPUSS_MS_ID_CM4
15 CPUSS_MS_ID_TC
Master ID for DAP Tap Controller
Datasheet
81
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Miscellaneous configuration
25
Miscellaneous configuration
Table 25-1
Miscellaneous configuration for CYT2B6 devices
Sl.
Number/
Configuration
Description
No.
instances
Number of clock paths. One for each of FLL,
PLL, Direct and CSV
0
SRSS_NUM_CLKPATH
SRSS_NUM_HFROOT
4
Number of CLK_HFs present
1
2
3
4
5
6
7
8
3
8
Number of protection contexts
PERI_PC_NR
Number of programmable clocks (outputs)
Number of divide-by-8 clock dividers
Number of divide-by-16 clock dividers
Number of divide-by-24.5 clock dividers
Number of MPU regions in CM0+
Number of MPU regions in CM4
PERI_CLOCK_NR
PERI_DIV_8_NR
110
32
16
8
PERI_DIV_16_NR
PERI_DIV_24_5_NR
CPUSS_CM0P_MPU_NR
CPUSS_CM4_MPU_NR
8
8
Number of 32-bit words in the IP internal
memory buffer (to allow for a 256-B, 512-B,
1-KB, 2-KB, 4-KB, 8-KB, 16-KB, and 32-KB
memory buffer)
9
CPUSS_CRYPTO_BUFF_SIZE
2048
4
Number of fault structures
10 CPUSS_FAULT_FAULT_NR
11 CPUSS_IPC_IPC_NR
Number of IPC structures
0 - Reserved for CM0+ access
1 - Reserved for CM4 access
2 - Reserved for DAP access
Remaining for user purposes
8
Number of EZ memory bytes. This memory is
used in EZ mode, CMD_RESP mode and FIFO
mode.
12 SCB0_EZ_DATA_NR
256
Note: Only SCB0 supports EZ mode
Number of SMPU protection structures
13 CPUSS_PROT_SMPU_STRUCT_NR
14 TCPWM_TR_ONE_CNT_NR
16
3
Number of input triggers per counter, routed
to one counter
Number of input triggers routed to all
counters, based on the pin package
15 TCPWM_TR_ALL_CNT_NR
27
Number of TCPWM0 counter groups
16 TCPWM_GRP_NR
3
Number of counters per TCPWM0 Group #0
17 TCPWM_GRP_NR0_GRP_GRP_CNT_NR
46
Counter width in number of bits per TCPWM0
Group #0
TCPWM_GRP_NR0_CNT_GRP_CNT_WIDT
18
H
16
4
Number of counters per TCPWM0 Group #1
19 TCPWM_GRP_NR1_GRP_GRP_CNT_NR
Counter width in number of bits per TCPWM0
Group #1
TCPWM_GRP_NR1_CNT_GRP_CNT_WIDT
20
H
16
2
Number of counters per TCPWM0 Group #2
21 TCPWM_GRP_NR2_GRP_GRP_CNT_NR
Counter width in number of bits per TCPWM0
Group #2
TCPWM_GRP_NR2_CNT_GRP_CNT_WIDT
22
H
32
Message RAM size in KB shared by all the
channels
CANFD0_MRAM_SIZE / CANFD1_M-
23
24
11
RAM_SIZE
Number of Event Generator comparator
structures
24 EVTGEN_COMP_STRUCT_NR
Datasheet
82
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Development support
26
Development support
CYT2B6 has a rich set of documentation, programming tools, and online resources to assist during the devel-
opment process. Visit www.infineon.com to find out more.
26.1
Documentation
A suite of documentation supports CYT2B6 to ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
26.1.1
Software user guide
A step-by-step guide for using the sample driver library along with third-party IDEs such as IAR EWARM and GHS
Multi.
26.1.2
Technical reference manual
The Technical reference manual (TRM) contains all the technical detail needed to use a CYT2B6 device, including
a complete description of all registers. The TRM is available in the documentation section at www.infineon.com.
26.2
Tools
CYT2B6 is supported on third-party development tool ecosystems such as IAR and GHS. CYT2B6 is also supported
by Infineon programming utilities for programming, erasing, or reading using the MiniProg4 or Segger J-link.
More details are available in the documentation section at www.infineon.com.
Datasheet
83
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27
Electrical specifications
27.1
Absolute maximum ratings
Use of this device under conditions outside the min and max limits listed in Table 27-1 may cause permanent
damage to the device. Exposure to conditions within the limits of Table 27-1 but beyond those of normal
operation for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C
in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When operated under condi-
tions within the limits of Table 27-1 but beyond those of normal operation, the device may not operate to speci-
fication.
Power considerations
The average chip-junction temperature, TJ, in °C, may be calculated using Equation 1:
TJ = TA + PD JA
Equation. 1
Where:
TA is the ambient temperature in °C.
JA is the package junction-to-ambient thermal resistance, in °C/W.
θ
PD is the sum of PINT and PIO (PD = PINT + PIO).
PINT is the chip internal power. (PINT = VDDD × IDD + VDDA × IA)
PIO represents the power dissipation on input and output pins; user determined.
For most applications, PIO < PINT and may be neglected.
On the other hand, PIO may be significant if the device is configured to continuously drive external modules
and/or memories.
Datasheet
84
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-1
Absolute maximum ratings
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/conditions
For ports 0, 2, 3, 5, 17, 18,
19, 21, 22, 23
SID10_5
VDDD_ABS_5
VDDD power supply voltage[34]
VSSD – 0.3
–
VSSD + 6.0
V
V
DDIO_1 ≥ VDDD
SID10B_5 VDDIO_1_ABS_5
VDDIO_1 power supply voltage[34]
VSSD – 0.3
–
VSSD + 6.0
V
For ports 6, 7, 8[35]
For ports 11, 12, 13, 14
VDDIO_2 = VDDA
SID10C1
SID11
VDDIO_2_ABS_5
VDDA_ABS
VREFH_ABS
VREFL_ABS
VDDIO_2 power supply voltage[34]
VDDA analog power supply voltage[34]
Analog reference voltage, HIGH [34]
Analog reference voltage, LOW[34]
VSSD – 0.3
VSSA – 0.3
VSSA – 0.3
VSSA – 0.3
–
–
–
–
VSSD + 6.0
VSSA + 6.0
VSSA + 6.0
VSSA + 0.3
V
V
V
V
SID12
VREFH VDDA + 0.3 V
SID12A
For ports 0, 2, 3, 5, 17, 18,
19, 21, 22, 23
For ports 6, 7, 8[35]
SID15A_5
SID15B_5
V
V
I0_ABS0_5
I1_ABS1_5
Input voltage[34]
VSSD – 0.5
–
VDDD + 0.5
V
Input voltage[34]
Input voltage[34]
Analog input voltage[34]
VSSD – 0.5
VSSD – 0.5
VSSA – 0.3
–
–
–
VDDIO_1 + 0.5
VDDIO_2 + 0.5
VDDA + 0.3
V
V
V
SID15C_5 VI2_ABS2_5
For ports 11, 12, 13, 14,
SID16
VIA_ABS
For ports 0, 2, 3, 5, 17, 18,
19, 21, 22, 23
For ports 6, 7, 8[35]
SID17A_5
V
O0_ABS0_5
O1_ABS1_5
Output voltage[34]
VSSD – 0.3
–
VDDD + 0.3
SID17B_5
V
Output voltage[34]
Output voltage[34]
Maximum clamp current [36, 37, 38]
VSSD – 0.3
VSSD – 0.3
–5
–
–
–
VDDIO_1 + 0.3
VDDIO_2 + 0.3
5
V
V
SID17C_5 VO2_ABS2_5
For ports 11, 12, 13, 14
SID18
ICLAMP_ABS
mA
Maximum positive clamp current per I/O
supply pin. Limit applies to I/O supply pin
closest to the B+ injected current[39]
+B injected DC currents
ICLAMP_SUP-
PLY_POS_ABS
SID18A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
10
10
50
50
6
mA are not allowed for Ports
11 and 21.
Maximum negative clamp current per I/O
ground pin. Limit applies to I/O supply pin
closest to the B+ injected current[39]
+B injected DC currents
mA are not allowed for Ports
11 and 21.
ICLAMP_SUP-
PLY_NEG_ABS
SID18B
SID18C
SID18D
SID20A
SID20B
SID20C
SID21A
SID21B
Maximum positive clamp current per I/O
supply, if not limited by the per supply pin
(based on SID18A).
ICLAMP_TO-
TAL_POS_ABS
mA
mA
Maximum negative clamp current per I/O
ground, if not limited by the per supply pin
(based on SID18B).
ICLAMP_TO-
TAL_NEG_ABS
For GPIO_STD,
mA configured for
drive_sel<1:0>= 0b0X
IOL1A_ABS
IOL1B_ABS
IOL1C_ABS
IOL2A_ABS
IOL2B_ABS
IOL2C_ABS
LOW-level maximum output current [41]
LOW-level maximum output current [41]
LOW-level maximum output current [41]
LOW-level maximum output current [41]
LOW-level maximum output current [41]
LOW-level maximum output current [41]
For GPIO_STD,
mA configured for
drive_sel<1:0>= 0b10
2
For GPIO_STD,
mA configured for
drive_sel<1:0>= 0b11
1
For GPIO_ENH,
mA configured for
drive_sel<1:0>= 0b0X
6
For GPIO_ENH,
mA configured for
drive_sel<1:0>= 0b10
2
For GPIO_ENH,
mA configured for
drive_sel<1:0>= 0b11
SID21C
1
Notes
34.These parameters are based on the condition that VSSD = VSSA = 0.0 V.
35.The I/Os in VDDIO_1 domain are referred to the VDDD domain in 64-LQFP package.
36.A current-limiting resistor must be provided such that the current at the I/O pin does not exceed rated values at any time, including
during power transients. Refer to Figure 27-1 for more information on the recommended circuit.
37.VDDIO and VDDD must be sufficiently loaded or protected to prevent them from being pulled out of the recommended operating range
by the clamp current.
38.When the conditions of [36], [37], and SID18A/B/C/D are met, |ICLAMP_ABS| supersedes VIA_ABS and VI_ABS
.
39.The definition of “closer” depends on the package. In LQFP packaging, “closest” is determined by counting pins. For example, in a
100-LQFP package, P5.2 (pin 16) is closer to the VDDD on pin 12 than on pin 24. Ports 11 and 21should not be used for injection currents.
The impact of injection currents is only defined for GPIO_STD/GPIO_ENH type I/Os.
40.The maximum output current is the peak current flowing through any one I/O.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-1
Absolute maximum ratings (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/conditions
SID26A
∑IOL_ABS_GPIO
LOW-level total output current [42]
–
–
50
mA
For GPIO_STD,
SID27A
IOH1A_ABS
IOH1B_ABS
IOH1C_ABS
IOH2A_ABS
IOH2B_ABS
IOH2C_ABS
HIGH-level maximum output current [41]
HIGH-level maximum output current [41]
HIGH-level maximum output current [41]
HIGH-level maximum output current [41]
HIGH-level maximum output current [41]
HIGH-level maximum output current [41]
–
–
–
–
–
–
–
–
–
–
–
–
–5
–2
–1
–5
–2
–1
mA configured for
drive_sel<1:0>= 0b0X
For GPIO_STD,
SID27B
SID27C
SID28A
SID28B
SID28C
mA configured for
drive_sel<1:0>= 0b10
For GPIO_STD,
mA configured for
drive_sel<1:0>= 0b11
For GPIO_ENH,
mA configured for
drive_sel<1:0>= 0b0X
For GPIO_ENH,
mA configured for
drive_sel<1:0>= 0b10
For GPIO_ENH,
mA configured for
drive_sel<1:0 ≥ 0b11
SID33A
SID34
∑IOH_ABS_GPIO
HIGH-level total output current [42]
Power dissipation
–
–
–
–
–50
mA
TJ should not exceed
150 °C
PD
1000
mW
SID35
SID36
SID37
SID38
TA
Ambient temperature
–40
–40
–55
–40
–
–
–
–
105
125
150
150
°C
°C
°C
°C
For S-grade devices
For E-grade devices
TA
Ambient temperature
TSTG
TJ
Storage temperature
Operating Junction temperature
Electrostatic discharge human body
model
SID39A
SID39B1
SID39B2
SID39C
VESD_HBM
VESD_CDM1
VESD_CDM2
ILU
2000
750
–
–
–
–
–
–
V
V
Electrostatic discharge charged device
model for corner pins
Electrostatic discharge charged device
model for all other pins
500
–
V
The maximum pin current the device can
tolerate before triggering a latch-up
–100
100
mA
Notes
41.The maximum output current is the peak current flowing through any one I/O.
42.The total output current is the maximum current flowing through all I/Os (GPIO_STD, and GPIO_ENH).
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
VDDD or VDDIO
Current
limiting
resistor
Protection
Diode
+B input
Protection
Diode
VSS
Figure 27-1
Example of a recommended circuit[43]
WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current, or tempera-
ture) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Note
43.+B is the positive battery voltage around 45 V.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.2
Device-level specifications
Table 27-2
Recommended operating conditions
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
conditions
Recommended operating conditions
SID40
VDDD, VDDA
,
Power supply voltage[44]
2.7[45]
–
5.5[46]
V
VDDIO_1
VDDIO_2
,
,
SID40A
SID41
VDDIO_1_EFP Power supply voltage for
3
–
–
5.5
11
V
eFuse programming[47]
Smoothing capacitor[48, 49]
3.76
µF
C
S1
VCCD
VREF_L
CS1
VSS
VSSA
Single-point connection
between analog and
digital grounds
Figure 27-2
Smoothing capacitor
Smoothing capacitor should be placed as close as possible to the VCCD pin.
Notes
44.VDDD, VDDIO_1, VDDIO_2, and VDDA do not have any sequencing limitation and can establish in any order. These supplies (except for VDDA
and VDDIO_2) are independent in voltage level. See 12-Bit SAR ADC DC Specifications when using ADC units.
45.3.0 V ±10% is supported with a lower BOD setting option for VDDD and VDDA. This setting provides robust protection for internal timing
but BOD reset occurs at a voltage below the specified operating conditions. A higher BOD setting option is available (consistent with
down to 3.0 V) and guarantees that all operating conditions are met.
46.5.0 V ±10% is supported with a higher OVD setting option for VDDD and VDDA. This setting provides robust protection for internal and
interface timing, but OVD reset occurs at a voltage above the specified operating conditions. A lower OVD setting option is available
(consistent with up to 5.0 V) and guarantees that all operating conditions are met. Voltage overshoot to a higher OVD setting range
for VDDD and VDDA is permissible, provided the duration is less than 2 hours cumulated. Note that during overshoot voltage condition
electrical parameters are not guaranteed.
47.eFuse programming must be executed with the part in a “quiet” state, with minimal activity (preferably only JTAG or a single LIN/CAN
channel on VDDD domain, no activity on VDDIO_1).
48.Smoothing capacitor, CS1 is required per chip (not per VCCD pin). The VCCD pins must be connected together to ensure a low-impedance
connection (see the requirement in Figure 27-2).
49.Capacitors used for power supply decoupling or filtering are operated under a continuous DC-bias. Many capacitors used with DC
power across them provide less than their target capacitance, and their capacitance is not constant across their working voltage
range. When selecting capacitors for use with this device, ensure that the selected components provide the required capacitance
under the specific operating conditions of temperature and voltage used in your design. While the temperature coefficient is normally
found within a parts catalog (such as, X7R, C0G, Y5V), the matching voltage coefficient may only be available on the component
datasheet or direct from the manufacturer. Use of components that do not provide the required capacitance under the actual oper-
ating conditions may cause the device to operate to less than datasheet specifications.
Datasheet
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.3
DC specifications
Table 27-3
DC specifications, CPU current and transition time specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter Description Min Typ Max Units Details/conditions
SID49C1A IDD1_CM04_8_1 LP Active mode (CM4
–
4
9
mA CM0+ and CM4 clocked at 8 MHz
with IMO. All peripherals are
disabled. No IO toggling.
and CM0+ at 8 MHz, all
peripherals are
disabled)
A
TYP: TA = 25 °C, VDDD = 5.0 V,
process typ (TT), CM0+ and CM4
executing Dhrystone from flash
with cache enabled
MAX: TA = 25 °C, VDDD = 5.5 V,
process worst (FF), CM0+ and
CM4 executing Dhrystone from
flash with cache enabled.
SID49CB IDD1_CM04_8B LP Active mode (CM4
and CM0+ at 8 MHz, all
peripherals are
–
5
49
mA CM0+ and CM4 clocked at 8 MHz
with IMO.
All peripherals are enabled. No
IO toggling.
enabled)
M-DMA transferring data from
code + work flash, P-DMA chains
with maximum trigger activity.
TYP: TA = 25 °C, VDDD = 5.0 V,
process typ (TT), CM0+ and CM4
executing Dhrystone from flash
with cache enabled
MAX: TA = 125 °C, VDDD = 5.5 V,
process worst (FF), CM0+ and
CM4 executing max_power.c
from Arm® with cache enabled.
SID49E2 IDD1_F80_512 Active mode (CM4 at
80 MHz, CM0+ at 80
–
29
85
mA PLL enabled at 80 MHz with ECO
reference.
MHz, all peripherals
All peripherals are enabled. No
I/O toggling.
are enabled)
M-DMA transferring data from
code + work flash, P-DMA chains
with maximum trigger activity.
TYP: TA = 25 °C, VDDD = 5.0 V,
process typ (TT), CM4 and CM0+
executing Dhrystone from flash
with cache enabled.
MAX: TA = 125 °C, VDDD = 5.5 V,
process worst (FF), CM4 and
CM0+ executing max_power.c
from flash with cache enabled
SID53A1 IDD2_8_1
All CPUs in Sleep mode
–
3
46
mA PLL disabled, CM4 and CM0+ are
sleeping at 8 MHz with IMO. All
peripherals, peripheral clocks,
interrupts, CSV, DMA, FLL, ECO
are disabled. No I/O toggling.
Typ: TA = 25 °C, VDDD = 5.0 V,
process typ (TT)
Max: TA = 125 °C, VDDD = 5.5 V,
process worst (FF)
Note
50.At cold temperature –5 °C to –40 °C, the DeepSleep to Active transition time can be higher than the max time indicated by as much
as 20 µs.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-3
DC specifications, CPU current and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ Max Units
Details/conditions
SID56A
IDD_CWU2
Average current for
cyclic wake-up
–
46
136
µA VDDD = 5.5 V, T = 25 °C, 64-KB
SRAM, ILO0 oAperation in
operation
DeepSleep, SmartIOoperations
with ILO0, CM0+, CM4: Retained
TYP: process typ (TT)
This is the average
current for the
specified LP Active
mode and DeepSleep
mode (RTC, WDT and
Event generator
operating).
MAX: process worst (FF)
This average current is achieved
under the following conditions.
1. MCU repetitively goes from
DeepSleep to LP Active with a
period of 32 ms.
2. One of the I/Os is toggled
using Smart I/O to activate an
external sensor connected to an
analog input of A/D in
DeepSleep
3. After 200 µs delay, the CM4
wakes up by event generator
trigger to LP Active mode with
IMO and A/D conversion is
triggered by software.
4. Group A/D conversion is
performed on 5 channels with
the sampling time of 1 µs each.
5. Once the group A/D
conversion is finished, and the
results fit in the window of the
range comparator, the I/O is
toggled back by software to
de-activate the sensor and the
CM4 goes back to DeepSleep.
SID59A
SID61A
IDD_DS64B
64-KB SRAM retention,
ILO0
–
–
35
130
3.5
µA DeepSleep Mode (RTC, WDT,
and event generator operating,
all other peripherals are off
except for retention registers),
TA = 25 °C, CM0+, CM4: Retained
Typ: VDDD = 5.0 V, process typ
(TT)
operation in
DeepSleep mode
Max: VDDD = 5.5 V, process worst
(FF)
IDD_DS64D
64-KB SRAM retention,
ILO0
0.9
mA DeepSleep Mode steady state at
TA = 125 °C (RTC, WDT, and event
generator operating, all other
peripherals are off except for
retention registers),
operation in
DeepSleep mode
CM0+, CM4: Retained
Typ: VDDD = 5.0 V, process typ
(TT)
Max: VDDD = 5.5 V, process worst
(FF)
Hibernate mode
SID62
IDD_HIB1
Hibernate Mode
–
5
–
µA ILO0/WDT operating. All other
peripherals, and all CPUs are
off.
TA = 25 °C, VDDD = 5.5 V,
process typ (TT)
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-3
DC specifications, CPU current and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ Max Units
Details/conditions
SID62A
IDD_HIB2
Hibernate Mode
–
–
130
µA ILO0/WDT operating. All other
peripherals, and all CPUs are
off.
TA = 125 °C, VDDD = 5.5 V,
process worst (FF)
Power mode transition times
SID65
tACT_DS
Power down time from
Active to DeepSleep
–
–
2.5
µs WhentheIMOisalreadyrunning
and all HFCLK roots are at least
8 MHz. HFCLK roots that are
slower than this will require
additional time to turn off.
SID63
tDS_ACT
DeepSleep to Active
transition time (IMO
clock, SRAM execution)
–
–
–
–
–
–
10[50]
20[50]
15[50]
µs When using the 8-MHz IMO.
Measured from wakeup
interrupt during DeepSleep
until wakeup.
SID63C
SID63A
tDS_ACT
DeepSleep to Active
transition time (IMO
clock, flash execution)
µs When using the 8-MHz IMO.
Measured from wakeup
interrupt during DeepSleep
until flash execution.
tDS_ACT_FLL
DeepSleep to Active
transition time (FLL
clock, SRAM execution)
µs When using the FLL to generate
80 MHz from the 8-MHz IMO.
Measured from wakeup
interrupt during DeepSleep
until the FLL locks.
SID63D
SID63B
SID68
tDS_ACT_FLL1 DeepSleep to Active
transition time (FLL
–
–
–
–
–
–
21.5[50] µs When using the FLL to generate
80 MHz from the 8-MHz IMO.
Measured from wakeup
clock, flash execution)
interrupt during DeepSleep
until flash execution.
tDS_ACT_PLL
DeepSleep to Active
transition time (PLL
clock, SRAM or flash
execution)
60[50]
µs When using the PLL to generate
80 MHz from the 8-MHz IMO.
Measured from wakeup
interrupt during DeepSleep
until the PLL locks.
tHVR_ACT
Release time from HV
reset (POR, BOD, OVD,
OCD, WDT, Hibernate
wakeup, or XRES_L)
release until CM0+
begins executing ROM
boot
265
µs Without boot runtime.
Guaranteed by design
SID68A
tLVR_ACT
Release time from LV
reset (Fault, Internal
system reset, MCWDT,
or CSV) during
–
–
10
µs Without boot runtime.
Guaranteed by design
Active/Sleep until
CM0+ begins executing
ROM boot
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-3
DC specifications, CPU current and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ Max Units
Details/conditions
SID68B
tLVR_DS
Release time from LV
reset (Fault, or
–
–
15
µs Without boot runtime.
Guaranteed by design
MCWDT) during
DeepSleep until CM0+
begins executing ROM
boot
SID80A
SID80B
SID81A
tRB_N
tRB_S
tFB
ROM boot startup time
or wakeup time from
hibernate in NORMAL
protection state
ROM boot startup time
or wakeup time from
hibernate in SECURE
protection state
Flash boot startup
time or wakeup time
from hibernate in
NORMAL/SECURE
protection state
–
–
–
–
–
–
1800
2740
80
µs Guaranteed by Design,
(Flash boot version 3.1.0.556
and later)
µs Guaranteed by Design,
(Flash boot version 3.1.0.556
and later)
µs Guaranteed by Design,
TOC2_FLAGS = 0x2CF,
Listen window = 0 ms
(Flash boot version 3.1.0.556
and later)
SID81B
tFB_A
Flash boot with app
authentication time in
NORMAL/SECURE
protection state
–
–
5000
µs Guaranteed by Design, TOC2_-
FLAGS = 0x24F, Listen window =
0 ms, Public key exponent e =
0x010001, APP size is 64 KB with
the last 256 bytes being a digital
signature in
RSASSA-PKCS1-v1.5.
Valid for RSA2K.
(Flash boot version 3.1.0.556
and later)
Regulator specifications
SID600
SID601
VCCD
IDD_ACT
Core supply voltage
1.05 1.1
1.15
150
V
Regulator operating
current in
–
–
–
–
80
1.5
–
µA Guaranteed by design
Active/Sleep mode
SID602
SID604
SID603
IDD_DPSLP
Regulator operating
current in
20
µA Guaranteed by design
mA Without triggering OVD
DeepSleep mode
IOUT
Available regulator
output current for
operation
150
375
IRUSH
In-rush current
–
mA Average VDDD current until Cs1
(connected to VCCD pin) is
charged after Active regulator is
turned on
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.4
Reset specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-4 XRES_L reset
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
conditions
XRES_L DC specifications
SID73
IDD_XRES
IDD when XRES_L asserted
–
–
0.9
mA TA = 125 °C, VDDD
5.5 V, process
=
worst (FF)
SID74
SID75
VIH
VIL
Input voltage HIGH threshold 0.7 × VDDD
–
–
–
V
V
CMOS input
CMOS input
Input voltage LOW threshold
–
0.3 ×
VDDD
SID76
SID77
SID78
RPULLUP
CIN
VHYSXRES
Pull-up resistor
Input capacitance
Input voltage hysteresis
7
–
–
–
–
20
5
–
kΩ
pF
V
0.05 ×
VDDD
XRES_L AC specifications
SID70
tXRES_ACT
XRES_L release to Active
transition
time
–
–
265
µs Without boot
runtime.
Guaranteed by
design
SID71
SID72
tXRES_PW
tXRES_FT
XRES_L pulse width
Pulse suppression width
5
100
–
–
–
–
µs
ns
release
HV/LV reset
System clock
System reset
release
RESET
ACTIVE
MODES
1
2
3
4
1:
2:
3:
4:
SID68/68A/68B: Time from HV/LV reset release until CM0+ begins executing ROM boot
SID80A/80B: ROM boot code operation
SID81A/81B: Flash boot code operation
User code operation
Figure 27-3
Reset sequence
Datasheet
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002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.5
I/O
All specifications are valid for –40 °C ≤ TA ≤ 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-5
I/O specifications
Spec ID
Parameter Description
Min
Typ
Max
Units Details/conditions
GPIO_STD specifications for ports P1 through P23
SID650
VOL1_GPIO_STD Output voltage
LOW level
–
–
0.6
V
V
V
V
V
V
V
V
V
V
V
V
IOL = 6 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
SID650C VOL1C_GPIO_STD Output voltage
LOW level
–
–
–
–
–
–
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
0.4
–
IOL = 5 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
SID651
SID652
VOL2_GPIO_STD Output voltage
LOW level
–
IOL = 2 mA
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
VOL3_GPIO_STD Output voltage
LOW level
–
IOL = 1 mA
drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
SID652C VOL3C_GPIO_STD Output voltage
LOW level
–
IOL = 2 mA
drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
SID653
VOL4_GPIO_STD Output voltage
LOW level
–
IOL = 0.5 mA
drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
SID653C VOL4C_GPIO_STD Output voltage
LOW level
–
IOL = 1 mA
drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
SID654
SID655
SID656
VOH1_GPIO_STD Output voltage
HIGH level
(VDDD or VDDIO_1 or
IOH = –2 mA
VDDIO_2 – 0.5
)
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
VOH2_GPIO_STD Output voltage
HIGH level
(VDDD or VDDIO_1 or
–
IOH = –5 mA
VDDIO_2 – 0.5
)
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
VOH3_GPIO_STD Output voltage
HIGH level
(VDDD or VDDIO_1 or
–
IOH = –1 mA
VDDIO_2 – 0.5
)
drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
SID656C VOH3C_GPI-
Output voltage
HIGH level
(VDDD or VDDIO_1 or
–
IOH = –2 mA
VDDIO_2 – 0.5
)
drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
O_STD
SID657
VOH4_GPIO_STD Output voltage
HIGH level
(VDDD or VDDIO_1 or
–
IOH = –0.5 mA
VDDIO_2 – 0.5
)
drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-5
Spec ID
I/O specifications (continued)
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID657C VOH4C_GPI-
Output voltage
HIGH level
(VDDD or VDDIO_1 or
–
–
V
IOH = –1 mA
VDDIO_2 – 0.5
)
drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
O_STD
SID658
RPD_GPIO_STD Pull-down resis-
tance
RPU_GPIO_STD Pull-up resistance
25
25
50
100
kΩ
SID659
SID660
50
–
100
–
kΩ
V
VIH_CMOS_GPI- Input voltage
0.7 × (VDDD or
HIGH threshold in
CMOS mode
V
DDIO_1 or VDDIO_2
O_STD
)
)
SID661
SID662
SID663
SID664
SID665
VIH_TTL_GPI-
O_STD
Input voltage
HIGH threshold in
TTL mode
2.0
–
–
–
–
–
–
–
V
V
V
V
V
VIH_AUTO_GPI- Input voltage
0.8 × (VDDD or
HIGH threshold in
AUTO mode
V
DDIO_1 or VDDIO_2
O_STD
VIL_CMOS_GPI- Input voltage
–
–
–
0.3 × (VDDD
LOW threshold in
CMOS mode
or VDDIO_1 or
O_STD
VDDIO_2
)
VIL_TTL_GPI-
O_STD
Input voltage
LOW threshold in
TTL mode
0.8
VIL_AUTO_GPI- Input voltage
0.5 × (VDDD
LOW threshold in
AUTO mode
or VDDIO_1 or
O_STD
VDDIO_2
)
SID666
SID668
SID669
SID670
VHYST_CMOS_G- Hysteresis in
CMOS mode
0.05 × (VDDD or
–
–
–
V
V
V
DDIO_1 or VDDIO_2
PIO_STD
)
VHYST_AUTO_G- Hysteresis in
0.05 × (VDDD or
–
5
AUTO mode
VDDIO_1 or VDDIO_2
PIO_STD
)
Cin_GPIO_STD
Input pin capaci-
tance
–
–
pF For 10 MHz
IIL_GPIO_STD
Input leakage
current
–250
0.02
250
nA For GPIO_STD except
P21.0, P21.1, P21.2,
P21.3, P23.3, P23.4.
V
DDIO_1 = VDDIO_2 =
VDDD = VDDA = 5.5 V,
VSSD < VI < VDDD
,
VDDIO_1, VDDIO_2
–40 °C TA 125 °C
TYP: TA = 25 °C,
VDDIO_1 = VDDIO_2
=
V
DDD = VDDA = 5.0 V
Datasheet
95
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-5
Spec ID
I/O specifications (continued)
Parameter Description
Min
Typ
Max
Units Details/conditions
SID670C IIL_GPIO_STD_B Input leakage
current
–700
0.02
700
nA Only for P21.0, P21.1,
P21.2, P21.3, P23.3,
P23.4.
V
DDIO_1 = VDDIO_2
VDDD = VDDA = 5.5 V,
SSD < VI < VDDD
=
V
,
VDDIO_1, VDDIO_2
–40 °C TA 125 °C
TYP: TA = 25 °C,
V
DDIO_1 = VDDIO_2
=
V
DDD = VDDA = 5.0 V
SID671
SID672
SID673
tR or tF
Rise time or fall
of VDDIO
Rise time or fall
1
1
1
–
–
–
10
20
20
ns 20-pF load,
drive_sel<1:0> = 0b00
(fast)_20_0_GPI- time (10% to 90%
)
O_STD
tR or tF
ns 50-pF load,
drive_sel<1:0> = 0b00
(fast)_50_0_GPI- time (10% to 90%
of VDDIO
)
O_STD
tR or tF
Rise time or fall
ns 20-pF load,
drive_sel<1:0> = 0b01,
guaranteed by design
ns 10-pF load,
drive_sel<1:0> = 0b10,
guaranteed by design
ns 6-pF load,
drive_sel<1:0> = 0b11,
guaranteed by design
ns 10-pF to 400-pF load,
RPU = 767 Ω,
(fast)_20_1_GPI- time (10% to 90%
of VDDIO
)
O_STD
SID674
SID675
SID676
tR or tF
Rise time or fall
1
1
–
–
–
20
20
(fast)_10_2_GPI- time (10% to 90%
of VDDIO
)
O_STD
tR or tF
Rise time or fall
(fast)_6_3_GPI- time (10% to 90%
of VDDIO
)
O_STD
tF (fast)_100_G- Fall time (30% to
PIO_STD
0.35
250
70% of VDDIO
)
drive_sel<1:0>= 0b00,
Freq = 100 kHz
SID677
tF (fast)_400_G- Fall time (30% to
PIO_STD
0.35
–
250
ns 10-pF to 400-pF load,
RPU = 350 Ω,
70% of VDDIO
)
drive_sel<1:0>= 0b00,
Freq = 400 kHz
SID678
SID679
fIN_GPIO_STD
fOUT_GPI-
Input frequency
Output frequency
–
–
–
–
80
50
MHz
MHz 20 pF load,
drive_sel<1:0>= 00,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
O_STD0H
SID680
SID681
fOUT_GPI-
O_STD0L
Output frequency
Output frequency
–
–
–
–
32
25
MHz 20 pF load,
drive_sel<1:0>= 00,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
MHz 20 pF load,
drive_sel<1:0>= 01,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
fOUT_GPI-
O_STD1H
Datasheet
96
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID682
fOUT_GPI-
O_STD1L
Output frequency
–
–
15
MHz 20 pF load,
drive_sel<1:0>= 01,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
SID683
SID684
SID685
SID686
fOUT_GPI-
O_STD2H
Output frequency
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
–
–
25
15
15
10
MHz 10 pF load,
drive_sel<1:0>= 10,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
MHz 10 pF load,
drive_sel<1:0>= 10,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
fOUT_GPI-
O_STD2L
fOUT_GPI-
O_STD3H
MHz 6 pF load,
drive_sel<1:0>= 11,
4.5 V ≤ VDDD or VDDIO_1
or VDDIO_2 ≤ 5.5 V
fOUT_GPI-
O_STD3L
MHz 6 pF load,
drive_sel<1:0>= 11,
2.7 V ≤ VDDD or VDDIO_1
or VDDIO_2 < 4.5 V
GPIO_ENH specifications only for P0
SID650A VOL1_GPIO_ENH Output voltage
LOW level
–
–
–
–
–
–
–
–
–
–
0.6
0.4
0.4
0.4
0.4
0.4
0.4
–
V
V
V
V
V
V
V
V
V
IOL = 6 mA
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD ≤ 5.5 V
SID650D VOL1D_GPI-
Output voltage
LOW level
–
IOL = 5 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD ≤ 5.5 V
O_ENH
SID651A VOL2_GPIO_ENH Output voltage
LOW level
–
IOL = 2 mA, 3 mA
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD < 4.5 V
SID652A VOL3_GPIO_ENH Output voltage
LOW level
–
IOL = 1 mA
drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD < 4.5 V
SID652D VOL3D_GPI-
Output voltage
LOW level
–
IOL = 2 mA
drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
O_ENH
SID653A VOL4_GPIO_ENH Output voltage
LOW level
–
IOL = 0.5 mA
drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD < 4.5 V
SID653D VOL4D_GPI-
Output voltage
LOW level
–
IOL = 1 mA
drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
O_ENH
SID654A VOH1_GPIO_ENH Output voltage
HIGH level
VDDD – 0.5
VDDD – 0.5
IOL = –2 mA
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD < 4.5 V
SID655A VOH2_GPIO_ENH Output voltage
HIGH level
–
IOL = –5 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD ≤ 5.5 V
Datasheet
97
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-5
Spec ID
I/O specifications (continued)
Parameter Description
Min
Typ
Max
Units Details/conditions
SID656A VOH3_GPIO_ENH Output voltage
HIGH level
VDDD – 0.5
–
–
V
IOL = –1 mA
drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD < 4.5 V
SID656D VOH3D_GPI-
Output voltage
HIGH level
VDDD – 0.5
VDDD – 0.5
VDDD – 0.5
25
–
–
–
–
V
IOL = –2 mA
drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
O_ENH
SID657A VOH4_GPIO_ENH Output voltage
HIGH level
V
IOL = –0.5 mA
drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD < 4.5 V
SID657D VOH4D_GPI-
Output voltage
HIGH level
–
–
V
IOL = –1 mA
drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
O_ENH
SID658A RPD_GPIO_ENH Pull-down
resistance
50
100
kΩ
SID659A RPU_GPIO_ENH Pull-up resistance
SID660A VIH_CMOS_GPI- Input voltage
25
50
–
100
–
kΩ
V
0.7 × VDDD
HIGH threshold in
CMOS mode
O_ENH
2
–
–
SID661A VIH_TTL_GPI-
Input voltage
HIGH threshold in
TTL mode
V
V
V
V
V
O_ENH
SID662A VIH_AUTO_GPI- Input voltage
0.8 × VDDD
–
–
–
–
–
HIGH threshold in
AUTO mode
O_ENH
SID663A VIL_CMOS_GPI- Input voltage
–
–
–
0.3 × VDDD
0.8
LOW threshold in
CMOS mode
Input voltage
LOW threshold in
TTL mode
O_ENH
SID664A VIL_TTL_GPI-
O_ENH
SID665A VIL_AUTO_GPI- Input voltage
0.5 × VDDD
LOW threshold in
AUTO mode
O_ENH
SID666A VHYST_CMOS_G- Hysteresis in
CMOS mode
0.05 × VDDD
0.05 × VDDD
–
–
–
–
–
V
V
PIO_ENH
SID668A VHYST_AUTO_G- Hysteresis in
AUTO mode
PIO_ENH
SID669A Cin_GPIO_ENH Input pin
capacitance
–
5
pF For 10 MHz
SID670A IIL_GPIO_ENH
Input leakage
current
–350
0.055
350
nA VDDD = VDDA = 5.5 V,
VSSD < VI < VDDD
,
–40 °C ≤ TA ≤ 125 °C
TYP: TA = 25 °C,
VDDD = VDDA = 5.0 V
SID671A tR or tF
Rise time or fall
1
1
–
–
10
20
ns 20-pF load,
(fast)_20_0_GPI- time (10% to 90%
drive_sel<1:0> = 0b00,
slow = 0
of VDDIO
)
O_ENH
SID672A tR or tF
Rise time or fall
ns 50-pF load,
(fast)_50_0_GPI- time (10% to 90%
drive_sel<1:0> = 0b00,
slow = 0
of VDDIO
)
O_ENH
Datasheet
98
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-5
Spec ID
I/O specifications (continued)
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID673A tR or tF
Rise time or fall
1
–
20
ns 20-pF load,
drive_sel<1:0> = 0b01,
slow = 0,
(fast)_20_1_GPI- time (10% to 90%
of VDDIO
)
O_ENH
guaranteed by design
SID674A tR or tF
Rise time or fall
1
1
–
–
–
–
20
20
ns 10-pF load,
drive_sel<1:0> = 0b10,
slow = 0,
(fast)_10_2_GPI- time (10% to 90%
of VDDIO
)
O_ENH
guaranteed by design
SID675A tR or tF
Rise time or fall
ns 6-pF load,
(fast)_6_3_GPI- time (10% to 90%
drive_sel<1:0> = 0b11,
slow = 0,
guaranteed by design
of VDDIO
)
O_ENH
SID676A tF_I2C
Fall time (30% to
20 × (VDDD
5.5)
/
/
250
160
ns 10-pF to 400-pF load,
drive_sel<1:0> = 0b00,
slow = 1,
(slow)_GPIO_EN 70% of VDDIO
)
H
minimum RPU = 400 Ω
SID677A tR or tF
Rise time or fall
20 × (VDDD
5.5)
ns 20-pF load,
drive_sel<1:0> = 0b00,
slow = 1,
(slow)_20_GPI- time (10% to 90%
of VDDIO
)
O_ENH
output frequency = 1
MHz
SID678A tR or tF
Rise time or fall
20 × (VDDD
5.5)
/
–
250
ns 400-pF load,
drive_sel<1:0> = 0b00,
slow = 1,
(slow)_400_GPI- time (10% to 90%
of VDDIO
)
O_ENH
output frequency =
400 kHz
SID679A fIN_GPIO_ENH
SID680A fOUT_GPI-
Input frequency
Output frequency
–
–
–
–
80
50
MHz
MHz 20-pF load,
drive_sel<1:0>= 0b00,
4.5 V ≤ VDDD ≤ 5.5 V
O_ENH0H
SID681A fOUT_GPI-
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
–
–
–
–
–
–
32
25
15
25
15
15
MHz 20-pF load,
drive_sel<1:0>= 0b00,
2.7 V ≤ VDDD < 4.5 V
MHz 20-pF load,
drive_sel<1:0>= 0b01,
4.5 V ≤ VDDD ≤ 5.5 V
MHz 20-pF load,
drive_sel<1:0>= 0b01,
2.7 V ≤ VDDD < 4.5 V
MHz 10-pF load,
drive_sel<1:0>= 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
O_ENH0L
SID682A fOUT_GPI-
O_ENH1H
SID683A fOUT_GPI-
O_ENH1L
SID684A fOUT_GPI-
O_ENH2H
SID685A fOUT_GPI-
MHz 10-pF load,
drive_sel<1:0>= 0b10,
2.7 V ≤ VDDD < 4.5 V
O_ENH2L
SID686A fOUT_GPI-
MHz 6-pF load,
drive_sel<1:0>= 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
O_ENH3H
Datasheet
99
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-5
Spec ID
I/O specifications (continued)
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID687A fOUT_GPI-
Output frequency
–
–
10
MHz 6-pF load,
drive_sel<1:0>= 0b11,
2.7 V ≤ VDDD < 4.5 V
O_ENH3L
GPIO input specifications
SID98
tFT
Analog glitch
filter (pulse
suppression
width)
Minimum pulse
width for GPIO
interrupt
–
–
–
50[51]
ns One filter per port
group
SID99
tINT
160
–
ns
Note
51.If longer pulse suppression width is required, use Smart I/O.
Datasheet
100
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.6
Analog peripherals
All specifications are valid for –40 °C ≤ TA ≤ 125 °C and for 2.7 V to 5.5 V except where noted.
27.6.1
SAR ADC
0xFFF
Actual conversion
characteristics
1.5 LSb
0xFFE
0xFFD
1 LSb (N - 1) + 0.5 LSb
VNT
0x003
0x002
0x001
Actual conversion
characteristics
Ideal
characteristics
0.5 LSb
VREFH
VREFL
Analog input
[LSb]
[V]
Total error of digital output N = ( VNT {1 LSb × (N – 1) + 0.5 LSb} ) / 1 LSb
1 LSb (Ideal value) = (VREFH – VREFL) / 4096
N: A/D converter digital output value
VZT (Ideal value): VREFL + 0.5 LSb [V]
VFST (Ideal value): VREFH – 1.5 LSb [V]
VNT: Voltage at which the digital output changes from N – 1 to N
Figure 27-4
ADC characteristics and error definitions
Table 27-6
12-bit SAR ADC DC specifications
Spec ID
Parameter
Description
Min
–
Typ
–
Max
12
Units
bits
V
Details/conditions
SID100
SID101
SID102
A_RES
SAR ADC resolution
A_VINS
Input voltage range
VREFH voltage range
VREFL
2.7
–
VREFH
VDDA
A_VREFH
–
V
ADC performance degrades when
high reference is higher than
supply
[52]
SID102A
SID103
A_VDDA
A_VREFL
VDDA voltage range
VREFL voltage range
2.7
–
–
5.5
V
V
VSSA
VSSA
ADC performance degrades when
low reference is lower than ground
SID103A
SID19A
Vband_gap
Internal band gap reference
voltage
0.882
–
0.9
–
0.918
0.25
V
CLAMP_COU-
Ratio of current collected on a pin
to the positive current injected into
a neighboring pin
%
PLING_RATIO_POS
SID19B
SID19C
Note
CLAMP_COU-
Ratio of current collected on a pin
to the negative current injected
into a neighboring pin
–
–
–
–
1.2
50
%
PLING_RATIO_NEG
RCLAMP_INTERNAL
Internal pin resistance to current
collection point
Ω
52.VDDD must be greater than 0.8 × VDDA when ADC[2] is enabled. VDDIO_1 must be greater than 0.8 × VDDA when ADC[0] is enabled.
Datasheet
101
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.6.2
Calculating the impact of neighboring pins
The three ADC specifications based on SID19A, SID19B, and SID19C, can be used to calculate the pin leakage and
resulting ADC offset caused by injection current using the below formula:
ILEAK = IINJECTED × CLAMP_COUPLING_RATIO
VERROR = ILEAK × (RCLAMP_INTERNAL + RSOURCE
)
Code Error = VERROR × 212 / VREF
Where:
I
I
INJECTED is the injected current in mA.
LEAK is the calculated leakage current in mA.
VERROR is the voltage error calculated due to leakage currents in V.
VREF is the ADC reference voltage in V.
Differential linearity error
Integral linearity error
0xFFF
Ideal
characteristics
Actual conversion
characteristics
N + 1
0xFFE
VFST
Actual conversion
characteristics
(Measured value)
(1 LSb [N - 1] + VZT)
0xFFD
N
VNT
(Measured value)
0x004
0x003
0x002
0x001
N - 1
Actual conversion
characteristics
V(N+
1)T
(Measured value)
VNT
(Measured value)
Ideal
characteristics
Actual conversion
characteristics
N -2
VZT
(Measured value)
VREFL
Analog input
VREFL
Analog input
VREFH
VREFH
Figure 27-5
Integral and differential linearity errors
Datasheet
102
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
EXTERNAL CIRCUIT
INTERNAL EQUIVALENT CIRCUIT
VDDIO
Channel selection MUX and ADC
REXT
RVIN
CVIN
CEXT
CIN
ESD Protection
REXT: Source impedance
CEXT: On-PCB capacitance
CIN: I/O pad or Input capacitance
RVIN: ADC equivalent input resistance
CVIN: ADC equivalent input capacitance
K: Constant for sampling accuracy, K = ln(abs(4096/LSbSAMPLE))
Sampling Time (tSAMPLE) requirement is shown in the following equation
tSAMPLE > K x { CVIN x ( RVIN + REXT ) + ( CIN + CEXT ) x (REXT) } [seconds]
K = value of 9.0 is recommended to get ±0.5 LSb sampling accuracy at 12-bit (LSbSAMPLE = ±0.5)
Figure 27-6
Table 27-7
ADC equivalent circuit for analog input
SAR ADC AC specifications
Spec ID Parameter
Description
Min
Typ
Max
Units Details/conditions
SID104
SID105
SID114
VZT
Zero transition voltage
–20
–
20
mV VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
before offset
adjustment
VFST
Full-scale transition
voltage
–20
–
20
mV VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
before offset
adjustment
fADC_4P5
ADC operating frequency
ADC operating frequency
Analog input sample time 412
2
2
–
–
–
26.67
13.34
–
MHz 4.5 V ≤ VDDA ≤ 5.5 V
MHz 2.7 V ≤ VDDA < 4.5 V
SID114A fADC_2P7
SID113 tS_4P5
ns 4.5 V ≤ VDDA ≤ 5.5 V
Guaranteed by design
SID113A tS_2P7
Analog input sample time 600
–
–
–
–
ns 2.7 V ≤ VDDA < 4.5 V
Guaranteed by design
SID113B tS_DR_4P5
Analog input sample time
when input is from
2
µs 4.5 V ≤ VDDA ≤ 5.5 V
Guaranteed by design
diagnostic reference
SID113C tS_DR_2P7
SID113D tS_TS
Analog input sample time 2.5
when input is from
–
–
–
–
µs 2.7 V ≤ VDDA < 4.5 V
Guaranteed by design
diagnostic reference
Analog input sample time
for temperature sensor
3
µs 2.7 V VDDA ≤ 5.5 V
Guaranteed by design
Datasheet
103
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-7
Spec ID Parameter
SID106 tST_4P5
SAR ADC AC specifications (continued)
Description
Min
Typ
–
Max
1
Units Details/conditions
Max throughput (Sample
per second)
–
Msps 4.5 V ≤ VDDA ≤ 5.5 V,
80MHz/3=26.67MHz,
11 sampling cycles,
15 conversion cycles
SID106A tST_2P7
Max throughput (Sample
per second)
–
–
0.5
Msps 2.7 V ≤ VDDA < 4.5 V
80 MHz / 6 = 13.3 MHz,
11 sampling cycles,
15 conversion cycles
SID107
SID108
CVIN
ADC input sampling
capacitance
Input path ON resistance
(4.5 V to 5.5 V)
Input path ON resistance
(2.7 V to 4.5 V)
Diagnostic path ON resis-
tance (4.5 V to 5.5 V)
–
–
–
–
–
–
–
–
–
4.8
9.4
13.9
40
50
4
pF Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
%
RVIN1
SID108A RVIN2
SID108B RDREF1
SID108C RDREF2
–
–
Diagnostic path ON resis-
tance (2.7 V to 4.5 V)
–
SID119
SID109
ACC_RLAD Diagnostic reference
resistor ladder accuracy
A_TE
–4
–5
Total error
5
LSb
VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
Total error after offset
and gain adjustment
at 12 bit resolution
mode
SID109A A_TEB
Total error
–12
–
12
LSb VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
Total error before
offset and gain
adjustment at 12 bit
resolution mode
SID110
SID111
SID112
A_INL
A_DNL
A_CE
Integral nonlinearity
–2.5
–0.99
–1
–
–
–
2.5
1.9
1
LSb VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
Differential nonlinearity
LSb
LSb
V
DDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
Channel-to-channel
V
DDA = 2.7 V to 5.5 V,
variation (for channels
connected to same ADC)
–40 °C ≤ TA ≤ 125 °C
SID115
IAIC
Analog input leakage
current
–350
70
350
nA When input pad is
selected for
conversion
SID116
SID117
IDIAGREF
IVDDA
Diagnostic reference
current
Analog power supply
current while ADC is
operating
–
–
–
70
µA
360
550
µA Per enabled ADC
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-7
SAR ADC AC specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Units Details/conditions
SID117A IVDDA_DS
Analog power supply
current while ADC is not
operating
–
–
21
µA Per enabled ADC
SID118
IVREF
Analog reference voltage
current while ADC is
operating
Analog reference voltage
current while ADC is not
operating
–
–
360
1.8
550
5
µA Per enabled ADC
µA Per enabled ADC
SID118A IVREF_LEAK
27.6.3
Temperature sensor
Table 27-8
Temperature sensor specifications
Spec ID Parameter
Description
Min
–5
Typ
–
Max
5
Units
Details/conditions
SID201
TSENSACC2 Temperature sensor
accuracy 2
°C –40 °C ≤ TJ ≤ 150 °C
This spec is valid when using
ADC[0] (VDDIO_1), ADC[1]
(VDDIO_2) or ADC[2] (VDDD
)
with the following condi-
tions:
a. 3.0 V ≤ VDDD, VDDIO_1 or
VDDIO_2 = VDDA = VREFH ≤ 3.6 V
or
b. 4.5 V ≤ VDDD, VDDIO_1 or
VDDIO_2 = VDDA = VREFH ≤ 5.5 V
SID201A TSENSACC3 Temperature sensor
accuracy 3
–10
–
10
°C –40 °C ≤ TJ ≤ 150 °C
This spec is valid when using
ADC[0] (VDDIO_1) or ADC[2]
(VDDD) with the following
condition:
2.7 V ≤VDDD or VDDIO_1 ≤ 5.5 V
and
2.7 V ≤ VDDA = VREFH ≤ 5.5 V
and
0.8 × VDDA < VDDD or VDDIO_1
27.6.4
Voltage divider accuracy
Table 27-9
Voltage divider accuracy
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/conditions
SID202 VMONDIV
Uncorrected monitor
voltage divider accuracy
(measured by ADC),
compared to ideal
supply/2
–20
2
20
%
Any HV supply pad
within 2.7 V–5.5 V
operating range
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.7
AC specifications
Unless otherwise noted, the timings are defined with the guidelines mentioned in the Figure 27-7.
Definition of rise / fall times
VDDD or VDDIO_1/2
80 %
80 %
20 %
20 %
VSSD
tR
tF
Time Reference Point Definition
VDDD or VDDIO_1/2
0.5 x VDDD or VDDIO_1/2
VSSD
Timing Reference Points
Figure 27-7
AC timings specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.8
Digital peripherals
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-10 Timer/counter/PWM (TCPWM) specifications
Spec ID Parameter
Description
Min
Typ
Max
Units Details/conditions
SID120A fC
TCPWM operating
frequency
–
–
80
MHz fC = peripheral clock
SID121
SID122
SID123
tPWMENEXT
tPWMEXT
tCRES
Input trigger pulse width for 2 / fC
all trigger events
–
–
–
–
–
–
ns Trigger Events can be
Stop, Start, Reload,
Count, Capture, or
Kill depending on
which mode of
operation is selected.
Output trigger pulse widths 2 / fC
ns Minimum possible
width of Overflow,
Underflow, and
Counter = Compare
(CC) value trigger
outputs
Resolution of counter
PWM resolution
1 / fC
ns Minimum time
between successive
counts
ns Minimumpulsewidth
of PWM output
ns Minimumpulsewidth
between Quadrature
phase inputs.
SID124
SID125
tPWMRES
tQRES
1 / fC
2 / fC
–
–
–
–
Quadrature inputs
resolution
TCPWM Timing Diagrams
Input Signal
VIH
VIL
1
2
1
2
VOH
VOL
Output Signal
1: tPWMENEXT, tQRES
2: tPWMEXT
Figure 27-8
TCPWM timing diagrams
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-11 Serial communication block (SCB) specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
–
–
80
MHz
SID129A fSCB
SCB operating frequency
I2C interface-standard-mode
SID130 fSCL
SCL clock frequency
–
–
–
–
–
–
100
–
kHz
ns
SID131 tHD;STA
SID132 tLOW
SID133 tHIGH
SID134 tSU;STA
Hold time, START condition
Low period of SCL
4000
4700
4000
4700
–
ns
High period of SCL
–
ns
Setup time for a repeated
START
–
ns
SID135 tHD;DAT
SID136 tSU;DAT
SID138 tF
Data hold time, for receiver
Data setup time
0
–
–
–
–
–
–
–
ns
250
–
ns
Fall time of SCL and SDA
Setup time for STOP
300
–
ns Input and output
SID139 tSU;STO
SID140 tBUF
4000
4700
ns
ns
Bus-free time between
START and STOP
–
SID141 CB
Capacitive load for each bus
line
–
–
–
–
400
pF
ns
ns
SID142 tVD;DAT
Time for datasignal from SCL
LOW to SDA output
3450
SID143 tVD;ACK
SID144 VOL
Data valid acknowledge time
LOW level output voltage
–
0
–
–
3450
0.4
V
Open-drain at 3 mA
sink current
SID145 IOL
I2C interface-fast-mode
LOW level output current
3
–
–
mA VOL = 0.4 V
SID150 fSCL_F
SCL clock frequency
Hold time, START condition
Low period of SCL
–
–
–
–
–
–
400
–
kHz
ns
SID151 tHD;STA_F
SID152 tLOW_F
SID153 tHIGH_F
SID154 tSU;STA_F
600
1300
600
600
–
ns
High period of SCL
–
ns
Setup time for a repeated
START
–
ns
SID155 tHD;DAT_F
SID156 tSU;DAT_F
SID158 tF_F
Data hold time, for receiver
Data setup time
0
–
–
–
–
–
ns
ns
100
Fall time of SCL and SDA
20 ×
300
ns Input and output,
GPIO_ENH: slow
(VDDD
/
mode, 400 pF load
5.5)
SID158A tFA_F
Fall time of SCL and SDA
Setup time for STOP
0.35
–
300
ns Input and output
GPIO_STD:
drive_sel<1:0>= 0b00
MIN: 10 pF load,
RPU = 35.41 kΩ
MAX: 400 pF load,
RPU = 350 Ω
SID159 tSU;STO_F
600
–
–
ns Input and output
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
SID160 tBUF_F
Bus free time between
START and STOP
1300
–
–
ns
pF
ns
SID161 CB_F
Capacitive load for each bus
line
–
–
–
–
400
900
SID162 tVD;DAT_F
Time for datasignal from SCL
LOW to SDA output
SID163 tVD;ACK_F
SID164 tSP_F
Data valid acknowledge time
–
–
–
–
900
50
ns
ns
Pulse width of spikes that
must be suppressed by the
input filter
SID165 VOL_F
LOW level output voltage
0
–
0.4
V
Open-drain at 3 mA
sink current
SID165 IOL_F
SID167 IOL2_F
LOW level output current
LOW level output current
3
6
–
–
–
–
mA VOL = 0.4 V
mA VOL = 0.6 V[53]
I2C interface-fast-plus mode
SID170 fSCL_FP
SID171 tHD;STA_FP
SID172 tLOW_FP
SID173 tHIGH_FP
SID174 tSU;STA_FP
SCL clock frequency
–
–
–
–
–
–
1
–
–
–
–
MHz
ns
Hold time, START condition
Low period of SCL
260
500
260
260
ns
High period of SCL
ns
Setup time for a repeated
START
ns
SID175 tHD;DAT_FP
SID176 tSU;DAT_FP
SID178 tF_FP
Data hold time, for receiver
Data setup time
0
–
–
–
–
–
ns
ns
50
Fall time of SCL and SDA
20 ×
160
ns Input and output
20-pF load
(VDDD
GPIO_ENH: slow mode
/5.5)
260
500
SID179 tSU;STO_FP
SID180 tBUF_FP
Setup time for STOP
–
–
–
–
ns Input and output
ns
Bus free time between
START and STOP
SID181 CB_FP
Capacitive load for each bus
line
–
–
–
–
20
pF
ns
SID182 tVD;DAT_FP
Time for datasignal from SCL
LOW to SDA output
450
SID183 tVD;ACK_FP
SID184 tSP_FP
Data valid acknowledge time
–
–
–
–
450
50
ns
ns
Pulse width of spikes that
must be suppressed by the
input filter
SID186 VOL_FP
LOW level output voltage
0
3
–
–
0.4
–
V
Open-drain at 3-mA
sink current
SID187 IOL_FP
LOW level output current
mA VOL = 0.4 V[54]
Notes
53.In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL
.
54.In order to drive full bus load at 1 MHz, 20 mA IOL is required at 0.4 V VOL. However, this device does not support it.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
SPI interface master (Full-clock mode: LATE_MISO_SAMPLE = 1) [Conditions: drive_sel<1:0>= 0x]
SID190B fSPI
SPI operating frequency
–
–
10
MHz Do not use half-clock
mode:
LATE_MISO_SAMPLE =
0
SID191 tDMO
SID192 tDSI
SID193 tHMO
SPI Master: MOSI valid after
SCLK driving edge
–
40
0
–
15
–
ns
SPI Master: MISO valid before
SCLK capturing edge
–
–
ns
SPI Master: Previous MOSI
data hold time
–
ns
SID194 tW_SCLK_H_L SPISCLKpulsewidthHIGHor
LOW
–
0.4 × (1
–
ns
/ fSPI
)
SID196 tDHI
SPI Master: MISO hold time
after SCLK capturing edge
0
–
–
ns
SID198 tEN_SETUP
SID199 tEN_SHOLD
SID195 CSPIM_MS
SSEL valid, before the first
SCK capturing edge
0.5 ×
–
–
–
–
ns Min is half clock period
ns Min is half clock period
pF
(1/fSPI
)
)
SSEL hold, after the last SCK 0.5 ×
–
capturing edge
(1/fSPI
–
SPI capacitive load
10
SPI interface slave (internally clocked) [Conditions: drive_sel<1:0>= 0x]
SID205 fSPI_INT
SID206 tDMI_INT
SPI operating frequency
–
5
–
–
10
–
MHz
ns
SPI Slave: MOSI Valid before
Sclock capturing edge
SID207 tDSO_INT
SID208 tHSP
SPI Slave: MISO Valid after
Sclock driving edge, in the
internal-clocked mode
–
–
62
ns
SPI Slave: Previous MISO
data hold time
3
–
–
–
–
–
–
–
–
ns
ns
ns
ns
SID209 tEN_SETUP_INT SPI Slave: SSEL valid to first
SCK valid edge
33
33
20
SID210 tEN_HOLD_INT SPI Slave Select active (LOW)
from last SCLK hold
SID211 tEN_SET-
SPI Slave: from SSEL valid, to
SCK falling edge before the
first data bit
UP_PRE
SID212 tEN_HOLD_PRE SPI Slave: from SCK falling
edge before the first data bit,
20
20
20
–
–
–
–
–
–
ns
ns
ns
to SSEL invalid
SID213 tEN_SETUP_CO SPI Slave: from SSEL valid, to
SCK falling edge in the first
data bit
SID214 tEN_HOLD_CO SPI Slave: from SCK falling
edge in the first data bit, to
SSEL invalid
SID215 tW_DIS_INT
SPI Slave Select inactive time
40
20
–
–
–
–
ns
ns
SID216 tW_SCLKH_INT SPI SCLK pulse width HIGH
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
20
12
–
Typ
–
Max Units Details/conditions
SID217 tW_SCLKL_INT SPI SCLK pulse width LOW
–
–
ns
ns
pF
SID218 tSIH_INT
SID219 CSPIS_INT
SPI MOSI hold from SCLK
SPI Capacitive Load
–
–
10
SPI interface slave (externally clocked) [Conditions: drive_sel<1:0>= 0x]
SID220B fSPI_EXT
SID221 tDMI_EXT
SPI operating frequency
–
5
–
–
10
–
MHz
ns
SPI Slave: MOSI Valid before
Sclock capturing edge
SID222 tDSO_EXT
SID223 tHSO_EXT
SPI Slave: MISO Valid after
Sclock driving edge, in the
external-clocked mode
–
–
32
ns
SPI Slave: Previous MISO
data hold time
3
–
–
–
–
–
–
ns
ns
ns
SID224 tEN_SET-
SPI Slave: SSEL valid to first
SCK valid edge
40
40
UP_EXT
SID225 tEN_HOLD_EXT SPI Slave Select active (LOW)
from last SCLK hold
SID226 tW_DIS_EXT
SPI Slave Select inactive time
80
34
34
20
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
pF
ns
SID227 tW_SCLKH_EXT SPI SCLK pulse width HIGH
SID228 tW_SCLKL_EXT SPI SCLK pulse width LOW
–
SID229 tSIH_EXT
SID230 CSPIS_EXT
SID231 tVSS_EXT
SPI MOSI hold from SCLK
SPI Capacitive Load
–
10
33
SPI Slave: MISO valid after
SSEL falling edge (CPHA = 0)
–
UART interface
SID240 fBPS
Data rate
–
–
10
Mbps
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
8
7
9
70%
30%
70%
70%
70%
30%
6
SDA
SCL
30%
30%
12
8
9
4
70%
70%
70%
70%
30%
70%
30%
30%
30%
30%
30%
30%
2
1
3
START condition
11
70%
30%
70%
30%
70%
70%
SDA
SCL
30%
70%
2
14
10
13
70%
70%
30%
9th clock
5
Repeated START
condition
STOP condition
START condition
1: SCL clock period = 1/fSCL
2: Hold time, START condition = tHD;STA
3: LOW period of SCL = tLOW
4: HIGH period of SCL = tHIGH
5: Setup time for a repeated START = tSU;STA
6: Data hold time, for receiver = tHD;DAT
7: Data setup time = tSU;DAT
8: Fall time of SCL and SDA = tF
9: Rise time of SCL and SDA = tR
10: Setup time for STOP = tSU;STO
11: Bus-free time between START and STOP = tBUF
12: Time for data signal from SCL LOW to SDA output = tVD;DAT
13: Data valid acknowledge time = tVD;ACK
14: Pulse width of spikes that must be suppressed by the input filter = tSP
Figure 27-9
I2C timing diagrams
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)
CPHA=0
9
SSEL
2
1
3
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
5
6
MISO
(input)
7
8
MOSI
(output)
1: SCLK period = 1 / fSPI
2: Enable lead time (setup)= tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold)= tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time= tDSI
6: Input data hold time= tDHI
7: Output data valid after SCLK driving edge= tDMO
8: Output data hold time= tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 27-10 SPI master timing diagrams with LOW clock phase
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)
CPHA=1
9
SSEL
2
3
1
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
5
6
MISO
(input)
7
8
MOSI
(output)
1: SCLK period = 1 / fSPI
2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tHDI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 27-11 SPI master timing diagrams with HIGH clock phase
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
SPI Slave Timing Diagrams
CPHA=0
10
SSEL
2
1
3
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
8
7
9
MISO
(output)
5
6
MOSI
(input)
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup)= tEN_SETUP_EXT
3: enable trail time (hold)= tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge= tDSO_EXT
8: output data valid after SSEL falling edge (CPHA=0)= tVSS_EXT
9: output data hold time = tHSO
10: SSEL high pulse width= tDIS_EXT
Figure 27-12 SPI slave timing diagrams with LOW clock phase
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
SPI slave Timing Diagrams
CPHA=1
9
SSEL
2
3
1
SCLK
(CPOL=0)
4
SCLK
(CPOL=1)
7
8
MISO
(output)
5
6
MOSI
(input)
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data hold time = tHSO
9: SSEL high pulse width = tDIS_EXT
Figure 27-13 SPI slave timing diagrams with HIGH clock phase
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.8.1
LIN specifications
Table 27-12 LIN specifications
Spec ID Parameter
SID249A fLIN
Description
Internalclockfrequencyto
the LIN block
Min
–
Typ
–
Max
80
Units Details/conditions
MHz
SID250
SID250A BR_REF
BR_NOM
Bit rate on the LIN bus
1
1
–
–
20
115.2
kbps Guaranteed by design
kbps Guaranteed by design
Bit rate on the LIN bus (not
in standard LIN specifi-
cation) for re-flashing in
LIN slave mode
27.8.2
CAN FD specifications
Table 27-13 CAN FD specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID630A fHCLK
System clock frequency
–
–
80
MHz fcclk ≤ fhclk,
Guaranteed by design
SID631A fCCLK
CAN clock frequency
–
–
80
MHz fcclk ≤ fhclk,
Guaranteed by design
27.9
Memory
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-14 Flash DC specifications
Spec ID
SID260
Parameter
VPE
Description
Erase and program voltage
Min Typ Max Units Details/conditions
2.7 5.5
–
V
Table 27-15 Flash AC specifications
Spec ID Parameter
Description
Min Typ Max Units
Details/conditions
SID257A fFO
Maximum flash memory
operation frequency
–
–
–
–
–
80
37.5
–
MHz Zero wait access to
code-flash memory up to
80 MHz
SID254
SID255
tERS_SUS
Maximum time from erase
suspend command till erase
is indeed suspend
–
µs
tERS_RES_SUS Minimum time allowed from 250
erase resume to erase
µs Guaranteed by design
suspend
Blank check time for N-bytes
of work-flash
SID258A tBC_WF_A
–
12.5 +
0.375
× N
µs At 80 MHz, N ≥ 4 and
multiple of 4, excludes
system overhead time
SID259
tSECTORE-
RASE1
Sector erase time
(Code-flash: 32 KB)
Sector erase time
(Code-flash: 8 KB)
–
–
–
45
15
80
90
ms Includes internal
preprogramming time
ms Includes internal
preprogramming time
SID259A tSECTORE-
30
RASE2
SID261
tSECTORE-
RASE3
Sector erase time
(Work-flash, 2 KB)
160
ms Includes internal
preprogramming time
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-15 Flash AC specifications (continued)
Spec ID Parameter
Description
Min Typ Max Units
Details/conditions
ms Includes internal
preprogramming time
SID262
SID263
SID264
SID265
SID266
SID267
SID268
tSECTORE-
RASE4
Sector erase time
–
5
15
60
70
(Work-flash, 128 bytes)
tWRITE1
64-bit write time
(Code-flash)
256-bit write time
(Code-flash)
–
30
40
µs Excludes system
overhead time
tWRITE2
tWRITE3
tWRITE4
tFRET1
–
µs Excludes system
overhead time
4096-bit write time
–
320 1200
µs Excludes system
overhead time
(Code-flash)[55]
32-bit write time
(Work-flash)
–
30
–
60
–
µs Excludes system
overhead time
years TA (power on and off) ≤85
Code-flash retention.
20
20
1000 program/erase cycles
°C average
tFRET3
Work-flash retention.
125,000 program/erase
cycles
–
–
years TA (power on and off) ≤85
°C average
SID269
tFRET4
Work-flash retention.
250,000 program/erase
cycles
10
–
–
years TA (power on and off) ≤85
°C average
SID612
SID613
ICC_ACT2
ICC_ACT3
Program operating current
(Code or Work-flash)
Erase operating current
(Code or Work-flash)
–
–
15
15
48
48
mA VDDD = 5 V
Guaranteed by design
mA VDDD = 5 V
Guaranteed by design
Note
55.The code-flash includes a 'Write Buffer' of 4096-bit. If the application software writes this buffer multiple times, to get the overall
write time multiply one sector write time with the corresponding factor (say for factor 64, example, 64 x 512 B = 32 KB [one sector])
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.10
System resources
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-16 System resources
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
conditions
Power-on-reset specifications
SID270 VPOR_R
SID276 VPOR_F
SID271 VPOR_H
SID272 tDLY_POR
VDDD rising voltage to de assert
POR
VDDD falling voltage to assert
POR
1.5
1.45
20
–
–
–
–
2.35
2.1
300
3
V
V
Guaranteed by
design
Level detection hysteresis
mV Guaranteed by
design
µs Guaranteed by
design
Delay between VDDD rising
through 2.3 V and an internal
deassertion of POR
–
SID273 tPOFF
SID274 POR_RR1
VDDD Power off time
100
–
–
–
–
µs VDDD < 1.45 V
V
DDD power ramp rate with
robust BOD (BOD operation is
guaranteed)
100 mV/µs This ramp
supports robust
BOD
SID275 POR_RR2
VDDD power ramp rate without
robust BOD
–
–
1000 mV/µs This ramp does not
support robust
BOD
tPOFF must be
satisfied
High-voltage BOD (HV BOD) specifications
SID500 VTR_2P7_R
HV BOD 2.7 V rising detection
2.474 2.55 2.627
V
V
point for VDDD and VDDA
(default)
SID501 VTR_2P7_F
HV BOD 2.7 V falling detection 2.449 2.525 2.601
point for VDDD and VDDA
(default)
SID502 VTR_3P0_R
SID503 VTR_3P0_F
HV BOD 3.0 V rising detection
point for VDDD and VDDA
HV BOD 3.0 V falling detection
point for VDDD and VDDA
2.765 2.85 2.936
2.74 2.825 2.91
V
V
SID505 HVBOD_RR_A Power ramp rate: VDDD and
DDA (Active)
SID506 HVBOD_RR_DS Power ramp rate: VDDD and
VDDA (DeepSleep)
–
–
–
–
–
–
100 mV/µs
V
10
mV/µs
SID507 tDLY_ACT_HVBOD Active mode delay between
VDDD falling/rising through
0.5
µs Guaranteed by
design
VTR_2P7_F/R or VTR_3P0_F/R and
an internal HV BOD signal
transitioning
SID507A tDLY_ACT_HVBOD Active mode delay between
VDDA falling/rising through
–
–
1
µs Guaranteed by
design
VTR_2P7_F/R or VTR_3P0_F/R and
internal HV BOD signal transi-
tioning
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
conditions
SID507B tDLY_DS_HVBOD DeepSleep mode delay
between VDDD/VDDA
–
–
4
µs Guaranteed by
design
falling/rising through
VTR_2P7_F/R or VTR_3P0_F/R and
an internal HV BOD signal
transitioning
SID508 tRES_HVBOD
Response time of HV BOD,
VDDD/VDDA supply. (For
100
–
–
ns Guaranteed by
design
falling-then-rising supply at
max ramp rate; threshold is
VTR_2P7_F or VTR_3P0_F.)
Low-voltage BOD (LV BOD) specifications
SID510 VTR_R_LVBOD
LV BOD rising detection point
for VCCD
LV BOD falling detection point 0.892 0.92 0.948
for VCCD
0.917 0.945 0.973
V
V
SID511 VTR_F_LVBOD
SID515 tDLY_ACT_LVBOD Active delay between VCCD
falling/rising through
–
–
1
µs Guaranteed by
design
VTR_R/F_LVBOD and an internal
LV BOD signal transitioning
SID515A tDLY_DS_LVBOD
DeepSleep mode delay
between VCCD falling/rising
through VTR_R/F_LVBOD and an
internal LV BOD signal transi-
tioning
–
–
12
µs Guaranteed by
design
SID516 tRES_LVBOD
Response time of LV BOD. (For
falling-then-rising supply at
max ramp rate; threshold is
VTR_F_LVBOD.)
100
–
–
ns Guaranteed by
design
Low-voltage detector (LVD) DC specifications
SID520 VTR_2P8_F
SID521 VTR_2P9_F
SID522 VTR_3P0_F
SID523 VTR_3P1_F
SID524 VTR_3P2_F
SID525 VTR_3P3_F
SID526 VTR_3P4_F
SID527 VTR_3P5_F
SID528 VTR_3P6_F
LVD 2.8 V falling detection
point for VDDD
LVD 2.9 V falling detection
point for VDDD
LVD 3.0 V falling detection
point for VDDD
LVD 3.1 V falling detection
point for VDDD
LVD 3.2 V falling detection
point for VDDD
LVD 3.3 V falling detection
point for VDDD
LVD 3.4 V falling detection
point for VDDD
LVD 3.5 V falling detection
point for VDDD
Typ – 2800 Typ +
4% 4%
Typ – 2900 Typ +
4% 4%
Typ – 3000 Typ +
4% 4%
Typ – 3100 Typ +
4% 4%
Typ – 3200 Typ +
4% 4%
Typ – 3300 Typ +
4% 4%
Typ – 3400 Typ +
4% 4%
Typ – 3500 Typ +
4% 4%
mV
mV
mV
mV
mV
mV
mV
mV
mV
LVD 3.6 V falling detection
point for VDDD
Typ – 3600 Typ +
4% 4%
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
conditions
SID529 VTR_3P7_F
SID530 VTR_3P8_F
SID531 VTR_3P9_F
SID532 VTR_4P0_F
SID533 VTR_4P1_F
SID534 VTR_4P2_F
SID535 VTR_4P3_F
SID536 VTR_4P4_F
SID537 VTR_4P5_F
SID538 VTR_4P6_F
SID539 VTR_4P7_F
SID540 VTR_4P8_F
SID541 VTR_4P9_F
SID542 VTR_5P0_F
SID543 VTR_5P1_F
SID544 VTR_5P2_F
SID545 VTR_5P3_F
SID546 VTR_2P8_R
SID547 VTR_2P9_R
SID548 VTR_3P0_R
SID549 VTR_3P1_R
SID550 VTR_3P2_R
SID551 VTR_3P3_R
LVD 3.7 V falling detection
point for VDDD
LVD 3.8 V falling detection
point for VDDD
LVD 3.9 V falling detection
point for VDDD
Typ – 3700 Typ +
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
4% 4%
Typ – 3800 Typ +
4% 4%
Typ – 3900 Typ +
4% 4%
LVD 4.0 V falling detection
point for VDDD
LVD 4.1 V falling detection
point for VDDD
LVD 4.2 V falling detection
point for VDDD
LVD 4.3 V falling detection
point for VDDD
LVD 4.4 V falling detection
point for VDDD
LVD 4.5 V falling detection
point for VDDD
LVD 4.6 V falling detection
point for VDDD
LVD 4.7 V falling detection
point for VDDD
LVD 4.8 V falling detection
point for VDDD
LVD 4.9 V falling detection
point for VDDD
LVD 5.0 V falling detection
point for VDDD
LVD 5.1 V falling detection
point for VDDD
LVD 5.2 V falling detection
point for VDDD
LVD 5.3 V falling detection
point for VDDD
LVD 2.8 V rising detection point Typ – 2825 Typ +
for VDDD 4% 4%
LVD 2.9 V rising detection point Typ – 2925 Typ +
for VDDD 4% 4%
Typ – 4000 Typ +
4% 4%
Typ – 4100 Typ +
4% 4%
Typ – 4200 Typ +
4% 4%
Typ – 4300 Typ +
4% 4%
Typ – 4400 Typ +
4% 4%
Typ – 4500 Typ +
4% 4%
Typ – 4600 Typ +
4% 4%
Typ – 4700 Typ +
4% 4%
Typ – 4800 Typ +
4% 4%
Typ – 4900 Typ +
4% 4%
Typ – 5000 Typ +
4% 4%
Typ – 5100 Typ +
4% 4%
Typ – 5200 Typ +
4% 4%
Typ – 5300 Typ +
4% 4%
mV Same as VTR_2P8_F
+ 25 mV
mV Same as VTR_2P9_F
+ 25 mV
mV Same as VTR_3P0_F
+ 25 mV
mV Same as VTR_3P1_F
+ 25 mV
mV Same as VTR_3P2_F
+ 25 mV
mV Same as VTR_3P3_F
+ 25 mV
LVD 3.0 V rising detection point Typ – 3025 Typ +
for VDDD 4% 4%
LVD 3.1 V rising detection point Typ – 3125 Typ +
for VDDD 4% 4%
LVD 3.2 V rising detection point Typ – 3225 Typ +
for VDDD 4% 4%
LVD 3.3 V rising detection point Typ – 3325 Typ +
for VDDD 4% 4%
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
conditions
SID552 VTR_3P4_R
SID553 VTR_3P5_R
SID554 VTR_3P6_R
SID555 VTR_3P7_R
SID556 VTR_3P8_R
SID557 VTR_3P9_R
SID558 VTR_4P0_R
SID559 VTR_4P1_R
SID560 VTR_4P2_R
SID561 VTR_4P3_R
SID562 VTR_4P4_R
SID563 VTR_4P5_R
SID564 VTR_4P6_R
SID565 VTR_4P7_R
SID566 VTR_4P8_R
SID567 VTR_4P9_R
SID568 VTR_5P0_R
SID569 VTR_5P1_R
SID570 VTR_5P2_R
SID571 VTR_5P3_R
LVD 3.4 V rising detection point Typ – 3425 Typ +
mV Same as VTR_3P4_F
+ 25 mV
mV Same as VTR_3P5_F
+ 25 mV
mV Same as VTR_3P6_F
+ 25 mV
for VDDD 4% 4%
LVD 3.5 V rising detection point Typ – 3525 Typ +
for VDDD 4% 4%
LVD 3.6 V rising detection point Typ – 3625 Typ +
for VDDD 4% 4%
LVD 3.7 V rising detection point Typ – 3725 Typ +
for VDDD 4% 4%
LVD 3.8 V rising detection point Typ – 3825 Typ +
for VDDD 4% 4%
LVD 3.9 V rising detection point Typ – 3925 Typ +
for VDDD 4% 4%
LVD 4.0 V rising detection point Typ – 4025 Typ +
for VDDD 4% 4%
LVD 4.1 V rising detection point Typ – 4125 Typ +
for VDDD 4% 4%
LVD 4.2 V rising detection point Typ – 4225 Typ +
for VDDD 4% 4%
LVD 4.3 V rising detection point Typ – 4325 Typ +
for VDDD 4% 4%
LVD 4.4 V rising detection point Typ – 4425 Typ +
for VDDD 4% 4%
LVD 4.5 V rising detection point Typ – 4525 Typ +
for VDDD 4% 4%
LVD 4.6 V rising detection point Typ – 4625 Typ +
for VDDD 4% 4%
LVD 4.7 V rising detection point Typ – 4725 Typ +
for VDDD 4% 4%
LVD 4.8 V rising detection point Typ – 4825 Typ +
for VDDD 4% 4%
LVD 4.9 V rising detection point Typ – 4925 Typ +
for VDDD 4% 4%
LVD 5.0 V rising detection point Typ – 5025 Typ +
for VDDD 4% 4%
LVD 5.1 V rising detection point Typ – 5125 Typ +
for VDDD 4% 4%
LVD 5.2 V rising detection point Typ – 5225 Typ +
for VDDD 4% 4%
mV Same as VTR_3P7_F
+ 25 mV
mV Same as VTR_3P8_F
+ 25 mV
mV Same as VTR_3P9_F
+ 25 mV
mV Same as VTR_4P0_F
+ 25 mV
mV Same as VTR_4P1_F
+ 25 mV
mV Same as VTR_4P2_F
+ 25 mV
mV Same as VTR_4P3_F
+ 25 mV
mV Same as VTR_4P4_F
+ 25 mV
mV Same as VTR_4P5_F
+ 25 mV
mV Same as VTR_4P6_F
+ 25 mV
mV Same as VTR_4P7_F
+ 25 mV
mV Same as VTR_4P8_F
+ 25 mV
mV Same as VTR_4P9_F
+ 25 mV
mV Same as VTR_5P0_F
+ 25 mV
mV Same as VTR_5P1_F
+ 25 mV
mV Same as VTR_5P2_F
+ 25 mV
LVD 5.3 V rising detection point Typ – 5325 Typ +
mV Same as VTR_5P3_F
+ 25 mV
for VDDD
Power ramp rate: VDDD (Active)
Power ramp rate: VDDD
(DeepSleep)
4%
–
–
4%
SID573 LVD_RR_A
SID574 LVD_RR_DS
–
–
100 mV/µs
10 mV/µs
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
conditions
SID575 tDLY_ACT_LVD
SID575A tDLY_DS_LVD
SID576 tRES_LVD
Active mode delay between
VDDD falling/rising through LVD
rising/falling point and an
internal LVD signal
–
–
1
4
–
µs Guaranteed by
design
transitioning
DeepSleep mode delay
between VDDD falling/rising
through LVD rising/falling
point and an internal LVD
signal rising
Response time of LVD, VDDD
supply. LVD guaranteed to
generate pulse for VDDD pulse
width greater than this. (For
falling-then-rising supply at
max ramp rate; pulse width is
time below LVD falling point)
–
–
–
µs Guaranteed by
design
100
ns Guaranteed by
design
High-voltage OVD (HV OVD) specifications
SID580 VTR_5P0_R
SID581 VTR_5P0_F
SID582 VTR_5P5_R
HV OVD 5.0-V rising detection
point for VDDD and VDDA
HV OVD 5.0-V falling detection 5.025 5.18 5.335
point for VDDD and VDDA
HV OVD 5.5-V rising detection
point for VDDD and VDDA
(default)
5.049 5.205 5.361
V
V
V
5.548 5.72 5.892
SID583 VTR_5P5_F
HV OVD 5.5-V falling detection 5.524 5.695 5.866
V
point for VDDD and VDDA
(default)
SID585 HVOVD_RR_A Power ramp rate: VDDD and
VDDA (Active)
SID586 HVOVD_RR_DS Power ramp rate: VDDD and
VDDA (DeepSleep)
SID587 tDLY_ACT_HVOVD Active mode delay between
VDDD falling/rising through
–
–
–
–
–
–
100 mV/µs
10
1
mV/µs
µs Guaranteed by
design
VTR_5P0_F/R or VTR_5P5_F/R and
an internal HV OVD signal
transitioning
SID587A tDLY_ACT_H-
Active mode delay between
VDDA falling/rising through
VTR_5P0_F/R or VTR_5P5_F/R and
an internal HV OVD signal
transitioning
–
–
–
–
1.5
4
µs Guaranteed by
design
VOVD_A
SID587B tDLY_DS_HVOVD DeepSleep mode delay
between VDDD/VDDA
µs Guaranteed by
design
falling/rising through
VTR_5P0_F/R or VTR_5P5_F/R and
an internal HV OVD signal
transitioning
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
conditions
SID588 tRES_HVOVD
Response time of HV OVD. (For
rising-then-falling supply at
max ramp rate; threshold is
VTR_5P0_R or VTR_5P5_R.)
100
–
–
ns Guaranteed by
design
Low-voltage OVD (LV OVD) specifications
SID590 VTR_R_LVOVD
LV OVD rising detection point
for VCCD
LV OVD falling detection point 1.237 1.275 1.313
for VCCD
1.261
1.3
1.339
V
V
SID591 VTR_F_LVOVD
SID595 tDLY_ACT_LVOVD Active mode delay between
VCCD falling/rising through
–
–
1
µs Guaranteed by
design
V
TR_F/R_LVOVD and an internal
LV OVD signal transitioning
SID595A tDLY_DS_LVOVD
DeepSleep mode delay
between VCCD falling/rising
through VTR_F/R_LVOVD and an
internal LV OVD signal transi-
tioning
–
–
12
µs Guaranteed by
design
SID596 tRES_LVOVD
Response time of LV OVD. (For
rising-then-falling supply at
max ramp rate; threshold is
VTR_R_LVOVD.)
100
–
–
ns Guaranteed by
design
Overcurrent detection (OCD) specifications
SID598 IOCD
OCD range for VCCD
156
18
–
–
315
72
mA Guaranteed by
design
mA Guaranteed by
design
SID599 IOCD_DPSLP
OCD range in DeepSleep mode
VDDD
6.0 V
CPU and
Peripherals
CPU and
Peripherals
Regulators
I/O
Regulators
I/O
Reset
By HV O VD
High-Z
HV O VD rising trip
(Default: 5.548 V to
5.892 V)
Norm al
O peration
Norm al
O peration
Enable
Reset
By
XRES_L
Disable
High-Z
HV BO D rising trip
(Default: 2.474 V to
2.627 V)
Reset
By HV BO D
PO R rising trip
(1.5 V to 2.35 V)
Reset
High-Z
By PO R
CM O S threshold
(0.7 V)
Disable
O FF
O FF
-0.3 V
VDDD
XRES_L
LO W Level
HIG H Level
Figure 27-14 Device operations supply range
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
2.3 V
VDDD
tDLY_POR
Internal reset by POR
VDDD
tPOFF
1.45 V
Figure 27-15 POR specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
VDDD, VDDA
VTR_2P7_R or VTR_3P0_R
VTR_2P7_F or VTR_3P0_F
Internal HV BOD signal
tDLY_ACT/DS_HVBOD
tDLY_ACT/DS_HVBOD
VDDD, VDDA
tRES_HVBOD
VTR_2P7_F or VTR_3P0_F
Figure 27-16 High-voltage BOD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
VCCD
VTR_R_LVBOD
VTR_F_LVBOD
Internal LV BOD signal
tDLY_ACT/DS_LVBOD
tDLY_ACT/DS_LVBOD
VCCD
tRES_LVBOD
VTR_F_LVBOD
Figure 27-17 Low-voltage BOD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
VTR_5P0_R or VTR_5P5_R
VTR_5P0_F or VTR_5P5_F
VDDD/VDDA
Internal HV OVD signal
tDLY_ACT/DS_HVOVD
tDLY_ACT/DS_HVOVD
VTR_5P0_R or VTR_5P5_R
tRES_HVOVD
VDDD/VDDA
Figure 27-18 High-voltage OVD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
VTR_R_LVOVD
VTR_F_LVOVD
VCCD
Internal LV OVD signal
tDLY_ACT/DS_LVOVD
tDLY_ACT/DS_LVOVD
VTR_R_LVOVD
tRES_LVOVD
VCCD
Figure 27-19 Low-voltage OVD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
VDDD
LVD rising detection point
LVD falling detection point
Internal LVD signal
tDLY_ACT/DS_LVD
tDLY_ACT/DS_LVD
VDDD
tRES_LVD
LVD falling detection point
Figure 27-20 LVD specifications
27.11
Debug
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
27.11.1
SWD
Table 27-17 SWD interface specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
SID300 fSWDCLK
SID301 tSWDI_SETUP
SID302 tSWDI_HOLD
SID303 tSWDO_VALID
SID304 tSWDO_HOLD
Parameter
Description
SWD clock input frequency
SWDI setup time
SWDI hold time
SWDO valid time
Min
–
0.25 × T
0.25 × T
Typ
–
–
–
–
Max Units Details/conditions
10
–
–
MHz 2.7 V ≤ VDDD ≤ 5.5 V
ns T = 1 / fSWDCLK
ns T = 1 / fSWDCLK
–
1
0.5 × T ns T = 1 / fSWDCLK
ns T = 1 / fSWDCLK
SWDO hold time
–
–
Datasheet
130
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.11.2
JTAG
Table 27-18 JTAG AC specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
Parameter
Description
TCK HIGH time
TCK LOW time
Min
30
30
66.7
12
12
–
Typ
–
–
–
–
–
–
–
–
Max Units Details/conditions
SID620 tJCKH
SID621 tJCKL
SID622 tJCP
SID623 tJSU
SID624 tJH
SID625 tJZX
SID626 tJXZ
SID627 tJCO
–
–
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
TCK clock period
–
–
–
TDI/TMS setup time
TDI/TMS hold time
TDO High-Z to active
TDO active to High-Z
TDO clock to output
30
30
30
–
–
tJCKH
tJCP
tJCKL
TCK
tJH
tJSU
TDI/TMS
TDO
tJCO
tJXZ
tJZX
Figure 27-21 JTAG timing diagram
27.11.3
Trace
Table 27-19 Trace specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
SID1412A CTRACE
SID1412 tTRACE_CYC
Parameter
Description
Trace Capacitive Load
Trace clock period
Min
–
40
Typ
–
–
Max Units Details/conditions
30
–
pF
ns Trace clock cycle
time for 25 MHz
SID1413 tTRACE_CLKL
SID1414 tTRACE_CLKH
Trace clock LOW pulse width
Trace clock HIGH pulse width
2
2
3
2
–
–
–
–
–
–
–
–
ns Clock low pulse
width
ns Clock high pulse
width
ns Trace data setup
time
ns Trace data hold time
SID1415A tTRACE_SETUP Trace data setup time
SID1416A tTRACE_HOLD
Trace data hold time
Datasheet
131
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.12
Clock specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
The following is a basic requirement on the clock frequency dependency of the cores: Cortex®-M0+ core should
run at an integer divider from the Cortex®-M4 core clock.
Example combinations are listed in the Table 27-20.
Table 27-20 Root and intermediate clocks[56]
Max frequency
Clock
CLK_HF0
CLK_HF1
Description
(MHz)
80
Root clock for CPUSS, PERI
Event generator (CLK_REF), Clock output on EXT_CLK pins (when used as
output)
80
CLK_HF2
2
CSV
CLK_FAST
80
Generated by dividing CLK_HF0, intermediate clock for CM4
Generated by clock gating CLK_PERI, intermediate clock for CM0+, Crypto,
P-DMA, M-DMA
Generated by clock gating CLK_HF0, intermediate clock for LIN, SCB, PASS,
CAN, TCPWM, IOSS, CPU trace
CLK_SLOW
CLK_PERI
80
80
Table 27-21 IMO AC specifications
Spec ID
SID310 fIMOTOL
SID311 tSTARTIMO
Parameter
Description
IMO operating frequency
IMO startup time
Min
7.92
–
Typ
8
–
Max Units Details/conditions
8.08
7.5
MHz
µs Startup time to 90%
of final frequency
SID312 IIMO_ACT
IMO current
–
13.5
22
µA Guaranteed by
design
Table 27-22 ILO AC specifications
Spec ID
SID320 fILOTRIM
SID321 tSTARTILO
Parameter
Description
ILO operating frequency
ILO startup time
Min
Typ
Max Units Details/conditions
31.1296 32.768 34.4064 kHz
–
8
12
µs Startuptimeto90% of
final frequency
SID323 IILO
ILO current
–
500
2800
nA Guaranteed by design
Note
56.Intermediate clocks that are not listed have the same limitations as that of their parent clock.
Datasheet
132
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-23 ECO specifications
Spec ID
SID330 fECO
SID332 RFDBK
Parameter
Description
Crystal frequency range
Feedback resistor value.
Min: RTRIM = 3; Max: RTRIM =
0 with 100 kΩ step size on
RTRIM
Min
3.988
100
Typ
–
–
Max Units Details/conditions
33.34 MHz
400
2000
10
kΩ Guaranteed by design
SID333 IECO3
ECO current at TJ = 150 °C
–
–
–
–
µA Maximum operation
current with a 33-MHz
crystal, max 18-pF
load
SID334 tSTART_4M
4-MHz ECO startup time[57]
ms Time from set
CLK_ECO_-
CONFIG.ECO_EN to 1
until
CLK_ECO_STATUS.EC
O_READY is set to 1
(See Clock Timing
Diagrams)
SID335 tSTART_33M
33-MHz ECO startup time[57]
–
–
1
ms Time from set
CLK_ECO_-
CONFIG.ECO_EN to 1
until
CLK_ECO_STATUS.EC
O_READY is set to 1
(See Clock Timing
Diagrams)
VDDD
MCU
ITrim
Rf
RTrim
ECO_IN: External crystal oscillator input pin
ECO_OUT: External crystal oscillator output pin
C1, C2: Load Capacitors
C3*, C4*: Stray Capacitance of the PCB
ECO_IN
VSSD
C1
C2
C3*
C4*
GTrim
VSSD
ECO_OUT
Rd
0R
Rd
FTrim
Figure 27-22 ECO connection scheme[58]
Notes
57.Mainly depends on the external crystal.
58.Refer to the family-specific Architecture TRM for more information on crystal requirements (002-19314, TRAVEO™ T2G Automotive
MCU body controller entry architecture technical reference manual).
Datasheet
133
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-24 PLL specifications
Spec ID Parameter
SID340 PLL_LOCK
SID341A fPLL_OUT
Description
Time to achieve PLL lock
Output frequency from PLL
block
Min
–
11
Typ
–
–
Max Units Details/conditions
35
80
µs
MHz
SID342 PLL_LJIT1
SID343 PLL_LJIT2
SID344 PLL_LJIT3
SID345A PLL_LJIT5
Long term jitter
Long term jitter
Long term jitter
Long term jitter
PLL input frequency
–0.25
–
–
–
–
0.25
ns For 125 ns
fPLL_VCO: 320 MHz
fPLL_OUT: 40 MHz to 80 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
–0.5
0.5
ns For 500 ns
f
PLL_VCO: 320 MHz
fPLL_OUT: 40 MHz to 80 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
–0.5
0.5
ns For 1000 ns
f
PLL_VCO: 320 MHz
fPLL_OUT: 40 MHz to 80 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
–0.75
0.75
ns For 10000 ns
f
PLL_VCO: 320 MHz
fPLL_OUT: 40 MHz to 80 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
SID346 fPLL_IN
SID347 IPLL_320M1
3.988
–
–
740
33.34 MHz
PLL operating current
(fOUT = 80 MHz)
1110
1125
1125
780
µA fIN = 4 MHz,
fPFD = 4 MHz,
fVCO = 320 MHz,
fOUT = 80 MHz
SID347A IPLL_320M2
SID347B IPLL_320M3
SID348 IPLL_80M1
SID348A IPLL_80M2
SID348B IPLL_80M3
PLL operating current
(fOUT = 80 MHz)
–
–
–
–
–
750
750
520
530
530
µA
fIN = 8 MHz,
fPFD = 8 MHz,
fVCO = 320 MHz,
fOUT = 80 MHz
PLL operating current
(fOUT = 80 MHz)
µA fIN = 16 MHz,
fPFD = 8 MHz,
fVCO = 320 MHz,
fOUT = 80 MHz
PLL operating current
(fOUT = 80 MHz)
µA fIN = 4 MHz,
fPFD = 4 MHz,
fVCO = 240 MHz,
fOUT = 80 MHz
PLL operating current
(fOUT = 80 MHz)
795
µA fIN = 8 MHz,
fPFD = 8 MHz,
fVCO = 240 MHz,
fOUT = 80 MHz
PLL operating current
(fOUT = 80 MHz)
795
µA
fIN = 16 MHz,
fPFD = 8 MHz,
fVCO = 240 MHz,
f
OUT = 80 MHz
Datasheet
134
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-24 PLL specifications (continued)
Spec ID Parameter
SID348C fPLL_VCO
SID349C fPLL_PFD
Description
VCO frequency
PFD frequency
Min
170
3.988
Typ
–
–
Max Units Details/conditions
400 MHz
8
MHz
Table 27-25 FLL specifications
Spec ID Parameter
Description
FLL wake up time
Min
Typ
Max Units Details/conditions
SID350A tFLL_WAKE_A
–
–
3.5
µs Wakeup with < 10 °C
temperature change
while in DeepSleep.
fFLL_IN = 8 MHz,
f
FLL_OUT = 80 MHz,
Time from stable
reference clock until
FLL frequency is
within 5% of final
value
SID351 fFLL_OUT
SID352 FLL_CJIT
Output frequency from FLL
block
24
–1
–
–
80
1
MHz Output range of FLL
divided-by-2 output
FLL frequency accuracy
%
This is added to the
error of the source
SID353 fFLL_IN
SID354 IFLL
Input frequency
0.25
–
–
80
MHz
FLL operating current
250
360
µA Reference clock: IMO,
CCO frequency: 160
MHz, FLL frequency:
80 MHz, guaranteed
by design
Datasheet
135
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
VDDD
MCU
Rf
WCO_IN: Watch crystal oscillator input pin
WCO_OUT: Watch crystal oscillator output pin
C1, C2: Load Capacitors
WCO_IN
VSSD
C3*, C4*: Stray Capacitance of the PCB
C1
C2
C3*
C4*
VSSD
WCO_OUT
Rd
0R
Figure 27-23 WCO connection scheme[60]
Table 27-26 WCO specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/conditions
SID360 fWCO
Watch Crystal frequency
–
32.768
–
kHz Maximum drive level:
0.5 µW
SID361 WCO_DC
SID362 tSTART_WCO
WCO duty cycle
WCO start up time[59]
10
–
–
–
90
%
1000
ms For Grade-S devices
Time from set
CTL.WCO_EN to 1
until
STATUS.WCO_OK is
set to 1. (See Clock
Timing Diagrams)
SID362E tSTART_WCOE
WCO start up time[59]
–
–
–
1400
ms For Grade-E devices
Time from set
CTL.WCO_EN to 1
until
STATUS.WCO_OK is
set to 1. (See Clock
Timing Diagrams)
SID363 IWCO
WCO current
1.4
–
µA
Table 27-27 External clock input specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
SID366 fEXT
External clock input
frequency
0.25
–
80
MHz For EXT_CLK pin (all
input level settings:
CMOS, TTL,
Automotive)
SID367 EXT_DC
External clock duty cycle
45
–
55
%
Notes
59.Mainly depends on the external crystal.
60.Please refer to family specific Architecture TRM for more information on crystal requirements (002-19314, TRAVEO™ T2G Automotive
MCU body controller entry architecture technical reference manual).
Datasheet
136
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
27.12.1
Clock timing diagrams
ECO: 4 MHz
PLL: 80 MHz
FLL: 80 MHz
CLK_ECO_STATUS.ECO_EN
Active
4 MHz
ECO_OUT
CLK_ECO_STATUS.ECO_READY
10 ms
CLK_PLL_CONFIG.ENABLE
CLK_PLL_STATUS.LOCKED
80 MHz
35 µs
PLL_OUTPUT
CLK_FLL_CONFIG.FLL_ENABLE
CLK_FLL_STATUS.LOCKED
CCO is already up-and-running
3.5 µs
80 MHz
FLL_OUTPUT
Figure 27-24 ECO to PLL or FLL diagram
Datasheet
137
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
WCO: 32.768 kHz
FLL: 80 MHz
CTL.WCO_EN
Active
32.768 kHz
WCO_OUT
STATUS.WCO_OK
1000 ms
CLK_FLL_CONFIG.FLL_ENABLE
CLK_FLL_STATUS.LOCKED
CCO is already up-and-running
3.5 µs
80 MHz
FLL_OUTPUT
Figure 27-25 WCO to FLL diagram
Table 27-28 MCWDT timeout specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/conditions
SID410 tMCWDT1
Minimum MCWDT timeout
58.12
–
–
µs When using the ILO
(32.768 kHz + 5%) and
16-bit MCWDT counter
Guaranteed by design
SID411 tMCWDT2
Maximum MCWDT timeout
–
–
2.11
s
When using the ILO
(32.768 kHz – 5%) and
16-bit MCWDT counter
Guaranteed by design
Datasheet
138
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Electrical specifications
Table 27-29 WDT timeout specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/conditions
SID412 tWDT1
SID413 tWDT2
SID414 tWDT3
Minimum WDT timeout
58.12
–
–
38.33
–
µs When using the ILO
(32.768 kHz + 5%) and
32-bit WDT counter
Guaranteed by design
Maximum WDT timeout
Default WDT timeout
–
–
–
h
When using the ILO
(32.768 kHz – 5%) and
32-bit WDT counter
Guaranteed by design
1000
ms When using the ILO
and 32-bit WDT
counter at 0x8000
(default value),
guaranteed by design
Datasheet
139
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2022-10-07
28
Ordering information
The CYT2B6 microcontroller part numbers and features are listed in Table 28-1. The Arm® TAP JTAG ID is 0x6BA0 0477.
Table 28-1
CYT2B6 ordering information[61]
[62]
[62]
[63]
[64]
[65]
[66]
[67]
CYT2B63BAS
CYT2B63BAE
CYT2B63BADQ0AZSGS
CYT2B63BADQ0AZEGS
CYT2B63CADQ0AZSGS
CYT2B63CADQ0AZEGS
CYT2B64BADQ0AZSGS
CYT2B64BADQ0AZEGS
CYT2B64CADQ0AZSGS
CYT2B64CADQ0AZEGS
CYT2B65BADQ0AZSGS
CYT2B65BADQ0AZEGS
CYT2B65CADQ0AZSGS
CYT2B65CADQ0AZEGS
64-LQFP
576
576
64
64
64
64
64
64
64
64
64
64
64
64
64
64
22
22
22
22
28
28
28
28
32
32
32
32
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
3
3
3
3
4
4
4
4
4
4
4
4
eSHE
eSHE
HSM
HSM
eSHE
eSHE
HSM
HSM
eSHE
eSHE
HSM
HSM
S
E
0x2E349069
64-LQFP
64-LQFP
64-LQFP
80-LQFP
80-LQFP
80-LQFP
80-LQFP
100-LQFP
100-LQFP
100-LQFP
100-LQFP
0x2E349069
0x2E349069
0x2E349069
0x2E351069
0x2E351069
0x2E351069
0x2E351069
0x2E359069
0x2E359069
0x2E359069
0x2E359069
CYT2B63CAS
CYT2B63CAE
576
576
576
576
576
576
576
576
576
576
64
64
64
64
64
64
64
64
64
64
S
E
S
E
S
E
S
E
S
E
[62]
CYT2B64BAS
CYT2B64BAE
[62]
CYT2B64CAS
CYT2B64CAE
[62]
CYT2B65BAS
CYT2B65BAE
[62]
CYT2B65CAS
CYT2B65CAE
Notes
61.Supported shipment types are “Tray” (default) and “Tape and Reel”. Add the character ‘T’ at the end to get the ordering code for “Tape and Reel” shipment type.
62.3DES/SHA-1/SHA-2/SHA-3/CRC/Vector unit for asymmetric cryptography features are not supported.
63.Code-flash size 576 KB = 32 KB × 14 (Large Sectors) + 8 KB × 16 (Small Sectors)
64.Work-flash size 64 KB = 2 KB × 24 (Large Sectors) + 128 B × 128 (Small Sectors).
65.S-grade Temperature (–40 °C to 105 °C).
66.E-grade Temperature (–40 °C to 125 °C).
67.JTAG ID CODE bits 12 through 27, represents the Silicon ID of the device.
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Ordering information
28.1
Part number nomenclature
Table 28-2
Device code nomenclature
Field Description
Value
Meaning
CY
T
Cypress Prefix
Category
CY
T
TRAVEO™
2
B
Family Name
Application
2
B
TRAVEO™ T2G (Core M4)
Body
Code-flash/Work-flash/SRAM
quantity
576 KB / 64 KB / 64 KB
D
P
6
3
4
5
B
C
A
S
E
64-LQFP
80-LQFP
100-LQFP
eSHE – on, HSM – off, RSA - 2K
eSHE – on, HSM – on, RSA - 2K
No options
S-grade (–40 °C to 105 °C)
E-grade (–40 °C to 125 °C)
Packages
H
I
Hardware Option
Marketing Option
Temperature Grade
C
Table 28-3
Ordering code nomenclature
Field Description
Value
Meaning
CY
T
Cypress Prefix
Category
CY
T
TRAVEO™
2
B
Family Name
Application
2
B
TRAVEO™ T2G (Core M4)
Body
Code-flash/Work-flash/SRAM
quantity
576 KB / 64 KB / 64 KB
D
P
6
3
4
64 LQFP
80 LQFP
Packages
5
100 LQFP
B
C
A
D
Q
0
AZ
S
E
ES
GS
Blank
T
eSHE – on, HSM – off, RSA - 2K
eSHE – on, HSM – on, RSA - 2K
No options
First revision
UMC (Fab 12i) Singapore
Reserved
H
Hardware Option
I
Marketing Option
Revision
Fab Location
Reserved
R
F
X
K
Package Code
LQFP
S-grade (–40 °C to 105 °C)
E-grade (–40 °C to 125 °C)
Engineering samples
Standard grade of automotive
Tray shipment
C
Q
S
Temperature Grade
Quality Grade
Shipment Type
Tape and Reel shipment
Datasheet
141
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Packaging
29
Packaging
CYT2B6 is offered in the packages listed in the Table 29-1.
Table 29-1
Package information
Contact/
[72]
Package
Dimensions
Coefficient of thermal expansion
I/O pins
Lead pitch
[70]
[71]
100-LQFP
80-LQFP
64-LQFP
14 × 14 × 1.7 mm (max)
12 × 12 × 1.7 mm (max)
10 × 10 × 1.7 mm (max)
0.5 mm
0.5 mm
0.5 mm
a1 = 8.5 ppm/°C, a2 = 33.6 ppm/°C
78
63
49
[70]
[71]
a1 = 8.5 ppm/°C, a2 = 33.5 ppm/°C
[70]
[71]
a1 = 8.5 ppm/°C, a2 = 33.2 ppm/°C
Table 29-2
Parameter
Package characteristics
Description
Conditions
S-grade
E-grade
–
Min
–40
–40
–
Typ
–
Max
105
125
150
37.6
32.7
29.8
32.0
26.7
21.3
7.8
Units
°C
T
T
Operating ambient temperature
Operating ambient temperature
Operating junction temperature
A
–
°C
A
T
–
°C
J
64 LQFP
80 LQFP
100 LQFP
64 LQFP
80 LQFP
100 LQFP
64 LQFP
80 LQFP
100 LQFP
–
–
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
Package thermal resistance,
R
–
–
[68, 69]
θJA
θJB
θJC
junction to ambient θ
JA
–
–
–
–
R
R
Package θ
–
–
JB
–
–
–
–
Package thermal resistance,
junction to case θ
–
–
6.6
JC
–
–
5.6
Table 29-3
Package
Solder reflow peak temperature, package moisture sensitivity level (MSL), IPC/JEDEC
J-STD-2
Maximum time at peak temperature
Maximum peak temperature (°C)
MSL
(seconds)
30 seconds
30 seconds
30 seconds
100 LQFP
80 LQFP
64 LQFP
260
260
260
3
3
3
Notes
68.Board condition complies to JESD51-7(4 Layers).
69.Maximum value °C/Watt shown is for TA = 125 °C.
70.a1 = CTE (Coefficient of Thermal Expansion) value below Tg (ppm/°C) (Tg is glass transition temperature which is 131°C).
71.a2 = CTE value above Tg (ppm/°C).
72.The numbers are estimated values based simulation only and are based on a single bill of material combination per package type.
Datasheet
142
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Packaging
4
4
5
D
D
5
7
7
D1
D1
75
51
51
75
76
50
50
76
E1
E1
E
E
5
5
4
4
7
7
3
6
100
26
26
100
1
1
25
25
2
5
7
e
0.10
C
A-B
D
3
BOTTOM VIEW
0.20
C A-B D
b
8
0.08
C
A-B
D
TOP VIEW
2
A
9
A
SEATING
PLANE
c
0.25
A1
A'
b
0.08
C
L1
10
SECTION A-A'
L
SIDE VIEW
DETAIL A
NOTES :
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE MOLD PARTING
LINE COINCIDENT WITH WHERE THE LEAD EXITS THE BODY.
3. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H.
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
4. TO BE DETERMINED AT SEATING PLANE C.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.25mm PRE SIDE.
DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE H.
6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED.
c
D
16.00 BSC
14.00 BSC
0.50 BSC
D1
e
E
16.00 BSC
14.00 BSC
7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOWER BODY
SECTIONS. DIMENSIONS D1 AND E1 ARE DETERMINED AT THE LARGEST
FEATURE OF THE BODY EXCLUSIVE OF MOLD FLASH AND GATE BURRS.
BUT INCLUDING ANY MISMATCH BETWEEN THE UPPER AND LOWER
SECTIONS OF THE MOLDER BODY.
8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR
PROTRUSION (S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED b
MAXIMUM BY MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE LEAD FOOT.
E1
L
0.45 0.60 0.75
1.00 REF
L1
9. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP.
002-11500 *B
10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO
THE LOWEST POINT OF THE PACKAGE BODY.
Figure 29-1
100-LQFP package outline
Datasheet
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Based on Arm® Cortex®-M4 dual
Packaging
4
D
D1
5
7
60
41
41
60
61
40
40
61
5
7
E1
E
4
3
6
80
21
21
80
1
20
20
1
2
5
7
D
0.10
C
C
A-B D
BOTTOM VIEW
3
e
0.08
A-B
D
b
0.20
C A-B D
8
TOP VIEW
2
A
A
SEATING
PLANE
9
c
A'
0.25
0.08
C
A1 10
L1
b
L
SIDE VIEW
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
c
D
14.00 BSC.
D1
e
12.00 BSC.
0.50 BSC
E
14.00 BSC.
E1
L
12.00 BSC.
0.45 0.60 0.75
1.00 REF
L1
002-11501 *A
Figure 29-2
80-LQFP package outline
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Packaging
4
D
D1
5
7
48
33
33
48
32
32
49
49
5
7
E1
E
4
3
6
17
17
64
64
1
16
16
1
2
5
7
e
A-B D
3
0.10
0.08
C
A-B
D
BOTTOM VIEW
0.20
C
C
A-B
D
8
b
TOP VIEW
2
A
9
c
A
SEATING
PLANE
b
0.25
A1
A'
SECTION A-A'
0.08
C
L1
10
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.2
0.20
12.00 BSC.
7
c
D
D1
e
10.00 BSC.
0.50 BSC
E
12.00 BSC.
E1
L
10.00 BSC.
0.45 0.60 0.75
1.00 REF
L1
002-11499 *A
Figure 29-3
64-LQFP package outline
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Appendix
30
Appendix
30.1
Bootloading or End-of-line Programming
• Triggered at device startup, if a trigger condition is applied
• Either CAN or LIN communication may be used
• Bootloader polls for the communication on CAN or LIN at separate time frames, until the overall 300-second
timeout is reached
• If a bootloader command is received on either communication interface, the polling stops and bootloader starts
using this interface
150 ms
10 ms
10 ms
CAN,
100 Kbps
Polling
CAN,
500 Kbps
Polling
LIN,
20 Kbps
Polling
CAN,
100 Kbps
Polling
Bootloader
Stopped
….
Overall bootloading time, if no communication ( 300 s)
Figure 30-1
Table 30-1
Bootloading sequence
CAN interface details
Sl. No.
CAN interface
Configuration
1
2
3
4
5
6
7
8
9
CAN Mode
CAN Instance
CAN TX
CAN RX
CAN Transceiver NSTB / EN (Low)
CAN Transceiver EN / EN (High)
CAN RX Message ID
CAN TX Message ID
Baud
Classic CAN
CAN0, Channel#1
P0.2 / CAN0_1_TX
P0.3 / CAN0_1_RX
P23.3 (optional)
P2.1 (optional)
0x1A1
0x1B1
100 or 500 kbps alternating
VSS
CAN
Transceiver
TRAVEOTM T2G MCU
EN (Low)
NSTB
EN
EN (High)
TX
TX
RX
RX
Figure 30-2
MCU to CAN transceiver connections
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Appendix
Table 30-2
LIN interface details
LIN interface
Sl. No.
Configuration
1
2
LIN Type
LIN Mode
LIN0, Channel#1
Slave
3
4
LIN Checksum Type
LIN TX
Classic
P0.1 / LIN1_TX
P0.0 / LIN1_RX
P2.1 (optional)
P23.3 (optional)
0x46
5
6
7
8
LIN RX
LIN EN / EN (High)
LIN EN (Low)
LIN TX PID
9
LIN RX PID
0x45
10
11
12
Baud
20 or 115.2 kbps
11
1 bit
Break Field Length
Break Delimiter Length
VDDD / VDDIO
LIN
Transceiver
TRAVEOTM T2G MCU
EN (Low)
EN (High)
EN
TX
RX
TX
RX
Figure 30-3
MCU to LIN transceiver connections
30.2
External IP revisions
Table 30-3
IP revisions
Module
IP
Revision
M_TTCAN IP revision: Rev.3.2.3
Cortex-M0+-r0p1
Vendor
Bosch
CANFD
mxttcanfd
armcm0p
Arm® Cortex®-M0+
Arm® Cortex®-M4
Arm® Coresight
Arm®
Arm®
Arm®
armcm4
Cortex-M4-r0p1
armcoresighttk
CoreSight-SoC-TM100-r3p2
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Acronyms
31
Acronyms
Table 31-1
Acronyms used in the document
Acronym
A/D
Description
Analog to Digital
Acronym
JTAG
Description
Joint test action group
Low drop out regulators
ABS
Absolute
LDO
ADC
Analog to Digital converter
LIN
Local Interconnect Network, a
communications protocol
AES
Advanced encryption standard
LVD
OTA
Low voltage detection
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus,
Arm® data transfer bus
Over-the-air programming
Arm®
Advanced RISC machine, a CPU archi-
tecture
OTP
One-time programmable
Over voltage detection
ASIL
BOD
Automotive safety integrity level
Brown-out detection
OVD
P-DMA
Peripheral-Direct Memory Access
same as DW
CAN FD
CMOS
Controller Area Network with Flexible
Data rate
PLL
Phase Locked Loop
Complementary metal-oxide-semicon-
ductor
POR
Power-on reset
CPU
CRC
Central Processing Unit
PPU
Peripheral protection unit
Cyclic redundancy check, an
error-checking protocol
PRNG
Pseudorandom number generator
CSV
CTI
Clock supervisor
PWM
Pulse-width modulation
Microcontroller Unit
Cross trigger interface
Data encryption standard
Design-For-Test
MCU
DES
DFT
DW
MCWDT
M-DMA
MISO
Multi-counter watchdog timer
Memory-Direct Memory Access
SPI Master-in slave-out
Memory mapped I/O
Datawire same as P-DMA
ECC
Error correcting code/Elliptical curve
cryptography
MMIO
ECO
ETM
External crystal oscillator
Embedded Trace Macrocell
MOSI
MPU
MTB
MUL
MUX
NVIC
RAM
RISC
ROM
RSA
SPI Master-out slave-in
Memory protection unit
Micro trace buffer
EVTGEN Event Generator
FLL
Frequency Locked Loop
Multiplier
FPU
GHS
GPIO
HSM
I/O
Floating point unit
Multiplexer
Green Hills tool chain with Multi IDE
General purpose input/output
Hardware security module
Input/output
Nested vectored interrupt controller
Random access memory
Reduced-instruction-set computing
Read only memory
I2C
Inter-Integrated Circuit, a communica-
tions protocol
Rivest-Shamir-Adleman Public Key
Encryption Algorithm
ILO
Internal low-speed oscillator
RTC
Real-time clock
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Based on Arm® Cortex®-M4 dual
Acronyms
Table 31-1
Acronyms used in the document (continued)
Description Acronym
Internal main oscillator
Acronym
IMO
Description
Successive approximation register
Serial communication block
I2C serial clock
SAR
IOSS
IPC
Input/output sub-system
Inter-processor communication
Infrared interface
SCB
SCL
IrDA
SDA
I2C serial data
IRQ
Interrupt request
SECDED
Single error correction, double error
detection
SHA
SHE
SMPU
SPI
Secure hash algorithm
TCPWM
TTL
Timer/Counter Pulse-width modulator
Transistor-transistor logic
Secure hardware extension
Shared memory protection unit
TRNG
True random number generator
Serial peripheral interface, a communica- UART
tions protocol
Universal Asynchronous Transmitter
Receiver
SRAM
SWD
SWJ
Static random access memory
Serial wire debug
WCO
WDT
Watch crystal oscillator
Watchdog timer reset
Serial wire JTAG
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Based on Arm® Cortex®-M4 dual
Errata
32
Errata
This section describes the errata for the CYT2B6 product family. Details include errata trigger conditions, scope
of impact, available workaround, and silicon revision applicability. Contact your local Infineon Sales Represen-
tative if you have questions.
Part numbers affected
Part numbers
All CYT2B6 parts
CYT2B6 qualification status
Production samples
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Errata
CYT2B6 errata summary
The following table defines the errata applicability to available CYT2B6 family devices.
Items
Errata ID
CYT2B6
Silicon rev.
Fix status
[1.] Crypto LSL1, LSR1, LSL1_WITH_CARRY, & LSR1_WITH_CARRY
No silicon fix planned.
Use workaround.
53
instructions may work incorrectly in certain scenarios
No silicon fix planned.
Use workaround.
[2] Crypto MEM_BUF may be corrupted
42
67
68
69
96
[3] ConfigureFmInterrupt API assumes a parameter with 8 bytes
No silicon fix planned.
Use workaround.
boundary, but actual boundary is 4 bytes
No silicon fix planned.
Use workaround.
[4] SMPU/MPU/PPU protection region size is limited to 2 GB
[5] DirectExecute API may return error if called with arguments placed
No silicon fix planned.
Use workaround.
in SRAM memory
No silicon fix planned.
Use workaround.
[6] CAN FD RX FIFO top pointer feature does not function as expected
[7] CAN FD debug message handling state machine does not reset to
No silicon fix planned.
Use workaround.
97
98
Idle state when CANFD_CH_CCCR.INIT is set
[8] TPIU peripheral ID mismatch
No fix planned
No silicon fix planned.
Use workaround
[9] Limitation of the memory hole in SCB register space
124
CYT2B63BADQ0AZSGS
CYT2B63BADQ0AZEGS
CYT2B63CADQ0AZSGS
CYT2B63CADQ0AZEGS
CYT2B64BADQ0AZSGS
CYT2B64BADQ0AZEGS
CYT2B64CADQ0AZSGS
CYT2B64CADQ0AZEGS
CYT2B65BADQ0AZSGS
CYT2B65BADQ0AZEGS
CYT2B65CADQ0AZSGS
CYT2B65CADQ0AZEGS
No silicon fix planned.
Use workaround
[10] WDT service can be missed
129
147
[11] CAN FD controller message order inversion when transmitting
from dedicated Tx Buffers configured with same Message ID
No silicon fix planned.
Use workaround
D
[12] CAN FD incomplete description of Dedicated Tx buffers and Tx
Queue related to transmission from multiple buffers configured with
the same Message ID
No silicon fix planned.
Use workaround. TRM
was updated.
167
[13] Misleading status is returned for Flash and eFuse system calls, if
there are pending NC ECC faults in SRAM controller #0
No silicon fix planned.
TRM will be updated.
175
176
185
No silicon fix planned.
TRM will be updated.
[14] WDT reset causes loss of SRAM retention
[15] Crypto ECC errors may be set after boot with application authen-
No silicon fix planned.
TRM will be updated.
tication
Will be fixed to update
the Flash settings, via
Manufacturing
Test
Program Update for
Code Flash setting; this
fix is transferred to
TRAVEO™ T2G devices
during Infineon Factory
Test Flow. Fixed devices
will be identified by
Device Date Code, which
is marked on every
TRAVEO™ T2G device.
[16]Incomplete erase of Code Flash cells could happen Erase Suspend
/ Erase Resume is used along with Erase Sector operation in
Non-Blocking mode
198
199
[17]Limitation for keeping the port state from peripheral IP after
wakeup from DeepSleep
No silicon fix planned.
TRM will be updated.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Errata
1. Crypto LSL1, LSR1, LSL1_WITH_CARRY, & LSR1_WITH_CARRY instructions may work incorrectly in certain scenarios
Problem definition
LSL1, LSR1, LSL1_WITH_CARRY, and LSR1_WITH_CARRY instructions should ignore the value in IW[3:0]
(shift by 1 instruction does not use these fields). But because of a HW issue, shift does not work if the
register data field pointed by IW[3:0] is ‘0’ (destination data is same as source data).
Parameters affected
Trigger condition(s)
Scope of impact
Workaround
NA
Using LSL1, LSR1, LSL1_WITH_CARRY, and LSR1_WITH_CARRY instructions
The shift does not happen (destination data is same as source data).
IW[3:0] should be pointed to a dummy register where the data field of the register is a non-zero value
(rsrc0->data[12:0]).
Since the stack pointer (r15) points to a non-zero value (to use the LSL1 instruction, you must have
allocated at least one register, so that SP will not be zero), it is safe to use r15 as rsrc0.
static __forceinline void LSL1 (int rdst, int rsrc1)
{
AHB_WRITE_W (MMIO_CRYPTO_INSTR_FF_WR, (CRYPTO_VU_LSL_OPC << 24)
| (rdst << 12)
| (rsrc1 << 4)
| 15);
}
This software workaround applies to other instructions such as LSR1, LSL1_WITH_CARRY & LSR1_WITH_-
CARRY as well.
Fix status
No silicon fix planned. Use workaround.
2. Crypto MEM_BUF may be corrupted
Problem definition
The SRAM in the Crypto block is 8 KB but the address decode is wired to create four 8-KB images of the
SRAM within a 32-KB address space. Writes to memory space above the initial 8-KB image will corrupt SRAM
contents.
Parameters affected
Trigger condition(s)
Scope of impact
Workaround
NA
Any write to address between 0x40108000 and 0x4010FFFF.
CRYPTO MEM_BUF may be corrupted.
The software should ensure that there is no access beyond 8 KB MEM_BUF address range from either MMIO
writes or address overflows while executing Crypto operations.
Fix status
No silicon fix planned. Use workaround.
3. ConfigureFmInterrupt API assumes a parameter with 8 bytes boundary, but actual boundary is 4 bytes
Problem definition
STATUS_ADDR_PROTECTED will be returned if the ConfigureFmInterrupt API is called with arguments stored
in SRAM with 4-byte boundary (available SRAM or protected boundary SRAM).
Parameters affected
Trigger condition(s)
NA
Call ConfigureFmInterrupt API with arguments stored in SRAM at 4 bytes boundary of available SRAM or
protected boundary of SRAM.
Scope of impact
Workaround
Fix status
ConfigureFmInterrupt API will fail by returning STATUS_ADDR_PROTECTED error status when called with
argument having 4 bytes boundary of available SRAM or protected boundary of SRAM.
Allow 4 bytes margin (that is, assume that the API parameter size is 8 and store the arguments) for ConfigureF-
mInterrupt API parameter.
No silicon fix planned. Use workaround.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Errata
4. SMPU/MPU/PPU protection region size is limited to 2 GB
Problem definition
If SMPU/MPU/PPU protection block size is configured for 4 GB (PROT_SMPU_SMPU_-
STRUCT_ATT0.REGION.SIZE = 31), then during protection check in SROM, the value of the internal uint32
variable will overflow (4G = 0x1 0000 0000). Therefore, SROM assumes the protection size equals zero, and no
protection will be applied.
Parameters affected
Trigger condition(s)
Scope of impact
NA
Configure SMPU/MPU/PPU to protect with region size equal to 4 GB or the region size with value 31u.
If SMPU/MPU/PPU is configured to protect region size of 4 GB, then SROM software does not apply any
protection as per the request.
Workaround
Fix status
Use two protection blocks of region size equal to 2 GB if 4-GB region size protection is required.
No silicon fix planned. Use workaround.
5. DirectExecute API may return error if called with arguments placed in SRAM memory
Problem definition
If DirectExecute API is called in the master PC (other than PC0 or PC1) with arguments in
SRAM_SCRATCH_ADDR, then the API will return STATUS_ADDR_PROTECTED status.
Parameters affected
Trigger condition(s)
Scope of impact
NA
Call DirectExecute API with arguments in SRAM_SCRATCH_ADDR and master PC configured > 1.
DirectExecute API, if called with master PC configured > 1 and arguments in SRAM_SCRATCH_ADDR, the API
will return STATUS_ADDR_PROTECTED.
Workaround
Fix status
Call DirectExecute API with master PC0 or PC1, if arguments are stored in SRAM memory.
No silicon fix planned. Use workaround.
6. CAN FD RX FIFO top pointer feature does not function as expected
Problem definition
The RX FIFO top pointer function calculates the address for received messages in Message RAM by hardware.
This address should restart from the start address after reading all messages of RX FIFO n size (n: 0 or 1).
However, the address does not restart from the start address when the RX FIFO n size is set to 1
(CANFD_CH_RXFnC.FnS = 0x01). This results in CPU/DMA reading messages from the wrong address in
Message RAM.
Parameters affected
Trigger condition(s)
NA
RX FIFO top pointer function is used when RX FIFO n size is set to 1 element
(CANFD_CH_RXFnC.FnS = 0x01).
Scope of impact
Workaround
Received message cannot be correctly read by using the RX FIFO top pointer function, when the RX FIFO n
size is set to 1 element.
Any of the following.
1) Set RX FIFO n size to 2 or more when using the RX FIFO top pointer function.
2) Do not use the RX FIFO top pointer function when RX FIFO n size is set to 1 element. Instead of reading
received messages from the RX FIFO top pointer, read directly from the Message RAM.
Fix status
No silicon fix planned. Use workaround.
Datasheet
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Based on Arm® Cortex®-M4 dual
Errata
7. CAN FD debug message handling state machine does not reset to Idle state when CANFD_CH_CCCR.INIT is set
Problem definition
If either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN module enters BusOff state,
the debug message handling state machine stays in its current state instead of being reset to Idle state. Config-
uring the CANFD_CH_CCCR.CCE bit does not change CANFD_CH_RXF1S.DMS.
Parameters affected
Trigger condition(s)
Scope of impact
NA
Either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN module enters BusOff state.
The errata is limited to the use case when the Debug on CAN functionality is active. Normal operation of the
CAN module is not affected, in which case the debug message handling state machine always remains in Idle
state. In the described use case, the debug message handling state machine is stopped and remains in the
current state signaled by the CANFD_CH_RXF1S.DMS bit. If CANFD_CH_RXF1S.DMS is set to 0b11, the DMA
request remains active.
Workaround
Fix status
In case the debug message handling state machine stops while CANFD_CH_RXF1S.DMS is 0b01 or 0b10, it can
be reset to Idle state by hardware reset or by reception of debug messages after CANFD_CH_CCCR.INIT is reset
to zero.
No silicon fix planned. Use workaround.
8. TPIU peripheral ID mismatch
Problem definition
Parameters affected
Trigger condition(s)
Scope of impact
Workaround
TPIU peripheral ID indicates that it is M3-TPIU instead of M4-TPIU.
NA
When the debugger reads PID registers for component identification.
The only impact is that the debuggers read the TPIU as M3-TPIU.
No specific workaround required. Debuggers can use trace features.
No fix planned
Fix status
9. Limitation of the memory hole in SCB register space
Problem definition
The memory hole [offset address: 0x1000 to 0xFFFF] inside the SCB register space is not aligned to the below
defined spec. Since the offset address bits [15:12] are ignored and treated as 4'b0000, write/read access to the
offset address [0x1000 to 0xFFFF] will actually happen to [0x0000 to 0x0FFF].
- Access to address gaps in mapped memory space: writes are ignored and any read returns a zero.
Parameters affected
Trigger condition(s)
Scope of impact
NA
Access to the memory hole [offset address: 0x1000 to 0xFFFF] in the SCB register space
The memory hole [offset address: 0x1000 to 0xFFFF] in the SCB register space is not aligned to other IP
registers.
Workaround
Fix status
Do not access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space.
No fix planned
10. WDT service can be missed
Problem definition
If WDT service happens within 4 ILO clock cycles before DeepSleep entry, it clears the counter but does not
fully complete an internal handshake. A service after DeepSleep wakeup may then be missed if it occurs less
than 2 ILO clock cycles after the processor resumes clocking. After this time, the internal handshake is
complete and servicing works normally.
Parameters affected
Trigger condition(s)
NA
Service WDT within four ILO clock cycles before DeepSleep entry and within two ILO clock cycles of processor
clock resuming
Scope of impact
WDT service after DeepSleep wakeup may be ignored and WDT continues counting.
This can cause unintended WARN_ACTION or UPPER_ACTION, including interrupt, fault, and/or reset.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Errata
Workaround
Fix status
Wait 130 µs or more after DeepSleep wakeup. (For example, to measure 130 µs, software can read the
WDT_CNT register at wake up and make sure that WDT_CNT was incremented of 4 units before servicing
WDT).
Afterwards, write '1' to WDT service (WDT_SERVICE.SERVICE) after waiting until WDT service
(WDT_SERVICE.SERVICE) reads '0'.
No silicon fix planned. Use workaround.
11. CAN FD controller message order inversion when transmitting from dedicated Tx Buffers configured with same Message ID
Problem definition
Configuration:
Several Tx buffers are configured with the same Message ID. Transmission of these Tx buffers is requested
sequentially with a delay between the individual Tx requests.
Expected behavior:
When multiple Tx buffers that are configured with the same Message ID have pending Tx requests, they shall
be transmitted in ascending order of their Tx buffer numbers. The Tx buffer with lowest buffer number and
pending Tx request is transmitted first.
Observed behavior:
It may happen, depending on the delay between the individual Tx requests, that in the case where multiple
Tx Buffers are configured with the same Message ID the Tx buffers are not transmitted in order of the Tx Buffer
number (lowest number first).
Parameters affected
Trigger condition(s)
Scope of impact
NA
When multiple Tx buffers that are configured with the same Message ID have pending Tx requests.
In the case described it may happen, that Tx buffers configured with the same Message ID and pending Tx
request are not transmitted with lowest Tx Buffer number first (message order inversion).
Workaround
Any of the following:
1) First write the group of Tx message with the same Message ID to the Message RAM and then afterwards
request transmission of all these messages concurrently by a single write access to CANFDx_CHy_TXBAR.
Before requesting a group of Tx messages with this Message ID ensure that no message with this Message ID
has a pending Tx request.
2) Use the Tx FIFO instead of dedicated Tx buffers for the transmission of several messages with the same
Message ID in a specific order.
Applications not able to use workaround #1 or #2 can implement a counter within the data section of their
messages sent with same ID in order to allow the recipients to determine the correct sending sequence.
Fix status
No silicon fix planned. Use workaround.
Datasheet
155
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Errata
12. CAN FD incomplete description of Dedicated Tx buffers and Tx Queue related to transmission from multiple buffers
configured with the same Message ID
Problem Definition
The following are the updated description in Sections "Dedicated Tx Buffers" and "Tx Queue" of the Archi-
tecture TRM related to the transmission from multiple buffers configured with the same Message ID.
Dedicated Tx buffers
- TRM Statement: If multiple Tx buffers are configured with the same Message ID, the Tx buffer with the
lowest buffer number is transmitted first.
- Enhancement: These Tx buffers shall be requested in ascending order with lowest buffer number first.
Alternatively all Tx buffers configured with the same Message ID can be requested simultaneously by a
single write access to CANFDx_CHy_TXBAR.
Tx queue
- TRM statement: If multiple queue buffers are configured with the same Message ID, the queue buffer with
the lowest buffer number is transmitted first.
- Replacement: If multiple Tx queue buffers are configured with the same Message ID, the transmission
order depends on numbers of the buffers where the messages were stored for transmission. As these buffer
numbers depend on the then current states of the PUT Index, a prediction of the transmission order is not
possible.
- TRM statement: An Add Request cyclically increments the Put Index to the next free Tx Buffer.
- Replacement: The PUT Index always points to that free buffer of the Tx Queue with the lowest number.
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
Using multiple dedicated Tx buffers or Tx queue buffers configured with the same Message ID.
If the dedicated Tx buffers with the same Message ID are not requested in ascending order or at the same
time, or if there are multiple Tx queue buffers with the same Message ID, it cannot be guaranteed, that these
messages are transmitted in ascending order with lowest buffer number first.
Workaround
Fix Status
In case a defined order of transmission is required, the Tx FIFO shall be used for transmission of messages
with the same Message ID. Alternatively dedicated Tx buffers with the same Message ID shall be requested
in ascending order with lowest buffer number first or by a single write access to CANFDx_CHy_TXBAR.
Alternatively a single Tx Buffer can be used to transmit those messages one after the other.
No silicon fix planned. Use workaround. TRM was updated accordingly.
13.Misleading status is returned for Flash and eFuse system calls, if there are pending NC ECC faults in SRAM controller #0
Problem Definition
Flash and eFuse system calls will return misleading status of 0xF0000005 (“Page is write protected”) even
for non-protected row, or 0xF0000002 (“Invalid eFuse address”) for valid eFuse address in case of pending
NC ECC faults in SRAM controller #0.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Return status of Flash and eFuse system calls.
NC ECC fault(s) pending in SRAM controller #0 and SWPUs are populated in the design.
Flash and eFuse system calls will not work until the NC ECC fault(s) pending in SRAM controller #0 is/are
properly handled.
Workaround
Fix Status
If the NC ECC fault(s) are not due to HW malfunction (i.e. if the faults are due to usage of non-initialized
SRAM or improper SRAM initialization), then clearing of these pending faults will resolve the issue.
No silicon fix planned. TRM will be updated.
Datasheet
156
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Errata
14.WDT reset causes loss of SRAM retention
Problem Definition
The “Reset Cause Distribution” table in the Architecture TRM shows that the WDT reset can retain SRAM if
there is an orderly shutdown of the SRAM only during a warning interrupt. However, this is wrong. WDT
reset causes loss of SRAM retention.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
NA
WDT reset
WDT reset causes loss of SRAM retention.
None
Fix Status
No silicon fix planned. TRM will be updated.
15.Crypto ECC errors may be set after boot with application authentication
Problem Definition
Due to the improper initialization of the Crypto memory buffer, Crypto ECC errors may be set after boot
with application authentication.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
N/A
Boot device with application authentication.
Crypto ECC errors may be set after boot with application authentication.
Clear or ignore Crypto ECC errors which generated during boot with application authentication.
No silicon fix planned. TRM will be updated.
Fix Status
16.Incomplete erase of Code Flash cells could happen Erase Suspend / Erase Resume is used along with Erase Sector operation
in Non-Blocking mode
Problem Definition
Code Flash memory can be erased in “Non-Blocking” mode; a Non-Blocking mode supported option allows
users to suspend an ongoing erase sector operation. When an ongoing erase operation is interrupted using
“Erase Suspend” and “Erase Resume”, Flash cells may not have been erased completely, even after the
erase operation complete is indicated by FLASHC_STATUS register. Only Code Flash is impacted by this
issue, Work Flash and Supervisory Flash (SFlash) are not impacted.
Parameters Affected
Trigger Condition(s)
N/A
Using EraseSector System Call in Non-Blocking mode for CM0+ to erase Code Flash and the ongoing erase
operation is interrupted using EraseSuspend and EraseResume System calls.
Scope of Impact
When Code Flash sectors are erased in Non-Blocking mode and the ongoing erase operation is interrupted
by Erase Suspend / Erase Resume, it cannot be guaranteed that the Code Flash cells are fully erased. Any
read on the Code Flash area after the erase is complete or read on the programmed data after ProgramRow
is complete can trigger ECC errors.
Workaround
Use any of the following:
1) Use Non-Blocking mode for EraseSector, but do not interrupt the erase operation using Erase Suspend/
Erase Resume.
2) If a Code Flash sector erase operation is interrupted using Erase Suspend / Erase Resume, then erase the
same sector again without Erase Suspend / Erase Resume before reading the sector or programming the
sector.
Fix Status
Will be fixed to update the Flash settings via Manufacturing Test Program Update for Code Flash setting;
this fix is transferred to TRAVEO™ T2G devices during Infineon Factory Test Flow. Fixed devices will be
identified by Device Date Code, which is marked on every TRAVEO™ T2G device.
Datasheet
157
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Errata
17.Limitation for keeping the port state from peripheral IP after wakeup from DeepSleep
Problem Definition
The port state is not retained when the port selects peripheral IP (except for LIN or CAN FD) and MCU wakes
up from DeepSleep.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
N/A
The port selects peripherals (except LIN or CAN FD) and MCU wakes up from DeepSleep.
Unexpected port output change might affect user system.
If the port selects peripherals (except LIN or CAN FD), and the port output value needs to be maintained
after wakeup from DeepSleep, set HSIOM_PRTx_PORT_SEL.IOy_SEL = 0 (GPIO) before DeepSleep and set
the required output value in GPIO configuration registers. After wakeup, change HSIOM_PRTx-
_PORT_SEL.IOy_SEL back to the peripheral module as needed.
Fix Status
No silicon fix planned. TRM will be updated to add above workaround.
Datasheet
158
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Revision history
Revision history
Document
Date of release
version
Description of changes
**
2020-02-07
2020-06-29
New datasheet
*A
Changed datasheet status to Preliminary.
Updated Features list:
- Updated TCPWM (16-bit) and Internal low-speed oscillator in Table 1-1.
- Added .
Updated ILO Clock Source description in Clock system.
Updated the block of CLOCK_PATH3 in the CYT2B6 clock diagram.
Updated VCCD in Power pin assignments.
Removed associated footnotes in Alternate pin functions in Active mode table.
Added Pin mux descriptions.
Updated MUX Group 10 in Trigger inputs.
Updated Peripheral clock assignments.
Updated Fault assignments.
Updated Miscellaneous configuration for CYT2B6 devices.
Updated Figure 27-2
Updated Ordering information.
Updated Device code nomenclature and Ordering code nomenclature.
Added note in Package characteristics.
Added External IP revisions.
*B
2021-07-08
Updated Features.
Updated Features list.
Updated Communication peripheral instance list.
Updated System resources.
Updated I/Os.
Updated High-speed I/O matrix connections.
Updated Alternate function pin assignments.
Updated Triggers one-to-one.
Updated Faults.
Updated Miscellaneous configuration.
Updated Electrical specifications.
Updated Part number nomenclature.
Updated Appendix.
Updated Errata.
*C
2022-10-07
Migrated to IFX template.
Updated Clock system.
Updated Pin assignment.
Updated Alternate function pin assignments.
Updated Packaging.
Updated Errata.
Datasheet
159
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2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Revision history change log
Revision history change log
Rev. *C Section updates
Section
Change Description
Current Spec (Rev. *B)
New Spec (Rev. *C)
Reason for change
3.2.3 Clock
System
Updated IMO Clock Source
description
The IMO operates at a frequency of 8 The IMO operates at a frequency of around Correction
MHz ±1%. The internal trim settings 8 MHz.
for the IMO can be dynamically
updated to provide a tolerance < 1%.
9. Pin
Updated Figure 9-2, 9-4, 9-6 Identifier (n) does not present
Added identifier (n).
New addition
New addition
Assignment
13. Alternate
Function Pin
Assignments
Updated Table 13-1
Updated Table 13-1
(none)
Added note [27]: Refer to Table 13-2 for
more information on pin multiplexer
abbreviations used.
13. Alternate
Function Pin
Assignments
Identifier (n) and note do not present Added identifier (n).
New addition
Improvement
Added note [28]: For any function marked
with an identifier (n), the AC timing is only
guaranteed within the respective group
"n".
27. Electrical
Specifications
Updated Figure 27-14
OVD, BOD
HV OVD, HV BOD
XRES_L: Hight Level (left side) / Low XRES_L: LOW Level (left side) / HIGH Level
Level (right side)
(right side)
27. Electrical
Updated Table 27-17 title
SWD Interface Specifications
SWD Interface Specifications [Conditions: New addition
drive_sel<1:0>= 00]
Specifications
27. Electrical
Updated Table 27-18 title
Updated Table 27-19 title
Updated Table 26-20
JTAG AC Specifications
Trace Specifications
JTAG AC Specifications [Conditions:
drive_sel<1:0>= 00]
New addition
New addition
Correction
Specifications
27. Electrical
Specifications
Trace Specifications [Conditions:
drive_sel<1:0>= 00]
27. Electrical
Specifications
CLK_HF2 / Max Frequency (MHz):
8
CLK_HF2 / Max Frequency (MHz):
2
29. Packaging Added note 72
-
[72]: The numbers are estimated values
based simulation only and are based on a
single bill of material combination per
package type.
Added note
32. Errata
Updated errata
-
Updated the workaround 1) of errata ID
147.
Added errata
Added errata ID 167, 175, 176, 185, 198, 199.
Rev *C Electrical Specification Updates
Changed
Item
Reason for
Change
Section
Spec ID
Description
Current Spec (Rev. *B)
New Spec (Rev. *C)
27. Electrical SID40
Specifications
Power supply voltage Note
[42]: 5.0 V ±10% is supported [46]: 5.0 V ±10% is supported with a higher Correction
with a higher OVD setting
OVD setting option for VDDD and VDDA. This
option for VDDD and VDDA. setting provides robust protection for
This setting provides robust internal and interface timing, but OVD reset
protection for internal and
interface timing, but OVD
reset occurs at a voltage
occurs at a voltage above the specified
operating conditions. A lower OVD setting
option is available (consistent with up to 5.0
abovethe specified operating V) and guarantees that all operating condi-
conditions. A lower OVD
setting option is available
tions are met. Voltage overshoot to a higher
OVD setting range for VDDD and VDDA is
(consistent with up to 5.0 V) permissible, provided the duration is less
and guarantees that all
than 2 hours cumulated. Note that during
operating conditions are met. overshoot voltage condition electrical
parameters are not guaranteed.
27. Electrical SID63
Specifications SID63A
SID63B
DeepSleep to Active
transition time
Note [50]
(none)
Added Note[50]: At cold temperature -5°C to Added note
-40°C, the DeepSleep to Active transition
time can be higher than the max time
indicated by as much as 20 us
SID63C
SID63D
27. Electrical SID200
Specifications
Temperature Sensor
accuracy 1
All
Temperature Sensor
accuracy 1
(none)
Merged to
SID201
Datasheet
160
002-25756 Rev. *C
2022-10-07
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Revision history change log
Rev *C Electrical Specification Updates (continued)
Changed
Reason for
Change
Section
Spec ID
Description
Current Spec (Rev. *B)
New Spec (Rev. *C)
- 40 °C =< TJ =< 150 °C
Item
27. Electrical SID201
Specifications
Temperature Sensor
accuracy 2
Description - 40 °C =< TJ < 150 °C
Details/Con This spec is valid when using This spec is valid when using ADC[0]
ditions
Merged with
SID200
ADC[0] (VDDIO_1), ADC[1]
(VDDIO_1), ADC[1] (VDDIO_2) or ADC[2]
(VDDIO_2) or ADC[2] (VDDD) (VDDD) with the following conditions:
with the following conditions: a. 3.0 V =< VDDD, VDDIO_1 or VDDIO_2 =
a. 3.0 V =< VDDD, VDDIO_1 or VDDA = VREFH =< 3.6 V
VDDIO_2 = VDDA = VREFH =< or
3.6 V
b. 4.5 V =< VDDD, VDDIO_1 or VDDIO_2 =
VDDA = VREFH =< 5.5 V
or
b. 4.5 V =< VDDD, VDDIO_1 or
VDDIO_2 = VDDA = VREFH =<
5.5 V
27. Electrical SID334
Specifications
4-MHz ECO start-up
time
Details/Con Start-up time to 90% of final Time from set CLK_ECO_CONFIG.ECO_EN Correction
ditions
frequency
to 1 until CLK_ECO_STATUS.ECO_READY is
set to 1. (See Clock Timing Diagrams)
27. Electrical SID335
Specifications
33-MHz ECO start-up
time
Details/Con Start-up time to 90% of final Time from set CLK_ECO_CONFIG.ECO_EN Correction
ditions
frequency
to 1 until CLK_ECO_STATUS.ECO_READY is
set to 1. (See Clock Timing Diagrams)
27. Electrical SID362
Specifications
WCO start up time
Details/Con For Grade-S devices
ditions
For Grade-S devices
Correction
Correction
Time from set CTL.WCO_EN to 1 until
STATUS.WCO_OK is set to 1. (See Figure
Clock Timing Diagrams)
27. Electrical SID362E WCO start up time
Specifications
Details/Con For Grade-E devices
ditions
For Grade-E devices
Time from set CTL.WCO_EN to 1 until
STATUS.WCO_OK is set to 1. (See Clock
Timing Diagrams)
Datasheet
161
002-25756 Rev. *C
2022-10-07
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Edition 2022-10-07
Published by
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002-25756 Rev. *C
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