CYPD7271-68LQXQ_技术文档

CYPD7271

EZ-PD™ CCG7DC dual-port USB-C power

delivery and DC-DC controller

General description

EZ-PD™ CCG7DC is Infineon highly integrated dual-port USB Type-C power delivery (PD) solution with integrated

buck-boost controllers. It complies to the latest USB Type-C and PD specifications, and is targeted for multi-port

consumer charging applications. Integration offered by CCG7DC not only reduces the BOM but also provides a

footprint optimized solution to support higher power density designs. CCG7DC has integrated gate drivers for

VBUS NFET on the provider path. It also includes hardware-controlled protection features on the VBUS. CCG7DC

supports a wide input voltage range (4 V to 24 V with 40 V tolerance) and programmable switching frequency (150

kHz to 600 kHz) in an integrated PD solution.

EZ-PD™ CCG7DC is the most programmable USB-PD solution with on-chip 32-bit Arm® Cortex®-M0 processor,

128-KB flash, 16-KB RAM and 32-KB ROM that leaves most flash available for user application use. It also includes

various analog and digital peripherals such as ADC, PWMs and Timers. The inclusion of a fully programmable MCU

with analog and digital peripherals allows the implementation of custom system management functions such as

dynamic load sharing and temperature monitoring.

Applications

• Cigarette lighter adapter (CLA)

• Multi-port AC-DC charger and adapter

Features

• USB-PD

- Supports two USB-PD ports

- Supports latest USB-PD 3.0 version 2.0 including programmable power supply (PPS) mode

- Extended data messaging (EDM)

• Type-C

- Configurable resistors RP and RD

- VBUS NFET gate driver

- Integrated 100-mW VCONN power supply and control

• 2x buck-boost controller

- 150 kHz to 600 kHz switching frequency

- 5.5 V to 24 V input, 40 V tolerant

- 3.3 V to 21.5 V output

- 20-mV voltage and 50-mA current steps for PPS

- Supports selectable pulse skipping mode (PSM) and forced continuous conduction mode (FCCM)

- Supports soft start

- Programmable spread spectrum frequency modulation for low EMI

- Programmable phase shift across two ports to further reduce the EMI

• 2x legacy/proprietary charging blocks

- Supports QC4+, QC4.0, Samsung AFC, Apple 2.4A, and BC v1.2 charging protocols

• Integrated voltage (VBUS) regulation and current sense amplifier (CSA)

- Integrated shunt regulator function for VBUS control

- Constant current or constant voltage mode

- Supports current sensing for constant current control

• System-level fault protection

- On-chip VBUS, overvoltage protection (OVP), overcurrent protection (OCP), undervoltage protection (UVP)

- VBUS to CC short protection

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Features

- Under-voltage lockout (UVLO)

- Supports over-temperature protection through integrated ADC circuit and internal temperature sensor

- Supports connector and board temperature measurement using external thermistors

• 32-bit MCU subsystem

- 48-MHz Arm® Cortex®-M0 CPU

- 128-KB flash

- 16-KB SRAM

- 32-KB ROM

• Peripherals and GPIOs

- 19 GPIOs

- Two over-voltage GPIOs

- 3x 8-bit ADC

- 4x 16-bit timer/counter/PWMs (TCPWM)

• Communication interfaces

- 4x SCBs (I²C/SPI/UART)

• Clocks and oscillators

- Integrated oscillator eliminating the need for an external clock

• Power supply

- 4 V to 24 V input (40-V tolerant)

- 3.3 V to 21.5 V output

- Integrated LDO capable of 5 V @ 150 mA

• Packages

- 68-pin QFN (8 mm  8 mm) package with –40 °C to +105 °C extended industrial temperature range

Datasheet

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Logic block diagram

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

MCU subsystem

I/O subsystem

Integrated digital blocks

CC

4x TCPWM

arm^®

Cortex®- M0

48 MHz

4x SCB

V_CONN

(I²C, SPI, UART)

19x GPIOs

Flash

(128 KB)

SROM

(32 KB)

USB PD subsystem x2

Baseband MAC &

PHY

V_CONNOCP, UV

SRAM

(16 KB)

V_BUSto CC

short protection

Hi -Voltage LDO

(24 V)

8-bit SAR

2xV_CONNFETs

V

_BUSOVP, OCP, SCP

protection

NFET load switch

gate driver

System resources

Buck-boost controller

Functional block diagram

EA_OUT_0

BST1_0 HGT1_0 SW1_0 LGT1_0 BST2_0 HGT2_0 SW2_0 LGT2_0 CSPO_0 CSNO_0

VBUS_CTRL_0

CSPI_0

CSNI_0

Input sense

amplifier (CSA),

slope

Error

amplifier

(CV)

Error

amplifier

(CC)

GDRV (Buck)

GDRV (Boost)

Slew rate control

NG ATE driver

High-side

CSA

High-side

Low-side driver

(LSDR)

High-side

Low-side driver

(LSDR)

driver (HSDR)

compensation

VBUS_IN

VBUS_C

discharge discharge

Zero crossing

detect (ZCD)

Zero crossing

detect (ZCD)

Charge control

CC reference

CC1_0

V5V_0

CC2_0

HV regulator

(24-5 V)

BMC

Reference

and IDAC

VIN

VDDD

VCCD

VCONN

PHY

Pulse-width

modulator

(PWM)

MCU subsystem

Charger

detect

DP_0

DM_0

3x 8-bit ADC

19 GPIOs

4x TCPWM

Cortex^®-M0

LV regulator

(5-1.8V)

4x SCB

(I2C/SPI/

UART/LIN)

Flash

SROM

(32KB)

SRAM

(16KB)

DP_1

DM_1

Charger

detect

(128KB)

Pulse-width

modulator

(PWM)

CC1_1

V5V_1

CC2_1

Reference

and IDAC

BMC

VCONN

PHY

XRES

POR/RESET

CC reference

Zero crossing

detect (ZCD)

Zero crossing

detect (ZCD)

Charge control

VBUS_IN

VBUS_C

discharge discharge

High-Side

Driver (HSDR)

Low-side driver

(LSDR)

High-side

driver (HSDR)

Low-side driver

(LSDR)

Error

amplifier

(CV)

Error

amplifier

(CC)

CSA, Slope

Compensation

High-Side

CSA

Slew rate control

NG ATE driver

GDRV (Buck)

GDRV (Boost)

EA_OUT_1

BST1_1 HGT1_1 SW1_1 LGT1_1 BST2_1 HGT1_2 SW1_2 LGT1_2 CSPO_1 CSNO_1

VBUS_CTRL_1

CSPI_1

CSNI_1

Datasheet

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Table of contents

General description ...........................................................................................................................1

Applications......................................................................................................................................1

Features ...........................................................................................................................................1

Logic block diagram ..........................................................................................................................3

Functional block diagram...................................................................................................................3

Table of contents...............................................................................................................................4

1 Functional overview .......................................................................................................................5

1.1 MCU subsystem.......................................................................................................................................................5

1.2 USB PD subsystem..................................................................................................................................................5

1.3 Buck-boost subsystem ...........................................................................................................................................7

1.4 Buck-boost controller operation regions ..............................................................................................................8

1.5 Analog blocks ........................................................................................................................................................11

1.6 Integrated digital blocks.......................................................................................................................................11

1.7 I/O subsystem .......................................................................................................................................................11

1.8 System resources..................................................................................................................................................12

2 Power subsystem..........................................................................................................................14

2.1 VIN undervoltage lockout (UVLO) ........................................................................................................................15

2.2 Using external VDDD supply.................................................................................................................................15

2.3 Power modes ........................................................................................................................................................15

3 Pin information ............................................................................................................................16

4 EZ-PD™ CCG7DC programming and bootloading ..............................................................................21

4.1 Programming the device flash over SWD interface.............................................................................................21

5 Applications .................................................................................................................................22

6 Electrical specifications.................................................................................................................26

6.1 Absolute maximum ratings ..................................................................................................................................26

6.2 Device-level specifications ...................................................................................................................................29

6.3 Digital peripherals.................................................................................................................................................34

6.4 System resources..................................................................................................................................................36

7 Ordering information ....................................................................................................................42

7.1 Ordering code definitions.....................................................................................................................................42

8 Packaging ....................................................................................................................................43

9 Package diagram ..........................................................................................................................44

10 Acronyms ...................................................................................................................................45

11 Document conventions................................................................................................................46

Revision history ..............................................................................................................................47

Datasheet

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Functional overview

1

Functional overview

MCU subsystem

CPU

1.1

1.1.1

The Cortex®-M0 in EZ-PD™ CCG7DC devices is a 32-bit MCU, which is optimized for low-power operation with

extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the thumb-2 instruction set. It

also includes a hardware multiplier, which provides a 32-bit result in one cycle. It includes an interrupt controller

(the NVIC block) with 32 interrupt inputs and a wakeup interrupt controller (WIC), which can wake the processor

up from deepsleep mode.

1.1.2

Flash ROM and SRAM

EZ-PD™ CCG7DC devices have 128-KB flash and 32-KB ROM for non-volatile storage. ROM stores libraries for

authentication and device drivers such as I²C, SPI, and so on. That spares flash for user application. Flash provides

the flexibility to store code for any customer feature and allows firmware upgrades to meet the latest USB PD

specifications and application needs.

The 16-KB RAM is used under software control to store the temporary status of system variables and parameters.

A supervisory ROM that contains boot and configuration routines is provided.

1.2

USB PD subsystem

This subsystem provides the interface to the Type-C USB port. This subsystem comprises:

• USB PD physical layer

• VCONN switches

• Under voltage (UVP), over voltage (OVP) on VBUS

• Output high-side CSA (HS CSA) for VBUS

• VBUS discharge control

• Gate driver for VBUS provider NFET

• Charger detection block for legacy charging

• VBUS to CC short-circuit protection

1.2.1

USB PD physical layer

The USB PD subsystem contains the USB PD physical layer block and supporting circuits. The USB PD physical

layer consists of a transmitter and receiver that communicate BMC encoded data over the CC channel per the PD

3.0 standard. All communication is half-duplex. The physical layer or PHY practices collision avoidance to

minimize communication errors on the channel.

Also, the USBPD block includes all termination resistors (Rp and Rd) and their switches as required by the USB

Type-C spec. Rp and Rd resistors are required to implement connection detection, plug orientation detection and

for the establishment of the USB source/sink roles. The Rp resistor is implemented as a current source.

CCG7DC device family is fully complaint with revisions 3.0 and 2.0 of the USB PD specification. The device

supports PPS operation at all valid voltages from 3.3 V to 21 V.

CCG7DC devices support Rp under HW control in unconnected (standby) state to minimize standby power.

CCG7DC devices support USB-PD extended messages containing data of up to 260 bytes. The extended messages

are larger than expected by USB-PD 2.0 hardware. As per the USB-PD protocol specification, USB-PD 3.0

compliant devices implement a Chunking mechanism; messages are limited to Revision 2.0 sizes unless both

source and sink confirm and negotiate compatibility with longer message lengths.

Datasheet

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Functional overview

1.2.2

VCONN switches

EZ-PD™ CCG7DC’s internal LDO voltage regulator is capable of powering a 100mW VCONN supply for electroni-

cally marked cable assemblies (EMCA), VCONN-powered devices (VPD), and VCONN-powered accessories as

defined in the USB Type-C specification. All circuitry including VCONN switches and over-current protection is

integrated in the device. In the event the VCONN current exceeds the VCONN OCP limit, CCG7DC can be

configured to shut down the Type-C port after a certain number of user configurable retries. The port can be

re-enabled after a physical disconnect.

1.2.3

VBUS UVP and OVP

VBUS undervoltage and overvoltage faults are monitored using internal resistor dividers. The fault thresholds

and response times are user configurable. Refer to the EZ-PD™ Configuration Utility for more details. In the

event of a UVP or OVP, CCG7DC can be configured to shut down the Type-C port after a certain number of user

configurable retries. The port can be re-enabled after a physical disconnect.

1.2.4

VBUS OCP and SCP

VBUS overcurrent and short-circuit faults are monitored using internal CSAs. Similar to OVP and UVP, the OCP

and SCP fault thresholds and response times are configurable as well. Refer to the EZ-PD™ Configuration Utility

for more details. In the event of OCP or SCP, CCG7DC can be configured to shut down the Type-C port after a

certain number of user configurable retries. The port can be re-enabled after a physical disconnect.

1.2.5

HS-CSA for VBUS

EZ-PD™ CCG7DC device family supports VBUS current measurement and control using an external resistor (5 mΩ)

in series with the VBUS path. The voltage drop across this resistor is used to measure the average output current.

The same resistor is also used to sense and precisely control the output current in the PPS current foldback mode

of operation.

1.2.6

VBUS discharge control

The chip supports high-voltage (21.5 V) VBUS discharge circuitry. Upon the detection of device disconnection,

faults, or hard resets, the chip will discharge the output VBUS terminals to vSafe5 V and/or vSafe0V within the

time limits specified in the USB PD specification.

1.2.7

Gate driver for VBUS provider NFET

EZ-PD™ CCG7DC devices have an integrated high-voltage gate driver to drive the gate of an external high-side

NFET on the VBUS provider path. The gate driver drives the load switch that controls the connection between

VBUS_IN and VBUS_C. VBUS_CTRL is the output of this gate driver. To turn off the external NFET, the gate driver

drives VBUS_IN low. To turn on the external NFET, it drives the gate to VBUS_IN + 8 V. There is an optional slow

turn-on feature which is meant to avoid sudden in-rush current. For a typical gate capacitance of 3-nF, a slow

turn-on time of 2 ms to 10 ms is configurable using firmware.

1.2.8

Legacy charge detection and support

The chip implements battery charger emulation and detection (source and sink) for USB BC.1.2, legacy Apple

charging, Qualcomm quick charge 2.0/3.0, Samsung AFC protocols and several upcoming proprietary charging

protocols.

1.2.9

VBUS to CC short protection

EZ-PD™ CCG7DC’s CC pins have integrated protection from accidental shorts to high-voltage VBUS. CCG7DC

devices can handle up to 24 V external voltage on its CC pins without damage. In the event an over-voltage is

detected on the CC pin, CCG7DC can be configured to shut down the Type-C port completely. The port will resume

normal operation once the CC voltage detected is within normal range.

Datasheet

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Functional overview

1.3

Buck-boost subsystem

The buck-boost subsystem in EZ-PD™ CCG7DC devices can be configured to operate in buck-boost mode,

buck-only mode or boost-only mode. While buck-boost mode requires four external switching FETs, buck-only

and boost-only modes require only two FETs. Buck-only mode is useful when CCG7DC device’s port is used for

multi-port AC/DC designs. Figure 1 illustrates the buck-boost subsystem’s main external components and

connections.

5 m

V_IN

V_OUT

CSR1

CSR2

VDDD

CYPD727x

Figure 1

Buck-boost schematic showing external components

Buck-boost subsystem in EZ-PD™ CCG7DC devices have the following key functional blocks:

• High-side (cycle-by-cycle) CSA

• High-side and low-side gate driver

• Pulse-width modulator (PWM)

• Error amplifier (EA)

1.3.1

High-side (cycle-by-cycle) CSA

EZ-PD™ CCG7DC device’s buck-boost controller implements peak current control in both boost and buck modes.

A high-side CSA is used for peak current sensing through an external resistor (5 mΩ; see CSR1 in Figure 1) placed

in series with the buck control FET. This CSA is high bandwidth and very wide common mode amplifier. This

current sense resistor is connected to the CSA block through pins CSPI and CSNI as shown in Figure 1. This block

implements slope compensation to avoid sub-harmonic oscillation for the internal current loop. In addition to

peak current sensing, it provides a current limit comparator for shutting off the buck-boost converter if the

current hits an upper threshold which is programmable.

1.3.2

High-side gate driver and low-side gate driver (HG/LG)

EZ-PD™ CCG7DC’s buck-boost controller provides four N-channel MOSFET gate drivers: two floating high-side

gate drivers at the HG1 and HG2 pins, and two ground referenced low-side drivers at the LG1 and LG2 pin. The

high-side gate drivers drive the high-side external FET with a nominal VGS of 5 V. The high-side gate driver has a

programmable drive strength to drive external FET. An external capacitor and Schottky diode form a bootstrap

network to collect and store the high voltage source (VIN + ~5 V for HG1 and VBUS + ~5 V for HG2) needed to drive

the high-side FET.

The low-side gate driver drives the low-side external FET with a nominal VGS of 5 V using energy sourced from

CCG7DC’s internal LDO regulator and stored in the capacitor between PVDD and PGND. Low-side gate driver has

programmable drive strength to drive external FET.

Datasheet

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Functional overview

In addition to drive strength, the high-side gate driver and the low-side gate driver have programmable options

for deadtime control and zero-crossing levels. High-side gate driver and low-side gate driver blocks include

zero-crossing detector (ZCD) to implement discontinuous-conduction mode (DCM) mode with diode emulation.

The gate drivers for the switching FETs function at their nominal drive voltage levels (5 V) provided the VIN voltage

is between 5.5 V and 24 V.

1.3.3

Error amplifier (EA)

EZ-PD™ CCG7DC's buck-boost controller contains two error amplifiers for output voltage and current regulation.

The error amplifier is a trans-conductance type amplifier with single compensation pin (COMP) to ground for both

the voltage and current loops. In voltage regulation, the output voltage is compared with the internal reference

voltage and the output of EA is fed to the PWM block. In current regulation, the average current is sensed by VBUS

high-side CSA through the external resistor. The output of the VBUS CSA is compared with internal reference in

error amplifier block and EA output is fed to the PWM block. CCG7DC devices negotiate a power delivery contract

over the Type-C port in compliance to USB-PD specification with the peer sink device and in turn controls the EA

output through the integrated programmable error amplifier circuit for achieving the required VBUS voltage

output.

1.3.4

Pulse-width modulator (PWM)

EZ-PD™ CCG7DC device family’s PWM block generates the control signals for the gate drivers driving the external

FETs in peak current mode control. There are many programmable options for minimum/maximum pulse width,

minimum/maximum period, frequency and pulse skip levels to optimize the system design.

CCG7DC devices have two firmware-selectable operating modes to optimize efficiency and reduce losses under

light load conditions: PSM and FCCM. It is critical in charger applications where the load can vary from a few watts

to 100 W.

1.3.5

Pulse skipping mode (PSM)

In pulse skipping mode, the controller reduces the total number of switching pulses without reducing the active

switching frequency by working in “bursts” of normal nominal-frequency switching interspersed with intervals

without switching. The output voltage thus increases during a switching burst and decreases during a quiet

interval. This mode results in minimal losses at the cost of higher output voltage ripple. When in this mode,

EZ-PD™ CCG7DC devices monitor the voltage across the buck or boost sync FET to detect when the inductor

current reaches zero; when this occurs, the CCG7DC devices switch off the buck or boost sync FET to prevent

reverse current flow from the output capacitors (i.e. diode emulation mode). Several parameters of this mode

are programmable through firmware, allowing the user to strike their own balance between light load efficiency

and output ripple.

1.3.6

Forced continuous conduction mode (FCCM)

In forced continuous conduction mode, the nominal switching frequency is maintained at all times, with the

inductor current going below zero (i.e. “backwards” or from the output to the input) for a portion of the switching

cycle as necessary to maintain the output voltage and current. This keeps the output voltage ripple to a minimum

at the cost of light-load efficiency.

1.4

Buck-boost controller operation regions

The CSA output is compared with the output of the error amplifier to determine the pulse width of the PWM. PWM

block compares the Input voltage and output voltage to determine the buck, boost, and buck-boost regions. The

switching time/period of the four gate drivers (HG1, LG1, HG2, LG2) depends upon the region in which the block

is operating as well as the mode such as DCM or FCCM. The exact VIN vs VOUT thresholds for transitions into and

out of each region are adjustable in firmware including the hysteresis.

Datasheet

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Functional overview

1.4.1

Buck region operation (VIN >> VBUS)

When the VIN voltage is significantly higher than the required VBUS voltage, EZ-PD™ CCG7DC devices operate in

the buck region. In this region, the boost side FETs are inactivated, with the boost control FET (connected to LG2)

turned off and the boost sync FET (connected to HG2) turned on. The buck side FETs are controlled as a buck

converter with synchronous rectification as shown in Figure 2. Depending on the application and requirement

the device can be configured to operate in buck mode only at all times using only two FETs.

ON

HG1

(Buck

control)

OFF

ON

LG1 (Buck

sync)

OFF

ON

LG2

(Boost

control)

OFF

ON

HG2

(Boost

sync)

OFF

Inductor

current

0

t

Figure 2

Buck operation waveforms

1.4.2

Boost region operation (VIN << VBUS)

When the VIN voltage is significantly lower than the required VBUS voltage, EZ-PD™ CCG7DC devices operate in

the boost region. In this region, the buck side FETs are inactivated, with the sync FET turned OFF and the buck

control FET turned ON. The boost side FETs are controlled as a boost converter with synchronous rectification as

shown in Figure 3.

ON

HG1

(Buck

control)

OFF

ON

LG1 (Buck

sync)

OFF

ON

LG2

(Boost

control)

OFF

ON

HG2

(Boost

sync)

OFF

Inductor

current

0

t

Figure 3

Boost operation waveforms

Datasheet

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Functional overview

1.4.3

Buck-boost region 1 operation (VIN ~> VBUS)

When the VIN voltage is slightly higher than the required VBUS voltage, EZ-PD™ CCG7DC devices operate in the

buck-boost region 1. In this region, the boost side FET (LG2) works at a fixed 20% duty cycle (programmable) while

the buck side (LG1 / HG1) duty cycle is modulated to control the output voltage. All four FETs are switching every

cycle in this operating region as shown in Figure 4.

ON

HG1

(Buck

control)

OFF

ON

LG1 (Buck

sync)

OFF

ON

LG2

(Boost

control)

OFF

ON

HG2

(Boost

sync)

OFF

Inductor

current

0

t

Figure 4

Buck-boost region 1 (VIN ~> VBUS) operation waveforms

1.4.4

Buck-boost region 2 operation (VIN ~< VBUS)

When the VIN voltage is slightly lower than the required VBUS voltage, EZ-PD™ CCG7DC devices operate in the

buck-boost region 2. In this region, the buck side (HG1) works at a fixed 80% duty cycle (programmable) while the

boost side (LG2) duty cycle is modulated to control the output voltage. All four FETs are switching every cycle in

this operating region as shown in Figure 5.

ON

HG1

(Buck

control)

OFF

ON

LG1 (Buck

sync)

OFF

ON

LG2

(Boost

control)

OFF

ON

HG2

(Boost

sync)

OFF

Inductor

current

0

t

Figure 5

Buck-boost region 2 (VIN ~< VBUS) operation waveforms

Datasheet

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Functional overview

1.4.5

Switching frequency and spread spectrum

EZ-PD™ CCG7DC devices offer programmable switching frequency between 150 kHz and 600 kHz. The controller

supports spread spectrum clocking within the operating frequency range in all operating modes. Spread

spectrum is essential for charging applications to meet EMC/EMI requirements by spreading emissions caused

by switching over a wide spectrum instead of a fixed frequency, thereby reducing the peak energy at any

particular frequency. Both the switching frequency and the spread spectrum span are firmware programmable.

1.5

Analog blocks

ADC

1.5.1

CCG7DC devices family have three 8-bit SAR ADCs available for general purpose A-D conversion applications in

the chip. The ADCs can be accessed from the GPIOs through an on-chip analog mux. See Table 27 for detailed

specs on the ADCs.

1.6

Integrated digital blocks

1.6.1

Serial communication block (SCB)

EZ-PD™ CCG7DC devices have four SCB blocks that can be configured for I²C, SPI, or UART. These blocks

implement full multi-master and slave I²C interfaces capable of multi-master arbitration. I²C is compatible with

the standard Philips I²C specification v3.0. These blocks operate at speeds of up to 1 Mbps and have flexible

buffering options to reduce interrupt overhead and latency for the CPU. The SCB blocks support 8-byte deep

FIFOs for receive and transmit, which, by increasing the time given for the CPU to read data, greatly reduces the

need for clock stretching caused by the CPU not having read data on time. The I²C port I/Os for SCB0 are

over-voltage tolerant (OVT). The I²C ports for SCB1-3 are not OVT compliant.

1.6.2

Timer, counter, pulse-width modulator (TCPWM)

The TCPWM block of EZ-PD™ CCG7DC devices support four timers or counters or pulse-width modulators. These

timers are available for internal timer use by firmware or for providing PWM-based functions on the GPIOs.

1.7

I/O subsystem

The EZ-PD™ CCG7DC devices have 19 GPIOs including the I2C and SWD pins which can also be used as GPIOs. The

GPIO block implements the following:

• Eight drive strength modes

- Input only

- Weak pull-up with strong pull-down

- Strong pull-up with weak pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up with strong pull-down

- Disabled

- Weak pull-up with weak pull-down

• Input threshold select (CMOS or LVTTL)

• Individual control of input and output disables

• Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode)

• Selectable slew rates for dV/dt related noise control.

• OVT on one pair of GPIOs

During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause

excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex

Datasheet

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Functional overview

between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals such as USB

Type-C port are also fixed in order to reduce internal multiplexing complexity. Data Output registers and Pin State

register store, respectively, the values to be driven on the pins and the states of the pins themselves. The config-

uration of the pins can be done by the programming of registers through software for each digital I/O port.

Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt

service routine (ISR) vector associated with it.

The I/O ports can retain their state during deepsleep mode or remain ON. If the operation is restored using reset,

then the pins shall go the high-Z state. If operation is restored by an interrupt event, then the pin drivers shall

retain their state until firmware chooses to change it. The IOs (on data bus) do not draw current on power down.

1.8

System resources

1.8.1

Watchdog timer (WDT)

EZ-PD™ CCG7DC devices have a watchdog timer running from the internal low-speed oscillator (ILO). This allows

watchdog operation during deepsleep and generate a watchdog reset if not serviced before the timeout occurs.

The watchdog reset is recorded in the Reset Cause register.

1.8.2

Reset

EZ-PD™ CCG7DC devices can be reset from a variety of sources including a software reset. Reset events are

asynchronous and guarantee reversion to a known state. The Reset cause is recorded in a register, which is sticky

through reset and allows software to determine the cause of the reset. XRES pin is the dedicated pin for reset to

apply hardware reset.

1.8.3

Clock system

CCG7DC devices have a fully integrated clock with no external crystal required. CCG7DC device’s clock system is

responsible for providing clocks to all sub-systems that require clocks (SCB and PD) and for switching between

different clock sources, without glitches.

The HFCLK signal can be divided down as shown to generate synchronous clocks for the digital peripherals. The

clock dividers have 8-bit, 16-bit and 16-bit fractional divide capability. The 16-bit capability allows a lot of flexi-

bility in generating fine-grained frequency values. The clock dividers generate either enabled clocks (that is, 1 in

N clocking where N is the divisor) or an approximately 50% duty cycle clock (exactly 50% for even divisors, one

clock difference in the high and low values for odd divisors).

In Figure 6, PERXYZCLK represents the clocks for different peripherals.

IMO

HFCLK

Pre-divider

ILO

LFCLK

HFCLK

Prescaler

SYSCLK

HALFSYSCLK

/2

Peripheral

dividers

PERXYZ_CLK

Figure 6

Clocking architecture of EZ-PD™ CCG7DC devices

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Functional overview

1.8.4

Internal main oscillator (IMO) clock source

The internal main oscillator is the primary source of internal clocking in CCG7DC devices. IMO default frequency

for CCG7DC devices is 48 MHz 2%.

1.8.5

ILO clock source

The internal low-speed oscillator is a very low power, relatively inaccurate, oscillator, which is primarily used to

generate clocks for peripheral operation in USB suspend (deepsleep) mode.

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Power subsystem

2

Power subsystem

Figure 7 illustrates an overview of the power subsystem architecture for EZ-PD™ CCG7DC devices. The power

subsystem of CCG7DC devices operate from VIN supply which can vary from 4 V to 24 V. The VDDD pin, the output

of 5 V LDO gets input from VIN supply. The VDDD pin can also be used as a power supply for external loads up to

150 mA. CCG7DC devices have two different power modes: Active and deepsleep, transitions between which are

managed by the power system. The VCCD pin, the output of the core (1.8 V) regulator, is brought out for

connecting a 0.1-µF capacitor for the regulator stability only. This pin is not supported as a power supply for

external load.

VBUS_IN_0 VBUS_C_0

VBUS_IN_1 VBUS_C_1

NGDO

PVDD

Buck-boost LS

Driver_P0

Buck-boost LS

Driver_P1

1 µF

PGND

VIN

PGND

VDDD

LDO

10 µF

CC1_1

CC2_1

CC2_0

CC1_0

Core regulator

VCCD

GND

0.1 µF

2 x CC

Tx/Rx

GPIOs

Core

Figure 7

Power system requirement block diagram

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Power subsystem

2.1

VIN undervoltage lockout (UVLO)

EZ-PD™ CCG7DC supports UVLO to allow the device to shut down when the input voltage is below the reliable

level. It guarantees predictable behavior when the device is up and running.

2.2

Using external VDDD supply

By default, external VDDD is not supported for CCG7DC devices. However, usage of external VDDD supply can be

enabled using firmware. The pre-requisite for enabling external forcing of VDDD is to always maintain VIN higher

than VDDD and the external load on VDDD pin of CCG7DC devices should never be higher than prescribed load

capability of internal VDDD LDO.

2.3

Power modes

The power modes of the device accessible and observable by the user are shown in Table 1.

Table 1 Power modes

Mode

Description

Power is valid and XRES is not asserted. An internal reset source is asserted or sleep controller is

sequencing the system out of reset.

RESET

ACTIVE

SLEEP

Power is valid and CPU is executing instructions.

Power is valid and CPU is not executing instructions. All logic that is not operating is clock gated

to save power.

Main regulator and most hard-IP are shut off. Deepsleep regulator powers logic, but only

low-frequency clock is available.

DEEPSLEEP

XRES

Power is valid and XRES is asserted. Core is powered down.

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Pin information

3

Pin information

Table 2

EZ-PD™ CCG7DC pinout table

Pin#

Pin name

GPIO port

Description

Negative power rail of port 0 buck high-side gate driver. This is also

connected to one input terminal of zero current detection of buck low-side

gate driver. Connect to the switch node (inductor) on the buck (input) side.

Use a short and wide trace to minimize the inductance and resistance of

this connection.

1

SW1_0

Buck low-side gate driver output of port 0. Connect to the buck (input) side

sync (low-side) FET gate. Use a wide trace to minimize inductance of this

connection.

2

3

LG1_0

Ground of low-side gate driver of port 0. This is also connected to one input

terminal of ZCD of buck low-side gate driver.

PGND_0

Connect directly to port 0’s board ground plane.

4

5

PVDD_0

LG2_0

Supply of low-side gate driver of port 0. Connect to VDDD. Use 1-µF and

0.1-µF bypass capacitors as close to the CCG7DC IC as possible.

Boost low-side gate driver output of port 0. Connect to the boost (output)

side control (low-side) FET gate. Use a wide trace to minimize inductance

of this connection.

Output of the buck-boost converter of port 0. This is also connected to one

input terminal of reverse current protection of boost high-side gate driver.

Connect to the boost sync (high-side) FET’s drain. Use a dedicated (Kelvin)

trace for this connection.

6

7

VOUT_0

SW2_0

Negative power rail of port 0 boost high-side gate driver. This is also

connected to one input terminal of reverse current protection of boost

high-side gate driver. Connect to the switch node (inductor) on the boost

(output) side. Use a short and wide trace to minimize the inductance and

resistance of this connection.

Boost high-side gate driver output of port 0. Connect to the boost (output)

side sync (high-side) FET gate. Use a wide trace to minimize inductance of

this connection.

8

9

HG2_0

–

BST2_0

Boosted power supply of port 0 boost high-side gate driver. Bootstrap

capacitor node. Connect Schottky diode from VDDD to BST2_0. Also,

connect a bootstrap capacitor from this pin to SW2_0.

10

COMP_0

EA output pin of port 0. Connect a compensation network to GND. Contact

Infineon for assistance in designing the compensation network.

Positive input of output CSA of port 0. Connect to positive terminal of the

output current sense resistor.

11

12

13

CSPO_0

CSNO_0

Negative input of output CSA of port 0 Connect to negative terminal of the

output current sense resistor.

VBUS_IN_0

Input of feedback voltage of EA of port 0. Connect to the VBUS node

between the output current sense resistor and the VBUS Provider NFET.

Type-C connector VBUS voltage of port 0. Connect to the Type-C

connector’s VBUS pin.

14

15

VBUS_C_0

CC1_0

Type-C connector configuration channel 1 of port 0. Connect directly to the

CC1 pin on the port’s Type-C connector. Also connect a 390-pF capacitor to

ground.

Type-C connector configuration channel 2 of port 0. Connect directly to the

CC2 pin on the port’s Type-C connector. Also connect a 390-pF capacitor to

ground.

16

17

CC2_0

VBUS NFET gate driver output of port 0. Connect to the provider NFET’s

gate.

VBUS_CTRL_0

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Pin information

Table 2

EZ-PD™ CCG7DC pinout table (continued)

Pin#

18

Pin name

CSN_0_GPIO0

CSP_0_GPIO1

GPIO2

GPIO port

P0.0

Description

P0.1

19

20

P0.2

GPIO

P0.3

21

GPIO3

P0.4

22

GPIO4

USB D+ of port 0/GPIO: D+ for implementing BC 1.2, AFC, QC or Apple

Charging.

23

DP_0_GPIO5

P1.0

P1.1

CCG7DC does not support USB data transmission on this pin.

USB D- of port 0/GPIO: D- for implementing BC 1.2, AFC, QC or Apple

Charging.

24

DM_0_GPIO6

CCG7DC does not support USB data transmission on this pin.

5-V LDO output. Connect a 1-µF ceramic bypass capacitor to this pin. Also,

connect this pin directly to pin 63.

25

26

27

VDDD

–

USB D- of port 1/GPIO: D- for implementing BC 1.2, AFC, QC or Apple

Charging. CCG7DC does not support USB data transmission on this pin.

DM_1_GPIO7

DP_1_GPIO8

P1.2

P1.3

USB D+ of port 1/ GPIO: D+ for implementing BC 1.2, AFC, QC or Apple

Charging. CCG7DC does not support USB data transmission on this pin.

–

External reset – active low. Contains a 3.5 k to 8.5 k internal pull-up.

28

29

30

31

32

33

XRES

GPIO9

P2.0

P2.1

P1.4

P1.5

P1.6

GPIO10

GPIO

GPIO11

CSP_1_GPIO12

CSN_1_GPIO13

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Pin information

Table 2

EZ-PD™ CCG7DC pinout table (continued)

Pin#

34

Pin name

GND

GPIO port

Description

Chip ground. Connect directly to the exposed pad (EPAD) and to pin 64.

VBUS NFET gate driver output of port 1. Connect to the provider NFET’s

gate.

35

VBUS_CTRL_1

Type-C connector configuration channel 2 of port 1. Connect directly to the

CC2 pin on the port’s Type-C connector. Also connect a 390-pF capacitor to

ground.

36

37

CC2_1

CC1_1

Type-C connector configuration channel 1 of port 1. Connect directly to the

CC1 pin on the port’s Type-C connector. Also connect a 390-pF capacitor to

ground.

Type-C connector BUS voltage of port 1. Connect to the Type-C connector’s

VBUS pin.

38

39

VBUS_C_1

VBUS_IN_1

Input of feedback voltage of EA of port 1. Connect to the VBUS node

between the output current sense resistor and the VBUS provider NFET.

–

Negative input of output CSA of port 1. Connect to negative terminal of the

output current sense resistor.

40

41

42

CSNO_1

CSPO_1

COMP_1

Positive input of output CSA of port 1. Connect to positive terminal of the

output current sense resistor.

EA output pin of port 1. Connect a compensation network to GND. Contact

Infineon for assistance in designing the compensation network.

Boosted power supply of port 1 boost high-side gate driver. Connect

Schottky diode from VDDD to BST2_1. Bootstrap capacitor node. Also,

connect a bootstrap capacitor from this pin to SW2_1.

43

44

BST2_1

HG2_1

Boost high-side gate driver output of port 1. Connect to the boost (output)

side sync (high-side) FET gate. Use a wide trace to minimize inductance of

this connection.

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Pin information

Table 2

EZ-PD™ CCG7DC pinout table (continued)

Pin#

Pin name

GPIO port

Description

Negative power rail of port 1 boost high-side gate driver. This is also

connected to one input terminal of reverse current protection of boost

high-side gate driver. Connect to the switch node (inductor) on the boost

(output) side. Use a short and wide trace to minimize the inductance and

resistance of this connection.

45

SW2_1

Output of the buck-boost converter of port 1. This is also connected to one

input terminal of reverse current protection of boost high-side gate driver.

Connect to the boost sync (high-side) FET’s drain. Use a dedicated (Kelvin)

trace for this connection.

46

47

VOUT_1

LG2_1

Boost low-side gate driver output of port 1. Connect to the boost (output)

side control (low-side) FET gate. Use a wide trace to minimize inductance

of this connection.

48

49

PVDD_1

PGND_1

Supply of low-side gate driver of port 1. Connect to VDDD. Use a 1 µF and

0.1 µF bypass capacitors as close to the CCG7DC device as possible.

Ground of low-side gate driver of port 1. This is also connected to one input

terminal of zero current detection of buck low-side gate driver.

Connect directly to Port 0’s board ground plane.

–

Buck low-side gate driver output of port 1. Connect to the buck (input) side

sync (low-side) FET gate. Use a wide trace to minimize inductance of this

connection.

50

51

LG1_1

SW1_1

Negative power rail of port 1 buck high-side gate driver. This is also

connected to one input terminal of zero current detection of buck low-side

gate driver. Connect to the switch node (inductor) on the buck (input) side.

Use a short and wide trace to minimize the inductance and resistance of

this connection.

Buck high-side gate driver output of port 1. Connect to the buck (input) side

control (high-side) FET gate. Use a wide trace to minimize inductance of

this connection.

52

HG1_1

Boosted power supply of port 1 buck high-side gate driver. Connect

Schottky diode from VDDD to BST1_1. Bootstrap capacitor node.

53

54

BST1_1

CSNI_1

Negative input of input CSA of port 1. Connect to the negative terminal of

the input current sense resistor. Use a dedicated (Kelvin) connection.

55

CSPI_1

Positive input of input CSA of port 1. Connect to the positive terminal of the

input current sense resistor. Use a dedicated (Kelvin) connection.

56

57

GPIO14/SWD_DA

T

P3.0

P3.1

GPIO/SWD programming and debug data signal

GPIO/SWD programming and debug clock signal

GPIO15/SWD_CL

K

P3.2

P3.3

P3.4

58

59

60

GPIO16

GPIO17

GPIO18

GPIO

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Pin information

Table 2

EZ-PD™ CCG7DC pinout table (continued)

Pin#

Pin name

GPIO port

Description

4 V–24 V input supply. Connect a ceramic bypass capacitor to GND close to

this pin.

61

VIN

1.8-V core LDO output. Connect a 0.1-µF bypass capacitor to ground. Do not

connect anything else to this pin.

62

63

VCCD

VDDD

5-V LDO output. Connect to pin 25. Also connect a 10-µF bypass capacitor

to this pin.

–

Chip ground. Connect to the EPAD and to pin 34.

64

65

GND

CSPI_0

Positive input of input CSA of port 0. Connect to the positive terminal of the

input current sense resistor. Use a dedicated (Kelvin) connection.

66

67

CSNI_0

BST1_0

Negative input of input CSA of port 0. Connect to the negative terminal of

the input current sense resistor. Use a dedicated (Kelvin) connection.

Boosted power supply of port 0 buck high-side gate driver. Bootstrap

capacitor node.

Connect Schottky diode from VDDD to BST1_0. Also, connect a bootstrap

capacitor from this pin to SW1_0.

–

Buck high-side gate driver output of port 0. Connect to the buck (input) side

control (high-side) FET gate. Use a wide trace to minimize inductance of

this connection.

68

HG1_0

EPAD

Exposed ground pad. Connect directly to pins 34 and 64.

1

2

3

4

5

6

7

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

SW1_1

LG 1 _1

PGND_1

PVDD_1

LG 2 _1

VOUT_1

SW2_1

HG2_1

BST2_1

COMP_1

CSPO_1

CSNO_1

VBUS_IN_1

VBUS_C_1

CC1_1

CC2_1

SW1_0

LG 1 _0

PGND_0

PVDD_0

LG 2 _0

VOUT_0

SW2_0

8

9

HG2_0

EPAD

BST2_0

COMP_0

CSPO_0

CSNO_0

VBUS_IN_0

VBUS_C_0

CC1_0

10

11

12

13

14

15

16

CC2_0

17

35

VBUS_CTRL_1

VBUS_CTRL_0

Figure 8

CCG7DC 68-QFN pinout

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

EZ-PD™ CCG7DC programming and bootload-

ing

4

EZ-PD™ CCG7DC programming and bootloading

There are two ways to program application firmware into a CCG7DC device:

1. Programming the device flash over SWD interface

2. Application firmware update over specific interfaces (CC, I2C)

Generally, the CCG7DC devices are programmed over SWD interface only during development or during the

manufacturing process of the end-product. Once the end-product is manufactured, the CCG7DC device's appli-

cation firmware can be updated via the appropriate bootloader interface. Infineon strongly recommends

customers to use the EZ-PD™ Configuration Utility to turn off the application FW Update over CC or I2C interface

in the firmware that is updated into CCG7DC's flash before mass production. This prevents unauthorized

firmware from being updated over CC interface in the field. If you desire to retain the application firmware update

over CC/I2C interfaces feature post-production for on-field firmware updates, contact Infineon Sales for further

guidelines.

4.1

Programming the device flash over SWD interface

The CCG7DC family of devices can be programmed using the SWD interface. Infineon provides programming kits

(CY8CKIT-002 MiniProg3 Kit) called MiniProg3 and (CY8CKIT-005 MiniProg4 Kit) MiniProg4 which can be used

to program the flash as well as debug firmware. The flash is programmed by downloading the information from

a hex file. This hex file is a binary file generated as an output of building the firmware project in PSoC Creator

Software. Click here for more information on how to use the MiniProg3 programmer. Click here for more infor-

mation on how to use the MiniProg4 programmer. There are many third-party programmers that support mass

programming in a manufacturing environment.

As shown in Figure 9, the SWD_DAT and SWD_CLK pins are connected to the host programmer’s SWDIO (data)

and SWDCLK (clock) pins respectively. During SWD programming, the device can be powered by the host

programmer by connecting its VTARG (power supply to the target device) to VDDD pins of CCG7DC device. If the

CCG7DC device is powered using an on-board power supply, it can be programmed using the “reset

programming” option. More details will be provided in the CCG7XXX programming specifications once it is

available.

3.3 V

V_DD

Host programmer

VTARG

CYPD7XXX

VDDD

10 µF

1 µF

0.1 µF

SWDCLK

SWDIO

XRES

SWD_CLK

SWD_DAT

XRES

V_CCD

0.1 µF

GND

Figure 9

Connecting the programmer to CYPD7XXX device

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Applications

5

Applications

Figure 10 illustrates a multi-port cigarette lighter adapter (CLA) application block diagram using EZ-PD™

CCG7DC. CLA is powered by the car battery and is used for charging the mobile/tablet/notebook. In this appli-

cation, CCG7DC will always be in DFP role supporting the charging of the device. It negotiates the power with the

connected device and uses the integrated buck-boost controller to supply the required voltage and current.

The DP/DM lines of the Type-C receptacles are connected to CCG7DC to support legacy charging protocols such

as QC3.0, Samsung AFC, Apple 2.4A charging, BC v1.2, and so on. When no load is connected to the USB Type-C

port, CCG7DC remains in Standby mode without switching on the buck-boost controller.

(USB PD, 3.3-21 V, 5A)

5 m

V_IN

V_BUS

Battery input

(9 V-24 V)

VDDD

0.1 μF

VDDD

68

67

1

2

5

9

7

8

6

11

12

13

17

14

1μF

4

3

PVDD_0

PGND_0

66

CSNI_0

CSPI_0

65

61

62

18

CSN_0_GPIO0

GPIO0

VIN

19

20

GPIO1

GPIO2

CSP_0_GPIO1

GPIO2

VCCD

0.1 μF

10

COMP_0

15

16

CC1

CC1_0

CC2_0

390pF

69

64

34

GND (EPAD)

GND

CC2

390pF

AGND

29

30

21

22

DP

GPIO9

23

24

DP_0_GPIO5

DM_0_GPIO6

GPIO10

GPIO3

GPIO4

DM

VDDD

63

25

VDDD

CYPD727x-68LQXQ

0.1 μF

10 μF

1μF

48

49

1

2

3

VDDD

AGND

PVDD_1

PGND_1

0.1 μF 1 μF

33

28

57

56

XRES

CSN_1_GPIO13

GPIO13

XRES

SWD_CLK

4

5

32

31

GPIO15

GPIO14

CSP_1_GPIO12

GPIO11

GPIO12

GPIO11

SWD_DAT

Programming header –

not needed for final

production

58

GPIO16

CC1

CC2

37

36

P1_NTC[0]

P0_NTC[0]

59

60

CC1_1

CC2_1

GPIO17

GPIO18

390-pF

42

COMP_1

27

26

DP

DP_1_GPIO8

DM_1_GPIO7

DM

55

54

CSPI_1

CSNI_1

52

39

35

38

53 51 50

47 43

45 44

46 41 40

VDDD

0.1μF

V_BUS

V_IN

5 m

(USB PD, 3.3-21 V, 5A)

Figure 10

EZ-PD™ CCG7DC CLA application diagram

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Applications

Table 3

Pin #

18

19

20

CLA GPIO pin mapping for application diagram in Figure 10

Pin name

Function

GPIO

P0.0

P0.1

P0.2

P0.3

P0.4

P1.0

P1.1

P1.2

P1.3

P2.0

P2.1

P1.4

P1.5

P1.6

P3.0

CLA

GPIO

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

General purpose IO, available for system level function

21

22

23

24

26

27

29

30

31

32

DP_0_GPIO5 Port 0: USB DP of Type-C port. Supports BC 1.2, QC,

P0_DP

P0_DM

P1_DM

P1_DP

GPIO

Apple Charging and AFC.

DM_0_GPIO6

DM_1_GPIO7 Port 1: USB DM of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC.

DP_1_GPIO8

GPIO9

General purpose IO, available for system level function

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

33

56

Connect to the host programmer’s SWDIO (data) for

programming the CCG7DC device

57

GPIO15

Connect to the host programmer’s SWDCLK (clock) for

programming the CCG7DC chip enable pin

P3.1

CHIP_EN

58

59

60

GPIO16

GPIO17

GPIO18

GPIO, available for system level function

Port 1: Thermistor

Port 0: Thermistor

P3.2

P3.3

P3.4

GPIO

P1_NTC[0]

P0_NTC[0]

Figure 11 illustrates a two Type-C port AC/DC power adapter application block diagram using CCG7DC. In this

application, CCG7DC will always be in DFP role supporting the charging of the device. It negotiates the power with

the connected device and uses the integrated buck controller to supply the required voltage and current. The

efficiency can be optimized by dynamically controlling the opto-coupler feedback and thereby regulate the buck

input voltage to the closest output voltage. This application can be configured to support the legacy charging

protocols - BC1.2 DCP, Qualcomm QC2.0/3.0, Apple Charging, and Samsung AFC.

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Applications

(USB PD, 3.3-21 V, 5A)

V_BUS

5

m

5

m

V_IN

VDDD

0.1 μF

VDDD

68

67

1

2

5

9

7

8

6

11

12

13

17

14

1 μF

4

3

PVDD_0

PGND_0

66

CSNI_0

CSPI_0

65

61

62

VIN

19

20

GPIO1

GPIO2

GND

CC1

CSP_0_GPIO1

GPIO2

VCCD

0.1 μF

10

COMP_0

15

16

CC1_0

CC2_0

390-pF

69

64

34

GND (EPAD)

GND

CC2

390-pF

AGND

GPIO13

33

CSN_1_GPIO13

GPIO9

29

30

DP

23

24

DP_0_GPIO5

DM_0_GPIO6

GPIO10

DM

GPIO3

GPIO4

21

22

GPIO3

GPIO4

18

GPIO0

VDDD

CSN_0_GPIO0

63

25

VDDD

10 μF

VDDD

CYPD727x-68LQXQ

0.1 μF

VDDD

1

2

3

0.1 μF 1 μF

1μF

AGND

48

49

PVDD_1

PGND_1

XRES

28

57

56

XRES

SWD_CLK

4

5

32

GND

GPIO15

GPIO14

GPIO12

CSP_1_GPIO12

GPIO11

SWD_DAT

31 GPIO11

PWM

P1_NTC[0]

P0_NTC[0]

58

GPIO16

CC1

CC2

37

36

59

60

CC1_1

CC2_1

GPIO17

GPIO18

390-pF

42

COMP_1

27

26

DP

DP_1_GPIO8

DM_1_GPIO7

DM

55

54

CSPI_1

CSNI_1

52

39

35

38

53 51 50

47 43

45 44 46

41 40

VDDD

0.1 μF

V_BUS

V_IN

5

m

5

m

(USB PD, 3.3-21V, 5A)

Figure 11

EZ-PD™ CCG7DC multi-port AC-DC adapter application diagram

Multi-port AC-DC adapter GPIO pin mapping for application diagram in Figure 11

Table 4

Pin #

Pin Name

Function

GPIO

P0.0

P0.1

P0.2

P0.3

P0.4

AC-DC

18 GPIO0

19 GPIO1

20 GPIO2

21 GPIO3

22 GPIO4

General purpose IO, available for system level function

GPIO

Port 0: USB DP of Type-C port.

23 DP_0_GPIO5

24 DM_0_GPIO6

26 DM_1_GPIO7

27 DP_1_GPIO8

P1.0

P1.1

P1.2

P1.3

P0_DP

P0_DM

P1_DM

P1_DP

Supports BC 1.2, QC, Apple Charging and AFC.

Port 0: USB DM of Type-C port.

Supports BC 1.2, QC, Apple Charging and AFC.

Port 1: USB DM of Type-C port.

Supports BC 1.2, QC, Apple Charging and AFC.

Port 1: USB DP of Type-C port.

Supports BC 1.2, QC, Apple Charging and AFC.

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Applications

Table 4

Pin #

Multi-port AC-DC adapter GPIO pin mapping for application diagram in Figure 11 ^(continued)

Pin Name

Function

GPIO

P2.0

P2.1

P1.4

P1.5

P1.6

AC-DC

29 GPIO9

30 GPIO10

31 GPIO11

32 GPIO12

33 GPIO13

General purpose IO, available for system level function

GPIO

Connect to the host programmer’s SWDIO (data) for

programming the EZ-PD™ CCG7DC device

Connect to the host programmer’s SWDCLK (clock) for

programming the EZ-PD™ CCG7DC chip enable pin

56 GPIO14

57 GPIO15

P3.0

P3.1

CHIP_EN

58 GPIO16

59 GPIO17

60 GPIO18

PWM output to dynamically control the opto-coupler feedback

Port 1: Thermistor

Port 0: Thermistor

P3.2

P3.3

P3.4

GPIO

P1_NTC[0]

P0_NTC[0]

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

6

Electrical specifications

6.1

Absolute maximum ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 5

Parameter

Absolute maximum ratings^[1]

Description

Min

Typ

Max

Unit

Description

Maximum input supply

voltage

VIN_MAJ

40

Maximum supply voltage

relative to VSS

Maximum supply voltage

relative to VSS

VDDD_MAJ

V5V_MAJ

6

–

V

Max _{VBUS_C}(P0/P1) voltage

relative to Vss

Max voltage on CC1 and

CC2 pins

–

VBUS_C_MAJ

24

VCC_PIN_ABS

VGPIO_ABS

Inputs to GPIO

–0.5

VDDD + 0.5

VGPIO_OVT_ABS OVT GPIO Voltage

6

25

–

IGPIO_ABS

Maximum current per GPIO –25

GPIO injectioncurrent, max

IGPIO_INJECTION for VIH > VDDD, and Min for –0.5

VIL < VSS

mA

V

Absolute max, current

injected per pin

0.5

Electrostatic discharge

human body model

(ESD HBM)

Electrostatic discharge

charged device model

(ESD CDM)

ESD_HBM

ESD_CDM

2000

500

All pins

–

Charged device model

ESD

LU

TJ

Pin current for latch-up

Junction temperature

–100

–40

100

125

mA

°C

–

Note

1. Usage above the absolute maximum conditions listed in Table 5 may cause permanent damage to the device.

Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The

maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the

device may not operate to specification.

Datasheet

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

Table 6

Pin#

Pin based absolute maximum ratings

Pin name

Absolute minimum (V) Absolute maximum (V)

1

2

3

SW1_0

-0.7

-0.5

-0.3

35

LG1_0^[2]

PVDD+0.5

0.3

PGND_0

4

5

PVDD_0

VDDD

PVDD+0.5

24

LG2_0^[2]

-0.5

-0.3

6

VOUT_0

7

8

9

SW2_0

24

HG2_0 (wrt SW2_0)^[2]

BST2_0 (wrt SW2_0)^[2]

COMP_0^[2]

-0.5

PVDD+0.5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

-0.5

-0.3

CSPO_0

CSNO_0

VBUS_IN_0

VBUS_C_0

CC1_0

24

-0.5

CC2_0

VBUS_CTRL_0

CSN_0_GPIO0^[2]

CSP_0_GPIO1^[2]

GPIO2^[2]

GPIO3^[2]

GPIO4^[2]

DP_0_GPIO5^[2]

DM_0_GPIO6^[2]

VDDD

32

PVDD+0.5

–

-0.5

6

DM_1_GPIO7^[2]

DP_1_GPIO8^[2]

XRES^[2]

PVDD+0.5

GPIO9^[2]

GPIO10^[2]

GPIO11^[2]

CSP_1_GPIO12^[2]

CSN_1_GPIO13^[2]

GND

–

Notes

2. Max voltage cannot exceed 6 V

3. Max absolute voltage wrt GND must not exceed 40 V

Datasheet

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

Table 6

Pin#

Pin based absolute maximum ratings ^(continued)

Pin name

Absolute minimum (V) Absolute maximum (V)

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

VBUS_CTRL_1

CC2_1

CC1_1

VBUS_C_1

VBUS_IN_1

CSNO_1

-0.5

32

24

-0.3

CSPO_1

COMP_1^[2]

BST2_1^[2](wrt SW2_1)

HG2_1^[2](wrt SW2_1)

SW2_1

-0.5

PVDD+0.5

-0.5

-0.3

-0.5

24

VOUT_1

LG2_1^[2]

PVDD_1

PGND_1

LG1_1^[2]

SW1_1

HG1_1^[2,3](wrt SW1_1)

BST1_1^[2,3](wrt SW1_1)

CSNI_1

PVDD+0.5

VDDD

0.3

PVDD+0.5

35

-0.3

-0.5

-0.7

-0.5

PVDD+0.5

-0.3

-0.5

40

CSPI_1

GPIO14/SWD_DAT^[2]

GPIO15/SWD_CLK^[2]

GPIO16^[2]

PVDD+0.5

GPIO17^[2]

GPIO18^[2]

VIN

VCCD

VDDD

GND

CSPI_0

CSNI_0

-0.3

–

40

–

6

–

40

-0.3

BST1_0^[2,3](wrt SW1_0)

HG1_0^[2,3](wrt SW1_0)

EPAD

–

-0.5

–

PVDD+0.5

–

Notes

2. Max voltage cannot exceed 6 V

3. Max absolute voltage wrt GND must not exceed 40 V

Datasheet

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

6.2

Device-level specifications

All specifications are valid for –40 °C  T_A 105 °C and T_J 125 °C, except where noted. Specifications are valid

for 3.0 V to 5.5 V except where noted.

6.2.1

DC specifications

Table 7

DC specifications (operating conditions)

Spec ID

Parameter

Description

Min

Typ

Max

Unit

Details/conditions

SID.PWR#1 VIN

Input supply voltage

4.0

24

Buck Boost Operating

input supply voltage

SID.PWR#1A VIN_BB

5.5

24

VDDD output with VIN

SID.PWR#2 VDDD_REG 5.5 V to 24 V,

4.6

–

5.5

Max load = 150 mA

V

–

VDDD output with VIN 4 V V_IN

-

SID.PWR#3 VDDD_MIN

SID.PWR#20 VBUS

SID.PWR#5 VCCD

–

21.5

–

to 5.5 V, Max load = 20mA 0.2

VBUS_C_0/1 valid range

3.3

Regulated output voltage

(for Core Logic)

–

1.8

100

10

External regulator

voltage bypass for VCCD

SID.PWR#16 CEFC_VCCD

SID.PWR#17 CEXC_VDDD

80

120

nF

µF

PowerSupplydecoupling

capacitor for VDDD

X5R ceramic

Bootstrap supply

capacitor (BST1_0,

BST1_1, BST2_0, BST2_1)

SID.PWR#18 CEXV

0.1

TA = 25°C, VIN = 12 V. CC

IOintransmit or receive,

no I/O sourcing current,

no VCONN load current,

–

Supply current at 0.4 MHz

switching frequency

SID.PWR#24 IDD_ACT

85

mA CPU at 24 MHz,

two PD ports active.

Buck-boost converter

ON, 3-nF gate driver

capacitance.

Deepsleep mode

Type-C not attached, CC

enabled for wakeup.

Rp connection should

be enabled for both PD

VIN = 12 V. CC wakeup on,

Type-C not connected

SID_DS1

SID_DS2

IDD_DS1

IDD_DS2

110

50

ports. TA = 25 °C.

All faults disabled.

–

µA

USB-PD disabled.

Wake-up from GPIO.

TA = 25 °C.

VIN = 12 V

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

Table 7

Spec ID

DC specifications (operating conditions) ^(continued)

Parameter

Description

Min

Typ

Max

Unit

Details/conditions

Type-C not attached, CC

enabled for wakeup. Rp

connection should be

V_IN= 12 V. CC wakeup on,

Type-C not connected

SID_DS3

IDD_DS3

–

450

–

µA enabled for both PD

ports. T_A= 25 °C.

All faults disabled

except VBAT-GND.

6.2.2

Table 8

Spec ID

CPU

CPU specifications

Parameter

Description

Min

Typ Max Unit

Details/conditions

–40 °C ≤ T_A≤ +105 °C,

SID.CLK#4

F_CPU

CPU input frequency

–

35

–

48

MHz

All V_DDD

–

Wakeup from deepsleep

mode

External reset pulse

width

SID.PWR#19 T_DEEPSLEEP

SYS.XRES#5 T_XRES

–

µs

5

–

Power-up to “ready to

SYS.FES#1 T_{_PWR_RDY}

5

25

ms

accept I²C/CC command”

6.2.3

GPIO

Table 9

GPIO DC specifications

Spec ID

Parameter

Description

Min

Typ

Max

Unit Details/conditions

Input voltage HIGH

threshold

Input voltage LOW

threshold

Output voltage HIGH

level

SID.GIO#9

V_{IH_CMOS}

0.7 × V_DDD

–

CMOS input

SID.GIO#10 V_{IL_CMOS}

–

V_DDD– 0.6

–

0.3 × V_DDD

–

V

I_OH= –4 mA,

–40 °C ≤ T_A≤ +105 °C

I_OL= 10 mA,

–40°C ≤ T_A≤ +105 °C

SID.GIO#7

SID.GIO#8

SID.GIO#2

SID.GIO#3

SID.GIO#4

V_{OH_3V}

V_{OL_3V}

Rpu

–

Output voltage LOW

level

0.6

Pull-up resistor when

enabled

Pull-down resistor

when enabled

Input leakage current

(absolute value)

3.5

5.6

–

8.5

k –40 °C ≤ T_A≤ +105 °C

Rpd

I_IL

2

nA +25 °C T_A, 3-V V_DDD

–40 °C ≤ T_A≤ +105 °C,

SID.GIO#5

SID.GIO#6

C_{PIN_A}

22

Capacitance on DP,

–

DM pins

Max pin capacitance

LVTTL input

pF

–40 °C ≤ T_A≤ +105 °C,

ALL V_DDD, All other

I/Os

C_PIN

3

–

7

SID.GIO#11 V_{IH_TTL}

SID.GIO#12 V_{IL_TTL}

2.0

–

0.8

V

–40 °C to +105 °C T_A

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

Table 9

Spec ID

GPIO DC specifications ^(continued)

Parameter

Description

Min

Typ

Max

Unit Details/conditions

Input hysteresis,

SID.GIO#13 V_HYSTTL

SID.GIO#14 V_HYSCMOS

100

V_DDD> 2.7 V

mV

–

LVTTL, V_DDD> 2.7 V

–

Input hysteresis

CMOS

0.1 × V_DDD

Table 10

Spec ID

GPIO AC specifications

Parameter

Description

Min Typ Max Unit Details/conditions

SID.GIO#16 T_RISEF

SID.GIO#17 T_FALLF

SID.GIO#18 T_RISES

SID.GIO#19 T_FALLS

Rise time in fast strong mode

Fall time in fast strong mode

Rise time in slow strong mode

Fall time in slow strong mode

GPIO F_OUT; 3.0 V V_DDD5.5 V,

fast strong mode

GPIO F_OUT; 3.0 V V_DDD5.5 V,

slow strong mode.

GPIO input operating

frequency; 3.0 V V_DDD5.5 V.

2

12

60

ns

10

C

_load= 25 pF,

–40 °C ≤ T_A≤ +105 °C

–

SID.GIO#20 F_{GPIO_OUT1}

SID.GIO#21 F_{GPIO_OUT2}

SID.GIO#22 F_{GPIO_IN}

16

7

–

MHz

16

–40 °C ≤ T_A≤ +105 °C

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Electrical specifications

Table 11

GPIO OVT DC specifications

Parameter

Details/

Spec ID

Description

Min Typ Max Unit

conditions

Max / Min current in

to any input or

output, pin-to-pin,

pin-to-supply

GPIO_20VT

SID.GPIO_20VT_GIO#4 GPIO_20VT_I_LU latch up current –140

limits

140 mA

GPIO_20VT

SID.GPIO_20VT_GIO#5 GPIO_20VT_RPU Pull-up resistor

value

GPIO_20VT

–40 °C ≤ T_A≤ +105 °C,

3.5

8.5

2

kΩ

All V_DDD

SID.GPIO_20VT_GIO#6 GPIO_20VT_RPD Pull-down

resistor value

GPIO_20VT

Input leakage

SID.GPIO_20VT_GIO#16 GPIO_20VT_IIL

current

nA +25 °C T_A, 3-V V_DDD

–

(absolute value)

GPIO_20VT pin

SID.GPIO_20VT_GIO#17 GPIO_20VT_CPIN

capacitance

-40 °C ≤ T_A≤ +105 °C,

10

–

pF

All V_DDD

GPIO_20VT

VDDD

- 0.6

SID.GPIO_20VT_GIO#33 GPIO_20VT_Voh Output voltage

I_OH= -4 mA

high level.

GPIO_20VT

Output Voltage

low level.

SID.GPIO_20VT_GIO#36 GPIO_20VT_Vol

–

0.6

I_OL= 8 mA

V

GPIO_20VT_Vih_ GPIO_20VT

–40 °C ≤ T_A≤ +105 °C,

SID.GPIO_20VT_GIO#41

SID.GPIO_20VT_GIO#42

2

–

LVTTL

LVTTL input

All V_DDD

GPIO_20VT_Vil_ GPIO_20VT

0.8

LVTTL

LVTTL input

GPIO_20VT

Input hysteresis 100

LVTTL

GPIO_20VT_Vhyst

tl

–40 °C ≤ T_A≤ +105 °C,

All V_DDD

SID.GPIO_20VT_GIO#43

–

mV

mA

–

GPIO_20VT

GPIO_20VT_ITOT

SID.GPIO_20VT_GIO#45 _

GPIO

Maximum total

V (GPIO_20VT pin)

> V_DDD

–

95

sink pin current

to ground

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

Table 12

GPIO OVT AC specifications

Details/

Spec ID

Parameter

Description

Min Typ Max Unit

conditions

GPIO_20VT rise time in

fast strong mode

GPIO_20VT fall time in

fast strong mode

GPIO_20VT rise time in

slow strong mode

GPIO_20VT fall time in

slow strong mode

GPIO_20VT GPIO Fout;

3 V  V_DDD 5.5 V.

Fast strong mode.

GPIO_20VT GPIO Fout;

3 V V_DDD5.5V. Slow

strong mode.

SID.GPIO_20VT_70

SID.GPIO_20VT_71

GPIO_20VT_TriseF

GPIO_20VT_TfallF

1

15

70

ns

SID.GPIO_20VT_GIO#46 GPIO_20VT_TriseS

SID.GPIO_20VT_GIO#47 GPIO_20VT_TfallS

10

All V_DDD

,

C_load= 25 pF

–

GPIO_20VT_FGPIO

SID.GPIO_20VT_GIO#48

_OUT1

33

7

GPIO_20VT_FGPIO

SID.GPIO_20VT_GIO#50

_OUT3

–

MHz

GPIO_20VT GPIO input

operating frequency;

3 V V_DDD5.5 V

GPIO_20VT_FGPIO

SID.GPIO_20VT_GIO#52

_IN

8

All V_DDD

6.2.4

XRES

Table 13

XRES DC specifications

Details/

Spec ID

Parameter

Description

Input voltage HIGH

Min

Typ

Max

Unit

conditions

SID.XRES#1

V_{IH_XRES}

threshold on XRES 0.7 × V_DDD

–

V

CMOS input

Input voltage LOW

threshold on XRES

–

SID.XRES#2

SID.XRES#3

SID.XRES#4

V_{IL_XRES}

C_{IN_XRES}

V_HYSXRES

0.3 × V_DDD

Input capacitance

on XRES pin

–

7

–

pF

–

Input voltage

hysteresis on XRES

0.05 × V_DDD

mV

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Electrical specifications

6.3

Digital peripherals

The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.

6.3.1

Pulse-width modulation (PWM) for GPIO pins

Table 14

PWM AC specifications

Spec ID

Parameter

Description

Min Typ Max Unit

Details/conditions

SID.TCPWM.1 TCPWM_FREQOperating frequency

–

Fc

MHz Fc max = CLK_SYS

Minimum possible width of

overflow, underflow, and

CC (counter equals

Output trigger pulse

SID.TCPWM.3 T_PWMEXT

width

2/Fc

compare value) outputs

–

ns

Minimum time between

successive counts

Minimum pulse width of

PWM output

SID.TCPWM.4 T_CRES

Resolution of counter

PWM resolution

1/Fc

SID.TCPWM.5 PWM_RES

6.3.2

Table 15

I²C

Fixed I²C AC specifications

Spec ID

Parameter

Description

Bit rate

Min Typ Max

Unit

Details/conditions

SID153

F_I2C1

–

1

Mbps

–

6.3.3

UART

Table 16

Fixed UART AC specifications

Spec ID

Parameter

Description

Bit rate

Min Typ Max

Unit

Details/conditions

SID162

F_UART

–

1

Mbps

–

6.3.4

SPI

Table 17

Fixed SPI AC specifications

Spec ID

Parameter

Description

Min Typ Max Unit

Details/conditions

SPI operating frequency

(Master; 6X oversampling)

SID166

F_SPI

–

8

MHz

–

Table 18

Fixed SPI slave mode AC specifications

Spec ID

Parameter

Description

Min Typ

Max

Unit

Details/conditions

MOSI valid before Sclock

capturing edge

SID170

SID171

T_DMI

40

–

MISO valid after Sclock

driving edge

48 +

(3 × T_CPU

T_DSO

T_CPU= 1/F_CPU

)

–

MISO valid after Sclock

driving edge in Ext Clk

mode

SID171A

T_{DSO_EXT}

–

48

–

ns

Previous MISO data hold

time

–

SID172

T_HSO

0

SSEL valid to first SCK

valid edge

SID172A

T_SSELSCK

100

Datasheet

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Electrical specifications

Table 19

Spec ID

Fixed SPI master mode AC specifications

Parameter

Description

Min Typ Max Unit

Details/conditions

MOSI valid after SClock

driving edge

SID167

SID168

SID169

T_DMO

–

20

0

15

–

MISO valid before SClock

capturing edge

Full clock,

T_DSI

–

ns

late MISO sampling

–

Previous MOSI data hold

time

Referred to slave

capturing edge

T_HMO

6.3.5

Memory

Table 20

Flash AC specifications

Spec ID

Parameter Description

Min Typ Max Unit

Details/conditions

Row (block) write time

(erase and program)

SID.MEM#2 FLASH_WRITE

20

–40 °C ≤ T_A≤ +85 °C,

All V_DDD

SID.MEM#1 FLASH_ERASE Row erase time

15.5

ms

7

–

FLASH_ROW_ Row program time after

SID.MEM#5

PGM

erase

SID178

SID180

T_BULKERASE

T_DEVPROG

Bulk erase time (32 KB)

Total device program time

35

–

7.5

s

25 °C ≤ T_A≤ 55 °C,

SID.MEM#6 FLASH__ENPBFlash write endurance

100k

20

cycles

All V_DDD

Flash retention, T_A≤ 55 °C,

SID182

F_RET1

F_RET2

–

100K P/E cycles

years

–

Flash retention, T_A≤ 85 °C,

10K P/E cycles

SID182A

10

Datasheet

35

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

6.4

System resources

6.4.1

Power-on-reset (POR) with brown-out

Table 21

Imprecise power-on reset (IPOR)

Spec ID

Parameter

V_RISEIPOR

Description

Min Typ Max Unit

Details/conditions

SID185

SID186

POR Rising trip voltage 0.80

POR Falling trip voltage 0.70

1.50

1.4

–40 °C ≤T_A≤ +105 °C,

–

V

All V_DDD

.

V_FALLIPOR

Table 22

Precise POR

Parameter

Spec ID

Description

Min Typ Max Unit

Details/conditions

Brown-out detect (BOD)

trip voltage in

SID190

SID192

V_FALLPPOR

V_FALLDPSLP

1.48

1.1

1.62

1.5

–40 °C ≤ T_A≤ +105 °C,

Active/Sleep modes

–

V

All V_DDD

.

BOD trip voltage in

deepsleep mode

6.4.2

SWD interface

Table 23

SWD interface specifications

Spec ID

Parameter

F_SWDCLK1

Description

Min

Typ

Max

Unit Details/conditions

SID.SWD#1

SID.SWD#2

SID.SWD#3

SID.SWD#4

SID.SWD#5

3.0 V  V_DDIO 5.5 V

–

14

MHz

T_SWDI_SETUP

T_SWDI_HOLD

T_SWDO_VALID

T_SWDO_HOLD

0.25 × T

–

T = 1/f SWDCLK

ns

–

1

0.50 × T

–

6.4.3

Internal main oscillator

Table 24

IMO AC specifications

Spec ID

Parameter

F_IMOTOL

T_STARTIMO

F_IMO

Description

Min

–

Typ Max Unit

Details/conditions

Frequency variation at

48 MHz (trimmed)

3.0 V ≤ V_DDD< 5.5 V.

–40 °C ≤ T_A≤ 105 °C.

SID.CLK#13

±2

%

–

SID226

IMO start-up time

IMO frequency

7

µs

–40 °C ≤ T_A≤ +105 °C,

All V_DDD

.

SID.CLK#1

24

48

MHz

6.4.4

Internal low-speed oscillator

Table 25

Spec ID

SID234

SID238

SID.CLK#5

ILO AC specifications

Parameter

T_STARTILO1

T_ILODUTY

F_ILO

Description

ILO start-up time

ILO duty cycle

Min

–

40

20

Typ Max Unit

Details/conditions

–

50

40

2

60

80

ms

%

–40 °C ≤ T_A≤ +105 °C,

All V_DDD

.

ILO frequency

kHz

–

Datasheet

36

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

6.4.5

PD

Table 26

PD DC specifications

Details/

Spec ID

Parameter

Description

Min Typ Max Unit

conditions

Transmitter output high

voltage

SID.DC.cc_shvt.1 vSwing

1.05

–

1.2

V

Transmitter output low

voltage

SID.DC.cc_shvt.2 vSwing_low

0.075

Transmitter output

impedance

SID.DC.cc_shvt.3 zDriver

SID.DC.cc_shvt.4 zBmcRx

SID.DC.cc_shvt.5 Idac_std

33

10

64

75

–



Receiver input impedance

M

Source current for USB

standard advertisement

96

Source current for 1.5 A at 5 V

SID.DC.cc_shvt.6 Idac_1p5a

SID.DC.cc_shvt.7 Idac_3a

166

304

194

356

µA

Source current for 3 A at 5 V

Pull down termination

resistance when acting as

UFP (upstream facing port)

SID.DC.cc_shvt.8 Rd

4.59

5.61

–

k

CC impedance to ground

when disabled

SID.DC.cc_shvt.10 zOPEN

108

–

CC voltages on DFP

side-standard USB

SID.DC.cc_shvt.11 DFP_default_0p2

0.15

0.25

V

SID.DC.cc_shvt.12 DFP_1.5A_0p4

SID.DC.cc_shvt.13 DFP_3A_0p8

SID.DC.cc_shvt.14 DFP_3A_2p6

CC voltages on DFP side-1.5 A 0.35

CC voltages on DFP side-3 A 0.75

CC voltages on DFP side-3 A 2.45

0.45

0.85

2.75

CC voltages on UFP

0.61

SID.DC.cc_shvt.15 UFP_default_0p66

0.7

side-standard USB

SID.DC.cc_shvt.16 UFP_1.5A_1p23

SID.DC.cc_shvt.17 Vattach_ds

SID.DC.cc_shvt.18 Rattach_ds

SID.DC.cc_shvt.19 VTX_step

CC voltages on UFP side-1.5 A 1.16

1.31

0.6

Deepsleep attach threshold

Deepsleep pull-up resistor

TX Drive voltage step size

0.3

10

80

%

50

k

mV

120

Datasheet

37

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

6.4.6

Analog-to-digital converter

Table 27

ADC DC specifications

Spec ID

SID.ADC.1 Resolution

Parameter

Description

ADC resolution

Min

–

Typ

8

Max

–

Unit

Bits

Details/conditions

–

Reference voltage

generated from

bandgap

Reference voltage

generated from V_DDD

Reference voltage

generated from

bandgap

SID.ADC.2 INL

Integral non-linearity

–1.5

1.5

2.5

SID.ADC.3 DNL

Differential non-linearity –2.5

Gain error –1.5

LSB

–

SID.ADC.4 Gain Error

1.5

Reference voltage

SID.ADC.5 VREF_ADC1 Reference voltage of ADC V_DDDmin

SID.ADC.6 VREF_ADC2 Reference voltage of ADC 1.96

V_DDDmax

2.04

generated from V_DDD

V

Reference voltage

generated from

deepsleep reference

2.0

6.4.7

HS CSA

Table 28

HS CSA DC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

CSA accuracy 5 mV < Vsense

< 10 mV

CSA accuracy 10 mV < Vsense

< 15 mV

SID.HSCSA.1 Csa_Acc1

SID.HSCSA.2 Csa_Acc2

-15

-10

15

10

CSA accuracy 15 mV < Vsense

< 25 mV

CSA accuracy 25 mV < Vsense

CSA SCP at 6A with 5-mΩ sense

resistor

CSASCP at 10A with 5-mΩsense

resistor

CSA OCP at 1A with 5-mΩ sense

resistor

SID.HSCSA.3 Csa_Acc3

SID.HSCSA.4 Csa_Acc4

SID.HSCSA.7 Csa_SCP_Acc1

-5

-3

5

3

–

%

Active mode

-10

10

SID.HSCSA.8 Csa_SCP_Acc2

SID.HSCSA.9 Csa_OCP_1A

SID.HSCSA.10 Csa_OCP_5A

104 130 156

123 130 137

CSA OCP for 5A with 5-mΩsense

resistor

Table 29

Spec ID

HS CSA AC specifications

Parameter

Description

Min Typ Max Unit Details/conditions

Delay from SCP threshold trip to

external NFET power gate turn

off

SID.HSCSA.AC.1 T_{SCP_GATE}

3.5

8

1-nF NFET gate

3-nF NFET gate

–

µs

Delay from SCP threshold trip to

SID.HSCSA.AC.2 T_{SCP_GATE_1}external NFET power gate turn

off

Datasheet

38

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

6.4.8

UV/OV

Table 30

UV/OV specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

Overvoltage threshold

Accuracy, 4 V to 11 V

Overvoltage threshold

Accuracy, 11 V to 21.5 V

Undervoltage threshold

Accuracy, 3 V to 3.3 V

Undervoltage threshold

Accuracy, 3.3 V to 4.0 V

SID.UVOV.1

SID.UVOV.2

SID.UVOV.3

SID.UVOV.4

SID.UVOV.5

V_THOV1

V_THOV2

V_THUV1

V_THUV2

V_THUV3

–3

–3.2

–4

3

3.2

4

–

%

Active mode

–3.5

–3

3.5

3

Undervoltage threshold

Accuracy, 4.0 V to 21.5 V

6.4.9

VCONN switch

Table 31

VCONN switch DC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

VCONN output voltage with

20 mA load current

Connector side pin leakage

current

DC.VCONN.1 VCONN_OUT

DC.VCONN.2 I_LEAK

4.5

–

5.5

10

V

–

µA

–

VCONN over-current

protection threshold

DC.VCONN.3 I_OCP

22.5

30 37.5 mA

Table 32

Spec ID

VCONN switch AC specifications

Parameter

Description

Min Typ Max Unit Details/conditions

AC.VCONN.1 T_ON

AC.VCONN.2 T_OFF

VCONN switch turn-on time

VCONN switch turn-off time

600

10

–

µs

–

6.4.10

V_BUS

Table 33

V_BUSdischarge specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

20-V NMOS ON resistance for

DS = 1

20-V NMOS ON resistance for

DS = 2

20-V NMOS ON resistance for

DS = 4

20-V NMOS ON resistance for

DS = 8

SID.VBUS.DISC.1 R1

SID.VBUS.DISC.2 R2

SID.VBUS.DISC.3 R4

SID.VBUS.DISC.4 R8

SID.VBUS.DISC.5 R16

500

250

125

62.5

31.25

–

2000

1000

500

250

125

10



Measured at 0.5 V

–

20-V NMOS ON resistance for

DS = 16

Vbus_stop_ Error percentage of final

When VBUS is

discharged to 5 V

SID.VBUS.DISC.6

%

error

VBUS value from setting

Datasheet

39

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

6.4.11

Voltage regulation

Table 34

Voltage regulation DC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

SID.DC.VR.1 VOUT

VBUS_IN output voltage range 3.3

–

21.5

V

VBUS_IN voltage regulation

accuracy

SID.DC.VR.2 VR

–

±3

±5

%

–

VIN Supply below which chip

will get reset

SID.DC.VR.3 VIN_UVLO

1.7

–

3.0

V

Table 35

Spec ID

SID.VREG.1 T_START

Voltage regulator specifications

Parameter

Description

Min Typ Max Unit Details/conditions

200 µs

Total startup time for the

regulator supply outputs

–

6.4.12

VBUS gate driver

Table 36

VBUS gate driver DC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

Gate to source overdrive during

ON condition

SID.GD.1

SID.GD.2

SID.GD.5

GD_VGS

4.5

5

10

V

NFET driver is ON

Applicable on

Resistance when pull-down

enabled

GD_RPD

GD_drv

–

2

k VBUS_CTRL to turn

off external NFET

–

Programmable typical gate

current

0.3

9.75 µA

–

Table 37

Spec ID

VBUS gate driver AC Specifications

Parameter

Description

Min Typ Max Unit Details/conditions

VBUS_CTRL LOW to HIGH (1V to

VBUS + 1 V) with 3-nF external

capacitance

VBUS_CTRL HIGH to LOW (90% to

10%) with 3-nF external

capacitance

SID.GD.3

SID.GD.4

T_ON

2

–

5

7

10 ms V_{BUS_IN}= 5 V

T_OFF

–

µs V_{BUS_IN}= 21.5 V

6.4.12.1

Table 38

Spec ID

PWM.1

PWM controller

Buck-boost PWM controller specifications

Parameter

F_SW

Description

Min Typ Max Unit Details/conditions

Switching frequency

150

–

600 kHz

Spread spectrum frequency

dithering span

PWM.2

PWM.3

PWM.4

FSS

10

%

–

Ratio_Buck_

BB

Ratio_Boost_

BB

Buck to buck boost ratio

Boost to buck boost ratio

–

1.16

0.84

–

Datasheet

40

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Electrical specifications

6.4.12.2

Table 39

Spec ID

NFET gate driver

Buck-boost NFET gate driver specifications

Parameter

Description

Min Typ Max Unit Details/conditions

Top-side gate driver

DR.1

DR.2

DR.3

DR.4

DR.5

DR.6

R_HS_PU

2

on-resistance - Gate pull-up

Top-side gate driver

on-resistance - Gate pull-down

Bottom-side gate driver

on-resistance - Gate pull-up

Bottom-side gate driver

on-resistance - Gate pull-down

Dead time before high-side rising

edge

Dead time before low-side rising

edge

R_HS_PD

R_LS_PU

R_LS_PD

Dead_HS

Dead_LS

1.5

Ω

2

1.5

–

30

ns

DR.7

DR.8

DR.9

DR.10

Tr_HS

Tf_HS

Tr_LS

Tf_LS

Top-side gate driver rise time

Top-side gate driver fall time

Bottom-side gate driver rise time

Bottom-side gate driver fall time

25

20

25

20

6.4.12.3

LS-SCP

Table 40

LS-SCP DC specifications

Spec ID

Parameter Description

Min Typ Max Unit

Details/conditions

Using differential inputs

(CSN_1_GPIO12,

CSP_1_GPIO13 or

CSP_0_GPIO0,

Short circuit current

detect @ 6A

SID.LSSCP.DC.1 SCP_6A

SID.LSSCP.DC.1A SCP_6A_SE

SID.LSSCP.DC.2 SCP_10A

SID.LSSCP.DC.2A SCP_10A_SE

5.4

4.5

9

6

6.6

7.5

11

CSN_0_GPIO1)

Using single ended inputs

(CSP_1_GPIO13 or

CSP_0_GPIO0)andinternal

ground

Short circuit current

detect @ 6A

A

Using differential inputs

(CSN_1_GPIO12,

CSP_1_GPIO13 or

CSP_0_GPIO0,

Short circuit current

detect @10A

10

CSN_0_GPIO1)

Using single ended inputs

(CSP_1_GPIO13 or

CSP_0_GPIO0)andinternal

ground

Short circuit current

detect @10A

7.5 10 12.5

6.4.12.4

Table 41

Spec ID

Thermal specifications

Parameter

OTP

Description

Thermal shutdown

Min Typ Max Unit

120 125 130 °C

Details/conditions

SID.OTP.1

–

Datasheet

41

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC control-

ler

Ordering information

7

Ordering information

Table 42 lists the EZ-PD™ CCG7DC part numbers and features.

Table 42

EZ-PD™ CCG7DC ordering information

Termination

Application

Switching

frequency

Package

type

MPN

Role

resistor

CYPD7271-68LQXQ Dual-port USB-C R_P

PD AC-DC power

DFP

(Power source

only)

150 kHz - 600 kHz 68-pin QFN

adapter/cigarette

lighter adapter

(CLA)

7.1

Ordering code definitions

CY

X

PD

XX XX

X

XX

X

T: Tape and reel (optional)

Grade/ temperature range: Q = Extended industrial grade (–40 °C to + 105 °C)

Lead: X = Pb-free

Package type: LQ = QFN

Number of pins in the package

Application and feature combination designation

Number of Type-C ports: 1 = 1 port, 2 = 2 port

Product type: 7 = Seventh-generation product family

Marketing code: PD = Power delivery product family

Company ID: CY = CYPRESS (An Infineon company)

Datasheet

42

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Packaging

8

Packaging

Table 43

Parameter

T_J

T_JA

T_JB

Package characteristics

Description

Operating junction temperature

Package _JA

Conditions

Min

–40

Typ

Max

125

14.8

4.3

Unit

°C

°C/W

25

–

Package _JB

T_JC

Package _JC

12.9

Table 44

Solder reflow peak temperature

Maximum time within 5°C of

peak temperature

30 seconds

Package

Maximum peak temperature

260°C

68-pin QFN

Table 45

Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2

Package

MSL

68-pin QFN

MSL 3

Datasheet

43

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Package diagram

9

Package diagram

NOTES:

DIMENSIONS

SYMBOL

e

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. N IS THE TOTAL NUMBER OF TERMINALS.

MIN.

0.30

NOM.

0.40 BSC

68

17

0.40

MAX.

0.50

3

DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED

BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS

THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE

DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.

ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.

N

ND

L

b

D2

E2

D

0.15

5.60

0.20

5.70

0.25

5.80

4

5

6

PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.

COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK

SLUG AS WELL AS THE TERMINALS.

5.70

8.00 BSC

E

A

8.00 BSC

7. JEDEC SPECIFICATION NO. REF. : N/A.

8. INDEX FEATURE CAN EITHER BE AN OPTION 1 : "MOUSE BITE" OR

OPTION 2 : CHAMFER.

-

0.65

0.05

A1

A3 (Option 1)

A3 (Option 2)

R

0.00

0.203 REF

0.152 REF

0.20 TYP

0.75 MIN

K

002-31802 *C

Figure 12

68-QFN package drawing (8 x 8 mm)

Datasheet

44

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Acronyms

10

Acronyms

Table 46

Acronyms used in this document

Acronym

Description

ADC

analog-to-digital converter

AFC

Samsung adaptive fast charging

Arm^

advanced RISC machine, a CPU architecture

central processing unit

CPU

CSA

current sense amplifier

DAC

digital-to-analog converter

forced continuous current/conduction mode

general-purpose input/output

high-side driver

FCCM

GPIO

HSDR

I²C, or IIC

IDAC

I/O

inter-integrated circuit, a communications protocol

current DAC

input/output, see also GPIO

low-side driver

LSDR

MCU

OCP

microcontroller unit

overcurrent protection

OVP

overvoltage protection

PD

power delivery

POR

power-on reset

PSoC™

PSM

Programmable system-on-chip

pulse skipping mode

PWM

RAM

pulse-width modulator

random-access memory

serial peripheral interface, a communications protocol

static random access memory

timer/counter/PWM

SPI

SRAM

TCPWM

a new standard with a slimmer USB connector and a reversible cable, capable of sourcing up to

100 W of power

Type-C

UART

UFP

universal asynchronous transmitter receiver, a communications protocol

upstream facing port

UVP

undervoltage protection

USB

UVLO

ZCD

universal Serial Bus

under-voltage lockout

zero crossing detector

Datasheet

45

002-32352 Rev. *C

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EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Document conventions

11

Document conventions

11.1

Units of measure

Table 47

Units of measure

Symbol

Unit of measure

°C

degrees Celsius

hertz

Hz

KB

1024 bytes

kHz

k

Mbps

MHz

M

Msps

µA

kilohertz

kilo ohm

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

microsecond

microvolt

µF

µs

µV

µW

mA

m

ms

mV

nA

microwatt

milliampere

milliohm

millisecond

millivolt

nanoampere

nanosecond

ohm

ns



pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

samples per second

Datasheet

46

002-32352 Rev. *C

2022-10-19

EZ-PD™ CCG7DC dual-port USB-C power delivery and DC-DC controller

Revision history

Document

Date

Description of changes

version

*C

2022-10-19

Publish to web.

Datasheet

47

002-32352 Rev. *C

2022-10-19

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

For further information on the product, technology,

delivery terms and conditions and prices please

contact your nearest Infineon Technologies office

(www.infineon.com).

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”).

Edition 2022-10-19

Published by

Infineon Technologies AG

81726 Munich, Germany

With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement of

intellectual property rights of any third party.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Except as otherwise explicitly approved by Infineon

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Technologies in

authorized

a written document signed by

Do you have a question about this

document?

Go to www.infineon.com/support

representatives

of

Infineon

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of the

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

Document reference

002-32352 Rev. *C

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.


型号：	CYPD7271-68LQXQ
厂家：	Infineon
描述：	EZ-PD™ CCG7DC CYPD7271-68LQXQ is the tray packing type option belonging to the CCG7DC family of highly integrated dual-port USB-C Power Delivery solutions with integrated buck-boost controllers. 光电二极管
文件：	总48页 (文件大小：423K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYPD7271-68LQXQ [INFINEON]

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