CYPD3177-24LQXQ [INFINEON]
EZ-PD™ Barrel Connector Replacement (BCR) CYPD3177-24LQXQ is the tray packing type option of EZ-PD™ BCR family, the highly-integrated USB Type-C port controllers for power sink applications. It targets electronic devices using legacy barrel connectors up to 100 W or USB micro-B for power inputs, enabling product designers to replace these incompatible connectors with USB-C.;![CYPD3177-24LQXQ](http://pdffile.icpdf.com/pdf2/p00366/img/icpdf/CYPD3177-24L_2240103_icpdf.jpg)
型号: | CYPD3177-24LQXQ |
厂家: | ![]() |
描述: | EZ-PD™ Barrel Connector Replacement (BCR) CYPD3177-24LQXQ is the tray packing type option of EZ-PD™ BCR family, the highly-integrated USB Type-C port controllers for power sink applications. It targets electronic devices using legacy barrel connectors up to 100 W or USB micro-B for power inputs, enabling product designers to replace these incompatible connectors with USB-C. 光电二极管 |
文件: | 总24页 (文件大小:370K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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EZ-PD™ BCR Datasheet
USB Type-C Port Controller for Power Sinks
General Description
EZ-PD™ BCR is Cypress’ highly-integrated pre-programmed USB Type-C port controller targeting electronic devices that have legacy
barrel connectors (up to 100W) or USB micro-B connectors for power such as drones, smart speakers, power tools, and other
rechargeable devices. EZ-PD BCR complies with the latest USB Type-C and USB Power Delivery (PD) standards and enables users
to quickly convert their devices from being powered through a barrel connector to being powered via the USB-C connector with few
external components and no firmware development is required. EZ-PD BCR integrates a complete USB Type-C transceiver, USB PD
policy manager, a load switch controller with a soft start, all termination resistors required for a USB Type-C port, and system-level
ESD protection. It is available in a 24-pin QFN package.
Features
Clocks and Oscillators
■ Integrated oscillator eliminating the need for external clock
USB Type-C and USB-PD Support
■ Supports USB PD3.0 Revision 2.0 Version 1.3
■ Configurable resistor RD
Power
■ Supports one USB Type-C port
■ 3.0-V to 24.5-V operation (30-V tolerant)
5V Legacy Charging
System-Level ESD Protection
■ Supports 5-V operation when connected to USB Type-A ports
■ On CC, VBUS_IN, DC_OUT, D+, D-, HPI_SDA and HPI_SCL
pins
System-Level Fault Protection
■ VBUS to CC Short Protection
■ ± 8-kV contact discharge and ±15-kV air gap discharge based
on IEC61000-4-2 level 4C
■ On-chip overvoltage protection (OVP)
Packages
■ 24-pin QFN package
■ Supports extended industrial temperature range
(–40°C to +105°C)
Logic Block Diagram
EZ-PD BCR
CC Transceiver
CC
Integrated Digital Blocks
I2C Interface
Fault Indicator
System
Resources
USB PD Subsystem
Load Switch
Controller
VBUS to CC Short
Circuit Protection
VBUS Range & Current
Limit Monitor
Charger Detect
Cypress Semiconductor Corporation
Document Number: 002-25383 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 18, 2021
EZ-PD™ BCR Datasheet
Contents
Functional Overview ........................................................3
USB-PD Subsystem ....................................................3
Integrated I2C Blocks ..................................................3
Power Systems Overview ................................................4
Pinouts ..............................................................................5
Application Overview .......................................................7
Electrical Specifications ................................................10
Absolute Maximum Ratings .......................................10
Device-Level Specifications ......................................10
Digital Peripherals .....................................................13
System Resources ....................................................13
Ordering Information ......................................................18
Ordering Code Definitions .........................................18
Packaging ........................................................................19
Acronyms ........................................................................21
Document Conventions .................................................21
Units of Measure .......................................................21
Document History Page .................................................22
Sales, Solutions, and Legal Information ......................23
Worldwide Sales and Design Support .......................23
Products ....................................................................23
PSoC® Solutions ......................................................23
Cypress Developer Community .................................23
Technical Support .....................................................23
Document Number: 002-25383 Rev. *B
Page 2 of 23
EZ-PD™ BCR Datasheet
Sink Load Switch Controller on VBUS Path
Functional Overview
The EZ-PD BCR device has an integrated load switch controller
to drive external PFETs on the VBUS sink path. This load switch
controller has a soft start feature that limits the in-rush current
flowing through the sink power path when the system is
connected to an external load and powered on.
USB-PD Subsystem
The USB-PD subsystem provides the interface to the USB
Type-C USB port. This subsystem comprises a high-voltage
regulator, OVP, and supply switch blocks. This subsystem also
includes all ESD protection required and supported on the USB
Type-C port.
SAFE_PWR_EN Gate Driver
The EZ-PD BCR device has a SAFE_PWR_EN gate driver that
can be used to drive an alternate load switch/FET. It is enabled
whenever the EZ-PD BCR device is unable to negotiate the
requested power contract. In such a scenario, the EZ-PD BCR
device negotiates a 5-V/900-mA contract which can be delivered
through the SAFE_PWR_EN FET to an alternate power rail in
the system. This allows the system to operate in a limited mode
when the requested power is unavailable through the USB
Type-C port.
USB-PD Physical Layer
The USB-PD Physical Layer consists of a transmitter and
receiver that communicate BMC-encoded data over the CC
channel based on the USB PD 3.0 standard. All communication
is half-duplex. The Physical Layer or PHY practices collision
avoidance to minimize communication errors on the channel.
The USB-PD block includes the termination resistor RD and its
switch as required by the USB-PD spec. RD resistor is required
to implement connection detection, plug orientation detection,
and for establishing USB UFP role.
VBUS Discharge FETs
The EZ-PD BCR device also has an integrated VBUS discharge
FET used to discharge VBUS to meet the USB-PD specification
timing on a detach condition.
According to the USB Type-C spec, a USB Type-C controller
such as the EZ-PD BCR device must present certain termination
resistors depending on its role in its unpowered state. The Sink
role requires RD resistor to be present on the CC pins even in an
unpowered state. To implement this function, EZ-PD BCR has a
dead battery RD resistor bonded to both the CC pins.
Integrated I2C Blocks
The EZ-PD BCR device has an I2C slave interface that can be
connected to an I2C host. The slave address is 0x08. Contact
Cypress Technical Support for further details related with EZ-PD
BCR HPI specification.
The I2C interface is capable of operating at speeds of up to
1 Mbps (Fast-mode Plus). The I2C interface is also compatible
with the I2C Standard-mode, Fast-mode, and Fast-mode Plus
devices as defined in the NXP I2C-bus specification and user
manual (UM10204). The I2C bus I/Os are implemented with
GPIO in open-drain modes.
VBUS Overvoltage Protection
The EZ-PD BCR device has an integrated hardware block for
VBUS OVP with configurable thresholds and response times on
the USB Type-C port.
VBUS Short Protection
The EZ-PD BCR device provides VBUS short protection on CC1
an CC2 pins. These pins are protected from accidental shorts to
high-voltage VBUS. Accidental shorts may occur because the
CC1 and CC2 pins are placed next to the VBUS pins in the USB
Type-C connector. A USB-PD controller without the high-voltage
VBUS short protection will be damaged in the event of accidental
shorts. When the protection circuit is triggered, the EZ-PD BCR
device can handle up to 17 V forever and between 17 V to
22 VDC for 1000 hours on the CC1 and CC2 pins. When a VBUS
short event occurs on the CC pins, a temporary high-ringing
voltage is observed due to the RLC elements in the USB Type-C
cable. Without the EZ-PD BCR device connected, this ringing
voltage can be twice (44 V) the maximum VBUS voltage
(21.5 V). However, when the EZ-PD BCR device is connected, it
is capable of clamping temporary high-ringing voltage and
protecting the CC pin using IEC ESD protection diodes.
The I2C interface is not completely compliant with the I2C spec
in the following aspects:
■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
■ Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.
Document Number: 002-25383 Rev. *B
Page 3 of 23
EZ-PD™ BCR Datasheet
Power Systems Overview
The EZ-PD BCR device can operate from two possible external supply sources: VBUS_IN (3.0 V–24.5 V) or VDDD (2.7 V–5.5 V).
When powered through VBUS_IN, the internal regulator generates VDDD of 3.3 V for chip operation. The regulated supply, VDDD,
is either used directly inside some analog blocks or further regulated down to VCCD (1.8 V), which powers majority of the core using
the regulators. Refer to the application diagram (see Figure 3) for capacitor connections.
Figure 1. Power System Requirement Block Diagram
VBUS_IN
LDO
OVP
VDC_OUT
FAULT
Gate Driver
SINK_FET_EN
VDDD
Fault Indicator
1µF
1.8-V
Regulator
VCCD
VSS
1µF
CC
Tx/Rx
Core
BCR
CC1, CC2
VSS
Document Number: 002-25383 Rev. *B
Page 4 of 23
EZ-PD™ BCR Datasheet
Pinouts
Table 1. EZ-PD BCR Pin Descriptions
24-Pin QFN
Pin Name
Description
Connect a resistor divider on this to 3.3 V (from the VDDD pin) to indicate the minimum voltage
needed by the system from the attached power adapter.
1
VBUS_MIN
Refer to Table 2 for recommended resistor values.
Connect a resistor divider on this to 3.3 V (from the VDDD pin) to indicate the maximum voltage
needed by the system from the attached power adapter.
Refer to Table 2 for recommended resistor values.
2
3
VBUS_MAX
Connect this signal to the gate of a FET through a series resistor. This pin is the output of a PMOS
FET gate driver that is slew-rate controlled.
This signal is enabled when the EZ-PD BCR device successfully negotiates a power contract
within the requested range.
VBUS_FET_EN
Connect this signal to the gate of a FET through a series resistor. This pin is the output of a PMOS
FET gate driver.
This signal is enabled when the EZ-PD BCR device fails to negotiate for higher power and defaults
to 5 V.
4
SAFE_PWR_EN
Connect a resistor divider on these pins to 3.3 V (from the VDDD pin) to set the operating current
requested from the power adapter.
Refer toTable 3 and Table 4 for recommended resistor values.
5
6
7
8
ISNK_COARSE
ISNK_FINE
HPI_INT
Active LOW HPI Interrupt pin
GPIO_1
Additional GPIO that can be set up over the HPI interface.
The EZ-PD BCR device pulls this line high if the power adapter cannot supply the required voltage
or current or if an OVP event was detected. The pin is low otherwise.
9
FAULT
The EZ-PD BCR device pulls this line low if no device is attached or if CC polarity is un-flipped
(CC1 connected). If a device is attached on CC2 (polarity is flipped), the EZ-PD BCR device pulls
this line high.
This is an open drain I/O that requires an external pull-up resistor. The presence or the value of
the pull-up resistor connected to this pin determines the data capability reported in the UFPVendor
Data Object (VDO) by the BCR device to the Downstream Facing Port (DFP).
If there is no pull-up resistor on this pin or if its value is less than or equal to 4.7 kΩ, then the UFP
VDO data capability bit is set to 1, which correlates to the port being data capable. If the value of
the pull-up resistor is 50 kΩ, then the UFP VDO data capability bit is set to 0, which correlates to
the port not being data capable.
10
11
FLIP
Connect this pin to the output of the PFETs controlled by the VBUS_FET_EN. This is used for
monitoring the VBUS output. This is the power output of the system.
VDC_OUT
12
13
14
15
16
17
HPI_SDA
HPI_SCL
CC2
This is an I2C slave interface provided for a host processor to control and monitor the EZ-PD BCR
device. For more details, refer to the HPI Specification for EZ-PD BCR device.
Communication Channel 2 pin used to negotiate a voltage/current with the attached adapter
Communication Channel 1 pin used to negotiate a voltage/current with the attached adapter
Leave this pin unconnected
CC1
D-
D+
Leave this pin unconnected
Connect to VBUS of USB Type-C connector. Used to supply power to the EZ-PD BCR device and
monitor incoming voltage.
18
VBUS_IN
19
20
21
22
GND
DNU1
DNU2
VSS
System Ground pin
Leave this pin unconnected
Leave this pin unconnected
Ground pin, connect to USB Type-C connector GND.
Document Number: 002-25383 Rev. *B
Page 5 of 23
EZ-PD™ BCR Datasheet
Table 1. EZ-PD BCR Pin Descriptions (continued)
24-Pin QFN
Pin Name
Description
23
24
–
VDDD
Output of internal 3.3-V regulator. Connect 1 µF and 2x 100-nF capacitors.
Output of internal 1.8-V regulator. Connect a 1-µF decoupling capacitor.
Ground
VCCD
EPAD
Figure 2. Pinout of 24-QFN Package (Top View)
VBUS_MIN
VBUS_MAX
VBUS_IN
D+
1
2
3
4
5
6
18
17
16
15
14
13
D-
VBUS_FET_EN
SAFE_PWR_EN
ISNK_COARSE
ISNK_FINE
EPAD
CC1
CC2
HPI_SCL
Document Number: 002-25383 Rev. *B
Page 6 of 23
EZ-PD™ BCR Datasheet
Application Overview
Figure 3 shows the EZ-PD BCR-based application diagram using the 24-pin QFN part. It has three main parts: USB Type-C receptacle
to provide the input power to the application, the Power Subsystem used as the output power, and four sets of resistor divider networks
to select the desired output voltage and current values.
The ‘Fault’ pin is used to indicate any voltage faults. When a fault condition is enabled, the output voltage of this application will go
down to 0V and the EZ-PD BCR device will attempt a protocol reset to recover from fault. For a detailed reference schematic, refer
to the CY4533 EZ-PD BCR EVK schematic.
Figure 3. EZ-PD BCR based Application Diagram (for Electronic Systems Requiring 12 V to 15 V Input at 2 A)
Type-C Receptacle
8
7
6
5
8
7
6
5
Power
Subsystem
3
2
1
3
2
1
1µF
10K
3.3µF
1µF
4
4
49.9K
8
7
6
5
8
7
6
5
3
2
1
3
2
1
SAFE_PWR
4
49.9 K
4
3.3V
1 K
0.1 µF
1 K
0.1µF
1µF
3.3 V
23
3
4
2.2 K
2.2 K
VBUS_FET_EN VDDD
VBUS_IN
SAFE_PWR_EN
18
14
11
VDC_OUT
CC2
CC1
D+
12
HPI_SDA
HPI_SCL
SOC
15
17
13
X
20
21
16
DNU1
DNU2
X
D-
X
X
CYPD3177-24LQXI
3.3 V
4.7 K
10
24
FLIP
7
8
HPI_INT
GPIO_1
X
X
VBUS
VCCD
1k
1 µF
19, 22
9
GND
FAULT
ISNK_COARSE
5
ISNK_FINE
6
VBUS_MIN
1
VBUS_MAX
2
VDDIO
VDDIO
VDDIO
VDDIO
R1
R3
R5
R7
R4
R6
R2
R8
Notes
1. Refer to Table 2, Table 3, and Table 4 for values of these resistor divider networks.
2. FLIP pin is in LOW state when Type-C Plug is upside-up, and in Hi-Z state when upside-down.
3. Use a 50-k resistor on the FLIP pin to set the UFP VDO data capability bit to 0.
Document Number: 002-25383 Rev. *B
Page 7 of 23
EZ-PD™ BCR Datasheet
The four sets of resistor divider networks are used to determine the voltage and current range that the EZ-PD BCR device will negotiate
with the USB Type-C power adapter. Table 2, Table 3, and Table 4 show the values of pull-up and pull-down resistors on each pin
applicable for a desired VBUS_MIN, VBUS_MAX, ISNK_COARSE or ISNK_FINE value.
Note 1: If VBUS_MIN is more than VBUS_MAX, the setting on VBUS_MAX is used as both minimum and maximum VBUS setting
for the system.
Note 2: EZ-PD BCR device does not monitor the current on VBUS_IN and enforce it within ISNK limits. It is the responsibility of the
system to not consume more current than what the power adapter can provide.
Note 3: VBUS_MIN and VBUS_MAX can be set to the same value to select one specific voltage level from the Type-C power adapter.
Note 4: Ensure that the board layout design does not inject any noise into the VBUS_MIN, VBUS_MAX, ISNK_COARSE, ISNK_FINE
pins.
Table 2. Resistor Divider Values for Minimum or Maximum Voltage Requested on VBUS
Voltage Requested
(V)
ResistorRatioRelative
to VDDD = 3.3 V
Suggested Pull-up
Resistor value (k)
Suggested Pull-down Voltage Range on Pin
Resistor value (k)
(mV)
5
0/6
1/6
Open
5.1
5.1
5.1
5.1
0
0
1
0–248
9
249–786
787–1347
1348–1920
1921–2778
≥ 2779
12
15
19
20
2/6
2.4
5.1
10
3/6
4/6
≥ 5/6
Open
Table 3. Resistor Divider Values for Coarse Setting on Operating Current (For VDDD = 3.3 V)
Operating Current
ResistorRatioRelative
to VDDD = 3.3 V
Suggested Pull-up
Resistor Value (k)
Suggested Pull-down Voltage Range on Pin
Requested for Coarse
Setting (A)
Resistor Value (k)
(mV)
0
1
2
3
4
5
0/6
1/6
Open
5.1
5.1
5.1
5.1
0
0
1
0–248
249–786
787–1347
1348–1920
1921–2778
≥ 2779
2/6
2.4
5.1
10
3/6
4/6
≥ 5/6
Open
Table 4. Resistor Divider Values for Fine Setting on Operating Current (For VDDD = 3.3 V)
Operating Current
ResistorRatioRelative
to VDDD = 3.3 V
Suggested Pull-up
Resistor Value (k)
Suggested Pull-down Voltage Range on Pin
Requested for Fine
Setting (A)
Resistor Value (k)
(mV)
+0
0/6
1/6
Open
5.1
5.1
5.1
0
0
1
0–248
249–786
787–1347
1348–1920
≥ 1921
+250
+500
+750
+900
2/6
2.4
5.1
Open
3/6
≥ 4/6
FAULT Pin Behavior
FAULT is driven to Logic HIGH if at least one of the following conditions is met:
■ Type-C power adapter cannot supply a voltage within VBUS_MIN and VBUS_MAX settings and/or supply a current of at least
ISNK_COARSE + ISNK_FINE value.
■ Voltage on VBUS_IN is 20% below the VBUS_MIN setting or 20% above the VBUS_MAX setting.
FAULT is driven to Logic LOW otherwise.
Document Number: 002-25383 Rev. *B
Page 8 of 23
EZ-PD™ BCR Datasheet
SAFE_PWR_EN pin Behavior
SAFE_PWR_EN is a PFET gate driver that can be used to provide power to the system when an incompatible power adapter is
attached to the system. SAFE_PWR_EN is driven to 0V when the Type-C power adapter cannot supply a voltage within VBUS_MIN
and VBUS_MAX settings and/or supply a current of at least ISNK_COARSE + ISNK_FINE value. In this case, the EZ-PD BCR device
negotiates for a 5V@ ISNK contract with the USB-PD Power Adapter when possible.
SAFE_PWR_EN pin is left floating (High-Z) in all other conditions.
VBUS_FET_EN pin Behavior
The VBUS_FET_EN pin is a PFET gate driver that drives to either 0 V or VBUS_IN depending on the state of the Type-C connection.
Contact Cypress Technical Support for more details on how to use this pin for specific applications.
Document Number: 002-25383 Rev. *B
Page 9 of 23
EZ-PD™ BCR Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 5. Absolute Maximum Ratings
Parameter
VBUS_MAX
Description
Min
Typ
Max
Unit
Details/Conditions
Max supply voltage relative to VSS on
VBUS_IN and VDC_OUT pins
–
–
30
V
VDDD_MAX
VCC_PIN_ABS
VGPIO_ABS
IGPIO_ABS
Max supply voltage relative to VSS
Max voltage on CC1, CC2 pins
GPIO voltage
–
–
–
–
–
–
6
22[1]
V
V
Absolute max
–0.5
–25
VDDD +0.5
25
V
Maximum current per GPIO
mA
GPIO injection current, Max for VIH
VDDD, and Min for VIL < VSS
>
Absolute max, current
injected per pin
IGPIO_injection
–0.5
–0.5
2200
–
–
–
0.5
6
mA
V
Applicable to pins HPI_INT
and GPIO_1
VGPIO_OVT_ABS OVT GPIO voltage
Electrostatic discharge human body
model
ESD_HBM
–
V
–
Electrostatic discharge charged device
model
ESD_CDM
LU
500
–
–
–
V
–
–
Pin current for latch-up
–100
100
mA
Contact discharge on CC1,
CC2, VBUS_IN, HPI_SDA
and HPI_SCL pins
ESD_IEC_CON Electrostatic discharge IEC61000-4-2
ESD_IEC_AIR Electrostatic discharge IEC61000-4-2
8000
–
–
–
–
V
V
Air discharge for D+, D-, CC1,
CC2, VBUS_IN, HPI_SDA
and HPI_SCL pins
15000
Device-Level Specifications
All specifications are valid for –40 °C TA 105°C and TJ 120°C, except where noted.
Table 6. DC Specifications
Spec ID
Parameter
VDDD
Description
Min
2.7
3.0
3.0
–
Typ Max Unit
Details/Conditions
SID.PWR#2
Power supply input voltage
Power supply input voltage
Power supply input voltage
Output voltage for core Logic
–
–
5.5
5.5
24.5
–
V
V
V
V
Sink mode, –40°C TA 105°C.
Source mode, –40°C TA 105°C.
–40 °C TA 105°C.
–
SID.PWR#2_A VDDD
SID.PWR#3
SID.PWR#5
VBUS_IN
VCCD
–
1.8
Power supply decoupling
capacitor for VDDD
SID.PWR#13 Cexc
SID.PWR#14 Cexv
0.8
–
1
–
–
µF X5R ceramic or better
µF X5R ceramic or better
Power supply decoupling
capacitor for VBUS_IN_DISH-
CARGE
0.1
Note
1. As per USB PD specification, maximum allowed VBUS = 21.5 V.
Document Number: 002-25383 Rev. *B
Page 10 of 23
EZ-PD™ BCR Datasheet
Table 6. DC Specifications (continued)
Spec ID Parameter
Description
Min
Typ Max Unit
Details/Conditions
Active Mode. Typical values measured at VDDD = 5.0 V or VBUS = 5.0 V and TA = 25°C.
VDDD = 5 V OR VBUS = 5 V,
TA = 25°C. CC1/CC2 in Tx or Rx,
Supply current from VBUS or
VDDD
SID.PWR#8
IDD_A
–
10
–
mA
no I/O sourcing current, 2 SCBs at
1 Mbps, EA/ADC/CSA/UVOV ON,
CPU at 24 MHz.
Sleep Mode. Typical values measured at VDD = 3.3 V and TA = 25°C.
CC, I2C, WDT wakeup on.
VDDD = 3.3 V, TA = 25°C,
SID25A
IDD_S
–
3
–
–
mA All blocks except CPU are on, CC
IO on, EA/ADC/CSA/UVOV On.
IMO at 24 MHz.
Deep Sleep Mode. Typical values measured at TA = 25°C.
For sink applications,
VBUS 4.0 to 24.5 V.
SID_P-
B_DS_A_SNK
VBUS = 24.5 V, TA = 25 °C, Part is in
deep sleep. Attached, CC I/O on,
ADC/CSA/UVOV on.
IDD_PB_DS_A_SNK
–
500
µA
CC, I2C, WDT Wakeup on
Table 7. AC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max Unit
Details/Conditions
SID.PWR#17 TSLEEP
Wakeup from sleep mode
–
0
–
µs
µs
–
–
Wakeup from Deep Sleep
mode
SID.PWR#18 TDEEPSLEEP
–
–
–
–
5
3
35
Power-up to “Ready to accept
I2C/CC command”
SYS.FES#1
T_PWR_RDY
25
–
ms
ms
–
–
Power-on I/O Initialization
Time
SID.PWR#18A TPOR_HIZ_T
I/O
Table 8. I/O DC Specifications
Spec ID
SID.GIO#37
SID.GIO#38
Parameter
VIH_CMOS
VIL_CMOS
Description
Min
Typ
Max
Unit
Details/Conditions
CMOS input
Input voltage HIGH threshold 0.7 × VDDD
–
–
–
V
Input voltage LOW threshold
Output voltage HIGH level
–
0.3 × VDDD
–
V
V
CMOS input
IOH = 4 mA at 3-V
VDDD
SID.GIO#33
SID.GIO#36
SID.GIO#16
VOH_3V
VOL_3V
IIL
VDDD –0.6
–
–
–
IOL = 10 mA at 3-V
VDDD
Output voltage LOW level
–
–
0.6
2
V
Input leakage current
(absolute value)
nA +25°C TA, 3-V VDDD
Capacitance on D+,
pF D- pins. Guaranteed
by characterization.
SID.GIO#17
CPIN_A
Max pin capacitance
Max pin capacitance
Input hysteresis CMOS
–
–
3
–
22
7
–40°C to +85°C TA,
All VDDD, all other
I/OS. Guaranteed by
characterization.
SID.GIO#17A CPIN
–
pF
VDDD < 4.5 V.
Guaranteed by
characterization.
SID.GIO#44
VHYSCMOS
0.05 × VDDD
–
mV
Document Number: 002-25383 Rev. *B
Page 11 of 23
EZ-PD™ BCR Datasheet
Table 8. I/O DC Specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
Current through protection
diode to VDDD/VSS
Guaranteed by
design.
SID69
IDIODE
ITOT_GPIO
–
–
100
µA
Maximum total sink chip
current
Guaranteed by
design.
SID.GIO#45
OVT
–
–
85
mA
Input current when Pad >
VDDD for OVT inputs
SID.GIO#46
IIHS
–
–
10.00
µA Per I2C specification
Table 9. I/O AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
TRISEF
TFALLF
Description
Min Typ Max Unit
Details/Conditions
SID70
SID71
Rise time in Fast Strong mode
Fall time in Fast Strong mode
2
2
–
–
12
12
ns 3.3-V VDDD, Cload = 25 pF
ns 3.3-V VDDD, Cload = 25 pF
Table 10. HPI Pins DC Specifications (Applicable to pins HPI_SDA and HPI_SCL only)
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min Typ Max Unit
Details/Conditions
Max / min current in to any
mA input or output, pin-to-pin,
pin-to-supply
GPIO_20VT Latch up current
limits
SID.GPIO_20VT#4 GPIO_20VT_I_LU
–140
–
140
GPIO_20VT Pull-up resistor
value
+25°C TA, 1.4 V to
k
SID.GPIO_20VT#5 GPIO_20VT_RPU
SID.GPIO_20VT#6 GPIO_20VT_RPD
SID.GPIO_20VT#16 GPIO_20VT_IIL
SID.GPIO_20VT#17 GPIO_20VT_CPIN
SID.GPIO_20VT#36 GPIO_20VT_Vol
SID.GPIO_20VT#69 GPIO_20VT_IDIODE
1
2.5
–
–
–
–
–
–
–
25
20
2
GPIO_20VT_Voh(min)
GPIO_20VT Pull-down
resistor value
k +25°C TA, 1.4-V to VDDD
GPIO_20VT Input leakage
current (absolute value)
nA +25°C TA, 3-V VDDD
–40°C to +85°C TA, All
pF
GPIO_20VT pin capacitance
15
–
25
0.4
100
VDDD, F = 1 MHz
GPIO_20VT Output Voltage
low level
V
IOL = 2 mA
–
GPIO_20VT Current through
protection diode to VDDD/VSS
–
µA
Table 11. HPI Pins AC Specifications (Applicable to pins HPI_SDA and HPI_SCL only)
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
GPIO_20VT Rise time in
Fast Strong Mode
SID.GPIO_20VT#70 GPIO_20VT_TriseF
SID.GPIO_20VT#71 GPIO_20VT_TfallF
1
–
45
ns All VDDD, Cload = 25 pF
ns All VDDD, Cload = 25 pF
GPIO_20VT Fall time in Fast
Strong Mode
2
–
15
Document Number: 002-25383 Rev. *B
Page 12 of 23
EZ-PD™ BCR Datasheet
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
I2C
Table 12. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Spec ID
SID149
Parameter
II2C1
II2C2
II2C4
Description
Min
–
Typ
–
Max
100
135
–
Unit
µA
Details/Conditions
Block current consumption at 100 kHz
Block current consumption at 400 kHz
I2C enabled in Deep Sleep mode
–
–
–
SID150
SID152
–
–
µA
–
1.4
µA
Table 13. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
Description
Min
Typ Max
400
Unit
Details/Conditions
Details/Conditions
FI2C1
Bit rate
–
–
kbps
–
System Resources
Power-on-Reset (POR) with Brown Out SWD Interface
Table 14. Imprecise Power On Reset (PRES) (Guaranteed by Characterization)
Spec ID
SID185
SID186
Parameter
VRISEIPOR
VFALLIPOR
Description
Min
0.80
0.70
Typ Max Unit
Power-on Reset (POR) rising trip
voltage
–
–
1.50
1.4
V
V
–
–
POR falling trip voltage
Table 15. Precise Power On Reset (POR)
(Guaranteed by Characterization)
Spec ID
SID190
SID192
Parameter
Description
Min
1.48
1.1
Typ Max Unit
Details/Conditions
Details/Conditions
Brown-out Detect (BOD) trip voltage
in active/sleep modes
VFALLPPOR
–
–
1.62
1.5
V
V
–
–
VFALLDPSLP BOD trip voltage in Deep Sleep mode
Table 16. USB PD DC Specifications
Spec ID Parameter
SID.PD.4 Rd
Description
UFP CC termination
Min
Typ Max Unit
4.59
5.1
5.1
5.61
6.12
k
k
–
UFP (Power Bank) Dead Battery CC
Termination on CC1 and CC2
All supplies forced to 0V and
1.32 V applied at CC1 or CC2
SID.PD.5
SID.PD.6
Rd_DB
4.08
Ground offset tolerated by BMC
receiver
Relative to the remote BMC
transmitter
Vgndoffset
–500
–
500
mV
Document Number: 002-25383 Rev. *B
Page 13 of 23
EZ-PD™ BCR Datasheet
Gate Driver Specifications
Table 17. Gate Driver DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max Unit
Details/Conditions
Applicable on
VBUS_P_CTRL and
VBUS_C_CTRL to turn ON
external PFET.
SID.GD.1
RPD
Pull-down resistance
–
–
3
4
k
Applicable on
SID.GD.2
RPU
Pull-up resistance
–
–
k VBUS_P_CTRL to turn OFF
external PFET.
Pull-down current sink at drive
strength of 1
SID.GD.3
SID.GD.4
SID.GD.5
SID.GD.6
SID.GD.7
SID.GD.8
SID.GD.9
IPD0
25
50
–
75
150
300
580
1200
2300
–
µA
Pull-down current sink at drive
strength of 2
IPD1
–
µA
I-mode (current mode) pull
down at 5 V.
Applicable on
VBUS_P_CTRL and
VBUS_C_CTRL to turn ON
external PFET.
Pull-down current sink at drive
strength of 4
IPD2
140
280
560
1120
–
–
µA
Pull-down current sink at drive
strength of 8
IPD3
–
–
µA
µA
µA
µA
Pull-down current sink at drive
strength of 16
IPD4
Pull-down current sink at drive
strength of 32
IPD5
–
+25°C TJ, 5-V VDDD
20-V VBUS
,
,
,
,
I_leak_p1
Pin leakage on VBUS_P_CTRL
Pin leakage on VBUS_C_CTRL
Pin leakage on VBUS_P_CTRL
Pin leakage on VBUS_C_CTRL
Pin leakage on VBUS_P_CTRL
Pin leakage on VBUS_C_CTRL
0.003
+25°C TJ, 5-V VDDD
20-V VBU
SID.GD.10
SID.GD.11
SID.GD.12
SID.GD.13
SID.GD.14
I_leak_c1
I_leak_p2
I_leak_c2
I_leak_p3
I_leak_c3
–
–
–
–
–
0.003
–
2
2
7
7
µA
µA
µA
µA
µA
+85°C TJ, 5-V VDDD
20-V VBU
–
–
–
–
+85°C TJ, 5-V VDDD
20-V VBU
+125°C TJ, 5-V VDDD
20-V VBU
,
,
+125°C TJ, 5-V VDDD
20-V VBU
Document Number: 002-25383 Rev. *B
Page 14 of 23
EZ-PD™ BCR Datasheet
Table 18. Gate Driver AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ Max
Unit
Details/Conditions
Cload = 2 nF,
Delay to VBUS –1.5 V from
initiation of falling edge,
VBUS = 5 V to 20 V,
50 k tied between
VBUS_C_CTRL and VBUS
SID.GD.15
TPD1
Pull down delay on SAFE_PWR_EN
–
–
–
–
2
5
2
µs
80% to 20%,
Discharge rate of output node on
SAFE_PWR_EN
50 k tied between
VBUS_C_CTRL and VBUS,
Cload = 2 nF, Vinitial = 24 V
SID.GD.16
SID.GD.17
Tr_discharge
–
–
V/µs
µs
Cload = 2 nF,
Delay to VBUS –1.5 V from
initiation of falling edge,
VBUS = 5 V to 20 V,
50 k tied between
VBUS_C_CTRL and VBUS
TPD2
Pull down delay on VBUS_FET_EN
Pull up delay on VBUS_FET_EN
Cload = 2 nF,
Delay to VBUS–1.5 V from
initiation of falling edge,
VBUS = 5 V to 20 V,
SID.GD.18
TPU
–
–
18
µs
50 k tied between
VBUS_C_CTRL and VBUS
Cload = 2 nF, 20% to 80% of
VBUS_P_CTRL range
SID.GD.19
SID.GD.20
SRPU
SRPD
Output slew rate on VBUS_FET_EN
Output slew rate on VBUS_FET_EN
–
–
–
–
5
5
V/µs
V/µs
Cload = 2 nF, 80% to 20% of
VBUS_P_CTRL range
Table 19. VBUS Discharge Specifications
Spec ID Parameter
Description
Min Typ Max Unit
Details/Conditions
SID.VBUS.DISC.6 I1
SID.VBUS.DISC.7 I2
SID.VBUS.DISC.8 I4
SID.VBUS.DISC.9 I8
SID.VBUS.DISC.10 I16
20-V NMOS ON current for DS = 1 0.15
–
–
–
–
–
1
2
mA
mA
20-V NMOS ON current for DS = 2
20-V NMOS ON current for DS = 4
20-V NMOS ON current for DS = 8
20-V NMOS ON current for DS = 16
0.4
0.9
2
4
mA Measured at 0.5 V
8
mA
mA
4
10
When VBUS is discharged to 5 V.
Guaranteed by Characterization.
VBUS_Stop Error percentage of final VBUS value
SID.VBUS.DISC.11
–
–
10
%
_Error
from setting
Document Number: 002-25383 Rev. *B
Page 15 of 23
EZ-PD™ BCR Datasheet
Table 20. Voltage (VBUS) Regulation DC Specifications
Spec ID
Parameter
Description
Min Typ Max Unit
Details/Conditions
Active mode shunt regulator at
3 V with bandgap
SID.DC.VR.1
V_IN_3
V(pad_in) at 3-V target
2.85
4.75
8.55
3
5
9
3.15
5.25
9.45
V
V
V
V
V
V
V
V
V
V
Active mode shunt regulator at
5 V
SID.DC.VR.2
SID.DC.VR.3
SID.DC.VR.4
SID.DC.VR.5
SID.DC.VR.6
SID.DC.VR.7
SID.DC.VR.8
SID.DC.VR.9
SID.DC.VR.10
V_IN_5
V_IN_9
V_IN_15
V_IN_20
V(pad_in) at 5-V target
V(pad_in) at 9-V target
V(pad_in) at 15-V target
V(pad_in) at 20-V target
Active mode shunt regulator at
9 V
Active mode shunt regulator at
15 V
14.25 15 15.75
Active mode shunt regulator at
20 V
19
2.7
4.5
8.1
20
3
21
3.3
5.5
9.1
Deep Sleep mode shunt
regulator at 3 V with bandgap
V_IN_3_DS V(pad_in) at 3-V target
V_IN_5_DS V(pad_in) at 5-V target
V_IN_9_DS V(pad_in) at 9-V target
V_IN_15_DS V(pad_in) at 15-V target
V_IN_20_DS V(pad_in) at 20-V target
Deep Sleep mode shunt
regulator at 5 V
5
Deep Sleep mode shunt
regulator at 9 V
9
Deep Sleep mode shunt
regulator at 15 V
13.5 15 16.5
Deep Sleep mode shunt
regulator at 20 V
18
20
22
SID.DC.VR.11
SID.DC.VR.12
IKA_OFF
IKA_ON
Off-state cathode current
–
–
–
–
10
10
µA
–
–
Current through cathode pin
mA
Table 21. VBUS Short Protection Specifications
Spec ID
Parameter
Description
Min
Typ
Max Unit
Details/Conditions
Short-to-VBUS system-side
clamping voltage on the
CC/P2.2/P2.3 pins
V_SHORT_
TRIGGER
SID.VSP.1
–
9
–
V
Guaranteed by Characterization.
Table 22. VBUS DC Regulator Specifications
Spec ID
Parameter
Description
Min
Typ
Max Unit
2.62
Details/Conditions
VBUS_-
DETECT
SID.VREG.2
VBUS detect threshold voltage
1.08
–
V
–
Table 23. VBUS AC Regulator Specifications
Spec ID
Parameter
Description
Min
Typ
Max Unit
200 µs
Details/Conditions
Totalstartuptimefortheregulator
supply outputs
SID.VREG.3 Tstart
–
–
Guaranteed by Characterization.
Document Number: 002-25383 Rev. *B
Page 16 of 23
EZ-PD™ BCR Datasheet
Analog to Digital Converter (Used for Determining VBUS_MIN,
Table 24. ADC DC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
ADC resolution
Min
Typ
Max Unit
Details/Conditions
SID.ADC.1
Resolution
–
8
–
Bits
–
Reference voltage generated from
VDDD
SID.ADC.2
INL
Integral non-linearity
Integral non-linearity
Differential non-linearity
–2.5
–1.5
–2.5
–
–
–
2.5
LSB
Reference voltage generated from
bandgap
SID.ADC.2A INL
SID.ADC.3 DNL
SID.ADC.3A DNL
1.5
2.5
LSB
LSB
Reference voltage generated from
VDDD
Reference voltage generated from
bandgap
Differential non-linearity
Gain error
–1.5
–1.5
1.96
–
–
1.5
1.5
LSB
LSB
V
SID.ADC.4
SID.ADC.6
Gain Error
VREF_ADC2
–
ADC reference voltage when
generated from band gap.
Reference voltage generated from
bandgap
2.0
2.04
VBUS_MAX, ISNK_COARSE, ISNK_FINE Values)
Table 25. ADC AC Specifications (Guaranteed by Design)
Spec ID
Parameter
Description
Min
Typ
Max Unit
V/ms –
Details/Conditions
Rate of change of sampled
voltage signal
SID.ADC.7
SLEW_Max
–
–
3
Document Number: 002-25383 Rev. *B
Page 17 of 23
EZ-PD™ BCR Datasheet
Ordering Information
Table 26 lists the EZ-PD BCR part numbers and features.
Table 26. EZ-PD BCR Ordering Information
Termination
Resistor
MPN
Application
Role
Package Type
Si ID
Barrel Connector Replacement or Generic
UFP Sink
CYPD3177-24LQXQ
RD, RD-DB
UFP
24-Pin QFN
2004
Ordering Code Definitions
-
XX XX
X
X
X
PD
X
XX
X
CY
T = Tape and Reel (Optional)
Temperature Grade:
Q = Extended industrial (–40 °C to +105 °C)
Lead: X = Pb-free
Package Type: LQ = QFN; S = SOIC
Number of pins in the package
Application and Feature Combination Designation
Number of USB Type-C Ports: 1 = 1 Port, 2 = 2 Port
Product Type: 3 = Third-generation product family
Marketing Code: PD = Power Delivery product family
Company ID: CY = Cypress
Document Number: 002-25383 Rev. *B
Page 18 of 23
EZ-PD™ BCR Datasheet
Packaging
Table 27. Package Characteristics
Parameter
TA
Description
Conditions
Min
–40
–40
–
Typ
25
25
–
Max
105
Unit
°C
Operating ambient temperature
Operating junction temperature
Package JA (24-QFN)
Extended Industrial
TJ
Extended Industrial
120
°C
TJA
TJC
–
–
19.98
4.78
°C/W
°C/W
Package JC (24-QFN)
–
–
Table 28. Solder Reflow Peak Temperature
Maximum Time within
5 °C of Peak Temperature
Package
Maximum Peak Temperature
24-pin QFN
260 °C
30 seconds
Table 29. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
24-pin QFN
MSL3
Document Number: 002-25383 Rev. *B
Page 19 of 23
EZ-PD™ BCR Datasheet
Figure 4. 24-pin QFN Package Outline
002-16934 *C
Document Number: 002-25383 Rev. *B
Page 20 of 23
EZ-PD™ BCR Datasheet
Acronyms
Document Conventions
Table 30. Acronyms Used in this Document
Units of Measure
Acronym
ADC
Description
analog-to-digital converter
Table 31. Units of Measure
Symbol
Unit of Measure
Arm®
advanced RISC machine, a CPU architecture
configuration channel
°C
degrees Celsius
hertz
CC
Hz
CPU
central processing unit
KB
kbps
kHz
k
1024 bytes
CS
current sense
kilobits per second
kilohertz
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
DIO
kilo ohm
ESD
GPIO
IC
electrostatic discharge
general-purpose input/output
integrated circuit
Mbps
MHz
M
Msps
µA
megabits per second
megahertz
mega-ohm
Inter-Integrated Circuit, a communications
protocol
I2C, or IIC
mega samples per second
microampere
microfarad
I/O
input/output, see also GPIO
low-dropout regulator
microcontroller unit
no connect
µF
LDO
MCU
NC
µs
microsecond
microvolt
µV
µW
mA
ms
mV
nA
microwatt
OVP
OVT
PD
overvoltage protection
overvoltage tolerant
power delivery
milliampere
millisecond
millivolt
PHY
POR
PRES
PSoC®
PWM
RISC
RX
physical layer
nanoampere
nanosecond
ohm
power-on reset
ns
precise power-on reset
Programmable System-on-Chip™
pulse-width modulator
reduced-instruction-set computing
receive
I2C serial clock
I2C serial data
W
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
SCL
SDA
SWD
TX
sps
V
samples per second
volt
serial wire debug, a test protocol
transmit
anewstandard withaslimmerUSB connectorand
a reversible cable, capable of sourcing up to
100 W of power
Type-C
USB
Universal Serial Bus
Document Number: 002-25383 Rev. *B
Page 21 of 23
EZ-PD™ BCR Datasheet
Document History Page
Document Title: EZ-PD™ BCR Datasheet, USB Type-C Port Controller for Power Sinks
Document Number: 002-25383
Submission
Revision
ECN
Description of Change
Date
*A
6643829 08/01/2019 Release to web.
Updated USB PD 3.0 version details.
Updated Pin 10 description in Pinouts.
Added a note in Figure 3.
*B
7138986 05/18/2021
Updated 24-pin QFN package drawing.
Document Number: 002-25383 Rev. *B
Page 22 of 23
EZ-PD™ BCR Datasheet
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by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-25383 Rev. *B
Revised May 18, 2021
Page 23 of 23
相关型号:
![](http://pdffile.icpdf.com/pdf2/p00366/img/page/CYPD3177-24L_2240103_files/CYPD3177-24L_2240103_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00366/img/page/CYPD3177-24L_2240103_files/CYPD3177-24L_2240103_2.jpg)
CYPD3177-24LQXQT
EZ-PD™ Barrel Connector Replacement (BCR) CYPD3177-24LQXQT is the tape and reel packing type option of EZ-PD™ BCR family, the highly-integrated USB Type-C port controllers for power sink applications. It targets electronic devices using legacy barrel connectors up to 100 W or USB micro-B for power inputs, enabling product designers to replace these incompatible connectors with USB-C.
INFINEON
![](http://pdffile.icpdf.com/pdf2/p00362/img/page/CYPD3184A1-2_2216842_files/CYPD3184A1-2_2216842_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00362/img/page/CYPD3184A1-2_2216842_files/CYPD3184A1-2_2216842_2.jpg)
CYPD3184A1-24LQXQ
PG-VQFN-24 tray packing secondary side controller with PD controller and synchronous rectifier with optocoupler-feedback for USB PD charger and adapters
INFINEON
![](http://pdffile.icpdf.com/pdf2/p00362/img/page/CYPD3184A1-2_2216842_files/CYPD3184A1-2_2216842_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00362/img/page/CYPD3184A1-2_2216842_files/CYPD3184A1-2_2216842_2.jpg)
CYPD3184A1-24LQXQT
PG-VQFN-24 tape and reel packing secondary side controller with PD controller and synchronous rectifier with optocoupler-feedback for USB PD charger and adapters
INFINEON
![](http://pdffile.icpdf.com/pdf2/p00274/img/page/CYPD4255-96B_1640874_files/CYPD4255-96B_1640874_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00274/img/page/CYPD4255-96B_1640874_files/CYPD4255-96B_1640874_2.jpg)
CYPD4255-96BZXI
Microprocessor Circuit, CMOS, PBGA96, 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, MO-225, BGA-96
CYPRESS
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