CYPD3135-40LQXI [INFINEON]
PG-VQFN-40 tray packing PD controller with Industry temperature grade for source application;型号: | CYPD3135-40LQXI |
厂家: | Infineon |
描述: | PG-VQFN-40 tray packing PD controller with Industry temperature grade for source application 光电二极管 外围集成电路 |
文件: | 总46页 (文件大小:1062K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
EZ-PD™ CCG3
USB Type-C Port Controller
General Description
EZ-PD™ CCG3 is a highly integrated USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD
CCG3 provides a complete USB Type-C and USB-Power Delivery port control solution for notebooks, dongles, monitors, docking
stations and power adapters. CCG3 uses Cypress’s proprietary M0S8 technology with a 32-bit, 48-MHz ARM® Cortex® -M0 processor
with 128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, a Crypto engine for authentication, a 20V-tolerant
regulator, and a pair of FETs to switch a 5V (VCONN) supply, which powers cables. CCG3 also integrates two pairs of gate drivers to
control external VBUS FETs and system level ESD protection. CCG3 is available in 40-QFN, 32-QFN, and 42-WLCSP packages.
Clocks and Oscillators
■ Integrated oscillator eliminating the need for external clock
Features
Type-C and USB-PD Support
Power
■ Integrated USB Power Delivery 3.0 support
■ Integrated USB-PD BMC transceiver
■ Integrated VCONN FETs
■ 2.7 V to 21.5 V operation
■ 2x Integrated dual-output gate drivers for external VBUS FET
■ Configurable resistors RA, RP, and RD
■ Dead Battery Detection support
switch control
■ Independent supply voltage pin for GPIO that allows 1.71 V to
■ Integrated fast role swap and extended data messaging
■ Supports one USB Type-C port
5.5 V signaling on the I/Os
■ Reset: 30 µA, Deep Sleep: 30 µA, Sleep: 3.5 mA
■ Integrated Hardware based overcurrent protection (OCP) and
overvoltage protection (OVP)
System-Level ESD Protection
■ On CC, SBU, DPLUS, DMINUS and VBUS pins
32-bit MCU Subsystem
■ 48-MHz ARM Cortex-M0 CPU
■ 128-KB Flash
■ ±8-kV ContactDischarge and±15-kVAirGap Dischargebased
on IEC61000-4-2 level 4C
Packages
■ 8-KB SRAM
■ 40-pin QFN, 32-pin QFN, and 42-ball CSP for
Notebooks/Accessories
Integrated Digital Blocks
■ Hardware Crypto block enables Authentication
■ Supports industrial temperature range (–40 °C to +105 °C)
■ Full-Speed USB Device Controller supporting Billboard Device
Class
■ Integrated timers and counters to meet response times
required by the USB-PD protocol
■ Four run-time reconfigurable serial communication blocks
(SCBs) with reconfigurable I2C, SPI, or UART functionality
Cypress Semiconductor Corporation
Document Number: 002-03288 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 23, 2018
EZ-PD™ CCG3
Logic Block Diagram
Document Number: 002-03288 Rev. *J
Page 2 of 45
EZ-PD™ CCG3
Contents
EZ-PD CCG3 Block Diagram ............................................4
Functional Overview ........................................................5
CPU and Memory Subsystem .....................................5
Crypto Block ................................................................5
Integrated Billboard Device .........................................5
USB-PD Subsystem (USBPD SS) ..............................5
Full-Speed USB Subsystem ........................................6
Peripherals ..................................................................6
GPIO ...........................................................................7
Power Systems Overview ................................................8
Pinouts ..............................................................................9
Available Firmware and Software Tools .......................13
EZ-PD Configuration Utility .......................................13
CCG3 Programming and Bootloading ..........................14
Programming the Device Flash over SWD
Electrical Specifications ................................................23
Absolute Maximum Ratings .......................................23
Device-Level Specifications ......................................24
Digital Peripherals .....................................................26
System Resources ....................................................28
Ordering Information ......................................................34
Ordering Code Definitions .........................................34
Packaging ........................................................................35
Acronyms ........................................................................38
Document Conventions .................................................39
Units of Measure .......................................................39
References and Links to Applications Collaterals .....40
Document History Page .................................................41
Sales, Solutions, and Legal Information ......................45
Worldwide Sales and Design Support .......................45
Products ....................................................................45
PSoC® Solutions ......................................................45
Cypress Developer Community .................................45
Technical Support .....................................................45
Interface .....................................................................14
Application Firmware Update over Specific
Interfaces (I2C, CC, USB) .........................................14
Applications ....................................................................17
Document Number: 002-03288 Rev. *J
Page 3 of 45
EZ-PD™ CCG3
EZ-PD CCG3 Block Diagram
Figure 1. EZ-PD CCG3 Block Diagram[1]
CPU Subsystem
CCG3
SWD/TC
Cortex
M0
48 MHz
FAST MUL
SPCIF
FLASH
2x64 KB
SRAM
8 KB
ROM
8 KB
32-bit
AHB-Lite
Read Accelerator
SRAM Controller
ROM Controller
NVIC, IRQMX
System Resources
Lite
System Interconnect (Single Layer AHB)
Peripheral Interconnect (MMIO)
Power
Sleep Control
WIC
Peripherals
POR
REF
PCLK
PWRSYS
Clock
Clock Control
WDT
USB-FS
USB-PD SS
IMO
ILO
Reset
Reset Control
XRES
Test
DFT Logic
DFT Analog
Pads, ESD
FS-PHY
Power Modes
Active/Sleep
Deep Sleep
High Speed I/O Matrix
22 x GPIOs, 2 x OVTs
I/O Subsystem
Note
1. See Acronyms section for more details.
Document Number: 002-03288 Rev. *J
Page 4 of 45
EZ-PD™ CCG3
Functional Overview
CPU and Memory Subsystem
CPU
USB-PD Subsystem (USBPD SS)
The USB-PD subsystem contains all of the blocks related to USB
Type-C and Power Delivery. The subsystem consists of the
following:
The Cortex-M0 CPU in EZ-PD CCG3 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
■ BiphaseMarkedCoding(BMC)PHY:USB-PDTransceiverwith
Fast Role Swap (FRS) transmit and detect
■ VCONN power FETs for the CC lines
■ VCONN R Termination and Leakers
A
■ Analog Crossbar to switch between the SBU1/SBU2 and
AUX_P/AUX_N pins
■ Programmable pull-up and pull-down termination on the
AUX_P/AUX_N pins
■ Hot Plug Detect (HPD) processor
■ VBUS_C regulator (20V LDO)
■ Power switch between VSYS supply and VBUS_C regulator
output
The CPU also includes a serial wire debug (SWD) interface,
which is a two-wire form of JTAG. The debug configuration used
for EZ-PD CCG3 has four break-point (address) comparators
and two watchpoint (data) comparators.
■ VBUS_C overvoltage (OV) and undervoltage (UV) detectors
■ Current sense amplifier (CSA) for overcurrent detection
■ Gate Drivers for VBUS_P and VBUS_C external Power FETs
■ VBUS_C discharge switch
Flash
The EZ-PD CCG3 device has a flash module with two banks of
64 KB flash, a flash accelerator, tightly coupled to the CPU to
improve average access times from the flash block. The flash
block is designed to deliver 1 wait-state (WS) access time at
48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash module can be used
to emulate EEPROM operation if required.
■ USB2.0 Full-Speed (FS) PHY with integrated 5.0 V to 3.3 V
regulator
■ Charger Detection/Emulation for USB BC1.2 and other
proprietary protocols
■ Two instances of 8-bit SAR ADCs
SROM
■ 8-kV IEC ESD Protection on the following pins: VBUS_C, CC1,
CC2, SBU1, SBU2, DP, DM
Asupervisory ROM that contains boot and configuration routines
is provided.
The EZ-PD CCG3 USB-PD subsystem interfaces to the pins of
a USB Type-C connector. It includes a USB Type-C baseband
transceiver and physical-layer logic. This transceiver performs
the BMC and the 4b/5b encoding and decoding functions as well
as integrating the 1.2-V analog front end (AFE). This subsystem
integrates the required terminations to identify the role of the
Crypto Block
CCG3 integrates
a crypto block for hardware assisted
authentication of firmware images. It also supports field
upgradeability of firmware in a trusted ecosystem. The CCG3
Crypto block provides cryptography functionality. It includes
hardware acceleration blocks for Advanced Encryption Standard
(AES) block cipher, Secure Hash Algorithm (SHA-1 and SHA-2),
Cyclic Redundancy Check (CRC), and pseudo random number
generation.
CCG3 device, including R and R for UFP/DFP roles and R
P
D
A
for EMCA/VCONN powered accessories. The programmable
VCONN leakers are included to discharge VCONN capacitance
during a disconnect event. It also integrates power FETs for
supplying VCONN power to the CC1/CC2 pins from the V5V pin.
The analog crossbar enables connecting either of the
SBU1/SBU2 pins to either of the AUX_P/AUX_N pins to support
DisplayPort sideband signaling. The integrated HPD processor
can be used to control or monitor the HPD signal of a DisplayPort
source or sink.
Integrated Billboard Device
CCG3 integrates a complete full speed USB 2.0 device controller
capable of functioning as a Billboard class device. The USB 2.0
device controller can also support other device classes.
Document Number: 002-03288 Rev. *J
Page 5 of 45
EZ-PD™ CCG3
The Overvoltage/Undervoltage (OV/UV) block monitors the
VBUS_C supply for programmable overvoltage and
undervoltage conditions. The CSA amplifies the voltage across
an external sense resistor, which is proportional to the current
being drawn from the external DC-DC VBUS supply converter.
The CSA output can either be measured with an ADC or
configured to detect an overcurrent condition. The VBUS_P and
VBUS_C gate drivers control the gates of external power FETs
for the VBUS_C and VBUS_P supplies. The gate drivers can be
configured to support both P and N type external power FETs.
The gate drivers are configured by default for nFET devices. In
applications using pFETs, the gate drivers must be appropriately
configured. The OV/UV and CSA blocks can generate interrupts
to automatically turn off the power FETs for the programmed
overvoltage and overcurrent conditions. The VBUS_C discharge
switch allows for discharging the VBUS_C line through an
external resistor.
The USB-PD subsystem also contains two 8-bit Successive
Approximation Register (SAR) ADCs for analog to digital
conversions. The voltage reference for the ADCs is generated
from the VDDD supply. Each ADC includes an 8-bit DAC and a
comparator. The DAC output forms the positive input of the
comparator. The negative input of the comparator is from a
4-input multiplexer. The four inputs of the multiplexer are a pair
of global analog multiplex busses, an internal bandgap voltage
and an internal voltage proportional to the absolute temperature.
Each GPIO pin can be connected to the global Analog Multiplex
Busses through a switch, which allows either ADC to sample the
pin voltage. When sensing the GPIO pin voltage with an ADC,
the pin voltage cannot exceed the VDDIO supply value.
Figure 2. USB-PD Subsystem
CONSUMER N/PFETs
charger
dc-dc
PRODUCER N/PFETs
VBUS_P_CTRL
OC
VBUS_C_CTRL
VBUS_P
VBUS_DISCHARGE
Gate
Gate
Driver
Driver
CSA
VDDD
VSYS
VBUS_C
POWER
SWITCH
LDO
VCONN
RA
OV/UV
VCONN
SWITCH
CC1
CC2
Leaker
V5V
PROGRAMMABLE
PULL-UP, PULL-DOWN
BMC
PHY w/ FRS
AUX_P
AUX_N
SBU1
ANALOG
CROSS-BAR
SBU2
DP
HPD
2x
ADCs
USB 2.0
FS PHY
HPD
CHARGER
DETECT
DM
USB PD SubSystem
2
In the I C mode, the SCB blocks are capable of operating at
speeds of up to 1 Mbps (Fast Mode Plus) and have flexible
buffering options to reduce interrupt overhead and latency for the
Full-Speed USB Subsystem
The FSUSB subsystem contains a full-speed USB device
controller as described in the Integrated Billboard Device
section.
2
CPU. These blocks also support I C that creates a mailbox
address range in the memory of EZ-PD CCG3 and effectively
reduce I C communication to reading from and writing to an
array in memory. In addition, the blocks support 8-deep FIFOs
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock
stretching caused by the CPU not having read data on time.
2
Peripherals
Serial Communication Blocks (SCB)
EZ-PD CCG3 has four SCBs, which can be configured to
2
2
implement an I C, SPI, or UART interface. The hardware I C
blocks implement full multi-master and slave interfaces capable
of multimaster arbitration. In the SPI mode, the SCB blocks can
be configured to act as master or slave.
2
2
The I C peripherals are compatible with the I C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I C-bus specification and user manual (UM10204).
2
2
The I C bus I/Os are implemented with GPIO in open-drain
modes.
Document Number: 002-03288 Rev. *J
Page 6 of 45
EZ-PD™ CCG3
2
The I C port on SCB 1-3 blocks of EZ-PD CCG3 are not
GPIO
2
completely compliant with the I C specification in the following
EZ-PD CCG3 has up to 20 GPIOs (these GPIOs can be
configured for GPIOs, SCB, SBU, and Aux signals) and SWD
pins, which can also be used as GPIOs. The I C pins from SCB
aspects:
2
2
■ The GPIO cells for SCB 1's I Cport arenot overvoltage-tolerant
and, therefore, cannot be hot-swapped or powered up
independently of the rest of the I C system.
0 are overvoltage-tolerant.
2
The GPIO block implements the following:
■ Seven drive strength modes:
❐ Input only
■ Fast-mode Plus has an I specification of 20 mA at a V of
OL
OL
0.4 V. The GPIO cells can sink a maximum of 8-mA I with a
OL
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
V
maximum of 0.6 V.
OL
■ Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.
Timer/Counter/PWM Block (TCPWM)
■ Input threshold select (CMOS or LVTTL)
EZ-PD CCG3 has four TCPWM blocks. Each implements a
16-bit timer, counter, pulse-width modulator (PWM), and
quadrature decoder functionality.
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■ Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
■ Selectable slew rates for dV/dt related noise control to improve
EMI
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
connect to an I/O pin.
Document Number: 002-03288 Rev. *J
Page 7 of 45
EZ-PD™ CCG3
Power Systems Overview
Figure 3 shows an overview of the CCG3 power system
requirement. CCG3 shall be able to operate from two possible
external supply sources VBUS (4.0 V–21.5 V) or VSYS (2.7 V–
5.5 V). The VBUS supply is regulated inside the chip with a
low-dropout regulator (LDO) down to 3.3-V level. The chip’s
internal VDDD rail is intelligently switched between the output of
the VBUS regulator and unregulated VSYS. The switched
supply, VDDD is either used directly inside some analog blocks
or further regulated down to VCCD which powers majority of the
core using regulators. Besides Reset mode, CCG3 has three
different power modes: Active, Sleep and Deep Sleep,
transitions between which are managed by the Power System.
A separate power domain VDDIO is provided for the GPIOs. The
VDDD and VCCD pins, both the output of regulators are brought
out for connecting a 1-µF capacitor for the regulator stability only.
These pins are not supported as power supplies. When CCG3 is
powered from VSYS that is greater than 3.3 V, the dedicated
USB regulator allows USB operation.
Figure 3. EZ-PD CCG3 Power System Block Diagram
VSYS
VBUS
Switch
LDO
1uF
1uF
VBUS_P
VBUS_DISCHARGE
VBUS_C_CTRL
OC
OVP Gate Driver
USB Regulator
OCP
VDDD
VBUS_P_CTRL
VCONN
Gate Driver
1uF
RA
Regulator
FS-USB
TX/RX
DP, DM
VCCD
1uF
CC
Tx/Rx
VDDIO
VSS
Core
CC1, CC2
VSS
GPIO
CCG3
Table 1. CCG3 Power Modes
Mode
Description
Power is Valid and XRES is not asserted. An internal reset source is asserted or SleepController
is sequencing the system out of reset.
RESET
ACTIVE
SLEEP
Power is Valid and CPU is executing instructions.
Power is Valid and CPU is not executing instructions. All logic that is not operating is clock gated
to save power.
Main regulator and most hard-IP are shut off. Deep Sleep regulator powers logic, but only
low-frequency clock is available.
DEEP SLEEP
Document Number: 002-03288 Rev. *J
Page 8 of 45
EZ-PD™ CCG3
Pinouts
Table 2. CCG3 Pin Description for 42-CSP, 32-QFN, and 40-QFN Devices
Pin Map
42-CSP
Pin Map
32-QFN
Pin Map
40-QFN
Name
Description
A5
A6
B6
C5
1
1
1
2
VBUS_P_CTRL1 VBUS Gate Driver Control 1 for Producer Switch
VBUS_P_CTRL0 VBUS Gate Driver Control 0 for Producer Switch
2
3
CC2
CC2
USB PD connector detect/Configuration Channel 2
USB PD connector detect/Configuration Channel 2
Input Supply Voltage for VCONN FETs
N/A
N/A
D4
3
4
V5V
V5V = 5.0V – 5.5V to supply VCONN > 4.75V @ 1.5W
V5V = 3.5V – 5.5V to supply VCONN > 3.00V @ 1W
C6
D6
4
5
CC1
CC1
USB PD connector detect/Configuration Channel 1
USB PD connector detect/Configuration Channel 1
N/A
N/A
VCONN Input - provides R termination for cable
applications
A
E6
N/A
6
VCONN
F6
D5
5
7
8
P1.0
P1.1
GPIO/UART_2_TX / SPI_2_MISO
GPIO/UART_2_RX / SPI_2_SEL
N/A
GPIO/UART_0_RX/ UART_3_CTS/ SPI_3_MOSI/
I2C_3_SCL
E5
G6
E4
F5
G5
G4
F4
6
7
9
P1.2
P1.3
GPIO/UART_0_TX/ UART_3_RTS/ SPI_3_CLK/
I2C_3_SDA
10
11
12
13
14
15
DisplayPort AUX_P signal / GPIO / UART_1_TX /
SPI_1_MISO
N/A
8
AUX_P / P1.6
SBU1 / P1.4
SBU2 / P1.5
AUX_N / P1.7
P2.0
USB Type-C SBU1 signal / GPIO / UART_3_TX/
SPI_3_MISO/ SWD_1_CLK
USB Type-C SBU2 signal / GPIO / UART_3_RX/
SPI_3_SEL/ SWD_1_DAT
9
DisplayPort AUX_N signal / GPIO / UART_1_RX /
SPI_1_SEL
N/A
10
GPIO / UART_1_CTS / SPI_1_CLK/ I2C_1_SCL /
SWD_0_DAT
GPIO / UART_1_RTS / SPI_1_MOSI/ I2C_1_SDA /
SWD_0_CLK
G3
G2
F3
11
13
14
16
17
18
P2.1
VDDD
VDDIO
VDDD supply Input / Output (2.7 V–5.5 V)
1.71 V–5.5 V supply for I/Os. This supply also powers the
global analog multiplex buses.
F2
G1
F1
E1
E2
D3
D2
D1
15
16
17
18
19
20
N/A
21
19
20
21
22
23
24
25
26
VCCD
VSYS
DPLUS
DMINUS
P2.4
1.8-V regulator output for filter capacitor
System power supply (2.7 V–5.5 V)
USB 2.0 DP
USB 2.0 DM
GPIO
P2.5
GPIO / UART_0_TX/ SPI_0_MOSI
GPIO / UART_0_RX/ SPI_0_CLK
External Reset Input. Internally pulled-up to VDDIO.
P2.6
XRES
I2C_0_SDA / GPIO_OVT / UART_0_CTS / SPI_0_SEL/
TCPWM0
C3
22
27
P0.0
Document Number: 002-03288 Rev. *J
Page 9 of 45
EZ-PD™ CCG3
Table 2. CCG3 Pin Description for 42-CSP, 32-QFN, and 40-QFN Devices (continued)
Pin Map
42-CSP
Pin Map
32-QFN
Pin Map
40-QFN
Name
Description
I2C_0_SCL / GPIO_OVT / UART_0_RTS / SPI_0_MISO/
TCPWM1
C2
23
28
P0.1
C1
C4
B1
A1
24
24
29
30
VBUS_C_CTRL1 VBUS Gate Driver Control 1 for Consumer Switch
VBUS_C_CTRL0 VBUS Gate Driver Control 0 for Consumer Switch
25
31
VBUS
VBUS Input
26
32
VBUS_DISCHARGE VBUS Discharge Control output
12, 27
EPAD
28
33
VSS
E3
Ground Supply (GND)
VSS
EPAD
34
A2
B2
P3.2
P3.3
GPIO / TCPWM0
GPIO / TCPWM1
N/A
35
GPIO / UART_2_CTS / SPI_2_MOSI/ I2C_2_SDA /
TCPWM2
B3
29
36
P3.4
A3
B4
A4
B5
30
N/A
31
37
38
39
40
P3.5
P3.6
GPIO / UART_2_RTS / SPI_2_CLK/ I2C_2_SCL / TCPWM3
GPIO
OC
Overcurrent sensor input
VBUS producer input
32
VBUS_P
Document Number: 002-03288 Rev. *J
Page 10 of 45
EZ-PD™ CCG3
Figure 4. Pinout of 40-QFN Package (Top View)
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
VBUS_P_CTRL1
VBUS_P_CTRL0
CC2
VBUS_C_CTRL0
VBUS_C_CTRL1
GPIO_OVT
GPIO_OVT
XRES
V5V
CC1
EPAD
VCONN
GPIO
GPIO
GPIO
GPIO
GPIO
DMINUS
DPLUS
GPIO
GPIO
Figure 5. Pinout of 32-QFN Package (Top View)
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VBUS_P_CTRL
CC2
VBUS_C_CTRL
GPIO_OVT
GPIO_OVT
XRES
V5V
CC1
EPAD
GPIO
GPIO
GPIO
GPIO
DMINUS
DPLUS
GPIO
SBU1
Document Number: 002-03288 Rev. *J
Page 11 of 45
EZ-PD™ CCG3
Figure 6. Pinout of 42-WLCSP Bottom (Balls Up) View
6
5
4
3
2
1
VBUS_P_CT VBUS_P_CT
GPIO
P3.5
GPIO
P3.2
VBUS_DISC
HARGE
A
B
C
D
E
F
OC
RL0
CC2
RL1
GPIO
P3.6
GPIO
P3.4
GPIO
P3.3
VBUS_P
VBUS
VBUS_C_CT GPIO_OVT
GPIO_OVT VBUS_C_CT
P0.1
CC1
CC1
CC2
RL0
P0.0
RL1
GPIO
P1.1
GPIO
P2.5
GPIO
P2.6
V5V
XRES
GPIO
P1.2
GPIO
P2.4
VCONN
AUX_P
VSS
DMINUS
DPLUS
VSYS
GPIO
P1.0
GPIO
P2.0
SBU1
SBU2
VDDIO
VCCD
VDDD
GPIO
P1.3
GPIO
P2.1
G
AUX_N
Document Number: 002-03288 Rev. *J
Page 12 of 45
EZ-PD™ CCG3
Available Firmware and Software Tools
EZ-PD Configuration Utility
The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through
the process of configuring and programming the chip. The utility allows users to:
1. Select and configure the parameters they want to modify
2. Program the resulting configuration onto the target CCGx device.
The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB
interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers
implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port
controllers, will be provided in later versions of the utility.
You can download the EZ-PD Configuration Utility and its associated documentation at the following link:
http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility
Document Number: 002-03288 Rev. *J
Page 13 of 45
EZ-PD™ CCG3
As shown in the block diagram in Figure 7, the SWD_0_DAT and
SWD_0_CLK pins are connected to the host programmer's
SWDIO (data) and SWDCLK (clock) pins respectively. During
SWD programming, the device can be powered by the host
programmer by connecting its VTARG (power supply to the
target device) to VSYS pin of CCG3 device. If the CCG3 device
is powered using an on-board power supply, it can be
CCG3 Programming and Bootloading
There are two ways to program application firmware into a CCG3
device:
1. Programming the device flash over SWD Interface
2. Application firmware update over specific interfaces (CC,
2
USB, I C)
programmed using the “Reset Programming” option. For more
details, refer to the CYPD3XXX Programming Specifications.
Generally, the CCG3 devices are programmed over SWD
interface only during development or during the manufacturing
process of the end product. Once the end product is manufac-
tured, the CCG3 device's application firmware can be updated
via the appropriate bootloader interface.
The CYPD3105 device for Thunderbolt cable applications is
pre-programmed with a micro-bootloader that allows users to
program the flash using the alternate SWD pins (SBU1 for
SWD_1_CLK and SBU2 for SWD_1_DAT) that can be
connected to the SBU interface of a Type-C connector. Note that
this interface can be used to program the flash only once. Subse-
quent re-programming of this device can be done through the
primary SWD interface (SWD_0_CLK and SWD_0_DAT pins).
Irrespective of which SWD interface is used for programming the
device, once the device is programmed with the hex file provided
by Cypress for thunderbolt cable application, subsequent
updates to the application firmware can be done over the CC
line. Refer to Application Firmware Update over Specific Inter-
faces (I2C, CC, USB) for more details.
Programming the Device Flash over SWD Interface
The CCG3 family of devices can be programmed using the SWD
interface. Cypress provides a programming kit (CY8CKIT-002
MiniProg3 Kit) called MiniProg3 which can be used to program
the flash as well as debug firmware. The flash is programmed by
downloading the information from a hex file. This hex file is a
binary file generated as an output of building the firmware project
in PSoC Creator Software. Click here for more information on
how to use the MiniProg3 programmer. There are many
third-party programmers that support mass programming in a
manufacturing environment.
Figure 7. Connecting the Programmer to CYPD3xxx Device
3.0 V
VDD
Host Programmer
CYPD3xxx
VCCD
1F
10V
X7R
VDD
VSYS
SWDCLK
SWDIO
XRES
SWD_0_CLK
VDDD
SWD_0_DAT
XRES
1F
10V
X7R
VDDIO
GND
VSS
GND
Application Firmware Update over I2C Interface
Application Firmware Update over Specific Interfaces
(I C, CC, USB)
2
This method primarily applies to CYPD3122, CYPD3125, and
CYPD3126 devices of the CCG3 family. In these applications,
the CCG3 device interfaces to an on-board application
The application firmware can be updated over three different
interfaces depending on the default firmware programmed into
the CCG3 device. Refer to Table 38 for more details on default
firmware that various part numbers of the CCG3 family of
devices are pre-programmed with (note that some of the devices
have bootloader only and some have bootloader plus application
firmware). The application firmware provided by Cypress for all
CCG3 applications have dual images. This allows fail-safe
update of the alternate image while executing from the current
image. For more information, refer to the EZ-PD Configuration
Utility User Manual.
2
processor or an embedded controller over I C interface. Refer to
Figure 8 for more details. Cypress provides pseudo-code for the
host processor for updating the CCG3 device firmware.
Document Number: 002-03288 Rev. *J
Page 14 of 45
EZ-PD™ CCG3
Figure 8. Application Firmware Update over I2C Interface
VDDD
2.2K 2.2K
2.2K
I2C_SDA
I2C_SCL
I2C_INT
Embedded Controller/
Application Processor
CYPD3xxx Device
To be Programmed
Application Firmware Update over CC Line
CY4531 CCG3 EVK is connected to the system containing the
CCG3 device on one end and a Windows PC running the
EZ-PDTM Configuration Utility as shown in Figure 9 on the other
end to program the CCG3 device.
This method primarily applies to the CYPD3135 device of the
CCG3 family. In these applications, the CY4531 CCG3 EVK can
be used to send programming and configuration data as Cypress
specific Vendor Defined Messages (VDMs) over the CC line. The
Figure 9. Application Firmware Update over CC Line
USB Serial Device of
CCG3 Daughter Card
USB Mini-B
cable
I2C
PC
Running
EZ-PD Configuration
Utility
CC Line
CYPD3135 device
to be Programmed
CCG3 Device on
CCG3 Daughter Card
Type-C
Receptacle
Mini-B
Receptacle
CY4531 CCG3 EVK
Application Firmware Update over USB
user has a Type-A to Type-C cable. This option requires that the
system contain the CCG3 device to be programmed to have a
Type-C receptacle. The other option (Option 3) is to have a
Windows PC with a native Type-C connector as shown in
Figure 10.
This method primarily applies to the CYPD3120 and CYPD3121
devices of the CCG3 family. In these applications, the firmware
update can be performed over the D+/D- lines (USB2.0) using
various possible options as shown in Figure 10. Option 1 is to
have a Windows PC running EZ-PD Configuration Utility
connected to the device to be programmed via the CY4531
CCG3 EVK. This setup can be avoided using option 2, where the
Document Number: 002-03288 Rev. *J
Page 15 of 45
EZ-PD™ CCG3
Figure 10. Application Firmware Update over USB
Option 1
USB Type-A to
Type-B cable
PC
Running
EZ-PD Configuration
Utility
D+/D-
CYPD 312x device
to be Programmed
Type-B
Receptacle
Type-C
Receptacle
CY4531 CCG3 EVK
OR
Option 2
USB Type-A to
Type-C cable
PC
Running
EZ-PD Configuration
Utility
CYPD 312x device
to be Programmed
OR
Option 3
Windows PC with
Native Type-C
Connector Running
EZ-PD Configuration
Utility
CYPD 312x device
to be Programmed
Type-C plug
Type-C
Receptacle
Document Number: 002-03288 Rev. *J
Page 16 of 45
EZ-PD™ CCG3
Applications
Figure 11 illustrates the application diagram of a power adapter
using a CCG3 device. In this application, CCG3 is used as DFP
(power provider) only. The maximum power profile that can be
supported by power adapters is up to 20 V, 100 W using 40-pin
QFN CCG3 devices. CCG3 has the ability to drive both types of
FETs and the state of GPIO P1.0 (floating or grounded) indicates
the type of FET (N-MOS or P-MOS FET) being used in the power
provider path.
The power provider FETs are controlled by high-voltage gate
driver outputs (VBUS_P_CTRL0 and VBUS_P_CTRL1 pins of
CCG3 device). The CCG3 device is also capable of supporting
proprietary charging protocols over the DP and DM lines of the
Type-C receptacle. By providing a 5-V source at the V5V pin of
the CCG3 device, the device becomes capable of delivering the
VCONN supply over either the CC1 or CC2 pins of the Type-C
connector.
CCG3 integrates all termination resistors and uses GPIOs
(VSEL0 and VSEL1) to indicate the negotiated power profile. If
required, the power profile can also be selected using CCG3
serial interfaces (I2C, SPI) or PWM. The VBUS voltage on the
Type-C port is monitored using internal circuits to detect under-
voltage and overvoltage conditions. To ensure quick discharge
of VBUS when the power adapter cable is detached, a discharge
path is provided with a resistor connected to the VBUS_DIS-
CHARGE pin of the CCG3 device.
The CCG3 family's power adapter parts are shipped with
bootloader and application firmware with limited functionality. Its
purpose is to facilitate application flashing over CC line using the
EZ-PD Configuration Utility. The power adapter requires an
explicit power contract to be negotiated prior to enabling the
EZ-PD Configuration utility to flash the application firmware. This
application firmware, based on the state of the GPIO (P1.0),
determines the type of provider load switch (NFET/PFET) and
supplies the 5-V VBUS over Type-C.
Overcurrent protection is enabled by sensing the current through
the 10-m sense resistor using the “OC” and “VBUS_P” pins of
the CCG3 device. The VBUS provider through the Type-C
connector can be turned on or off using the provider path FETs.
Figure 11. Power Adapter Application Diagram (40-QFN Device)
VBUS_OC
DC/DC
OR
VBUS_IN
VBUS_OUT
DMN3018SSD-13
DMN3018SSD-13
VBUS
S
D
D
S
AC-DC Secondary
(5-20V)
10 m 1%
G
G
10F
50V
10M
10M
VSEL2
VSEL1
100
2
39
OC
VBUS_P_CTRL0
VBUS_P_CTRL1
28
1
VSEL2/P0.0
27
VSEL1/P0.1
32
VBUS_DISCHARGE
CC2
40
31
3
5
VBUS_P
VBUS
CC2
CC1
CC1
1F
29
50V
X7R
33
20
17
VBUS_C_CTRL1
X
X
390pF
5%
X7R
390pF
5%
X7R
GND
Type-C
Receptacle
CYPD3135-40LQXIT
VSYS
X
30
4
VBUS_OUT
5V
VBUS_C_CTRL0
40QFN
VDDD
V5V
P2.4
100K
18
23
VDDIO
AUX_P
AUX_N
VCONN
10K
11
14
6
X
21
22
1F
10V
X7R
DPLUS
DMINUS
GPIO
X
X
8, 9, 10, 15, 16, 24, 25,
34, 35, 36, 37, 38
XRES
26
VCCD
19
SBU1 SBU2
12 13
P1.0
7
1.3F
10V
X7R
X
X
X
P1.0 indicates FET type in design.
Floating condition indicates NFETs
and connected to GND indicates
PFETs in provider path.
GND
0.1F
Document Number: 002-03288 Rev. *J
Page 17 of 45
EZ-PD™ CCG3
Figure 12 illustrates a power bank application diagram using a
CCG3 device. In this application, the Type-C receptacle is used
for providing as well as consuming power. The consumer path
will be active when the battery is charged using a Type-C power
source that is connected to the Type-C receptacle in Figure 12.
The provider path will be active when the power bank is used for
providing power to a sink device connected to the Type-C recep-
tacle. Additionally, a Type-A receptacle can also be provided for
providing power to the sinks that have a legacy USB interface.
The CCG3 device negotiates power contracts between the
power bank and the sink/source device connected to the Type-C
receptacle. The CCG3 device also controls and drives the
provider and consumer path FETs and can monitor overcurrent
and overvoltage conditions on the Type-C VBUS line.
Figure 12. Power Bank Application Diagram (40-QFN Device)
DMN3018SSD-13
DMN3018SSD-13
Consumer Path
CCG3 gate driver control configuration
needs to be appropriately set, based
on the VBUS FET type (nFET/pFET).
D
S
S
D
G
G
Power
Subsystem
+
10M
10M
VBUS
Provider Path
Battery
DMN3018SSD-13
DMN3018SSD-13
S
D
D
S
1F
35V
X7R
10 m 1%
10F
G
G
10M
50V
10M
2
1
39
OC
VBUS_P_CTRL0 VBUS_P_CTRL1
VBUS_C_CTRL1
VBUS
X
4
29
V5V
31
VBUS
40
VBUS_P
VSYS
VBATT
VBUS
20
0.1F
10V
0.1F
10V
1F
10V
100
30
32
VBUS_C_CTRL0
7, 8, 15, 16, 23,
24, 25, 27, 28, 38
GPIO
VBUS_DISCHARGE
CC2
3
5
17
18
CC2
CC1
VDDD
CYPD3121-40LQXIT
CC1
0.1F
10V
0.1F
10V
1F
10V
40QFN
VDDIO
390pF
5%
X7R
Type-C
Receptacle
6
390pF
5%
X7R
VCONN
X
12
21
GPIO/SBU1
GPIO/SBU2
X
DPLUS
13
22
11
X
DMINUS
37
36
I2C_SCL/GPIO
I2C_SDA/GPIO
GPIO
AUX_P/GPIO
X
14
AUX_N/GPIO
XRES
X
34
X
SS
26
33
DP
DN
0.1F
10V
X7R
GND
I2C_
SCL/GPIO SDA/GPIO
10
I2C_
GPIO
VCCD
19
GND
35
9
1uF
10V
X7R
From Power
Subsystem
VBUS
Type-A
Receptacle
Discrete Ckts to
support Legacy
Charge Source
CCG3
GPIO
DP
DN
GND
Document Number: 002-03288 Rev. *J
Page 18 of 45
EZ-PD™ CCG3
Figure 13 illustrates a USB Type-C to DisplayPort (4-lane) adapter application, which enables connectivity between a PC that supports
a Type-C port with DisplayPort Alternate Mode support and a legacy monitor that has a DisplayPort interface.
The application meets the requirements described in Section 4.2 of the VESA DisplayPort Alt Mode on USB Type-C Standard Version
1.0 (Scenarios 2a and 2b USB Type-C to DisplayPort Cables).
Figure 13. USB Type-C to DisplayPort Adapter Application Diagram
2
1
39
OC
VBUS_P_CTRL0 VBUS_P_CTRL1
VBUS_C_CTRL1
4
29
6
V5V
31
40
VBUS
VBUS_P
VBUS
1F
10V
VCONN
VCONN
VCONN
20
VSYS
0.1F
10V
0.1F
10V
1F
10V
30
32
VBUS_C_CTRL0
7, 8, 15, 16, 24,
25, 27, 28, 38
GPIO
VBUS_DISCHARGE
CC2
3
5
17
VDDD
CYPD3120-40LQXIT
CC1
CC
0.1F
10V
1F
10V
18
37
36
1F
10V
40QFN
VDDIO
390pF
5%
X7R
I2C_SCL / P3.5
I2C_SDA / P3.4
I2C_INT / P3.2
mDP/
DP
Type-C Plug
21
DPLUS
DP
34
22
12
13
DMINUS
SBU1
DN
11
14
35
AUX_P
SBU1
AUX_N
SBU2
XRES
SBU2
SS
HotPlug Detect
26
33
HOTPLUG_DET / P3.3
0.1F
10V
X7R
GND
MUX_I2C_ MUX_I2C_
SCL/P1.2 SDA/P1.3
P2.4
VCCD
GND
23
19
9
10
1F
10V
X7R
X
P2.4 indicates type of end application. Floating
condition indicates usage for Type-C to DP
application and connected to GND indicates
usage for Type-C to HDMI adapter application.
Display Port Data Lanes
Document Number: 002-03288 Rev. *J
Page 19 of 45
EZ-PD™ CCG3
Figure 14 illustrates a USB Type-C to HDMI adapter application, which enables connectivity between a PC that supports a Type-C
port with DisplayPort Alternate Mode support and a legacy monitor that has HDMI interface. It enables users of any Notebook that
implements USB-Type C to connect to other display types.
This application meets the requirements described in Section 4.3 of the VESADisplayPort Alt Mode on USB Type-C Standard Version
1.0. This application supports display output at a resolution of up to 4K Ultra HD (3840x2160) at 60 Hz.
Figure 14. USB Type-C to HDMI Adapter Application
VBUS
1.2V
5V
VCONN
Power
OR
3.3V
Regulator
BuckBoost
5V BuckBoost not
needed for DVI/VGA
2
1
39
OC
P2.4 indicates type of end application.
VBUS_P_CTRL0 VBUS_P_CTRL1
Floating condition indicates usage for
Type-C to DP application and connected
to GND indicates usage for Type-C to
HDMI adapter application.
29
23
VBUS_C_CTRL1
P2.4
4
V5V
31
40
VBUS
VBUS_P
VBUS
1uF
10V
6
VCONN
VCONN
VCONN
20
VSYS
0.1uF
10V
0.1uF
10V
1uF
10V
30
32
VBUS_C_CTRL0
7, 8, 15, 16, 24,
25, 27, 28, 38
GPIO
VBUS_DISCHARGE
CC2
3.3V
3
5
HDMI/
DVI/
VGA
18
VDDIO
VDDD
CYPD3120-40LQXIT
CC1
CC
17
37
36
40QFN
0.1uF
10V
1uF
10V
Type-C
Plug
1uF
10V
390pF
5%
X7R
I2C_SCL / P3.5
I2C_SDA / P3.4
I2C_INT / P3.2
21
DPLUS
DP
34
22
12
13
DMINUS
SBU1
DN
11
14
AUX_P
AUX_N
SBU1
SBU2
XRES
SBU2
SS
26
33
0.1uF
10V
X7R
AUX_P/N
HOTPLUG_
DET / P3.3
GND
35
MUX_I2C_ MUX_I2C_
SCL/P1.2 SDA/P1.3
VCCD
19
GND
9
10
1uF
10V
X7R
HotPlug
Detect
1.2V
3.3V
DP to HDMI/
DVI/VGA
Convertor
Display Port
Data Lanes
Document Number: 002-03288 Rev. *J
Page 20 of 45
EZ-PD™ CCG3
Figure 15 illustrates a Notebook DRP application diagram using a CCG3 device. The Type-C port can be used as a power provider
2
or a power consumer. The CCG3 device communicates with the embedded controller (EC) over I C. It also controls the Data Mux to
route the HighSpeed signals either to the USB chipset (during normal mode) or the DisplayPort Chipset (during Alternate Mode). The
SBU, SuperSpeed, and HighSpeed lines are routed directly from the Display Mux of the notebook to the Type-C receptacle.
Figure 15. DRP Application Diagram
VINT20
DMN3018SSD-13
DMN3018SSD-13
Charger
DC/DC
D
S
S
D
G
G
10M
10M
VBUS
VBUS_SUPPLY
DMN3018SSD-13
DMN3018SSD-13
S
D
D
S
1uF
35V
X7R
10 m 1%
10uF
50V
G
G
10M
10M
2
1
V3P3 and V5P0 are 3.3V and 5V
supplies coming from the motherboard.
39
OC
VBUS_P_CTRL0 VBUS_P_CTRL1
VBUS_C_CTRL1
V5P0
VBUS
CCG3 gate driver control configuration
needs to be appropriately set, based
on the VBUS FET type (nFET/pFET).
4
31
40
29
V5V
VBUS
VBUS_P
VSYS
V3P3
VBUS
20
0.1uF
10V
0.1uF
10V
1uF
10V
100
30
32
VBUS_C_CTRL0
7, 8, 15, 16, 23,
24, 25, 27, 28, 38
GPIO
VBUS_DISCHARGE
CC2
VDDD
3
5
17
CC2
CC1
VDDD
CYPD3125-40LQXIT
CC1
18
0.1uF
10V
0.1uF
10V
1uF
10V
VDDIO
40QFN
390pF
5%
X7R
Type-C
Receptacle
6
390pF
5%
X7R
VCONN
DPLUS
X
VDDD
12
21
SBU1
SBU2
X
X
13
37
36
2.2K 2.2K
2.2K
22
11
14
DMINUS
I2C_SCL / P3.5
I2C_SDA / P3.4
I2C_INT / P3.2
AUX_P
AUX_N
X
X
Embedded
Controller
34
26
33
XRES
SS
0.1uF
10V
X7R
DP/DN
GND
D+/-
HOTPLUG_
DET / P3.3
GND
MUX_I2C_ MUX_I2C_
SCL/P1.2 SDA/P1.3
VCCD
19
35
9
10
D+/-
SS
1uF
10V
X7R
USB
Chipset
HPD
HS/SS/
DP/SBU
Lines
DisplayPort
Chipset
HPD
SDA
SCL
SS
DP0/1/2/3
AUX+/-
Data Mux
Document Number: 002-03288 Rev. *J
Page 21 of 45
EZ-PD™ CCG3
Figure 16 illustrates a CCG3 device based Charge-through
Dongle application block diagram. This Charge-through dongle
application also implements Cypress’s USB SuperSpeed Hub
controller HX3 (CYUSB3304-68LTXI) available in 68-QFN
package, Low-power single chip USB 3.0 to Gigabit Ethernet
Bridge Controller GX3 (CYUSB3610-68LTXC) available in
68-QFN package and the CCG2 (CYPD2122-24LQXI) which
acts as an Upstream Facing Port (UFP) and sinks power when
connected to USB Type-C chargers.
This application enables connectivity between a USB Type-C
Notebook and HDMI Display, legacy USB device and Gigabit
Ethernet while also connecting a USB Type-C charging cable.
The Charge-ThroughDonglesolution allows simultaneousHDMI
display, Superspeed data transfers, Ethernet connection and
charging of a USB Type-C Notebook. Charge-Through Dongle is
also widely known as Multiport Adapter. More details including
the schematic of the CCG3 device based Charge-through
Dongle reference design can be found here.
Figure 16. Charge-through Dongle Application Block Diagram (40-QFN Device)
5.0V
3.3V
1.2V
VBUS_C
VBUS_N
1.2V
5V
3.3V
Power
VCONN_N
DP to HDMI
Protocol Convertor
MegaChips
2x lane DP
HDMI
Receptacle
4
To Display
MCDP2900
VBUS_A
SS/HS lines
USB3.1
Type-A
Receptacle
DS1
DS2
Legacy USB
devices
Cypress
HX3
CYUSB3304
68-QFN
4
SS lines
HS lines
8
DS3
3.3V 1.2V 5V
To Notebook
Cypress GX3
CYUSB3610
68-QFN
Ethernet Port
VBUS_N
Type-C plug
HS lines
VCONN_N
VBUS_C
CCG3
DRP
CYPD3123
40-QFN
CC
Type-C receptacle From DFP
for Charging
Charger
CCG2
UFP
CC
I2C
CYPD2122
24-QFN
Document Number: 002-03288 Rev. *J
Page 22 of 45
EZ-PD™ CCG3
Electrical Specifications
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings
Parameter
Description
Digital supply relative to V
Min
Typ
Max
Units
Details/Conditions
V
V
–0.5
–
–
–
6
6
V
V
SYS_MAX
SS
Max supply voltage relative to V
Max supply voltage relative to V
5V
SS
SS
,
V
–
–
26
V
BUS_MAX_ON
V
regulator enabled
BUS
Max supply voltage relative to V
,
SS
V
regulator enabled 100% of the
–
–
24.5
V
BUS
time
V
BUS_MAX_OFF
Max supply voltage relative to V
,
SS
V
regulator enabled 25% of the
–
–
26
V
Absolute max
BUS
time
V
V
Max supply voltage relative to V
GPIO voltage
–
–0.5
–0.5
–25
–
–
–
–
–
–
–
6
V
V
DDIO_MAX
SS
VDDIO+ 0.5
GPIO_ABS
V
OVT GPIO voltage
6
25
6
V
GPIO_OVT_ABS
GPIO_ABS
I
Maximum current per GPIO
mA
V
V
V
Max voltage relative to V
SS
CONN_MAX
Max voltage on CC1 and CC2 pins
–
6
V
CC_ABS
GPIO injection current, Max for V
>
IH
I
–0.5
–
–
0.5
–
mA Absolute max, current injected per pin
GPIO_INJECTION
VDDD, and Min for V < V
IL
SS
Electrostatic discharge human body
model
ESD_HBM
2200
V
–
–
Electrostatic discharge charged
device model
ESD_CDM
LU
500
–
–
–
–
100
–
V
Pin current for latch-up
–100
mA Tested at 125 °C
Contact discharge on CC1, CC2, VBUS,
DPLUS, DMINUS, SBU1 and SBU2 pins
ESD_IEC_CON Electrostatic discharge IEC61000-4-2 8000
ESD_IEC_AIR Electrostatic discharge IEC61000-4-2 15000
V
V
Air discharge for CC1, CC2, VBUS,
DPLUS, DMINUS, SBU1 and SBU2 pins
–
–
Document Number: 002-03288 Rev. *J
Page 23 of 45
EZ-PD™ CCG3
Device-Level Specifications
All specifications are valid for –40 °C T 105 °C and T 120 °C, except where noted.
A
J
Table 4. DC Specifications
Spec ID
Parameter
Description
Min
2.7
3
Typ Max Units
Details/Conditions
SID.PWR#1
VSYS
–
–
–
–
5.5
5.5
V
V
UFP Mode.
SID.PWR#1_A VSYS
DFP/DRP or Gate Driver Modes
Power Supply Input
Voltage
SID.PWR#23
SID.PWR#13
SID.PWR24
VCONN
2.7
1.71
–
–
–
5.5
V
V
V
–
2.7V < VDDD < 5.5 V
–
[2]
VDDIO
VCCD
IO Supply Voltage
5.5
Output Voltage for core
Logic
1.8
–
–
From VSYS or VBUS
VBUS = 5V,
SID.PWR#4
IDD
Supply current
–
25
mA T = 25 °C / VSYS = 5 V, TA = 25 °C
A
FS USB, CC IO in Tx or Rx, no I/O sourcing
current, 2 SCBs at 1 Mbps, CPU at 24 MHz.
Power supply for USB
operation
SID.PWR#1_B VSYS
SID.PWR#1_C VSYS
4.5
–
–
5.5
V
V
USB configured, USB Regulator enabled
USB configured, USB Regulator disabled
Power supply for USB
operation
3.15
3.45
Power supply for charger
detect/emulation
operation
SID.PWR#1_D VSYS
3.15
–
5.5
V
–40 °C to +85 °C T
A
Power supply input
voltage
FS USB disabled. Total current consumption
from VBUS <15 mA.
SID.PWR#27
SID.PwR#28
SID.PWR#30
SID.PWR#15
SID.PWR#16
VBUS
3.5
4.5
4.00
1
–
–
21.5
21.5
21.5
1.6
V
V
V
Power supply input
voltage for USB operation
VBUS
FS USB configured, USB Regulator disabled
Power supply input
voltage
VBUS_P
–
Externalregulatorvoltage
bypass for VCCD
C
1.3
1
µF X5R ceramic or better
µF X5R ceramic or better
efc
Power supply decoupling
capacitor for VSYS
C
0.8
–
exc
Sleep Mode. VSYS = 2.7 V to 5.5 V. Typical values measured at V = 3.3 V and TA = 25 °C.
DD
2
CC, I C, WDT wakeup
on.
VSYS = 3.3 V, T = 25 °C, All blocks except
mA CPU are on, CC IO on, USB in Suspend
A
SID25A
I
–
–
3.5
30
–
–
DD20A
IMO at 48 MHz.
Mode, no I/O sourcing current
Deep Sleep Mode
VSYS = 3.0 to 3.6 V. CC
Attach, I C, WDT
Wakeup on.
Power Source = VSYS, DFP Mode, Type-C
2
2
SID_DS
I
µA Not Attached. CC Attach, I C and WDT
DD_DS
enabled for Wakeup.
XRES Current
Supply current while
XRES asserted.
This does not include
current drawn due to the
XRES internal pull-up
resistor.
Power Source = VSYS = 3.3 V, Type-C
SID307
I
–
30
–
µA device not attached,
DD_XR
T = 25 °C
A
Note
2. If VDDIO > VDDD, GPIO P2.4 cannot be used. It must be left unconnected. See Table 2 for pin numbers.
Document Number: 002-03288 Rev. *J
Page 24 of 45
EZ-PD™ CCG3
Table 5. AC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
CPU input frequency
Min Typ Max Units
Details/Conditions
SID.CLK#4
F
DC
–
–
0
–
–
48 MHz All VDDD
CPU
SID.PWR#20 T
SID.PWR#21 T
SID.XRES#5 T
Wakeup from sleep mode
Wakeup from Deep Sleep mode
External reset pulse width
–
35
–
µs
–
–
SLEEP
DEEPSLEEP
XRES
–
µs
5
µs All VDDIO
2
Power-up to “Ready to accept I C/CC
command”
SYS.FES#1
T
–
5
25
ms
–
_PWR_RDY
I/O
Table 6. I/O DC Specifications
Spec ID
SID.GIO#37
SID.GIO#38
SID.GIO#39
SID.GIO#40
SID.GIO#41
SID.GIO#42
SID.GIO#33
SID.GIO#34
SID.GIO#35
Parameter
Description
Input voltage HIGH threshold 0.7 × VDDIO
Input voltage LOW threshold
LVTTL input, VDDIO < 2.7 V 0.7× VDDIO
Min
Typ
Max
Units
V
Details/Conditions
CMOS input
CMOS input
V
V
V
V
V
V
V
V
V
–
–
–
–
–
–
–
–
–
–
IH_CMOS
–
0.3 × VDDIO
V
IL_CMOS
–
V
–
–
–
–
IH_VDDIO2.7-
IL_VDDIO2.7-
IH_VDDIO2.7+
IL_VDDIO2.7+
OH_3V
LVTTL input, VDDIO < 2.7 V
LVTTL input, VDDIO 2.7 V
LVTTL input, VDDIO 2.7 V
Output voltage HIGH level
Output voltage HIGH level
Output voltage LOW level
–
0.3 × VDDIO
V
2.0
–
0.8
–
V
–
V
VDDIO –0.6
VDDIO –0.5
–
V
I
I
I
I
= 4 mA at 3V VDDIO
= 1 mA at 1.8V VDDIO
= 4 mA at 1.8V VDDIO
= 4 mA at 3V VDDIO
OH
OH
OL
OL
–
V
OH_1.8V
0.6
V
OL_1.8V
SID.GIO#36
V
Output voltage LOW level
–
–
0.6
V
OL_3V
for SBU and AUX pins
SID.GIO#5
SID.GIO#6
R
R
Pull-up resistor value
3.5
3.5
5.6
5.6
8.5
8.5
k +25 °C T , all VDDIO
PU
A
Pull-down resistor value
k +25 °C T , all VDDIO
PD
A
+25 °C T , all VDDIO.
nA Guaranteed by
A
Input leakage current
(absolute value)
SID.GIO#16
I
–
–
–
–
2
IL
characterization.
All VDDIO, all packages,
all I/Os except SBU and
AUX. Guaranteed by
characterization.
SID.GIO#17
C
Max pin capacitance
3.0
16
7
pF
PIN
All VDDIO, all packages,
pF SBUpinsonly.Guaranteed
SID.GIO#17A C
SID.GIO#17B C
Max pin capacitance
Max pin capacitance
18
PIN_SBU
by characterization.
All VDDIO, all packages,
pF AUXpinsonly.Guaranteed
by characterization.
–
15
12
40
–
14
–
PIN_AUX
Input hysteresis, LVTTL
VDDIO 2.7 V
Guaranteed by
mV
SID.GIO#43
SID.GIO#44
V
V
I
HYSTTL
characterization
VDDIO < 4.5 V.
mV Guaranteed by characteri-
zation.
Input hysteresis CMOS
0.05 × VDDIO
–
HYSCMOS
Current through protection
diode to VDDIO/Vss
Guaranteed by characteri-
zation
SID69
–
–
–
–
100
85
µA
DIODE
Maximum total sink chip
current
Guaranteed by characteri-
zation
SID.GIO#45
I
mA
TOT_GPIO
Document Number: 002-03288 Rev. *J
Page 25 of 45
EZ-PD™ CCG3
Table 6. I/O DC Specifications (continued)
Spec ID
OVT
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Input current when Pad >
VDDIO for OVT inputs
2
SID.GIO#46
I
–
–
10.00
µA Per I C specification
IHS
Table 7. I/O AC Specifications
(Guaranteed by Characterization)
Spec ID
SID70
Parameter
Description
Rise time in Fast Strong mode
Fall time in Fast Strong mode
Min Typ Max Units
Details/Conditions
T
T
2
2
–
–
12
12
ns 3.3 V VDDIO, C
= 25 pF
RISEF
FALLF
load
load
SID71
ns 3.3 V VDDIO, C
= 25 pF
XRES
Table 8. XRES DC Specifications
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
Input voltage HIGH
threshold on XRES pin
SID.XRES#1 V
SID.XRES#2 V
SID.XRES#3 C
SID.XRES#4 V
0.7 × VDDIO
–
–
V
V
CMOS input
CMOS input
IH_XRES
IL_XRES
IN_XRES
HYSXRES
Input voltage LOW
threshold on XRES pin
–
–
–
–
–
0.3 × VDDIO
Input capacitance on
XRES pin
Guaranteed by charac-
terization
7
–
pF
mV
Input voltage hysteresis
on XRES pin
Guaranteed by charac-
terization
0.05 × VDDIO
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for GPIO Pins
Table 9. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Operating frequency
Min
–
Typ
–
Max Units
Details/Conditions
Fc max = CLK_SYS.
Maximum = 48 MHz.
SID.TCPWM.3
SID.TCPWM.4
T
Fc
–
MHz
ns
CPWMFREQ
PWMENEXT
T
Input trigger pulse width
2/Fc
–
For all trigger events
Minimum possible width of
Overflow, Underflow, and CC
(Counter equals Compare
value) outputs
SID.TCPWM.5
T
Output trigger pulse width
2/Fc
–
–
ns
PWMEXT
Minimum time between
successive counts
SID.TCPWM.5A T
Resolution of counter
PWM resolution
1/Fc
1/Fc
1/Fc
–
–
–
–
–
–
ns
ns
ns
CRES
Minimum pulse width of PWM
output
SID.TCPWM.5B PWM
RES
Minimum pulse width between
quadrature-phase inputs
SID.TCPWM.5C Q
Quadrature inputs resolution
RES
Document Number: 002-03288 Rev. *J
Page 26 of 45
EZ-PD™ CCG3
I2C
2
Table 10. Fixed I C DC Specifications
(Guaranteed by Characterization)
Spec ID
SID149
Parameter
Description
Min
–
Typ
–
Max Units
Details/Conditions
I
I
I
I
Block current consumption at 100 kHz
Block current consumption at 400 kHz
Block current consumption at 1 Mbps
60
185
390
1.4
µA
µA
µA
µA
–
–
–
–
I2C1
I2C2
I2C3
I2C4
SID150
SID151
SID152
–
–
–
–
2
I C enabled in Deep Sleep mode
–
–
2
Table 11. Fixed I C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
Description
Min
Typ Max Units
Details/Conditions
F
Bit rate
–
–
1
Mbps
–
I2C1
Table 12. Fixed UART DC Specifications
(Guaranteed by Characterization)
Spec ID
SID160
SID161
Parameter
Description
Min
Typ
Max Units
Details/Conditions
Block current consumption at
100 Kb/s
I
I
–
–
125
312
µA
µA
–
UART1
Block current consumption at
1000 Kb/s
–
–
–
UART2
Table 13. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID
SID162
Parameter
Description
Min
Typ
Max Units
Details/Conditions
Bit rate
–
–
1
Mbps
–
F
UART
Table 14. Fixed SPI DC Specifications
(Guaranteed by Characterization)
Spec ID
SID163
Parameter
Description
Min
Typ
Max Units
Details/Conditions
I
I
I
Block current consumption at 1 Mb/s
Block current consumption at 4 Mb/s
Block current consumption at 8 Mb/s
–
–
–
–
–
–
360
560
600
µA
µA
µA
–
–
–
SPI1
SPI2
SPI3
SID164
SID165
Table 15. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID
SID166
Parameter
Description
Min
Typ
Max Units
MHz
Details/Conditions
SPI Operating frequency (Master; 6X
oversampling)
F
–
–
8
–
SPI
Table 16. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
SID167
Parameter
Description
Min
Typ
Max Units
Details/Conditions
T
MOSI Valid after SClock driving edge
–
–
15
ns
–
DMO
DSI
MISO Valid before SClock capturing
edge
Full clock, late MISO
sampling
SID168
SID169
T
T
20
0
–
–
–
ns
Referred to slave capturing
edge
Previous MOSI data hold time
–
ns
HMO
Document Number: 002-03288 Rev. *J
Page 27 of 45
EZ-PD™ CCG3
Table 17. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
SID170
Parameter
Description
Min
40
–
Typ
–
Max
Units Details/Conditions
MOSI Valid before Sclock capturing
edge
T
–
42 + 3 × T
48
ns
ns
ns
–
DMI
SID171
T
T
MISO Valid after Sclock driving edge
–
T
= 1/F
CPU CPU
DSO
CPU
MISO Valid after Sclock driving edge
in Ext Clk mode
SID171A
–
–
–
DSO_EXT
SID172
T
T
Previous MISO data hold time
0
–
–
–
–
ns
ns
–
–
HSO
SID172A
SSEL Valid to first SCK Valid edge
100
SSELSCK
System Resources
Power-on-Reset (POR) with Brown Out SWD Interface
Table 18. Imprecise Power On Reset (PRES) (Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
0.80
0.70
Typ
–
Max Units
Details/Conditions
Power-on Reset (POR) rising trip
voltage
SID185
SID186
V
1.50
1.4
V
V
–
–
RISEIPOR
FALLIPOR
V
POR falling trip voltage
–
Table 19. Precise Power On Reset (POR) (Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
–
Max Units
Details/Conditions
Brown-out Detect (BOD) trip voltage
in active/sleep modes
SID190
SID192
V
1.48
1.62
1.5
V
V
–
–
FALLPPOR
FALLDPSLP
V
BOD trip voltage in Deep Sleep mode 1.1
–
Table 20. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SWDCLK 1/3 CPU clock
SID.SWD#1
F_SWDCLK1
3.3 V VDDIO 5.5 V
–
–
–
–
–
–
–
14
7
MHz
MHz
ns
frequency
SWDCLK 1/3 CPU clock
frequency
SID.SWD#2
SID.SWD#3
SID.SWD#4
SID.SWD#5
SID.SWD#6
F_SWDCLK2
1.8 V VDDIO 3.3 V
–
Guaranteed by
characterization
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
0.25 × T
–
Guaranteed by
characterization
0.25 × T
–
ns
Guaranteed by
characterization
–
1
0.50 × T ns
ns
Guaranteed by
characterization
–
Document Number: 002-03288 Rev. *J
Page 28 of 45
EZ-PD™ CCG3
Internal Main Oscillator
Table 21. IMO DC Specifications
(Guaranteed by Design)
Spec ID
SID218
Parameter
Description
Min
Typ
Max Units
1000 µA
Details/Conditions
I
IMO operating current at 48 MHz
–
–
–
IMO1
Table 22. IMO AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max Units
Details/Conditions
Frequency variation at 24, 36, and
48 MHz (trimmed)
SID.CLK#13
F
–
–
±2
7
%
µs
ps
–25 °C T 85 °C, all VDDD
IMOTOL
A
Guaranteed by
characterization
SID226
T
IMO start-up time
–
–
STARTIMO
Guaranteed by
characterization
SID229
T
F
RMS jitter at 24 MHz
IMO frequency
–
145
–
–
JITRMSIMO2
SID.CLK#1
24
48
MHz All VDDD
IMO
Internal Low-Speed OscillatorPower Down
Table 23. ILO DC Specifications
(Guaranteed by Design)
Spec ID
SID231
SID233
Parameter
Description
operating current
Min
–
Typ
0.3
2
Max Units
Details/Conditions
I
I
I
I
1.05
15
µA
nA
–
–
ILO1
LO
leakage current
–
ILOLEAK
LO
Table 24. ILO AC Specifications
Spec ID Parameter
Description
Min
Typ
Max Units
Details/Conditions
Guaranteed by
characterization
SID234
T
I
start-up time
–
–
2
ms
STARTILO1
LO
Guaranteed by
characterization
SID238
T
F
I
I
duty cycle
frequency
40
20
50
40
60
80
%
ILODUTY
LO
SID.CLK#5
kHz
–
ILO
LO
Table 25. PD DC Specifications
Spec ID Parameter
Description
Min
Typ
Max Units
Details/Conditions
DFP CC termination for default USB
Power
SID.PD.1
R _std
64
80
96
µA
–
P
SID.PD.2
SID.PD.3
SID.PD.4
R _1.5A
DFP CC termination for 1.5A power
DFP CC termination for 3.0A power
UFP CC termination
166
304
4.59
180 194.4
330 356.4
µA
µA
kΩ
–
–
–
P
R _3.0A
P
R
5.1
5.61
D
UFP Dead Battery CC
termination on CC1 and CC2.
UFP Dead Battery CC termination on
SID.PD.5
R _DB
CC1 and CC2, valid for 1.5Aand 3.0A 4.08
5.1
6.12
kΩ For Default R termination,
D
P
R termination values
the voltage on CC1 and CC2
is guaranteed to be <1.32 V.
P
All supplies forced to 0 V and
kΩ
SID.PD.6
SID.PD.7
R
EMCA cable termination
0.8
0.4
1.0
1.2
–
A
0.2 V applied at VCONN.
2.7 V applied at VCONN with
MΩ
R _OFF
EMCA cable termination - Disabled
0.75
A
R disabled.
A
Document Number: 002-03288 Rev. *J
Page 29 of 45
EZ-PD™ CCG3
Table 25. PD DC Specifications (continued)
Spec ID
SID.PD.8
Parameter
Description
Min
–
Typ
–
Max Units
Details/Conditions
R
VCONN leaker for 0.1-µF load
VCONN leaker for 0.5-µF load
VCONN leaker for 1.0-µF load
VCONN leaker for 2.0-µF load
VCONN leaker for 5.0-µF load
VCONN leaker for 10-µF load
216
43.2
21.6
10.8
4.32
2.16
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
leak_1
leak_2
leak_3
leak_4
leak_5
leak_6
SID.PD.9
R
R
R
R
R
–
–
SID.PD.10
SID.PD.11
SID.PD.12
SID.PD.13
–
–
ManagedActive Cable (MAC)
discharge.
–
–
–
–
–
–
Leaker on VCONN for discharge
upon cable detach
SID.PD.14
I
150
–
550
µA
–
leak
Relative to the remote BMC
mV transmitter. Guaranteed by
characterization.
Ground offset tolerated by BMC
receiver
SID.PD.15
V
–400
–
400
gndoffset
Table 26. CSA Specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/Conditions
Overall Error atAv = 15 using deep sleep
reference
Guaranteed by
characterization.
SID.CSA.1
Out_E_Trim_15_DS
Out_E_Trim_15_BG
Out_E_Trim_100
–7.00
–4.50
–
–
–
7.00
4.50
%
%
%
Overall Error at Av = 15 using bandgap
reference
Guaranteed by
characterization.
SID.CSA.2
SID.CSA.3
Overall Error at Av = 100 using either
bandgap or deep sleep reference
–24.50
24.50
–
Table 27. UV/OV Specifications
Spec ID
Parameter
Description
Min
Typ
Max Units
Details/Conditions
Voltage threshold Accuracy,
Tested at VBUS = 3.75 V,
4.5 V, 5.25 V, 12 V, 16 V
SID.UVOV.1
V
–6
6
%
%
THUVOV1
V
16 V
BUS
Voltage threshold Accuracy,
16 V
SID.UVOV.2
V
–10
10
Tested at VBUS = 20 V
THUVOV2
V
BUS
Gate Driver Specifications
Table 28. Gate Driver DC Specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
1. Gate driver Supply Voltage 5V, where
Gate driver supply voltage = VBUS _P for
VBUS_P_CTRL_ outputs, and VBUS_C
for VBUS_C_CTRL_ outputs.
Gate to Source
Overdrive
DC.NGDO.1
VGS1
5
–
16.5
V
2. Gate driver current = 0
3. Gate driver configuration = NFET
4. Gate driver pump clock divider = 1
1. Gate driver Supply Voltage 3.75V, where
Gate driver supply voltage = VBUS _P for
VBUS_P_CTRL_ outputs, and VBUS_C
for VBUS_C_CTRL_ outputs.
Gate to Source
Overdrive
DC.NGDO.2
DC.NGDO.6
VGS2
3.75
–
–
–
16.5
5
V
2. Gate driver current = 0
3. Gate driver configuration = NFET
4. Gate driver pump clock divider = 1
Resistance when “pull
down” enabled
R
kΩ
–
PD
Document Number: 002-03288 Rev. *J
Page 30 of 45
EZ-PD™ CCG3
Table 29. Gate Driver AC Specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
1. Gate driver configuration =
NFET
Gate turn-on time to gate_driver_sup-
ply_voltage + 5V for supply voltage
5V and VBUS * 2 for supply voltage <
5V
AC.NGDO.1
T
–
–
1
ms
ON
2. Load = The gate of a SI9936
MOSFET
SBU
Table 30. Analog Crossbar Switch Specifications
Spec ID Parameter Description
Min Typ Max
Units
Details/Conditions
Voltage input from 0 V
to 3.6 V
SID.SBU.1 Ron_sw
Switch ON Resistance
–
–
10
Ω
SID.SBU.2 Rpu_aux_1
SID.SBU.3 Rpu_aux_2
SID.SBU.4 Rpd_aux_1
SID.SBU.5 Rpd_aux_2
SID.SBU.6 Rpd_aux_3
SID.SBU.7 Rpd_aux_4
AUX_P/N Pull-up Resistance – 100k
AUX_P/N Pull-up Resistance – 1M
AUX_P/N Pull-down Resistance – 100k
AUX_P/N Pull-down Resistance – 1M
80
0.8
80
–
–
–
–
–
–
120
1.2
kΩ
MΩ
kΩ
–
–
–
–
–
–
120
1.2
0.8
MΩ
kΩ
AUX_P/N Pull-down Resistance – 470k 329
AUX_P/N Pull-down Resistance – 4.7M 3.29
611
6.11
MΩ
Charger Detect
Table 31. Charger Detect Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.CD.1
VDAT_REF
BC1.2 Data Detect Voltage Threshold
250
–
400
mV
–
With current sink of
25 µA–175 µA
SID.CD.2
SID.CD.3
VDM_SRC
VDP_SRC
BC1.2 DM Voltage Source
BC1.2 DP Voltage Source
500
500
–
–
700
700
mV
mV
With current sink of
25 µA–175 µA
SID.CD.4
SID.CD.5
SID.CD.6
SID.CD.7
SID.CD.8
SID.CD.9
IDM_SINK
IDP_SINK
IDP_SRC
RDP_UP
BC1.2 DM Current Sink
25
25
–
–
–
–
–
–
–
175
175
µA
µA
µA
kΩ
kΩ
kΩ
kΩ
–
–
–
–
–
–
–
BC1.2 DP Current Sink
BC1.2 DP DCD Current Source
USB FS DP Pull-up Termination
USB FS DM Pull-up Termination
USB FS DP Pull-down Termination
USB FS DM Pull-down Termination
7
13
0.9
1.575
1.575
24.8
24.8
RDM_UP
RDP_DWN
0.9
14.25
14.25
SID.CD.10 RDM_DWN
Thechargerdetectfunction
and data line leakage is
enabled.
SID.CD.11 RDAT_LKG
DP/DM Data Line Leakage Termination 300
–
500
kΩ
BC1.2 DCP Port Resistance between
DP and DM
SID.CD.12 RDCP_DAT
SID.CD.13 VSETH
–
–
–
40
Ω
V
–
–
USB FS Logic Threshold
1.26
1.54
Document Number: 002-03288 Rev. *J
Page 31 of 45
EZ-PD™ CCG3
Analog to Digital Converter
Table 32. ADC DC Specifications (Guaranteed by Characterization)
Spec ID
SID.ADC.1
SID.ADC.2
SID.ADC.3
SID.ADC.4
Parameter
Resolution
INL
Description
ADC resolution
Min
–
Typ
8
Max
–
Units
Bits
Details/Conditions
–
–
–
–
Integral non-linearity
Differential non-linearity
Gain error
–1.5
–2.5
–1
–
1.5
2.5
1
LSB
LSB
LSB
DNL
–
Gain Error
–
Table 33. ADC AC Specifications (Guaranteed by Design)
Spec ID
Parameter
Description
Min
Typ Max Units
V/ms
Details/Conditions
Rate of change of sampled voltage
signal
SID.ADC.5
SLEW_Max
–
–
3
–
Table 34. VBUS_C Regulator DC Specifications
Spec ID
Parameter
Description
Min
Typ Max Units
Details/Conditions
VBUS regulator output voltage
measured at VDDD for
VBUS = 4.5 V to 21.5 V
VBUS = 4.5 V - 21.5 V range.
VDDD voltage measured with no
load and a load of 30 mA.
SID.20vreg.1 VBUSREG
SID.20vreg.2 VBUSREG2
SID.20vreg.6 VBUSLINREG
3
–
–
–
3.6
3.6
0.5
V
V
VBUS regulator output voltage
measured at VDDD for
VBUS = 3.5 V to 21.5 V
VBUS = 4.5 V - 21.5 V range.
VDDD voltage measured with no
load and a load of 15 mA.
3
–
VBUS supply varied from 4.5 V to
21.5VandthechangeintheVDDD
measured.
VBUS regulator line regulation
for VBUS from 4.5 V to 21.5 V
%/V
Guaranteed by Characterization.
Supply of 4.5 V - 21.5 V applied on
VBUS and the load current swept
0.2 %/mA from 0 to 30 mA. The change in
VDDD is measured.
VBUS regulator load regulation
for VBUS from 4.5 V to 21.5 V
SID.20vreg.8 VBUSLOADREG
–
–
Guaranteed by Characterization.
Table 35. VBUS_C Regulator AC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
Apply VBUS and measure start time on
VDDD pin.
AC.20vreg.1 T
Regulator Start-up time
–
–
120
µs
START
Time from assertion of an internal disable
µs signal to for load current on VDDD to
decrease from 30 mA to 10 µA.
AC.20vreg.2 T
Regulator power down time
–
–
1
STOP
Table 36. VSYS Switch Specification
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
Resistance from VSYS supply
input to the output supply
VDDD
Measured with a load current of 5 mA- 10 mA
on VDDD.
SID.vddsw.1 Res_sw
–
–
1.5
Ω
Document Number: 002-03288 Rev. *J
Page 32 of 45
EZ-PD™ CCG3
Memory
Table 37. Flash AC Specifications
Spec ID
Parameter
Description
Row erase time
Min Typ Max Units
Details/Conditions
SID.MEM#3 FLASH_ERASE
–
–
15.5
ms
–
Row (Block) write time (erase
and program)
SID.MEM#4 FLASH_WRITE
–
–
20
ms
–
SID.MEM#8 FLASH_ROW_PGM Row program time after erase
–
–
–
–
–
–
7
ms
ms
s
–
SID178
SID180
TBULKERASE
TDEVPROG
Bulk erase time (64k Bytes)
Total device program time
35
7.5
–
Guaranteed by characterization
Flash retention, T ≤ 55 °C,
100 K P/E cycles
A
SID182
FRET1
FRET2
FRET3
20
10
3
–
–
–
–
–
–
years Guaranteed by characterization
years Guaranteed by characterization
years Guaranteed by characterization
Flash retention, T ≤ 85 °C,
A
SID182A
SID182B
10 K P/E cycles
Flash retention, T ≤ 105 °C,
A
10 K P/E cycles
Document Number: 002-03288 Rev. *J
Page 33 of 45
EZ-PD™ CCG3
Ordering Information
Table 38 lists the EZ-PD CCG3 part numbers and features.
Table 38. EZ-PD CCG3 Ordering Information
Part Number
Application
Termination Resistor
Role
Default FW
Package
Si ID
CYPD3120-40LQXIT
CYPD3120-40LQXI
CYPD3121-40LQXIT
CYPD3121-40LQXI
CYPD3122-40LQXIT
CYPD3122-40LQXI
CYPD3123-40LQXIT
CYPD3123-40LQXI
CYPD3125-40LQXIT
CYPD3125-40LQXI
CYPD3126-42FNXIT DRP
CYPD3135-32LQXQT
USB Bootloader
and Application FW
[4]
Dongle
R , R , R
UFP
40-QFN
1D00
P
D
D_DB
[5]
[6]
Power Banks
R
, R , R
DRP
DFP
DRP
USB Bootloader
40-QFN
40-QFN
40-QFN
1D02
1D03
1D09
P
D
D_DB
2
Monitor (DFP)
R , R , R
D_DB
I C Bootloader
P
D
USB Bootloader
and Application FW
Charge-through Dongle
R , R , R
P D
D_DB
2
Notebooks, Smartphones R , R , R
DRP
DRP
DFP
I C Bootloader
40-QFN
42-CSP
32-QFN
1D04
1D07
1D08
P
D
D_DB
[4]
2
R , R , R
D_DB
I C Bootloader
P
D
CC Bootloader and
Power Adapter
R
R
R
[7]
P
Application FW
CYPD3135-32LQXQ
CYPD3135-40LQXIT
CYPD3135-40LQXI
CYPD3135-40LQXQT
CYPD3135-40LQXQ
CC Bootloader and
Power Adapter
Power Adapter
DFP
DFP
40-QFN
40-QFN
1D05
1D05
[7]
P
P
Application FW
CC Bootloader and
[7]
Application FW
Ordering Code Definitions
-
XX
XX XX
X X X
X
CY PD
X
T = Tape and Reel
Temperature Grade:
I = Industrial (–40 °C - 85 °C), Q = Extended industrial (–40 °C - 105 °C)
Lead: X = Pb-free
Package Type: FN = CSP; LQ = QFN
Number of pins in the package
Application and Feature Combination Designation
Number of Type-C Ports: 1 = 1 Port, 2 = 2 Port
Product Type: 3 = Third-generation product family, CCG3
Marketing Code: PD = Power Delivery product family
Company ID: CY = Cypress
Notes
3. Termination resistor denoting an EMCA.
4. Termination resistor denoting an upstream facing port.
5. Termination resistor denoting a downstream facing port.
6. Termination resistor denoting dead battery termination.
7. The CYPD3135 parts are shipped with bootloader and application firmware with limited functionality. Its purpose is to facilitate application flashing over CC line using
the EZ-PD Configuration Utility. The power adapter requires an explicit power contract to be negotiated prior to enabling the EZ-PD Configuration utility to flash the
application firmware. This application firmware, based on the state of the GPIO (P1.0), determines the type of provider load switch (NFET/PFET) and supplies the
5V VBUS over Type-C.
Document Number: 002-03288 Rev. *J
Page 34 of 45
EZ-PD™ CCG3
Packaging
Table 39. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
85
Units
°C
Industrial
T
T
Operating ambient temperature
Operating junction temperature
–40
25
A
Extended Industrial
105
100
125
17
°C
Industrial
°C
–40
25
J
Extended Industrial
°C
T
T
T
T
T
T
Package (40-pin QFN)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JA
JC
JA
JC
JA
JC
JA
Package (40-pin QFN)
2
JC
Package (42-ball WLCSP)
34
JA
Package (42-ball WLCSP)
0.3
18
JC
Package (32-pin QFN)
JA
Package (32-pin QFN)
4
JC
Table 40. Solder Reflow Peak Temperature
Package
Maximum Time within 5 °C of Peak
Temperature
Maximum Peak Temperature
40-pin QFN
260 °C
260 °C
260 °C
30 seconds
30 seconds
30 seconds
42-ball WLCSP
32-pin QFN
Table 41. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
42-ball WLCSP
MSL
MSL 1
MSL 3
MSL 3
40-pin QFN
32-pin QFN
Document Number: 002-03288 Rev. *J
Page 35 of 45
EZ-PD™ CCG3
Figure 17. 40-pin QFN Package Outline, 001-80659
001-80659 *A
Figure 18. 42-ball CSP Package Outline, 002-04062
002-04062 *A
Document Number: 002-03288 Rev. *J
Page 36 of 45
EZ-PD™ CCG3
Figure 19. 32-pin QFN Package Outline, 001-42168
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1.
DIMENSIONS
MIN. NOM. MAX.
HATCH AREA IS SOLDERABLE EXPOSED PAD
SYMBOL
2. BASED ON REF JEDEC # MO-248
3. PACKAGE WEIGHT: 0.0388g
A
A1
A2
D
0.50
-
0.55
0.60
4. DIMENSIONS ARE IN MILLIMETERS
0.020 0.045
0.15 BSC
4.90
3.40
4.90
3.40
0.30
0.18
5.00
3.50
5.10
3.60
5.10
3.60
0.50
0.30
D2
E
5.00
E2
L
3.50
0.40
001-42168 *F
0.25
b
e
0.50 TYP
Document Number: 002-03288 Rev. *J
Page 37 of 45
EZ-PD™ CCG3
Table 42. Acronyms Used in this Document (continued)
Acronyms
Acronym
opamp
OCP
Description
operational amplifier
Table 42. Acronyms Used in this Document
Acronym
ADC
Description
analog-to-digital converter
overcurrent protection
overvoltage protection
printed circuit board
OVP
AES
advanced encryption standard
PCB
AMBA(advancedmicrocontroller bus architecture)
high-performance bus
AHB
PD
power delivery
PGA
programmable gain amplifier
physical layer
API
application programming interface
advanced RISC machine, a CPU architecture
Biphase Mark Code
®
PHY
ARM
POR
power-on reset
BMC
CC
PRES
precise power-on reset
Programmable System-on-Chip™
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
configuration channel
®
PSoC
CCG3
CPU
Cable Controller Generation 3
central processing unit
PWM
RAM
RISC
RMS
RTC
RX
cyclic redundancy check, an error-checking
protocol
CRC
CS
current sense
DFP
downstream facing port
real-time clock
digital input/output, GPIO with only digital capabil-
ities, no analog. See GPIO.
receive
DIO
SAR
SCB
SCL
SDA
S/H
successive approximation register
serial communication block
DRP
dual role port
electrically erasable programmable read-only
memory
2
EEPROM
I C serial clock
2
I C serial data
electronicallymarkedcableassembly, aUSBcable
that includes an IC that reports cable
characteristics (e.g., current rating) to the Type-C
ports
sample and hold
EMCA
SHA
secure hash algorithm
Serial Peripheral Interface, a communications
protocol
SPI
EMI
ESD
FS
electromagnetic interference
electrostatic discharge
full-speed
SRAM
SWD
static random access memory
serial wire debug, a test protocol
timer/counter pulse-width modulator
GPIO
HPD
IC
general-purpose input/output
hot plug detect
TCPWM
Thunder-
bolt
TX
Trademark of Intel
transmit
integrated circuit
IDE
integrated development environment
2
I C, or IIC Inter-Integrated Circuit, a communications protocol
a new standard with a slimmer USB connector and
a reversible cable, capable of sourcing up to 100 W
of power
Type-C
ILO
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
input/output subsystem
IMO
IOSS
I/O
Universal Asynchronous Transmitter Receiver, a
communications protocol
UART
input/output, see also GPIO
low-dropout regulator
USB
Universal Serial Bus
USB Power Delivery
USB Full-Speed
LDO
LVD
USB PD
USB-FS
low-voltage detect
LVTTL
MCU
MMIO
NC
low-voltage transistor-transistor logic
microcontroller unit
USB input/output, CCG2 pins used to connect to a
USB port
USBIO
USBPD SS USB PD subsystem
memory mapped input/output
no connect
VDM
vendor defined messages
external reset I/O pin
XRES
NMI
nonmaskable interrupt
NVIC
nested vectored interrupt controller
Document Number: 002-03288 Rev. *J
Page 38 of 45
EZ-PD™ CCG3
Document Conventions
Units of Measure
Table 43. Units of Measure
Symbol
°C
Unit of Measure
degrees Celsius
hertz
Hz
KB
kHz
k
Mbps
MHz
M
Msps
µA
1024 bytes
kilohertz
kilo ohm
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
microsecond
microvolt
µF
µs
µV
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
ohm
ns
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
sps
V
samples per second
volt
Document Number: 002-03288 Rev. *J
Page 39 of 45
EZ-PD™ CCG3
References and Links to Applications Collaterals
Knowledge Base Articles
■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and
CCG4 - KBA210740
■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™
CCG2
■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™
■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
CCG4 Using PSoC® Programmer and MiniProg3 - KBA96477
■ AN210403 - Hardware Design Guidelines for Dual Role Port
■ CCGX Frequently Asked Questions (FAQs) - KBA97244
■ Handling Precautions for CY4501 CCG1 DVK - KBA210560
■ Cypress EZ-PD™ CCGx Hardware - KBA204102
■ Difference between USB Type-C and USB-PD - KBA204033
■ CCGx Programming Methods - KBA97271
Applications Using EZ-PD™ USB Type-C Controllers
■ AN210771 - Getting Started with EZ-PD™ CCG4
Reference Designs
■ EZ-PD™ CCG2 Electronically Marked Cable Assembly
(EMCA) Paddle Card Reference Design
■ Getting started with Cypress USB Type-C Products -
KBA04071
■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution
■ CCG1 USB Type-C to DisplayPort Cable Solution
■ Type-C to DisplayPort Cable Electrical Requirements
■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution
■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution
■ Dead Battery Charging Implementation in USB Type-C
Solutions - KBA97273
■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle
Card Reference Design
■ TerminationResistorsRequiredfortheUSBType-CConnector
– KBA97180
■ VBUS Bypass Capacitor Recommendation for Type-C Cable
and Type-C to Legacy Cable/AdapterAssemblies – KBA97270
■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card
Reference Schematics
■ Need for Regulator and Auxiliary Switch in Type-C to
DisplayPort (DP) Cable Solution - KBA97274
■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle
■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution
■ CCG2 20W Power Adapter Reference Design
■ CCG2 18W Power Adapter Reference Design
■ Need for a USB Billboard Device in Type-C Solutions –
KBA97146
■ CCG1DevicesinType-CtoLegacy Cable/AdapterAssemblies
– KBA97145
■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference
■ Cypress USB Type-C Controller Supported Solutions –
Design Kit
KBA97179
Kits
■ Termination Resistors for Type-C to Legacy Ports – KBA97272
■ CY4501 CCG1 Development Kit
■ CY4502 EZ-PD™ CCG2 Development Kit
■ CY4531 EZ-PD CCG3 Evaluation Kit
■ CY4541 EZ-PD™ CCG4 Evaluation Kit
■ Handling Instructions for CY4502 CCG2 Development Kit –
KBA97916
■ Thunderbolt™ Cable Application Using CCG3 Devices -
KBA210976
■ Power AdapterApplication Using CCG3 Devices - KBA210975
■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974
■ Device Flash Memory Size and Advantages - KBA210973
■ Applications of EZ-PD™ CCG4 - KBA210739
Application Notes
Datasheets
■ CCG1 Datasheet: USB Type-C Port Controller with Power
Delivery
■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode
Controller on Type-C
■ AN96527 - Designing USB Type-C Products Using Cypress’s
CCG1 Controllers
■ CCG2: USB Type-C Port Controller Datasheet
■ CCG4: Two-Port USB Type-C Controller Datasheet
Document Number: 002-03288 Rev. *J
Page 40 of 45
EZ-PD™ CCG3
Document History Page
Document Title: EZ-PD™ CCG3 USB Type-C Port Controller
Document Number: 002-03288
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
4905678
VGT
09/11/2015 New data sheet.
Updated General Description:
Updated the number of GPIOs to 20.
Updated Functional Overview:
Updated GPIO:
*A
4953333
VGT
10/08/2015 Updated the number of GPIOs to 20.
Updated Pinouts:
Updated Table 2.
Updated Figure 4.
Added Figure 6.
Changed status from Advance to Preliminary.
Updated Features.
Added EZ-PD CCG3 Block Diagram.
Updated Functional Overview:
Updated USB-PD Subsystem (USBPD SS) (Updated description).
Added Full-Speed USB Subsystem.
Updated Pinouts:
Updated Table 2.
Updated Figure 4.
Updated Figure 6.
Added Applications.
Updated Electrical Specifications:
Updated Absolute Maximum Ratings:
Updated Table 3.
Updated Device-Level Specifications:
Updated Table 4.
*B
5007726
VGT
11/25/2015 Updated Table 5.
Updated I/O:
Updated Table 6.
Updated XRES:
Updated Table 8.
Updated System Resources:
Updated Power-on-Reset (POR) with Brown Out SWD Interface:
Updated Table 18.
Updated Table 19.
Updated Table 20.
Updated Internal Main Oscillator:
Updated Table 22.
Updated Internal Low-Speed OscillatorPower Down:
Updated Table 23.
Updated Table 24.
Updated Internal Low-Speed OscillatorPower Down:
Updated Table 25.
Document Number: 002-03288 Rev. *J
Page 41 of 45
EZ-PD™ CCG3
Document History Page (continued)
Document Title: EZ-PD™ CCG3 USB Type-C Port Controller
Document Number: 002-03288
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Updated Analog to Digital Converter:
Updated Table 32.
*B (cont.)
5007726
VGT
11/25/2015 Updated Table 33.
Updated Packaging:
Added Figure 18 (spec 002-04062 *A).
Updated General Description.
Updated Features.
Updated Logic Block Diagram.
Updated Power Systems Overview.
Updated Pinouts:
Updated Table 2.
Added table “CCG3 Pin Description for 16-SOIC Device”.
Added figure “Pinout of 16-SOIC Package (Top View)”.
*C
5080470
VGT
01/11/2016 Updated Applications:
Updated Figure .
Updated Figure 11.
Updated figure “Power Adapter Application Diagram (16-SOIC Device)”.
Updated Figure 15.
Updated Ordering Information.
Updated Packaging:
Added spec 51-85022 *E.
Added Errata.
Updated Pinouts:
Updated table “CCG3 Pin Description for 16-SOIC Device”.
Updated figure “Pinout of 16-SOIC Package (Top View)”.
Updated Applications:
*D
5137796
VGT
03/09/2016 Updated Figure 11.
Updated Figure 12.
Updated Ordering Information
Updated Errata.
Updated to new template.
Updated General Description:
Updated description.
Updated Features:
Updated Type-C and USB-PD Support:
Updated description.
Updated Packages:
Updated description.
*E
5240836
VGT
04/28/2016
Updated Logic Block Diagram.
Updated Functional Overview:
Updated Integrated Billboard Device:
Updated description.
Updated USB-PD Subsystem (USBPD SS):
Updated description.
Added Figure 2 and Figure 5.
Document Number: 002-03288 Rev. *J
Page 42 of 45
EZ-PD™ CCG3
Document History Page (continued)
Document Title: EZ-PD™ CCG3 USB Type-C Port Controller
Document Number: 002-03288
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Updated Power Systems Overview: Updated description.
Updated Figure 3.
Updated Pinouts:
Updated Table 2:
Updated details in “Description” column corresponding to VDDIO pin.
Removed table “CCG3 Pin Description for 16-SOIC Device”.
Removed figure “Pinout of 16-SOIC Package (Top View)”.
Updated Applications: Removed figure “Power Adapter Application Diagram
(16-SOIC Device)”.
Added Figure 12.
Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated Table 4.
Updated details in “Details/Conditions” column corresponding to
“SID.PWR#1_A” Spec ID and “V
” parameter.
SYS
Replaced “V
” with “5.5” in “Max” column corresponding to “SID.PWR#13”
DDIO
DDD
*E (cont.)
5240836
VGT
04/28/2016
Spec ID and “V
” parameter.
Added “SID.PWR#13_A” Spec ID corresponding to “V
details.
” parameter and its
DDIO
Added “SID.PWR#1_C” and “SID.PWR#1_D” Spec IDs corresponding to
“V ” parameter and its details.
SYS
Replaced “enabled” with “disabled” in “Details/Conditions” column
corresponding to “SID.PwR#28” Spec ID and “V ” parameter.
BUS
Updated details in “Description” and “Details/Conditions” columns
corresponding to “SID307” Spec ID and “I
Updated System Resources:
” parameter.
DD_XR
Added Gate Driver Specifications, Charger Detect.
Updated Ordering Information: Updated part numbers.
Updated details in “Application” column corresponding to part number
“CYPD3121-40LQXIT”.
Updated Ordering Code Definitions
Updated Packaging: Removed spec 51-85022 *E.
Removed Errata.
Added Available Firmware and Software Tools, CCG3 Programming and
Bootloading, and References and Links to Applications Collaterals.
Added descriptive notes for the application diagrams.
Updated Features, Applications and Timer/Counter/PWM Block (TCPWM).
Updated Table 2 through Table 6, Table 18, Table 19, Table 22, Table 23,
Table 25, and Table 31 through Table 38.
Updated Figure 7, Figure 8, Figure , Figure 11, and Figure 19 (package
diagram spec 001-42168 *E).
*F
5342389
VGT
07/28/2016
Added Figure 5, Figure 13, and Figure 14.
Added Table 26, Table 27, Table 37, and Table 39 through Table 41.
Added VDM in Acronyms.
Updated Cypress logo and copyright information.
Added Table 34 through Table 36.
Updated Table 3, Table 4, Table 6, and Table 37.
Updated Copyright and Disclaimer.
*G
5449433
VGT
09/26/2016
Added Compliance information in Sales, Solutions, and Legal Information.
Document Number: 002-03288 Rev. *J
Page 43 of 45
EZ-PD™ CCG3
Document History Page (continued)
Document Title: EZ-PD™ CCG3 USB Type-C Port Controller
Document Number: 002-03288
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Removed Preliminary document status.
Updated Sales information and Copyright details.
Added Gate Driver Specifications in Table 28 and Table 29.
Updated Applications.
Added Figure 16.
*H
5514508
VGT
01/13/2017
Updated Ordering Information:
Added “CYPD3123-40LQXIT” part number.
Removed “CYPD3105-42FNXIT” part number.
Updated Table 2, added non Tape and Reel part numbers and Note 7 in
Table 38, Updated description prior to Figure 11.
*I
5662219
6032274
VGT
VGT
03/29/2017
2/21/2018
Updated description of V5V pin in Table 2.
Removed parameter SID.PWR#13_A from Table 4.
Updated description in USB-PD Subsystem (USBPD SS).
Updated Packaging: 32-pin QFN Package Outline, 001-42168 (*E to *F).
*J
Document Number: 002-03288 Rev. *J
Page 44 of 45
EZ-PD™ CCG3
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
®
®
Arm Cortex Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB
Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify
the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely
responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any
modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you
had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT
NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.
© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-03288 Rev. *J
Revised February 23, 2018
Page 45 of 45
相关型号:
CYPD3135-40LQXIT
PG-VQFN-40 tape and reel packing PD controller with industry temperature grade for source application
INFINEON
CYPD3135-40LQXQ
PG-VQFN-40 tray packing PD controller with Q temperature grade for source application
INFINEON
CYPD3135-40LQXQT
PG-VQFN-40 tape and reel packing PD controller with Q temperature grade for source application
INFINEON
CYPD3171-24LQXQ
PG-VQFN-24 tray packing PD controller with PFET gate driver and dual-role port with direct-feedback and programmable
INFINEON
CYPD3171-24LQXQT
PG-VQFN-24 tape and reel packing PD controller with PFET gate driver and dual-role port with direct-feedback and programmable
INFINEON
CYPD3172-24LQXQ
PG-VQFN-24 tray packing PD controller with NFET gate driver with optocoupler-feedback and fixed functions for USB PD charger and adapters
INFINEON
CYPD3172-24LQXQT
PG-VQFN-24 tape and reel packing PD controller with NFET gate driver with optocoupler-feedback and fixed functions for USB PD charger and adapters
INFINEON
CYPD3172P-24LQXQ
PG-VQFN-24 tray packing PD controller with NFET gate driver with optocoupler-feedback and programmable for USB PD charger and adapters
INFINEON
©2020 ICPDF网 联系我们和版权申明