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EZ-PD™ CCG2 Datasheet

USB Type-C Port Controller

General Description

EZ-PD™ CCG2 is a USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG2 provides a

complete USB Type-C and U1SB Power Delivery port control solution for passive cables, active cables, and powered accessories. It

can also be used in many upstream and downstream facing port applications. EZ-PD CCG2 uses Cypress’s proprietary M0S8

technology with a 32-bit, 48-MHz Arm^®Cortex^®-M0 processor with 32-KB flash and integrates a complete Type-C Transceiver

including the Type-C termination resistors R_P, R_Dand R_A.

Type-C Support

■ Integrated transceiver (baseband PHY)

Applications

■ USB Type-C EMCA cables

■ Integrated UFP (R_D), EMCA (R_A) termination resistors, and

■ USB Type-C powered accessories

current sources for DFP (R_P)

■ USB Type-C upstream facing ports

■ Supports one USB Type-C port

■ USB Type-C downstream facing ports

Low-Power Operation

■ 2.7-V to 5.5-V operation

Features

■ Two independent VCONN rails with integrated isolation

between the two

32-bit MCU Subsystem

■ 48-MHz ARM Cortex-M0 CPU

■ 32-KB Flash

■ Independent supply voltage pin for GPIO that allows 1.71-V to

5.5-V signaling on the I/Os

■ 4-KB SRAM

■ Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.0 mA

■ In-system reprogrammable

System-Level ESD on CC and VCONN Pins

■ ±8-kVContactDischargeand±15-kVAirGapDischargebased

on IEC61000-4-2 level 4C

Integrated Digital Blocks

■ Integrated timers and counters to meet response times

required by the USB-PD protocol

Packages

■ Run-time reconfigurable serial communication block (SCB)

with reconfigurable I²C, SPI, or UART functionality

■ 1.63 mm × 2.03 mm, 20-ball wafer-level CSP (WLCSP) with

0.4-mm ball pitch

Clocks and Oscillators

■ Integrated oscillator eliminating the need for external clock

■ 2.5 mm × 3.5 mm × 0.6 mm 14-pin DFN

■ 4.0 mm × 4.0 mm, 0.55 mm 24-pin QFN

■ Supports industrial (40 °C to +85 °C) and extended industrial

⁽40 °C to +105 °C) temperature ranges

Logic Block Diagram

CCG2: USB Type-C Cable Controller

MCU Subsystem

I/O Subsystem

CC⁵

Integrated Digital Blocks

TCPWM¹

VCONN1

SCB²

(I²C, SPI, UART)

CORTEX-M0

48 MHz

VCONN2

SCB²

(I²C, SPI, UART)

VDDIO

GPIO⁶

Port

Profiles and

Configurations

Flash

(32 KB)

Baseband MAC

Baseband PHY

4

SRAM

(4 KB)

Integrated R_d³, R_a

,

7

and R_p

Serial Wire Debug

¹Timer, counter, pulse-width modulation block

²Serial communication block configurable as UART, SPI, or I²C

³Termination resistor denoting a UFP

⁴Termination resistor denoting an EMCA

⁵Configuration Channel

⁶General-purpose input/output

7

Current Sources to indicate a DFP

Cypress Semiconductor Corporation

Document Number: 001-93912 Rev. *N

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 4, 2020

EZ-PD™ CCG2 Datasheet

Available Firmware and Software Tools

EZ-PD Configuration Utility

The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through

the process of configuring and programming the chip. The utility allows users to:

1. Select and configure the parameters they want to modify

2. Program the resulting configuration onto the target CCGx device.

The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB

interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers

implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port

controllers, will be provided in later versions of the utility.

You can download the EZ-PD Configuration Utility and its associated documentation at the following link:

http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility

Document Number: 001-93912 Rev. *N

Page 2 of 41

EZ-PD™ CCG2 Datasheet

Contents

EZ-PD CCG2 Block Diagram ............................................4

Functional Overview .........................................................4

CPU and Memory Subsystem .....................................4

USB-PD Subsystem (SS) ............................................5

System Resources .......................................................5

Peripherals ..................................................................6

GPIO ............................................................................6

Pinouts ...............................................................................7

Power .................................................................................9

CCG2 Programming and Bootloading ..........................10

Programming the CCG2 Device Flash

over SWD Interface ...........................................................10

Application Firmware Update (I2C, CC) ....................11

Application Diagrams .....................................................13

EMCA Applications ....................................................13

Upstream Facing Port Applications ...........................16

Downstream Facing Port Applications .......................18

C-HDMI Dongle Application .......................................19

C-DisplayPort Dongle Application ..............................20

Dock/Monitor Application ...........................................21

Electrical Specifications .................................................22

Absolute Maximum Ratings .......................................22

Device Level Specifications .......................................23

Digital Peripherals .....................................................25

Memory ......................................................................27

System Resources ....................................................28

Ordering Information ......................................................31

Ordering Code Definitions .........................................31

Packaging ........................................................................32

Acronyms ........................................................................35

Document Conventions .................................................36

Units of Measure .......................................................36

References and Links To Applications Collaterals .....37

Knowledge Base Articles ...........................................37

Application Notes .......................................................37

Reference Designs ....................................................37

Kits .............................................................................37

Datasheets ................................................................37

Document History Page .................................................38

Sales, Solutions, and Legal Information ......................41

Worldwide Sales and Design Support .......................41

Products ....................................................................41

PSoC®Solutions ........................................................41

Cypress Developer Community .................................41

Technical Support ......................................................41

Document Number: 001-93912 Rev. *N

Page 3 of 41

EZ-PD™ CCG2 Datasheet

EZ-PD CCG2 Block Diagram

Figure 1. EZ-PD CCG2 Block Diagram

CPU Subsystem

CCG2

SWD/TC

SPCIF

Cortex

M0

48 MHz

FAST MUL

FLASH

32 KB

SRAM

4 KB

SROM

8 KB

32-bit

AHB-Lite

Read Accelerator

SRAM Controller

SROM Controller

NVIC, IRQMX

System Resources

Lite

System Interconnect (Single Layer AHB)

Peripheral Interconnect (MMIO)

Power

Sleep Control

WIC

Peripherals

POR

REF

PCLK

PWRSYS

Clock

Clock Control

WDT

USB-PD SS

IMO

ILO

Reset

Reset Control

XRES

Test

DFT Logic

DFT Analog

Pads, ESD

Power Modes

Active/Sleep

Deep Sleep

High Speed I/O Matrix

12 x GPIOs, 2 x OVTs

I/O Subsystem

input, which is made available to the user when it is not in use

for system functions requested by the user.

Functional Overview

CPU and Memory Subsystem

The CPU also includes a serial wire debug (SWD) interface,

which is a 2-wire form of JTAG. The debug configuration used for

EZ-PD CCG2 has four break-point (address) comparators and

two watchpoint (data) comparators.

CPU

The Cortex-M0 CPU in EZ-PD CCG2 is part of the 32-bit MCU

subsystem, which is optimized for low-power operation with

extensive clock gating. It mostly uses 16-bit instructions and

executes a subset of the Thumb-2 instruction set. This enables

fully compatible binary upward migration of the code to higher

performance processors such as the Cortex-M3 and M4, thus

enabling upward compatibility. The Cypress implementation

includes a hardware multiplier that provides a 32-bit result in one

cycle. It includes a nested vectored interrupt controller (NVIC)

block with 32 interrupt inputs and also includes a Wakeup

Interrupt Controller (WIC). The WIC can wake the processor up

from the Deep Sleep mode, allowing power to be switched off to

the main processor when the chip is in the Deep Sleep mode.

The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)

Flash

The EZ-PD CCG2 device has a flash module with a flash

accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The flash block is designed to

deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS

access time at 24 MHz. The flash accelerator delivers 85% of

single-cycle SRAM access performance on average. Part of the

flash module can be used to emulate EEPROM operation if

required.

SROM

Asupervisory ROM that contains boot and configuration routines

is provided.

Document Number: 001-93912 Rev. *N

Page 4 of 41

EZ-PD™ CCG2 Datasheet

EZ-PD CCG2 USB-PD sub-system can be configured to

respond to SOP, SOP’, or SOP” messaging.

USB-PD Subsystem (SS)

EZ-PD CCG2 has a USB-PD subsystem consisting of a USB

Type-C baseband transceiver and physical-layer logic. This

transceiver performs the BMC and the 4b/5b encoding and

decoding functions as well as the 1.2-V front end. This

subsystem integrates the required termination resistors to

identify the role of the EZ-PD CCG2 solution. R_Ais used to

identify EZ-PD CCG2 as an accessory or an electronically

marked cable. R_Dis used to identify EZ-PD CCG2 as a UFP in

a hybrid cable or a dongle. When configured as a DFP, integrated

current sources perform the role of R_Por pull-up resistors. These

current sources can be programmed to indicate the complete

range of current capacity on VBUS defined in the Type-C spec.

EZ-PD CCG2 responds to all USB-PD communication. The

The USB-PD sub-system contains a 8-bit SAR (Successive

Approximation Register) ADC for analog to digital conversions.

The ADC includes a 8-bit DAC and a comparator. The DAC

output forms the positive input of the comparator. The negative

input of the comparator is from a 4-input multiplexer. The four

inputs of the multiplexer are a pair of global analog multiplex

busses an internal bandgap voltage and an internal voltage

proportional to the absolute temperature. All GPIO inputs can be

connected to the global Analog Multiplex Busses through a

switch at each GPIO that can enable that GPIO to be connected

to the mux bus for ADC use. The CC1, CC2 and RD1 pins are

not available to connect to the mux busses.

Figure 2. USB-PD Subsystem

To/From system Resources

vref

iref

VDDD

VCONN power logic

To/ from AHB

8-bit ADC

VDDD

Enable

Logic

From AMUX

Ra Enable

VConn1 detect

VConn2 detect

VCONN1

Ra

VCONN

Detect

VCONN2

TxRx Enable

8kV IEC ESD

Digital Baseband PHY

Analog Baseband PHY

Tx_data

Enable Logic

from AHB

Tx

SRAM

4b5b

Encoder

BMC

Encoder

SOP

Insert

Rp

TX

CC1

RD1

CC2

CRC

Rx_data

to AHB

RX

Rx

4b5b

SOP

BMC

SRAM

Decoder

Detect

Decoder

Ref

Comp

8kV IEC ESD

Active

Rd

DB

Rd

CC control

CC detect

Deep Sleep Reference Enable

Functional, Wakeup Interrupts

Deep Sleep

Vref & Iref Gen

vref, iref

Clock System

System Resources

Power System

The clock system for EZ-PD CCG2 consists of the Internal Main

Oscillator (IMO) and the Internal Low-power Oscillator (ILO).

The power system is described in detail in the section Power on

page 9. It provides assurance that voltage levels are as required

for each respective mode and either delay mode entry (on

power-on reset (POR), for example) until voltage levels are as

required for proper function or generate resets (Brown-Out

Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). EZ-PD

CCG2 can operate from three different power sources over the

range of 2.7 to 5.5 V and has three different power modes,

transitions between which are managed by the power system.

EZ-PD CCG2 provides Sleep and Deep Sleep low-power

modes.

Document Number: 001-93912 Rev. *N

Page 5 of 41

EZ-PD™ CCG2 Datasheet

Timer/Counter/PWM Block (TCPWM)

Peripherals

EZ-PD CCG2 has six TCPWM blocks. Each implements a 16-bit

timer, counter, pulse-width modulator (PWM), and quadrature

decoder functionality. The block can be used to measure the

period and pulse width of an input signal (timer), find the number

of times a particular event occurs (counter), generate PWM

signals, or decode quadrature signals.

Serial Communication Blocks (SCB)

EZ-PD CCG2 has two SCBs, which can be configured to

implement an I²C, SPI, or UART interface. The hardware I²C

blocks implement full multi-master and slave interfaces capable

of multimaster arbitration. In the SPI mode, the SCB blocks can

be configured to act as master or slave.

GPIO

In the I²C mode, the SCB blocks are capable of operating at

speeds of up to 1 Mbps (Fast Mode Plus) and have flexible

buffering options to reduce interrupt overhead and latency for the

CPU. These blocks also support I²C that creates a mailbox

address range in the memory of EZ-PD CCG2 and effectively

reduce I²C communication to reading from and writing to an

array in memory. In addition, the blocks support 8-deep FIFOs

for receive and transmit which, by increasing the time given for

the CPU to read data, greatly reduce the need for clock

stretching caused by the CPU not having read data on time.

The I²C peripherals are compatible with the I²C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus

I/Os are implemented with GPIO in open-drain modes.

EZ-PD CCG2 has up to 10 GPIOs in addition to the I²C and SWD

pins, which can also be used as GPIOs. The I²C pins from SCB

0 are overvoltage-tolerant. The number of available GPIOs vary

with the package. The GPIO block implements the following:

■ Seven drive strength modes:

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

The I²C port on SCB 1 block of EZ-PD CCG2 is not completely

■ Input threshold select (CMOS or LVTTL)

compliant with the I²C spec in the following respects:

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■ The GPIO cells for SCB 1's I²Cport arenot overvoltage-tolerant

and, therefore, cannot be hot-swapped or powered up

independently of the rest of the I²C system.

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode)

■ Fast-mode Plus has an I_OLspecification of 20 mA at a V_OLof

0.4 V. The GPIO cells can sink a maximum of 8-mA I_OLwith a

■ Selectable slew rates for dV/dt related noise control to improve

EMI

V_OLmaximum of 0.6 V.

During power-on and reset, the I/O pins are forced to the disable

state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed

I/O matrix is used to multiplex between various signals that may

connect to an I/O pin.

■ Fast-mode and Fast-mode Plus specify minimum Fall times,

which are not met with the GPIO cell; Slow strong mode can

help meet this spec depending on the bus load.

Document Number: 001-93912 Rev. *N

Page 6 of 41

EZ-PD™ CCG2 Datasheet

Pinouts

Table 1. Pinouts

Group

Pin Map Ball Location

Pin Map

14-DFN

Name

Description

24-QFN

20-CSP

USB Type-C

Port

CC1

2

B4

3

USB PD connector detect/Configuration Channel 1

CC2

RD1

1

3

A4

B3

N/A

USB PD connector detect/Configuration Channel 2

Dedicated Rd resistor pin for CC1

Must be left open for cable applications and connected

together with CC1 ball for UFP or DFP with dead battery

applications

GPIOs and

GPIO

22

C3

N/A

GPIO / SPI_0_CLK / UART_0_ RX

serial interfaces

GPIO

18

13

10

15

14

17

21

23

24

20

19

11

12

16

5

D3

C2

D2

B2

13

10

N/A

11

GPIO / SPI_0_MOSI / UART_0_TX

GPIO / I2C_1_SDA / SPI_1_MISO / UART_1_RX

GPIO / I2C_1_SCL / SPI_1_CLK / UART_1_TX

GPIO / SPI_1_SEL / UART_1_RTS

GPIO

N/A

A3

N/A

1

GPIO

I2C_0_SCL

I2C_0_SDA

SWD _IO

SWD_CLK

XRES

GPIO / I2C_0_SCL / SPI_0_MISO / UART_0_RTS

GPIO / I2C_0_SDA / SPI_0_SEL / UART_0_CTS

SWD IO / GPIO / UART_1_CTS / SPI_1_MOSI

SWD clock / GPIO

A2

14

8

E2

D1

B1

9

RESET

12

5

Reset input

POWER

VCONN1

VCONN2

VDDIO

VCCD

E4

VCONN 1 input (4.0 V to 5.5 V)

VCONN 2 input (4.0 V to 5.5 V)

1.71-V to 5.5-V supply for I/Os

1.8-V regulator output for filter capacitor

VDDD supply input/output (2.7 V to 5.5 V)

Ground supply

4

C4

E1

4

8

N/A

6

7

A1

VDDD

9

E3

7

EPAD

2

VDDD

6

VSS

N/A

D4

VSS

Ground supply

EPAD

VSS

C1

Ground supply

Document Number: 001-93912 Rev. *N

Page 7 of 41

EZ-PD™ CCG2 Datasheet

Figure 3. 20-ball WLCSP EZ-PD CCG2 Ball Map (Bottom (Balls Up) View)

4

3

2

1

CC2

I2C_0_SDA

I2C_0_SCL

VCCD

A

CC1

VCONN2

VSS

GPIO

RD1

XRES

B

C

D

E

GPIO

VDDD

VSS

GPIO

SWD_CLK

VCONN1

SWD_IO

VDDIO

Figure 4. 14-pin DFN Pin Map (Top View)

14

13

12

11

10

9

1

2

3

4

5

6

7

I2C_0_SDA

GPIO

I2C_0_SCL

VSS

XRES

CC1

GPIO

VCONN2

VCONN1

VCCD

GPIO

SWD_CLK

SWD_IO

8

VDDD

Figure 5. 24-Pin QFN Pin Map (Top View)

1

2

3

4

5

6

18

17

16

15

14

13

CC2

CC1

GPIO

XRES

GPIO

RD1

EPAD

VCONN2

VCONN1

VDDD

Document Number: 001-93912 Rev. *N

Page 8 of 41

EZ-PD™ CCG2 Datasheet

pins are left open. In DFP applications, the lowest VDDD level

that CCG2 can operate is 3.0 V due to the need to support

disconnect detection thresholds of up to 2.7 V.

Power

The following power system diagram shows the set of power

supply pins as implemented in EZ-PD CCG2.

A separate I/O supply pin, VDDIO, allows the GPIOs to operate

at levels from 1.71 to 5.5 V. The VDDIO pin can be equal to or

less than the voltages connected to the VCONN1, VCONN2, and

VDDD pins. The independent VDDIO supply is not available on

the 14-DFN package. On this package, the VDDIO rail is

internally connected to the VDDD rails.

EZ-PD CCG2 can operate from three different power sources.

VCONN1 and VCONN2 pins can be used as connections to the

VCONN pins on a Type-C plug of a cable or VCONN-powered

accessory. Each of these inputs support operation over 4.0 to

5.5 V. An internal isolation between VCONN1 and VCONN2 pins

is provided allowing them to be at different levels simultaneously.

CCG2 can be used in EMCA applications with only one or both

VCONN pins as power sources. This is illustrated later in the

section on Applications. Besides being power inputs, each

VCONN pin is also internally connected to a R_Atermination

resistor required for EMCA and VCONN-powered accessories.

The VCCD output of EZ-PD CCG2 must be bypassed to ground

via an external capacitor (in the range of 1 to 1.6 µF; X5R

ceramic or better).

Bypass capacitors must be used from VDDD and VCONN pins

to ground; typical practice for systems in this frequency range is

to use a 0.1-µF capacitor. Note that these are simply rules of

thumb and that for critical applications, the PCB layout, lead

inductance, and the bypass capacitor parasitic should be

simulated to design and obtain optimal bypassing.

EZ-PD CCG2 can also be operate from 2.7 to 5.5 V when

operated from the VDDD supply pin. VCONN-powered

accessory applications require that CCG2 work down to 2.7 V. In

such applications, both the VDDD and VCONN pins should be

connected to the VCONN pin of the Type-C plug in the

accessory.

An example of the power supply bypass capacitors is shown in

Figure 6.

In UFP, DFP, and DRP applications, CCG2 can be operated from

VDDD as the only supply input. In such applications, the VCONN

Figure 6. EZ-PD CCG2 Power and Bypass Scheme Example

V_CONN1

V_CONN2

0.1uF

1uF

R_A

0.1uF

V_DDD

Core Regulator

V_CCD

V_DDIO

1uF

CC

Tx/Rx

GPIO

Core

V_SS

Document Number: 001-93912 Rev. *N

Page 9 of 41

EZ-PD™ CCG2 Datasheet

MiniProg3 Kit) called MiniProg3 and (CY8CKIT-005 MiniProg4

Kit) MiniProg4 which can be used to program the flash as well as

debug firmware. The flash is programmed by downloading the

information from a hex file. This hex file is a binary file generated

as an output of building the firmware project in PSoC Creator

Software. Click here for more information on how to use the

MiniProg3 programmer. Click here for more information on how

to use the MiniProg4 programmer. There are many third-party

programmers that support mass programming in a manufac-

turing environment.

As shown in the block diagram in Figure 7, the SWD_IO and

SWD_CLK pins are connected to the host programmer's SWDIO

(data) and SWDCLK (clock) pins respectively. During SWD

programming, the device can be powered by the host

programmer by connecting its VTARG (power supply to the

target device) to VDDD pin of CCG2 device. If the CCG2 device

is powered using an on-board power supply, it can be

programmed using the “Reset Programming” option. For more

details, refer to CCGx Programming Specifications.

CCG2 Programming and Bootloading

There are two ways to program application firmware into a

CCG2 device:

1. Programming the device flash over SWD Interface

2. Application firmware update over specific interfaces (CC,

I²C)

Generally, the CCG2 devices are programmed over SWD

interface only during development or during the manufacturing

process of the end product. Once the end product is

manufactured, the CCG2 device's application firmware can be

updated via the appropriate bootloader interface. However, it is

recommended to disable the update over bootloader interface

before the end product goes to mass production, unless a

secure method of firmware update is implemented by the

customer.

Programming the CCG2 Device Flash over SWD

Interface

The CCG2 family of devices can be programmed using the SWD

interface. Cypress provides programming kits (CY8CKIT-002

Figure 7. Connecting the Programmer to CCG2 Device

3.3 V

V_DD

1F

Host Programmer

CYPD2XXX

VTARG

VDDD

SWDCLK

SWDIO

XRES

SWD_CLK

SWD_IO

XRES

V_CCD

1F

GND

Document Number: 001-93912 Rev. *N

Page 10 of 41

EZ-PD™ CCG2 Datasheet

Application Firmware Update over I²C Interface

2

Application Firmware Update (I C, CC)

This method primarily applies to CYPD2104, CYPD2119,

CYPD2120, CYPD2121, CYPD2122, CYPD2125 devices of the

CCG2 family. In these applications, the CCG2 device interfaces

to an on-board application processor or an embedded controller

or a billboard device that will act as a USB to I²C bridge over I²C

interface. Refer to Figure 8 for more details. For dongle applica-

tions like C-HDMI or C-DisplayPort, the application firmware

update can be done as shown in Figure 9.

The application firmware can be updated over two different inter-

faces depending on the default firmware programmed into the

CCG2 device. Refer to Table 28 for more details on default

firmware that various part numbers of the CCG2 family of

devices are pre-programmed with (note that some of the devices

have bootloader only and some have bootloader plus application

firmware).

Figure 8. Application Firmware Update Over I²C Interface

VDDD

2.2K 2.2K

2.2K

I2C_SDA

I2C_SCL

I2C_INT

Embedded Controller/

Application Processor

CYPD2xxx Device

To be Programmed

Figure 9. Application Firmware Update Over I²C Interface (for CYPD2119 and CYPD2120 Devices)

Display Dongle

Type-A to Type-C Cable

Billboard

(CY7C65211)

OR

Type-C Cable

I2C

Windows PC with Native

Type-C Connector

Running EZ-PD

Configuration Utility

CYPD2xxx

(Dongle)

Document Number: 001-93912 Rev. *N

Page 11 of 41

EZ-PD™ CCG2 Datasheet

Application Firmware Update over CC Interface for DFPApplica-

tions

This method primarily applies to the CYPD2134 device of the

CCG2 family. For bootloading, the CY4532 CCG3PA EVK can

be used to send programming and configuration data as Cypress

specific Vendor Defined Messages (VDMs) over the CC line. The

CY4532 EVK’s base board is connected to the system

containing CCG2 device on one end and a Windows PC running

the EZ-PD™ Configuration Utility as shown in Figure 10 on the

other end to bootload the CCG2 device.

Figure 10. Application Firmware Update Over CC Interface for DFP Applications

USB Serial Device of

CY4532 EVK Power

Board

PC

Running

EZ-PD

USB Mini-B

cable

I²C

CC Line

CYPD2xxx device

to be Bootloaded

CCG4 Device on

CY4532 EVK Power

Board

Configuration

Utility

CY4532 CCG3PA EVK’s

Power Board

Type-C

Receptacle

Mini-B

Receptacle

Application Firmware Update Over CC Interface for Cable Appli-

cations

Utility User Manual for further details on how to do the application

firmware update over CC interface for Cable applications.

This method primarily applies to the CYPD2103 and CYPD2105

devices of the CCG2 family. Refer to the EZ-PD Configuration

Document Number: 001-93912 Rev. *N

Page 12 of 41

EZ-PD™ CCG2 Datasheet

CCG2 device can be powered irrespective of which plug is

connected to the host (DFP). However, in the application

diagrams shown in Figure 13 and Figure 14, the VCONN signal

does not run through the entire cable, but only runs to the

respective VCONN pin of the CCG2 device at each end of the

plug. Also, only one CCG2 device is powered at any given

instance, depending on which one is nearer to the DFP that

supplies VCONN.

Application Diagrams

EMCA Applications

Figure 11 to Figure 14 show the application diagrams of a

Passive EMCA application using CCG2 devices. Figure 11 and

Figure 12 show the application using a single CCG2 device per

cable present at one of the two plugs, whereas Figure 13 and

Figure 14 show the same with two CCG2 devices per cable

present at each plug. The VBUS signal, the SuperSpeed lines,

HighSpeed lines, and CC lines are connected directly from one

end to another.

Note: Application diagram in Figure 12 requires external diodes

to operate in the extended VCONN voltage range of 2.7V to 5.5V

Cypress provides different firmware images for PD3.0 EMCA

and USB4 EMCA. Please contact Cypress for the latest firmware

images.

The application diagrams shown in Figure 11 and Figure 12

require a single VCONN wire to run through the cable so that the

Figure 11. Passive EMCA Application – Single EZ-PD CCG2 Per Cable (VCONN range between 4.0V to 5.5V)

Type-C

Plug

Type-C

Plug

VBUS

VCONN 2

VCONN 1

1uF

E3

E1

VDDD

VDDIO

C4

D3

E4

VCONN2

GPIO

VCONN1

0.1uF

C3

A1

C2

D2

GPIO

VCCD

1uF

B2

A4

B4

VDDIO

4.7 k

GPIO

CCG2

20-CSP

CC2

CC1

B1

D4

XRES

VSS

B3

C1

VSS

RD1

I2C_0 I2C_0

_SCL _SDA

A3

A2

SWD_ SWD_

IO CLK

E2

D1

CC

SuperSpeed and HighSpeed Lines

GND

Document Number: 001-93912 Rev. *N

Page 13 of 41

EZ-PD™ CCG2 Datasheet

Figure 12. Passive EMCA Application (PD3.0/USB4) – Single EZ-PD CCG2 Per Cable (VCONN range between 2.7V to 5.5V)

Type-C

Plug

Type-C

Plug

VBUS

Select a diode with V_Fless than 0.3V at 10mA

NSR0620P2T5G

VCONN 2

VCONN 1

2

1

2

1uF

E3

E1

VDDD

VDDIO

C4

D3

E4

C3

A1

VCONN2

GPIO

VCONN1

GPIO

0.1uF

C2

D2

GPIO

B2

A4

B4

VCCD

GPIO

1uF

CCG2

CC2

CC1

B1

D4

C1

XRES

VSS

B3

VSS

RD1

I2C_0 I2C_0

_SCL _SDA

SWD_SWD_

IO

E2

CLK

D1

A3

A2

CC

SuperSpeed and HighSpeed Lines

GND

Document Number: 001-93912 Rev. *N

Page 14 of 41

EZ-PD™ CCG2 Datasheet

Figure 13. Passive EMCA Application – Single EZ-PD CCG2 Per Plug (VCONN range between 4.0V to 5.5V)

Type-C

Plug

Type-C

Plug

VBUS

VCONN

1uF

E3

VDDD

E1

VDDIO

E3

VDDD

E1

VDDIO

E4

D3

C4

VCONN1

GPIO

VCONN2

C4

D3

E4

VCONN2

GPIO

VCONN1

0.1uF

C3

A1

C2

D2

GPIO

C3

A1

GPIO

C2

D2

GPIO

VCCD

1uF

VDDIO

VCCD

1uF

VDDIO

B2

A4

B4

GPIO

B2

A4

B4

CCG2

GPIO

CCG2

4.7k

CC2

CC1

4.7k

B1

D4

C1

CC2

CC1

XRES

VSS

B1

D4

C1

XRES

VSS

B3

VSS

RD1

B3

VSS

RD1

I2C_0 I2C_0

_SCL _SDA

SWD_ SWD_

IO

E2

I2C_0 I2C_0

_SCL _SDA

SWD_ SWD_

IO

E2

CLK

D1

CLK

D1

A3

A2

A3

A2

CC

SuperSpeed and HighSpeed Lines

GND

Figure 14. Passive EMCA Application – Single EZ-PD CCG2 Per Plug (VCONN range between 2.7V to 5.5V)

Type-C Plug

VBUS

VCONN2

VCONN1

1uF

B1

A2

B1

VDDD

A2

VDDD

VDDIO

D2

A1

VDDIO

VCONN2

VCONN1

A1

D2

VCONN2

VCONN1

0.1uF

C2

B2

GPIO

0.1uF

C2

B2

GPIO

D1

D3

CCG2

VCCD

XRES

D1

D3

1uF

CCG2

VCCD

XRES

C3

D4

1uF

CC2

CC1

C3

D4

CC2

CC1

B3

C1

VSS

RD1

B3

C1

VSS

RD1

SWD_CLK

A4

I2C_SCL

B4

SWD_IO

A3

I2C_SDA

C4

I2C_SCL

B4

SWD_CLK

A4

I2C_SDA SWD_IO

C4 A3

CC

SuperSpeed and HighSpeed Lines

GND

Document Number: 001-93912 Rev. *N

Page 15 of 41

EZ-PD™ CCG2 Datasheet

Upstream Facing Port Applications

Figure 15 shows a CCG2 device being used in a UFP application (tablet with a Type-C port) only as a power consumer.

The Type-C receptacle brings in HighSpeed and SuperSpeed lines, which are connected directly to the applications processor. The

VBUS line from the Type-C receptacle goes directly to the UFP (tablet) charger circuitry. The applications processor communicates

over the I²C signal with the CCG2 device, and the CC1 and CC2 lines from the Type-C receptacle are connected directly to the

respective CC1/2 pins of the CCG2 device.

Figure 15. Upstream Facing Port (UFP) Application – Tablet with a Type-C Port

Charger

VBUS

5.0 V

1.8 V

1 uF

E3

VDDD

E1

VDDIO

C4

D3

C2

D2

B2

A4

VCONN2

VCONN1

SWD_IO

SWD_CLK

GPIO

E4

E2

1.8 V

GPIO

CC2

D1

4.7 kΩ

CCG2

Type-C

Receptacle

INT

C3

A3

A2

B4

B3

I2C_0_SCL

CC1

Application

Processor

390 pF

1.8 V

390 pF

I2C_0_SDA

RD1

VSS

D4

VSS

C1

VCCD XRES

A1

B1

4.7 kΩ

1 uF

HighSpeed Lines

SuperSpeed Lines

Application

Processor/

Graphics

Controller

Notebook Applications

mode) or the DisplayPort Chipset (during Alternate Mode). The

SBU lines, SuperSpeed and HighSpeed lines are routed directly

from the Display Mux of the notebook to the Type-C receptacle.

Figure 16 shows a Notebook DRP application diagram using a

CCG2 device. CCG2 is not recommended for new designs for

the PC and notebook applications. CCG4, CCG5, CCG5C,

CCG6DF, CCG6SF devices are more suited for notebook appli-

cations. The below section is just maintained for legacy

purposes.

Optional FETs are provided for applications that need to provide

power for accessories and cables using the VCONN pin of the

Type-C receptacle. VBUS FETs are also used for providing

power over VBUS and for consuming power over VBUS. A

VBUS_DISCHARGE FET controlled by CCG2 device is used to

quickly discharge VBUS after the Type-C connection is

detached.

The Type-C port can be used as a power provider or a power

consumer. The CCG2 device communicates with the Embedded

controller (EC) over I²C. It also controls the Data Mux to route

the High Speed signals either to the USB chipset (during normal

Document Number: 001-93912 Rev. *N

Page 16 of 41

EZ-PD™ CCG2 Datasheet

Figure 16. Dual Role Port (DRP) Application (Not Recommended for New Designs)

VBUS FETs for

CONSUMER PATH

VBUS_SINK

CHARGER

VBUS_C_CTRL

VBUS

(5-20V)

VBUS FETs for

PROVIDER PATH

VBUS_SOURCE

VBUS

DC/DC

3.3V

VDDIO

VBUS_P_CTRL

1uF

5

1uF

VBUS_P_CTRL

15

18

22

21

24

1

VCONN1

GPIO

CC2

VBUS_DISCHARGE

5.0V

VBUS_C_CTRL

VDDIO

4

11

VCONN2

SWD_IO

SWD_CLK

GPIO

VBUS_DISCHARGE

CC2_VCONN_CTRL

CC1_VCONN_CTRL

2.2kΩ

OPTIONAL

12

FETS for DFPs

SUPPORTING

VCONN

2.2kΩ

I2C_INT

2.2kΩ

Type-C

Receptacle

CCG2

24-QFN

14

20

CC2

I2C_0_SCL

I2C_0_SDA

XRES

Embedded

Controller

19

2

CC1

VBUS

4.7kΩ

VDDIO

16

3

RD1

390pF

100kΩ

EPAD

17

VBUS_MON

VSS

GPIO

10kΩ

D+/-

HPD

USB

Chipset

SS

DP/DN

D+/-

HS/SS/DP/

SBU Lines

SDA

SCL

DisplayPort

Chipset

GND

HPD

SS

Data Mux

DP0/1/2/3

AUX+/-

Document Number: 001-93912 Rev. *N

Page 17 of 41

EZ-PD™ CCG2 Datasheet

detect undervoltage and overvoltage conditions on VBUS. To

ensure quick discharge of VBUS when the power adapter cable

is detached, a discharge path is also provided.

Downstream Facing Port Applications

Figure 17 shows a CCG2 receptacle-based Power Adapter

application in which the CCG2 device is used as a DFP. CCG2

integrates all termination resistors and uses GPIOs (VSEL_0

and VSEL_1) to indicate the negotiated power profile. The VBUS

voltage on the Type-C port is monitored using internal ADC to

For downstream facing port applications, CCG3PAoffers a much

more integrated solution and depending on the customer’s appli-

cation, it may result in additional BoM cost savings. Please refer

to the CCG3PA datasheet for more information.

Figure 17. Downstream Facing Port (DFP) Application

DC/DC

OR

VBUS

(5-20V)

VSEL_1

VSEL_0

VBUS_IN

AC-DC

SECONDARY

(5-20V)

OPTIONAL VDDIO

SUPPLY. CAN SHORT

TO VDDD IN SINGLE

SUPPLY SYSTEMS

3.3V

VDDIO

VBUS_P_CTRL

1uF

5

1uF

VBUS_P_CTRL

VSEL_1 and VSEL_0

15

18

22

21

24

1

VCONN1

GPIO

CC2

CONTROL THE SECONDARY

SIDE OF AN AC-DC OR A DC-DC

TO SELECT THE VOLTAGE ON

VBUS_IN. AN EXAMPLE IS

SHOWN BELOW:

VBUS_DISCHARGE

5.0V

4

11

VCONN2

SWD_IO

SWD_CLK

GPIO

Type-C

Receptacle

5.0V

VBUS_DISCHARGE

CC2_VCONN_CTRL

VSEL_1

VSEL_0

VBUS_IN

5V

OPTIONAL

FETS for DFPs

SUPPORTING

VCONN

0

1

0

1

0

1

12

9V

15V

20V

CCG2

24-QFN

CC1_VCONN_CTRL

14

VSEL_1

VSEL_0

20

GPIO

19

2

GPIO

CC1

VBUS

4.7kΩ

VDDIO

16

3

390pF

XRES

RD1

100kΩ

VBUS_MON

EPAD

17

VSS

GPIO

10kΩ

Document Number: 001-93912 Rev. *N

Page 18 of 41

EZ-PD™ CCG2 Datasheet

users of any Notebook that implements USB-Type C to connect

to other display types.

C-HDMI Dongle Application

CCG2 is not recommended for new designs of Type-C to video

dongles. CCG3 offers a much more integrated solution for this

application and also supports PD3.0. Please refer to the CCG3

datasheet for more details.This section is just maintained for

legacy purposes only.

This application has a Type-C plug on one end and the legacy

video (HDMI/DVI/VGA) receptacle on the other end. This appli-

cation meets the requirements described in Section 4.3 of the

VESA DisplayPort Alt Mode on USB Type-C Standard Version

1.0. This application supports display output at a resolution of up

to 4K Ultra HD (3840x2160) at 60 Hz. It also supports the USB

Billboard Device Class, which is required by the USB PD speci-

fication for enumeration of any accessories that support

Alternate Mode when connected to a host PC.

Figure 18 shows a USB Type-C to HDMI/DVI/VGAadapter appli-

cation, which enables connectivity between a PC that supports

a Type-C port with DisplayPort Alternate Mode support and a

legacy monitor that has HDMI/DVI/VGA interface. It enables

Figure 18. USB Type-C to HDMI/DVI/VGA Dongle Application Diagram

5V

VBUS_VCONN

1.2V

3.3V

VBUS

Power OR

BuckBoost

Regulator

VCONN

D+/-

VBUS

USB-Billboard

CY7C65210

XRES INT SDA SCL

3.3V

2.2kꢀ 5%

VBUS

VBUS_VCONN VCONN

2.2kꢀ 5%

18

10 13

22

P1.7 P2.1 P1.3 P1.0

14

16

5

HDMI/DVI/

VGA

Receptacle

4

100KΩ, 1%

10KΩ, 1%

P1.4

VCONN2

Type-C

Plug

4.7KΩ

17

XRES

0.1µF

P1.6

1µF

12

11

VCONN1

SWD_CLK

SWD_IO

CYPD2119

6

VDDD1

VDDD2

VDDIO

CC1

3.3V

9

21

23

P2.0

P2.2

24QFN

8

1µF

2

7

VCCD

CC

3

RD1

1µF

1

CC2

EPAD

P0.1

20

P1.5

15

P2.3:P0.0

[24:19]

HotPlug Detect

1.2V

3.3V

DP to HDMI/

DVI/VGA

Convertor

SBU_1/2

SW for AUX

Display Port

Data Lanes

Document Number: 001-93912 Rev. *N

Page 19 of 41

EZ-PD™ CCG2 Datasheet

Figure 19 shows a Type-C plug on one end and a DP/mDP plug

on the other end. The application meets the requirements

described in Section 4.2 of the VESA DisplayPort Alt Mode on

USB Type-C Standard Version 1.0 (Scenarios 2a and 2b USB

Type-C to DisplayPort Cables). It also supports the USB

Billboard Device Class, which is required by the USB PD speci-

fication for enumeration of any accessories that support

Alternate Mode when connected to a host PC.

C-DisplayPort Dongle Application

CCG2 is not recommended for new designs of Type-C to video

dongles. CCG3 offers a much more integrated solution for this

application and also supports PD3.0. Please refer to the CCG3

datasheet for more details.This section is just maintained for

legacy purposes only.

Figure 19 shows a USB Type-C to DisplayPort adapter appli-

cation, which enables connectivity between a PC that supports

a Type-C port with DisplayPort Alternate Mode support and a

legacy monitor that has a DisplayPort interface.

Figure 19. USB Type-C to Display Port Application Diagram

Paddle Card

VBUS_VCONN

Power OR

VBUS

VCONN

VBUS

D+/-

USB-Billboard

CY7C65210

XRES INT SDA SCL

VBUS_VCONN

2.2kꢀ 5%

VBUS

2.2kꢀ 5%

18

10 13

22

P1.7 P2.1 P1.3 P1.0

14

16

5

4

100KΩ, 1%

P1.4

VCONN2

Type-C

Plug

mDP/

DP

VCONN

4.7KΩ

17

XRES

P1.6

12

11

VCONN1

SWD_CLK

SWD_IO

CYPD2120

10KΩ, 1%

0.1µF

6

VDDD1

VDDD2

VDDIO

CC1

VBUS_VCONN

9

21

23

P2.0

P2.2

24QFN

8

1µF

2

7

VCCD

CC

3

RD1

1µF

1

CC2

EPAD

P0.1

20

P1.5

15

P2.3:P0.0

[24:19]

HotPlug Detect

AUX_P/N

SBU_1/2

Display Port

Data Lanes

SW for AUX

Display Port

Data Lanes

Document Number: 001-93912 Rev. *N

Page 20 of 41

EZ-PD™ CCG2 Datasheet

Electrical Specifications

Absolute Maximum Ratings

Table 2. Absolute Maximum Ratings^[1]

Parameter

V_{DDD_MAX}

Description

Min

Typ

Max

Units

Details/Conditions

Digital supply relative to V_SS

Max supply voltage relative to V_SS

GPIO voltage

–0.5

–

6

V

Absolute max

V_{CONN1_MAX}

V_{CONN2_MAX}

V_{DDIO_MAX}

V_{GPIO_ABS}

6

–

6

–

6

–0.5

V_DDIO+ 0.5

Absolute max voltage for CC1 and

CC2 pins

V_{CC_ABS}

–

6

V

Absolute max

I_{GPIO_ABS}

I_{GPIO_injection}

Maximum current per GPIO

–25

–0.5

25

0.5

mA

GPIO injection current, Max for

V_IH> V_DDD, and Min for V_IL< V_SS

Absolute max, current

injected per pin

Electrostatic discharge human

body model

ESD_HBM

2200

–

V

–

Electrostatic discharge charged

device model

ESD_CDM

LU

500

–

V

–

Pin current for latch-up

–200

200

mA

Contact discharge on

CC1, CC2, VCONN1, and

VCONN2 pins

Electrostatic discharge

IEC61000-4-2

ESD_IEC_CON

ESD_IEC_AIR

8000

–

V

Air discharge for pins

CC1, CC2, VCONN1, and

VCONN2

Electrostatic discharge

IEC61000-4-2

15000

Note

1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Document Number: 001-93912 Rev. *N

Page 22 of 41

EZ-PD™ CCG2 Datasheet

Device Level Specifications

All specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,

except where noted.

Table 3. DC Specifications

Spec ID

Parameter

Description

Power supply input voltage

GPIO power supply

Min

2.7

3.0

4.0

1.71

–

Typ

–

Max

5.5

–

Units

Details/Conditions

UFP Applications

SID.PWR#1

V_DDD

V

SID.PWR#1_A V_DDD

–

DFP/DRP Applications

SID.PWR#23

V_CONN1

–

SID.PWR#23_A V_CONN2

–

SID.PWR#13

SID.PWR#24

V_DDIO

V_CCD

–

Output voltage (for core logic)

1.8

Externalregulatorvoltagebypasson

V_CCD

SID.PWR#15

SID.PWR#16

SID.PWR#25

C_EFC

C_EXC

1

–

1.3

1

1.6

–

µF

X5R ceramic or better

Power supply decoupling capacitor

on V_DDD

Power Supply Decoupling Capacitor

on V_CONN1and V_CONN2

0.1

–

Active Mode, V_DDD= 2.7 to 5.5 V. Typical values measured at V_DD= 3.3 V.

V_CONN1or V_CONN2= 5 V,

T_A= 25 °C,

CC I/O IN Transmit or

Receive, R_Adisconnected,

no I/O sourcing current, CPU

at 12 MHz

SID.PWR#12

I_DD12

Supply current

–

7.5

2.0

–

mA

Sleep Mode, V_DDD= 2.7 to 5.5 V

V_DDD= 3.3 V, T_A= 25 °C, all

I²C wakeup. WDT ON. IMO at

48 MHz

blocks except CPU are ON,

CC I/O ON, no I/O sourcing

current

SID25A

I_DD20A

3.0

Deep Sleep Mode, V_DDD= 2.7 to 3.6 V (Regulator on)

V_CONN1, V_CONN2= 5 V,

T_A= 25 °C.

R_Atermination disabled on

V_CONN1and V_CONN2, see

SID.PD.7.

V_CONN1= 5.0, R_Atermination

disabled

SID_DS_RA

I_{DD_DS_RA}

–

100

–

µA

VCONN leaker circuits

turned off during deep sleep

R_Aswitch disabled on

V_DDD= 2.7 to 3.6 V. I²C wakeup and

WDT ON

V_CONN1and V_CONN2

.

SID34

I_DD29

–

50

–

µA

V_DDD= 3.3 V, T_A= 25 °C

Power source = V_DDD

,

Type-C not attached, CC

enabled for wakeup, R_P

disabled

SID_DS

I_{DD_DS}

V_DDD= 2.7 to 3.6 V. CC wakeup ON

Supply current while XRES asserted

2.5

XRES Current

SID307

I_{DD_XR}

–

1

10

µA

–

Document Number: 001-93912 Rev. *N

Page 23 of 41

EZ-PD™ CCG2 Datasheet

Table 4. AC Specifications

Spec ID

Parameter

Description

CPU frequency

Min

Typ

Max

Units

Details/Conditions

SID.CLK#4

F_CPU

DC

–

48

MHz

3.0 V V_DDD5.5 V

Guaranteed by

characterization

SID.PWR#20

T_SLEEP

Wakeup from sleep mode

–

0

–

µs

24-MHz IMO.

Guaranteed by charac-

SID.PWR#21

T_DEEPSLEEPWakeup from Deep Sleep mode

–

35

µs

terization

Guaranteed by

characterization

SID.XRES#5

SYS.FES#1

I/O

T_XRES

External reset pulse width

5

–

5

–

µs

Power-up to “Ready to accept I2C /

CC command”

Guaranteed by

characterization

T_{_PWR_RDY}

25

ms

Table 5. I/O DC Specifications

Spec ID

SID.GIO#37

SID.GIO#38

SID.GIO#39

SID.GIO#40

SID.GIO#41

SID.GIO#42

Parameter

Description

Min

Typ

Max

Units Details/Conditions

[2]

V_IH

Input voltage HIGH threshold

Input voltage LOW threshold

LVTTL input, V_DDIO< 2.7 V

LVTTL input, V_DDIO 2.7 V

0.7 × V_DDIO

–

V

CMOS input

V_IL

V_IH

V_IL

V_IH

V_IL

–

0.3 × V_DDIO

CMOS input

[2]

0.7× V_DDIO

–

2.0

–

0.3 × V_DDIO

–

0.8

I_OH= 4 mA at 3-V

V_DDIO

SID.GIO#33

SID.GIO#34

SID.GIO#35

V_OH

V_OL

Output voltage HIGH level

Output voltage LOW level

V_DDIO– 0.6

V_DDIO– 0.5

–

V

I_OH= 1 mA at 1.8-V

V_DDIO

I_OL= 4 mA at 1.8-V

V_DDIO

0.6

SID.GIO#36

SID.GIO#5

SID.GIO#6

V_OL

Output voltage LOW level

Pull-up resistor

–

0.6

8.5

V

I_OL= 8 mA at 3 V V_DDIO

R_PULLUP

3.5

5.6

kΩ

–

R_PULLDOWNPull-down resistor

–

25 °C, V_DDIO= 3.0

nA V.Guaranteed by

characterization

Input leakage current (absolute

value)

SID.GIO#16

SID.GIO#17

SID.GIO#43

I_IL

–

2

7

–

Guaranteed by

pF

C_IN

Input capacitance

characterization

V_DDIO 2.7 V.

mV Guaranteed by

characterization.

V_HYSTTL

Input hysteresis LVTTL

Input hysteresis CMOS

25

40

Guaranteed by

mV

SID.GPIO#44 V_HYSCMOS

0.05 × V_DDIO

–

characterization

Current through protection diode to

V_DDIO/Vss

Guaranteed by

µA

SID69

I_DIODE

–

100

200

characterization

Maximum total source or sink chip

current

Guaranteed by

mA

SID.GIO#45

I_{TOT_GPIO}

characterization

Note

2.

V

must not exceed V

+ 0.2 V.

IH

DDIO

Document Number: 001-93912 Rev. *N

Page 24 of 41

EZ-PD™ CCG2 Datasheet

Table 6. I/O AC Specifications

(Guaranteed by Characterization)

Spec ID

SID70

Parameter

T_RISEF

Description

Min

2

Typ

–

Max

12

Units

ns

Details/Conditions

3.3-V V_DDIO, Cload = 25 pF

Rise time

Fall time

SID71

T_FALLF

2

–

12

ns

XRES

Table 7. XRES DC Specifications

Spec ID

Parameter

V_IH

Description

Min

Typ

Max Units

Details/Conditions

0.7 ×

V_DDIO

SID.XRES#1

Input voltage HIGH threshold

–

V

CMOS input

0.3 ×

V_DDIO

SID.XRES#2

SID.XRES#3

SID.XRES#4

V_IL

Input voltage LOW threshold

Input capacitance

–

CMOS input

Guaranteed by

characterization

C_IN

7

pF

0.05 ×

V_DDIO

V_HYSXRES

Input voltage hysteresis

mV Guaranteed by characterization

Digital Peripherals

The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.

Pulse Width Modulation (PWM) for GPIO Pins

Table 8. PWM AC Specifications

(Guaranteed by Characterization)

Spec ID

SID.TCPWM.3

SID.TCPWM.4

Parameter

Description

Min

–

Typ

Fc

Max

–

Units

Details/Conditions

Fc max = CLK_SYS. Maximum

= 48 MHz.

T_CPWMFREQOperating frequency

MHz

ns

T_PWMENEXTInput trigger pulse width

–

2/Fc

–

For all Trigger Events

Minimum possible width of

Overflow, Underflow, and CC

(Counter equals Compare

value) outputs

SID.TCPWM.5

T_PWMEXT

Output trigger pulse width

–

2/Fc

–

ns

Minimum time between

successive counts

SID.TCPWM.5A T_CRES

SID.TCPWM.5B PWM_RES

SID.TCPWM.5C Q_RES

Resolution of counter

PWM resolution

–

1/Fc

–

ns

Minimum pulse width of PWM

output

Minimum pulse width between

quadrature-phase inputs

Quadrature inputs resolution

Document Number: 001-93912 Rev. *N

Page 25 of 41

EZ-PD™ CCG2 Datasheet

I²C

Table 9. Fixed I²C DC Specifications

(Guaranteed by Characterization)

Spec ID

SID149

Parameter

I_I2C1

Description

Min Typ Max Units

Details/Conditions

–

Block current consumption at 100 kbps

Block current consumption at 400 kbps

Block current consumption at 1 Mbps

I²C enabled in Deep Sleep mode

–

60

µA

SID150

SID151

SID152

I_I2C2

I_I2C3

I_I2C4

185

390

1.4

Table 10. Fixed I²C AC Specifications

(Guaranteed by Characterization)

Spec ID

SID153

Parameter

F_I2C1

Description

Min

Typ Max Units

Mbps –

Details/Conditions

Bit rate

–

1

UART

Table 11. Fixed UART DC Specifications

(Guaranteed by Characterization)

Spec ID

SID160

SID161

Parameter

Description

Min Typ

Max Units

Block current consumption at

100 Kbps

Guaranteed by

characterization

I_UART1

–

125

312

µA

Block current consumption at

1000 Kbps

Guaranteed by

characterization

I_UART2

Table 12. Fixed UART AC Specifications

(Guaranteed by Characterization)

Spec ID

SID162

SPI

Parameter

Description

Min

Typ

Max Units

Details/Conditions

Guaranteed by

characterization

F_UART

Bit rate

–

1

Mbps

Table 13. Fixed SPI DC Specifications

(Guaranteed by Characterization)

Spec ID

SID163

Parameter

I_SPI1

I_SPI2

I_SPI3

Description

Min

Typ

Max

Units

Details/Conditions

Guaranteed by

characterization

Block current consumption at 1 Mbps

–

360

µA

Guaranteed by

characterization

SID164

SID165

Block current consumption at 4 Mbps

Block current consumption at 8 Mbps

–

560

600

µA

Guaranteed by

characterization

Table 14. Fixed SPI AC Specifications

(Guaranteed by Characterization)

Spec ID

SID166

Parameter

F_SPI

Description

Min

Typ

Max

Units

Details/Conditions

SPI Operating frequency (Master; 6X

oversampling)

Guaranteed by

characterization

–

8

MHz

Document Number: 001-93912 Rev. *N

Page 26 of 41

EZ-PD™ CCG2 Datasheet

Table 15. Fixed SPI Master Mode AC Specifications

(Guaranteed by Characterization)

Spec ID

SID167

Parameter

T_DMO

Description

Min

Typ

Max

Units

Details/Conditions

MOSI Valid after SClock driving

edge

Guaranteed by

characterization

–

15

ns

Full clock, late MISO

sampling.Guaranteed

by characterization

MISO Valid before SClock

capturing edge

SID168

SID169

T_DSI

20

0

–

ns

Referred to Slave

capturing edge.

Guaranteed by

characterization

T_HMO

Previous MOSI data hold time

Table 16. Fixed SPI Slave Mode AC Specifications

(Guaranteed by Characterization)

Spec ID

SID170

Parameter

T_DMI

Description

Min

Typ

Max

Units Details/Conditions

MOSI Valid before Sclock

Capturing edge

Guaranteed by

ns

40

–

characterization

TCPU = 1/FCPU.

Guaranteed by

characterization.

MISO Valid after Sclock driving

edge

42 + (3 ×

SID171

T_DSO

–

ns

T_CPU

48

–

)

MISO Valid after Sclock driving

edge in Ext Clk mode

Guaranteed by

characterization

SID171A

SID172

T_{DSO_EXT}

T_HSO

–

0

–

ns

Guaranteed by

characterization

Previous MISO data hold time

Guaranteed by

characterization

SID172A

T_SSELSCK

SSEL Valid to first SCK Valid edge 100

–

Memory

Table 17. Flash AC Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Row (block) write time (erase and

program)

Row (block) =

128 bytes

[3]

SID.MEM#4 T_ROWWRITE

–

20

ms

[3]

SID.MEM#3 T_ROWERASE

Row erase time

–

13

7

ms

–

[3]

SID.MEM#8 T_ROWPROGRAM

Row program time after erase

Bulk erase time (32 KB)

[3]

SID178

T_BULKERASE

35

Guaranteed by

characterization

[3]

SID180

T_DEVPROG

Total device program time

Flash endurance

–

100 K

20

–

7.5

–

seconds

cycles

years

Guaranteed by

characterization

SID181

SID182

SID182A

F_END

Flash retention. T_A 55 °C, 100 K

P/E cycles

Guaranteed by

characterization

F_RET1

F_RET2

–

Flash retention. T_A 85 °C, 10 K

P/E cycles

Guaranteed by

characterization

10

–

years

Note

3. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.

Document Number: 001-93912 Rev. *N

Page 27 of 41

EZ-PD™ CCG2 Datasheet

System Resources

Power-on-Reset (POR) with Brown Out

Table 18. Imprecise Power On Reset (PRES)

Spec ID

SID185

Parameter

V_RISEIPOR

Description

Rising trip voltage

Min

Typ

Max

Units

Details/Conditions

Guaranteed by

characterization

0.80

–

1.50

V

Guaranteed by

characterization

SID186

V_FALLIPOR

Falling trip voltage

0.75

–

1.4

V

Table 19. Precise Power On Reset (POR)

Spec ID Parameter

SID190 V_FALLPPOR

Description

Min

Typ

Max

Units

Details/Conditions

BOD trip voltage in active and

sleep modes

Guaranteed by

characterization

1.48

–

1.62

V

Guaranteed by

characterization

SID192

V_FALLDPSLP

BOD trip voltage in Deep Sleep

1.1

–

1.5

V

SWD Interface

Table 20. SWD Interface Specifications

Spec ID Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SWDCLK 1/3 CPU

SID.SWD#1 F_SWDCLK1

SID.SWD#2 F_SWDCLK2

3.3 V  V_DDIO 5.5 V

–

14

MHz

clock frequency

SWDCLK  1/3 CPU

clock frequency

1.8 V  V_DDIO 3.3 V

–

7

MHz

ns

Guaranteed by

characterization

SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK

SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK

0.25 × T

–

Guaranteed by

characterization

0.25 × T

–

0.5 × T

–

ns

Guaranteed by

characterization

SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK

SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK

Internal Main Oscillator

–

1

ns

Guaranteed by

characterization

ns

Table 21. IMO DC Specifications

(Guaranteed by Design)

Spec ID

SID218

Parameter

I_IMO

Description

Min

Typ

Max

Units

Details/Conditions

–

IMO operating current at 48 MHz

–

1000

µA

Table 22. IMO AC Specifications

Spec ID Parameter

SID.CLK#13 F_IMOTOL

Description

Min

Typ

Max

Units

Details/Conditions

Frequency variation at 24, 36,

and 48 MHz (trimmed)

–

±2

%

–

Guaranteed by

characterization

SID226

T_STARTIMO

IMO startup time

–

7

µs

Guaranteed by

characterization

SID229

F_IMO

T_JITRMSIMO

–

RMS jitter at 48 MHz

IMO frequency

–

145

–

ps

24

48

MHz

–

Document Number: 001-93912 Rev. *N

Page 28 of 41

EZ-PD™ CCG2 Datasheet

Internal Low-Speed Oscillator

Table 23. ILO DC Specifications

(Guaranteed by Design)

Spec ID

SID231

SID233

Parameter

I_ILO

I_ILOLEAK

Description

Min

–

Typ

0.3

2

Max

1.05

15

Units

µA

Details/Conditions

Guaranteed by

Characterization

ILO operating current at 32 kHz

ILO leakage current

–

nA

Guaranteed by Design

Table 24. ILO AC Specifications

Spec ID

Parameter

T_STARTILO

Description

Min

Typ

Max

Units

Details/Conditions

Guaranteed by

characterization

SID234

ILO startup time

–

2

ms

Guaranteed by

characterization

SID236

T_ILODUTY

ILO duty cycle

ILO Frequency

40

20

50

40

60

80

%

SID.CLK#5 F_ILO

kHz

–

Power Down

Table 25. PD DC Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

DFP CC termination for default

USB Power

SID.PD.1 Rp_std

SID.PD.2 Rp_1.5A

64

80

96

µA

–

DFP CC termination for 1.5A

power

166

180

194

µA

DFP CC termination for 3.0A

power

SID.PD.3 Rp_3.0A

SID.PD.4 Rd

304

330

5.1

356

µA

kΩ

–

UFP CC termination

4.59

5.61

All supplies forced to 0 V

and0.6VappliedatRD1

or CC2

UFP Dead Battery CC termi-

nation on RD1 and CC2

SID.PD.5 Rd_DB

SID.PD.6 R_A

4.08

0.8

5.1

1.0

6.12

1.2

–

kΩ

M

All supplies forced to 0 V

and 0.2 V applied at

V_CONN1or V_CONN2

Power cable termination

2.7 V applied at V_CONN1

or V_CONN2with R_A

disabled

Power cable termination -

Disabled

SID.PD.7 Ra_OFF

0.4

0.75

SID.PD.8 Rleak_1

SID.PD.9 Rleak_2

SID.PD.10 Rleak_3

SID.PD.11 Rleak_4

SID.PD.12 Rleak_5

SID.PD.13 Rleak_6

V_CONNleaker for 0.1-µF load

V_CONNleaker for 0.5-µF load

V_CONNleaker for 1.0-µF load

V_CONNleaker for 2.0-µF load

V_CONNleaker for 5.0-µF load

V_CONNleaker for 10-µF load

–

216

41.2

19.6

9.8

kΩ

Managed Active Cable

(MAC) discharge

4.1

2.0

Leaker on V_CONN1and V_CONN2

for discharge upon cable detach

SID.PD.14 Ileak

150

–

µA

–

Document Number: 001-93912 Rev. *N

Page 29 of 41

EZ-PD™ CCG2 Datasheet

Analog-to-Digital Converter

Table 26. ADC DC Specifications

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

bits Guaranteed by characterization

LSB Guaranteed by characterization

SID.ADC.1 Resolution ADC resolution

–

8

–

SID.ADC.2 INL

SID.ADC.3 DNL

Integral non-linearity

Differential non-linearity

–1.5

–2.5

–1

1.5

2.5

1

SID.ADC.4 Gain Error Gain error

Table 27. ADC AC Specifications

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

Rate of change of sampled voltage

signal

SID.ADC.5 SLEW_Max

–

3

V/ms Guaranteed by characterization

Document Number: 001-93912 Rev. *N

Page 30 of 41

EZ-PD™ CCG2 Datasheet

Ordering Information

The EZ-PD CCG2 part numbers and features are listed in Table 28.

Table 28. EZ-PD CCG2 Ordering Information

Type-C Termination

Part Number

Application

Role

Default FW

Package

Ports

Resistor

[4]

CYPD2103-20FNXIT

CYPD2103-14LHXIT

CYPD2104-20FNXIT

Cable

1

R_A

Cable

20-ball CSP

14-pin DFN

20-ball CSP

EMCA CC Bootloader with

Application firmware

[4]

R_A

Accessory

R_D

Accessory

I²C Bootloader Only

[5]

EMCA CC Bootloader with

Application firmware

[4]

CYPD2105-20FNXIT

Active Cable

1

R_A

Active Cable

20-ball CSP

[5]

I²C Bootloader with Appli-

cation firmware

CYPD2119-24LQXIT

CYPD2120-24LQXIT

C-DP

1

R_D

UFP

24-pin QFN

[5]

C-HDMI

R_D

Dock/Monitor

Upstream port

[5]

CYPD2121-24LQXIT

1

R_P^[6], R_D

DRP

24-pin QFN

[5]

CYPD2122-20FNXIT

CYPD2122-24LQXI

CYPD2122-24LQXIT

Tablet

1

R_P^[6], R_D

DRP

20-ball CSP

24-pin QFN

Notebook

I²C Bootloader Only

Dock/Monitor

Downstream port

[6]

CYPD2125-24LQXIT

1

R_P

DFP

24-pin QFN

[6]

CYPD2134-24LQXIT

CYPD2134-24LQXQT

DFP

1

R_P

DFP

24-pin QFN

DFP CC Bootloader Only

[6]

R_P

Ordering Code Definitions

X

XX

X

I

T

2

CY PD

-

1

T = Tape and Reel

Temperature Grade:

^{I = Industrial (}40 °C to 85 °C), Q = Extended Industrial (40 °C to105 °C)

Pb-free

Package Type: XX = FN, LH or LQ

FN = CSP; LH = DFN; LQ = QFN

Number of pins in the package: XX = 14, 20, or 24

Device Role: Unique combination of role and termination:

X = 0 or 1 or 2 or 3 or 4 or 5 or 9

Feature: Unique Applications:

X = 0 or 1 or 2 or 3

Number of Type-C Ports: 1 = 1 Port

Product Type: 2 = Second-generation product family, CCG2

Marketing Code: PD = Power Delivery product family

Company ID: CY = Cypress

Notes

4. Termination resistor denoting an EMCA.

5. Termination resistor denoting an accessory or upstream facing port.

6. Termination resistor denoting a downstream facing port.

Document Number: 001-93912 Rev. *N

Page 31 of 41

EZ-PD™ CCG2 Datasheet

Packaging

Table 29. Package Characteristics

Parameter

T_A

Description

Conditions

Min

Typ

Max

85

105

100

125

–

Units

°C

Industrial

Operating ambient temperature

Operating junction temperature

–40

25

Extended Industrial

°C

Industrial

°C

T_J

–40

–

Extended Industrial

°C

T_JA

T_JC

T_JA

T_JC

T_JA

T_JC

Package _JA(20-ball WLCSP)

Package _JC(20-ball WLCSP)

Package _JA(14-pin DFN)

Package _JC(14-pin DFN)

Package _JA(24-pin QFN)

Package _JC(24-pin QFN)

–

66

0.7

31

59

22

29

°C/W

–

Table 30. Solder Reflow Peak Temperature

Package Maximum Peak Temperature

20-ball WLCSP

Maximum Time within 5 °C of Peak Temperature

260 °C

30 seconds

14-pin DFN

24-pin QFN

Table 31. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

20-ball WLCSP

MSL

MSL 1

MSL 3

14-pin DFN

24-pin QFN

Document Number: 001-93912 Rev. *N

Page 32 of 41

EZ-PD™ CCG2 Datasheet

Figure 21. 20-ball WLCSP (1.63 × 2.03 × 0.55 mm) Package Outline, 001-95010

001-95010 *B

Document Number: 001-93912 Rev. *N

Page 33 of 41

EZ-PD™ CCG2 Datasheet

Figure 22. 14-pin DFN ((2.5 × 3.5 × 0.6 mm) 0.95 × 3.00 E-Pad (Sawn)) Package Outline, 001-96312

001-96312 **

Figure 23. 24-Pin QFN ((4 × 4 × 0.55 mm) 2.65 × 2.65 E-Pad (Sawn)) Package Outline, 001-13937

001-13937 *H

Document Number: 001-93912 Rev. *N

Page 34 of 41

EZ-PD™ CCG2 Datasheet

Table 32. Acronyms Used in this Document (continued)

Acronyms

Acronym

NVIC

opamp

OCP

OVP

PCB

Description

nested vectored interrupt controller

operational amplifier

overcurrent protection

overvoltage protection

printed circuit board

power delivery

Table 32. Acronyms Used in this Document

Acronym

ADC

Description

analog-to-digital converter

API

ARM^®

application programming interface

advanced RISC machine, a CPU architecture

configuration channel

CC

PD

CCG2

CPU

Cable Controller Generation 2

central processing unit

PGA

PHY

programmable gain amplifier

physical layer

cyclic redundancy check, an error-checking

protocol

CRC

POR

PRES

PSoC^®

PWM

RAM

RISC

RMS

RTC

power-on reset

CS

current sense

precise power-on reset

Programmable System-on-Chip™

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

DFP

downstream facing port

digital input/output, GPIO with only digital capabil-

ities, no analog. See GPIO.

DIO

DRP

dual role port

electrically erasable programmable read-only

memory

EEPROM

real-time clock

a USB cable that includes an IC that reports cable

characteristics (e.g., current rating) to the Type-C

ports

EMCA

RX

receive

SAR

successive approximation register

I²C serial clock

I²C serial data

EMI

ESD

FPB

FS

electromagnetic interference

electrostatic discharge

flash patch and breakpoint

full-speed

SCL

SDA

S/H

sample and hold

Serial Peripheral Interface, a communications

protocol

SPI

GPIO

IC

general-purpose input/output

integrated circuit

SRAM

SWD

TX

static random access memory

serial wire debug, a test protocol

transmit

IDE

integrated development environment

Inter-Integrated Circuit, a communications

protocol

I²C, or IIC

a new standard with a slimmer USB connector and

a reversible cable, capable of sourcing up to

100 W of power

ILO

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

input/output, see also GPIO

low-voltage detect

Type-C

IMO

I/O

Universal Asynchronous Transmitter Receiver, a

communications protocol

UART

USB

LVD

LVTTL

MCU

NC

Universal Serial Bus

low-voltage transistor-transistor logic

microcontroller unit

USB input/output, CCG2 pins used to connect to a

USB port

USBIO

XRES

no connect

external reset I/O pin

NMI

nonmaskable interrupt

Document Number: 001-93912 Rev. *N

Page 35 of 41

EZ-PD™ CCG2 Datasheet

Document Conventions

Units of Measure

Table 33. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

hertz

Hz

KB

kHz

k

Mbps

MHz

M

Msps

µA

1024 bytes

kilohertz

kilo ohm

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

microsecond

microvolt

µF

µs

µV

µW

mA

ms

mV

nA

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

ohm

ns



pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

V

samples per second

volt

Document Number: 001-93912 Rev. *N

Page 36 of 41

EZ-PD™ CCG2 Datasheet

■ AN95615 – Designing USB 3.1 Type-C Cables Using EZ-PD™

CCG2

References and Links To Applications

Collaterals

■ AN95599 – Hardware Design Guidelines for EZ-PD™ CCG2

Knowledge Base Articles

■ AN210403 – Hardware Design Guidelines for Dual Role Port

■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and

Applications Using EZ-PD™ USB Type-C Controllers

CCG4 – KBA210740

■ AN210771 – Getting Started with EZ-PD™ CCG4

■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™

CCG4 Using PSoC® Programmer and MiniProg3 – KBA96477

Reference Designs

■ CCGX Frequently Asked Questions (FAQs) – KBA97244

■ Handling Precautions for CY4501 CCG1 DVK – KBA210560

■ Cypress EZ-PD™ CCGx Hardware – KBA204102

■ Difference between USB Type-C and USB-PD – KBA204033

■ CCGx Programming Methods – KBA97271

■ EZ-PD™ CCG2 Electronically Marked Cable Assembly

(EMCA) Paddle Card Reference Design

■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution

■ CCG1 USB Type-C to DisplayPort Cable Solution

■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution

■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution

■ Getting started with Cypress USB Type-C Products –

KBA04071

■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle

■ Type-C to DisplayPort Cable Electrical Requirements

Card Reference Design

■ Dead Battery Charging Implementation in USB Type-C

Solutions – KBA97273

■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card

Reference Schematics

■ TerminationResistorsRequired forthe USBType-C Connector

– KBA97180

■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle

■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution

■ CCG2 20W Power Adapter Reference Design

■ CCG2 18W Power Adapter Reference Design

■ VBUS Bypass Capacitor Recommendation for Type-C Cable

and Type-C to Legacy Cable/AdapterAssemblies – KBA97270

■ Need for Regulator and Auxiliary Switch in Type-C to

DisplayPort (DP) Cable Solution – KBA97274

■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference

Design Kit

■ Need for a USB Billboard Device in Type-C Solutions –

KBA97146

Kits

■ CCG1DevicesinType-CtoLegacy Cable/AdapterAssemblies

– KBA97145

■ CY4501 CCG1 Development Kit

■ CY4502 EZ-PD™ CCG2 Development Kit

■ CY4531 EZ-PD™ CCG3 Evaluation Kit

■ CY4541 EZ-PD™ CCG4 Evaluation Kit

■ Cypress USB Type-C Controller Supported Solutions –

KBA97179

■ Termination Resistors for Type-C to Legacy Ports – KBA97272

■ Handling Instructions for CY4502 CCG2 Development Kit –

KBA97916

Datasheets

■ Thunderbolt™ Cable Application Using CCG3 Devices -

KBA210976

■ CCG1 Datasheet: USB Type-C Port Controller with Power

Delivery

■ PowerAdapterApplication Using CCG3 Devices – KBA210975

■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode

■ Methods to Upgrade Firmware on CCG3 Devices –

Controller on Type-C

KBA210974

■ CCG3: USB Type-C Controller Datasheet

■ Device Flash Memory Size and Advantages – KBA210973

■ Applications of EZ-PD™ CCG4 – KBA210739

■ CCG4: Two-Port USB Type-C Controller Datasheet

Application Notes

■ AN96527 – Designing USB Type-C Products Using Cypress’s

CCG1 Controllers

Document Number: 001-93912 Rev. *N

Page 37 of 41

EZ-PD™ CCG2 Datasheet

Document History Page

Description Title: EZ-PD™ CCG2 Datasheet, USB Type-C Port Controller

Document Number: 001-93912

Submission

Revision

ECN

Description of Change

Date

*E

*F

4680071

4718374

03/07/2015 Post to external web.

04/09/2015 Added 24-pin QFN package related information in all instances across the document.

Updated Application Diagrams:

Added Figure 16.

Added Figure 17.

Updated Ordering Information:

Updated Table 28:

Updated part numbers.

Updated Packaging:

Added spec 001-13937 *E.

*G

4774142

06/15/2015 Changed status from Preliminary to Final.

Updated Logic Block Diagram.

Updated Functional Overview:

Updated GPIO:

Updated description.

Updated Power:

Updated description.

Updated Application Diagrams:

Updated Figure 17.

Updated Electrical Specifications:

Updated Device Level Specifications:

Updated Table 3:

Added SID.PWR#1_A spec and its corresponding details.

Updated Digital Peripherals:

Updated UART:

Updated Table 11:

Updated all values corresponding to SID160 spec.

Updated Ordering Information:

Updated Table 28:

Updated part numbers.

Removed “Errata”.

*H

4979175

10/23/2015 Updated EZ-PD CCG2 Block Diagram:

Updated Figure 1.

Updated Pinouts:

Updated Figure 5.

Document Number: 001-93912 Rev. *N

Page 38 of 41

EZ-PD™ CCG2 Datasheet

Document History Page (continued)

Description Title: EZ-PD™ CCG2 Datasheet, USB Type-C Port Controller

Document Number: 001-93912

Submission

Revision

ECN

Description of Change

Date

*H (cont.)

4979175

10/23/2015 Updated Electrical Specifications:

Updated Absolute Maximum Ratings:

Updated Table 2:

Added VCC_ABS spec and its corresponding details.

Updated Device Level Specifications:

Updated I/O:

Updated Table 5:

Updated details in “Details/Conditions” column corresponding to SID.GIO#16, SID.GIO#17

specs.

Updated XRES:

Updated Table 7:

Updated details in “Details/Conditions” column corresponding to SID.XRES#3 spec.

Updated Digital Peripherals:

Updated UART:

Updated Table 11:

Updated details in “Details/Conditions” column corresponding to all specs.

Updated Table 12:

Updated details in “Details/Conditions” column corresponding to all specs.

Updated SPI:

Updated Table 13:

Updated details in “Details/Conditions” column corresponding to all specs.

Updated Table 14:

Updated details in “Details/Conditions” column corresponding to all specs.

Updated Table 15:

Updated details in “Details/Conditions” column corresponding to all specs.

Updated Table 16:

Updated details in “Details/Conditions” column corresponding to all specs.

Updated System Resources:

Updated Internal Main Oscillator:

Updated Table 13:

Updated details in “Details/Conditions” column corresponding to SID226, SID229 specs

Updated Analog-to-Digital Converter:

Updated Table 26:

Updated details in “Details/Conditions” column corresponding to all specs.

Updated all values corresponding to SID.ADC.4 spec.

Updated Table 27:

Updated details in “Details/Conditions” column corresponding to all specs.

*I

5028128

5186972

12/04/2015 Updated Application Diagrams:

Added Figure 18.

Added Figure 19.

Added Figure 20.

Updated Ordering Information:

Updated Table 28:

Updated part numbers.

*J

03/28/2016 Updated Features:

Updated Packages:

Updated description.

Updated Ordering Information:

Updated Table 28:

Updated part numbers.

Updated Packaging:

No change in revisions.

Updated Table 29:

Updated all details corresponding to T_Aand T_Jparameters.

Document Number: 001-93912 Rev. *N

Page 39 of 41

EZ-PD™ CCG2 Datasheet

Document History Page (continued)

Description Title: EZ-PD™ CCG2 Datasheet, USB Type-C Port Controller

Document Number: 001-93912

Submission

Revision

ECN

Description of Change

Date

*K

5303957

06/13/2016 Added Available Firmware and Software Tools.

Updated Application Diagrams:

Added description.

Updated Figure 12.

Updated Figure 15.

Updated Figure 16.

Updated Figure 17.

Added References and Links To Applications Collaterals.

Updated to new template.

*L

5387677

6097993

08/02/2016 Updated Ordering Information:

Updated Table 28:

Updated part numbers.

Completing Sunset Review.

*M

07/11/2018 Updated Application Diagrams:

Updated description.

Updated Figure 11 (Updated caption only).

Added Figure 12.

Updated Figure 13 (Updated caption only).

Added Figure 14.

Updated Packaging:

spec 001-95010 – Changed revision from *A to *B.

spec 001-13937 – Changed revision from *F to *G.

Added compliance to USB Specification.

Updated to new template.

*N

7035126

12/04/2020 Updated Figure 6 in Power section.

Added CCG2 Programming and Bootloading section.

Updated descriptions before all application diagrams in Application Diagrams section.

Added column “Default FW” in Table 28 in Ordering Information section.

Updated Figure 23 in Packaging section.

Document Number: 001-93912 Rev. *N

Page 40 of 41

EZ-PD™ CCG2 Datasheet

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Arm^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

| Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/wireless

Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB

Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify

the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely

responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any

modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you

had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT

NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,

such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product

to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any

liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming

code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this

information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons

systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances

management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device

or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you

shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from

and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United

States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-93912 Rev. *N

Revised December 4, 2020

Page 41 of 41


型号：	CYPD2119-24LQXI
厂家：	Infineon
描述：	EZ-PD™ CCG2 USB Type-C Port Controller 光电二极管
文件：	总42页 (文件大小：665K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYPD2119-24LQXI [INFINEON]

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