CY9BF168NPQC-G-JNE2 [INFINEON]
FM4 CY9BFx6xM/N/R-Series Motor Control Arm® Cortex®-M4 Microcontroller (MCU) Family;型号: | CY9BF168NPQC-G-JNE2 |
厂家: | Infineon |
描述: | FM4 CY9BFx6xM/N/R-Series Motor Control Arm® Cortex®-M4 Microcontroller (MCU) Family 微控制器 |
文件: | 总161页 (文件大小:3559K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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CY9B160R Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
The CY9B160R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and
competitive cost.
These series are based on the ARM® Cortex®-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions
such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C, LIN).
Features
[SRAM]
32-bit ARM® Cortex®-M4F Core
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to I-code bus or
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
◼Processor version: r0p1
◼Up to 160 MHz Frequency Operation
◼FPU built-in
◼SRAM0: Up to 64 Kbytes
◼SRAM1: Up to 32 Kbytes
◼SRAM2: Up to 32 Kbytes
◼Support DSP instruction
◼Memory Protection Unit (MPU): improves the reliability of an
embedded system
External Bus Interface
◼Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
◼Supports SRAM, NOR, NAND Flash and SDRAM device
◼Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
◼8-/16-bit Data width
◼24-bit System timer (Sys Tick): System timer for OS task
management
◼Up to 25-bit Address bit
On-chip Memories
◼Maximum Access size: 256M byte
◼Supports Address/Data multiplex
◼Supports external RDY function
◼Supports scramble function
[Flash memory]
These series are based on two independent on-chip Flash
memories.
◼MainFlash memory
Up to 1024 Kbytes
◼Possible to set the validity/invalidity of the scramble function
for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4
Mbytes units.
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
The read access to Flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to Flash memory can be obtained by
Flash Accelerator System.
◼Possible to set two kinds of the scramble key
◼Note: It is necessary to prepare the dedicated software
library to use the scramble function.
Security function for code protection
◼WorkFlash memory
32 Kbytes
Read cycle:
Multi-function Serial Interface (Max 8 channels)
◼64 bytes with FIFO (the FIFO step numbers are variable
depending on the settings of the communication mode or bit
length.)
• 6 wait-cycle: the operation frequency more than 120
MHz, and up to 160 MHz
◼Operation mode is selectable from the followings for each
• 4 wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
• 2 wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
• 0 wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
channel.
UART
CSIO
LIN
I2C
Cypress Semiconductor Corporation
Document Number: 002-04918 Rev. *G
• 198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 21, 2021
CY9B160R Series
[UART]
DSTC (Descriptor System Data Transfer Controller)
(128 channels)
◼Full-duplex double buffer
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the Descriptor system and,
following the specified contents of the Descriptor which has
already been constructed on the memory, can access directly
the memory /peripheral device and performs the data transfer
operation.
◼Selection with or without parity supported
◼Built-in dedicated baud rate generator
◼External clock available as a serial clock
◼Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
It supports the software activation, the hardware activation and
the chain activation functions.
◼Various error detect functions available (parity errors,
framing errors, and overrun errors)
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
[CSIO]
◼Full-duplex double buffer
◼Successive Approximation type
◼Built-in 3 units
◼Built-in dedicated baud rate generator
◼Overrun error detect function available
◼Serial chip select function (ch.6 and ch.7 only)
◼Supports high-speed SPI (ch.4 and ch.6 only)
◼Data length 5 to 16-bit
◼Conversion time: 0.5 μs @ 5 V
◼Priority conversion available (priority at 2 levels)
◼Scanning conversion mode
◼Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
[LIN]
◼LIN protocol Rev.2.1 supported
◼Full-duplex double buffer
DA converter (Max 2 channels)
◼R-2R type
◼Master/Slave mode supported
◼12-bit resolution
◼LIN break field generation (can change to 13 to 16-bit
length)
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
◼LIN break delimiter generation (can change to 1 to 4-bit
length)
◼16-bit PWM timer
◼16-bit PPG timer
◼Various error detect functions available (parity errors,
framing errors, and overrun errors)
[I2C]
◼16-/32-bit reload timer
◼16-/32-bit PWC timer
◼Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
◼Fast-mode Plus (Fm+) (Max 1000 kbps, only for ch.3 = ch.A
General Purpose I/O Port
and ch.7 = ch.B) supported
This series can use its pins as general purpose I/O ports when
they are not used for external bus or peripherals. Moreover,
the port relocate function is built in. It can set which I/O port
the peripheral function can be allocated.
DMA Controller (8 channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
◼Capable of pull-up control per pin
◼Capable of reading pin level directly
◼Built-in the port relocate function
◼8 independently configured and operated channels
◼Transfer can be started by software or request from the built-
in peripherals
◼Up to 100 high-speed general-purpose I/O ports @ 120 pin
Package
◼Transfer address area: 32-bit (4 Gbytes)
◼Transfer mode: Block transfer/Burst transfer/Demand
transfer
◼Some pin is 5V tolerant I/O.
◼See “Pin Description” and “I/O Circuit Type” for the
corresponding pins.
◼Transfer data type: bytes/half-word/word
◼Transfer block count: 1 to 16
◼Number of transfers: 1 to 65536
Document Number: 002-04918 Rev. *G
Page 2 of 160
CY9B160R Series
Multi-function Timer (Max 2 units)
Dual Timer (32-/16-bit Down Counter)
The Multi-function timer is composed of the following blocks.
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Minimum resolution: 6.25 ns
Operation mode is selectable from the followings for each
channel.
◼16-bit free-run timer × 3 ch./unit
◼Input capture × 4 ch./unit
◼Free-running
◼Periodic ( = Reload)
◼One-shot
◼Output compare × 6 ch./unit
◼A/D activation compare × 6 ch./unit
◼Waveform generator × 3 ch./unit
◼16-bit PPG timer × 3 ch./unit
Watch Counter
The Watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in high-speed CR clock or built-in low-speed CR
clock as the clock source.
The following function can be used to achieve the motor
control.
◼PWM signal output function
Interval timer: up to 64s (Max) @ Sub Clock: 32.768 kHz
◼DC chopper waveform output function
◼Dead time function
External Interrupt Controller Unit
◼External interrupt input pin: Max 16 pins
◼Include one non-maskable interrupt (NMI)
◼Input capture function
◼A/D convertor activate function
◼DTIF (Motor emergency stop) interrupt function
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
This series consists of two different watchdogs, a “Hardware”
watchdog and a “Software” watchdog.
“Hardware” watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, “Hardware” watchdog is active in any
power saving mode except STOP.
◼Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
◼Timer interrupt function after set time or each set time.
◼Capable of rewriting the time with continuing the time count.
◼Leap year automatic count is available.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
◼CCITT CRC16 Generator Polynomial: 0x1021
Quadrature Position/Revolution Counter (QPRC)
(Max 2 channels)
◼IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
SD Card Interface
It is possible to use the SD card that conforms to the following
standards.
◼The detection edge of the three external event input pins
◼Part 1 Physical Layer Specification version 3.01
◼Part E1 SDIO Specification version 3.00
AIN, BIN and ZIN is configurable.
◼16-bit position counter
◼Part A2 SD Host Controller Standard Specification version
◼16-bit revolution counter
◼Two 16-bit compare registers
3.00
◼1-bit or 4-bit data bus
Document Number: 002-04918 Rev. *G
Page 3 of 160
CY9B160R Series
Clock and Reset
Low-power Consumption Mode
Six low-power consumption modes are supported.
[Clocks]
◼SLEEP
◼TIMER
◼RTC
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
◼Main clock:
◼Sub Clock:
4 MHz to 48 MHz
32.768 kHz
◼STOP
◼High-speed internal CR Clock: 4 MHz
◼Low-speed internal CR Clock: 100 kHz
◼Main PLL Clock
◼Deep standby RTC (selectable from with/without RAM
retention)
◼Deep standby stop (selectable from with/without RAM
retention)
[Resets]
VBAT
◼Reset requests from INITX pin
◼Power on reset
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
◼Software reset
◼Watchdog timers reset
◼Low voltage detector reset
◼Clock supervisor reset
◼RTC
◼32 kHz oscillation circuit
◼Power-on circuit
◼Back up register: 32 bytes
◼Port circuit
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
◼External OSC clock failure (clock stop) is detected, reset is
asserted.
Debug
◼Serial Wire JTAG Debug Port (SWJ-DP)
◼External OSC frequency anomaly is detected, interrupt or
reset is asserted.
◼Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
Low-Voltage Detector (LVD)
Unique ID
Unique value of the device (41-bit) is set.
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
Power Supply
Two Power Supplies
◼LVD1: error reporting via interrupt
◼LVD2: auto-reset operation
◼Wide range voltage:
VCC
=
=
2.7 V to 5.5 V
2.7 V to 5.5 V
◼Power supply for VBAT:
VBAT
Document Number: 002-04918 Rev. *G
Page 4 of 160
CY9B160R Series
Contents
1. Product Lineup.................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment................................................................................................................................................................. 9
4. Pin Description................................................................................................................................................................ 15
5. I/O Circuit Type................................................................................................................................................................ 43
6. Handling Precautions ..................................................................................................................................................... 50
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 50
Precautions for Package Mounting.............................................................................................................................. 51
Precautions for Use Environment................................................................................................................................ 52
7. Handling Devices ............................................................................................................................................................ 53
8. Block Diagram................................................................................................................................................................. 56
9. Memory Size.................................................................................................................................................................... 57
10. Memory Map .................................................................................................................................................................... 57
11. Pin Status in Each CPU State ........................................................................................................................................ 60
12. Electrical Characteristics ............................................................................................................................................... 67
12.1 Absolute Maximum Ratings......................................................................................................................................... 67
12.2 Recommended Operating Conditions.......................................................................................................................... 68
12.3 DC Characteristics....................................................................................................................................................... 71
12.3.1Current Rating.............................................................................................................................................................. 71
12.3.2 Pin Characteristics ....................................................................................................................................................... 79
12.4 AC Characteristics....................................................................................................................................................... 81
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 81
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 82
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 82
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)......................................... 83
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) .... 83
12.4.6 Reset Input Characteristics.......................................................................................................................................... 83
12.4.7 Power-on Reset Timing................................................................................................................................................ 84
12.4.8 GPIO Output Characteristics........................................................................................................................................ 84
12.4.9 External Bus Timing..................................................................................................................................................... 85
12.4.10 Base Timer Input Timing........................................................................................................................................... 96
12.4.11 CSIO/UART Timing .................................................................................................................................................. 97
12.4.12 External Input Timing.............................................................................................................................................. 130
12.4.13 Quadrature Position/Revolution Counter Timing .................................................................................................... 131
12.4.14 I2C Timing............................................................................................................................................................... 133
12.4.15 SD Card Interface Timing ....................................................................................................................................... 135
12.4.16 ETM Timing ............................................................................................................................................................ 137
12.4.17 JTAG Timing........................................................................................................................................................... 138
12.5 12-bit A/D Converter.................................................................................................................................................. 139
12.6 12-bit D/A Converter.................................................................................................................................................. 142
12.7 Low-Voltage Detection Characteristics...................................................................................................................... 143
12.7.1 Low-Voltage Detection Reset..................................................................................................................................... 143
12.7.2 Interrupt of Low-Voltage Detection............................................................................................................................. 143
12.8 MainFlash Memory Write/Erase Characteristics........................................................................................................ 144
12.9 WorkFlash Memory Write/Erase Characteristics....................................................................................................... 144
12.10 Standby Recovery Time ............................................................................................................................................ 145
12.10.1 Recovery cause: Interrupt/WKUP........................................................................................................................... 145
Document Number: 002-04918 Rev. *G
Page 5 of 160
CY9B160R Series
12.10.2 Recovery cause: Reset........................................................................................................................................... 147
13. Ordering Information .................................................................................................................................................... 149
14. Package Dimensions .................................................................................................................................................... 150
15. Major Changes .............................................................................................................................................................. 157
Document History............................................................................................................................................................... 158
Sales, Solutions, and Legal Information........................................................................................................................... 160
Document Number: 002-04918 Rev. *G
Page 6 of 160
CY9B160R Series
1. Product Lineup
Memory Size
Product name
MainFlash memory
WorkFlash memory
On-chip SRAM
SRAM0
MB9BF166M/N/R
512 Kbytes
32 Kbytes
64 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
MB9BF167M/N/R
768 Kbytes
32 Kbytes
96 Kbytes
48 Kbytes
24 Kbytes
24 Kbytes
MB9BF168M/N/R
1024 Kbytes
32 Kbytes
128 Kbytes
64 Kbytes
SRAM1
SRAM1
32 Kbytes
32 Kbytes
Function
MB9BF166M
MB9BF167M
MB9BF168M
MB9BF166N
MB9BF167N
MB9BF168N
MB9BF166R
MB9BF167R
MB9BF168R
Product name
Pin count
CPU
80
100/112
120/144
Cortex-M4F, MPU, NVIC 128ch.
Freq.
160 MHz
2.7 V to 5.5 V
8 ch.
Power supply voltage range
DMAC
DSTC
128 ch.
Addr:25-bit (Max),
R/W data: 8-/16-bit
(Max),
CS:9 (Max),
SRAM,
Addr:25-bit (Max),
R/W data: 8-/16-bit
(Max),
CS:9 (Max),
SRAM,
Addr:19-bit (Max),
R/W data: 8-bit
(Max),
CS:5 (Max),
SRAM,
External Bus Interface
NOR Flash,
SDRAM
NOR Flash,
NAND Flash, SDRAM
NOR Flash
Multi-function Serial Interface (UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
8 ch. (Max)
8 ch. (Max)
A/D activation compare
Input capture
Free-run timer
Output compare
Waveform generator
PPG
6 ch.
4 ch.
3 ch.
6 ch.
3 ch.
3 ch.
2 units (Max)
SD Card Interface
1 unit
QPRC
2 ch. (Max)
Dual Timer
1 unit
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog Timer
External Interrupts
I/O Ports
1 unit
1 unit
Yes
1 ch. (SW) + 1 ch. (HW)
16 pins (Max) + NMI × 1
63 pins (Max)
80 pins (Max)
24 ch. (3 units)
100 pins (Max)
12-bit A/D Converter
12-bit D/A Converter
16 ch. (3 units)
2 units (Max)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2 ch.
High-speed
Low-speed
4 MHz
100 kHz
SWJ-DP/ETM
Yes
Built-in CR
Debug Function
Unique ID
Notes:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics” for accuracy of
built-in CR.
−
Document Number: 002-04918 Rev. *G
Page 7 of 160
CY9B160R Series
2. Packages
MB9BF166M
MB9BF167M
MB9BF168M
MB9BF166N
MB9BF167N
MB9BF168N
MB9BF166R
MB9BF167R
MB9BF168R
Product name
Package
LQFP: LQH080 (0.5 mm pitch)
LQFP: LQJ080 (0.65 mm pitch)
QFP: PQH100 (0.65 mm pitch)
LQFP: LQI100 (0.5 mm pitch)
LQFP: LQM120 (0.5 mm pitch)
BGA: LDC112 (0.5 mm pitch)
BGA: LDC144 (0.5 mm pitch)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
: Supported
Note:
−
See “Package Dimensions” for detailed information on each package.
Document Number: 002-04918 Rev. *G
Page 8 of 160
CY9B160R Series
3. Pin Assignment
LQH080/LQJ080
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
60 VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
59 P21/AN17/SIN0_0/INT06_1
58 P22/CROUT_0/AN16/TIOB7_1/SOT0_0
57 P23/AN15/TIOA7_1/SCK0_0/RTO00_1
56 P1B/AN11/SCK4_1/IC02_1/MAD18_0
55 P1A/AN10/SOT4_1/IC01_1/MAD17_0
54 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
53 P18/AN08/SCK2_2/MAD15_0
52 AVRH
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2 13
P3A/TIOA0_1/AIN0_0/RTO00_0 14
51 AVRL
LQFP - 80
50 AVSS
49 AVCC
48 P17/AN07/SOT2_2/WKUP3/MAD14_0
47 P16/AN06/SIN2_2/INT14_1/MAD13_0
46 P15/AN05/SCK0_1/MAD12_0
45 P14/AN04/SOT0_1/IC03_2/MAD11_0
44 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
43 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
42 P11/AN01/SOT1_1/IC00_2/MAD08_0
41 P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0
P3B/TIOA1_1/BIN0_0/RTO01_0 15
P3C/TIOA2_1/ZIN0_0/RTO02_0 16
P3D/TIOA3_1/RTO03_0/MAD00_0 17
P3E/TIOA4_1/RTO04_0/MAD01_0 18
P3F/TIOA5_1/RTO05_0/MAD02_0 19
VSS 20
Note:
−
The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-04918 Rev. *G
Page 9 of 160
CY9B160R Series
LQI100
(TOP VIEW)
VCC
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
1
2
3
4
5
6
7
8
9
75 VSS
74 P20/AN18/AIN1_1/INT05_0/MAD24_0
73 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
72 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
71 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
70 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
69 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
68 P1C/AN12/CTS4_1/IC03_1/MAD19_0
67 P1B/AN11/SCK4_1/IC02_1/MAD18_0
66 P1A/AN10/SOT4_1/IC01_1/MAD17_0
65 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
64 P18/AN08/SCK2_2/MAD15_0
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12
P34/TIOB4_1/FRCK0_0/MADATA11_0 13
P35/TIOB5_1/IC03_0/INT08_1/MADATA12_0 14
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 15
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 16
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 17
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 18
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 19
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 20
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 21
P3D/TIOA3_1/RTO03_0/MAD00_0 22
LQFP - 100
63 AVRH
62 AVRL
61 AVSS
60 AVCC
59 P17/AN07/SOT2_2/WKUP3/MAD14_0
58 P16/AN06/SIN2_2/INT14_1/MAD13_0
57 P15/AN05/SCK0_1/MAD12_0
56 P14/AN04/SOT0_1/IC03_2/MAD11_0
55 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
54 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
53 P11/AN01/SOT1_1/IC00_2/MAD08_0
52 P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0
51 VCC
P3E/TIOA4_1/RTO04_0/MAD01_0 23
P3F/TIOA5_1/RTO05_0/MAD02_0 24
VSS 25
Note:
−
The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-04918 Rev. *G
Page 10 of 160
CY9B160R Series
LQM120
(TOP VIEW)
VCC
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
P57/SCK6_0/MADATA07_0
1
2
3
4
5
6
7
8
9
90 VSS
89 P20/AN18/AIN1_1/INT05_0/MAD24_0
88 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
87 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
86 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
85 P24/SIN2_1/RTO01_1/INT01_2
84 P25/TIOA5_0/SOT2_1/RTO02_1
83 P26/TIOB5_0/SCK2_1/RTO03_1
82 P27/TIOA6_2/RTO04_1/INT02_2
81 P1F/ADTG_4/TIOB6_2/RTO05_1
80 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
79 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
78 P1C/AN12/CTS4_1/IC03_1/MAD19_0
77 P1B/AN11/SCK4_1/IC02_1/MAD18_0
76 P1A/AN10/SOT4_1/IC01_1/MAD17_0
75 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
74 P18/AN08/SCK2_2/MAD15_0
P58/SIN4_2/AIN1_0/INT04_2/MADATA08_0 10
P59/SOT4_2/BIN1_0/INT07_1/MADATA09_0 11
P5A/SCK4_2/ZIN1_0/MADATA10_0 12
P5B/CTS4_2/MADATA11_0 13
LQFP - 120
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_0 14
P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_0 15
P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_0 16
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_0 17
P34/TIOB4_1/FRCK0_0/MNALE_0 18
73 AVRH
P35/TIOB5_1/IC03_0/INT08_1/MNCLE_0 19
P36/SIN5_2/IC02_0/INT09_1/MNWEX_0 20
P37/SOT5_2/IC01_0/INT05_2/MNREX_0 21
P38/SCK5_2/IC00_0/INT06_2 22
72 AVRL
71 AVSS
70 AVCC
69 P17/AN07/SOT2_2/WKUP3/MAD14_0
68 P16/AN06/SIN2_2/INT14_1/MAD13_0
67 P15/AN05/SCK0_1/MAD12_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 23
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 24
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 25
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 26
P3D/TIOA3_1/RTO03_0/MAD00_0 27
66 P14/AN04/SOT0_1/IC03_2/MAD11_0
65 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
64 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
63 P11/AN01/SOT1_1/IC00_2/MAD08_0
62 P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0
61 VCC
P3E/TIOA4_1/RTO04_0/MAD01_0 28
P3F/TIOA5_1/RTO05_0/MAD02_0 29
VSS 30
Note:
−
The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-04918 Rev. *G
Page 11 of 160
CY9B160R Series
PQH100
(TOP VIEW)
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 81
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 82
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 83
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 84
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 85
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 86
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 87
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 88
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 89
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 90
P34/TIOB4_1/FRCK0_0/MADATA11_0 91
50 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
49 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
48 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
47 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
46 P1C/AN12/CTS4_1/IC03_1/MAD19_0
45 P1B/AN11/SCK4_1/IC02_1/MAD18_0
44 P1A/AN10/SOT4_1/IC01_1/MAD17_0
43 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
42 P18/AN08/SCK2_2/MAD15_0
QFP - 100
41 AVRH
40 AVRL
P35/TIOB5_1/IC03_0/INT08_1/MADATA12_0 92
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 93
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 94
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 95
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 96
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 97
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 98
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 99
39 AVSS
38 AVCC
37 P17/AN07/SOT2_2/WKUP3/MAD14_0
36 P16/AN06/SIN2_2/INT14_1/MAD13_0
35 P15/AN05/SCK0_1/MAD12_0
34 P14/AN04/SOT0_1/IC03_2/MAD11_0
33 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
32 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
31 P11/AN01/SOT1_1/IC00_2/MAD08_0
P3D/TIOA3_1/RTO03_0/MAD00_0 100
Note:
−
The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-04918 Rev. *G
Page 12 of 160
CY9B160R Series
LDC112
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
TCK/
SWCLK
A
B
C
D
E
F
VSS
VCC
P50
P53
P55
P31
P34
VSS
P39
P3C
P3E
VCC
VSS
P81
VSS
P51
P54
P56
P32
P35
P37
P3A
P3D
P3F
VSS
P40
P80
P60
P52
VCC
P61
VSS
VSS
AN21
AN22
AN23
P0A
AN19
AN20
P0B
P0C
VSS
P0D
VSS
P0E
VSS
VSS
VCC
AN17
AN15
TMS/
SWDIO
P62 TRSTX
TDO/
SWO
P63
TDI
AN18
AN16
index
P30
P33
P36
P38
P3B
AN14
AN12
AN10
AN08
AN06
AN13 AVRH
AN11 AVRL
AN09 AVSS
AN07 AVCC
G
H
J
AN05
AN03
AN01
VSS
X1
AN04
AN02
AN00
VCC
VSS
K
L
P43
P42
P41
P45
VSS
X0A
P48
INITX
X1A
P4B
P49
VSS
P4C
VCC
VBAT
P4E
P4D
C
VSS
MD0
X0
M
N
P44
MD1
VSS
VSS
Note:
−
The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-04918 Rev. *G
Page 13 of 160
CY9B160R Series
LDC144
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
B
C
D
E
F
VSS
VCC
P50
P52
P55
P59
P31
P35
P39
VSS
P3F
VCC
VSS
P81
VSS
P51
P53
P56
P5A
P32
P36
P3A
P3D
P41
VSS
P40
P80
P60
VSS
P54
P57
P5B
P33
P37
P3B
P3E
VSS
P43
P42
VCC
P61
P62
VSS
P58
P30
P34
P38
P3C
VSS
P44
VSS
INITX
VSS
P63
P64
P66
P67
P68
VSS
TCK/
VSS
TDO/
AN21
AN20
AN19
P0A
VSS
P0B
P0D
VSS
P24
P0C
VSS
VSS
AN17
P25
VCC
VSS
VSS
P0E
SWCLK SWO
TDI
AN23
AN22
AN18
AN16
P26
VSS
AN15
P27
TMS/
SWDIO
P65 TRSTX
index
P1F
AN14
AN10
AN07
AN04
AN02
VSS
MD0
X0
AN13
AN12
G
H
J
AN11
AN08
AN05
VSS
P74
AN09 AVRH
AN06 AVRL
AN03 AVSS
AN01 AVCC
K
L
P45
VSS
X1A
X0A
P49
P48
VSS
VSS
P4C
P4B
P70
P4E
P4D
C
P72
P71
VCC
VSS
AN00
VSS
X1
VSS
VCC
VSS
M
N
VSS
VBAT
P73
MD1
Note:
−
The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-04918 Rev. *G
Page 14 of 160
CY9B160R Series
4. Pin Description
List of pin numbers
The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)
to select the pin.
Pin No
LQFP80
I/O circuit
type
Pin state
type
Pin Name
VCC
LQFP120
LQFP100
QFP100
79
BGA112
B1
BGA144
B1
1
2
1
2
1
-
-
P50
CTS4_0
AIN0_2
2
3
4
5
6
7
80
81
82
83
84
85
C1
C2
C3
D1
D2
E1
C1
C2
D1
D2
D3
E1
E
E
E
E
E
E
K
K
I
RTO10_0
(PPG10_0)
INT00_0
MADATA00_0
P51
RTS4_0
BIN0_2
3
4
5
6
7
3
4
5
6
7
RTO11_0
(PPG10_0)
INT01_0
MADATA01_0
P52
SCK4_0
(SCL4_0)
ZIN0_2
RTO12_0
(PPG12_0)
MADATA02_0
P53
TIOA1_2
SOT4_0
(SDA4_0)
I
RTO13_0
(PPG12_0)
MADATA03_0
P54
TIOB1_2
SIN4_0
K
RTO14_0
(PPG14_0)
INT02_0
MADATA04_0
P55
ADTG_1
SIN6_0
K
RTO15_0
(PPG14_0)
INT07_2
MADATA05_0
Document Number: 002-04918 Rev. *G
Page 15 of 160
CY9B160R Series
Pin No
LQFP80
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
QFP100
BGA112
BGA144
P56
SOT6_0
(SDA6_0)
8
9
8
8
86
E2
E2
E
K
DTTI1X_0
INT08_2
MADATA06_0
P57
SCK6_0
(SCL6_0)
-
-
-
-
-
-
-
-
E3
E4
E
E
I
MADATA07_0
P58
SIN4_2
10
11
AIN1_0
K
INT04_2
MADATA08_0
P59
SOT4_2
(SDA4_2)
-
-
-
-
F1
E
K
BIN1_0
INT07_1
MADATA09_0
P5A
SCK4_2
(SCL4_2)
12
13
14
-
-
-
-
-
-
-
-
F2
F3
F4
E
E
I
I
ZIN1_0
MADATA10_0
P5B
CTS4_2
MADATA11_0
P30
TIOB0_1
RTS4_2
INT15_2
9
-
9
87
E3
E
Q
WKUP1
-
14
-
F4
MADATA07_0
MADATA12_0
P31
-
-
-
TIOB1_1
15
G1
10
-
10
-
88
-
F1
-
SIN3_1
I
K
INT09_2
-
-
MADATA08_0
MADATA13_0
15
G1
Document Number: 002-04918 Rev. *G
Page 16 of 160
CY9B160R Series
Pin No
LQFP80
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
QFP100
BGA112
BGA144
P32
TIOB2_1
16
G2
SOT3_1
(SDA3_1)
11
11
-
89
F2
N
K
INT10_1
-
16
-
MADATA09_0
MADATA14_0
P33
-
-
-
G2
ADTG_6
TIOB3_1
17
G3
12
12
90
F3
SCK3_1
N
K
(SCL3_1)
INT04_0
-
17
-
MADATA10_0
MADATA15_0
P34
-
-
-
-
-
-
G3
18
G4
TIOB4_1
13
-
91
-
G1
-
E
E
I
FRCK0_0
MADATA11_0
MNALE_0
P35
-
18
-
G4
TIOB5_1
IC03_0
19
H1
14
-
-
-
92
-
G2
-
K
INT08_1
-
19
-
H1
MADATA12_0
MNCLE_0
Document Number: 002-04918 Rev. *G
Page 17 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P36
SIN5_2
IC02_0
20
H2
15
-
-
93
G3
E
K
K
INT09_1
MADATA13_0
MNWEX_0
P37
-
20
-
H2
-
-
-
SOT5_2
(SDA5_2)
21
H3
16
-
-
-
-
94
-
H2
-
E
IC01_0
INT05_2
MADATA14_0
MNREX_0
P38
-
21
-
H3
SCK5_2
(SCL5_2)
22
-
H4
-
17
95
H3
E
K
IC00_0
INT06_2
MADATA15_0
P39
ADTG_2
DTTI0X_0
RTCCO_2
SUBOUT_2
MSDCLK_0
P3A
13
-
23
24
25
18
19
20
96
97
98
J1
J2
J3
J1
J2
J3
L
I
TIOA0_1
AIN0_0
14
-
G
G
I
RTO00_0
(PPG00_0)
MSDCKE_0
P3B
TIOA1_1
BIN0_0
15
-
I
RTO01_0
(PPG00_0)
MRASX_0
Document Number: 002-04918 Rev. *G
Page 18 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P3C
TIOA2_1
ZIN0_0
16
26
21
99
K1
J4
G
I
RTO02_0
(PPG02_0)
-
MCASX_0
P3D
TIOA3_1
27
28
29
22
23
24
17
100
K2
L1
L2
K2
K3
L1
G
G
G
I
I
I
RTO03_0
(PPG02_0)
MAD00_0
P3E
TIOA4_1
18
19
1
RTO04_0
(PPG04_0)
MAD01_0
P3F
TIOA5_1
2
RTO05_0
(PPG04_0)
MAD02_0
VSS
30
31
25
26
20
-
3
4
N1
M1
N1
M1
-
-
-
-
VCC
P40
TIOA0_0
32
33
34
27
28
29
-
-
-
5
6
7
N2
N3
M3
N2
L2
N3
G
G
G
K
K
I
RTO10_1
(PPG10_1)
INT12_1
P41
TIOA1_0
RTO11_1
(PPG10_1)
INT13_1
P42
TIOA2_0
RTO12_1
(PPG12_1)
MSDWEX_0
P43
ADTG_7
TIOA3_0
35
30
-
8
L3
M3
G
I
RTO13_1
(PPG12_1)
MCSX8_0
Document Number: 002-04918 Rev. *G
Page 19 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P44
TIOA4_0
36
31
21
9
M4
L4
R
J
J
RTO14_1
(PPG14_1)
DA0
P45
TIOB0_0
37
32
22
10
L5
K5
R
RTO15_1
(PPG14_1)
DA1
38
39
33
34
23
24
11
12
M6
N5
N4
N5
INITX
P46
B
P
C
S
X0A
P47
40
41
42
35
36
37
25
26
27
13
14
15
N6
L6
M5
L6
Q
O
O
T
X1A
P48
U
U
VREGCTL
P49
M7
K6
VWAKEUP
VBAT
C
43
44
45
46
38
39
40
41
28
29
30
31
16
17
18
19
N8
N7
N8
N9
M9
-
-
-
-
-
-
-
-
N9
N10
M8
VSS
VCC
P4B
TIOB1_0
SCS7_1
MAD03_0
P4C
47
42
32
20
L7
L8
L7
E
I
TIOB2_0
SCK7_1
(SCL7_1)
48
43
33
21
K7
N
I
AIN1_2
MAD04_0
P4D
TIOB3_0
SOT7_1
(SDA7_1)
49
44
34
22
M9
M8
N
K
BIN1_2
INT13_2
MAD05_0
P4E
TIOB4_0
SIN7_1
ZIN1_2
50
45
35
23
L9
L8
I
Q
FRCK1_1
INT11_1
WKUP2
MAD06_0
Document Number: 002-04918 Rev. *G
Page 20 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P70
TIOA4_2
AIN0_1
IC13_1
P71
51
-
-
-
-
-
-
-
K8
E
I
TIOB4_2
BIN0_1
IC12_1
INT15_1
P72
52
53
-
L9
E
E
K
TIOA6_0
SIN2_0
ZIN0_1
IC11_1
INT14_2
P73
-
-
-
-
K9
K
TIOB6_0
SOT2_0
(SDA2_0)
54
55
-
-
-
-
-
-
-
-
M10
L10
E
E
K
IC10_1
INT03_2
P74
SCK2_0
(SCL2_0)
I
DTTI1X_1
PE0
56
57
58
46
47
48
36
37
38
24
25
26
M10
M11
N11
N10
M11
N11
C
J
E
D
A
MD1
MD0
PE2
A
X0
PE3
59
49
39
27
N12
N12
A
B
X1
60
61
50
51
40
-
28
29
N13
M13
N13
M13
VSS
-
-
-
-
VCC
P10
AN00
SIN1_1
FRCK0_2
INT02_1
MAD07_0
P11
62
63
52
53
41
42
30
31
L13
L12
L12
K12
F
F
M
AN01
SOT1_1
(SDA1_1)
L
IC00_2
MAD08_0
Document Number: 002-04918 Rev. *G
Page 21 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P12
AN02
SCK1_1
(SCL1_1)
64
54
43
32
K13
K11
F
L
IC01_2
RTCCO_1
SUBOUT_1
MAD09_0
P13
AN03
SIN0_1
IC02_2
INT03_1
MAD10_0
P14
65
66
55
56
44
45
33
34
K12
J13
J12
J11
F
F
M
AN04
SOT0_1
(SDA0_1)
L
IC03_2
MAD11_0
P15
AN05
67
68
57
58
46
47
35
36
J12
J11
J10
F
F
L
SCK0_1
(SCL0_1)
MAD12_0
P16
AN06
H12
SIN2_2
INT14_1
MAD13_0
P17
M
AN07
SOT2_2
(SDA2_2)
69
59
48
37
H12
H11
F
P
WKUP3
MAD14_0
AVCC
AVSS
AVRL
70
71
72
73
60
61
62
63
49
50
51
52
38
39
40
41
H13
G13
F13
E13
K13
J13
H13
G13
-
-
-
-
-
-
-
-
AVRH
P18
AN08
74
64
53
42
H11
H10
F
L
SCK2_2
(SCL2_2)
MAD15_0
Document Number: 002-04918 Rev. *G
Page 22 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P19
AN09
SIN4_1
IC00_1
INT05_1
MAD16_0
P1A
75
65
54
43
G12
G12
F
M
AN10
SOT4_1
(SDA4_1)
76
77
66
67
55
56
44
45
G11
F12
G11
G10
M
M
L
IC01_1
MAD17_0
P1B
AN11
SCK4_1
(SCL4_1)
L
IC02_1
MAD18_0
P1C
AN12
78
79
80
81
82
68
69
70
-
-
-
-
-
-
46
47
48
-
F11
E12
E11
-
F13
F12
F11
F10
E13
CTS4_1
IC03_1
MAD19_0
P1D
F
F
F
E
E
L
L
L
I
AN13
RTS4_1
DTTI0X_1
MAD20_0
P1E
AN14
ADTG_5
FRCK0_1
MAD21_0
P1F
ADTG_4
TIOB6_2
RTO05_1
(PPG04_1)
P27
TIOA6_2
-
-
-
K
RTO04_1
(PPG04_1)
INT02_2
Document Number: 002-04918 Rev. *G
Page 23 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P26
TIOB5_0
SCK2_1
(SCL2_1)
83
-
-
-
-
E12
E
I
RTO03_1
(PPG02_1)
P25
TIOA5_0
SOT2_1
(SDA2_1)
84
85
-
-
-
-
-
-
-
-
E11
E10
E
E
I
RTO02_1
(PPG02_1)
P24
SIN2_1
K
RTO01_1
(PPG00_1)
INT01_2
P23
AN15
TIOA7_1
57
SCK0_0
(SCL0_0)
86
71
49
D13
D13
F
L
RTO00_1
(PPG00_1)
-
MAD22_0
P22
CROUT_0
AN16
58
87
72
50
D12
D12
TIOB7_1
F
L
SOT0_0
(SDA0_0)
-
ZIN1_1
P21
59
AN17
SIN0_0
BIN1_1
INT06_1
MAD23_0
P20
88
89
73
74
51
52
C13
C12
D11
C12
F
F
M
M
-
59
-
AN18
-
AIN1_1
INT05_0
MAD24_0
VSS
90
91
75
76
60
61
53
54
A13
B13
A13
A12
-
-
-
-
VCC
Document Number: 002-04918 Rev. *G
Page 24 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P0E
TIOB5_2
SCS6_1
IC13_0
92
77
62
55
A12
B13
L
I
S_CLK_0
MDQM1_0
P0D
TIOA5_2
SCK6_1
(SCL6_1)
93
78
63
56
B11
C10
L
I
IC12_0
S_CMD_0
MDQM0_0
P0C
TIOA6_1
SOT6_1
(SDA6_1)
94
79
64
57
B10
A11
L
I
IC11_0
S_DATA1_0
MALE_0
P0B
TIOB6_1
SIN6_1
95
80
65
58
A10
B10
IC10_0
L
K
INT00_1
S_DATA0_0
MCSX0_0
P0A
SIN1_0
FRCK1_0
INT12_2
S_DATA3_0
MCSX1_0
P09
96
81
66
59
A9
D9
L
K
67
-
AN19
TRACED0
TIOA3_2
97
82
60
B9
C9
M
N
SOT1_0
(SDA1_0)
67
S_DATA2_0
MCSX5_0
P08
AN20
TRACED1
TIOB3_2
98
83
-
61
C9
B9
F
N
SCK1_0
(SCL1_0)
MCSX4_0
Document Number: 002-04918 Rev. *G
Page 25 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P07
AN21
TRACED2
TIOA0_2
99
84
-
-
-
62
A8
A9
F
N
N
O
SCK7_0
(SCL7_0)
MCLKOUT_0
P06
AN22
TRACED3
TIOB0_2
100
85
63
B8
D8
F
SOT7_0
(SDA7_0)
MCSX3_0
P05
AN23
ADTG_0
TRACECLK
SIN7_0
INT01_1
MCSX2_0
P04
101
86
64
C8
C8
F
102
103
104
105
87
88
89
90
68
69
70
71
65
66
67
68
C7
B7
C6
A6
B8
D7
C7
B7
TDO
E
E
E
E
G
G
H
G
SWO
P03
TMS
SWDIO
P02
TDI
MCSX6_0
P01
TCK
SWCLK
P00
106
107
91
92
72
-
69
70
B6
A5
D6
A7
TRSTX
MCSX7_0
VSS
E
-
H
-
P68
TIOB7_2
108
109
-
-
-
-
-
-
-
-
C6
B6
E
E
K
SCK3_0
(SCL3_0)
INT00_2
P67
TIOA7_2
I
SOT3_0
(SDA3_0)
Document Number: 002-04918 Rev. *G
Page 26 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
I/O circuit
type
Pin state
type
Pin Name
LQFP120
LQFP100
BGA112
BGA144
P66
ADTG_8
SIN3_0
INT11_2
P65
110
-
-
-
-
-
-
-
-
A6
E
K
I
TIOB7_0
111
112
D5
C5
E
E
SCK5_1
(SCL5_1)
P64
TIOA7_0
-
-
-
-
K
K
SOT5_1
(SDA5_1)
INT10_2
P63
93
-
73
-
71
-
C5
-
CROUT_1
SIN5_1
INT03_0
S_CD_0
MWEX_0
P62
113
114
115
B5
C4
B4
E
93
73
71
C5
ADTG_3
SIN5_0
INT04_1
S_WP_0
MOEX_0
P61
94
74
72
B5
I
K
TIOB2_2
SOT5_0
(SDA5_0)
95
75
73
B4
E
I
RTCCO_0
SUBOUT_0
P60
TIOA2_2
SCK5_0
(SCL5_0)
116
96
76
74
B3
B3
I
F
NMIX
WKUP0
MRDY_0
VCC
117
118
119
97
98
99
77
78
79
75
76
77
A4
A3
A2
A4
A3
A2
-
-
P80
H
H
R
R
P81
Document Number: 002-04918 Rev. *G
Page 27 of 160
CY9B160R Series
Pin No
LQFP80 QFP100
78
I/O circuit
type
Pin state
type
Pin Name
LQFP120
120
LQFP100
BGA112
A1
BGA144
A1
100
80
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A7
A5
B2
A8
B12
A10
B2
C11
H1
B11
B12
C3
N4
M5
N7
C11
C13
D4
L11
A11
M12
D10
K1
M2
VSS
-
-
-
-
-
-
-
-
-
-
-
-
K4
K10
L3
L5
L11
L13
M2
M4
M6
M7
M12
N6
Document Number: 002-04918 Rev. *G
Page 28 of 160
CY9B160R Series
List of pin functions
The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)
to select the pin.
Pin No
LQFP LQFP LQFP QFP
Pin
Pin name
ADTG_0
Function description
BGA
112
C8
E1
J1
BGA
144
C8
E1
J1
function
120
101
7
100
86
80
100
64
-
7
13
74
-
-
12
-
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
7
85
96
72
-
48
90
8
23
114
81
80
17
35
110
62
63
64
65
66
67
68
69
74
75
76
77
78
79
80
86
87
88
89
97
98
99
100
101
32
24
99
37
14
100
33
25
5
18
94
-
70
12
30
-
B5
C4
A/D converter external trigger input pin
-
F10
F11
G3
M3
A6
E11
F3
L3
-
-
-
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
71
72
73
74
82
83
84
85
86
27
19
84
32
9
85
28
20
5
42
10
6
29
21
96
43
11
95
41
42
43
44
45
46
47
48
53
54
55
56
-
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
49
50
51
52
60
61
62
63
64
5
97
62
10
87
63
6
98
83
20
88
84
7
L13
L12
K13
K12
J13
J12
J11
H12
H11
G12
G11
F12
F11
E12
E11
D13
D12
C13
C12
B9
C9
A8
B8
C8
N2
J2
A8
L5
E3
B8
L12
K12
K11
J12
J11
J10
H12
H11
H10
G12
G11
G10
F13
F12
F11
D13
D12
D11
C12
C9
B9
A9
D8
C8
N2
J2
A9
K5
F4
D8
L2
J3
D2
L7
G1
D3
N3
ADC
A/D converter analog input pin.
Anxx describes ADC ch.xx.
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
-
-
57
58
59
-
67
-
-
-
-
-
14
-
22
9
-
-
15
5
32
10
6
AN21
AN22
AN23
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base Timer
0
N3
J3
D1
L7
Base Timer
1
47
15
6
34
26
116
48
16
115
F1
D2
M3
K1
B3
L8
-
16
76
33
11
75
99
74
21
89
73
J4
B3
K7
G2
B4
Base Timer
2
F2
B4
Document Number: 002-04918 Rev. *G
Page 29 of 160
CY9B160R Series
Pin No
Pin
function
Pin name
TIOA3_0
Function description
LQFP LQFP LQFP QFP
120 100 80 100
35 30
BGA
112
L3
BGA
144
M3
-
8
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
SWCLK
SWDIO
Base timer ch.3 TIOA pin
27
97
49
17
98
36
28
51
50
18
52
84
29
93
83
19
92
53
94
82
54
95
81
112
86
109
111
87
108
105
22
82
44
12
83
31
23
-
17
67
34
12
-
21
18
-
100
60
22
90
61
9
1
-
23
91
-
K2
B9
M9
F3
C9
M4
L1
-
K2
C9
M8
G3
B9
L4
K3
K8
L8
G4
L9
E11
L1
C10
E12
H1
B13
K9
A11
E13
M10
B10
F10
C5
D13
B6
D5
D12
C6
B7
D7
B8
Base Timer
3
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base Timer
4
45
13
-
35
-
-
L9
G1
-
-
-
-
2
-
24
78
-
14
77
-
79
-
-
80
-
-
71
-
-
19
63
-
-
62
-
64
-
-
65
-
-
57
-
-
58
-
71
69
68
71
70
68
69
-
L2
B11
-
G2
A12
-
B10
-
-
A10
-
-
D13
-
-
56
-
92
55
-
57
-
-
58
-
-
49
-
-
Base Timer
5
Base Timer
6
Base Timer
7
Base timer ch.7 TIOB pin
72
-
50
-
D12
-
Serial wire debug interface clock input pin
Serial wire debug interface data input / output pin 103
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
JTAG test mode state input/output pin
Trace CLK output pin of ETM
90
88
87
90
89
87
88
86
82
83
84
85
91
68
66
65
68
67
65
66
64
60
61
62
63
69
A6
B7
C7
A6
C6
C7
B7
C8
B9
C9
A8
B8
B6
SWO
TCK
TDI
TDO
102
105
104
102
103
101
97
98
99
100
106
B7
C7
B8
D7
C8
C9
B9
A9
D8
D6
Debugger
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
-
-
-
-
Trace data output pin of ETM
JTAG test reset Input pin
72
Document Number: 002-04918 Rev. *G
Page 30 of 160
CY9B160R Series
Pin No
LQFP LQFP LQFP QFP
Pin
function
Pin name
MAD00_0
Function description
BGA
112
K2
BGA
144
K2
120
27
100
22
80
17
100
100
1
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
28
29
47
48
49
50
62
63
64
65
66
67
68
69
74
75
76
77
78
79
80
86
88
89
23
24
42
43
44
45
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
71
73
74
18
19
32
33
34
35
41
42
43
44
45
46
47
48
53
54
55
56
-
L1
L2
L7
L8
M9
L9
K3
L1
L7
K7
M8
L8
2
20
21
22
23
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
49
51
52
L13
L12
K13
K12
J13
J12
J11
H12
H11
G12
G11
F12
F11
E12
E11
D13
C13
C12
L12
K12
K11
J12
J11
J10
H12
H11
H10
G12
G11
G10
F13
F12
F11
D13
D11
C12
External
Bus
External bus interface address bus
-
-
-
-
-
Document Number: 002-04918 Rev. *G
Page 31 of 160
CY9B160R Series
Pin No
Pin
function
Pin name
MCSX0_0
Function description
LQFP LQFP LQFP QFP
120 100 80 100
95 80 65 58
BGA
112
BGA
144
B10
A10
A9
C8
B8
C9
B9
C6
B6
L3
C1
C2
C3
D1
D2
E1
E2
E3
F1
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MCSX8_0
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MDQM0_0
96
101
100
98
97
104
106
35
2
3
4
5
6
81
86
85
83
82
89
91
30
2
3
4
5
6
66
-
-
59
64
63
61
60
67
69
8
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
56
55
D9
C8
D8
B9
C9
C7
D6
M3
C1
C2
D1
D2
D3
E1
E2
E3
E4
F1
External bus interface chip select output pin
-
67
70
72
-
2
3
4
5
6
7
8
9
10
11
12
-
-
-
-
-
7
8
9
7
8
9
External bus interface data bus
(Address / data multiplex bus)
10
11
12
13
14
15
16
17
93
92
10
11
12
13
14
15
16
17
78
77
F2
F3
F2
G1
G2
G3
H2
H3
B11
A12
F3
F4
External
Bus
G1
G2
G3
C10
B13
63
62
External bus interface byte mask signal output
pin
MDQM1_0
External bus interface Address Latch enable
output signal for multiplex
MALE_0
94
79
64
57
B10
A11
MRDY_0
MCLKOUT_0
External bus interface external RDY input signal
External bus interface external clock output pin
External bus interface ALE signal to control
NAND Flash output pin
External bus interface CLE signal to control
NAND Flash output pin
External bus interface read enable signal to
control NAND Flash
External bus interface write enable signal to
control NAND Flash
External bus interface read enable signal for
SRAM
External bus interface write enable signal for
SRAM
SDRAM interface
SDRAM clock output pin
SDRAM interface
SDRAM clock enable pin
SDRAM interface
SDRAM row address strobe pin
SDRAM interface
SDRAM column address strobe pin
SDRAM interface
SDRAM write enable pin
116
99
96
84
76
-
74
62
B3
A8
B3
A9
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MOEX_0
18
19
21
20
114
113
23
24
25
26
34
-
-
-
-
G4
H1
H3
H2
C4
B5
J1
-
-
-
-
-
-
-
-
-
-
-
-
94
93
18
19
20
21
29
74
73
-
72
71
96
97
98
99
7
B5
C5
J1
J2
J3
K1
M3
MWEX_0
MSDCLK_0
MSDCKE_0
MRASX_0
MCASX_0
MSDWEX_0
-
J2
External
Bus
-
J3
-
J4
-
N3
Document Number: 002-04918 Rev. *G
Page 32 of 160
CY9B160R Series
Pin No
Pin
Pin name
INT00_0
Function description
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
LQFP LQFP LQFP QFP
120 100 80 100
80
BGA
112
C1
BGA
144
C1
function
2
2
80
-
3
86
-
6
52
-
93
55
-
12
94
-
74
65
16
73
17
-
7
14
8
15
10
11
-
45
-
27
81
28
44
58
-
2
65
-
3
-
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_1
INT07_2
INT08_1
INT08_2
INT09_1
INT09_2
INT10_1
INT10_2
INT11_1
INT11_2
INT12_1
INT12_2
INT13_1
INT13_2
INT14_1
INT14_2
INT15_1
INT15_2
NMIX
95
108
3
101
85
6
58
-
81
64
-
84
30
-
71
33
-
90
72
-
52
43
94
51
95
-
85
92
86
93
88
89
-
A10
-
C2
C8
-
D2
L13
-
C5
K12
-
B10
C6
C2
C8
E10
D3
L12
E13
B5
J12
M10
G3
C4
E4
-
6
62
82
113
65
54
17
114
10
89
75
21
88
22
11
7
41
-
73
44
-
12
74
-
-
54
-
59
-
-
7
-
8
-
10
11
-
35
-
-
66
-
F3
B5
-
C12
G12
H2
C13
H3
-
C12
G12
H3
D11
H4
F1
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External
Interrupt
E1
G2
E2
G3
F1
F2
-
E1
H1
E2
H2
G1
G2
C5
L8
19
8
20
15
16
112
50
110
32
96
33
49
68
53
52
14
116
23
-
5
59
6
22
36
-
L9
-
A6
N2
A9
N3
M9
J11
-
N2
D9
L2
M8
H12
K9
34
47
-
-
9
-
9
96
-
87
74
-
L9
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
E3
B3
F4
B3
76
Document Number: 002-04918 Rev. *G
Page 33 of 160
CY9B160R Series
Pin No
Pin
Pin name
Function description
LQFP LQFP LQFP QFP
BGA
112
B6
BGA
144
D6
function
120
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
62
63
64
65
66
67
68
69
74
75
76
77
78
79
80
81
89
88
87
86
85
100
91
80
72
100
69
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
90
89
88
87
86
85
84
83
82
81
80
79
78
77
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
-
71
70
69
68
-
-
-
-
67
66
65
64
63
62
41
42
43
44
45
46
47
48
53
54
55
56
-
68
67
66
65
64
63
62
61
60
59
58
57
56
55
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
-
A6
B7
C6
C7
B7
D7
C7
B8
C8
C8
B8
D8
General-purpose I/O port 0
A8
A9
C9
B9
B9
C9
A9
D9
A10
B10
B11
A12
L13
L12
K13
K12
J13
J12
J11
H12
H11
G12
G11
F12
F11
E12
E11
-
B10
A11
C10
B13
L12
K12
K11
J12
J11
J10
H12
H11
H10
G12
G11
G10
F13
F12
F11
F10
C12
D11
D12
D13
E10
E11
E12
E13
GPIO
General-purpose I/O port 1
-
-
-
-
59
58
57
-
-
-
74
73
72
71
-
-
-
-
52
51
50
49
-
-
-
-
C12
C13
D12
D13
-
-
-
-
General-purpose I/O port 2
84
83
82
-
Document Number: 002-04918 Rev. *G
Page 34 of 160
CY9B160R Series
Pin No
Pin
function
Pin name
Function description
LQFP LQFP LQFP QFP
120 100 80 100
14 87
BGA
112
E3
BGA
144
F4
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
9
9
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
39
40
41
42
47
48
49
50
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
34
35
36
37
42
43
44
45
2
10
11
12
-
-
-
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
12
13
14
15
20
21
22
23
80
81
82
83
84
85
86
-
F1
F2
F3
G1
G2
G3
H2
H3
J1
J2
J3
K1
K2
L1
L2
N2
N3
M3
L3
M4
L5
N5
N6
L6
M7
L7
L8
M9
L9
C1
C2
C3
D1
D2
E1
E2
-
G1
G2
G3
G4
H1
H2
H3
H4
J1
-
-
General-purpose I/O port 3
13
14
15
16
17
18
19
-
J2
J3
J4
K2
K3
L1
N2
L2
N3
M3
L4
K5
N5
M5
L6
K6
L7
K7
M8
L8
C1
C2
D1
D2
D3
E1
E2
E3
E4
F1
F2
F3
-
-
-
21
22
24
25
26
27
32
33
34
35
2
3
4
5
6
7
8
-
-
GPIO
General-purpose I/O port 4
3
4
5
6
7
8
9
10
11
12
13
3
4
5
6
7
8
-
-
General-purpose I/O port 5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Document Number: 002-04918 Rev. *G
Page 35 of 160
CY9B160R Series
Pin No
Pin
Pin name
Function description
LQFP LQFP LQFP QFP
BGA
112
B3
BGA
144
B3
function
120
116
115
114
113
112
111
110
109
108
51
52
53
54
55
118
119
56
58
59
100
96
95
94
93
-
-
-
-
-
80
76
100
74
P60
P61
P62
P63
P64
P65
P66
P67
P68
P70
P71
P72
P73
P74
P80
P81
PE0
PE2
PE3
75
74
73
-
-
-
-
-
-
-
-
-
-
78
79
36
38
39
59
44
73
72
71
-
-
-
-
-
-
-
-
-
-
76
77
24
26
27
51
33
B4
B4
B5
C4
C5
B5
General-purpose I/O port 6
-
C5
-
D5
-
A6
-
B6
-
C6
GPIO
-
-
-
-
-
K8
-
L9
General-purpose I/O port 7
-
K9
-
-
M10
L10
A3
-
98
99
46
48
49
73
55
A3
A2
M10
N11
N12
C13
K12
General-purpose I/O port 8
A2
N10
N11
N12
D11
J12
General-purpose I/O port E
SIN0_0
SIN0_1
88
65
Multi-function serial interface ch.0 input pin
SOT0_0
(SDA0_0)
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA0 when it is used in an I2C (operation mode
4).
87
66
86
67
72
56
71
57
58
45
57
46
50
34
49
35
D12
J13
D13
J12
D12
J11
D13
J10
SOT0_1
(SDA0_1)
Multi- function
Serial
0
SCK0_0
(SCL0_0)
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SCL0 when it is used in an I2C (operation mode
4).
SCK0_1
(SCL0_1)
SIN1_0
SIN1_1
96
62
81
52
66
41
59
30
A9
L13
D9
L12
Multi-function serial interface ch.1 input pin
SOT1_0
(SDA1_0)
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA1 when it is used in an I2C (operation mode
4).
97
63
98
64
82
53
83
54
67
42
-
60
31
61
32
B9
C9
SOT1_1
(SDA1_1)
Multi- function
Serial
1
L12
C9
K12
B9
SCK1_0
(SCL1_0)
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a
CSIO (operation modes 4) and as SCL1 when it
is used in an I2C (operation mode 4).
SCK1_1
(SCL1_1)
43
K13
K11
Document Number: 002-04918 Rev. *G
Page 36 of 160
CY9B160R Series
Pin No
Pin
function
Pin name
SIN2_0
SIN2_1
SIN2_2
Function description
LQFP LQFP LQFP QFP
120 100 80 100
53
BGA
112
BGA
144
K9
-
-
58
-
-
47
-
-
36
-
-
Multi-function serial interface ch.2 input pin
85
68
E10
H12
J11
SOT2_0
(SDA2_0)
SOT2_1
54
-
-
-
-
M10
E11
H11
L10
E12
H10
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as 84
-
-
-
-
Multi- function (SDA2_1)
SDA2 when it is used in an I2C (operation mode
4).
Serial
2
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
69
55
83
74
59
-
48
-
37
-
H12
-
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a
CSIO (operation modes 2) and as SCL2 when it
is used in an I2C (operation mode 4).
-
-
-
-
64
53
42
H11
110
15
-
10
-
10
-
88
-
F1
A6
G1
Multi-function serial interface ch.3 input pin
SIN3_1
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA3 when it is used in an I2C (operation mode
4).
SOT3_0
(SDA3_0)
109
-
-
-
-
B6
Multi- function
Serial
3
SOT3_1
(SDA3_1)
16
11
11
89
F2
G2
SCK3_0
(SCL3_0)
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a
CSIO (operation modes 2) and as SCL3 when it
is used in an I2C (operation mode 4).
108
17
-
-
-
-
C6
G3
SCK3_1
(SCL3_1)
12
12
90
F3
SIN4_0
SIN4_1
SIN4_2
6
75
10
6
65
-
6
54
-
84
43
-
D2
G12
-
D3
G12
E4
Multi-function serial interface ch.4 input pin
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
CTS4_0
CTS4_1
CTS4_2
RTS4_0
RTS4_1
RTS4_2
5
5
5
83
44
-
D1
G11
-
D2
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as 76
SDA4 when it is used in an I2C (operation mode
66
-
55
-
G11
F1
4).
11
Multi- function
Serial
4
4
4
4
82
45
-
C3
F12
-
D1
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
CSIO (operation modes 2) and as SCL4 when it
is used in an I2C (operation mode 4).
77
12
67
-
56
-
G10
F2
2
2
68
-
3
69
9
2
-
-
3
-
9
80
46
-
81
47
87
C1
F11
-
C2
E12
E3
C1
F13
F3
C2
F12
F4
Multi-function serial interface ch.4 CTS input pin
78
13
3
Multi-function serial interface ch.4 RTS output pin 79
14
Document Number: 002-04918 Rev. *G
Page 37 of 160
CY9B160R Series
Pin No
Pin
function
Pin name
SIN5_0
SIN5_1
SIN5_2
Function description
LQFP LQFP LQFP QFP
BGA
112
B5
BGA
144
C4
120
114
113
20
100
94
-
80
74
100
72
Multi-function serial interface ch.5 input pin
-
-
-
93
-
B5
H2
15
G3
SOT5_0
(SDA5_0)
SOT5_1
115
95
-
75
-
73
-
B4
-
B4
C5
H3
B3
D5
H4
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as 112
Multi- function (SDA5_1)
SDA5 when it is used in an I2C (operation mode
4).
Serial
5
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
SIN6_0
21
16
96
-
-
94
74
-
H2
B3
-
116
111
22
76
-
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
CSIO (operation modes 2) and as SCL5 when it
is used in an I2C (operation mode 4).
17
-
95
H3
7
95
7
80
7
65
85
58
E1
A10
E1
B10
Multi-function serial interface ch.6 input pin
SIN6_1
SOT6_0
(SDA6_0)
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA6 when it is used in an I2C (operation mode
4).
8
8
8
86
57
-
E2
B10
-
E2
SOT6_1
(SDA6_1)
94
9
79
-
64
-
A11
E3
Multi- function
Serial
6
SCK6_0
(SCL6_0)
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
CSIO (operation modes 2) and as SCL6 when it
is used in an I2C (operation mode 4).
SCK6_1
(SCL6_1)
93
92
78
77
63
62
56
55
B11
A12
C10
B13
Multi-function serial interface ch.6 serial chip
select pin
SCS6_1
SIN7_0
SIN7_1
101
50
86
45
-
35
64
23
C8
L9
C8
L8
Multi-function serial interface ch.7 input pin
SOT7_0
(SDA7_0)
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA7 when it is used in an I2C (operation mode
4).
100
85
-
63
B8
D8
SOT7_1
(SDA7_1)
49
99
48
47
44
84
43
42
34
-
22
62
21
20
M9
A8
L8
L7
M8
A9
K7
L7
Multi- function
Serial
7
SCK7_0
(SCL7_0)
Multi-function serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a
CSIO (operation modes 2) and as SCL7 when it
is used in an I2C (operation mode 4).
SCK7_1
(SCL7_1)
33
32
Multi-function serial interface ch.7 serial chip
select pin
SCS7_1
Document Number: 002-04918 Rev. *G
Page 38 of 160
CY9B160R Series
Pin No
LQFP LQFP LQFP QFP
120 100 80 100
Pin
function
Pin name
DTTI0X_0
Function description
BGA
112
BGA
144
Input signal controlling wave form generator
23 18 13 96
J1
J1
outputs RTO00 to RTO05 of Multi-function timer
0.
DTTI0X_1
79
69
-
47
E12
F12
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
18
80
62
22
75
63
21
76
64
20
77
65
19
78
66
13
70
52
17
65
53
16
66
54
15
67
55
14
68
56
-
-
91
48
30
95
43
31
94
44
32
93
45
33
92
46
34
G1
G4
16-bit free-run timer ch.0 external clock input pin
E11
L13
H3
G12
L12
H2
G11
K13
G3
F12
K12
G2
F11
L12
H4
G12
K12
H3
G11
K11
H2
G10
J12
H1
41
-
54
42
-
55
43
-
56
44
-
16-bit input capture ch.0 input pin of Multi-
function timer 0.
Icxx describes channel number.
IC02_1
IC02_2
IC03_0
IC03_1
-
45
F11
J13
F13
J11
IC03_2
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Multi-
function
Timer
0
24
86
25
85
26
84
27
83
28
82
29
81
19
71
20
-
14
57
15
-
97
49
98
-
J2
D13
J3
-
J2
D13
J3
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
E10
J4
21
-
16
-
99
-
K1
-
E11
K2
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
22
-
17
-
100
-
K2
-
E12
K3
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
23
-
18
-
1
L1
-
-
E13
L1
24
-
19
-
2
L2
-
-
F10
Document Number: 002-04918 Rev. *G
Page 39 of 160
CY9B160R Series
Pin No
LQFP LQFP LQFP QFP
120 100 80 100
Pin
function
Pin name
DTTI1X_0
Function description
BGA
112
BGA
144
Input signal controlling wave form generator
outputs RTO10 to RTO15 of Multi-function timer
1.
8
8
8
-
86
E2
E2
DTTI1X_1
55
-
-
-
L10
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
96
50
95
54
94
53
93
52
92
51
81
45
80
-
79
-
78
-
77
-
66
35
65
-
64
-
63
-
62
-
59
23
58
-
57
-
56
-
55
-
A9
L9
A10
-
B10
-
B11
-
A12
-
D9
L8
16-bit free-run timer ch.1 external clock input pin
B10
M10
A11
K9
C10
L9
16-bit input capture ch.1 input pin of Multi-
function timer 1.
Icxx describes channel number.
B13
K8
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_0
AIN1_1
AIN1_2
BIN1_0
BIN1_1
BIN1_2
ZIN1_0
ZIN1_1
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
2
2
2
-
80
5
C1
N2
C2
N3
C3
M3
D1
L3
C1
N2
C2
L2
32
3
27
3
Multi-
function
Timer
1
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
3
-
81
6
33
4
28
4
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
4
-
82
7
D1
N3
D2
M3
D3
L4
34
5
29
5
5
-
83
8
35
6
30
6
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
6
21
7
22
84
9
D2
M4
E1
L5
36
7
31
7
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
85
10
E1
K5
37
32
24
51
2
25
52
3
26
53
4
10
89
48
11
88
49
12
87
50
19
-
2
20
-
3
21
-
4
14
-
2
15
-
3
16
-
4
-
-
33
-
-
34
-
-
97
-
80
98
-
81
99
-
82
-
52
21
-
51
22
-
J2
-
C1
J3
-
C2
K1
-
C3
-
C12
L8
-
C13
M9
-
J2
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
K8
C1
J3
L9
C2
J4
K9
D1
E4
C12
K7
F1
D11
M8
F2
Quadrature
Position/
Revolution
Counter
0
-
74
43
-
73
44
-
Quadrature
Position/
Revolution
Counter
1
72
45
50
23
D12
L9
D12
L8
ZIN1_2
35
Document Number: 002-04918 Rev. *G
Page 40 of 160
CY9B160R Series
Pin No
Pin
Pin name
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
WKUP0
WKUP1
WKUP2
WKUP3
DA0
Function description
0.5 seconds pulse output pin of Real-time clock
Sub clock output pin
LQFP LQFP LQFP QFP
BGA
112
B4
BGA
144
B4
function
120
115
64
23
115
64
23
116
14
50
69
100
95
80
75
100
73
54
18
95
54
18
96
9
45
59
31
32
36
43
13
75
43
13
76
9
35
48
21
22
26
32
96
73
32
96
74
87
23
37
9
K13
J1
K11
J1
Real-time clock
B4
K13
J1
B4
K11
J1
Deep standby mode return signal input pin 0
Deep standby mode return signal input pin 1
Deep standby mode return signal input pin 2
Deep standby mode return signal input pin 3
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
On-board regulator control pin
B3
E3
L9
B3
F4
L8
Low-Power
Consumption
Mode
H12
M4
L5
H11
L4
K5
L6
36
37
41
DAC
DA1
VREGCTL
10
14
L6
VBAT
The return signal input pin from a hibernation
state
SD memory card interface
SD memory card clock output pin
SD memory card interface
SD memory card command output
VWAKEUP
S_CLK_0
S_CMD_0
42
92
93
37
77
78
27
62
63
15
55
56
M7
K6
A12
B11
B13
C10
S_DATA1_0
S_DATA0_0
S_DATA3_0
S_DATA2_0
94
95
96
97
79
80
81
82
64
65
66
67
57
58
59
60
B10
A10
A9
A11
B10
D9
SD memory card interface
SD memory card data bus
SD I/F
B9
C9
SD memory card interface
SD memory card detection pin
SD memory card interface
SD memory card write protection
External Reset Input pin.
A reset is valid when INITX = “L”.
Mode 1 pin.
S_CD_0
S_WP_0
INITX
113
114
38
93
94
33
73
74
23
71
72
11
C5
B5
M6
B5
C4
N4
Reset
Mode
MD1
MD0
During serial programming to Flash memory,
MD1 = “L” must be input.
Mode 0 pin.
During normal operation, MD0 = “L” must be
input. During serial programming to Flash
memory, MD0 = “H” must be input.
56
57
46
47
36
37
24
25
M10
M11
N10
M11
1
1
1
-
31
-
61
77
79
4
19
29
54
75
B1
B1
31
46
61
91
117
26
41
51
76
97
M1
M8
M13
B13
A4
M1
M9
M13
A12
A4
Power
VCC
Power supply Pin
Document Number: 002-04918 Rev. *G
Page 41 of 160
CY9B160R Series
Pin No
Pin
function
Pin name
Function description
LQFP LQFP LQFP QFP
BGA
112
A5
BGA
144
A7
120
107
100
92
80
100
70
-
30
45
60
90
120
-
-
-
-
-
-
-
-
-
-
-
25
40
50
75
100
-
-
-
-
-
-
-
-
-
-
-
20
30
40
60
80
-
-
-
-
-
-
-
-
-
-
-
-
-
3
18
28
53
78
-
-
-
-
-
-
-
-
-
-
-
-
-
N1
N10
N13
A13
A1
A7
B2
B12
C11
H1
N4
M5
N7
L11
A11
M12
M2
-
N1
N9
N13
A13
A1
A5
A8
A10
B2
B11
B12
C3
C11
C13
D4
D10
K1
GND
VSS
GND Pin
-
-
-
-
K4
-
-
-
-
-
-
-
-
-
-
K10
L3
-
-
-
-
-
L5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L11
L13
M2
M4
M6
M7
M12
N6
GND
VSS
GND Pin
X0
X1
X0A
X1A
CROUT_0
CROUT_1
Main clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) input pin
Sub clock (oscillation) I/O pin
58
59
39
40
87
113
48
49
34
35
72
93
38
39
24
25
58
73
26
27
12
13
50
71
N11
N12
N5
N6
D12
C5
N11
N12
N5
M5
D12
B5
Clock
Built-in high-speed CR-osc clock output port
A/D converter and D/A converter
analog power supply pin
AVCC
70
60
49
38
H13
K13
ADC
Power
AVRL
AVRH
A/D converter analog reference voltage input pin
A/D converter analog reference voltage input pin
VBAT power supply pin.
Backup power supply (battery etc.) and system
power supply.
72
73
62
63
51
52
40
41
F13
E13
H13
G13
VBAT
Power
VBAT
43
38
28
16
N8
N7
ADC
GND
C pin
A/D converter and D/A converter
GND pin
Power supply stabilization capacity pin
AVSS
C
71
44
61
39
50
29
39
17
G13
N9
J13
N8
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant
to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in
other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04918 Rev. *G
Page 42 of 160
CY9B160R Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
When the main oscillation is
selected.
P-ch
P-ch
Digital output
Digital output
• Oscillation feedback resistor
: Approximately 1 MΩ
• With Standby mode control
X1
When the GPIO is selected.
• CMOS level output.
N-ch
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
R
• Pull-up resistor
: Approximately 50 Kω
• IOH =-4 Ma, IOL =4 Ma
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
N-ch
Digital output
X0
Digital output
Pull-up resistor control
B
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 Kω
Pull-up resistor
Digital input
Document Number: 002-04918 Rev. *G
Page 43 of 160
CY9B160R Series
Type
C
Circuit
Remarks
• Open drain output
• CMOS level hysteresis input
Digital input
N-ch
Digital output
E
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 Kω
P-ch
P-ch
Digital output
• IOH = -4 Ma, IOL = 4 Ma
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
P-ch
P-ch
Digital output
• Pull-up resistor
: Approximately 50 Kω
• IOH = -4 Ma, IOL = 4 Ma
N-ch
Digital output
Pull-up resistor control
R
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-04918 Rev. *G
Page 44 of 160
CY9B160R Series
Type
Circuit
Remarks
G
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 Kω
• IOH = -12 Ma, IOL = 12 Ma
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor
control
Digital input
Standby mode
control
H
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
• IOH = -20.5 Ma, IOL = 18.5 Ma
Digital output
P-ch
Digital output
N-ch
R
Digital input
Standby mode
Control
Document Number: 002-04918 Rev. *G
Page 45 of 160
CY9B160R Series
Type
Circuit
Remarks
I
• CMOS level output
• CMOS level hysteresis input
• 5V tolerant
• With standby mode control
• Pull-up resistor
: Approximately 50 Kω
• IOH =-4 Ma, IOL =4 Ma
• Available to control of PZR
registers.
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor
control
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
L
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 Kω
• IOH = -8 Ma, IOL = 8 Ma
P-ch
P-ch
Digital output
Digital output
N-ch
Pull-up resistor
control
R
Digital input
Standby mode
control
Document Number: 002-04918 Rev. *G
Page 46 of 160
CY9B160R Series
Type
Circuit
Remarks
M
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 Kω
• IOH = -8 Ma, IOL = 8 Ma
P-ch
P-ch
Digital output
Digital output
N-ch
Pull-up resistor
control
R
Digital input
Standby mode
control
Analog input
Input control
N
・ CMOS level output
・CMOS level hysteresis input
・5V tolerant
・Pull-up resistor control
・ Standby mode control
・Pull-up resistor:
Pull-up resistor
control
Digital output
P-ch
P-ch
approximately 50 Kω
・IOH = -4 Ma, IOL = 4 Ma (GPIO)
・IOL = 20 Ma (Fast mode Plus)
・Available to control of PZR
register (pseudo-open drain
control)
N-ch
N-ch
Digital output
・For PZR registers, refer to GPIO
in the FM4 Family Peripheral
Manual Main Part (002-04856).
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
Fast mode
control
R
Digital input
Standby mode
control
Document Number: 002-04918 Rev. *G
Page 47 of 160
CY9B160R Series
Type
Circuit
Remarks
O
・ CMOS level output
・CMOS level hysteresis input
・5 V tolerant
・Pull-up resistor control
・ Pull-up resistor:
Pull-up resistor
control
Digital output
P-ch
approximately 50 Kω
P-ch
N-ch
・ IOH = -4 Ma, IOL= 4 Ma
・ Available to control of PZR
register (pseudo-open drain
control)
・ For PZR registers, refer to GPIO
in the “FM4 Family Peripheral
Manual Main Part (002-04856)”.
・ For I/O setting, refer to VBAT
Domain in the FM4 Family
Peripheral Manual Main Part
(002-04856).
Digital output
Digital input
R
P
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
P-ch
Pull-up resistor
control
Digital output
• Pull-up resistor
: Approximately 50 Kω
• IOH =-4 Ma, IOL =4 Ma
• For I/O setting, refer to VBAT
Domain in the Peripheral Manual
P-ch
N-ch
X0A
Digital output
R
Digital input
Standby mode
control
OSC
Document Number: 002-04918 Rev. *G
Page 48 of 160
CY9B160R Series
Type
Circuit
Remarks
Q
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is
selected.
Pull-up resistor
control
Digital output
P-ch
• Oscillation feedback resistor
: Approximately 10 MΩ
• With Standby mode control
P-ch
N-ch
X1A
• When the GPIO is selected.
Digital output
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
R
• Pull-up resistor
: Approximately 50 Kω
Digital input
• IOH = -4 Ma, IOL = 4 Ma
• For I/O setting, refer to VBAT
Domain in the Peripheral Manual
Standby mode
control
OSC
RX
Standby mode
control
Clock input
R
• CMOS level output
• CMOS level hysteresis input
• Analog output
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 Kω
• IOH = -12 Ma, IOL = 12 Ma
(4.5 V to 5.5 V)
• IOH = -8 Ma, IOL = 8 Ma
(2.7 V to 4.5 V)
Pull-up resistor
P-ch
control
P-ch
N-ch
Digital output
Digital output
R
Digital input
Standby mode
control
Analog output
Document Number: 002-04918 Rev. *G
Page 49 of 160
CY9B160R Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess
of several hundred Ma to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04918 Rev. *G
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CY9B160R Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising
from such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress’ recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
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CY9B160R Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of
1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of 52tyrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
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CY9B160R Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this
device.
Power supply pins
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed
operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the
fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard
VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power
supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
• Surface mount type
Size:
More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 Pf to 7 Pf
• Lead type
Load capacitance: Approximately 6 Pf to 7 Pf
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0.
X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
⚫ Example of Using an External Clock
Device
X0(X0A)
Set as External
clock input
Can be used as
general-purpose
I/O ports.
X1(PE3), X1A (P47)
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CY9B160R Series
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with
power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 Μf would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time. The device operates normally after all power on.
VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then VCC turns
Power-off. About Hibernation control, see Chapter 7-2: VBAT Domain(A) in FM4 Family Peripheral Manual Main Part(002-04856).
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VBAT → VCC
VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
VCC → VBAT
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the
end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash products and
MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics
among the products with different memory sizes and between Flash products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Document Number: 002-04918 Rev. *G
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CY9B160R Series
Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Adjoining wiring on circuit board
If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of P48/VREGCTL, there is a possibility
that the oscillation erroneously counts because X1A has noise with the change of P48/VREGCTL. Keep as much distance as
possible between both wirings and insert the ground pattern between them in order to avoid this possibility.
Device
P46/
X0A
P47/
X1A
P48/
P49/
VREGCTL VWAKEUP
Not allowed to run
both wirings in parallel
Ground
Insert the ground pattern
Handling when using debug pins
When debug pins(TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set
them as output, do not set them as input.
Document Number: 002-04918 Rev. *G
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CY9B160R Series
8. Block Diagram
MB9BF166M/N/R, F167M/N/R, F168M/N/R
TRSTX,TCK,
TDI,TMS
TDO
SRAM0
32/48/64 Kbytes
SWJ-DP
TPIU*
ETM*
ROM
Table
TRACEDx,
TRACECLK
SRAM1
16/24/32 Kbytes
I
D
SRAM2
16/24/32 Kbytes
FPU MPU NVIC
Sys
MainFlash I/F
MainFlash
1 Mbytes/
768 Kbytes/
512 Kbytes
Trace Buffer
(16 Kbytes)
Dual-Timer
Security
Watchdog Timer
(Software)
WorkFlash
32 Kbytes
WorkFlash I/F
Clock Reset
Generator
INITX
DMAC
8ch.
Watchdog Timer
(Hardware)
CSV
DSTC
CLK
S_CLK,S_CMD
S_DATAx
SD-CARD I/F
S_CD,S_WP
P0x,
Source Clock
Main
Osc
P1x,
GPIO
.
.
.
X0
X1
CR
100 kHz
CR
PLL
PIN-Function-Ctrl
PEx
VBAT Domain
4 MHz
X0A
X1A
Sub
Osc
MADx
CROUT
MADATAx
External Bus I/F
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT,MSDWEX,
MSDCLK,MSDCKE,
MRASX,MCASX
AVCC,
AVSS,
AVRH
12-bit A/D Converter
Unit 0
Power-On
Reset
ANxx
Unit 1
Unit 2
ADTGx
LVD
LVD Ctrl
Regulator
C
IRQ-Monitor
CRC Accelerator
Watch Counter
TIOAx
TIOBx
Base Timer
16-bit 16ch./
32-bit 8ch.
AINx
BINx
ZINx
WKUPx
Deep Standby Ctrl
QPRC
2ch.
Peripheral Clock Gating
Low-speed CR Prescaler
VWAKEUP
VBAT Domain
Real-Time Clock
Port Ctrl.
A/D Activation Compare
6ch.
VREGCTL
RTCCO,
SUBOUT
16-bit Input Capture
4ch.
IC0x
External Interrupt
Controller
16pin + NMI
INTx
NMIX
16-bit Free-run Timer
3ch.
FRCK0
MD0,
MD1
MODE-Ctrl
16-bit Output Compare
6ch.
SCKx
SINx
DTTI0X
RTO0x
Multi-function Serial I/F
8ch.
HW flow control(ch.4)
Waveform Generator
3ch.
SOTx
CTS4
RTS4
12-bit D/A Converter
2units
16-bit PPG
3ch.
DAx
Multi-function Timer × 2
*: For the MB9BF166M, MB9BF167M and MB9BF168M, ETM is not available.
Document Number: 002-04918 Rev. *G
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CY9B160R Series
9. Memory Size
See “Memory size” in “Product Lineup” to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0x4007_0000
0x4006_F000
0x4006_E000
GPIO
SD-Card I/F
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
Cortex-M4 Private
0x4006_2000
0x4006_1000
0x4006_0000
DSTC
DMAC
Peripherals
0xE000_0000
Reserved
0x4004_0000
0x4003_F000
EXT-bus I/F
Reserved
External Device
Area
0x4003_C800
0x4003_C100
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
Peripheral Clock Gating
Low Speed CR Prescaler
RTC/Port Ctrl
Watch Counter
CRC
0x6000_0000
Reserved
0x4400_0000
0x4200_0000
MFS
Reserved
32 Mbytes
Bit band alias
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
LVD/DS mode
Reserved
D/AC
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
0x4000_0000
0x2400_0000
0x2200_0000
32 Mbytes
Bit band alias
Reserved
CR Trim
Reserved
Reserved
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x2010_0000
0x200E_0000
0x200C_0000
A/DC
QPRC
Base Timer
PPG
WorkFlash I/F
WorkFlash
Reserved
0x2004_8000
0x2004_0000
0x2003_8000
0x2000_0000
0x1FFF_0000
0x0050_0000
0x0040_0000
Reserved
SRAM2
SRAM1
Reserved
SRAM0
Reserved
0x4002_2000
0x4002_1000
0x4002_0000
MFT Unit1
MFT Unit0
See "⚫Memory Map (2)"
for the memory size
details.
Reserved
0x4001_6000
0x4001_5000
Security/CR Trim
Dual Timer
Reserved
0x4001_3000
MainFlash
0x4001_2000
0x4001_1000
SW WDT
HW WDT
0x0000_0000
0x4001_0000
Clock/Reset
Reserved
0x4000_1000
0x4000_0000
MainFlash I/F
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Page 57 of 160
CY9B160R Series
Memory Map (2)
MB9BF168M/N/R
MB9BF167M/N/R
MB9BF166M/N/R
0x2008_0000
0x2008_0000
0x200C_8000
0x200C_0000
0x2008_0000
Reserved
Reserved
Reserved
0x200C_8000
0x200C_0000
0x200C_8000
0x200C_0000
WorkFlash
32 Kbytes
WorkFlash
32 Kbytes
WorkFlash
32 Kbytes
Reserved
Reserved
0x2004_8000
0x2004_0000
Reserved
0x2004_6000
0x2004_0000
0x2003_A000
SRAM2
32 Kbytes
0x2004_4000
0x2004_0000
0x2003_C000
SRAM2
24 Kbytes
SRAM2
16 Kbytes
SRAM1
SRAM1
24 Kbytes
SRAM1
32 Kbytes
16 Kbytes
0x2003_8000
0x2000_0000
Reserved
Reserved
Reserved
0x2000_0000
0x1FFF_4000
0x2000_0000
0x1FFF_8000
SRAM0
32 Kbytes
SRAM0
48 Kbytes
SRAM0
64 Kbytes
0x1FFF_0000
Reserved
Reserved
Reserved
0x0050_0000
0x0040_2000
0x0040_0000
0x0050_0000
0x0040_2000
0x0040_0000
0x0050_0000
0x0040_2000
0x0040_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
0x0010_0000
Reserved
Reserved
0x000C_0000
MainFlash
1 Mbytes
0x0008_0000
0x0000_0000
MainFlash
768 Kbytes
MainFlash
512 Kbytes
0x0000_0000
0x0000_0000
Document Number: 002-04918 Rev. *G
Page 58 of 160
CY9B160R Series
Peripheral Address Map
Start address
End address
0x4000_0FFF
Bus
AHB
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_C100
0x4003_C800
0x4003_F000
0x4004_0000
0x4006_0000
0x4006_1000
0x4006_4000
0x4006_E000
0x4006_F000
0x4006_7000
0x200E_0000
MainFlash I/F register
Reserved
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4003_FFFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_4FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_C0FF
0x4003_C7FF
0x4003_EFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_3FFF
0x4006_DFFF
0x4006_EFFF
0x4006_FFFF
0x41FF_FFFF
0x200E_FFFF
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Reserved
PPG
Base Timer
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Internal CR trimming
Reserved
External Interrupt Controller
Interrupt Request Batch-Read Function
Reserved
APB0
APB1
D/A Converter
Reserved
Low Voltage Detector
Deep standby mode Controller
Reserved
Multi-function serial Interface
CRC
APB2
Watch Counter
RTC/Port Ctrl
Low-speed CR Prescaler
Peripheral Clock Gating
Reserved
External Memory interface
Reserved
DMAC register
DSTC register
Reserved
SD-Card I/F
AHB
GPIO
Reserved
WorkFlash I/F register
Document Number: 002-04918 Rev. *G
Page 59 of 160
CY9B160R Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
◼INITX = 0
This is the period when the INITX pin is the “L” level.
◼INITX = 1
This is the period when the INITX pin is the “H” level.
◼SPL = 0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to “0”.
◼SPL = 1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to “1”.
◼Input enabled
Indicates that the input function can be used.
◼Internal input fixed at “0”
This is the status that the input function cannot be used. Internal input is fixed at “L”.
◼Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
◼Setting disabled
Indicates that the setting is disabled.
◼Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
◼Analog input is enabled
Indicates that the analog input is enabled.
◼Trace output
Indicates that the trace function can be used.
◼GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
◼Setting prohibition
Prohibition of a setting by specification limitation.
Document Number: 002-04918 Rev. *G
Page 60 of 160
CY9B160R Series
List of Pin Status
Power-on
reset or low-
voltage
detection
state
Device
internal
reset
Return from
Deep
standby
INITX
input
state
Run mode
or SLEEP
mode state
Deep standby RTC
mode or Deep standby
STOP mode state
TIMER mode,
RTC mode, or
STOP mode state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
‐
‐
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at “0”
GPIO
selected
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
A
Main crystal
oscillator
input pin/
Input
Input
Input
Input
Input
Input
Input
Input
Input
External main
clock input
selected
enabled
enabled enabled enabled
enabled
enabled
enabled
enabled
enabled
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at “0”
GPIO
selected
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
Hi-Z /
Hi-Z /
External main
clock input
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at “0”
Internal
input fixed
at “0”
B
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Hi-Z /
Hi-Z /
Internal
input
fixed
at “0”
Hi-Z /
Internal
input
fixed
at “0”
state/When state/When state/When state/When state/When state/When
Internal
input fixed
at “0”/
or Input
enable
Main crystal
oscillator
output pin
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at “0”
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at “0”
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at “0”
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at “0”
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at “0”
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at “0”
Pull-up /
Input
enabled
Pull-up / Pull-up /
Input Input
enabled enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
INITX
input pin
C
D
Mode
input pin
Input
enabled
Input
Input
Input
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
enabled enabled enabled
Mode
Input
Input Input Input
Input
Input
Input
Input
Input
input pin
enabled
enabled enabled enabled
Maintain
enabled
Maintain
previous
state
enabled
enabled
enabled
enabled
E
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
Setting
disabled
Setting
Setting
GPIO
selected
GPIO
selected
previous
state
disabled disabled
Document Number: 002-04918 Rev. *G
Page 61 of 160
CY9B160R Series
Power-on
reset or low-
voltage
detection
state
Device
internal
reset
Return from
Deep
standby
INITX
input
state
Run mode
or SLEEP
mode state
Deep standby RTC
mode or Deep standby
STOP mode state
TIMER mode,
RTC mode, or
STOP mode state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
‐
‐
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Maintain
previous
state
Setting
disabled
Setting
disabled disabled
Setting
NMIX selected
GPIO
selected
Hi-Z /
WKUP
input
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Resource other
than above
selected
F
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Internal
input fixed
at “0”
enabled
Hi-Z
Hi-Z
Maintain
previous
state
GPIO
selected
Pull-up / Pull-up /
Input
enabled enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Input
Maintain
previous
state
Maintain
previous
state
G
GPIO
Hi-Z /
Hi-Z /
selected
Internal
input fixed
at “0”
GPIO
selected
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
Pull-up / Pull-up /
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Hi-Z
Input
Input
enabled enabled
Maintain
previous
state
Maintain
previous
state
H
Resource other
than above
selected
GPIO
Hi-Z /
Hi-Z /
selected
Internal
input fixed
at “0”
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
GPIO
selected
GPIO
Resource
selected
Hi-Z /
Hi-Z /
Hi-Z /
Input
Hi-Z /
Input
Maintain
previous
Maintain
previous
state
selected
Internal
input fixed
at “0”
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
I
Hi-Z
GPIO
selected
enabled enabled state
Analog output
selected
Setting
disabled
Setting
disabled disabled
Setting
*2
*3
GPIO
Hi-Z /
Maintain
previous
state
selected
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
Resource other
than above
selected
J
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Maintain
previous
state
Internal
input fixed
at “0”
Hi-Z
GPIO
selected
Document Number: 002-04918 Rev. *G
Page 62 of 160
CY9B160R Series
Power-on
reset or low-
voltage
detection
state
Device
internal
reset
Return from
Deep
standby
INITX
input
state
Run mode
or SLEEP
mode state
Deep standby RTC
mode or Deep standby
STOP mode state
TIMER mode,
RTC mode, or
STOP mode state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
‐
‐
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
External
Maintain
previous
state
interrupt
enabled
selected
Setting
disabled
Setting
disabled disabled
Setting
GPIO
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
K
Resource other
than above
selected
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Internal
input fixed
at “0”
Hi-Z
Hi-Z
GPIO
selected
Hi-Z /
Internal
input
fixedat
„0“ /
Analog
input
enabled enabled
Hi-Z /
Internal
input
fixedat
„0“ /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Analog input
selected
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
L
Resource other
than above
selected
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at “0”
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
GPIO
selected
Hi-Z /
Internal
input
Hi-Z /
Internal
input
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Analog input
selected
fixed
fixed
Hi-Z
at “0” /
Analog
input
at “0” /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled enabled
M
External
interrupt
enabled
selected
Resource other
than above
selected
GPIO
Maintain
previous
state
GPIO
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at “0”
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at “0”
GPIO
selected
Hi-Z /
Internal
input fixed
at “0”
selected
Document Number: 002-04918 Rev. *G
Page 63 of 160
CY9B160R Series
Power-on
reset or low-
voltage
detection
state
Device
internal
reset
Return from
Deep
standby
INITX
input
state
Run mode
or SLEEP
mode state
Deep standby RTC
mode or Deep standby
STOP mode state
TIMER mode,
RTC mode, or
STOP mode state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
‐
‐
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
input
Hi-Z /
Internal
input
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Analog input
selected
fixed
fixed
Hi-Z
at”0” /
Analog
input
at “0” /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled enabled
N
Trace
output
Trace selected
GPIO
Hi-Z /
Resource other
than above
selected
GPIO
selected
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at “0”
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at “0”
GPIO
selected
Hi-Z /
Internal
input fixed
at “0”
Hi-Z /
Internal
input
Hi-Z /
Internal
input
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Analog input
selected
fixed
fixed
Hi-Z
at “0” /
Analog
input
at “0” /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled enabled
Trace
output
Trace selected
O
External
interrupt
enabled
selected
Maintain
previous
state
GPIO
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at “0”
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at “0”
GPIO
selected
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at “0”
GPIO
selected
Document Number: 002-04918 Rev. *G
Page 64 of 160
CY9B160R Series
Power-on
reset or low-
voltage
detection
state
Device
internal
reset
Return from
Deep
standby
INITX
input
state
Run mode
or SLEEP
mode state
Deep standby RTC
mode or Deep standby
STOP mode state
TIMER mode,
RTC mode, or
STOP mode state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply
stable
‐
‐
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
input
fixedat
„0“ /
Analog
input
enabled enabled
Hi-Z /
Internal
input
fixedat
„0“ /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Internal
input fixed
at “0” /
Analog
input
Analog input
selected
Hi-Z
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
P
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP input
enabled
WKUP
enabled
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
Setting
disabled
Setting
disabled disabled
Setting
GPIO
selected
GPIO
Hi-Z /
Hi-Z /
selected
Internal
input fixed
at “0”
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
Hi-Z /
WKUP
WKUP input WKUP
enabled
enabled
input
enabled
Maintain
previous
state
Setting
disabled
Setting
disabled disabled
Setting
External
interrupt
enabled
selected
Resource other
than above
selected
GPIO
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Q
GPIO
Hi-Z /
selected
Internal
input fixed
at “0”
Internal
input fixed
at “0”
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Internal
input fixed
at “0”
Hi-Z
Hi-Z
selected
GPIO
Hi-Z /
Hi-Z /
Hi-Z /
Input
Hi-Z /
Input
Maintain
previous
Maintain
previous
state
selected
Internal
input fixed
at “0”
GPIO
selected
Internal
input fixed
at “0”
Internal
input fixed
at “0”
GPIO
selected
R
enabled enabled state
*1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep
standby STOP mode.
*2: Maintain previous state at timer mode. GPIO selected Internal input fixed at “0” at RTC mode, STOP mode.
*3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at “0” at RTC mode, STOP mode.
Document Number: 002-04918 Rev. *G
Page 65 of 160
CY9B160R Series
List of VBAT Domain Pin Status
Return
Return
from
Deep
standby
mode
state
Run
mode or
SLEEP
mode
from
VBAT
RTC
mode
state
VBAT
RTC
mode
state
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP
mode state
INITX
input
state
Power-
TIMER mode,
RTC mode, or
STOP mode state
on
reset*1
state
state
Function
group
Power
supply
Power
supply
stable
Power
Power Power
Power supply
stable
Power supply
stable
Power supply
stable
supply supply supply
unstable
stable
INITX = 1
-
stable stable
‐
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
-
-
‐
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
-
-
Maintain Maintain Maintain Maintain
Previous Previous previous previous
Maintain
Previous
state
Maintain
Previous
state
Maintain
Previous
state
Maintain
Previous
state
GPIO
selected
Setting
disabled
Setting
prohibition
-
state
state
state
state
Sub crystal
oscillator
input pin /
External
sub clock
input
S
Maintain
previous
state
Maintain
previous
state
Input
Input
Input
Input
Input
Input
enabled
Input
enabled
Input
enabled
Input
enabled
enabled enabled enabled enabled enabled
selected
Maintain Maintain Maintain Maintain
Maintain
Previous
state
Maintain
Previous
state
Maintain
Previous
state
Maintain
Previous
state
GPIO
selected
Setting
Setting
prohibition
Previous Previous previous previous
disabled
-
state
state
state
state
External
sub clock Setting
input
selected
Maintain Maintain Maintain Maintain
Previous Previous previous previous
Maintain
Previous
state
Maintain
previous
state
Maintain
Previous
state
Maintain Maintain
previous previous
Maintain
previous
state
disabled
state
state
state
state
state
state
T
Hi-Z /
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Internal
input fixed
at “0”/
or Input
enable
Sub crystal
oscillator
output pin
Maintain Maintain Maintain
Previous Previous previous
Maintain Maintain
Previous previous
Maintain
previous
state
state/When state/When state/When state/When
oscillation oscillation oscillation oscillation
stops,
Hi-Z*2
state
state
state
state
state
stops,
Hi-Z*2
stops,
Hi-Z*2
stops,
Hi-Z*2
Resource
selected
Maintain Maintain Maintain Maintain
previous previous previous previous
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain Maintain
previous previous
Maintain
previous
state
U
Hi-Z
state
state
state
state
state
state
GPIO
selected
*1: When VBAT and VCC power on.
*2: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the previous state.
When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop
Document Number: 002-04918 Rev. *G
Page 66 of 160
CY9B160R Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage *1, *2
VCC
VSS – 0.5
VSS + 6.5
V
3
Power supply voltage (VBAT) *1 ,
*
VBAT
VSS – 0.5
VSS – 0.5
VSS – 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
V
V
V
4
Analog power supply voltage *1 ,
*
AVCC
AVRH
4
Analog reference voltage *1 ,
*
VCC + 0.5
(≤ 6.5V)
VSS – 0.5
VSS – 0.5
VSS – 0.5
V
V
V
Input voltage *1
VI
VSS + 6.5
5V tolerant
AVCC + 0.5
(≤ 6.5V)
VCC + 0.5
(≤ 6.5V)
10
Analog pin input voltage *1
Output voltage *1
VIA
VO
VSS – 0.5
V
Ma
Ma
Ma
Ma
Ma
Ma
Ma
Ma
Ma
4Ma type
8Ma type
12Ma type
I2C Fm+
4Ma type
8Ma type
12Ma type
I2C Fm+
20
20
22.4
4
8
“L” level maximum output current *5
“L” level average output current *6
IOL
-
IOLAV
-
12
20
“L” level total maximum output current
“L” level total maximum output current *7
∑IOL
-
-
100
50
∑IOLAV
Ma
Ma
Ma
- 10
4Ma type
8Ma type
“H” level maximum output current *5
“H” level average output current *6
IOH
-
-
20
- 20
- 4
8
- 12
- 100
Ma
Ma
Ma
Ma
Ma
12Ma type
4Ma type
8Ma type
12Ma type
IOHAV
“H” level total maximum output current
“H” level total average output current *7
Storage temperature
∑IOH
-
∑IOHAV
TSTG
-
- 50
Ma
°C
- 55
+ 150
*1: These parameters are based on the condition that VSS = AVSS = 0.0V.
*2: VCC must not drop below VSS – 0.5V.
*3: VBAT must not drop below VSS – 0.5V.
*4: Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on.
*5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100ms period.
*7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current
or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-04918 Rev. *G
Page 67 of 160
CY9B160R Series
12.2 Recommended Operating Conditions
Value
Parameter
Symbol
VCC
VBAT
Conditions
Unit
Remarks
Min
2.7*3
Max
Power supply voltage
-
-
-
-
-
-
5.5
V
V
V
Power supply voltage (VBAT)
Analog power supply voltage
Analog reference voltage
2.7
2.7
5.5
5.5
AVCC
AVRH
Tj
AVCC = VCC
2
*
AVCC
V
Junction temperature
Ambient temperature
- 40
- 40
+ 125
°C
°C
Operating
temperature
1
TA
*
*1: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction
temperature (Tj).
The calculation formula of the ambient temperature (TA) is shown below.
TA(Max) = Tj(Max) – Pd(Max) × θja
Pd:
θja:
Power dissipation (W)
Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL
IOH
VOL
VOH
:
:
“L” level output current
“H” level output current
“L” level output voltage
“H” level output voltage
:
:
*2: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5. 12-bit A/D
Converter” for the details.
*3: Between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage, instruction execution
and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible
to operate.
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table for package thermal resistance and maximum permissible power
Maximum permissible power
(Mw)
Thermal resistance
Package
Printed circuit board
θja (°C/W)
TA = +85°C
TA = +105°C
333
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
60
39
58
38
57
38
48
34
62
43
60
40
55
40
667
1026
690
1053
702
1053
833
1177
645
930
667
1000
727
LQH080
(0.5mm pitch)
513
335
526
351
526
417
588
323
465
333
500
364
500
LQJ080
(0.65mm pitch)
LQI100
(0.5mm pitch)
PQH100
(0.65mm pitch)
LQM120
(0.5mm pitch)
LDC112
(0.5mm pitch)
LDC144
(0.5mm pitch)
1000
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device’s electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in
device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-04918 Rev. *G
Page 68 of 160
CY9B160R Series
Calculation method of power dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL
IOH
VOL
VOH
:
“L” level output current
“H” level output current
“L” level output voltage
“H” level output voltage
:
:
:
ICC is a current consumed in device.
It can be analyzed as follows.
ICC = ICC(INT) + ΣICC(IO)
ICC(INT): Current consumed in internal logic and memory, etc. through regulator
ΣICC(IO): Sum of current (I/O switching current) consumed in output pin
For ICC (INT), it can be anticipated by 12.3.1 “Current Rating” in 12.3. DC Characteristics” (This rating value does not include ICC
(IO) for a value at pin fixed).
For Icc (IO), it depends on system used by customers.
The calculation formula is shown below.
ICC(IO) = (CINT + CEXT) × VCC × fsw
CINT
CEXT
fSW
:
:
Pin internal load capacitance
External load capacitance of output pin
Pin switching frequency
:
Parameter
Symbol
Conditions
Capacitance value
4Ma type
8Ma type
12Ma type
1.93Pf
3.45Pf
3.42Pf
Pin internal load capacitance
CINT
Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself.
1. Measure current value ICC (Typ) at normal temperature (+25°C).
2. Add maximum leak current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC(Typ) + ICC(leak_max)
Parameter
Symbol
Conditions
Current value
Tj = +125°C
Tj = +105°C
Tj = +85°C
45.5Ma
26.8Ma
16.2Ma
Maximum leak current at
operating
ICC(leak_max)
Document Number: 002-04918 Rev. *G
Page 69 of 160
CY9B160R Series
Current explanation diagram
Pd = VCC×ICC + Σ(IOL×VOL)+Σ((VCC-VOH)×(-IOH))
ICC = ICC(INT)+ΣICC(IO)
VCC
A
ICC
Chip
ΣICC(IO)
ICC(INT)
A
IOL
Regulator
VOL
V
Flash
VOH
A
IOH
V
Logic
RAM
CEXT
Document Number: 002-04918 Rev. *G
Page 70 of 160
CY9B160R Series
12.3 DC Characteristics
12.3.1 Current Rating
Table 12-1. Typical and maximum current consumption in Normal operation(PLL), code running from Flash memory
(Flash accelerator mode and trace buffer function enabled)
Value
Typ*1 Max*2
Pin
name
Parameter
Symbol
Conditions
Frequency*4
Unit
Remarks
160MHz
144MHz
54
103
49
98
120MHz
100MHz
80MHz
60MHz
40MHz
20MHz
8MHz
4MHz
160MHz
144MHz
41
35
28
22
16
8.9
5.1
3.8
34
31
26
22
18
90
84
77
71
64
58
54
53
83
80
75
71
67
3
*
Ma
When all peripheral
clocks are ON
Power supply
current
Normal operation*5,*6
(PLL)
ICC
VCC
120MHz
100MHz
80MHz
3
*
Ma
When all peripheral
clocks are OFF
60MHz
40MHz
14
63
10
59
55
53
52
20MHz
8MHz
4MHz
6.2
3.8
3.1
Table 12-2. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from
Flash memory (Flash accelerator mode and trace buffer function disabled)
Value
Typ*1 Max*2
Pin
name
Parameter
Symbol
Conditions
Frequency*7
Unit
Remarks
160MHz
144MHz
74
126
68
120
120MHz
100MHz
80MHz
60MHz
40MHz
20MHz
8MHz
4MHz
160MHz
144MHz
59
52
44
36
27
17
8.3
5.4
51
112
104
97
89
79
67
58
55
103
3
*
Ma
When all peripheral
clocks are ON
Power supply
current
Normal operation*8
(PLL)
ICC
VCC
47
42
37
33
28
100
94
90
85
80
120MHz
100MHz
80MHz
3
*
Ma
When all peripheral
clocks are OFF
60MHz
40MHz
21
73
64
56
54
20MHz
8MHz
4MHz
13
6.9
4.6
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2
Document Number: 002-04918 Rev. *G
Page 71 of 160
CY9B160R Series
*5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
*6: Data access is nothing to MainFlash memory
*7: Frequency is a value of HCLK. PCLK0 = PCLK2 = HCLK/2, PCLK1 = HCLK
*8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
Table 12-3. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from
Flash memory (flash 0 wait-cycle mode and read access 0 wait)
Frequency*4
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ*1
Max*2
(MHz)
72MHz
46
98
60MHz
48MHz
36MHz
24MHz
40
33
27
19
92
85
78
70
3
*
Ma
When all peripheral
clocks are ON
12MHz
8MHz
4MHz
72MHz
60MHz
11
61
58
55
85
81
76
71
65
8.5
5.5
33
29
25
20
15
Normal
Power supply
current
ICC
VCC
operation*5
(PLL)
48MHz
36MHz
24MHz
3
*
Ma
When all peripheral
clocks are OFF
12MHz
8MHz
4MHz
9.2
6.9
4.6
59
56
54
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00)
Document Number: 002-04918 Rev. *G
Page 72 of 160
CY9B160R Series
Table 12-4. Typical and maximum current consumption in Normal operation(other than PLL), code with data accessing
running from Flash memory (flash 0 wait-cycle mode and read access 0 wait
Value
Typ*1 Max*2
Pin
name
Parameter
Symbol
Conditions
Frequency*4
Unit
Remarks
3
*
3.3
51
Ma
When all peripheral
clocks are ON
*
When all peripheral
clocks are OFF
Normal
operation*5
(built-in high-speed
CR)
4MHz
3
2.8
51
Ma
Ma
Ma
Ma
Ma
3
*
0.64
0.56
0.64
0.58
48
48
48
48
When all peripheral
clocks are ON
Normal
operation*5
(sub oscillation)
Power supply
current
32kHz
ICC
VCC
3
*
When all peripheral
clocks are OFF
3
*
When all peripheral
clocks are ON
Normal
operation*5
(built-in
100kHz
3
*
low-speed CR)
When all peripheral
clocks are OFF
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000)
Document Number: 002-04918 Rev. *G
Page 73 of 160
CY9B160R Series
Table 12-5. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2
Value
Typ*1 Max*2
Pin
name
Parameter
Symbol
Conditions
Frequency*4
Unit
Remarks
160MHz
144MHz
35
84
32
81
120MHz
100MHz
80MHz
60MHz
40MHz
20MHz
8MHz
4MHz
160MHz
144MHz
27
23
19
15
11
6.5
4.1
3.3
16
14
12
11
76
72
68
64
60
55
53
52
65
63
61
60
58
3
*
Ma
When all peripheral
clocks are ON
Power supply
current
Sleep operation
(PLL)
ICCS
VCC
120MHz
100MHz
80MHz
3
*
9.0
Ma
When all peripheral
clocks are OFF
60MHz
40MHz
7.4
56
5.6
3.9
2.9
2.6
54
53
52
51
20MHz
8MHz
4MHz
Table 12-6. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK
Value
Typ*1 Max*2
Pin
name
Parameter
Symbol
Conditions
Frequency*5
Unit
Remarks
72MHz
22
19
16
71
68
64
60MHz
48MHz
36MHz
24MHz
3
*
12
61
58
Ma
When all peripheral
clocks are ON
9.0
12MHz
8MHz
4MHz
72MHz
60MHz
5.8
4.6
3.6
9.5
8.3
7.1
5.8
4.6
55
54
52
58
57
56
55
53
Power supply
current
Sleep operation
(PLL)
ICCS
VCC
48MHz
36MHz
24MHz
3
*
Ma
When all peripheral
clocks are OFF
12MHz
8MHz
4MHz
3.5
3.0
2.7
52
52
51
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2
*5: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK
Document Number: 002-04918 Rev. *G
Page 74 of 160
CY9B160R Series
Table 12-7. Typical and maximum current consumption in Sleep operation(other than PLL), when PCLK0 = PCLK1 =
PCLK2 = HCLK/2
Value
Typ*1 Max*2
Pin
name
Parameter
Symbol
Conditions
Frequency*4
Unit
Remarks
3
*
1.5
49
Ma
When all peripheral
clocks are ON
Sleep
operation
(built-in high-speed
CR)
4MHz
3
*
1.0
49
48
48
Ma
Ma
Ma
When all peripheral
clocks are OFF
3
*
0.59
0.51
When all peripheral
clocks are ON
Sleep
operation
(sub oscillation)
32kHz
Power supply
current
3
*
ICCS
VCC
When all peripheral
clocks are OFF
3
*
0.61
0.53
48
48
Ma
Ma
When all peripheral
clocks are ON
Sleep
operation
(built-in low-speed
CR)
100kHz
3
*
When all peripheral
clocks are OFF
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2
Document Number: 002-04918 Rev. *G
Page 75 of 160
CY9B160R Series
Table 12-8. Typical and maximum current consumption in STOP mode, TIMER mode and RTC mode
Value
Typ*1 Max*2
Pin
name
Parameter
Symbol
Conditions
Frequency
Unit
Ma
Remarks
*3, *4
0.33
1.8
TA = +25°C
*3, *4
TA = +85°C
*3, *4
TA = +105°C
*3, *4
TA = +25°C
*3, *4
TA = +85°C
*3, *4
TA = +105°C
*3, *4
TA = +25°C
ICCH
STOP mode
-
-
15
22
2.2
16
22
Ma
Ma
Ma
Ma
Ma
-
0.70
TIMER mode (built-in
high-speed CR)
4MHz
32kHz
-
-
0.33
-
1.8
15
Ma
Ma
Power supply
current
*3, *4
TA = +85°C
TIMER mode
(sub oscillation)
VCC
ICCT
*3, *4
TA = +105°C
*3, *4
TA = +25°C
*3, *4
TA = +85°C
*3, *4
TA = +105°C
*3, *4
TA = +25°C
*3, *4
TA = +85°C
*3, *4
TA = +105°C
-
22
1.8
15
22
1.8
15
22
Ma
Ma
Ma
Ma
Ma
Ma
Ma
0.34
TIMER mode
(built-in
low-speed CR)
100kHz
32kHz
-
-
0.33
RTC mode
(sub oscillation)
ICCR
-
-
*1: VCC = 3.3V
*2: VCC = 5.5V
*3: When all ports are fixed.
*4: When LVD is OFF
Document Number: 002-04918 Rev. *G
Page 76 of 160
CY9B160R Series
Table 12-9. Typical and maximum current consumption in Deep Standby STOP mode, Deep Standby RTC mode and VBAT
Value
Parameter
Symbol
Pin name
Conditions
Frequency
Unit
Remarks
Typ*1
Max*2
*3, *4
TA = +25°C
*3, *4
TA = +85°C
*3, *4
TA = +105°C
*3, *4
TA = +25°C
*3, *4
TA = +85°C
*3, *4
TA = +105°C
*3, *4
TA = +25°C
*3, *4
TA = +85°C
*3, *4
TA = +105°C
*3, *4
TA = +25°C
*3, *4
TA = +85°C
*3, *4
TA = +105°C
*3, *4, *5
TA = +25°C
*3, *4, *5
TA = +85°C
*3, *4, *5
TA = +105°C
*3, *4
29
140
Μa
Deep standby
STOP mode
(When RAM is
OFF)
-
644
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
Μa
-
1011
273
ICCHD
-
48
Deep standby
STOP mode
(When RAM is ON)
-
2676
4162
140
-
VCC
29
Deep standby
RTC mode
(When RAM is
OFF)
-
644
-
1011
273
Power supply
current
ICCRD
32kHz
48
Deep standby
RTC mode
(When RAM is ON)
-
2676
4162
0.29
5.77
10.6
22.6
35.2
41.8
-
0.015
RTC stop*6
-
-
ICCVBAT
VBAT
-
1.53
TA = +25°C
*3, *4
TA = +85°C
*3, *4
RTC operation*6
-
-
TA = +105°C
*1: VCC = 3.3V
*2: VCC = 5.5V
*3: When all ports are fixed.
*4: When LVD is OFF
*5: When sub oscillation is OFF
*6: In the case of setting RTC after VCC power on
Document Number: 002-04918 Rev. *G
Page 77 of 160
CY9B160R Series
Table 12-10. Typical and maximum current consumption in Low-voltage detection circuit, Main flash memory write/erase
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
Low-voltage
detection circuit
(LVD) power supply
current
For occurrence of
interrupt
ICCLVD
At operation
-
4
7
Μa
VCC
Main flash memory
write/erase current
ICCFLASH
At Write/Erase
At Write/Erase
-
-
13.4
11.5
15.9
13.6
Ma
Ma
Work flash memory
write/erase current
ICCWFLASH
Peripheral current dissipation
Frequency (MHz)
80
Clock system
Peripheral
Unit
Unit
Remarks
40
160
0.85
GPIO
All ports
0.22
0.74
0.32
0.14
0.93
0.16
0.55
0.43
1.48
0.61
0.27
1.81
0.34
1.09
DMAC
-
-
-
-
2.88
HCLK
DSTC
1.17
0.55
3.63
0.66
2.17
Ma
External bus I/F
SD card I/F
Base timer
4ch.
Multi-functional timer/PPG
1unit/4ch.
Quadrature
position/Revolution
counter
PCLK1
PCLK2
Ma
Ma
1unit
0.04
0.09
0.17
A/DC
1unit
1ch.
0.20
0.31
0.39
0.62
0.78
-
Muli-function serial
Document Number: 002-04918 Rev. *G
Page 78 of 160
CY9B160R Series
12.3.2 Pin Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin name
CMOS
hysteresis input
pin, MD0, MD1
5V tolerant
input pin
Input pin
doubled as I2C
Fm+
Conditions
Unit
Remarks
Min
VCC×0.8
Typ
Max
-
-
-
-
-
-
VCC + 0.3
V
V
V
“H” level input
voltage (hysteresis
input)
VIHS
VCC×0.8
VCC×0.7
VSS + 5.5
VSS + 5.5
CMOS
hysteresis input
pin, MD0, MD1
5V tolerant
input pin
Input pin
doubled as I2C
Fm+
-
-
-
VSS – 0.3
VSS – 0.3
VSS
-
-
-
VCC×0.2
VCC×0.2
VCC×0.3
V
V
V
“L” level input
voltage (hysteresis
input)
VILS
VCC ≥ 4.5 V,
IOH = - 4Ma
4Ma type
8Ma type
VCC – 0.5
VCC – 0.5
-
-
VCC
V
V
VCC < 4.5 V,
IOH = - 2Ma
VCC ≥ 4.5 V,
IOH = - 8Ma
VCC < 4.5 V,
IOH = - 4Ma
VCC ≥ 4.5 V,
IOH = - 12Ma
VCC
VOH
“H” level output
voltage
12Ma type
VCC – 0.5
VCC – 0.5
-
-
VCC
V
V
VCC < 4.5 V,
IOH = - 8Ma
VCC ≥ 4.5 V,
IOH = - 4Ma
VCC < 4.5 V,
IOH = - 3Ma
The pin
doubled as I2C
Fm+
VCC
At GPIO
Document Number: 002-04918 Rev. *G
Page 79 of 160
CY9B160R Series
Value
Typ
Parameter
Symbol
Pin name
Conditions
VCC ≥ 4.5 V,
Unit
Remarks
Min
Max
IOL = 4Ma
4Ma type
VSS
VSS
VSS
-
-
-
0.4
0.4
0.4
V
V
V
VCC < 4.5 V,
IOL = 2Ma
VCC ≥ 4.5 V,
IOH = 8Ma
8Ma type
VCC < 4.5 V,
IOH = 4Ma
“L” level output
voltage
VCC ≥ 4.5 V,
IOL = 12Ma
VOL
12Ma type
VCC < 4.5 V,
IOL = 8Ma
VCC ≥ 4.5 V,
IOH = 4Ma
At GPIO
The pin
doubled as
I2C Fm+
VCC < 4.5 V,
IOH = 3Ma
VSS
-
-
0.4
+ 5
V
VCC ≤ 5.5 V,
IOH = 20Ma
At I2C Fm+
Input leak current
IIL
-
-
- 5
25
30
Μa
Kω
VCC ≥ 4.5 V
VCC < 4.5 V
50
80
100
200
Pull-up resistor
value
RPU
Pull-up pin
Other than
VCC,
VBAT,
VSS,
Input capacitance
CIN
-
-
5
15
Pf
AVCC,
AVSS, AVRH
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Page 80 of 160
CY9B160R Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
4
4
4
4
48
20
48
20
When crystal oscillator is
connected
MHz
MHz
Input frequency
FCH
When using external clock
X0,
X1
20.83
50
250
Input clock cycle
tCYLH
-
ns
%
When using external clock
When using external clock
VCC < 4.5V
PWH/Tcylh,
PWL/Tcylh
250
Input clock pulse width
45
55
Input clock rising time and tCF,
-
-
-
-
5
ns
When using external clock
Base clock (HCLK/FCLK)
falling time
tCR
FCC
-
160
MHz
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
Internal operating clock*1
frequency
FCP0
FCP1
FCP2
-
-
-
-
-
-
-
-
-
80
MHz
MHz
MHz
160
80
-
-
-
-
-
-
-
-
6.25
12.5
6.25
12.5
-
-
-
-
ns
ns
ns
ns
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
tCYCC
Internal operating clock*1
cycle time
tCYCP0
tCYCP1
tCYCP2
APB2 bus clock*2
*1: For more information about each internal operating clock, see “Chapter: Clock” in “FM4 Family Peripheral Manual”.
*2: For about each APB bus which each peripheral is connected to, see “Block Diagram” in this datasheet.
X0
Document Number: 002-04918 Rev. *G
Page 81 of 160
CY9B160R Series
12.4.2 Sub Clock Input Characteristics
(VBAT = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal oscillator
is connected
When using external
clock
When using external
clock
-
-
32.768
-
kHz
kHz
μs
Input frequency
1/ tCYLL
-
-
32
10
-
-
100
X0A,
X1A
Input clock cycle
tCYLL
-
31.25
PWH/tCYLL
PWL/tCYLL
,
When using external
clock
Input clock pulse width
45
-
55
%
0.8 × VBAT
VBAT
VBAT
VBAT
X0A
VBAT
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
4.08
Tj = -20°C to + 105°C
Tj = - 40°C to + 125°C
Tj = - 40°C to + 125°C
-
3.92
3.88
3
4
Clock frequency
Clock frequency
FCRH
When trimming*1
4
4
4.12
5
MHz
FCRH
When not trimming
Frequency stabilization
time
2
tCRWT
-
-
30
μs
*
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use high-
speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min
Typ
Max
Clock frequency
FCRL
-
50
100
150
kHz
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Page 82 of 160
CY9B160R Series
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Unit
Remarks
Parameter
Symbol
Min
200
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
-
-
μs
4
16
PLL input clock frequency
PLL multiplication rate
FPLLI
-
-
-
-
-
MHz
13
200
-
80
multiplier
MHz
320
160
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLO
FCLKPLL
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see “Chapter: Clock” in “FM4 Family Peripheral Manual”.
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main
PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Unit
Remarks
Parameter
Symbol
Min
200
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
-
-
μs
PLL input clock frequency
PLL multiplication rate
FPLLI
-
3.8
50
190
-
4
-
4.2
75
MHz
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLO
FCLKPLL
-
320
160
-
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see “Chapter: Clock” in “FM4 Family Peripheral Manual”.
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has
been trimmed.
12.4.6 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Reset input time
Symbol
tINITX
Pin name
Condition
Unit
ns
Remarks
Min
Max
INITX
-
500
-
Document Number: 002-04918 Rev. *G
Page 83 of 160
CY9B160R Series
12.4.7 Power-on Reset Timing
(VSS = 0V, TA = -40°C to +85°C)
Value
Parameter
Symbol Pin Name
Conditions
Unit
Remarks
Min
50
Typ
Max
1
Power supply shut down time
Power ramp rate
tOFF
-
-
-
-
-
ms
*
Dv/dt
tPRT
VCC
VCC: 0.2V to 2.70V
-
1.3
1000 Mv/µs *2
0.60 ms
Time until releasing Power-on reset
0.33
*1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This Dv/dt characteristic is applied at the power-on of cold start (tOFF>50ms).
Note:
− If Toff cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary:
VDH: detection voltage of Low Voltage detection reset. See “12.7. Low-Voltage Detection Characteristics”.
12.4.8 GPIO Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Output frequency
*: GPIO is a target.
Symbol
tPCYCLE
Pin name
Conditions
Unit
MHz
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
-
-
50
32
Pxx*
MHz
Pxx
tPCYCLE
Document Number: 002-04918 Rev. *G
Page 84 of 160
CY9B160R Series
12.4.9 External Bus Timing
External bus clock output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Unit
Parameter
Symbol
Pin name
MCLKOUT*1
*1: The external bus clock (MCLKOUT) is a divided clock of HCLK.
Conditions
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
-
-
50*2
32*3
MHz
MHz
Output frequency
tCYCLE
For more information about setting of clock divider, see “Chapter: External Bus Interface” in “FM4 Family Peripheral Manual”.
*2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100MHz.
*3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64MHz.
0.8 × Vcc
0.8 × Vcc
MCLK
tCYCLE
External bus signal input/output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Remarks
VIH
VIL
0.8 × VCC
V
V
V
V
Signal input characteristics
0.2 × VCC
0.8 × VCC
0.2 × VCC
-
VOH
VOL
Signal output characteristics
VIH
VIL
VIH
VIL
Signal input
VOH
VOL
VOH
VOL
Signal output
Document Number: 002-04918 Rev. *G
Page 85 of 160
CY9B160R Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Unit
Parameter
Symbol
tOEW
tCSL – AV
Pin name
Conditions
VCC ≥ 4.5V
Min
Max
MOEX
MOEX
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Mininum pulse width
MCSX↓→Address output
delay time
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
-9
-12
+9
+12
MCSX[7:0],
MAD[24:0]
MOEX,
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
MOEX↑→Address hold time tOEH – AX
0
MAD[24:0]
MCLK×m-9
MCLK×m-12
MCSX↓→
MOEX↓ delay time
tCSL – OEL
MOEX,
MCSX[7:0]
MOEX↑→
MCSX↑ time
tOEH – CSH
0
MCLK×m-9
MCLK×m-12
MCSX↓→MDQM↓
tCSL – RDQML
MCSX,
delay time
MDQM[1:0]
20
38
MOEX,
Data set up→MOEX↑ time
tDS – OE
tDH – OE
tWEW
MADATA[15:0]
MOEX,
MADATA[15:0]
-
MOEX↑→
Data hold time
0
-
-
MWEX
MWEX
MCLK×n-3
0
Mininum pulse width
MWEX↑→Address output
delay time
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MWEX,
MAD[24:0]
tWEH – AX
MCLK×n-9
MCLK×n-12
MCSX↓→MWEX↓ delay time tCSL – WEL
MWEX↑→MCSX↑ delay time tWEH – CSH
MCSX↓→MDQM↓ delay time tCSL-WDQML
MWEX,
MCSX[7:0]
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCSX,
MDQM[1:0]
MCSX↓→
Data output time
MCSX,
tCSL-DX
tWEH – DX
MADATA[15:0]
MWEX,
MADATA[15:0]
MCLK-12
MCLK+12
MCLK×m+9
MCLK×m+12
MWEX↑→
Data hold time
0
Note:
When the external load capacitance CL = 30Pf (m = 0 to 15, n = 1 to 16)
−
Document Number: 002-04918 Rev. *G
Page 86 of 160
CY9B160R Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
tWEH-AX
MCSX[7:0]
MAD[24:0]
MOEX
tCSL-AV
tOEH-AX
tCSL-AV
Address
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
tDS-OE
tDH-OE
tWEH-DX
MADATA[15:0]
Invalid
RD
WD
tCSL-DX
Document Number: 002-04918 Rev. *G
Page 87 of 160
CY9B160R Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Unit
Parameter
Symbol
Pin name
Conditions
VCC ≥ 4.5V
Min
Max
9
MCLK,
Address delay time
tAV
1
1
1
1
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAD[24:0]
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
12
9
tCSL
tCSH
tREL
tREH
tDS
12
9
MCLK,
MCSX delay time
MOEX delay time
MCSX[7:0]
12
9
12
9
MCLK,
MOEX
12
19
37
Data set up
→MCLK↑ time
MCLK,
-
-
MADATA[15:0]
MCLK↑→
Data hold time
MCLK,
tDH
0
MADATA[15:0]
9
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
1
12
9
MCLK,
MWEX
MWEX delay time
1
12
9
1
12
9
MDQM[1:0]
delay time
MCLK,
MDQM[1:0]
1
12
MCLK+18
MCLK+24
18
MCLK↑→
Data output time
MCLK,
MCLK+1
1
MADATA[15:0]
MCLK↑→
Data hold time
MCLK,
MADATA[15:0]
24
Note:
−
When the external load capacitance CL = 30Pf
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
Address
MAD[24:0]
tREL
tREH
MOEX
tDQML
tDQMH
tDQML
tDQMH
MDQM[1:0]
tWEL
tWEH
MWEX
tDS
tDH
tOD
RD
Invalid
WD
MADATA[15:0]
tODS
Document Number: 002-04918 Rev. *G
Page 88 of 160
CY9B160R Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Unit
Parameter
Symbol
tALE-CHMADV
Pin name
Conditions
VCC ≥ 4.5V
Min
Max
10
20
Multiplexed address delay
time
0
ns
ns
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
MALE,
MADATA[15:0]
MCLK×n+0
MCLK×n+0
MCLK×n+10
MCLK×n+20
Multiplexed address hold
time
tCHMADH
Note:
−
When the external load capacitance CL = 30Pf (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04918 Rev. *G
Page 89 of 160
CY9B160R Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
tCHAL
Pin name
Conditions
Unit
ns
Remarks
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
9
1
1
12
9
ns
ns
ns
MCLK,
MALE delay time
ALE
tCHAH
12
VCC ≥ 4.5V
MCLK↑→
Multiplexed address delay
time
tCHMADV
1
1
tOD
ns
ns
VCC < 4.5V
VCC ≥ 4.5V
MCLK,
MADATA[15:0]
MCLK↑→
Multiplexed data output time
tCHMADX
tOD
VCC < 4.5V
Note:
−
When the external load capacitance CL = 30Pf
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04918 Rev. *G
Page 90 of 160
CY9B160R Series
NAND Flash Mode
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Unit
Symbol
tNREW
Pin name
MNREX
Conditions
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
MNREX
Min pulse width
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
38
-
-
Data set up
→MNREX↑ time
MNREX↑→
MNREX,
MADATA[15:0]
tDS – NRE
MNREX,
MADATA[15:0]
MNALE,
tDH – NRE
0
-
Data hold time
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MNALE↑→
MNWEX delay time
MNALE↓→
tALEH – NWEL
tALEL – NWEL
tCLEH – NWEL
tNWEH – CLEL
tNWEW
MNWEX
MNALE,
MNWEX
MNWEX delay time
MNCLE↑→
MNWEX delay time
MNWEX↑→
MNCLE,
MNWEX
MNCLE,
MNWEX
0
MNCLE delay time
MNWEX
Min pulse width
MNWEX↓→
MNWEX
MCLK×n-3
-
- 9
-12
+ 9
+12
MCLK×m+9
MCLK×m+12
MNWEX,
MADATA[15:0]
tNWEL – DV
tNWEH – DX
Data output time
MNWEX↑→
Data hold time
MNWEX,
MADATA[15:0]
0
Note:
−
When the external load capacitance CL = 30Pf (m = 0 to 15, n = 1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
Document Number: 002-04918 Rev. *G
Page 91 of 160
CY9B160R Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
Document Number: 002-04918 Rev. *G
Page 92 of 160
CY9B160R Series
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin name
MCLK,
Conditions
Unit
Remarks
Min
Max
MCLK↑
VCC ≥ 4.5V
VCC < 4.5V
19
37
MRDY input
setup time
tRDYI
-
ns
MRDY
When RDY is input
···
MCLK
Over 2cycle
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycle
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-04918 Rev. *G
Page 93 of 160
CY9B160R Series
SDRAM Mode
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Unit
Parameter
Symbol
tCYCSD
Pin name
MSDCLK
Min
Max
Output frequency
-
32
12
MHz
ns
MSDCLK,
MAD[15:0]
Address delay time
tAOSD
2
MSDCLK,
MADATA[31:0]
MSDCLK↑→Data output delay time
tDOSD
2
2
1
2
2
2
2
2
23
0
12
20
12
12
12
12
12
12
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSDCLK↑→Data output
Hi-Z time
MSDCLK,
MADATA[31:0]
tDOZSD
tWROSD
tMCSSD
tRASSD
tCASSD
tMWESD
tCKESD
tDSSD
MSDCLK,
MDQM[1:0]
MDQM[1:0] delay time
MCSX delay time
MRASX delay time
MCASX delay time
MSDWEX delay time
MSDCKE delay time
Data set up time
MSDCLK,
MCSX8
MSDCLK,
MRASX
MSDCLK,
MCASX
MSDCLK,
MSDWEX
MSDCLK,
MSDCKE
MSDCLK,
MADATA[31:0]
MSDCLK,
MADATA[31:0]
Data hold time
tDHSD
-
Note:
When the external load capacitance CL = 30Pf
−
Document Number: 002-04918 Rev. *G
Page 94 of 160
CY9B160R Series
SDRAM Access
tCYCSD
MSDCLK
MAD[24:0]
MDQM[1:0]
MCSX
tAOSD
Address
tWROSD
tMCSSD
tRASSD
MRASX
tCASSD
tMWESD
tCKESD
MCASX
MSDWEX
MSDCKE
tDSSD
RD
tDHSD
MADATA[15:0]
MADATA[15:0]
tDOSD
tDOZSD
WD
Document Number: 002-04918 Rev. *G
Page 95 of 160
CY9B160R Series
12.4.10 Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin name
TIOAn/TIOBn
(when using as ECK,
TIN)
Conditions
Unit
Remarks
Min
2tCYCP
Max
tTIWH
,
Input pulse width
-
-
ns
tTIWL
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
tTRGH
Pin name
TIOAn/TIOBn
Conditions
Unit
ns
Remarks
Min
2tCYCP
Max
,
Input pulse width
-
-
tTRGL
(when using as TGIN)
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see “Block Diagram” in this datasheet.
Document Number: 002-04918 Rev. *G
Page 96 of 160
CY9B160R Series
12.4.11 CSIO/UART Timing
Synchronous serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min Max
VCC ≥ 4.5V
Unit
Pin
name
Parameter
Symbol
Conditions
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK↓→SOT delay time
tSLOVI
tIVSHI
tSHIXI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
Internal shift clock
operation
SIN→SCK↑
setup time
-
-
-
-
SCK↑→SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
tSLSH
tSHSL
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
2tCYCP – 10
tCYCP + 10
-
-
2tCYCP – 10
tCYCP + 10
-
-
ns
ns
SCK↓→SOT delay time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
External shift
clock
operation
SIN→SCK↑
setup time
10
20
10
20
SCKx,
SINx
SCK↑→SIN hold time
-
-
SCK falling time
SCK rising time
Tf
Tr
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30Pf.
Document Number: 002-04918 Rev. *G
Page 97 of 160
CY9B160R Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 98 of 160
CY9B160R Series
Synchronous serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
Internal shift clock
operation
SIN→SCK↓
setup time
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
tIVSLI
50
0
-
-
30
0
-
-
ns
ns
SCK↓→SIN hold time
tSLIXI
tSLSH
tSHSL
Serial clock “L” pulse width
Serial clock “H” pulse width
2tCYCP – 10
tCYCP + 10
-
-
2tCYCP – 10
tCYCP + 10
-
-
ns
ns
SCK↑→SOT delay time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
SIN→SCK↓
setup time
External shift clock
operation
10
20
10
20
SCKx,
SINx
SCK↓→SIN hold time
-
-
SCK falling time
SCK rising time
Tf
Tr
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30Pf.
Document Number: 002-04918 Rev. *G
Page 99 of 160
CY9B160R Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
VIH
SCK
SOT
VIL
VIL
tR
VIL
tF
tSHOVE
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
SIN
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 100 of 160
CY9B160R Series
Synchronous serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Unit
Pin
name
Parameter
Symbol
Conditions
Min
Max
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
SIN→SCK↓
setup time
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
Internal shift clock
operation
tIVSLI
tSLIXI
tSOVLI
50
-
-
-
30
0
-
-
-
ns
ns
ns
SCK↓→SIN hold time
SOT→SCK↓ delay time
0
2tCYCP
30
2tCYCP
10
–
–
2tCYCP – 30
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK↑→SOT delay time
tSLSH
tSHSL
tSHOVE
SCKx
2tCYCP – 10
tCYCP + 10
-
-
-
ns
ns
ns
SCKx
SCKx,
SOTx
SCKx,
SINx
-
tCYCP + 10
-
50
-
30
External shift
clock operation
SIN→SCK↓
setup time
tIVSLE
tSLIXE
10
20
-
-
10
20
-
-
ns
ns
SCKx,
SINx
SCK↓→SIN hold time
SCK falling time
SCK rising time
Tf
Tr
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
−
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30Pf.
Document Number: 002-04918 Rev. *G
Page 101 of 160
CY9B160R Series
tSCYC
VOH
VOL
VOL
SCK
SOT
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
SIN
MS bit = 0
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 002-04918 Rev. *G
Page 102 of 160
CY9B160R Series
Synchronous serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
4tCYCP
-
4tCYCP
-
SCK↓→SOT delay time
tSLOVI
tIVSHI
tSHIXI
tSOVHI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
- 30
+ 30
- 20
30
0
+ 20
ns
ns
ns
ns
ns
ns
ns
ns
ns
SIN→SCK↑
setup time
Internal shift clock
operation
50
-
-
SCK↑→SIN hold time
0
-
-
2tCYCP
30
2tCYCP
10
tCYCP
10
–
–
SOT→SCK↑ delay time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK↓→SOT delay time
2tCYCP – 30
-
-
SCKx
SCKx
2tCYCP – 10
-
-
+
tCYCP + 10
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
50
-
-
30
-
External shift clock
operation
SIN→SCK↑
setup time
10
20
10
20
SCK↑→SIN hold time
-
-
SCK falling time
SCK rising time
Tf
Tr
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30Pf.
Document Number: 002-04918 Rev. *G
Page 103 of 160
CY9B160R Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
SCK
VIH
VIH
VIH
VIL
VIL
VIL
tSLOVE
SOT
SIN
VOH
VOL
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 104 of 160
CY9B160R Series
When using synchronous serial chip select (SCINV = 0, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min Max
(*1)-50 (*1)+0
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
(*1)-50
Max
(*1)+0
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
ns
ns
Internal shift
clock operation
(*2)+0
(*2)+50
(*2)+0
(*2)+50
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
3tCYCP+30
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock operation
3tCYCP+30
-
3tCYCP+30
-
SCS↓→SUT delay time
SCS↑→SUT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
When the external load capacitance CL = 30Pf.
−
−
Document Number: 002-04918 Rev. *G
Page 105 of 160
CY9B160R Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 106 of 160
CY9B160R Series
When using synchronous serial chip select (SCINV = 1, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min Max
(*1)-50 (*1)+0
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
(*1)-50
Max
(*1)+0
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
tCSSI
tCSHI
ns
ns
Internal shift
clock operation
(*2)+0
(*2)+50
(*2)+0
(*2)+50
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
3tCYCP+30
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock operation
3tCYCP+30
-
3tCYCP+30
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
When the external load capacitance CL = 30Pf.
−
−
Document Number: 002-04918 Rev. *G
Page 107 of 160
CY9B160R Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 108 of 160
CY9B160R Series
When using synchronous serial chip select (SCINV = 0, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min Max
(*1)-50 (*1)+0
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
(*1)-50
Max
(*1)+0
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
tCSSI
tCSHI
ns
ns
Internal shift
clock operation
(*2)+0
(*2)+50
(*2)+0
(*2)+50
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
3tCYCP+30
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock operation
3tCYCP+30
-
3tCYCP+30
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
When the external load capacitance CL = 30Pf.
−
−
Document Number: 002-04918 Rev. *G
Page 109 of 160
CY9B160R Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 110 of 160
CY9B160R Series
When using synchronous serial chip select (SCINV = 1, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min Max
(*1)-50 (*1)+0
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
(*1)-50
Max
(*1)+0
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
tCSSI
tCSHI
ns
ns
Internal shift
clock operation
(*2)+0
(*2)+50
(*2)+0
(*2)+50
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
3tCYCP+30
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock operation
3tCYCP+30
-
3tCYCP+30
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
When the external load capacitance CL = 30Pf.
−
−
Document Number: 002-04918 Rev. *G
Page 111 of 160
CY9B160R Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 112 of 160
CY9B160R Series
High-speed synchronous serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min Max
VCC ≥ 4.5V
Pin
Parameter
Serial clock cycle time
SCK↓→SOT delay time
Symbol
tSCYC
Conditions
Unit
name
Min
4tCYCP
Max
SCKx
4tCYCP
-
-
ns
ns
SCKx,
SOTx
tSLOVI
-10
+10
-10
+10
-
Internal shift clock
operation
14
SIN→SCK↑
setup time
SCKx,
SINx
tIVSHI
-
12.5
ns
12.5*
SCKx,
SINx
SCK↑→SIN hold time
tSHIXI
tSLSH
tSHSL
5
-
-
-
5
-
-
-
ns
ns
ns
Serial clock “L” pulse width
Serial clock “H” pulse width
SCKx
SCKx
2tCYCP – 5
tCYCP + 10
2tCYCP – 5
tCYCP + 10
SCKx,
SOTx
SCK↓→SOT delay time
tSLOVE
tIVSHE
tSHIXE
-
15
-
-
15
-
ns
ns
ns
External shift clock
operation
SIN→SCK↑
setup time
SCKx,
SINx
5
5
5
5
SCKx,
SINx
SCK↑→SIN hold time
-
-
SCK falling time
SCK rising time
Tf
Tr
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
These characteristics only guarantee the following pins.
−
−
−
−
No chip select:
Chip select:
SIN4_1, SOT4_1, SCK4_1
SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30Pf. (For *, when CL = 10Pf)
Document Number: 002-04918 Rev. *G
Page 113 of 160
CY9B160R Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 114 of 160
CY9B160R Series
High-speed synchronous serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min Max
VCC ≥ 4.5V
Pin
name
Parameter
Symbol
Conditions
Unit
Min
Max
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-10
-
4tCYCP
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
+10
-10
+10
Internal shift clock
operation
14
SIN→SCK↓
setup time
SCKx,
SINx
tIVSLI
-
12.5
-
12.5*
SCKx,
SINx
SCK↓→SIN hold time
tSLIXI
5
-
5
-
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK↑→SOT delay time
tSLSH
tSHSL
tSHOVE
tIVSLE
tSLIXE
SCKx
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
tCYCP + 10
-
tCYCP + 10
-
SCKx,
SOTx
-
15
-
-
15
-
External shift clock
operation
SIN→SCK↓
setup time
SCKx,
SINx
5
5
5
5
SCKx,
SINx
SCK↓→SIN hold time
-
-
SCK falling time
SCK rising time
Tf
Tr
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
These characteristics only guarantee the following pins.
−
−
−
−
No chip select:
Chip select:
SIN4_1, SOT4_1, SCK4_1
SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30Pf. (For *, when CL = 10Pf)
Document Number: 002-04918 Rev. *G
Page 115 of 160
CY9B160R Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 116 of 160
CY9B160R Series
High-speed synchronous serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min Max
VCC ≥ 4.5V
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
Serial clock cycle time
tSCYC
tSHOVI
tIVSLI
SCKx
4tCYCP
-10
-
4tCYCP
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKx,
SOTx
SCK↑→SOT delay time
+10
-10
+10
14
Internal shift clock
operation
SIN→SCK↓
setup time
SCKx,
SINx
-
12.5
-
12.5*
SCKx,
SINx
SCK↓→SIN hold time
tSLIXI
5
-
5
-
SCKx,
SOTx
SOT→SCK↓ delay time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK↑→SOT delay time
tSOVLI
tSLSH
tSHSL
tSHOVE
tIVSLE
tSLIXE
2tCYCP – 10
-
2tCYCP – 10
-
SCKx
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
tCYCP + 10
-
tCYCP + 10
-
SCKx,
SOTx
-
15
-
-
15
-
External shift clock
operation
SIN→SCK↓
setup time
SCKx,
SINx
5
5
5
5
SCKx,
SINx
SCK↓→SIN hold time
-
-
SCK falling time
SCK rising time
Tf
Tr
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
These characteristics only guarantee the following pins.
−
−
−
−
No chip select:
Chip select:
SIN4_1, SOT4_1, SCK4_1
SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30Pf. (For *, when CL = 10Pf)
Document Number: 002-04918 Rev. *G
Page 117 of 160
CY9B160R Series
tSCYC
VOH
VOL
VOL
SCK
SOT
SIN
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
tF
VIH
VIL
VIH
SCK
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 002-04918 Rev. *G
Page 118 of 160
CY9B160R Series
High-speed synchronous serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min Max
VCC ≥ 4.5V
Pin
name
Parameter
Symbol
Conditions
Unit
Min
Max
Internal shift clock operation
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
SCKx
4tCYCP
-10
-
4tCYCP
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKx,
SOTx
SCK↓→SOT delay time
+10
-10
+10
14
SIN→SCK↑
setup time
SCKx,
SINx
Internal shift clock
operation
-
12.5
-
12.5*
SCKx,
SINx
SCK↑→SIN hold time
5
-
5
-
SCKx,
SOTx
SOT→SCK↑ delay time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK↓→SOT delay time
2tCYCP – 10
-
2tCYCP – 10
-
SCKx
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
tCYCP + 10
-
tCYCP + 10
-
SCKx,
SOTx
-
15
-
-
15
-
External shift clock
operation
SIN→SCK↑
setup time
SCKx,
SINx
5
5
5
5
SCKx,
SINx
SCK↑→SIN hold time
-
-
SCK falling time
SCK rising time
Tf
Tr
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
These characteristics only guarantee the following pins.
−
−
−
−
No chip select:
Chip select:
SIN4_1, SOT4_1, SCK4_1
SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30Pf. (For *, when CL = 10Pf)
Document Number: 002-04918 Rev. *G
Page 119 of 160
CY9B160R Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
SCK
VIH
VIH
VIH
VIL
VIL
VIL
tSLOVE
SOT
SIN
VOH
VOL
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 120 of 160
CY9B160R Series
When using high-speed synchronous serial chip select (SCINV = 0, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
(*1)-20
Max
(*1)+0
Min
(*1)-20
Max
(*1)+0
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
ns
ns
Internal shift clock
operation
(*2)+0
(*2)+20
(*2)+0
(*2)+20
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+15
-
3tCYCP+15
-
ns
ns
ns
ns
ns
0
-
0
-
External shift clock
operation
3tCYCP+15
-
3tCYCP+15
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
25
-
-
25
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
When the external load capacitance CL = 30Pf.
−
−
Document Number: 002-04918 Rev. *G
Page 121 of 160
CY9B160R Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 122 of 160
CY9B160R Series
When using high-speed synchronous serial chip select (SCINV = 1, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
(*1)-20
Max
(*1)+0
Min
(*1)-20
Max
(*1)+0
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
tCSSI
tCSHI
ns
ns
Internal shift
clock operation
(*2)+0
(*2)+20
(*2)+0
(*2)+20
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+15
-
3tCYCP+15
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock operation
3tCYCP+15
-
3tCYCP+15
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
25
-
-
25
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
When the external load capacitance CL = 30Pf.
−
−
Document Number: 002-04918 Rev. *G
Page 123 of 160
CY9B160R Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 124 of 160
CY9B160R Series
When using high-speed synchronous serial chip select (SCINV = 0, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
(*1)-20
Max
(*1)+0
Min
(*1)-20
Max
(*1)+0
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
tCSSI
tCSHI
ns
ns
Internal shift clock
operation
(*2)+0
(*2)+20
(*2)+0
(*2)+20
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+15
-
3tCYCP+15
-
ns
ns
ns
ns
ns
0
-
0
-
External shift clock
operation
3tCYCP+15
-
3tCYCP+15
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
25
-
-
25
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
When the external load capacitance CL = 30Pf.
−
−
Document Number: 002-04918 Rev. *G
Page 125 of 160
CY9B160R Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 126 of 160
CY9B160R Series
When using high-speed synchronous serial chip select (SCINV = 1, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
(*1)-20
Max
(*1)+0
Min
(*1)-20
Max
(*1)+0
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
tCSSI
tCSHI
ns
ns
Internal shift
clock operation
(*2)+0
(*2)+20
(*2)+0
(*2)+20
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+15
-
3tCYCP+15
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock operation
3tCYCP+15
-
3tCYCP+15
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
25
-
-
25
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
When the external load capacitance CL = 30Pf.
−
−
Document Number: 002-04918 Rev. *G
Page 127 of 160
CY9B160R Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04918 Rev. *G
Page 128 of 160
CY9B160R Series
External clock (EXT = 1) : when in asynchronous mode only
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
tSLSH
Condition
Unit
ns
Remarks
Min
tCYCP + 10
Max
Serial clock “L” pulse width
Serial clock “H” pulse width
-
tSHSL
tCYCP + 10
-
ns
ns
ns
CL = 30Pf
SCK falling time
SCK rising time
Tf
-
-
5
5
Tr
tR
VIL
tF
VIH
tSHSL
tSLSH
SCK
VIH
VIH
VIL
VIL
Document Number: 002-04918 Rev. *G
Page 129 of 160
CY9B160R Series
12.4.12 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Min
Parameter
Symbol
Pin name
ADTG
Conditions
Unit
Remarks
Max
A/D converter trigger input
1
-
2tCYCP
*
-
ns
FRCKx
Free-run timer input clock
Input capture
Input pulse
width
tINH
,
Icxx
tINL
1
DTTIxX
INT00 to INT31,
NMIX
-
-
-
2tCYCP
*
-
-
-
-
ns
ns
ns
ns
Waveform generator
External interrupt,
NMI
2tCYCP + 100*1
500*2
WKUPx
500*3
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to,
see “Block Diagram” in this data sheet.
*2: When in STOP mode, in timer mode.
*3: When in deep standby RTC mode, in deep standby STOP mode.
Document Number: 002-04918 Rev. *G
Page 130 of 160
CY9B160R Series
12.4.13 Quadrature Position/Revolution Counter Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Unit
Parameter
AIN pin “H” width
AIN pin “L” width
BIN pin “H” width
Symbol
tAHL
tALL
tBHL
tBLL
Conditions
Min
Max
-
-
-
-
BIN pin “L” width
BIN rising time from
AIN pin “H” level
AIN falling time from
BIN pin “H” level
BIN falling time from
AIN pin “L” level
AIN rising time from
BIN pin “L” level
AIN rising time from
BIN pin “H” level
BIN falling time from
AIN pin “H” level
AIN falling time from
BIN pin “L” level
BIN rising time from
AIN pin “L” level
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
2tCYCP
*
-
ns
ZIN pin “H” width
ZIN pin „L“ width
tZHL
tZLL
QCR:CGSC = “0”
QCR:CGSC = “0”
AIN/BIN rising and falling time from
determined ZIN level
Determined ZIN level from AIN/BIN
rising and falling time
tZABE
tABEZ
QCR:CGSC = “1”
QCR:CGSC = “1”
*: tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see “Block Diagram” in this data
sheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
Document Number: 002-04918 Rev. *G
Page 131 of 160
CY9B160R Series
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-04918 Rev. *G
Page 132 of 160
CY9B160R Series
2
12.4.14 I C Timing
Standard-mode, Fast-mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Standard-mode
Min Max
100
Fast-mode
Parameter
Symbol
FSCL
Conditions
Unit
Remarks
Min
Max
400
SCL clock frequency
0
0
kHz
(Repeated) START condition
hold time
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCL clock “L” width
SCL clock “H” width
tLOW
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tHIGH
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTA
4.7
0
-
0.6
-
μs
CL = 30Pf,
R = (Vp/IOL)*1
tHDDAT
tSUDAT
tSUSTO
3.45*2
0
0.9*3
μs
ns
μs
250
4.0
-
-
100
0.6
-
-
Bus free time between
“STOP condition” and
“START condition”
tBUF
4.7
-
1.3
-
μs
2MHz ≤
tCYCP<40MHz
40MHz ≤
tCYCP<60MHz
60MHz ≤
tCYCP<80MHz
80MHz ≤
tCYCP<100MHz
100MHz ≤
tCYCP<120MHz
120MHz ≤
tCYCP<140MHz
140MHz ≤
tCYCP<160MHz
160MHz ≤
4
4
4
4
4
4
4
4
2tCYCP
4tCYCP
6tCYCP
8tCYCP
*
*
*
*
-
-
-
-
-
-
-
-
2tCYCP
4tCYCP
6tCYCP
8tCYCP
*
*
*
*
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Noise filter
tSP
*5
4
4
4
4
4
4
4
4
10tCYCP
12tCYCP
14tCYCP
16tCYCP
*
*
*
*
10tCYCP
12tCYCP
14tCYCP
16tCYCP
*
*
*
*
tCYCP<180MHz
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least “L” period (tLOW) of device’s SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
“tSUDAT ≥ 250 ns”.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see “Block Diagram” in this data sheet.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
Document Number: 002-04918 Rev. *G
Page 133 of 160
CY9B160R Series
Fast-mode Plus (Fm+)
(VCC = 2.7V to 5.5V, VSS = 0V)
Fast-mode Plus (Fm+)*6
Parameter
Symbol
FSCL
Conditions
Unit
Remarks
Min
Max
1000
SCL clock frequency
0
kHz
μs
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHDSTA
0.26
-
SCL clock “L” width
SCL clock “H” width
SCL clock frequency
tLOW
0.5
-
-
-
μs
μs
μs
tHIGH
tSUSTA
0.26
0.26
(Repeated) START condition hold time
SDA ↓ → SCL ↓
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
CL = 30Pf,
tHDDAT
tSUDAT
tSUSTO
0
0.45*2, *3
μs
ns
μs
R = (Vp/IOL)*1
50
0.26
-
-
Bus free time between
“STOP condition” and
“START condition”
tBUF
0.5
-
μs
60MHz ≤
tCYCP<80MHz
80MHz ≤
tCYCP<100MHz
100MHz ≤
tCYCP<120MHz
120MHz ≤
tCYCP<140MHz
140MHz ≤
tCYCP<160MHz
160MHz ≤
4
6 tCYCP
*
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
4
8 tCYCP
*
4
4
4
4
10 tCYCP
12 tCYCP
14 tCYCP
16 tCYCP
*
*
*
*
Noise filter
tSP
*5
tCYCP<180MHz
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least “L” period (tLOW) of device’s SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
“tSUDAT ≥ 250 ns”.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see “Block Diagram” in this data sheet.
To use Fast-mode Plus (Fm+), set the peripheral bus clock at 64 MHz or more.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
*6: When using Fast-mode Plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register.
See “Chapter: I/O Port” in “FM4 Family Peripheral Manual” for the details.
SDA
SCL
Document Number: 002-04918 Rev. *G
Page 134 of 160
CY9B160R Series
12.4.15 SD Card Interface Timing
Default-Speed Mode
◼Clock CLK (All values are referred to VIH and VIL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Parameter
Symbol
Pin name
S_CLK
Conditions
Remarks
Max
Min
Clock frequency Data Transfer Mode
Clock frequency Identification Mode
fPP
fOD
0
16
MHz
S_CLK
0*/100
400
kHz
CCARD ≤ 10Pf
(1card)
Clock low time
Clock high time
Clock rising time
Clock falling time
tWL
S_CLK
S_CLK
S_CLK
S_CLK
10
10
-
-
-
10
10
ns
ns
ns
ns
tWH
tTLH
tTHL
-
*: 0Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required.
◼Card Inputs CMD, DAT (referenced to Clock CLK)
Value
Parameter
Input set-up time
Input hold time
Symbol
Pin name
Conditions
Remarks
Min
Max
S_CMD,
S_DATA3:0
S_CMD,
tISU
tIH
5
5
-
-
ns
ns
CCARD ≤ 10Pf
(1card)
S_DATA3:0
◼Card Outputs CMD, DAT (referenced to Clock CLK)
Value
Parameter
Symbol
Pin name
Conditions
Remarks
Min
Max
Output Delay time during Data
Transfer Mode
Output Delay time durinn Identification
Mode
S_CMD,
S_DATA3:0
S_CMD,
tODLY
tODLY
0
0
22
50
ns
ns
CCARD ≤ 40Pf
(1card)
S_DATA3:0
tWH
tWL
S_CLK
VIH
VIH
VIH
VIL
(SD Clock)
VIL
tTLH
tTHL
tIH
tISU
S_CMD,
VIH
VIL
VIH
VIL
S_DATA3:0
(Card Input)
tODLY(Min)
tODLY(Max)
S_CMD,
VOH
VOL
VOH
VOL
S_DATA3:0
(Card Output)
Defalt-Speed Mode
Note:
−
The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the
Host.
Document Number: 002-04918 Rev. *G
Page 135 of 160
CY9B160R Series
High-Speed Mode
◼Clock CLK (All values are referred to VIH and VIL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Parameter
Symbol
Pin name
S_CLK
Conditions
Remarks
Max
Min
Clock frequency Data Transfer Mode
fPP
0
32
MHz
Clock low time
Clock high time
Clock rising time
Clock falling time
tWL
S_CLK
S_CLK
S_CLK
S_CLK
7
7
-
-
-
3
3
ns
ns
ns
ns
CCARD ≤ 10Pf
(1card)
tWH
tTLH
tTHL
-
◼Card Inputs CMD, DAT (referenced to Clock CLK)
Value
Parameter
Input set-up time
Input hold time
Symbol
Pin name
Conditions
Remarks
Min
Max
S_CMD,
S_DATA3:0
S_CMD,
tISU
tIH
8
2
-
-
ns
ns
CCARD ≤ 10Pf
(1card)
S_DATA3:0
◼Card Outputs CMD, DAT (referenced to Clock CLK)
Value
Parameter
Symbol
Pin name
Conditions
Remarks
Min
Max
Output Delay time during Data
Transfer Mode
S_CMD,
S_DATA3:0
S_CMD,
CL ≤ 40Pf
(1card)
CL ≥ 15Pf
(1card)
tODLY
tOH
-
22
ns
ns
Pf
Output Hold time
2.5
-
-
S_DATA3:0
Total System capacitance for each
line*
CL
-
1card
40
*: In order to satisfy severe timing, host shall drive only one card.
tWH
tWL
VIH
VIH
VIH
S_CLK
50%VCC
50%VCC
tIH
VIL
VIL
(SD Clock)
tTLH
tTHL
tISU
S_CMD,
VIH
VIL
VIH
VIL
S_DATA3:0
(Card Input)
tOH(Min)
tODLY(Max)
S_CMD,
VOH
VOL
VOH
VOL
S_DATA3:0
(Card Output)
High-Speed Mode
Notes:
−
The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the
Host.
−
In high-speed mode, set the Clock frequency (Fpp) and the AHB Bus Clock frequency to the same values.
Document Number: 002-04918 Rev. *G
Page 136 of 160
CY9B160R Series
12.4.16 ETM Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin name
TRACECLK,
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
2
2
-
9
Data hold
tETMH
ns
TRACED[3:0]
15
50
32
-
MHz
MHz
ns
TRACECLK
frequency
1/ tTRACE
-
TRACECLK
20
TRACECLK
clock cycle
tTRACE
31.25
-
ns
Note:
−
When the external load capacitance CL = 30Pf.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-04918 Rev. *G
Page 137 of 160
CY9B160R Series
12.4.17 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
TMS, TDI setup time
TMS, TDI hold time
TDO delay time
Symbol
tJTAGS
Pin name
TCK,
Conditions
VCC ≥ 4.5V
Unit
ns
Remarks
Min
Max
15
15
-
-
TMS, TDI
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
TCK,
TMS, TDI
tJTAGH
tJTAGD
ns
ns
-
-
25
45
TCK,
TDO
Note:
−
When the external load capacitance CL = 30Pf.
TCK
TMS/TDI
TDO
Document Number: 002-04918 Rev. *G
Page 138 of 160
CY9B160R Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Value
Typ
Parameter
Resolution
Symbol
Pin name
Unit
bit
Remarks
Min
Max
-
-
-
-
-
-
-
-
-
12
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition
voltage
-
-
- 4.5
-2.5
- 15
+ 4.5
+ 2.5
+ 15
LSB
LSB
Mv
AVRH = 2.7V to
5.5V
VZT
Anxx
VFST
Anxx
-
AVRH – 15
-
AVRH + 15
-
Mv
μs
Conversion time
-
0.5*1
0.15
0.3
-
-
-
-
-
AVCC ≥ 4.5V
AVCC ≥ 4.5V
AVCC < 4.5V
AVCC ≥ 4.5V
AVCC < 4.5V
Sampling time*2
Ts
-
-
10
μs
25
1000
1000
Compare clock cycle*3
Tcck
ns
μs
50
State transition time to
operation permission
Tstt
-
-
-
-
1.0
-
-
0.69
1.0
0.92
18
Ma
Μa
A/D 1unit operation
When A/D stop
Power supply current
(analog + digital)
AVCC
A/D 1unit operation
AVRH = 5.5V
Reference power supply
current
(AVRH)
1.1
0.3
1.97
6.3
Ma
Μa
-
AVRH
-
-
-
When A/D stop
Analog input capacity
CAIN
-
12.05
Pf
1.2
1.8
4
AVCC ≥ 4.5V
AVCC < 4.5V
Analog input resistance
Interchannel disparity
RAIN
-
-
-
-
-
-
-
Kω
LSB
Μa
V
-
-
-
Analog port input leak
current
Anxx
Anxx
5
Analog input voltage
-
-
AVSS
4.5
-
-
-
AVRH
AVCC
AVCC
Tcck < 50ns
Tcck ≥ 50ns
Reference voltage
AVRH
V
2.7
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 150ns, the value of compare time: 350ns
(AVCC ≥ 4.5V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting*4 of sampling
time and compare clock cycle, see “Chapter: A/D Converter” in “FM4 Family PERIPHERAL MANUAL Analog Macro Part”. The
register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at
Base clock (HCLK).
*2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1).
*3: The compare time (Tc) is the value of (Equation 2).
*4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock
are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see “Block Diagram”
in this data sheet.
Document Number: 002-04918 Rev. *G
Page 139 of 160
CY9B160R Series
ANxx
Comparator
Rext
RAIN
Analog input pin
Analog signal
source
CAIN
(Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9
Ts:
Sampling time
RAIN
:
Input resistance of A/D = 1.2Kω at 4.5V < AVCC < 5.5V
Input resistance of A/D = 1.8Kω at 2.7V < AVCC < 4.5V
Input capacity of A/D = 12.05Pf at 2.7V < AVCC < 5.5V
Output impedance of external circuit
CAIN
:
Rext:
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Compare clock cycle
Tcck:
Document Number: 002-04918 Rev. *G
Page 140 of 160
CY9B160R Series
Definition of 12-bit A/D Converter Terms
◼Resolution:
Analog variation that is recognized by an A/D converter.
◼Integral Nonlinearity:
Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001)
and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual
conversion characteristics.
◼Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to change the output code
by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actual
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Asured
value)
Ideal characteristics
0x001
ly-measured value)
Analog input
VZT
Actual conversion characteristics
AVss
AVRH
AVss
AVRH
Analog input
VNT – {1LSB × (N – 1) +
VZT
}
Integral Nonlinearity of digital output N
=
[LSB]
1LSB
V(N + 1) T – VNT
1LSB
Differential Nonlinearity of digital output N
VFST – VZT
=
- 1 [LSB]
1LSB
=
4094
N:
A/D converter digital output value.
VZT:
VFST
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0Xffe to 0Xfff.
Voltage at which the digital output changes from 0x(N – 1) to 0Xn.
:
VNT
:
Document Number: 002-04918 Rev. *G
Page 141 of 160
CY9B160R Series
12.6 12-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7Vto5.5V, VSS = AVSS = 0V)
Value
Typ
Pin
name
Parameter
Resolution
Symbol
Unit
bit
Remarks
Min
Max
12
-
-
-
tc20
tc100
INL
0.56
2.79
- 16
0.69
3.42
-
0.81
4.06
+ 16
μs
Load 20Pf
Conversion time
μs
Load 100Pf
Integral Nonlinearity*
LSB
Dax
Differential Nonlinearity*
DNL
- 0.98
-
- 20.0
3.10
2.0
-
+ 1.5
10.0
+ 1.4
4.50
-
LSB
Mv
Mv
Kω
MΩ
Μa
Μa
-
-
When setting 0x000
When setting 0Xfff
D/A operation
When D/A stop
D/A 1unit operation AVCC = 3.3V
D/A 1unit operation AVCC = 5.0V
Output voltage offset
VOFF
RO
3.80
-
330
510
Analog output impedance
260
400
410
620
IDDA
IDSA
Power supply current*
*: During no load
AVCC
-
-
14
Μa
When D/A stop
Document Number: 002-04918 Rev. *G
Page 142 of 160
CY9B160R Series
12.7 Low-Voltage Detection Characteristics
12.7.1 Low-Voltage Detection Reset
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
2.25
2.30
Max
2.65
Detected voltage
Released voltage
VDL
VDH
-
-
2.45
2.50
V
V
When voltage drops
When voltage rises
2.70
12.7.2 Interrupt of Low-Voltage Detection
Value
Typ
Parameter
Symbol
Conditions
SVHI = 00111
SVHI = 00100
SVHI = 01100
SVHI = 01111
SVHI = 01110
SVHI = 01001
SVHI = 01000
Unit
Remarks
Min
Max
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 11000
-
LVD stabilization wait time
TLVDW
-
-
4480×tCYCP
*
μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04918 Rev. *G
Page 143 of 160
CY9B160R Series
12.8 MainFlash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V)
Value
Typ
Parameter
Unit
Remarks
Min
Max
3.7
Large Sector
Small Sector
0.7
Sector erase time
-
s
Includes write time prior to internal erase
0.3
12
1.1
Write cycles
< 100 times
Write cycles >
100 times
100
Half word (16-bit)
write time
-
-
μs
s
Not including system-level overhead time
Includes write time prior to internal erase
200
68
Chip erase time
13.6
Write cycles and data hold time
Erase/Write cycles (cycle)
Data hold time (year)
1,000
20 *
10,000
10 *
5 *
100,000
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test
result into average temperature value at + 85°C) .
12.9 WorkFlash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V)
Value
Typ
0.3
Parameter
Sector erase time
Unit
Remarks
Min
Max
1.5
-
-
s
Includes write time prior to internal erase
Not including system-level overhead time
Half word (16-bit)
write time
20
200
6
μs
s
Chip erase time
-
1.2
Includes write time prior to internal erase
Write cycles and data hold time
Erase/Write cycles (cycle)
Data hold time (year)
1,000
20 *
10,000
100,000
10 *
5 *
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test
result into average temperature value at + 85°C) .
Document Number: 002-04918 Rev. *G
Page 144 of 160
CY9B160R Series
12.10Standby Recovery Time
12.10.1 Recovery cause: Interrupt/WKUP
The time from recovery cause reception of the internal circuit to the program operation start is shown.
Recovery count time
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max*
Sleep mode
HCLK×1
High-speed CR Timer mode
Main Timer mode
40
80
μs
PLL Timer mode
Low-speed CR timer mode
Sub timer mode
450
896
900
μs
μs
1136
RTC mode
stop mode
Ticnt
316
270
581
μs
(High-speed CR /Main/PLL run mode return)
RTC mode
stop mode
540
(Low-speed CR/sub run mode return)
without RAM
retention
with RAM
retention
365
365
667
667
μs
μs
Deep standby RTC mode with RAM retention
Deep standby stop mode with RAM retention
*: The maximum value depends on the built-in CR accuracy.
Example of standby recovery operation (when in external interrupt recovery*)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-04918 Rev. *G
Page 145 of 160
CY9B160R Series
Example of standby recovery operation (when in internal resource interrupt recovery*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See “Chapter: Low Power Consumption Mode” and “Operations of Standby Modes” in FM4 Family Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See “Chapter: Low Power Consumption Mode” in “FM4 Family Peripheral Manual”.
Document Number: 002-04918 Rev. *G
Page 146 of 160
CY9B160R Series
12.10.2 Recovery cause: Reset
The time from reset release to the program operation start is shown.
Recovery count time
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max*
Sleep mode
155
155
266
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
266
μs
Low-speed CR timer mode
Sub timer mode
315
315
567
567
μs
μs
Trcnt
RTC mode
stop mode
315
567
μs
μs
μs
without RAM
retention
with RAM
retention
Deep standby RTC mode with RAM retention
Deep standby stop mode with RAM retention
336
667
*: The maximum value depends on the built-in CR accuracy.
Example of standby recovery operation (when in INITX recovery)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
Document Number: 002-04918 Rev. *G
Page 147 of 160
CY9B160R Series
Example of standby recovery operation (when in internal resource reset recovery*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery cause.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See “Chapter: Low Power Consumption Mode” and “Operations of Standby Modes” in FM4 Family Peripheral Manual.
−
The time during the power-on reset/low-voltage detection reset is excluded to the recovery source. See “12.4.7 Power-on
Reset Timing” in “12.4. AC Characteristics” in “12.Electrical Characteristics” for the detail on the time during the power-on
reset/low-voltage detection reset.
−
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-04918 Rev. *G
Page 148 of 160
CY9B160R Series
13.Ordering Information
Part Number
Flash
RAM
128 KB
Package
Plastic・LQFP (0.5 mm pitch), 80 pin
CY9BF168MPMC-GNE2
1 MB
1 MB
(LQH080)
CY9BF168NPMC-GNE2
CY9BF167NPMC-GNE2
CY9BF166NPMC-GNE2
CY9BF168RPMC-GNE2
CY9BF167RPMC-GNE2
CY9BF166RPMC-GNE2
128 KB
96 KB
64 KB
128 KB
96 KB
64 KB
Plastic・LQFP (0.5 mm pitch), 100 pin
768 KB
512 KB
1 MB
(LQI100)
Plastic・LQFP (0.5 mm pitch), 120 pin
768 KB
512 KB
(LQM120)
Document Number: 002-04918 Rev. *G
Page 149 of 160
CY9B160R Series
14.Package Dimensions
Package Type
Package Code
LQFP-120
LQM120
4
D
5
7
D1
90
61
61
90
91
91
60
60
E1
E
4
5
7
3
6
31
31
120
1
30
30
1
2
5
7
A-B D
e
0.10
C
3
BOTTOM VIEW
0.20
C A-B D
0.08
C
A-B
D
b
8
TOP VIEW
2
A
c
9
θ
A
SEATING
PLANE
A1
10
b
0.25
A'
SECTION A-A'
0.08
C
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17 0.22 0.27
0.115 0.195
18.00 BSC
0.15
c
D
D1
e
16.00 BSC
0.50 BSC
E
18.00 BSC
16.00 BSC
E1
L
0.45 0.60 0.75
0° 8°
θ
PACKAGE OUTLINE, 120 LEAD LQFP
18.0X18.0X1.7 MM LQM120 REV**
002-16172 **
Document Number: 002-04918 Rev. *G
Page 150 of 160
CY9B160R Series
Package Type
Package Code
LQFP-100
LQI100
002-11500 *B
Document Number: 002-04918 Rev. *G
Page 151 of 160
CY9B160R Series
Package Type
Package Code
QFP-100
PQH100
D
4
D1
5
7
80
51
51
80
81
50
50
81
E1
E
4
5
7
6
3
100
31
31
100
1
30
30
1
2
5
7
e
0.20
C
A-B
D
3
BOTTOM VIEW
b
0.40
C
A-B D
0.13
C A-B
D
8
TOP VIEW
2
θ
9
c
A
SEATING
PLANE
L2
A'
10
0.10
C
b
SECTION A-A'
DETAIL A
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
3.35
A
A1
b
0.05
0.27
0.11
0.45
0.37
0.23
0.32
c
D
23.90 BSC
20.00 BSC
0.65 BSC
D1
e
E
17.90 BSC
14.00 BSC
E1
0°
8°
0.88 1.03
1.95 REF
0.25 BSC
θ
L
0.73
L1
L2
PACKAGE OUTLINE, 100 LEAD QFP
002-15156 **
20.00X14.00X3.35 MM PQH100 REV**
Document Number: 002-04918 Rev. *G
Page 152 of 160
CY9B160R Series
Package Type
Package Code
LQFP-80
LQH080
002-11501 *A
Document Number: 002-04918 Rev. *G
Page 153 of 160
CY9B160R Series
Package Type
Package Code
LQFP-80
LQJ080
4
5
D
7
D1
60
41
41
60
61
40
40
61
E1
E
5
7
4
3
6
80
21
21
80
1
20
b
20
1
2
5
7
0.10
C
C
A-B
D
e
3
0.20
C A-B D
ddd
A-B
D
8
2
A
9
A
θ
SEATING
PLANE
c
A'
A1
b
0.10
C
0.25
L
L1
10
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.16 0.32 0.38
0.09 0.20
0.20
c
D
16.00 BSC
14.00 BSC
0.65 BSC
D1
e
E
16.00 BSC
14.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
θ
0°
8°
PACKAGE OUTLINE, 80 LEAD LQFP
14.0X14.0X1.7 MM LQJ080 REV**
002-14043 **
Document Number: 002-04918 Rev. *G
Page 154 of 160
CY9B160R Series
Package Type
Package Code
BGA-112
LDC112
A
0.20
C A
13
12
11
10
9
7
8
7
6
5
B
4
3
2
1
N
M
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
8
PIN A1
CORNER
7
112xφb
0.05
C A B
0.20
C B
6
TOPVIEW
BOTTOM VIEW
DETAILA
0.20
C
C
0.10
C
SIDEVIEW
DETAIL A
NOTES
1. ALLDIMENSIONSARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
MIN. NOM. MAX.
1.35
2. DIMENSIONSAND TOLERANCES METHODSPERASMEY14.5-2009.
THISOUTLINE CONFORMSTO JEP95, SECTION 4.5.
3. BALL POSITION DESIGNATION PERJEP95, SECTION 3, SPP-010.
4. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.
A
D
E
0.15
0.25
7.00 BSC
7.00 BSC
6.00 BSC
6.00 BSC
13
0.35
1
5. SYMBOL "MD"ISTHE BALLMATRIX SIZE IN THE "D"DIRECTION.
SYMBOL "ME"ISTHE BALLMATRIX SIZE IN THE "E"DIRECTION.
n ISTHE NUMBEROF POPULATED SOLDERBALL POSITIONSFORMATRIX
SIZE MD X ME.
D
E
1
6. DIMENSION "b"ISMEASURED ATTHE MAXIMUM BALL DIAMETER
IN A PLANE PARALLEL TO DATUM C.
1
7. "SD" AND "SE" ARE MEASURED WITH RESPECTTO DATUMSA AND BAND
DEFINE THE POSITION OF THE CENTERSOLDERBALL IN THE OUTERROW.
WHEN THERE ISAN ODD NUMBEROF SOLDERBALLSIN THE OUTERROW,
"SD"OR"SE"=0.
WHEN THERE ISAN EVEN NUMBEROF SOLDERBALLSIN THE OUTERROW,
"SD"= eD/2 AND "SE" = eE/2.
MD
ME
n
13
112
8. A1 CORNERTO BE IDENTIFIED BY CHAMFER, LASERORINK MARK.
METALLIZED MARK INDENTATION OROTHERMEANS.
Φb
eD
0.20
0.30
0.40
0.50 BSC
0.50 BSC
0.00
9. "+"INDICATESTHE THEORETICAL CENTEROF DEPOPULATED BALLS.
eE
SD /SE
PACKAGE OUTLINE, 112 BALLFBGA
7.0X7.0X1.35 MM LDC112 REV**
002-16663 **
Document Number: 002-04918 Rev. *G
Page 155 of 160
CY9B160R Series
Package Type
Package Code
BGA-144
LDC144
A
0.20
2X
C A
13
12
11
10
9
7
8
7
6
5
B
4
3
2
1
N
M
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
8
PIN A1
CORNER
7
144xφb
0.05
C A B
0.20
2X
C B
6
TOPVIEW
BOTTOM VIEW
DETAILA
0.20
C
C
0.08
C
SIDEVIEW
DETAIL A
NOTES
1. ALLDIMENSIONSARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
MIN. NOM. MAX.
1.30
2. DIMENSIONSAND TOLERANCES METHODSPERASMEY14.5-2009.
THISOUTLINE CONFORMSTO JEP95, SECTION 4.5.
3. BALL POSITION DESIGNATION PERJEP95, SECTION 3, SPP-010.
4. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.
A
D
E
0.15
0.25
7.00 BSC
7.00 BSC
6.00 BSC
6.00 BSC
13
0.35
1
5. SYMBOL "MD"ISTHE BALLMATRIX SIZE IN THE "D"DIRECTION.
SYMBOL "ME"ISTHE BALLMATRIX SIZE IN THE "E"DIRECTION.
n ISTHE NUMBEROF POPULATED SOLDERBALL POSITIONSFORMATRIX
SIZE MD X ME.
D
E
1
6. DIMENSION "b"ISMEASURED ATTHE MAXIMUM BALL DIAMETER
IN A PLANE PARALLEL TO DATUM C.
1
7. "SD" AND "SE" ARE MEASURED WITH RESPECTTO DATUMSA AND BAND
DEFINE THE POSITION OF THE CENTERSOLDERBALL IN THE OUTERROW.
WHEN THERE ISAN ODD NUMBEROF SOLDERBALLSIN THE OUTERROW,
"SD"OR"SE"=0.
WHEN THERE ISAN EVEN NUMBEROF SOLDERBALLSIN THE OUTERROW,
"SD"= eD/2 AND "SE" = eE/2.
MD
ME
n
13
144
8. A1 CORNERTO BE IDENTIFIED BY CHAMFER, LASERORINK MARK.
METALLIZED MARK INDENTATION OROTHERMEANS.
Φb
eD
0.20
0.30
0.40
0.50 BSC
0.50 BSC
0.00
9. "+"INDICATESTHE THEORETICAL CENTEROF DEPOPULATED BALLS.
eE
SD /SE
PACKAGE OUTLINE, 144 BALLFBGA
7.0X7.0X1.3 MM LDC144 REV**
002-16662 **
Document Number: 002-04918 Rev. *G
Page 156 of 160
CY9B160R Series
15.Major Changes
Spansion Publication Number: DS709-00004
Page
Section
Change Results
Preliminary → Data Sheet
-
-
Description
Deleted the following description:
The products which are described in this data sheet are placed into
TYPE4 product categories in “FM4
1
Family PERIPHERAL MANUAL”.
Features
Revised the following description:
Multi-Function Serial Interface
[I2c]
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3 and ch.7)
supported
3
→Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and
ch.7=ch.B) supported
Features
Unique Id
Added new section
Added “Unique ID”
7
9
Product Lineup
Function
51, 52
59
I/O Circuit Type
Revised the remarks of “Type O, P, Q”
Added new section
Handling Devices
Handling When Using Debug Pins
60
Block Diagram
Revised the block diagram
Electrical Characteristics
2. Recommended Operating Conditions
Revised “Table for package thermal resistance and maximum
permissible power”
72
Electrical Characteristics
3. Dc Characteristics
(1) Current Rating
• Revised the value of TBD
• Added the note to “ICCVBAT”
75 to 80
85
Electrical Characteristics
4. Ac Characteristics
Revised the waveform chart
(2) Sub Clock Input Characteristics
Electrical Characteristics
• Revised the value of TBD
85
4. Ac Characteristics
• Revised the table and the note of “Built-in High-speed CR”
(3) Built-In Cr Oscillation characteristics
Electrical Characteristics
• Revised the value of TBD
144
5. 12-Bit A/D Converter
• Revised the condition of the electrical characteristics table
Electrical Characteristics for the A/D Converter
Electrical Characteristics
• Revised the value of TBD
6. 12-Bit D/A Converter
Electrical Characteristics for the D/A Converter
• Revised the condition and Remarks of the electrical characteristics
table
147
Electrical Characteristics
• Revised the value of TBD
150
152
10. Standby Recovery Time
(1) Recovery Cause : Interrupt/Wkup
• Revised the table of Recovery count time
Electrical Characteristics
10. Standby Recovery Time
(2) Recovery Cause : Reset
• Revised the value of TBD
• Revised the table of Recovery count time
Note: Please see “Document History” about later revised information.
Document Number: 002-04918 Rev. *G
Page 157 of 160
CY9B160R Series
Document History
Document Title: CY9B160R Series, 32-bit ARM® Cortex®-M4F FM4 Microcontroller
Document Number: 002-04918
MB9B160R
Series ECN
Orig. of
Change
Submission
Date
Revision
Description of Change
Migrated to Cypress and assigned document number 002-04918.
No change to document contents or format.
**
–
AKIH
06/27/2013
Updated to Cypress template.
*A
*B
5162380
5516291
AKIH
03/07/2016
02/02/2017
Updated “12.4.7 Power-On Reset Timing”. Changed parameter from
“Power Supply rise time(Tr)[ms]” to “Power ramp rate(Dv/dt)[Mv/us]” and
add some comments (Page 84)
YSKA
Modified the Chapter name “12.4.11 UART Timing” to “12.4.11 CSIO/UART
Timing”.
(Page 97)
Modified “12.4.11 CSIO/UART Timing)”. Deleted “SPI=1, MS=0” in the titles
and added MS=0,1 in the schematic (Page 105-112, 121-128)
Added the Baud rate spec in “12.4.12 CSIO/UART Timing”.(Page 97, 99,
101, 103)
“Modified RTC description in “Features, Real-Time Clock(RTC)”
Changed starting count value from 01 to 00. Deleted “second, or day of
the week” in the Interrupt function (Page 3)
Added Maximum Access size in “Features” (Page 1)
Modifications related to the VBAT in the following chapter.
“7. Handling Devices” Notes on Power-on (Page 54) “11. Pin Status in
Each CPU State” List of VBAT Domain Pin Status (Page 66) “12.3.1
Current Rating” Table12-9. Typical and Maximum Current Consumption in
Deep Standby STOP Mode, Deep Standby RTC Mode and VBAT (Page
77)
Added Notes for JTAG (Page 42), Changed “J-TAG” to” JTAG” in “4 List of
Pin Functions” (Page 30)
Modify typo in number of power supply (Three -> Two) (Page 4)
Updated Package code and dimensions as follows (Page 8-14, 68, 150-
156)
FPT-120P-M37 -> LQM120, FPT-100P-M23 -> LQI100,
FPT-100P-M36 -> PQH100, FPT-80P-M37 -> LQH080,
FPT-80P-M40 -> LQJ080, BGA-112P-M05 -> LDC112,
BGA-144P-M09 -> LDC144
Changed the mode name of I2C as follows (Page 2, 133-134)
Typical mode -> Standard-mode, High-speed mode -> Fast-mode
Modified from “Analog port input current” to “Analog port input leak current”
in “12.5 12-bit A/D Converter” (Page 139)
Modified according to the Datasheet Errata as below (No.1-9)
1. Modified Reference voltage value in “Electrical Characteristics for the
A/D Converter” in “12.5 12-bit A/D Converter” (Page 139)
2. Modified typo in “Features, Processor version” (Page 1)
3. Updated Remarks of Type H, I in “5. I/O Circuit Type” (Page 45)
Document Number: 002-04918 Rev. *G
Page 158 of 160
CY9B160R Series
MB9B160R
Series ECN
Orig. of
Change
Submission
Date
Revision
Description of Change
4. Updated “List of VBAT Domain Pin Status” (Page 66)
5. Modified “12.2 Recommended Operating Conditions” (Page 68)
6. Added “Frequency stabilization time” spec in “12.4.3 Built-in CR
Oscillation Characteristics” (Page 82)
7. Added “Conversion time” spec in “12.6 12-bit D/A Converter” (Page
142)
8. Modified some spec values in “12.10.1 Recovery cause:
Interrupt/WKUP” (Page 145) and “12.10.2 Recovery cause: Reset”
(Page 147)
9. Modified the “sampling time” and “State transition time to operation
permission” spec values in ”12.5 12-bit A/D Converter” (Page 139)
Deleted MPNs below from “13. Ordering Information” (Page 149)
MB9BF166RBGL-GE1, MB9BF167RBGL-GE1, MB9BF168RBGL-GE1
Added MPNs below to “13. Ordering Information” (Page 149)
MB9BF166RBGL-GK7E1, MB9BF167RBGL-GK7E1, MB9BF168RBGL-
GK7E1
Updated IO circuit (type A, N, O) (Page 43)
Modified the expression of the “Reference power supply current” “12.5 12-
bit A/D Converter” (Page 139)
Modified the expression of the “Built-in CR” and add Note in the “1. Product
Lineup” (Page 7)
Modified typo (SCLKx_0 -> SCKx_0) (Page 97, 99, 101, 103)
Updated Cypress Logo and Copyright.
*C
*D
5738077
5873294
YSAT
HUAL
05/16/2017
09/25/2017
1.new note format had been updated from *x to *x
2.double heading number had been cancelled on chapter 12.2
3.some chapter number missed in reference
Updated Electrical Characteristics:
Updated Recommended Operating Conditions:
Updated description.
Updated Ordering Information:
Updated part numbers.
*E
*F
6623270
6886941
XITO
XITO
07/15/2019
06/18/2020
Updated to new template.
Updated Document Title to read as “CY9B160R Series, 32-bit ARM®
Cortex®-M4F FM4 Microcontroller”.
Replaced MB9B160R with CY9B160R in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Information:
7218160
XITO
08/21/2021
*G
Updated part numbers.
Updated Package Dimensions:
spec 002-11500 – Changed revision from *A to *B.
spec 002-11501 – Changed revision from ** to *A.
Document Number: 002-04918 Rev. *G
Page 159 of 160
CY9B160R Series
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2013-2021. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
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reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,
“Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security
Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the
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It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
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and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the
High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from
any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns
harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use
of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited
extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04918 Rev. *G
August 21, 2021
Page 160 of 160
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