CY8C4248BZS-L489_技术文档

CY8C4248

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

General description

PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system

controllers with an Arm® Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital

blocks with flexible automatic routing. The PSoC™ 4200L product family, based on this platform, is a combination

of a microcontroller with digital programmable logic, programmable analog, programmable interconnect,

secure expansion of memory off-chip, high-performance analog-to-digital conversion, opamps with Comparator

mode, and standard communication and timing peripherals. The PSoC™ 4200L products will be fully compatible

with members of the PSoC™ 4 platform for new applications and design needs. The programmable analog and

digital subsystems allow flexibility and in-field tuning of the design.

Features

• 32-bit MCU subsystem

- 48 MHz Arm® Cortex®-M0 CPU with single-cycle multiply

- Up to 256 kB of flash with read accelerator

- Up to 32 kB of SRAM

- DMA engine with 32 channels

• Programmable analog

- Four opamps that operate in Deep Sleep mode at very low current levels

- All opamps have reconfigurable high current pin-drive, high-bandwidth internal drive, ADC input buffering,

and Comparator modes with flexible connectivity allowing input connections to any pin

- Four current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin

- Two low-power comparators that operate in Deep Sleep mode

• Programmable digital

- Eight programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital blocks

or UDBs)

- Infineon-provided peripheral component library, user-defined state machines, and Verilog input

• Low-power 1.71 V to 5.5 V operation

- 20-nA Stop Mode with GPIO pin wakeup

- Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs

• Capacitive sensing

- Two capacitive sigma-delta blocks provide best-in-class SNR (>5:1) and water tolerance

- Infineon-supplied software component makes capacitive sensing design easy

- Automatic hardware tuning (SmartSense)

• Segment LCD drive

- LCD drive supported on any pin with up to a maximum of 64 outputs (common or segment)

- Operates in Deep Sleep mode with 4 bits per pin memory

• Serial communication

- Four independent run-time reconfigurable Serial Communication Blocks (SCBs) with reconfigurable I²C, SPI,

or UART functionality

- USB Full-Speed device interface 12 Mbits/sec with Battery Charger Detect capability

- Two independent CAN blocks for industrial and automotive networking

• Timing and pulse-width modulation

- Eight 16-bit timer/counter pulse-width modulator (TCPWM) blocks

- Center-aligned, Edge, and Pseudo-random modes

- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Features

• Up to 98 programmable GPIOs

- 124-ball VFBGA package

- Any of up to 94 GPIO pins can be CAPSENSE™, analog, or digital

- Drive modes, strengths, and slew rates are programmable

• PSoC™ Creator design environment

- Integrateddevelopment environment (IDE)providesschematicdesign entry andbuild (with analogand digital

automatic routing)

- Applications programming interface (API) component for all fixed-function and programmable peripherals

• Industry-standard tool compatibility

- After schematic entry, development can be done with Arm®-based industry-standard development tools

Datasheet

2 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Table of contents

General description ...........................................................................................................................1

Features ...........................................................................................................................................1

Table of contents...............................................................................................................................3

1 More information............................................................................................................................4

2 PSoC™ Creator................................................................................................................................5

3 PSoC™ 4200L block diagram ............................................................................................................6

4 Functional definition.......................................................................................................................7

4.1 CPU and memory subsystem .................................................................................................................................7

4.2 System resources....................................................................................................................................................7

4.3 Analog blocks ..........................................................................................................................................................9

4.4 Programmable digital...........................................................................................................................................12

4.5 Fixed function digital ............................................................................................................................................13

4.6 GPIO.......................................................................................................................................................................13

4.7 SIO .........................................................................................................................................................................14

4.8 Special function peripherals ................................................................................................................................14

5 Pinouts ........................................................................................................................................15

6 Power ..........................................................................................................................................20

6.1 Unregulated external supply................................................................................................................................20

6.2 Regulated external supply....................................................................................................................................20

7 Electrical specifications.................................................................................................................21

7.1 Absolute maximum ratings .................................................................................................................................21

7.2 Device level specifications....................................................................................................................................21

7.3 Analog peripherals................................................................................................................................................27

7.4 Digital peripherals.................................................................................................................................................33

7.5 Memory..................................................................................................................................................................37

7.6 System resources..................................................................................................................................................38

8 Ordering information ....................................................................................................................46

8.1 Part numbering conventions................................................................................................................................47

9 Packaging ....................................................................................................................................48

10 Acronyms ...................................................................................................................................50

11 Document conventions................................................................................................................54

11.1 Units of measure .................................................................................................................................................54

Revision history ..............................................................................................................................55

Datasheet

3 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

More information

1

More information

Infineon provides a wealth of data at www.infineon.com to help you to select the right PSoC™ device for your

design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list

of resources, see the knowledge base article KBA86521, How to Design with PSoC™ 3, PSoC™ 4, and PSoC™

5LP. Following is an abbreviated list for PSoC™ 4:

• Overview: PSoC™ Portfolio, PSoC™ Roadmap

• Product Selectors: PSoC™ 1, PSoC™ 3, PSoC™ 4, PSoC™ 5LP

In addition, PSoC™ Creator includes a device selection tool.

• Application notes: Infineon offers a large number of PSoC™ application notes covering a broad range of topics,

from basic to advanced level. Recommended application notes for getting started with PSoC™ 4 are:

- AN79953: Getting started with PSoC™ 4

- AN88619: PSoC™ 4 hardware design considerations

- AN86439: Using PSoC™ 4 GPIO pins

- AN57821: Mixed signal circuit board layout

- AN81623: Digital design best practices

- AN73854: Introduction to bootloaders

- AN89610: Arm® Cortex® code optimization

- AN85951: PSoC™ 4 and PSoC™ 6 MCU CAPSENSE™ design guide

• Technical reference manual (TRM) is in two documents:

- Architecture TRM details each PSoC™ 4 functional block.

- Registers TRM describes each of the PSoC™ 4 registers.

• Development kits:

- CY8CKIT-042, PSoC™ 4 pioneer kit, is an easy-to-use and inexpensive development platform. This kit includes

connectors for Arduino™ compatible shields and Digilent® Pmod™ daughter cards.

- CY8CKIT-046, PSoC™ 4 L-Series pioneer kit, is an easy-to-use and inexpensive development platform. This kit

includes connectors for Arduino™ compatible shields.

- CY8CKIT-049 is a very low-cost prototyping platform. It is a low-cost alternative to sampling PSoC™ 4 devices.

- CY8CKIT-001 is a common development platform for any one of the PSoC™ 1, PSoC™ 3, PSoC™ 4, or PSoC™

5LP families of devices.

The MiniProg3 device provides an interface for flash programming and debug.

Datasheet

4 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

PSoC™ Creator

2

PSoC™ Creator

PSoC™ Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware

and firmware design of PSoC™ 3, PSoC™ 4, and PSoC™ 5LP based systems. Create designs using classic, familiar

schematic capture supported by over 100 pre-verified, production-ready PSoC™ Components; see the list of

component datasheets. With PSoC™ Creator, you can:

1. Drag and drop component icons to build your hardware system design in the main design workspace

2. Codesign your application firmware with the PSoC™ hardware, using the PSoC™ Creator IDE C compiler

3. Configure components using the configuration tools

4. Explore the library of 100+ components

5. Review component datasheets

1

2

3

4

5

Figure 1

Multiple-sensor example project in PSoC™ Creator contents

Datasheet

5 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

PSoC™ 4200L block diagram

3

PSoC™ 4200L block diagram

The PSoC™ 4200L devices include extensive support for programming, testing, debugging, and tracing both

hardware and firmware.

The Arm® serial wire debug (SWD) interface supports all programming and debug features of the device.

Complete debug-on-chip functionality enables full-device debugging in the final system using the standard

production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the

standard programming connections are required to fully support debug.

The PSoC™ Creator IDE provides fully integrated programming and debug support for PSoC™ 4200L devices. The

SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4200L family provides a

level of security not possible with multi-chip application solutions or with microcontrollers. This is due to its

ability to disable debug features, robust flash protection, and because it allows customer-proprietary function-

ality to be implemented in on-chip programmable blocks.

The debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to

re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware

that enables debugging.

Additionally, all device interfaces can be permanently disabled (device security) for applications concerned

about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and

interrupting flash programming sequences. Because all programming, debug, and test interfaces are disabled

when maximum device security is enabled, PSoC™ 4200L with device security enabled may not be returned for

failure analysis. This is a trade-off the PSoC™ 4200L allows the customer to make.

CPU Subsystem

PSoC 4200L

Architecture

SWD/TC

Cortex

M0

48MHz

FAST MUL

SPCIF

FLASH

256KB

SRAM

32KB

ROM

8 KB

DataWire/

DMA

32-bit

AHB- Lite

Read Accelerator

SRAM Controller

ROM Controller

Initiator/ MMIO

NVIC, IRQMX

System Resources

Power

Sleep Control

WIC

System Interconnect (Multi Layer AHB)

Peripheral Interconnect (MMIO)

Peripherals

POR

REF

LVD

BOD

PWRSYS

NVLatches

PCLK

Clock

Clock Control

WDT

Programmable

Digital

Programmable

Analog

512B

IMO

ILO

ECO 2x PLL

SAR ADC

(12-bit)

UDB

...

UDB

Reset

Reset Control

XRES

x1

x8

Test

DFT Logic

DFT Analog

SMX

CTBm

x2

2x OpAmp

Port Interface & Digital System Interconnect (DSI)

Power Modes

Active/ Sleep

Deep Sleep

Hibernate

High Speed I / O Matrix, 1x Programmable I/O

80 x GPIO, 14 x GPIO_OVT,2x SIO

I/O Subsystem

Figure 2

Block diagram

Datasheet

6 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Functional definition

4

Functional definition

CPU and memory subsystem

CPU

4.1

4.1.1

The Cortex®-M0 CPU in the PSoC™ 4200L is part of the 32-bit MCU subsystem, which is optimized for low-power

operation with extensive clock gating. Most instructions are 16 bits in length and execute a subset of the Thumb-2

instruction set. This enables fully compatible binary upward migration of the code to higher performance

processors such as the Cortex®-M3 and M4, thus enabling upward compatibility. The Infineon implementation

includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt

controller (NVIC) block with 32 interrupt inputs and also includes a Wakeup Interrupt Controller (WIC), which can

wake the processor up from the Deep Sleep mode allowing power to be switched off to the main processor when

the chip is in the Deep Sleep mode. The Cortex®-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is

made available to the user when it is not in use for system functions requested by the user.

The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a 2-wire form of JTAG;

the debug configuration used for PSoC™ 4200L has four break-point (address) comparators and two watchpoint

(data) comparators.

4.1.2

Flash

The PSoC™ 4200L has a flash module with a flash accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The flash block is designed to deliver 2 wait-state (WS) access time at 48 MHz

and with 1-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance

on average. Part of the flash module can be used to emulate EEPROM operation if required.

4.1.3

SRAM

SRAM memory is retained during Hibernate.

4.1.4

SROM

A supervisory ROM that contains boot and configuration routines is provided.

4.1.5

DMA

A DMA engine is provided that can do 32-bit transfers and has chainable ping-pong descriptors.

4.2

System resources

Power system

4.2.1

The power system is described in detail in the section “Power” on page 20. It provides assurance that voltage

levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for

example) until voltage levels are as required for proper function or generate resets (brown-out detect (BOD)) or

interrupts (low voltage detect (LVD)). The PSoC™ 4200L operates with a single external supply over the range of

1.71 to 5.5 V and has five different power modes, transitions between which are managed by the power system.

The PSoC™ 4200L provides Sleep, Deep Sleep, Hibernate, and Stop low-power modes.

Datasheet

7 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Functional definition

4.2.2

Clock system

The PSoC™ 4200L clock system is responsible for providing clocks to all subsystems that require clocks and for

switching between different clock sources without glitching. In addition, the clock system ensures that no

meta-stable conditions occur.

The clock system for the PSoC™ 4200L consists of a crystal oscillator (4 to 33 MHz), a watch crystal oscillator (32

kHz), a phase-locked loop (PLL), the IMO and the ILO internal oscillators, and provision for an external clock.

IMO

clk_hf

clk_ext

PLL #1

ECO

(optional )

PLL #0

dsi_in[0]

dsi_in[1]

dsi_in[2]

dsi_in[3]

dsi_out[3:0]

ILO

clk_lf

WCO

Figure 3

PSoC™ 4200L MCU clocking architecture

The clk_hf signal can be divided down to generate synchronous clocks for the UDBs, and the analog and digital

peripherals. There are a total of 16 clock dividers for the PSoC™ 4200L, each with 16-bit divide capability; this

allows 12 to be used for the fixed-function blocks and four for the UDBs. The analog clock leads the digital clocks

to allow analog events to occur before digital clock-related noise is generated. The 16-bit capability allows a lot

of flexibility in generating fine-grained frequency values and is fully supported in PSoC™ Creator.

4.2.3

IMO clock source

The IMO is the primary source of internal clocking in the PSoC™ 4200L. It is trimmed during testing to achieve the

specified accuracy. Trim values are stored in nonvolatile latches (NVL). Additional trim settings from flash can be

used to compensate for changes. The IMO default frequency is 24 MHz and it can be adjusted between 3 to 48 MHz

in steps of 1 MHz. IMO tolerance with Infineon-provided calibration settings is ±2%.

4.2.4

ILO clock source

The ILO is a very low power oscillator, nominally 32 kHz, which is primarily used to generate clocks for peripheral

operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Infineon

provides a software component, which does the calibration.

4.2.5

Crystal oscillators and PLL

The PSoC™ 4200L clock subsystem also implements two oscillators: high-frequency (4 to 33 MHz) and

low-frequency (32-kHz watch crystal) that can be used for precision timing applications. The PLL can generate a

48-MHz output from the high-frequency oscillator.

4.2.6

Watchdog timer

A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during

Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is

recorded in the Reset Cause register.

Datasheet

8 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Functional definition

4.2.7

Reset

The PSoC™ 4200L can be reset from a variety of sources including a software reset. Reset events are asynchronous

and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset

and allows software to determine the cause of the reset. An XRES pin is reserved for external reset to avoid

complications with configuration and multiple pin functions during power-on or reconfiguration.

4.2.8

Voltage reference

The PSoC™ 4200L reference system generates all internally required references. A 1% voltage reference spec is

provided for the 12-bit ADC. To allow better signal-to-noise ratios (SNR) and better absolute accuracy, it is

possible to add an external bypass capacitor to the internal reference using a GPIO pin or to use an external

reference for the SAR.

4.3

Analog blocks

12-bit SAR ADC

4.3.1

The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks

at that frequency to do a 12-bit conversion.

The block functionality is augmented for the user by adding a reference buffer to it (trimmable to ±1%) and by

providing the choice (for the PSoC™ 4200L case) of three internal voltage references: V_DD, V_DD/2, and V_REF

(nominally 1.024 V) as well as an external reference through a GPIO pin. The Sample-and-Hold (S/H) aperture is

programmable allowing the gain bandwidth requirements of the amplifier driving the SAR inputs, which

determine its settling time, to be relaxed if required. The system performance will be 65 dB for true 12-bit

precision if appropriate references are used and system noise levels permit. To improve performance in noisy

conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference

amplifier.

The SAR is connected to a fixed set of pins through an 8-input sequencer (expandable to 16 inputs). The sequencer

cycles through selected channels autonomously (sequencer scan) and does so with zero switching overhead

(that is, the aggregate sampling bandwidth is equal to 1 Msps, whether it is for a single channel or distributed

over several channels). The sequencer switching is effected through a state machine or through firmware-driven

switching. A feature provided by the sequencer is buffering of each channel to reduce CPU interrupt service

requirements. To accommodate signals with varying source impedance and frequency, it is possible to have

different sample times programmable for each channel. In addition, the signal range specification through a pair

of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the

digitized value exceeds the programmed range; this allows fast detection of out-of-range values without the

necessity of having to wait for a sequencer scan to be completed and the CPU to read the values and check for

out-of-range values in software.

The SAR is able to digitize the output of the on-board temperature sensor for calibration and other

temperature-dependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a

high-speed clock (up to 18 MHz). The SAR operating range is 1.71 to 5.5 V.

Datasheet

9 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Functional definition

AHB System Bus and Programmable Logic

Interconnect

SARSEQ

Sequencing

and Control

Data and

Status Flags

POS

NEG

SARADC

External

Reference

and

Reference

Selection

Bypass

(optional)

VDDD

VREF

VDD/2

Inputs from other Ports

Figure 4

SAR ADC system diagram

4.3.2

Analog multiplex bus

The PSoC™ 4200L has two concentric analog buses (Analog Mux Bus A and Analog Mux Bus B) that circumnavigate

the periphery of the chip. These buses can transport analog signals from any pin to various analog blocks

(including the opamps) and to the CAPSENSE™ blocks allowing, for instance, the ADC to monitor any pin on the

chip. These buses are independent and can also be split into three independent sections. This allows one section

to be used for CAPSENSE™ purposes, one for general analog signal processing, and the third for general-purpose

digital peripherals and GPIO.

4.3.3

Four opamps (CTBm Blocks)

The PSoC™ 4200L has four opamps with Comparator modes, which allow most common analog functions to be

performed on-chip eliminating external components; PGAs, voltage buffers, filters, trans-impedance amplifiers,

and other functions can be realized with external passives saving power, cost, and space. The on-chip opamps

are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without requiring external

buffering. The opamps can operate in the Deep Sleep mode at very low power levels. The following diagram

shows one of two identical opamp pairs of the opamp subsystem.

Datasheet

10 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Functional definition

OA0

+

10x

1x

-

Internal

Out0

P0

P1

P2

P3

P4

P5

P6

P7

OA1

-

1x

+

Internal

Out1

10x

Figure 5

Identical opamp pairs in opamp subsystem

The ovals in Figure 5 represent analog switches, which may be controlled via user firmware, the SAR sequencer,

or user-defined programmable logic. The opamps (OA0 and OA1) are configurable via these switches to perform

all standard opamp functions with appropriate feedback components.

The opamps (OA0 and OA1) are programmable and reconfigurable to provide standard opamp functionality via

switchable feedback components, unity gain functionality for driving pins directly, or for internal use (such as

buffering SAR ADC inputs as indicated in the diagram), or as true comparators.

The opamp inputs provide highly flexible connectivity and can connect directly to dedicated pins or, via the

analog mux buses, to any pin on the chip. Analog switch connectivity is controllable by user firmware as well as

user-defined programmable digital state machines (implemented via UDBs).

The opamps operate in Deep Sleep mode at very low currents allowing analog circuits to remain operational

during Deep Sleep.

4.3.4

Temperature sensor

The PSoC™ 4200L has one on-chip temperature sensor. This consists of a diode, which is biased by a current

source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the

reading and produces a temperature value using Infineon-supplied software that includes calibration and linear-

ization.

4.3.5

Low-power comparators

The PSoC™ 4200L has a pair of low-power comparators, which can also operate in the Deep Sleep and Hibernate

modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage

levels during low-power modes. The comparator outputs are normally synchronized to avoid meta-stability

unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by

a comparator switch event.

Datasheet

11 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Functional definition

4.4

Programmable digital

4.4.1

Universal digital blocks (UDBs) and port interfaces

The PSoC™ 4200L has eight UDBs; the UDB array also provides a switched Digital System Interconnect (DSI) fabric

that allows signals from peripherals and ports to be routed to and through the UDBs for communication and

control. The UDB array is shown in the following figure.

AHB Bridge CPUSS Dig CLKS

4to8

8 to32

UDBIF

BUS IF

CLK IF

IRQ IF

Port IF

DSI

Scalable array of

UDBs(max 8 )

=

UDB

Routing

Channels

UDB

DSI

Programmable Digital Subsystem

Figure 6

UDB array

UDBs can be clocked from a clock divider block, from a port interface (required for peripherals such as SPI), and

from the DSI network directly or after synchronization.

A port interface is defined, which acts as a register that can be clocked with the same source as the PLDs inside

the UDB array. This allows faster operation because the inputs and outputs can be registered at the port interface

close to the I/O pins and at the edge of the array. The port interface registers can be clocked by one of the I/Os

from the same port. This allows interfaces such as SPI to operate at higher clock speeds by eliminating the delay

for the port input to be routed over DSI and used to register other inputs. The port interface is shown in Figure 7.

The UDBs can generate interrupts (one UDB at a time) to the interrupt controller. The UDBs retain the ability to

connect to most of the pins on the chip through the DSI, with the exception of the pins from Port 7, 8, and 9.

High Speed I/O Matrix

To Clock

Tree

8

4

Input Registers

Output Registers

Enables

7

6

. . .

0

7

6

. . .

0

3

2

1

0

Digital

GlobalClocks

9

4

[1]

[0]

[1]

Clock Selector

Block from

UDB

2

3 DSI Signals ,

1 I/O Signal

4

8

[1]

[0]

[1]

Reset Selector

Block from

UDB

From DSI

To DSI

From DSI

Figure 7

Port interface

Datasheet

12 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Functional definition

4.5

Fixed function digital

4.5.1

Timer/Counter/PWM (TCPWM) block

The TCPWM block consists of one 16-bit counter with user-programmable period length. There is a Capture

register to record the count value at the time of an event (which may be an I/O event), a period register which is

used to either stop or auto-reload the counter when its count is equal to the period register, and compare

registers to generate compare value signals, which are used as PWM duty cycle outputs. The block also provides

true and complementary outputs with programmable offset between them to allow use as deadband program-

mable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for

example, this is used in motor drive systems when an overcurrent state is indicated and the PWMs driving the

FETs need to be shut off immediately with no time for software intervention. The PSoC™ 4200L has eight TCPWM

blocks.

4.5.2

Serial Communication Blocks (SCB)

The PSoC™ 4200L has four SCBs, which can each implement an I²C, UART, or SPI interface.

I²C Mode: The hardware I²C block implements a full multi-master and slave interface (it is capable of multimaster

arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible

buffering options to reduce interrupt overhead and latency for the CPU. It also supports EzI2C that creates a

mailbox address range in the memory of the PSoC™ 4200L and effectively reduces I²C communication to reading

from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit

which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused

by the CPU not having read data on time. The FIFO mode is available in all channels and is very useful in the

absence of DMA.

The I²C peripheral is compatible with the I²C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined

in the NXP I²C-bus specification and user manual (UM10204). The I²C bus I/O is implemented with GPIO in

open-drain modes.

UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface

(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic

UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals

connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame

error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.

SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (essentially adds a start pulse used to synchronize SPI

Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.

4.5.3

USB device

A Full-speed USB 2.0 device interface is provided. It has a Control endpoint and eight other endpoints. The

interface has a USB transceiver and can be operated from the IMO obviating the need for a crystal oscillator.

4.5.4

CAN blocks

There are two independent CAN 2.0B blocks, which are certified CAN conformant.

4.6

GPIO

The PSoC™ 4200L has 96 GPIOs. The GPIO block implements the following:

• Eight drive strength modes including strong push-pull, resistive pull-up and pull-down, weak (resistive) pull-up

and pull-down, open drain and open source, input only, and disabled

• Input threshold select (CMOS or LVTTL)

• Individual control of input and output disables

• Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode and Hibernate modes)

• Selectable slew rates for dV/dt related noise control to improve EMI

Datasheet

13 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Functional definition

The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the

blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A

multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may

connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal multiplexing

complexity (these signals do not go through the DSI network). DSI signals are not affected by this and any pin may

be routed to any UDB through the DSI network, with the exception of pins from Port 7, 8, and 9.

Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the

pins themselves.

Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt

service routine (ISR) vector associated with it (13 for PSoC™ 4200L).

There are 14 GPIO pins that are overvoltage tolerant (V_INcan exceed V_DD). The overvoltage cells will not sink more

than 10 µA when their inputs exceed V_DDIOin compliance with I²C specifications. Meeting the I²C minimum fall

time requirement for FM and FM+ may require the slower slew rate setting depending on bus loading (also applies

to all GPIO and SIO pins).

4.7

SIO

The Special I/O (SIO) pins have the following features in addition to the GPIO features:

• Overvoltage protection and hot swap capability

• Programmable switching thresholds

• Programmable output pull-up voltage capability

They allow interfacing to buses, such as I²C with full I²C compatibility and interfacing to devices operating at

different voltage levels. There are two SIO pins on the PSoC™ 4200L.

4.8

Special function peripherals

LCD segment Drive

4.8.1

The PSoC™ 4200L has an LCD controller, which can drive up to eight commons and up to 56 segments. Any pin

can be either a common or a segment pin. It uses full digital methods to drive the LCD segments requiring no

generation of internal LCD voltages. The two methods used are referred to as digital correlation and PWM.

Digital correlation pertains to modulating the frequency and levels of the common and segment signals to

generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero. This method is

good for STN displays but may result in reduced contrast with TN (cheaper) displays.

PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the

integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher

power consumption but can result in better results when driving TN displays.

4.8.2

CAPSENSE™

CAPSENSE™ is supported on all pins in the PSoC™ 4200L through two CAPSENSE™ Sigma-Delta (CSD) blocks that

can be connected to any pin through an analog mux bus that any GPIO pin can be connected to via an Analog

switch. CAPSENSE™ function can thus be provided on any pin or group of pins in a system under software control.

A component is provided for the CAPSENSE™ block to make it easy for the user.

Shield voltage can be driven on another Mux Bus to provide water tolerance capability. Water tolerance is

provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from

attenuating the sensed input.

Each CAPSENSE™ block has two IDACs which can be used for general purposes if CAPSENSE™ is not being

used.(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is

available). The two CAPSENSE™ blocks can be used independently.

Datasheet

14 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Pinouts

5

Pinouts

The following is the pin list for the PSoC™ 4200L.

Table 1 Pinout

124-BGA

Name

124-BGA

C3

C5

B5

A5

A4

B4

C4

A3

B3

B1

C3

D4

B2

C1

C2

D1

D2

D3

E1

E2

E3

K4

A1

F1

F2

F3

G1

G2

G3

H1

H2

K4

J1

Name

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

H13

H12

G13

G12

K10

G11

F13

F12

F11

E13

E12

E11

D13

D12

C13

C12

B12

C11

A12

D10

B13

A13

A11

B11

A10

B10

C10

A9

P0.0

P0.1

P0.2

P0.3

VSSD

P0.4

P0.5

P0.6

P0.7

P8.0

P8.1

P8.2

P8.3

P8.4

P8.5

P8.6

P8.7

XRES

VCCD

VSSD

VDDD

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

P9.6

P9.7

P1.7

VREF

VSSA

VDDA

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

VSSD

VDDA

P10.0

P10.1

P10.2

P10.3

P10.4

P10.5

P10.6

P10.7

VSSD

P6.0

B9

C9

C8

B8

A8

A7

B7

P5.0

P5.1

P5.2

P5.3

P5.4

J2

J3

K1

P6.1

P6.2

P6.3

Datasheet

15 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Pinouts

Table 1

Pinout

124-BGA

Name

124-BGA

K2

L1

L2

K3

L3

L8

N9

Name

P6.4

P12.0

P12.1

P6.5

VSSD

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

C7

A6

B6

A2

P5.5

P5.6

P5.7

VDDA

P3.0

P3.1

P3.2

P3.3

P3.4

B2

N2

M2

N3

M3

N4

M4

N5

M5

M1

N1

N6

M6

L6

N7

M7

L7

N8

M8

N12

N13

M9

N10

M10

N11

M11

M12

L11

L12

L13

M13

L9

P3.5

P3.6

P3.7

P4.6

P4.7

VDDIO

P11.0

P11.1

P11.2

P11.3

P11.4

P11.5

P11.6

P11.7

VDDIO

VSSD

D+/P13.0

D-/P13.1

VBUS/P13.2

P7.0

L10

K13

K12

K11

J13

J12

J11

P7.1

P7.2

P7.3

P7.4

P7.5

P7.6

P7.7

Port 12 (Port pins 12.0 and 12.1) are SIO pins.

Port 13 (Port pins 13.0 and 13.1) require VBUS (P13.2) to be powered.

Ports 6 (Port pins P6.0..6.5) and 9 (Port pins 9.0..9.7) are overvoltage tolerant (GPIO_OVT)

Balls C6, D11, H11, H3, L4, and L5 are No Connects (NC) on the 124-BGA package.

Datasheet

16 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Pinouts

Each of the pins shown in the previous table can have multiple programmable functions as shown in the following

table.

Port/pin

Analog

USB

Alt. function 1

Alt. function 2

Alt. function 3

Alt. function 4

Alt. function 5

P0.0

lpcomp.in_p[0]

can[1].can_rx:0

usb.vbus_valid

scb[0].spi_select1:3

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

lpcomp.in_n[0]

lpcomp.in_p[1]

lpcomp.in_n[1]

wco_in

can[1].can_tx:0

scb[0].spi_select2:3

scb[0].spi_select3:3

scb[1].uart_rx:0

scb[1].uart_tx:0

scb[1].uart_cts:0

scb[1].uart_rts:0

scb[1].i2c_scl:0

scb[1].i2c_sda:0

scb[1].spi_mosi:0

scb[1].spi_miso:0

scb[1].spi_clk:0

wco_out

srss.ext_clk:0

can[1].can_tx-

_enb_n:0

srss.wakeup

scb[1].spi_select0:0

P8.0

P8.1

P8.2

P8.3

P8.4

P8.5

P8.6

P8.7

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

P9.6

P9.7

P5.0

scb[3].uart_rx:0

scb[3].uart_tx:0

scb[3].uart_cts:0

scb[3].uart_rts:0

scb[3].i2c_scl:0

scb[3].i2c_sda:0

lpcomp.comp[0]:0

lpcomp.comp[1]:0

scb[3].spi_mosi:0

scb[3].spi_miso:0

scb[3].spi_clk:0

scb[3].spi_select0:0

scb[3].spi_select1:0

scb[3].spi_select2:0

scb[3].spi_select3:0

tcpwm.line[0]:2

tcpwm.line_compl[0]:2

tcpwm.line[1]:2

scb[0].uart_rx:0

scb[0].uart_tx:0

scb[0].uart_cts:0

scb[0].uart_rts:0

scb[0].i2c_scl:0

scb[0].i2c_sda:0

scb[0].spi_mosi:0

scb[0].spi_miso:0

scb[0].spi_clk:0

tcpwm.line_compl[1]:2

tcpwm.line[2]:2

scb[0].spi_select0:0

scb[0].spi_select1:0

scb[0].spi_select2:0

scb[0].spi_select3:0

tcpwm.line_compl[2]:2

tcpwm.line[3]:2

scb[3].i2c_scl:3

scb[3].i2c_sda:3

scb[2].i2c_scl:0

tcpwm.line_compl[3]:2

tcpwm.line[4]:2

ctb1_pads[0]

csd[1].c_mod

scb[2].uart_rx:0

scb[2].uart_tx:0

scb[2].uart_cts:0

scb[2].uart_rts:0

scb[2].spi_mosi:0

scb[2].spi_miso:0

scb[2].spi_clk:0

P5.1

P5.2

P5.3

ctb1_pads[1]

csd[1].c_sh_tank

tcpwm.line_compl[4]:2

tcpwm.line[5]:2

scb[2].i2c_sda:0

lpcomp.comp[0]:1

lpcomp.comp[1]:1

ctb1_pads[2]

ctb1_oa0_out_10x

ctb1_pads[3]

ctb1_oa1_out_10x

tcpwm.line_compl[5]:2

scb[2].spi_select0:0

P5.4

P5.5

P5.6

P5.7

P1.0

ctb1_pads[4]

ctb1_pads[5]

ctb1_pads[6]

ctb1_pads[7]

ctb0_pads[0]

tcpwm.line[6]:2

tcpwm.line_compl[6]:2

tcpwm.line[7]:2

scb[2].spi_select1:0

scb[2].spi_select2:0

scb[2].spi_select3:0

tcpwm.line_compl[7]:2

tcpwm.line[2]:1

scb[0].uart_rx:1

scb[0].uart_tx:1

scb[0].uart_cts:1

scb[0].uart_rts:1

scb[0].i2c_scl:1

scb[0].i2c_sda:1

scb[0].spi_mosi:1

scb[0].spi_miso:1

scb[0].spi_clk:1

P1.1

P1.2

P1.3

ctb0_pads[1]

tcpwm.line_compl[2]:1

tcpwm.line[3]:1

ctb0_pads[2]

ctb0_oa0_out_10x

ctb0_pads[3]

ctb0_oa1_out_10x

tcpwm.line_compl[3]:1

scb[0].spi_select0:1

P1.4

P1.5

P1.6

P1.7

ctb0_pads[4]

ctb0_pads[5]

ctb0_pads[6]

tcpwm.line[6]:1

tcpwm.line_compl[6]:1

tcpwm.line[7]:1

scb[0].spi_select1:1

scb[0].spi_select2:1

scb[0].spi_select3:1

ctb0_pads[7],

sar_ext_vref

tcpwm.line_compl[7]:1

Datasheet

17 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Pinouts

Port/pin

P2.0

Analog

USB

Alt. function 1

tcpwm.line[4]:1

Alt. function 2

scb[1].uart_rx:1

scb[1].uart_tx:1

scb[1].uart_cts:1

scb[1].uart_rts:1

Alt. function 3

Alt. function 4

scb[1].i2c_scl:1

scb[1].i2c_sda:1

Alt. function 5

scb[1].spi_mosi:1

scb[1].spi_miso:1

scb[1].spi_clk:1

sarmux_pads[0]

sarmux_pads[1]

sarmux_pads[2]

sarmux_pads[3]

sarmux_pads[4]

sarmux_pads[5]

sarmux_pads[6]

sarmux_pads[7]

P2.1

tcpwm.line_compl[4]:1

tcpwm.line[5]:1

P2.2

P2.3

tcpwm.line_compl[5]:1

tcpwm.line[0]:1

scb[1].spi_select0:1

scb[1].spi_select1:0

scb[1].spi_select2:0

scb[1].spi_select3:0

P2.4

P2.5

tcpwm.line_compl[0]:1

tcpwm.line[1]:1

P2.6

P2.7

tcpwm.line_compl[1]:1

P10.0

P10.1

P10.2

P10.3

P10.4

P10.5

P10.6

P10.7

P6.0

scb[2].uart_rx:1

scb[2].uart_tx:1

scb[2].uart_cts:1

scb[2].uart_rts:1

scb[2].i2c_scl:1

scb[2].i2c_sda:1

scb[2].spi_mosi:1

scb[2].spi_miso:1

scb[2].spi_clk:1

scb[2].spi_select0:1

scb[2].spi_select1:1

scb[2].spi_select2:1

scb[2].spi_select3:1

tcpwm.line[4]:0

scb[3].uart_rx:1

can[0].can_tx-

_enb_n:0

scb[3].i2c_scl:1

scb[3].spi_mosi:1

P6.1

P6.2

tcpwm.line_compl[4]:0

tcpwm.line[5]:0

scb[3].uart_tx:1

scb[3].uart_cts:1

scb[3].uart_rts:1

can[0].can_rx:0

can[0].can_tx:0

scb[3].i2c_sda:1

scb[2].i2c_scl:3

scb[2].i2c_sda:3

scb[0].i2c_scl:3

scb[1].i2c_scl:3

scb[1].i2c_sda:3

scb[0].i2c_sda:3

scb[1].i2c_scl:2

scb[1].i2c_sda:2

cpuss.swd_data:0

cpuss.swd_clk:0

scb[3].spi_miso:1

scb[3].spi_clk:1

P6.3

tcpwm.line_compl[5]:0

tcpwm.line[6]:0

scb[3].spi_select0:1

scb[3].spi_select1:1

scb[3].spi_select3:1

P6.4

P12.0

P12.1

P6.5

tcpwm.line[7]:0

tcpwm.line_compl[7]:0

tcpwm.line_compl[6]:0

tcpwm.line[0]:0

scb[3].spi_select2:1

scb[1].spi_mosi:2

scb[1].spi_miso:2

scb[1].spi_clk:2

P3.0

scb[1].uart_rx:2

scb[1].uart_tx:2

scb[1].uart_cts:2

scb[1].uart_rts:2

P3.1

tcpwm.line_compl[0]:0

tcpwm.line[1]:0

P3.2

P3.3

tcpwm.line_compl[1]:0

tcpwm.line[2]:0

scb[1].spi_select0:2

scb[1].spi_select1:1

scb[1].spi_select2:1

scb[1].spi_select3:1

P3.4

P3.5

tcpwm.line_compl[2]:0

tcpwm.line[3]:0

P3.6

P3.7

tcpwm.line_compl[3]:0

tcpwm.line[4]:3

P11.0

P11.1

P11.2

P11.3

P11.4

P11.5

P11.6

P11.7

P4.0

scb[2].uart_rx:2

scb[2].uart_tx:2

scb[2].uart_cts:2

scb[2].uart_rts:2

scb[2].i2c_scl:2

scb[2].i2c_sda:2

cpuss.swd_data:1

cpuss.swd_clk:1

scb[2].spi_mosi:2

scb[2].spi_miso:2

scb[2].spi_clk:2

tcpwm.line_compl[4]:3

tcpwm.line[5]:3

tcpwm.line_compl[5]:3

tcpwm.line[6]:3

scb[2].spi_select0:2

scb[2].spi_select1:2

scb[2].spi_select2:2

scb[2].spi_select3:2

tcpwm.line_compl[6]:3

tcpwm.line[7]:3

tcpwm.line_compl[7]:3

scb[0].uart_rx:2

scb[0].uart_tx:2

scb[0].uart_cts:2

can[0].can_rx:1

can[0].can_tx:1

scb[0].i2c_scl:2

scb[0].i2c_sda:2

lpcomp.comp[0]:2

scb[0].spi_mosi:2

scb[0].spi_miso:2

scb[0].spi_clk:2

P4.1

P4.2

csd[0].c_mod

can[0].can_tx-

_enb_n:1

P4.3

P4.4

csd[0].c_sh_tank

scb[0].uart_rts:2

lpcomp.comp[1]:2

scb[0].spi_select0:2

scb[0].spi_select1:2

can[1].can_tx-

_enb_n:1

P4.5

P4.6

can[1].can_rx:1

can[1].can_tx:1

scb[0].spi_select2:2

scb[0].spi_select3:2

P4.7

P13.0

P13.1

USBDP

USBDM

Datasheet

18 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Pinouts

Port/pin

P13.2

P7.0

Analog

USB

Alt. function 1

Alt. function 2

Alt. function 3

Alt. function 4

Alt. function 5

VBUS

srss.eco_in

tcpwm.line[0]:3

tcpwm.line_compl[0]:3

tcpwm.line[1]:3

scb[3].uart_rx:2

scb[3].uart_tx:2

scb[3].uart_cts:2

scb[3].uart_rts:2

scb[3].i2c_scl:2

scb[3].i2c_sda:2

scb[3].spi_mosi:2

scb[3].spi_miso:2

scb[3].spi_clk:2

P7.1

srss.eco_out

P7.2

P7.3

tcpwm.line_compl[1]:3

tcpwm.line[2]:3

scb[3].spi_select0:2

scb[3].spi_select1:2

scb[3].spi_select2:2

scb[3].spi_select3:2

P7.4

P7.5

tcpwm.line_compl[2]:3

tcpwm.line[3]:3

P7.6

P7.7

tcpwm.line_compl[3]:3

Descriptions of the power pin functions are as follows:

VDDD: Power supply for both analog and digital sections (where there is no V_DDApin)

VDDA: Analog V_DDpin where package pins allow; should be present before or concurrently with VDDD and the

value of VDDA should be equal to or higher than VDDD and VDDIO

VDDIO: I/O pin power domain. It should not be present without VDDD.

VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise

VSS: Ground pin

VCCD: Regulated digital supply (1.8 V ±5%)

VBUS: USB voltage. There is no constraint on VBUS with respect to VDDD. However, since it comes from USB, it

is typically assumed to and ideally be 5 V (4.35 to 5.5 V is the range).

GPIO and GPIO_OVT pins can be used as CSD sense and shield pins (a total of 96). Up to 64 of the pins can be used

for LCD drive.

The following package is supported: 124-ball BGA.

Datasheet

19 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Power

6

Power

The supply voltage range is 1.71 V to 5.5 V with all functions and circuits operating over that range.

The PSoC™ 4200L family allows two distinct modes of power supply operation: Unregulated external supply and

regulated external supply modes.

6.1

Unregulated external supply

In this mode, the PSoC™ 4200L is powered by an external power supply that can be anywhere in the range of 1.8 V

to 5.5 V. This range is also designed for battery-powered operation, for instance, the chip can be powered from a

battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the PSoC™

4200L supplies the internal logic and the VCCD output of the PSoC™ 4200L must be bypassed to ground via an

external Capacitor (in the range of 1 to 1.6 µF; X5R ceramic or better).

VDDA and VDDD must be shorted together on the PC board; the grounds, VSSA and VSS must also be shorted

together. Bypass capacitors must be used from VDDD and VDDA to ground, typical practice for systems in this

frequency range is to use a capacitor in the 1 µF range in parallel with a smaller capacitor (0.1 µF, for example).

Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and

the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing.

Power supply

VDDD–VSS and VDDIO-VSS

VDDA–VSSA

Bypass capacitors

0.1 µF ceramic at each pin plus bulk capacitor 1 to 10 µF.

0.1 µF ceramic at pin. Additional 1 µF to 10 µF bulk capacitor

1 µF ceramic capacitor at the VCCD pin

VCCD–VSS

VREF–VSSA

(optional)

The internal bandgap may be bypassed with a 1 µF to 10 µF capacitor for

better ADC performance.

6.2

Regulated external supply

In this mode, the PSoC™ 4200L is powered by an external power supply that must be within the range of 1.71 V to

1.89 V (1.8 ±5%); note that this range needs to include power supply ripple. In this mode, the VCCD and VDDD pins

are shorted together and bypassed. The internal regulator is disabled in firmware.

Datasheet

20 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7

Electrical specifications

7.1

Table 2

Absolute maximum ratings

Absolute maximum ratings^[1]

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

conditions

SID1

SID2

V_{DD_ABS}

Analog or digital supply relative –0.5

–

6

V

Absolute

to V_SS(V_SSD= V_SSA

)

maximum

V_{CCD_ABS}

V_{GPIO_ABS}

I_{GPIO_ABS}

I_{G-PIO_in-}

Direct digital core voltage input –0.5

relative to V_SSD

–

1.95

V

Absolute

maximum

Absolute

maximum

SID3

GPIO voltage; V_DDDor V_DDA

–0.5

V_DD+ 0.5

SID4

Current per GPIO

–25

25

0.5

–

mA Absolute

maximum

mA Absolute

maximum

SID5

GPIO injection current per pin

–0.5

2200

jection

ESD_HBM

BID44

BID45

BID46

7.2

Electrostatic discharge human

body model

V

ESD_CDM

LU

Electrostatic discharge charged 500

device model

–

V

Pin current for latch-up

–140

140

mA

Device level specifications

All specifications are valid for –40°C ≤ T_A≤ 105°C and T_J≤ 125°C, except where noted. Specifications are valid for

1.71 V to 5.5 V, except where noted.

Table 3

DC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max Units

conditions

SID53

V_DDD

Power supply input voltage

1.8

–

5.5

V

With regulator

enabled

Internally

unregulated

supply

(V_DDA= V_DDD= V_DD

)

SID255

Power supply input voltage

unregulated

1.71

1.8

1.89

SID54

SID55

V_CCD

C_EFC

Output voltage (for core logic)

External regulator voltage (V_CCD

bypass

–

1

1.8

1.3

–

1.6

V

)

µF X5R ceramic or

better

SID56

C_EXC

Power supply decoupling

capacitor

–

1

–

µF X5R ceramic or

better

Active mode

SID6

SID7

SID8

SID9

I_DD1

Execute from flash; CPU at 6 MHz

Execute from flash; CPU at 12 MHz

Execute from flash; CPU at 24 MHz

Execute from flash; CPU at 48 MHz

–

2.2

3.7

6.7

3.1

4.8

8.0

mA

I_DD2

I_DD3

I_DD4

12.8

14.5

Note

1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in com-

pliance with JEDEC Standard JESD22-A103, high temperature storage life. When used below absolute maximum conditions but above

normal operating conditions, the device may not operate to specification.

Datasheet

21 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 3

DC specifications

Details/

Spec ID# Parameter

Sleep Mode

Description

Min

Typ

Max Units

conditions

SID21

SID22

SID23

SID24

I_DD16

I_DD17

I_DD18

I_DD19

I²C wakeup, WDT, and

–

2.9

2.1

2.9

2.8

mA V_DD= 1.71 to

1.89, 6 MHz

mA V_DD= 1.8 to 5.5,

6 MHz

mA V_DD= 1.71 to

1.89, 12 MHz

mA V_DD= 1.8 to 5.5,

12 MHz

Comparators on. Regulator Off.

I²C wakeup, WDT, and

Comparators on.

1.7

2.4

2.3

I²C wakeup, WDT, and

Comparators on. Regulator Off.

I²C wakeup, WDT, and

Comparators on.

Deep Sleep Mode, –40°C to + 60°C

SID30

I_DD25

I²C wakeup and WDT on.

Regulator Off.

I²C wakeup and WDT on.

–

13.5

µA V_DD= 1.71 to

1.89

µA V_DD= 1.8 to 3.6

µA V_DD= 3.6 to 5.5

SID31

SID32

I_DD26

I_DD27

–

1.3

–

20.0

Deep Sleep Mode, +85°C

SID33

I_DD28

I²C wakeup and WDT on.

Regulator Off.

I²C wakeup and WDT on.

–

45.0

µA V_DD= 1.71 to

1.89

SID34

SID35

I_DD29

I_DD30

–

15

–

60.0

45.0

µA V_DD= 1.8 to 3.6

µA V_DD= 3.6 to 5.5

Hibernate Mode, –40°C to + 60°C

SID39

I_DD34

Regulator Off.

–

1123

nA V_DD= 1.71 to

1.89

SID40

SID41

I_DD35

I_DD36

–

150

–

1600

nA V_DD= 1.8 to 3.6

nA V_DD= 3.6 to 5.5

Hibernate Mode, +85°C

SID42

I_DD37

Regulator Off.

–

4142

nA V_DD= 1.71 to

1.89

SID43

SID44

I_DD38

I_DD39

–

9700

10,400

nA V_DD= 1.8 to 3.6

nA V_DD= 3.6 to 5.5

Stop Mode

SID304

I_DD43A

I_DD43B

Stop Mode current; V_DD= 3.6 V

–

20

–

659

nA T = –40°C to

+60°C

nA T = +85°C

SID304A

1810

XRES current

SID307

I_{DD_XR}

Supply current while XRES (Active

Low) asserted

–

2

5

mA

Datasheet

22 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 4

AC specifications

Details/

Spec ID# Parameter

Description

CPU frequency

Wakeup from sleep mode

Min Typ

Max Units

48

–

conditions

SID48

SID49

F_CPU

T_SLEEP

DC

–

0

MHz 1.71 ≤ V_DD≤ 5.5

µs Guaranteed by

characterization

SID50

T_DEEPSLEEP

Wakeup from Deep Sleep mode

–

25

µs 24-MHz IMO.

Guaranteed by

characterization

SID51

SID51A

SID52

T_HIBERNATE

T_STOP

Wakeup from Hibernate mode

Wakeup from Stop mode

External reset pulse width

–

1

–

0.7

1.9

–

ms Guaranteed by

characterization

ms Guaranteed by

characterization

µs Guaranteed by

characterization

T_RESETWIDTH

Datasheet

23 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.2.1

GPIO

Table 5

GPIO DC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

conditions

[2]

SID57

V_IH

I_IHS

V_IL

Input voltage high threshold

0.7 × V_DD

–

V

CMOS Input

D

–

SID57A

SID58

Input current when Pad > V_DDIO

for OVT inputs

–

10

µA Per I²C Spec

Input voltage low threshold

LVTTL input, V_DDD< 2.7 V

–

0.3 ×

V_DDD

–

V

CMOS Input

[2]

SID241

SID242

V_IH

V_IL

0.7 × V_DD

D

–

0.3 ×

V_DDD

2.0

–

[2]

SID243

SID244

SID59

V_IH

V_IL

LVTTL input, V_DDD≥ 2.7 V

Output voltage high level

–

0.8

V_DDD– 0.6

–

V

V_OH

–

I_OH= 4 mA,

V_DDD≥ 3 V

SID60

SID61

SID62

SID62A

V_OH

Output voltage high level

Output voltage low level

Pull-up resistor

V_DDD– 0.5

–

V

I_OH= 1 mA at 1.8 V

V_DDD

I_OL= 4 mA at 1.8 V

V_DDD

I_OL= 8 mA,

V_DDD≥ 3 V

V_OL

–

0.6

0.4

V_OL

I_OL= 3 mA,

V_DDD≥ 3 V

SID63

SID64

SID65

R_PULLUP

R_PULLDOWNPull-down resistor

I_IL

3.5

–

5.6

–

8.5

2

kΩ

Input leakage current

(absolute value)

nA 25°C, V_DDD= 3.0 V

SID65A

SID66

I_{IL_CTBM}

C_IN

Input leakage current

–

4

7

nA

(absolute value) for CTBM pins

Input capacitance

pF Not applicable for

P6.4, P6.5, P12.0,

P12.1, and for

USB pins.

SID67

SID68

V_HYSTTL

Input hysteresis LVTTL

25

0.05 ×

V_DDD

40

–

mV V_DDD≥ 2.7 V

mV

V_HYSCMOSInput hysteresis CMOS

SID69

I_DIODE

Current through protection

diode to V_DD/Vss

Maximum Total Source or Sink

Chip Current

–

100

200

µA Guaranteed by

characterization

SID69A

I_{TOT_GPIO}

–

mA Guaranteed by

characterization

Note

2. V_IHmust not exceed V_DDD+ 0.2 V.

Datasheet

24 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 6

GPIO AC specifications

(Guaranteed by characterization)^[3]

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

conditions

SID70

SID71

SID72

SID73

SID74

T_RISEF

Rise time in fast strong mode

Fall time in fast strong mode

Rise time in slow strong mode

Fall time in slow strong mode

2

–

12

ns

3.3 V V_DDD

,

Cload = 25 pF

T_FALLF

T_RISES

T_FALLS

F_GPIOUT1

2

10

–

12

60

33

ns

3.3 V V_DDD

Cload = 25 pF

3.3 V V_DDD

Cload = 25 pF

3.3 V V_DDD

Cload = 25 pF

,

GPIO Fout;3.3 V ≤V_DDD≤ 5.5 V. Fast

strong mode.

MHz 90/10%, 25 pF

load, 60/40 duty

cycle

SID75

F_GPIOUT2

F_GPIOUT3

F_GPIOUT4

F_GPIOIN

GPIO Fout;1.7 V≤ V_DDD≤ 3.3 V. Fast

–

16.7

7

MHz 90/10%, 25 pF

load, 60/40 duty

cycle

MHz 90/10%, 25 pF

load, 60/40 duty

cycle

MHz 90/10%, 25 pF

load, 60/40 duty

cycle

strong mode.

SID76

GPIO Fout;3.3 V ≤ V_DDD≤ 5.5 V.

Slow strong mode.

SID245

SID246

GPIO Fout;1.7 V ≤ V_DDD≤ 3.3 V.

Slow strong mode.

3.5

48

GPIO input operating frequency;

1.71 V ≤ V_DDD≤ 5.5 V

MHz 90/10% V_IO

Note

3. Simultaneous switching transitions on many fully-loaded GPIO pins may cause ground perturbations depending on several

factors including PCB and decoupling capacitor design. For applications that are very sensitive to ground perturbations, the

slower GPIO slew rate setting may be used.

Datasheet

25 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.2.2

XRES

Table 7

XRES DC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

conditions

SID77

V_IH

Input voltage high threshold

0.7 ×

V_DDD

–

3.5

–

V

CMOS Input

SID78

SID79

SID80

SID81

V_IL

R_PULLUP

C_IN

Input voltage low threshold

Pull-up resistor

Input capacitance

–

5.6

3

0.3 × V_DDD

V

kΩ

pF

8.5

–

V_HYSXRES

Input voltage hysteresis

–

100

mV Guaranteed by

characterization

SID82

I_DIODE

Current through protection

diode to V_DDD/V_SS

–

100

µA Guaranteed by

characterization

Table 8

XRES AC specifications

Details/

Spec ID# Parameter

Description

Min

1

Typ

–

Max

–

Units

µs

conditions

SID83

T_RESETWIDTHReset pulse width

Guaranteed by

characterization

Datasheet

26 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.3

Analog peripherals

7.3.1

Opamp

Table 9

Opamp specifications

(Guaranteed by characterization)

Spec ID#

Parameter

I_DD

Description

Opamp block current. No

load.

Min Typ Max Units Details/conditions

–

SID269

SID270

SID271

I_{DD_HI}

Power = high

Power = medium

Power = low

Load = 20 pF, 0.1 mA. V_DDA

2.7 V

–

1100 1850

µA

–

I_{DD_MED}

I_{DD_LOW}

GBW

550

150

–

950

350

–

=

SID272

SID273

SID274

GBW_HI

Power = high

Power = medium

Power = low

V_DDA≥ 2.7 V, 500 mV from rail

Power = high

Power = medium

Power = low

V_DDA= 1.71 V, 500 mV from rail

Power = high

6

4

–

1

–

5

–

2

–

MHz

–

mA

–

mA

V

GBW_MED

GBW_LO

I_{OUT_MAX}

I_{OUT_MAX_HI}

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

I_OUT

I_{OUT_MAX_HI}

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

V_IN

–

10

–

4

–

SID275

SID276

SID277

SID278

SID279

SID280

SID281

Power = medium

Power = low

Input voltage range

–0.05

V_DDA

– 0.2

Charge-pump on,

V_DDA≥ 2.7 V

SID282

V_CM

Input common mode voltage –0.05

–

VDDA

– 0.2

V

Charge-pump on,

V_DDA≥ 2.7 V

V_OUT

V_{OUT_1}

V_DDA≥ 2.7 V

Power = high, I_load=10 mA

–

0.5

–

SID283

SID284

SID285

SID286

VDDA

– 0.5

V

V_{OUT_2}

V_{OUT_3}

V_{OUT_4}

Power = high, I_load=1 mA

0.2

–

VDDA

– 0.2

VDDA

– 0.2

VDDA

– 0.2

Power = medium, I_load=1 mA 0.2

Power = low, I_load=0.1mA

0.2

SID288

SID288A

SID288B

SID290

SID290A

SID290B

SID291

SID292

V_{OS_TR}

V_{OS_DR_TR}

CMRR

Offset voltage, trimmed

1

–

±0.5

±1

±2

1

–

10

–

mV

High mode

Medium mode

Low mode

Offset voltage drift, trimmed –10

±3

µV/°C High mode

µV/°C Medium mode

µV/°C Low mode

dB

Offset voltage drift, trimmed

DC

–

60

70

±10

70

–

V

_DDD= 3.6 V

PSRR

At 1 kHz, 100 mV ripple

85

VDDD = 3.6 V

Datasheet

27 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 9

Opamp specifications

(Guaranteed by characterization) ^(continued)

Spec ID#

Parameter

Noise

V_N1

Description

Min Typ Max Units Details/conditions

–

94

–

SID293

SID294

SID295

SID296

SID297

SID298

SID299

SID299A

Input referred, 1 Hz - 1GHz,

power = high

Input referred, 1 kHz, power =

high

Input referred, 10kHz, power

= high

Inputreferred, 100kHz, power

= high

Stable up to maximum load.

Performance specs at 50 pF.

Cload = 50 pF, Power = High,

V_DDA≥ 2.7 V

µVrms

V_N2

–

6

–

72

28

15

–

nV/rtHz

pF

V_N3

V_N4

–

Cload

Slew_rate

T_op_wake

OL_GAIN

125

–

V/µs

From disable to enable, no

external RC dominating

Open Loop Gain

25

–

µs

–

90

–

dB

Comp_mode Comparator mode; 50 mV

drive,

T_rise= T_fall(approx.)

SID300

SID301

T_PD1

T_PD2

Response time; power = high

Response time; power =

medium

–

150

400

–

ns

SID302

SID303

T_PD3

Vhyst_op

Response time; power = low

Hysteresis

–

2000

10

–

ns

mV

Deep Sleep Mode

Mode 2 is lowest current

range. Mode 1 has higher

GBW.

Deep Sleep mode

V_DDA≥ 2.7 V.

SID_DS_1 IDD_HI_M1

SID_DS_2 IDD_MED_M1 Mode 1, Medium current

SID_DS_3 IDD_LOW_M1 Mode 1, Low current

SID_DS_4 IDD_HI_M2

SID_DS_5 IDD_MED_M2 Mode 2, Medium current

SID_DS_6 IDD_LOW_M2 Mode 2, Low current

Mode 1, High current

–

1400

700

200

120

60

–

µA

25°C

Mode 2, High current

15

4

SID_DS_7 GBW_HI_M1

Mode 1, High current

MHz 20-pF load, no DC

load

0.2 V to V_DDA– 1.5 V

SID_DS_8 GBW_MED_M1 Mode 1, Medium current

SID_DS_9 GBW_LOW_M1 Mode 1, Low current

–

2

–

MHz 20-pF load, no DC

load

0.2 V to V_DDA– 1.5 V

0.5

MHz 20-pF load, no DC

load

0.2 V to V_DDA– 1.5 V

SID_DS_10 GBW_HI_M2

Mode 2, High current

MHz 20-pF load, no DC

load 0.2 V to V_DDA

1.5 V

–

Datasheet

28 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 9

(Guaranteed by characterization) ^(continued)

Spec ID# Parameter Description

Opamp specifications

Min Typ Max Units Details/conditions

SID_DS_11 GBW_MED_M2 Mode 2, Medium current

–

0.2

–

MHz 20-pF load, no DC

load 0.2 V to V_DDA

1.5 V

MHz 20-pF load, no DC

load 0.2 V to V_DDA

1.5 V

–

SID_DS_12 GBW_LOW_M2 Mode 2, Low current

–

0.1

–

SID_DS_13 VOS_HI_M1

Mode 1, High current

–

5

–

mV

mA

With trim 25°C, 0.2 V

to V_DDA– 1.5 V

SID_DS_14 VOS_MED_M1 Mode 1, Medium current

SID_DS_15 VOS_LOW_M1 Mode 1, Low current

With trim 25°C, 0.2 V

to V_DDA– 1.5 V

With trim 25°C, 0.2 V

to V_DDA– 1.5 V

With trim 25°C, 0.2 V

to V_DDA– 1.5 V

With trim 25°C, 0.2 V

to V_DDA– 1.5 V

5

SID_DS_16 VOS_HI_M2

Mode 2, High current

5

SID_DS_17 VOS_MED_M2 Mode 2, Medium current

SID_DS_18 VOS_LOW_M2 Mode 2, Low current

5

With trim 25°C, 0.2 V

to V_DDA-1.5 V

SID_DS_19 IOUT_HI_M1

Mode 1, High current

10

4

Output is 0.5 V to

V_DDA-0.5 V

SID_DS_20 IOUT_MED_M1 Mode 1, Medium current

SID_DS_21 IOUT_LOW_M1 Mode 1, Low current

Output is 0.5 V to

V_DDA-0.5 V

Output is 0.5 V to

V_DDA-0.5 V

SID_DS_22 IOUT_HI_M2

Mode 2, High current

1

Output is 0.5 V to

_DDA-0.5 V

V

SID_DS_23 IOUT_MED_M2 Mode 2, Medium current

SID_DS_24 IOUT_LOW_M2 Mode 2, Low current

1

Output is 0.5 V to

V_DDA-0.5 V

0.5

Output is 0.5 V to

V_DDA-0.5 V

Datasheet

29 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.3.2

Comparator

Table 10

Comparator DC specifications

Spec ID# Parameter

Description

Min Typ

Max

Units Details/conditions

SID85

SID85A

SID86

V_OFFSET2

V_OFFSET3

V_HYST

Input offset voltage. Custom

trim. Common mode voltage

range from 0 to V_DD-1.

Input offset voltage. Ultra

low-power mode.

–

±4

mV

±12

10

–

mV V_DDD≥2.2 V for Temp <

0°C, V_DDD≥ 1.8 V for

Temp > 0°C

mV Guaranteed by

characterization

Hysteresis when enabled.

Common mode voltage range

from 0 to V_DD-1.

35

SID87

V_ICM1

V_ICM2

Input common mode voltage

in normal mode

Input common mode voltage

in low power mode

Input common mode voltage

in ultra low power mode

0

–

V_DDD

0.2

V_DDD

–

V

Modes 1 and 2.

SID247

SID247A V_ICM2

V_DDD

1.15

–

V_DDD≥2.2 V for Temp <

0°C, V_DDD≥ 1.8 V for

Temp > 0°C

SID88

CMRR

Common mode rejection ratio 50

Common mode rejection ratio 42

–

dB V_DDD≥ 2.7 V.

Guaranteed by

characterization

SID88A

dB V_DDD< 2.7 V.

Guaranteed by

characterization

SID89

I_CMP1

I_CMP2

I_CMP3

Block current, normal mode

Blockcurrent,lowpowermode

–

280

50

6

400

100

28

µA Guaranteed by

characterization

µA Guaranteed by

characterization

SID248

SID259

Block current, ultra low power

mode

µA Guaranteed by

characterization, V_DDD

≥ 2.2 V for Temp < 0°C,

V_DDD≥1.8 V for Temp >

0°C

SID90

Z_CMP

DC input impedance of

comparator

35

–

MΩ Guaranteed by

characterization

Table 11

Comparator AC specifications

(Guaranteed by characterization)

Details/

Spec ID# Parameter

Description

Response time, normal mode

Response time, low power mode

Response time, ultra low power

mode

Min

–

Typ

38

70

Max

110

200

15

Units

conditions

ns 50-mV overdrive

µs 200-mV

SID91

SID258

SID92

T_RESP1

T_RESP2

T_RESP3

–

2.3

overdrive. V_DDD

2.2 V for Temp <

0°C, V_DDD≥ 1.8 V

for Temp > 0°C

≥

Datasheet

30 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.3.3

Temperature sensor

Table 12

Temperature sensor specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

conditions

SID93

T_SENSACC

Temperature sensor accuracy

–5

±1

+5

°C –40 to +85°C

7.3.4

SAR ADC

Table 13

SAR ADC DC specifications

Details/

Spec ID# Parameter

Description

Resolution

Min Typ

Max

12

16

Units

bits

conditions

SID94

SID95

A_RES

–

A_CHNIS_S Number of channels - single

ended

SID96

SID97

SID98

SID99

A-CHNKS_D Number of channels - differential

–

8

–

Diff inputs use

neighboring I/O

A-MONO

Monotonicity

Yes. Based on

characterization

With external

reference.

A_GAINERR Gain error

±0.1

2

%

A_OFFSET Input offset voltage

mV Measured with 1-V

V_REF.

SID100

SID101

A_ISAR

A_VINS

Current consumption

Input voltage range - single ended V_SS

–

1

V_DDA

mA

V

Based on device

characterization

SID102

SID103

SID104

A_VIND

Input voltage range - differential

Input resistance

V_SS

–

V_DDA

2.2

V

Based on device

characterization

A_INRES

A_INCAP

kΩ Based on device

characterization

Input capacitance

–

10

pF Based on device

characterization

Table 14

SAR ADC AC specifications

(Guaranteed by characterization)

Details/

Spec ID# Parameter

Description

Power supply rejection ratio

Common mode rejection ratio

Min Typ

Max

Units

dB

conditions

SID106

SID107

SID108

A_PSRR

A_CMRR

70

66

–

1

dB Measured at 1 V

Msps

A_SAMP_1 Sample rate with external

reference bypass cap

SID108A A_SAMP_2 Sample rate with no bypass cap.

Reference = V_DD

SID108B A_SAMP_3 Sample rate with no bypass cap.

Internal reference

–

500

100

–

ksps

SID109

A_SNDR

Signal-to-noise and distortion

ratio (SINAD)

65

dB

F_IN= 10 kHz

Datasheet

31 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 14

SAR ADC AC specifications

(Guaranteed by characterization) (continued)

Details/

Spec ID# Parameter

SID111 A_INL

Description

Integral non linearity

Min Typ

Max

+2

Units

conditions

–1.7

–1.5

–1

–

LSB V_DD= 1.71 to 5.5,

1 Msps, V_REF= 1 to

5.5.

SID111A A_INL

SID111B A_INL

Integral non linearity

+1.7

+2.2

+2

LSB

dB

V

_DDD= 1.71 to 3.6,

1 Msps, V_REF= 1.71

to V_DDD

.

Integral non linearity

V_DDD= 1.71 to 5.5,

500 ksps, V_REF= 1

to 5.5.

V_DDD= 1.71 to5.5, 1

Msps, V_REF= 1 to

5.5.

SID112

A_DNL

Differential non linearity

Total harmonic distortion

SID112A A_DNL

SID112B A_DNL

–1

V

_DDD= 1.71 to3.6, 1

Msps,V_REF=1.71to

V_DDD

.

–1

+2.2

–65

V_DDD= 1.71 to 5.5,

500 ksps, V_REF= 1

to 5.5.

SID113

A_THD

–

F

_IN= 10 kHz.

7.3.5

CSD

Table 15

CSD block specification

Spec

ID#

Details/

Parameter

Description

Min Typ

Max Units

conditions

CSD specification

SID308 VCSD

SID309 IDAC1

SID310 IDAC1

SID311 IDAC2

SID312 IDAC2

SID313 SNR

Voltage range of operation

DNL for 8-bit resolution

INL for 8-bit resolution

DNL for 7-bit resolution

INL for 7-bit resolution

1.71

–1

–3

–1

–3

5

–

5.5

1

3

1

3

V

LSB

Ratio of counts of finger to noise.

Guaranteed by characterization

–

Ratio Capacitance range

of 9 to 35 pF, 0.1 pF

sensitivity

SID314 IDAC1_CRT1 Output current of Idac1 (8-bits) in

high range

SID314A IDAC1_CRT2 Output current of Idac1(8-bits) in

low range

SID315 IDAC2_CRT1 Output current of Idac2 (7-bits) in

high range

SID315A IDAC2_CRT2 Output current of Idac2 (7-bits) in

low range

–

612

306

–

µA

304.8

152.4

Datasheet

32 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.4

Digital peripherals

The following specifications apply to the Timer/Counter/PWM peripheral in timer mode.

7.4.1

Timer/counter/PWM

Table 16

TCPWM specifications

(Guaranteed by characterization)

Details/

Spec ID# Parameter

Description

Min

Typ Max Units

conditions

All modes

Block current consumption

at 3 MHz

SID.TCPWM.1 ITCPWM1

SID.TCPWM.2 ITCPWM2

SID.TCPWM.2A ITCPWM3

45

µA (Timer/Counter/

PWM)

–

All modes

µA (Timer/Counter/

PWM)

All modes

µA (Timer/Counter/

PWM)

Block current consumption

at 12 MHz

155

–

Block current consumption

at 48 MHz

650

Fc

–

Fc max = Fcpu.

Maximum = 48 MHz

SID.TCPWM.3 TCPWMFREQ Operating frequency

MHz

Trigger Events can

be Stop, Start,

Reload, Count,

Input Trigger Pulse Width

SID.TCPWM.4 TPWMENEXT

2/Fc

ns Capture, or Kill

depending on which

mode of operation is

selected.

–

for all Trigger Events

Minimum possible

width of Overflow,

Underflow, and CC

ns

Output Trigger Pulse

SID.TCPWM.5 TPWMEXT

widths

2/Fc

–

(Counter equals

Compare value)

trigger outputs

Minimum time

ns between successive

counts

Minimum pulse

ns width of PWM

Output

SID.TCPWM.5A TCRES

SID.TCPWM.5B PWMRES

Resolution of Counter

PWM Resolution

1/Fc

–

Minimum pulse

Quadrature inputs

resolution

width between

SID.TCPWM.5C QRES

1/Fc

ns

–

Quadrature phase

inputs.

Datasheet

33 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.4.2

Table 17

I²C

Fixed I²C DC specifications

(Guaranteed by characterization)

Spec ID# Parameter

SID149 I_I2C1

Description

Block current consumption

at 100 kHz

Min Typ

Max Units Details/conditions

–

10.5

55

135

310

1.4

µA

SID150

SID151

SID152

I_I2C2

I_I2C3

I_I2C4

Block current consumption

at 400 kHz

Block current consumption

at 1 Mbps

I²C enabled in Deep Sleep

mode

–

Table 18

Fixed I²C AC specifications

(Guaranteed by characterization)

Spec ID#

SID153

Parameter

F_I2C1

Description

Min

–

Typ Max Units Details/conditions

Mbps

Bit rate

–

1

Datasheet

34 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.4.3

LCD direct drive

Table 19

LCD direct drive DC specifications

(Guaranteed by characterization)

Details/

Spec ID# Parameter

Description

Min

Typ Max Units

conditions

SID154 I_LCDLOW

Operating current in low power

mode

–

5

–

µA 16 × 4 small segment

disp. at 50 Hz

SID155 C_LCDCAP

LCD capacitance per

–

500 5000

pF Guaranteed by Design

mV

segment/common driver

SID156 LCD_OFFSETLong-term segment offset

SID157 I_LCDOP1

–

20

–

PWM Mode current. 5-V bias.

24-MHz IMO

0.6

mA 32 × 4 segments.

50 Hz, 25°C

SID158 I_LCDOP2

PWM Mode current. 3.3-V bias.

24-MHz IMO.

–

0.5

–

mA 32 × 4 segments.

50 Hz, 25°C

Table 20

LCD direct drive AC specifications

(Guaranteed by characterization)

Spec ID# Parameter

Description

LCD frame rate

Min

10

Typ

50

Max Units Details/conditions

SID159

F_LCD

150

Hz

Table 21

Fixed UART DC specifications

(Guaranteed by characterization)

Spec ID# Parameter

Description

Min Typ Max Units Details/conditions

SID160

I_UART1

Block current consumption at

100 Kbits/sec

–

9

55

µA

SID161

I_UART2

Block current consumption at

1000 Kbits/sec

–

312

µA

Table 22

Fixed UART AC specifications

(Guaranteed by characterization)

Spec ID# Parameter

Description

Min Typ Max Units Details/conditions

Mbps

SID162

F_UART

Bit rate

–

1

Datasheet

35 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.4.4

SPI specifications

Table 23

Fixed SPI DC specifications

(Guaranteed by characterization)

Spec ID# Parameter

SID163

Description

Block current consumption at

1 Mbits/sec

Block current consumption at

4 Mbits/sec

Block current consumption at

8 Mbits/sec

Min

–

Typ

–

Max

360

Units

µA

I_SPI1

I_SPI2

I_SPI3

SID164

SID165

–

560

600

µA

Table 24

Fixed SPI AC specifications

(Guaranteed by characterization)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

SID166

F_SPI

SPI operating frequency (master; 6X

oversampling)

–

8

MHz

Table 25

Fixed SPI master mode AC specifications

(Guaranteed by characterization)

Spec ID#

SID167

SID168

Parameter

T_DMO

T_DSI

Description

MOSI valid after Sclock driving edge

MISO valid before Sclock capturing

edge. Full clock, late MISO Sampling

used

Min

–

20

Typ

–

Max

15

–

Units

ns

SID169

T_HMO

Previous MOSI data hold time with

respect to capturing edge at Slave

0

–

ns

Table 26

Fixed SPI slave mode AC specifications

(Guaranteed by characterization)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

SID170

T_DMI

MOSI valid before Sclock capturing

edge

40

–

ns

SID171

T_DSO

MISO valid after Sclock driving edge

–

42+3×

T_SCB

ns

SID171A

T_{DSO_ext}

MISO valid after Sclock driving edge

in Ext. Clock mode

48

SID172

SID172A

T_HSO

T_SSELSCK

Previous MISO data hold time

SSEL Valid to first SCK Valid edge

0

100

–

ns

Datasheet

36 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.5

Memory

Table 27

Flash DC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max Units

conditions

SID173

V_PE

Erase and program voltage 1.71

–

5.5

V

Table 28

Flash AC specifications

Spec ID# Parameter

Description

Min

Typ

Max

Units Details/conditions

SID174

T_ROWWRITE

Row (block) write time

(erase and program)

–

20

ms

Row (block) =

256 bytes

SID175

SID176

T_ROWERASE

T_ROWPROGRAMRow program time after

erase

Row erase time

–

13

7

ms

SID178

SID180

T_BULKERASE

T_DEVPROG

Bulk erase time (128 KB)

Total device program time

–

35

ms

15 seconds Guaranteed by

characterization

SID181

SID182

SID182A

F_END

F_RET

Flash endurance

100 k

20

–

cycles Guaranteed by

characterization

years Guaranteed by

characterization

years Guaranteed by

characterization

years Guaranteed by

characterization.

Flash retention. T_A≤ 55°C,

100 k P/E cycles

Flash retention. T_A≤ 85°C,

10 k P/E cycles

Flash retention. T_A≤ 105°C,

10 k P/E cycles, ≤ three years

at T_A≥ 85°C

10

–

SID182B F_RETQ

10

20

Datasheet

37 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.6

System resources

7.6.1

Power-on reset (POR) with brown out

Table 29

Imprecise power-on reset (PRES)

Spec ID#

Parameter

Description

Min

Typ

Max Units Details/conditions

SID185

V_RISEIPOR

Rising trip voltage

0.80

–

1.45

V

Guaranteed by

characterization

SID186

SID187

V_FALLIPOR

V_IPORHYST

Falling trip voltage

Hysteresis

0.75

15

–

1.4

V

Guaranteed by

characterization

200

mV Guaranteed by

characterization

Table 30

Precise power-on reset (POR)

Spec ID# Parameter

Description

Min

Typ

Max Units Details/conditions

SID190

V_FALLPPOR

BOD trip voltage in active

and sleep modes

1.64

–

V

Guaranteed by

characterization

SID192

V_FALLDPSLP

BOD trip voltage in Deep

Sleep

1.4

–

V

Guaranteed by

characterization

7.6.2

Voltage monitors

Table 31

Voltage monitors DC specifications

Spec ID# Parameter

Description

Min

1.71

1.76

1.85

1.95

2.05

2.15

2.24

2.34

2.44

2.54

2.63

2.73

2.83

2.93

3.12

4.39

–

Typ

1.75

1.80

1.90

2.00

2.10

2.20

2.30

2.40

2.50

2.60

2.70

2.80

2.90

3.00

3.20

4.50

–

Max Units Details/conditions

SID195

SID196

SID197

SID198

SID199

SID200

SID201

SID202

SID203

SID204

SID205

SID206

SID207

SID208

SID209

SID210

SID211

V_LVI1

V_LVI2

V_LVI3

V_LVI4

V_LVI5

V_LVI6

V_LVI7

V_LVI8

LVI_A/D_SEL[3:0] = 0000b

LVI_A/D_SEL[3:0] = 0001b

LVI_A/D_SEL[3:0] = 0010b

LVI_A/D_SEL[3:0] = 0011b

LVI_A/D_SEL[3:0] = 0100b

LVI_A/D_SEL[3:0] = 0101b

LVI_A/D_SEL[3:0] = 0110b

LVI_A/D_SEL[3:0] = 0111b

LVI_A/D_SEL[3:0] = 1000b

LVI_A/D_SEL[3:0] = 1001b

LVI_A/D_SEL[3:0] = 1010b

LVI_A/D_SEL[3:0] = 1011b

LVI_A/D_SEL[3:0] = 1100b

LVI_A/D_SEL[3:0] = 1101b

LVI_A/D_SEL[3:0] = 1110b

LVI_A/D_SEL[3:0] = 1111b

Block current

1.79

1.85

1.95

2.05

2.15

2.26

2.36

2.46

2.56

2.67

2.77

2.87

2.97

3.08

3.28

4.61

100

V

V_LVI9

V_LVI10

V_LVI11

V_LVI12

V_LVI13

V_LVI14

V_LVI15

V_LVI16

LVI_IDD

µA Guaranteed by

characterization

Table 32

Voltage monitors AC specifications

Spec ID# Parameter

Description

Min

Typ

Max

Units Details/conditions

SID212 T_MONTRIP

Voltage monitor trip time

–

1

µs Guaranteed by

characterization

Datasheet

38 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.6.3

SWD interface

Table 33

SWD interface specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details/conditions

SID213 F_SWDCLK1

3.3 V ≤ V_DD≤ 5.5 V

–

14

MHz SWDCLK ≤ 1/3 CPU

clock frequency

SID214 F_SWDCLK2

1.71 V ≤ V_DD≤ 3.3 V

–

7

MHz SWDCLK ≤ 1/3 CPU

clock frequency

SID215 T_SWDI_SETUP T = 1/f SWDCLK

SID216 T_SWDI_HOLD T = 1/f SWDCLK

0.25 * T

–

ns

Guaranteed by

characterization

0.25 * T

–

0.5 * T

–

Guaranteed by

characterization

Guaranteed by

characterization

Guaranteed by

characterization

SID217 T_SWDO_VALID T = 1/f SWDCLK

SID217A T_SWDO_HOLD T = 1/f SWDCLK

–

1

7.6.4

Internal main oscillator

Table 34

IMO DC specifications

(Guaranteed by design)

Details/

Spec ID# Parameter

SID218 I_IMO1

SID219 I_IMO2

SID220 I_IMO3

SID221 I_IMO4

SID222 I_IMO5

Description

Min

Typ

Max

1000

325

225

180

Units

conditions

IMO operating current at 48 MHz

IMO operating current at 24 MHz

IMO operating current at 12 MHz

IMO operating current at 6 MHz

IMO operating current at 3 MHz

–

µA

150

Table 35

IMO AC specifications

Details/

Spec ID#

SID223

Parameter

F_IMOTOL1

Description

Frequency variation from 3 to

48 MHz

Min

–

Typ

–

Max

±2

Units

%

conditions

SID226

SID227

SID228

SID229

T_STARTIMO

IMO startup time

–

12

–

µs

ps

T_JITRMSIMO1

T_JITRMSIMO2

T_JITRMSIMO3

RMS Jitter at 3 MHz

RMS Jitter at 24 MHz

RMS Jitter at 48 MHz

156

145

139

–

Datasheet

39 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

7.6.5

Internal low-speed oscillator

Table 36

ILO DC specifications

(Guaranteed by design)

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

conditions

SID231 I_ILO1

ILO operating current at 32

kHz

–

0.3

1.05

µA

Guaranteed by

characterization

SID233 I_ILOLEAK

ILO leakage current

–

2

15

nA

Guaranteed by

design

Table 37

ILO AC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

conditions

SID234 T_STARTILO1

ILO startup time

–

2

ms Guaranteed by

characterization

SID236 T_ILODUTY

SID237 F_ILOTRIM1

ILO duty cycle

40

15

50

32

60

50

%

Guaranteed by

characterization

32 kHz trimmed frequency

kHz ±60% with trim.

Table 38

PLL DC specifications

Details/

Units

Spec ID# Parameter

Description

Min

Typ

Max

conditions

SID410 IDD_PLL_48

SID411 IDD_PLL_24

In = 3 MHz, Out = 48 MHz

In = 3 MHz, Out = 24 MHz

–

530

300

610

405

µA

Table 39

PLL AC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max Units

conditions

SID412 F_PLLIN

SID413 F_PLLINT

PLL input frequency

PLL intermediate frequency;

prescaler out

1

–

48

3

MHz

SID414 F_PLLVCO

SID415 D_IVVCO

VCO output frequency before 22.5

post-divide

–

104

8

MHz

–

VCO Output post-divider

range; PLL output frequency

is F_PPLVCO/D_IVVCO

1

SID416 PLLlocktime

SID417 Jperiod_1

Lock time at startup

Period jitter for VCO ≥ 67 MHz

–

250

150

us

ps Guaranteed By

design

SID416A Jperiod_2

Period jitter for VCO ≤ 67 MHz

–

200

ps Guaranteed By

design

Datasheet

40 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 40

External clock specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

conditions

SID305 ExtClkFreq

External clock input

frequency

0

–

48

MHz Guaranteed by

characterization

SID306 ExtClkDuty

Duty cycle; Measured at V_DD/2

45

–

55

%

Guaranteed by

characterization

Table 41

Watch crystal oscillator (WCO) specifications

Details /

Spec ID# Parameter

Description

Min

Typ

Max Units

conditions

IMO WCO-PLL calibrated mode

SID330 IMOWCO1

SID331 IMOWCO2

SID332 IMOWCO3

SID333 IMOWCO4

Frequency variation with IMO –0.6

set to 3 MHz

Frequency variation with IMO –0.4

set to 5 MHZ

Frequency variation with IMO –0.3

set to 7 or 9 MHZ

–

0.6

0.4

0.3

0.2

%

Does not include

WCO tolerance

Does not include

WCO tolerance

Does not include

WCO tolerance

Does not include

WCO tolerance

All other IMO frequency

settings

–0.2

WCO specifications

SID398 FWCO

SID399 FTOL

Crystal frequency

Frequency tolerance

–

32.768

50

–

250

kHz

ppm With 20-ppm

crystal.

SID400 ESR

SID401 PD

SID402 TSTART

SID403 CL

SID404 C0

SID405 IWCO1

Equivalent series resistance

Drive Level

Startup time

Crystal load capacitance

Crystal shunt capacitance

Operating current (high power

mode)

–

6

–

50

–

1.35

–

1

500

12.5

–

kΩ

µW

ms

pF

uA

8

Table 42

External crystal oscillator (ECO) specifications

Details/

Spec ID# Parameter

SID316 IECO1

SID317 FECO

Description

Block operating current

Crystal frequency range

Min

–

4

Typ

–

Max Units

conditions

1.5

33

mA

MHz

Datasheet

41 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 43

UDB AC specifications

(Guaranteed by characterization)

Details/

Spec ID#

Parameter

Description

Min Typ

Max

Units

conditions

Datapath performance

SID249 F_MAX-TIMER

Max frequency of 16-bit timer in

a UDB pair

Maxfrequencyof16-bitadderin

a UDB pair

Max frequency of 16-bit

CRC/PRS in a UDB pair

–

48

MHz

SID250 F_MAX-ADDER

SID251 F_{MAX_CRC}

PLD performance in UDB

SID252 F_{MAX_PLD}

Max frequency of 2-pass PLD

function in a UDB pair

–

48

MHz

Clock to output performance

SID253 T_{CLK_OUT_UDB1}Prop. delay for clock in to data

out at 25°C, Typ.

SID254 T_{CLK_OUT_UDB2}Prop. delay for clock in to data

out, Worst case.

–

15

25

–

ns

Table 44

Block specs

Parameter

Details/

Spec ID#

Description

Min Typ Max Units

conditions

SID256

T_WS48

Number of wait states at

48 MHz

2

–

CPU execution

from Flash.

Guaranteed by

characterization

SID257

SID260

T_WS24

Number of wait states at

24 MHz

1

–

CPU execution

from Flash.

Guaranteed by

characterization

Percentage of Vbg

(1.024 V).

Guaranteed by

characterization

V_REFSAR

Trimmed internal reference to

SAR

–1

+1

%

SID261

SID262

F_SARINTREF

SAR operating speed without

external reference bypass

–

3

500

–

4

ksps 12-bit resolution.

Guaranteed by

characterization

T_CLKSWITCH

Clock switching from clk1 to

clk2 in clk1 periods

Periods Guaranteed by

design

* Tws48 and Tws24 are guaranteed by design

Datasheet

42 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 45

(Based on LPC Component Specs; all specs except TLCLKDO are guaranteed by design -10-pF load, 3-V V_DDIOand

V_DDD

UDB port adaptor specifications

)

Details/

Spec ID#

SID263

Parameter

T_LCLKDO

Description

Min

–

Typ

–

Max Units

conditions

LCLK to output delay

18

7

ns

SID264

T_DINLCLK

Input setup time to LCLCK

rising edge

–

SID265

T_DINLCLKHLD

Input hold time from LCLK

rising edge

0

–

ns

SID266

SID267

SID268

T_LCLKHIZ

T_FLCLK

LCLK to output tristated

LCLK frequency

–

28

33

60

ns

MHz

%

T_LCLKDUTY

LCLK duty cycle (percentage

high)

40

Table 46

USB device block specifications (USB only)

Details /

Spec ID# Parameter

Description

Min

Typ

Max Units

conditions

SID321

SID322

SID323

Vusb_5

Vusb_3.3

Vusb_3

Device supply for USB

operation

Device supply for USB

operation

Device supply for USB

operation (Functional

operation only)

4.5

–

5.5

3.6

V

USB Configured, USB

Reg. enabled

USB Configured, USB

Reg. bypassed

USB Configured, USB

Reg. bypassed

3.15

2.85

SID324

SID325

SID326

SID327

SID328

SID329

Iusb_config

Device supply current in

–

10

8

–

mA

V

_DDD= 5 V

Active mode, IMO = 24 MHz

Device supply current in

Active mode, IMO = 24 MHz

_DDD= 3.3 V

Isub_suspend Device supply current in

Sleep mode

Isub_suspend Device supply current in

Sleep mode

Isub_suspend Device supply current in

Sleep mode

Isub_suspend Device supply current in

Sleep mode

0.5

0.3

0.5

0.3

_DDD= 5 V, PICU

wakeup

_DDD= 5 V, Device

disconnected

_DDD= 3.3 V, PICU

wakeup

_DDD= 3.3 V, Device

disconnected

V

Datasheet

43 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 47

SIO specifications

Spec

ID#

Parameter

Description

Min

Typ

Max

Units Details / conditions

SIO DC specifications

SID330 V_IH

Input voltage high

threshold

Input voltage low threshold

0.7 * V_DD

–

0.3*VDD

–

V

CMOS input; with

respect to V_DDIO

CMOS input; with

respect to V_DDIO

Vr is the SIO reference

voltage

SID331 V_IL

SID332 V_IH

Differential input mode

high voltage; hysteresis

disabled

Vr + 0.2

SID333 V_IL

SID334 V_OH

SID335 V_OH

SID336 V_OH

SID337 V_OL

SID338 V_OL

Differential input mode low

voltage, hysteresis disabled

Output high voltage in

unregulated mode

Output high voltage in

regulated mode

Output high voltage in

regulated mode

Output low voltage

Input voltage reference

Output voltage reference

(regulated mode)

Output voltage reference

(regulated mode)

–

V_DDIO– 0.4

Vr – 0.65

Vr – 0.3

–

Vr-0.2

–

V

Vr is the SIO reference

voltage

I_OH= 4 mA, V_DD= 3.3 V

Vr + 0.2

0.8

I_OH= 1 mA

I_OH= 0.1 mA

V_DDIO= 3.3 V, I_OL= 25

mA

V_DDIO= 1.8 V, I_OL= 4

mA

–

0.4

SID339 Vinref

SID340 Voutref

0.48

1

–

0.52 * V_DDIO

V

_DDIO– 1

V_DDIO> 3.3

V_DDIO< 3.3

SID341 Voutref

1

–

V

_DDIO– 0.5

V

SID342 R_PULLUP

SID343 R_PULLDOWN

SID344 I_IL

Pull-up resistor

Pull-down resistor

Input leakage current

(absolute value)

3.5

–

5.6

–

8.5

14

kΩ

nA V_IH≤ V_DDSIO; 25°C

SID345 I_IL

Input leakage current

(absolute value)

–

10

nA V_IH> V_DDSIO; 25°C

SID346 C_IN

Input capacitance

–

40

7

–

pF

mV

SID347 VHYST-Single Hysteresis in single-ended

mode

SID348 VHYST_Diff

Hysteresis in differential

mode

Current through protection

diode to V_DD/V_SS

–

35

–

mV

µA

SID349 I_DIODE

100

SIO AC specifications (Guaranteed by design)

SID350 T_RISEF

Rise time in Fast Strong

mode

Fall time in Fast Strong

mode

–

12

ns 3.3-V V_DD, Cload = 25

pF

ns 3.3-V V_DD, Cload = 25

pF

SID351 T_FALLF

Datasheet

44 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Electrical specifications

Table 47

SIO specifications ^(continued)

Spec

ID#

Parameter

Description

Min

Typ

Max

Units Details / conditions

SID352 T_RISES

SID353 T_FALLS

SID354 F_SIOUT1

Rise time in Slow Strong

mode

Fall time in Slow Strong

mode

SIO Fout; Unregulated, Fast

Strong mode

–

75

ns 3.3-V V_DD, Cload = 25

pF

ns 3.3-V V_DD, Cload = 25

pF

MHz 3.3-V ≤ V_DD≤ 5.5 V,

25 pF. Guaranteed by

design.

–

70

33

SID355 F_SIOUT2

SID356 F_SIOUT3

SID357 F_SIOUT4

SID358 F_SIOUT3

SID359 F_SIOUT4

SID360 F_SIOUT5

SID361 F_GPIOIN

SIO Fout; Unregulated, Fast

Strong mode

SIO Fout; Regulated, Fast

Strong mode

SIO Fout; Regulated, Fast

Strong mode

SIO Fout; Unregulated,

Slow Strong mode.

SIO Fout, Unregulated,

Slow Strong mode.

SIO Fout, Regulated, Slow

Strong mode.

–

16

20

10

5

MHz 1.71-V ≤ V_DD≤ 3.3 V,

25 pF

MHz 3.3-V ≤ V_DD≤ 5.5 V,

25 pF

MHz 1.71 V ≤ V_DD≤ 3.3 V,

25 pF

MHz 3.3 V ≤ V_DD≤ 5.5 V,

25 pF

3.5

2.5

48

MHz 1.71 V ≤ V_DD≤ 3.3 V,

25 pF

MHz 1.7 V ≤ V_DD≤ 5.5 V,

25 pF

GPIO input operating

MHz 1.71 V ≤ V_DD≤ 5.5 V

frequency;1.71 V ≤ V_DD

≤

5.5 V

Table 48

CAN specifications

Spec

ID#

Parameter

Description

Min

Typ

Max

Units Details / conditions

SID420 IDD_CAN

SID421 CAN_bits

Block current consumption

CAN Bit rate (Min 8-MHz

clock)

–

200

1

uA

Mbps

Datasheet

45 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Ordering information

8

Ordering information

The PSoC™ 4200L family part numbers and features are listed in the following table.

Table 49 PSoC™ 4200L ordering information

Features

Package

MPN

4248 CY8C4248BZA-L489 48 256 32

CY8C4248BZS-L489 48 256 32

8

4

1

Yes 1000 ksps

2

8

4

Yes Yes 98

Yes

The nomenclature used in Table 49 is based on the following part numbering convention:

Table 50

MPN nomenclature

Description

Infineon prefix

Architecture

Family

Field

Values

Meaning

CY8C

4

A

B

C

4

2

4

PSoC™ 4

4200 family

48 MHz

CPU speed

Flash capacity

6

64 KB

7

128 KB

8

256 KB

DE

Package code

AX, AZ

TQFP

LT

Q FN

BZ

BGA

FD

CSP

F

S

Temperature range

Series designator

A

S

L

M

Auto A (-40 to +85°C)

AUTO S (-40 to +105°C)

PSoC™ 4 S-Series

PSoC™ 4 L-Series

PSoC™ 4 M-Series

XYZ

Attributes code

000-999

Code of feature set in the specific family

Datasheet

46 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Ordering information

8.1

Part numbering conventions

The part number fields are defined as follows.

CY8C

4

A

B C D E

F

-

S

X Y Z

Infineon prefix

Architecture

Family group within architecture

Speed grade

Flash capacity

Package code

Temperature range

Series designator

Attributes code

Datasheet

47 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Packaging

9

Packaging

Table 51

Package dimensions

SPEC ID#

PKG_1

Package

124-ball VFBGA

Description

124-ball, 9 mm x 9 mm x 1.0 mm height with

0.65 mm ball pitch

Package DWG #

001-97718

Table 52

Parameter

T_A

Package characteristics

Description

Conditions

Min

Typ

Max Units

Operating ambient

temperature

(CY8C4248BZS - L489)

–40

25

105

°C

Operating ambient

temperature

(CY8C4248BZA-L489)

–40

25

–

85

T_J

Operating junction

temperature

125

T_JA

T_JC

–

85

6

–

°C/Watt

Package θ_JA(124-ball VFBGA)

Package θ_JC(124-ball VFBGA)

Table 53

Solder reflow peak temperature

Maximum peak temperature

Package

124-ball VFBGA

Maximum time at peak temperature

260°C

30 seconds

Table 54

Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2

Package

MSL

124-ball VFBGA

MSL 3

Datasheet

48 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Packaging

001-97718 *B

Figure 8

124-ball VFBGA package outline

Datasheet

49 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Acronyms

10

Acronyms

Table 55

Acronyms used in this document

Acronym

Description

abus

ADC

AG

analog local bus

analog-to-digital converter

analog global

AHB

AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data

transfer bus

ALU

arithmetic logic unit

AMUXBUS

API

analog multiplexer bus

application programming interface

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

APSR

Arm^®

ATM

BW

bandwidth

CAN

CMRR

CPU

CRC

Controller Area Network, a communications protocol

common-mode rejection ratio

central processing unit

cyclic redundancy check, an error-checking protocol

digital-to-analog converter, see also IDAC, VDAC

digital filter block

DAC

DFB

DIO

digital input/output, GPIO with only digital capabilities, no analog. See GPIO.

Dhrystone million instructions per second

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

DMIPS

DMA

DNL

DNU

DR

port write data registers

DSI

digital system interconnect

DWT

ECC

data watchpoint and trace

error correcting code

ECO

external crystal oscillator

EEPROM

EMI

electrically erasable programmable read-only memory

electromagnetic interference

external memory interface

EMIF

EOC

EOF

end of conversion

end of frame

EPSR

ESD

execution program status register

electrostatic discharge

ETM

embedded trace macrocell

Datasheet

50 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Acronyms

Table 55

Acronym

Acronyms used in this document ^(continued)

Description

FIR

finite impulse response, see also IIR

flash patch and breakpoint

full-speed

FPB

FS

GPIO

HVI

general-purpose input/output, applies to a PSoC™ pin

high-voltage interrupt, see also LVI, LVD

integrated circuit

IC

IDAC

current DAC, see also DAC, VDAC

integrated development environment

Inter-Integrated Circuit, a communications protocol

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

IDE

I²C, or IIC

IIR

ILO

IMO

INL

I/O

IPOR

IPSR

IRQ

interrupt program status register

interrupt request

ITM

LCD

LIN

instrumentation trace macrocell

liquid crystal display

Local Interconnect Network, a communications protocol.

link register

LR

LUT

LVD

LVI

lookup table

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

LVTTL

MAC

MCU

MISO

NC

microcontroller unit

master-in slave-out

no connect

NMI

NRZ

NVIC

NVL

opamp

PAL

PC

nonmaskable interrupt

non-return-to-zero

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

programmable array logic, see also PLD

program counter

PCB

PGA

printed circuit board

programmable gain amplifier

Datasheet

51 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Acronyms

Table 55

Acronym

Acronyms used in this document ^(continued)

Description

PHUB

PHY

PICU

PLA

peripheral hub

physical layer

port interrupt control unit

programmable logic array

programmable logic device, see also PAL

phase-locked loop

PLD

PLL

PMDD

POR

PRES

PRS

PS

package material declaration data sheet

power-on reset

precise power-on reset

pseudo random sequence

port read data register

PSoC™

PSRR

PWM

RAM

RISC

RMS

RTC

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

real-time clock

RTL

register transfer language

remote transmission request

receive

RTR

RX

SAR

successive approximation register

switched capacitor/continuous time

I²C serial clock

SC/CT

SCL

SDA

S/H

I²C serial data

sample and hold

SINAD

SIO

signal to noise and distortion ratio

special input/output, GPIO with advanced features. See GPIO.

start of conversion

SOC

SOF

SPI

start of frame

Serial Peripheral Interface, a communications protocol

slew rate

SR

SRAM

SRES

SWD

SWV

TD

static random access memory

software reset

serial wire debug, a test protocol

single-wire viewer

transaction descriptor, see also DMA

total harmonic distortion

THD

Datasheet

52 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Acronyms

Table 55

Acronym

Acronyms used in this document ^(continued)

Description

TIA

transimpedance amplifier

technical reference manual

transistor-transistor logic

TRM

TTL

TX

transmit

UART

UDB

USB

USBIO

VDAC

WDT

WOL

WRES

XRES

XTAL

Universal Asynchronous Transmitter Receiver, a communications protocol

universal digital block

Universal Serial Bus

USB input/output, PSoC™ pins used to connect to a USB port

voltage DAC, see also DAC, IDAC

watchdog timer

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

Datasheet

53 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Document conventions

11

Document conventions

11.1

Units of measure

Table 56

Units of measure

Symbol

Unit of measure

°C

degrees Celsius

decibel

dB

fF

femto farad

hertz

Hz

KB

1024 bytes

kbps

Khr

kHz

kΩ

ksps

LSB

Mbps

MHz

MΩ

Msps

µA

kilobits per second

kilohour

kilohertz

kilo ohm

kilosamples per second

least significant bit

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

µF

µH

µs

microhenry

microsecond

microvolt

µV

µW

mA

ms

mV

nA

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

nanovolt

ns

nV

Ω

ohm

pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

sqrtHz

V

samples per second

square root of hertz

volt

Datasheet

54 of 56

002-35633 Rev. **

2022-06-16

PSoC™ 4 MCU: PSoC™ 4200L Automotive

Based on Arm® Cortex®-M0

Revision history

Document

Date of release

version

Description of changes

**

2022-06-16

New datasheet.

Datasheet

55 of 56

002-35633 Rev. **

2022-06-16

Please read the Important Notice and Warnings at the end of this document

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

For further information on the product, technology,

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”).

Edition 2022-06-16

Published by

delivery terms and conditions and prices please

contact your nearest Infineon Technologies office

(www.infineon.com).

Infineon Technologies AG

81726 Munich, Germany

With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement of

intellectual property rights of any third party.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Do you have a question about this

document?

Go to www.infineon.com/support

authorized

representatives

of

Infineon

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of the

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

Document reference

002-35633 Rev. **

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.


型号：	CY8C4248BZS-L489
厂家：	Infineon
描述：	Automotive PSoC™ 4200L
文件：	总56页 (文件大小：770K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C4248BZS-L489 [INFINEON]

相关型号：

CY8C4248FLI-BL483

CY8C4248FLI-BL583

CY8C4248FLI-BL583T

CY8C4248FNI-BL453

CY8C4248FNI-BL463

CY8C4248FNI-BL473

CY8C4248FNI-BL483

CY8C4248FNI-BL493

CY8C4248FNI-BL543

CY8C4248FNI-BL543T

CY8C4248FNI-BL553

CY8C4248FNI-BL553T