CY8C4127AXI-S445 [INFINEON]
32位PSoC™ 4 Arm® Cortex®-M0/M0+;型号: | CY8C4127AXI-S445 |
厂家: | Infineon |
描述: | 32位PSoC™ 4 Arm® Cortex®-M0/M0+ |
文件: | 总54页 (文件大小:852K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY8C41xx
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital
blocks with flexible automatic routing. PSoC™ 4100S Plus is a member of the PSoC™ 4 platform architecture. It is
a combination of a microcontroller with standard communication and timing peripherals, a capacitive
touch-sensing system (CAPSENSE™) with best-in-class performance, programmable general-purpose
continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC™ 4100S Plus
products are upward compatible with members of the PSoC™ 4 platform for new applications and design needs.
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply
- Up to 128 KB of flash with read accelerator
- Up to 16 KB of SRAM
- 8-channel DMA engine
• Programmable analog
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and comparator
modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.
- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and Channel Sequencer with signal averag-
ing
- Single-slope 10-bit ADC function provided by a capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital
- Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs
• Low-power 1.71-V to 5.5-V operation
- Deep Sleep mode with operational analog and 2.5-µA digital system current
• Capacitive sensing
- Capacitive sigma-delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense)
• LCD drive capability
- LCD segment drive capability on GPIOs
• Serial communication
- Five independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
• Timing and pulse-width modulation
- Eight 16-bit Timer, Counter, Pulse-Width Modulator (TCPWM) blocks
- Center-aligned, edge, and pseudo-random modes
- Comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications
- Quadrature decoder
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
002-19966 Rev. *K
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Features
• Clock sources
- 4 to 33 MHz External Crystal Oscillator (ECO)
- PLL to generate 48-MHz frequency
- 32-kHz Watch Crystal Oscillator (WCO)
- ±2% Internal Main Oscillator (IMO)
- 32-kHz Internal Low-power Oscillator (ILO)
• True random number generator (TRNG)
- TRNG generates truly random number for secure key generation for Cryptography applications
• CAN block
- CAN 2.0B block with support for Time-Triggered CAN (TTCAN)
• Up to 54 programmable GPIO pins
- 44-pin TQFP (0.8-mm pitch), 48-pin TQFP (0.5-mm pitch), and 64-pin TQFP normal (0.8 mm) and fine pitch
(0.5 mm) packages
- Any GPIO pin can be CAPSENSE™, analog, or digital
- Drive modes, strengths, and slew rates are programmable
• ModusToolbox™ software
- Comprehensive collection of multi-platform tools and software libraries
- Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CAPSENSE™
• PSoC™ Creator design environment
- Integrated development environment (IDE) provides schematic design entry and build, with analog and digital
automatic routing
- Application programming interface (API) Components for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents...............................................................................................................................3
1 Development ecosystem .................................................................................................................4
1.1 PSoC™ 4 MCU resources .........................................................................................................................................4
1.2 ModusToolbox™ software ......................................................................................................................................5
1.3 PSoC™ Creator ........................................................................................................................................................6
Block diagram...................................................................................................................................7
2 Functional definition.......................................................................................................................8
2.1 CPU and memory subsystem .................................................................................................................................8
2.2 System resources....................................................................................................................................................8
2.3 Analog blocks ........................................................................................................................................................10
2.4 Programmable digital blocks...............................................................................................................................11
2.5 Fixed function digital blocks ................................................................................................................................11
2.6 GPIO.......................................................................................................................................................................12
2.7 Special function peripherals ................................................................................................................................12
3 Pinouts ........................................................................................................................................14
3.1 Alternate pin functions .........................................................................................................................................17
4 Power ..........................................................................................................................................20
4.1 Mode 1: 1.8 V to 5.5 V external supply..................................................................................................................20
4.2 Mode 2: 1.8 V ±5% external supply.......................................................................................................................20
5 Electrical specifications.................................................................................................................22
5.1 Absolute maximum ratings .................................................................................................................................22
5.2 Device level specifications....................................................................................................................................22
5.3 Analog peripherals................................................................................................................................................26
5.4 Digital peripherals.................................................................................................................................................35
5.5 Memory..................................................................................................................................................................37
5.6 System resources..................................................................................................................................................38
6 Ordering information ....................................................................................................................42
7 Packaging ....................................................................................................................................45
7.1 Package diagrams.................................................................................................................................................46
8 Acronyms.....................................................................................................................................49
9 Document conventions..................................................................................................................53
9.1 Units of measure ...................................................................................................................................................53
Revision history ..............................................................................................................................54
Datasheet
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1
Development ecosystem
1.1
PSoC™ 4 MCU resources
Infineon provides a wealth of data at www.Infineon.com to help you select the right PSoC™ device and quickly
and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for
PSoC™ 4 MCU:
• Overview: PSoC™ portfolio, PSoC™ roadmap
• Product selectors: PSoC™ 4 MCU
• Application notes cover a broad range of topics, from basic to advanced level, and include the following:
- AN79953: Getting started With PSoC™ 4. This application note has a convenient flow chart to help decide
which IDE to use: ModusToolbox™ software or PSoC™ Creator.
- AN91184: PSoC™ 4 Bluetooth® LE - Designing Bluetooth® LE applications
- AN88619: PSoC™ 4 hardware design considerations
- AN73854: Introduction to bootloaders
- AN89610: Arm® Cortex® code optimization
- AN86233: PSoC™ 4 MCU low-power modes and reduction techniques
- AN57821: PSoC™ 3, PSoC™ 4, and PSoC™ 5LP mixed-signal circuit board layout considerations
- AN85951: PSoC™ 4 and PSoC™ 6 CAPSENSE™ design guide
• Code examples demonstrate product features and usage, and are also available on Infineon GitHub reposi-
tories.
• Technical reference manuals (TRMs) provide detailed descriptions of PSoC™ 4 MCU architecture and registers.
• PSoC™ 4 MCU programming specification provides the information necessary to program PSoC™ 4 MCU
nonvolatile memory.
• Development tools
- ModusToolbox™ software enables cross platform code development with a robust suite of tools and software
libraries.
- PSoC™ Creator is a free Windows-based IDE. It enables concurrent hardware and firmware design of PSoC™ 3,
PSoC™ 4, PSoC™ 5LP, and PSoC™ 6 MCU based systems. Applications are created using schematic capture and
over 150 pre-verified, production-ready peripheral Components.
- CY8CKIT-149 PSoC™ 4100S Plus prototyping kit, is a low-cost and easy-to-use evaluation platform. This kit
provides easy access to all the device I/Os in a breadboard-compatible format.
- MiniProg4 and MiniProg3 all-in-one development programmers and debuggers.
- PSoC™ 4 MCU CAD libraries provide footprint and schematic support for common tools. IBIS models are also
available.
• Training videos are available on a wide range of topics including the PSoC™ 4 MCU 101 series.
• Infineon developer community enables connection with fellow PSoC™ developers around the world, 24 hours
a day, 7 days a week, and hosts a dedicated PSoC™ 4 MCU community.
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.2
ModusToolbox™ software
ModusToolbox™ software is Infineon' comprehensive collection of multi-platform tools and software libraries
that enable an immersive development experience for creating converged MCU and wireless systems. It is:
• Comprehensive - it has the resources you need
• Flexible - you can use the resources in your own workflow
• Atomic - you can get just the resources you want
Infineon provides a large collection of code repositories on GitHub, including:
• Board Support Packages (BSPs) aligned with Infineon kits
• Low-level resources, including a peripheral driver library (PDL)
• Middleware enabling industry-leading features such as CAPSENSE™
• An extensive set of thoroughly tested code example applications
ModusToolbox™ Software is IDE-neutral and easily adaptable to your workflow and preferred development
environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the
optional Eclipse IDE for ModusToolbox™, as Figure 1 shows. For information on using Infineon tools, refer to the
documentation delivered with ModusToolbox™ software, and AN79953 -Getting started with PSoC™ 4.
Figure 1
ModusToolbox™ software tools
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.3
PSoC™ Creator
PSoC™ Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems concur-
rently, based on PSoC™ 4 MCU. As Figure 2 shows, with PSoC™ Creator you can:
1. Explore the library of 200+ Components
2. Drag and drop Component icons to complete your hardware system design in the main design workspace
3. Configure Components using the Component configuration tools and the Component datasheets
4. Co-design your application firmware and hardware in the PSoC™ Creator IDE or build a project for a third-party
IDE
5. Prototype your solution with the PSoC™ 4 Pioneer kits. If a design change is needed, PSoC™ Creator and
Components enable you to make changes on-the-fly without the need for hardware revisions.
Figure 2
PSoC™ Creator schematic entry and Components
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Block diagram
Block diagram
CPU Subsystem
PSoC™ 4100S
SWD/TC, MTB
SPCIF
Plus
DataWire/
DMA
Cortex® M0+
FLASH
128 KB
SRAM
16 KB
ROM
8 KB
32-bit
48 MHz
FAST MUL
AHB- Lite
Initiator / MMIO
SRAM Controller
Read Accelerator
ROM Controller
NVIC, IRQMUX, MPU
System Resources
Lite
System Interconnect (Single Layer AHB)
Peripheral Interconnect (MMIO)
Power
Sleep Control
Peripherals
WIC
PCLK
POR
REF
PWRSYS
Clock
Clock Control
WDT
Programmable
Analog
ILO
IMO
SAR ADC
( 12-bit)
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
x1
SARMUX
CTBm
2 x Opamp
High Speed I / O Matrix & Smart I/O
Up to 54 x GPIOs
Power Modes
Active/Sleep
DeepSleep
I/O Subsystem
PSoC™ 4100S Plus devices include extensive support for programming, testing, debugging, and tracing both
hardware and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4100S Plus
devices. The SWD interface is fully compatible with industry-standard third-party tools. PSoC™ 4100S Plus
provides a level of security not possible with multi-chip application solutions or with microcontrollers. It has the
following advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4100S Plus, with device security enabled, may not be
returned for failure analysis. This is a trade-off the PSoC™ 4100S Plus allows the customer to make.
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Functional definition
2
Functional definition
CPU and memory subsystem
CPU
2.1
2.1.1
The Cortex®-M0+ CPU in the PSoC™ 4100S Plus is part of the 32-bit MCU subsystem, which is optimized for
low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a
subset of the Thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight
interrupt inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake the processor from
Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.
The CPU subsystem includes an 8-channel DMA engine and also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug configuration used for PSoC™ 4100S Plus has four
breakpoint (address) comparators and two watchpoint (data) comparators.
2.1.2
Flash
The PSoC™ 4100S Plus device has a flash module with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS)
access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.
2.1.3
SRAM
16 KB of SRAM are provided with zero wait-state access at 48 MHz.
2.1.4
SROM
An 8-KB supervisory ROM that contains boot and configuration routines is provided.
2.2
2.2.1
System resources
Power system
The power system is described in detail in the section Power. It provides assurance that voltage levels are as
required for each respective mode and either delays mode entry (for example, on power-on reset (POR)) until
voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detection).
PSoC™ 4100S Plus operates with a single external supply over the range of either 1.8 V ±5% (externally regulated)
or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which are
managed by the power system. PSoC™ 4100S Plus provides Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in
Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In
Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes
35 µs. The opamps can remain operational in Deep Sleep mode.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.2.2
Clock system
The PSoC™ 4100S Plus clock system is responsible for providing clocks to all subsystems that require clocks and
for switching between different clock sources without glitching. In addition, the clock system ensures that there
are no metastable conditions.
The clock system for the PSoC™ 4100S Plus consists of the IMO, ILO, a 32-kHz Watch Crystal Oscillator (WCO), MHz
ECO and PLL, and provision for an external clock. The WCO block allows locking the IMO to the 32-kHz oscillator.
External Clock
HFCLK
IMO
ECO
Divide By
2,4,8
PLL
WDC0
16-bits
WCO
ILO
LFCLK
WDC1
16-bits
WDC2
32-bits
Watchdog Counters (WDC)
WDT
Watchdog Timer (WDT)
Prescaler
SYSCLK
HFCLK
Integer
Dividers
12X 16-bit
Fractional
Dividers
5X 16.5-bit, 1X 24.5 bit
Figure 3
PSoC™ 4100S Plus MCU clocking architecture
The HFCLK signal can be divided down as shown to generate synchronous clocks for the analog and digital
peripherals. There are 18 clock dividers for the PSoC™ 4100S Plus (six with fractional divide capability, twelve with
integer divide only). The twelve 16-bit integer divide capability allows a lot of flexibility in generating fine-grained
frequency. In addition, there are five 16-bit fractional dividers and one 24-bit fractional divider.
2.2.3
IMO clock source
The IMO is the primary source of internal clocking in the PSoC™ 4100S Plus. It is trimmed during testing to achieve
the specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of
4 MHz. The IMO tolerance with Infineon-provided calibration settings is ±2% over the entire voltage and
temperature range.
2.2.4
ILO clock source
The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the
watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to
the IMO to improve accuracy. Infineon provides a software component, which does the calibration.
2.2.5
Watch Crystal Oscillator (WCO)
The PSoC™ 4100S Plus clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that
can be used for precision timing applications.
2.2.6
External Crystal Oscillators (ECO)
The PSoC™ 4100S Plus also implements a 4 to 33 MHz crystal oscillator.
2.2.7
Watchdog timer and counters
A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during
Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is
recorded in a Reset Cause register, which is firmware readable. The watchdog counters can be used to implement
a Real-Time clock using the 32-kHz WCO.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.2.8
Reset
PSoC™ 4100S Plus can be reset from a variety of sources including a software reset. Reset events are
asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky
through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset
by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled.
2.3
Analog blocks
12-bit SAR ADC
2.3.1
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks
at that frequency to do a 12-bit conversion.
The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the
amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to
provide an external bypass (through a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected
channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth
is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching
is effected through a state machine or through firmware driven switching. A feature provided by the sequencer
is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying
source impedance and frequency, it is possible to have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers (low and high range values) is implemented with
a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast
detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed
and the CPU to read the values and check for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating
range is 1.71 V to 5.5 V.
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
External
Reference and
Bypass
Reference
Selection
(optional )
VDDA
VREF
VDDA /2
Inputs from other Ports
Figure 4
SAR ADC
2.3.2
Two opamps (Continuous-time block; CTB)
PSoC™ 4100S Plus has two opamps with Comparator modes which allow most common analog functions to be
performed on-chip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers,
and other functions can be realized, in some cases with external passives. saving power, cost, and space. The
on-chip opamps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without
requiring external buffering.
2.3.3
Low-power comparators (LPC)
PSoC™ 4100S Plus has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows
the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during
low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating
in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.
The LPC outputs can be routed to pins.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.3.4
Current DACs
PSoC™ 4100S Plus has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable
current ranges.
2.3.5
Analog multiplexed buses
PSoC™ 4100S Plus has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal
resources (IDACs, comparator) to connect to any pin on the I/O ports.
2.4
Programmable digital blocks
Smart I/O block
2.4.1
The Smart I/O block is a fabric of switches and LUTs that allows Boolean functions to be performed in signals
being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip
and on signals going out as outputs.
2.5
Fixed function digital blocks
2.5.1
Timer, Counter, Pulse-Width Modulator (TCPWM) block
The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register
to record the count value at the time of an event (which may be an I/O event), a period register that is used to
either stop or auto-reload the counter when its count is equal to the period register, and compare registers to
generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and
complementary outputs with programmable offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this
is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be
shut off immediately with no time for software intervention. Each block also incorporates a Quadrature decoder.
There are eight TCPWM blocks in PSoC™ 4100S Plus.
2.5.2
Serial Communication Block (SCB)
PSoC™ 4100S Plus has five serial communication blocks, which can be programmed to have SPI, I2C, or UART
functionality.
I2C mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of
multi-master arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has
flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that
creates a mailbox address range in the memory of PSoC™ 4100S Plus and effectively reduces I2C communication
to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and Fast-mode devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain
modes.
PSoC™ 4100S Plus is not completely compliant with the I2C spec in the following respect:
GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of
the rest of the I2C system.
UART mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
SPI mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.5.3
CAN
There is a CAN 2.0B block with support for TT-CAN.
2.6
GPIO
PSoC™ 4100S Plus has up to 54 GPIOs. The GPIO block implements the following:
• Eight drive modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width (less for Ports 5 and 6). During
power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request
(IRQ) and interrupt service routine (ISR) vector associated with it.
2.7
2.7.1
Special function peripherals
CAPSENSE™
CAPSENSE™ is supported in the PSoC™ 4100S Plus through a capacitive sigma-delta (CSD) block that can be
connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be
provided on any available pin or group of pins in a system under software control. A PSoC™ Creator component
is provided for the CAPSENSE™ block to make it easy for the user.
Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water
tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capac-
itance from attenuating the sensed input. Proximity sensing can also be implemented.
The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).
The CAPSENSE™ block also provides a 10-bit Slope ADC function which can be used in conjunction with the
CAPSENSE™ function. The CAPSENSE™ block is an advanced, low-noise, programmable block with program-
mable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and ground to null out
power-supply related noise.
2.7.2
LCD segment drive
PSoC™ 4100S Plus has an LCD controller, which can drive up to 8 commons and up to 30 segments. It uses full
digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods
used are referred to as Digital Correlation and PWM. Digital Correlation pertains to modulating the frequency and
drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it
up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast
with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance
of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This
method results in higher power consumption but can result in better results when driving TN displays.
Datasheet
12
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Pinouts
3
Pinouts
The following table provides the pin list for PSoC™ 4100S Plus for the 44-pin TQFP, 48-pin TQFP, and 64-pin TQFP
normal and fine pitch packages.
Table 1
Pinout
64-TQFP
44-TQFP
48-TQFP
Name
Pin
39
40
41
42
43
44
45
46
47
48
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
Pin
24
25
26
27
28
29
30
31
32
33
34
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
VDDD
Pin
28
29
30
31
32
33
34
35
36
37
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
VSSD
VDDD
P5.0
P5.1
P5.2
P5.3
P5.5
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
38
39
VSSD
VDDD
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VSSD
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
40
41
42
43
44
45
46
47
48
1
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
2
3
4
5
6
7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
2
3
4
5
6
7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
Datasheet
13
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Pinouts
Table 1
Pinout (continued)
64-TQFP
44-TQFP
48-TQFP
Name
Pin
8
9
Name
P2.6
P2.7
VSSD
NC
P6.0
P6.1
P6.2
P6.4
P6.5
VSSD
Pin
8
9
Name
P2.6
P2.7
Pin
8
9
P2.6
P2.7
10
11
12
13
14
15
16
17
10
P6.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSSD
NC
P3.0
P3.1
P3.2
NC
P3.3
P3.4
P3.5
P3.6
P3.7
VDDD
P4.0
P4.1
P4.2
P4.3
18
19
20
P3.0
P3.1
P3.2
11
12
13
P3.0
P3.1
P3.2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
P3.3
P3.4
P3.5
P3.6
P3.7
VDDD
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.6
P5.7
P7.0
P7.1
14
15
16
17
18
19
20
21
22
23
P3.3
P3.4
P3.5
P3.6
P3.7
VDDD
P4.0
P4.1
P4.2
P4.3
26
27
P7.0
P7.1
Datasheet
14
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Pinouts
Descriptions of the power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
GPIOs by package:
64 TQFP
44 TQFP
37
48 TQFP
Number
54
38
Datasheet
15
002-19966 Rev. *K
2023-01-24
3.1
Alternate pin functions
Each Port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a
CAPSENSE™ pin. The pin assignments are shown in the following table.
Table 2
Port/pin
P0.0
Alternate pin functions
Analog
Smart I/O
ACT #0
ACT #1
ACT #3
DS #2
scb[2].i2c_scl:0
scb[2].i2c_sda:0
DS #3
lpcomp.in_p[0]
lpcomp.in_n[0]
lpcomp.in_p[1]
lpcomp.in_n[1]
wco.wco_in
tcpwm.tr_in[0] scb[2].uart_cts:0
tcpwm.tr_in[1] scb[2].uart_rts:0
scb[0].spi_select1:0
scb[0].spi_select2:0
scb[0].spi_select3:0
scb[2].spi_select0:1
scb[1].spi_mosi:1
scb[1].spi_miso:1
scb[1].spi_clk:1
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
scb[1].uart_rx:0 scb[2].uart_rx:0
scb[1].uart_tx:0 scb[2].uart_tx:0
scb[1].uart_cts: scb[2].uart_tx:1
0
scb[1].i2c_scl:0
scb[1].i2c_sda:0
wco.wco_out
exco.eco_in
srss.ext_clk:0
P0.7
exco.eco_out
tcpwm.line[0]:3 scb[1].uart_rts:
0
scb[1].spi_select0:1
P5.0
P5.1
tcpwm.line[4]:2
tcpwm.line_-
compl[4]:2
scb[2].uart_rx:1
scb[2].uart_tx:2
scb[2].i2c_scl:1
scb[2].i2c_sda:1
scb[2].spi_mosi:0
scb[2].spi_miso:0
P5.2
P5.3
tcpwm.line[5]:2
tcpwm.line_-
compl[5]:2
scb[2].uart_cts:1 lpcomp.comp[0]:2
scb[2].uart_rts:1 lpcomp.comp[1]:0 scb[2].spi_select0:0
scb[2].spi_clk:0
P5.4
P5.5
tcpwm.line[6]:2
tcpwm.line_-
compl[6]:2
scb[2].spi_select1:0
scb[2].spi_select2:0
P1.0
P1.1
ctb0_oa0+
ctb0_oa0-
SmartIo[2].io[0] tcpwm.line[2]:1 scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].i2c_sda:0
scb[0].spi_mosi:1
scb[0].spi_miso:1
SmartIo[2].io[1]
tcpwm.line_-
compl[2]:1
scb[0].uart_tx:1
P1.2
P1.3
P1.4
ctb0_oa0_out
ctb0_oa1_out
ctb0_oa1-
SmartIo[2].io[2] tcpwm.line[3]:1 scb[0].uart_cts:
1
tcpwm.tr_in[2]
tcpwm.tr_in[3]
scb[2].i2c_scl:2
scb[2].i2c_sda:2
scb[3].i2c_scl:0
scb[0].spi_clk:1
scb[0].spi_select0:1
scb[0].spi_select1:1
SmartIo[2].io[3]
tcpwm.line_-
compl[3]:1
scb[0].uart_rts:
1
SmartIo[2].io[4] tcpwm.line[6]:1
Table 2
Port/pin
P1.5
Alternate pin functions (continued)
Analog
Smart I/O
ACT #0
tcpwm.line_-
compl[6]:1
ACT #1
ACT #3
DS #2
scb[3].i2c_sda:0
DS #3
scb[0].spi_select2:1
ctb0_oa1+
SmartIo[2].io[5]
P1.6
P1.7
ctb0_oa0+
SmartIo[2].io[6] tcpwm.line[7]:1
scb[0].spi_select3:1
scb[2].spi_clk:1
ctb0_oa1+
sar_ext_vref0
sar_ext_vref1
SmartIo[2].io[7]
tcpwm.line_-
compl[7]:1
P2.0
P2.1
sarmux[0]
sarmux[1]
SmartIo[0].io[0] tcpwm.line[4]:0
csd.comp
tcpwm.tr_in[4]
tcpwm.tr_in[5]
scb[1].i2c_scl:1
scb[1].i2c_sda:1
scb[1].spi_mosi:2
scb[1].spi_miso:2
SmartIo[0].io[1]
tcpwm.line_-
compl[4]:0
P2.2
P2.3
sarmux[2]
sarmux[3]
SmartIo[0].io[2] tcpwm.line[5]:1
scb[1].spi_clk:2
scb[1].spi_select0:2
SmartIo[0].io[3]
tcpwm.line_-
compl[5]:1
P2.4
P2.5
sarmux[4]
sarmux[5]
SmartIo[0].io[4] tcpwm.line[0]:1 scb[3].uart_rx:1
scb[1].spi_select1:1
scb[1].spi_select2:1
SmartIo[0].io[5]
tcpwm.line_-
compl[0]:1
scb[3].uart_tx:1
P2.6
P2.7
P6.0
P6.1
P6.2
P6.3
sarmux[6]
sarmux[7]
SmartIo[0].io[6] tcpwm.line[1]:1 scb[3].uart_cts:
1
scb[1].spi_select3:1
scb[2].spi_mosi:1
scb[3].spi_mosi:0
scb[3].spi_miso:0
scb[3].spi_clk:0
SmartIo[0].io[7]
tcpwm.line_-
compl[1]:1
scb[3].uart_rts:
1
lpcomp.comp[0]:0
scb[3].i2c_scl:1
scb[3].i2c_sda:1
tcpwm.line[4]:1 scb[3].uart_rx:0
can.can_tx-
_enb_n:0
can.can_rx:0
tcpwm.line_-
compl[4]:1
scb[3].uart_tx:0
tcpwm.line[5]:0 scb[3].uart_cts:
0
can.can_tx:0
tcpwm.line_-
compl[5]:0
scb[3].uart_rts:
0
scb[3].spi_select0:0
P6.4
P6.5
tcpwm.line[6]:0
tcpwm.line_-
compl[6]:0
scb[4].i2c_scl
scb[4].i2c_sda
scb[3].spi_select1:0
scb[3].spi_select2:0
P3.0
SmartIo[1].io[0] tcpwm.line[0]:0 scb[1].uart_rx:1
scb[1].i2c_scl:2
scb[1].spi_mosi:0
Table 2
Port/pin
P3.1
Alternate pin functions (continued)
Analog
Smart I/O
ACT #0
tcpwm.line_-
compl[0]:0
ACT #1
scb[1].uart_tx:1
ACT #3
DS #2
scb[1].i2c_sda:2
DS #3
scb[1].spi_miso:0
SmartIo[1].io[1]
P3.2
P3.3
SmartIo[1].io[2] tcpwm.line[1]:0 scb[1].uart_cts:
1
cpuss.swd_data
cpuss.swd_clk
scb[1].spi_clk:0
SmartIo[1].io[3]
tcpwm.line_-
compl[1]:0
scb[1].uart_rts:
1
scb[1].spi_select0:0
P3.4
P3.5
SmartIo[1].io[4] tcpwm.line[2]:0
tcpwm.tr_in[6]
scb[1].spi_select1:0
scb[1].spi_select2:0
SmartIo[1].io[5]
tcpwm.line_-
compl[2]:0
P3.6
P3.7
SmartIo[1].io[6] tcpwm.line[3]:0
scb[4].spi_select3 scb[1].spi_select3:0
SmartIo[1].io[7]
tcpwm.line_-
compl[3]:0
lpcomp.comp[1]:1
scb[2].spi_miso:1
P4.0
P4.1
P4.2
csd.vref_ext
csd.cshield
csd.cmod
scb[0].uart_rx:0
scb[0].uart_tx:0
scb[0].uart_cts:
0
can.can_rx:1
can.can_tx:1
can.can_tx-
_enb_n:1
scb[0].i2c_scl:1
scb[0].i2c_sda:1
lpcomp.comp[0]:1
scb[0].spi_mosi:0
scb[0].spi_miso:0
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:
0
lpcomp.comp[1]:2 scb[0].spi_select0:0
P4.4
P4.5
P4.6
P4.7
P5.6
P5.7
scb[4].uart_rx
scb[4].uart_tx
scb[4].uart_cts
scb[4].uart_rts
scb[4].spi_mosi
scb[4].spi_miso
scb[4].spi_clk
scb[4].spi_select0
scb[4].spi_select1 scb[2].spi_select3:0
scb[4].spi_select2
scb[0].spi_select1:2
scb[0].spi_select2:2
scb[0].spi_select3:2
tcpwm.line[7]:0
tcpwm.line_-
compl[7]:0
P7.0
P7.1
tcpwm.line[0]:2 scb[3].uart_rx:2
scb[3].i2c_scl:2
scb[3].i2c_sda:2
scb[3].spi_mosi:1
scb[3].spi_miso:1
tcpwm.line_-
compl[0]:2
scb[3].uart_tx:2
P7.2
tcpwm.line[1]:2 scb[3].uart_cts:
2
scb[3].spi_clk:1
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Power
4
Power
The following power system diagram shows the set of power supply pins as implemented for the
PSoC™ 4100S Plus. The system has one regulator in Active mode for the digital circuitry. There is no analog
regulator; the analog circuits run directly from the VDD input.
VDDA
VDDD
VDDA
VSSA
VDDD
VSSD
Analog
Domain
Digital
Domain
VCCD
1.8 Volt
Regulator
Figure 5
Power supply connections
There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated
externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5% (externally regulated; 1.71 to
1.89, internal regulator bypassed).
4.1
Mode 1: 1.8 V to 5.5 V external supply
In this mode, PSoC™ 4100S Plus is powered by an external power supply that can be anywhere in the range of 1.8
to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from
a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of PSoC™ 4100S
Plus supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be bypassed to
ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else.
4.2
Mode 2: 1.8 V ±5% external supply
In this mode, PSoC™ 4100S Plus is powered by an external power supply that must be within the range of 1.71 to
1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins
are shorted together and bypassed. The internal regulator can be disabled in the firmware.
Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is
to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass
capacitor parasitic should be simulated to design and obtain optimal bypassing.
An example of a bypass scheme is shown in the following diagram.
Datasheet
19
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Power
Power supply bypass connections example
1.8 V to 5.5 V
0.1 µF
1.8 V to 5.5 V
0.1 µF
VDDA
VDDD
1 µF
1 µF
VCCD
PSoC™ 4100S Plus
0.1 µF
VSS
Figure 6
External supply range from 1.8 V to 5.5 V with internal regulator active
Datasheet
20
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5
Electrical specifications
5.1
Table 3
Absolute maximum ratings
Absolute maximum ratings[1]
Spec ID# Parameter
Description
Min Typ Max Units Details/conditions
SID1
VDDD_ABS
VCCD_ABS
VGPIO_ABS
IGPIO_ABS
Digital supply relative to VSS
Direct digital core voltage input
relative to VSS
GPIO voltage
Maximum current per GPIO
–0.5
–
6
–
SID2
–0.5
–
1.95
V
–
SID3
SID4
–0.5
–25
–
–
VDD+0.5
25
–
–
mA
GPIO injection current, Max for VIH
> VDDD, and Min for VIL < VSS
Electrostatic discharge human
body model
Electrostatic discharge charged
device model
Pin current for latch-up
Current injected per
pin
SID5
IGPIO_injection
ESD_HBM
–0.5
–
–
0.5
–
BID44
2200
–
V
BID45
BID46
ESD_CDM
LU
500
–
–
–
–
–
–140
140
mA
5.2
Device level specifications
All specifications are valid for –40°C TA 105°C and TJ 125°C, except where noted. Specifications are valid for
1.71 V to 5.5 V, except where noted.
Table 4
DC specifications
Typical values measured at VDD = 3.3 V and 25°C.
Spec ID# Parameter
SID53 VDD
Description
Min Typ Max Units Details/conditions
Internally regulated
supply
Power supply input voltage
Power supply input voltage (VCCD
1.8
–
5.5
V
Internally
unregulated supply
SID255 VDD
1.71
–
1.89
= VDDD = VDDA
)
SID54
SID55
VCCD
CEFC
Output voltage (for core logic)
External regulator voltage (VCCD
bypass
–
–
1.8
0.1
–
–
–
)
X5R ceramic or
better
X5R ceramic or
better
µF
SID56
CEXC
Power supply bypass capacitor
–
1
–
Active mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25°C.
SID10
SID16
SID19
IDD5
IDD8
IDD11
Execute from flash; CPU at 6 MHz
Execute from flash; CPU at 24 MHz
Execute from flash; CPU at 48 MHz
–
–
–
1.8
3.0
5.4
2.4
4.6
7.1
mA
Note
1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in
compliance with JEDEC Standard JESD22-A103, high temperature storage life. When used below Absolute Maximum conditions but
above normal operating conditions, the device may not operate to specification.
Datasheet
21
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 4
DC specifications (continued)
Typical values measured at VDD = 3.3 V and 25°C.
Spec ID# Parameter Description
Min Typ Max Units Details/conditions
Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
IDD17
I2C wakeup WDT, and
Comparators on
I2C wakeup, WDT, and
Comparators on
–
–
1.1
1.5
1.8
2.1
mA 6 MHZ
12 MHZ
SID25
IDD20
Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and
Comparators on
I2C wakeup, WDT, and
Comparators on
–
–
1.1
1.5
1.8
2.1
mA 6 MHZ
mA 12 MHZ
SID28A IDD23A
Deep Sleep mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID30
IDD25
I2C wakeup and WDT on; T = –40°C
to 60°C
I2C wakeup and WDT on
–
–
2.5
2.5
40
µA T = –40°C to 60°C
SID31
IDD26
125
µA Max is at 3.6 V and
85°C
Deep Sleep mode, VDD = 3.6 V to 5.5 V (Regulator on)
I2C wakeup and WDT on; T = –40°C
2.5
2.5
40
SID33
SID34
IDD28
IDD29
–
–
µA T = –40°C to 60°C
to 60°C
Max is at 5.5 V and
I2C wakeup and WDT on
125
µA
85°C
Deep Sleep mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
I2C wakeup and WDT on; T = –40°C
to 60°C
2.5
60
SID36
SID37
IDD31
IDD32
–
–
µA T = –40°C to 60°C
Max is at 1.89 V and
I2C wakeup and WDT on
2.5
180
µA
85°C
XRES current
Supply current while XRES
asserted
SID307 IDD_XR
–
2
5
mA
–
Table 5
AC specifications
Spec ID# Parameter
Description
CPU frequency
Wakeup from Sleep mode
Wakeup from Deep Sleep mode
Min Typ Max Units Details/conditions
SID48
FCPU
DC
–
–
0
48
–
MHz 1.71 VDD 5.5
SID49[2] TSLEEP
µs
SID50[2] TDEEPSLEEP
–
35
–
Note
2. Guaranteed by characterization.
Datasheet
22
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.2.1
GPIO
Table 6
GPIO DC Specifications
Spec ID# Parameter
Description
Input voltage high threshold 0.7 VDDD
Min
Typ
–
Max
–
0.3
VDDD
Units Details/conditions
[3]
SID57
VIH
VIL
VIH
VIL
CMOS Input
SID58
Input voltage low threshold
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD < 2.7 V
–
0.7 VDDD
–
–
–
–
CMOS Input
[3]
[3]
SID241
SID242
–
–
–
0.3
VDDD
–
0.8
SID243
SID244
VIH
VIL
LVTTL input, VDDD 2.7 V
LVTTL input, VDDD 2.7 V
2.0
–
–
–
–
–
V
IOH = 4 mA at 3 V
SID59
SID60
SID61
SID62
VOH
VOH
VOL
VOL
Output voltage high level
Output voltage high level
Output voltage low level
Output voltage low level
VDDD –0.6
–
–
–
–
–
VDDD
IOH = 1 mA at 1.8 V
VDDD
IOL = 4 mA at 1.8 V
VDDD
VDDD –0.5
–
–
–
0.6
0.6
I
OL = 10 mA at 3 V
VDDD
SID62A
SID63
SID64
VOL
RPULLUP
Output voltage low level
Pull-up resistor
–
3.5
3.5
–
5.6
5.6
0.4
8.5
8.5
IOL = 3 mA at 3 V VDDD
–
–
kΩ
RPULLDOWN Pull-down resistor
Input leakage current
SID65
SID66
IIL
–
–
2
nA 25°C, VDDD = 3.0 V
(absolute value)
CIN
Input capacitance
Input hysteresis LVTTL
–
25
–
40
7
–
pF
–
SID67[4] VHYSTTL
VDDD 2.7 V
0.05 ×
VDDD
200
SID68[4] VHYSCMOS
Input hysteresis CMOS
–
–
–
–
–
mV VDD < 4.5 V
VDD > 4.5 V
SID68A[4] VHYSCMOS5V5 Input hysteresis CMOS
Current through protection
SID69[4] IDIODE
–
100
µA
–
–
diode to VDD/VSS
Maximum total source or
SID69A[4] ITOT_GPIO
–
–
200
mA
sink chip current
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Datasheet
23
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 7
GPIO AC specifications
(Guaranteed by characterization)
Spec ID# Parameter
Description
Min
Typ Max Units Details/Conditions
3.3 V VDDD
,
SID70
SID71
SID72
SID73
SID74
SID75
SID76
SID245
TRISEF
Rise time in fast strong mode
Fall time in fast strong mode
Rise time in slow strong mode
Fall time in slow strong mode
2
–
–
–
–
–
–
–
–
12
12
Cload = 25 pF
ns
3.3 V VDDD
Cload = 25 pF
3.3 V VDDD
Cload = 25 pF
3.3 V VDDD
Cload = 25 pF
90/10%, 25 pF load,
60/40 duty cycle
90/10%, 25 pF load,
60/40 duty cycle
,
TFALLF
2
10
10
–
,
TRISES
60
–
–
,
TFALLS
60
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
FGPIOUT1
FGPIOUT2
FGPIOUT3
FGPIOUT4
33
–
16.7
7
90/10%, 25 pF load,
–
MHz 60/40 duty cycle
90/10%, 25 pF load,
60/40 duty cycle
–
3.5
GPIO input operating
frequency;
1.71 V VDDD 5.5 V
SID246
FGPIOIN
–
–
48
90/10% VIO
5.2.2
XRES
Table 8
XRES DC specifications
Spec ID# Parameter
Description
Min Typ Max Units
Details/conditions
0.7 ×
SID77
SID78
VIH
VIL
Input voltage high threshold
Input voltage low threshold
–
–
–
VDDD
V
CMOS Input
0.3
VDDD
–
SID79
SID80
RPULLUP
CIN
Pull-up resistor
Input capacitance
–
–
60
–
–
7
kΩ
pF
–
–
Typical hysteresis is
200 mV for VDD > 4.5 V
SID81[5] VHYSXRES
Input voltage hysteresis
–
–
100
–
–
mV
µA
Current through protection
diode to VDD/VSS
SID82
IDIODE
100
Table 9
XRES AC specifications
Description
SID83[5] TRESETWIDTH Reset pulse width
Spec ID# Parameter
Min Typ Max Units
Details/conditions
1
–
–
–
–
µs
–
–
Wake-up time from reset
release
BID194[5] TRESETWAKE
2.7
ms
Note
5. Guaranteed by characterization.
Datasheet
24
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3
Analog peripherals
5.3.1
CTBm opamp
Table 10
CTBm opamp specifications
Spec ID# Parameter
Description
Min Typ Max Units Details/conditions
IDD
Opamp block current,
External load
SID269
SID270
SID271
IDD_HI
IDD_MED
IDD_LOW
GBW
power = hi
power = med
power = lo
Load = 20 pF, 0.1 mA
VDDA = 2.7 V
–
–
–
1100 1850
550 950
150 350
µA
–
–
–
SID272
SID273
SID274
GBW_HI
power = hi
power = med
power = lo
6
3
–
–
–
1
–
–
–
MHz Input and output are
0.2 V to VDDA-0.2 V
GBW_MED
GBW_LO
Input and output are
0.2 V to VDDA-0.2 V
Input and output are
0.2 V to VDDA-0.2 V
IOUT_MAX
IOUT_MAX_HI
VDDA = 2.7 V, 500 mV from rail
power = hi
SID275
SID276
SID277
10
10
–
–
–
5
–
–
–
mA Output is 0.5 V to
VDDA -0.5 V
IOUT_MAX_MID power = med
IOUT_MAX_LO power = lo
Output is 0.5 V to
VDDA -0.5 V
Output is 0.5 V to
VDDA -0.5 V
IOUT
IOUT_MAX_HI
VDDA = 1.71 V, 500 mV from rail
power = hi
SID278
SID279
SID280
4
4
–
–
–
2
–
–
–
mA Output is 0.5 V to
VDDA -0.5 V
IOUT_MAX_MID power = med
IOUT_MAX_LO power = lo
Output is 0.5 V to
VDDA-0.5 V
Output is 0.5 V to
VDDA-0.5 V
IDD_Int
Opamp block current Internal
Load
SID269_I IDD_HI_Int
SID270_I IDD_MED_Int
SID271_I IDD_LOW_Int
GBW
power = hi
power = med
power = lo
VDDA = 2.7 V
power = hi
–
–
–
–
8
1500 1700
700 900
µA
–
–
–
–
–
–
–
–
–
–
SID272_I GBW_HI_Int
MHz Output is 0.25 V to
VDDA-0.25 V
General opamp specs for both
internal and external modes
SID281
SID282
VIN
Charge-pump on, VDDA = 2.7 V –0.05
–
–
VDDA
0.2
VDDA
0.2
-
-
V
–
–
VCM
Charge-pump on, VDDA = 2.7 V –0.05
Datasheet
25
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 10
CTBm opamp specifications (continued)
Spec ID# Parameter
Description
VDDA = 2.7 V
Min Typ Max Units Details/conditions
VOUT
SID283
SID284
SID285
SID286
SID288
SID288A
SID288B
VOUT_1
VOUT_2
VOUT_3
VOUT_4
VOS_TR
VOS_TR
VOS_TR
power=hi, Iload=10 mA
power=hi, Iload=1 mA
power=med, Iload=1 mA
power=lo, Iload=0.1 mA
Offset voltage, trimmed
Offset voltage, trimmed
Offset voltage, trimmed
0.5
0.2
0.2
0.2
–
–
–
–
VDDA
-0.5
VDDA
-0.2
VDDA
-0.2
VDDA
-0.2
V
–
–
–
–
–1.0 0.5 1.0
mV
High mode, input 0 V
to VDDA-0.2 V
Medium mode, input
0 V to VDDA-0.2 V
Low mode, input 0 V
to VDDA-0.2 V
–
–
1
2
–
–
SID290
SID290A
SID290B
SID291
VOS_DR_TR
VOS_DR_TR
VOS_DR_TR
CMRR
Offset voltage drift, trimmed
Offset voltage drift, trimmed
Offset voltage drift, trimmed
DC
–10
–
–
3
10
10
80
10
–
–
µV/°C High mode
µV/°C Medium mode
Low mode
70
–
dB
Input is 0 V to
DDA-0.2 V, Output is
0.2 V to VDDA-0.2 V
V
SID292
PSRR
At 1 kHz, 10-mV ripple
70
85
–
VDDD = 3.6 V,
high-power mode,
input is 0.2 V to
VDDA-0.2 V
Noise
VN2
SID294
SID295
SID296
SID297
SID298
SID299
SID299A
Input-referred, 1 kHz, power =
Hi
Input-referred, 10 kHz, power
= Hi
Input-referred, 100 kHz,
power = Hi
Stable up to max. load. Perfor-
mance specs at 50 pF.
–
–
–
–
6
–
–
72
28
15
–
–
–
nV/rtHz Input and output are
at 0.2 V to VDDA-0.2 V
VN3
Input and output are
at 0.2 V to VDDA-0.2 V
Input and output are
at 0.2 V to VDDA-0.2 V
VN4
–
CLOAD
125
–
pF
V/µs
µs
–
–
–
SLEW_RATE Cload = 50 pF, Power = High,
DDA = 2.7 V
T_OP_WAKE From disable to enable, no
external RC dominating
–
V
–
25
–
OL_GAIN
Open Loop Gain
90
dB
COMP_MODE Comparator mode; 50 mV
drive, Trise=Tfall (approx.)
Datasheet
26
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 10
CTBm opamp specifications (continued)
Spec ID# Parameter
Description
Min Typ Max Units Details/conditions
SID300
SID301
SID302
TPD1
TPD2
TPD3
Response time; power = hi
–
–
–
150
–
–
–
ns
Input is 0.2 V to
VDDA-0.2 V
Response time; power = med
Response time; power = lo
Hysteresis
500
Input is 0.2 V to
VDDA-0.2 V
2500
Input is 0.2 V to
V
–
–
DDA-0.2 V
SID303
SID304
VHYST_OP
WUP_CTB
–
–
10
–
–
25
mV
µs
Wake-up time from Enabled
to Usable
Deep Sleep
mode
Mode 2 is lowest current
range. Mode 1 has higher
GBW.
SID_DS_1 IDD_HI_M1
SID_DS_2 IDD_MED_M1
SID_DS_3 IDD_LOW_M1
SID_DS_4 IDD_HI_M2
SID_DS_5 IDD_MED_M2
SID_DS_6 IDD_LOW_M2
SID_DS_7 GBW_HI_M1
Mode 1, High current
Mode 1, Medium current
Mode 1, Low current
Mode 2, High current
Mode 2, Medium current
Mode 2, Low current
Mode 1, High current
–
–
–
–
–
–
–
1400
700
200
120
60
–
–
–
–
–
–
–
µA
25°C
25°C
25°C
25°C
25°C
25°C
15
4
MHz 20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_8 GBW_MED_M1 Mode 1, Medium current
SID_DS_9 GBW_LOW_M1 Mode 1, Low current
–
–
–
–
–
2
–
–
–
–
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
0.5
0.5
0.2
0.1
SID_DS_10 GBW_HI_M2
Mode 2, High current
SID_DS_11 GBW_MED_M2 Mode 2, Medium current
SID_DS_12 GBW_Low_M2 Mode 2, Low current
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
Datasheet
27
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 10
CTBm opamp specifications (continued)
Spec ID# Parameter
SID_DS_13 VOS_HI_M1
Description
Mode 1, High current
Min Typ Max Units Details/conditions
–
–
–
–
–
–
–
–
–
5
–
–
–
–
–
–
–
–
–
mV
With trim 25°C, 0.2 V
to VDDA-0.2 V
With trim 25°C, 0.2 V
to VDDA-0.2 V
With trim 25°C, 0.2 V
to VDDA-0.2 V
With trim 25°C, 0.2V
to VDDA-0.2 V
With trim 25°C, 0.2 V
to VDDA-0.2 V
With trim 25°C, 0.2 V
to VDDA-0.2 V
SID_DS_14 VOS_MED_M1
Mode 1, Medium current
5
SID_DS_15 VOS_LOW_M1 Mode 1, Low current
5
SID_DS_16 VOS_HI_M2
SID_DS_17 VOS_MED_M2
Mode 2, High current
5
Mode 2, Medium current
5
SID_DS_18 VOS_LOW_M2 Mode 2, Low current
SID_DS_19 IOUT_HI_M1 Mode 1, High current
5
10
10
4
mA Output is 0.5 V to
VDDA-0.5 V
SID_DS_20 IOUT_MED_M1 Mode 1, Medium current
SID_DS_21 IOUT_LOW_M1 Mode 1, Low current
Output is 0.5 V to
VDDA-0.5 V
Output is 0.5 V to
VDDA-0.5 V
SID_DS_22 IOUT_HI_M2
SID_DS_23 IOUT_MED_M2 Mode 2, Medium current
SID_DS_24 IOUT_LOW_M2 Mode 2, Low current
Mode 2, High current
–
–
–
1
1
0.5
–
–
–
Datasheet
28
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.2
Comparator
Table 11
Comparator DC specifications
Spec ID# Parameter
Description
Min Typ
Max
±10
±4
Units Details/conditions
SID84
SID85
SID86
VOFFSET1
VOFFSET2
VHYST
Input offset voltage, Factory trim
Input offset voltage, Custom trim
Hysteresis when enabled
–
–
–
–
–
10
mV
35
Input common mode voltage in
normal mode
Input common mode voltage in
low power mode
Input common mode voltage in
ultra low power mode
Common mode rejection ratio
Common mode rejection ratio
Block current, normal mode
Block current, low power mode
SID87
VICM1
VICM2
0
0
0
–
–
–
VDDD-0.1
VDDD
Modes 1 and 2
V
SID247
SID247A VICM3
SID88 CMRR
SID88A CMRR
SID89
SID248
VDDD-1.15
VDDD ≥ 2.2 V at –40°C
50
42
–
–
–
–
–
–
–
400
100
VDDD ≥ 2.7V
dB
VDDD ≤ 2.7V
ICMP1
ICMP2
–
µA
Block current in ultra low-power
mode
DC Input impedance of
comparator
SID259
SID90
ICMP3
ZCMP
–
–
–
6
–
VDDD ≥ 2.2 V at –40°C
35
MΩ
Table 12
Comparator AC specifications
Spec ID# Parameter
Description
Min Typ
Max
Units Details/conditions
Response time, normal mode, 50
mV overdrive
Responsetime, low power mode,
50 mV overdrive
Response time, ultra-low power
mode, 200 mV overdrive
SID91
SID258
SID92
TRESP1
TRESP2
TRESP3
–
–
–
38
70
110
ns
200
15
2.3
µs
VDDD ≥ 2.2 V at –40°C
5.3.3
Temperature sensor
Table 13
Temperature sensor specifications
Spec ID# Parameter
Description
Temperature sensor accuracy
Min Typ
–5 ±1
Max
5
Units Details/conditions
°C –40 to +85°C
SID93
TSENSACC
Note
6. Guaranteed by characterization.
Datasheet
29
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.4
SAR ADC
Table 14
SAR ADC specifications
Details/
Spec ID# Parameter
Description
Min Typ
Max
Units
conditions
SAR ADC DC specifications
SID94
SID95
SID96
A_RES
Resolution
–
–
–
–
–
–
12
16
4
bits
A_CHNLS_S Number of channels - single ended
A-CHNKS_D Number of channels - differential
Diff inputs use
neighboring I/O
SID97
SID98
A-MONO
A_GAINERR Gain error
Monotonicity
–
–
–
–
–
±0.1
Yes
%
With external
reference
SID99
A_OFFSET
Input offset voltage
–
–
2
mV Measured with
1-V reference
SID100
SID101
SID102
SID103
SID104
SID260
A_ISAR
A_VINS
A_VIND
A_INRES
A_INCAP
VREFSAR
Current consumption
–
VSS
VSS
–
–
–
–
–
–
1
mA
V
V
KΩ
pF
V
Input voltage range - single ended
Input voltage range - differential
Input resistance
Input capacitance
Trimmed internal reference to SAR 1.188 1.2
VDDA
VDDA
2.2
10
1.212
–
SAR ADC AC specifications
SID106
SID107
SID108
SID109
A_PSRR
A_CMRR
A_SAMP
A_SNR
Power supply rejection ratio
Common mode rejection ratio
Sample rate
Signal-to-noise and distortion ratio 65
(SINAD)
70
66
–
–
–
–
–
–
–
1
–
dB
dB Measured at 1 V
Msps
dB
FIN = 10 kHz
SID110
SID111
A_BW
A_INL
Input bandwidth without aliasing
Integral non linearity. VDD = 1.71 to –1.7
5.5, 1 Msps
–
–
–
A_samp/2 kHz
2
LSB VREF = 1 to VDD
SID111A A_INL
SID111B A_INL
Integral non linearity. VDDD = 1.71 to –1.5
3.6, 1 Msps
Integral non linearity. VDD = 1.71 to –1.5
5.5, 500 ksps
Differential non linearity. VDD = 1.71 –1
to 5.5, 1 Msps
Differential non linearity. VDD = 1.71 –1
to 3.6, 1 Msps
–
–
1.7
1.7
2.2
2
LSB VREF = 1.71 to
VDD
LSB VREF = 1 to VDD
SID112
A_DNL
LSB VREF = 1 to VDD
–
–
SID112A A_DNL
SID112B A_DNL
LSB VREF = 1.71 to
VDD
LSB VREF = 1 to VDD
Differential non linearity. VDD = 1.71 –1
to 5.5, 500 ksps
2.2
–
–
–
–
SID113
SID261
A_THD
Total harmonic distortion
–65
100
dB Fin = 10 kHz
ksps 12-bit
resolution
FSARINTREF SAR operating speed without
external reference bypass
–
Datasheet
30
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.5
CSD and IDAC
Table 15
CSD and IDAC specifications
Spec ID#
SYS.PER#3
Parameter
VDD_RIPPLE
Description
Min Typ Max Units Details/conditions
Max allowed ripple on
power supply, DC to
10 MHz
–
–
±50
mV
VDD > 2 V (with ripple),
25°C TA, Sensitivity =
0.1 pF
SYS.PER#16 VDD_RIP-
PLE_1.8
Max allowed ripple on
power supply, DC to
10 MHz
–
–
±25
mV
VDD > 1.75 V (with
ripple), 25°C TA,
Parasitic Capacitance
(CP) < 20 pF,
Sensitivity ≥ 0.4 pF
SID.CSD.BLK ICSD
Maximum block current
–
–
4000
µA Maximum block
current for both IDACs
in dynamic
(switching) mode
including compar-
ators, buffer, and
reference generator
SID.CSD#15 VREF
Voltage reference for CSD
and comparator
External voltage reference 0.6
for CSD and comparator
IDAC1 (7-bits) block
current
IDAC2 (7-bits) block
current
0.6 1.2 VDDA
0.6
-
-
V
V
VDDA – 0.6 or 4.4,
whichever is lower
SID.CSD#15A VREF_EXT
SID.CSD#16 IDAC1IDD
SID.CSD#17 IDAC2IDD
VDDA
0.6
VDDA – 0.6 or 4.4,
whichever is lower
–
–
–
–
–
1750
1750
5.5
µA
µA
V
–
SID308
VCSD
Voltage range of operation 1.71
1.8 V ±5% or 1.8 V to
5.5 V
VDDA – 0.6 or 4.4,
whichever is lower
SID308A
VCOMPIDAC
Voltage compliance range 0.6
of IDAC
VDDA
0.6
–
V
SID309
SID310
IDAC1DNL
IDAC1INL
DNL
INL
–1
–2
–
–
1
2
LSB
LSB INL is ±5.5 LSB for
DDA < 2 V
V
SID311
SID312
IDAC2DNL
IDAC2INL
DNL
INL
–1
–2
–
–
1
2
LSB
LSB INL is ±5.5 LSB for
DDA < 2 V
V
SID313
SNR
Ratio of counts of finger to
noise. Guaranteed by
characterization
5
–
–
Ratio Capacitance range of
5 to 35 pF, 0.1-pF
sensitivity. All use
cases. VDDA > 2 V.
SID314
IDAC1CRT1
IDAC1CRT2
IDAC1CRT3
IDAC1CRT12
Output current of IDAC1 (7 4.2
bits) in low range
Output current of IDAC1(7 34
bits) in medium range
Output current of IDAC1(7 275
bits) in high range
–
–
–
–
5.4
41
µA LSB = 37.5-nA typ
µA LSB = 300-nA typ
µA LSB = 2.4-µA typ
µA LSB = 75-nA typ
SID314A
SID314B
SID314C
330
10.5
Output current of IDAC1 (7
bits) in low range, 2X mode
8
Datasheet
31
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 15
Spec ID#
CSD and IDAC specifications (continued)
Parameter
Description
Min Typ Max Units Details/conditions
SID314D
IDAC1CRT22
Output current of IDAC1(7 69
bits) in medium range, 2X
mode
–
82
µA LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of IDAC1(7 540
bits) in high range, 2X
mode
–
660
µA LSB = 4.8-µA typ
SID315
IDAC2CRT1
IDAC2CRT2
IDAC2CRT3
IDAC2CRT12
IDAC2CRT22
Output current of IDAC2 (7 4.2
bits) in low range
Output current of IDAC2 (7 34
bits) in medium range
Output current of IDAC2 (7 275
bits) in high range
–
–
–
–
–
5.4
41
µA LSB = 37.5-nA typ
µA LSB = 300-nA typ
µA LSB = 2.4-µA typ
µA LSB = 75-nA typ
µA LSB = 600-nA typ
SID315A
SID315B
SID315C
SID315D
330
10.5
82
Output current of IDAC2 (7
bits) in low range, 2X mode
8
Output current of IDAC2(7 69
bits) in medium range, 2X
mode
SID315E
IDAC2CRT32
Output current of IDAC2(7 540
bits) in high range, 2X
mode
–
660
µA LSB = 4.8-µA typ
SID315F
SID315G
IDAC3CRT13
IDAC3CRT23
Output current of IDAC in
8-bit mode in low range
Output current of IDAC in
8-bit mode in medium
range
8
–
–
10.5
82
µA LSB = 37.5-nA typ
µA LSB = 300-nA typ
69
SID315H
SID320
IDAC3CRT33
IDACOFFSET
Output current of IDAC in 540
8-bit mode in high range
–
–
660
1
µA LSB = 2.4-µA typ
All zeroes input
–
LSB Polarity set by Source
or Sink. Offset is 2
LSBs for 37.5 nA/LSB
mode
SID321
SID322
IDACGAIN
IDACMIS-
MATCH1
Full-scale error less offset
Mismatch between IDAC1
and IDAC2 in Low mode
–
–
–
–
±10
9.2
%
LSB LSB = 37.5-nA typ
SID322A
IDACMIS-
MATCH2
Mismatch between IDAC1
and IDAC2 in Medium
mode
Mismatch between IDAC1
and IDAC2 in High mode
Settling time to 0.5 LSB for
8-bit IDAC
Settling time to 0.5 LSB for
7-bit IDAC
–
–
5.6
LSB LSB = 300-nA typ
LSB LSB = 2.4-µA typ
SID322B
SID323
SID324
SID325
IDACMIS-
MATCH3
–
–
–
–
–
–
6.8
5
IDACSET8
IDACSET7
CMOD
µs Full-scale transition.
No external load
µs Full-scale transition.
No external load
nF 5-V rating, X7R or NP0
cap
–
5
External modulator
capacitor.
2.2
–
Datasheet
32
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.6
10-bit CAPSENSE™ ADC
Table 16
10-bit CAPSENSE™ ADC Specifications
Spec ID# Parameter
Description
Resolution
Min Typ Max Units
Details/conditions
SIDA94
A_RES
–
–
10
bits Auto-zeroing is required
every millisecond
SIDA95
A_CHNLS_S Number of channels - single
ended
–
–
16
Defined by AMUX bus
SIDA97
SIDA98
A-MONO
Monotonicity
–
–
–
–
–
Yes
A_GAINERR Gain error
±3
%
In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA99
A_OFFSET
Input offset voltage
–
–
–
±18 mV In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA100
SIDA101
A_ISAR
A_VINS
Current consumption
Input voltage range - single VSSA
ended
–
–
0.25 mA
VDDA
V
SIDA103
SIDA104
SIDA106
A_INRES
A_INCAP
A_PSRR
Input resistance
Input capacitance
Power supply rejection ratio
–
–
–
2.2
20
60
–
–
–
KΩ
pF
dB In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA107
SIDA108
A_TACQ
A_CONV8
Sample acquisition time
–
–
1
–
–
µs
Conversion time for 8-bit
resolution at conversion rate
= Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
21.3 µs Does not include acqui-
sition time. Equivalent to
44.8 ksps including acqui-
sition time.
SIDA108A A_CONV10
Conversion time for 10-bit
resolution at conversion rate
= Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
Signal-to-noise and
distortion ratio (SINAD)
–
–
–
–
61
–
85.3 µs Does not include acqui-
sition time. Equivalent to
11.6 ksps including acqui-
sition time.
SIDA109
A_SND
A_BW
–
dB With 10-Hz input sine
wave, external 2.4-V
reference, VREF (2.4 V)
mode
SIDA110
Input bandwidth without
aliasing
22.4 KHz 8-bit resolution
SIDA111
SIDA112
A_INL
A_DNL
Integral non linearity. 1 ksps
Differential non linearity.
1 ksps
–
–
–
–
2
1
LSB
LSB
VREF = 2.4 V or greater
Datasheet
33
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4
Digital peripherals
5.4.1
Timer, Counter, Pulse-Width Modulator (TCPWM)
Table 17
TCPWM specifications
Spec ID
Parameter
Description
Block current
consumption at 3 MHz
Block current
consumption at 12 MHz
Block current
consumption at 48 MHz
Min Typ Max Units
Details/conditions
All modes (TCPWM)
SID.TCPWM.1 ITCPWM1
SID.TCPWM.2 ITCPWM2
SID.TCPWM.2A ITCPWM3
–
–
–
–
–
–
–
45
All modes (TCPWM)
All modes (TCPWM)
155
650
μA
Fc max = CLK_SYS
Maximum = 48 MHz
For all trigger events[7]
TCPWMFREQ
TPWMENEXT
SID.TCPWM.3
SID.TCPWM.4
Operating frequency
–
–
Fc
–
MHz
Input trigger pulse width 2/Fc
Minimum possible width
of Overflow, Underflow,
and CC (Counter equals
Compare value) outputs
Output trigger pulse
widths
TPWMEXT
SID.TCPWM.5
2/Fc
–
–
Minimum time between
successive counts
Minimum pulse width of
PWM Output
TCRES
SID.TCPWM.5A
SID.TCPWM.5B
Resolution of counter
PWM resolution
1/Fc
1/Fc
–
–
–
–
ns
PWMRES
Minimum pulse width
between Quadrature
phase inputs
Quadrature inputs
resolution
QRES
SID.TCPWM.5C
1/Fc
–
–
5.4.2
I2C
Table 18
Spec ID
SID149
Fixed I2C DC specifications[7]
Parameter
II2C1
Description
Block current
consumption at 100 kHz
Min Typ Max Units
Details/conditions
–
–
–
–
–
–
–
1
50
135
310
–
–
SID150
SID151
SID152
II2C2
II2C3
II2C4
Block current
–
–
consumption at 400 kHz
µA
Block current
consumption at 1 Mbps
I2C enabled in Deep
Sleep mode
Table 19
Spec ID
SID153
Fixed I2C AC specifications[7]
Parameter
Description
Bit rate
Min Typ Max Units
Msps
Details/conditions
–
FI2C1
–
–
1
Note
7. Guaranteed by characterization.
Datasheet
34
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4.3
Table 20
SPI
SPI DC specifications[8]
Spec ID Parameter
Description
Min Typ
Max Units Details/conditions
Block current consumption at
1 Mbps
Block current consumption at
4 Mbps
Block current consumption at
8 Mbps
SID163
SID164
SID165
ISPI1
ISPI2
ISPI3
–
–
–
–
–
–
360
560
600
–
–
–
µA
Table 21
SPI AC Specifications[8]
Spec ID Parameter
Description
Min Typ
Max Units Details/conditions
SPI operating frequency (Master;
6X oversampling)
SID166
FSPI
–
–
8
MHz
Fixed SPI Master mode AC specifications
MOSI valid after SClock driving
edge
MISO valid before SClock
capturing edge
SID167
SID168
SID169
TDMO
TDSI
–
20
0
–
–
–
15
–
–
Full clock, late MISO
sampling
Referred to slave
capturing edge
ns
THMO
Previous MOSI data hold time
–
Fixed SPI Slave mode AC specifications
MOSIvalidbeforeSclockcapturing
edge
MISO valid after Sclock driving
edge
MISO valid after Sclock driving
edge in Ext. Clk mode
Previous MISO data hold time
SID170
SID171
TDMI
TDSO
40
–
–
–
–
–
–
TCPU = 1/FCPU
–
42 +
3*Tcpu
ns
ns
SID171A TDSO_EXT
SID172 THSO
–
48
0
100
–
–
–
–
–
–
SID172A TSSELSSCK SSEL valid to first SCK Valid edge
5.4.4
Table 22
UART
UART DC specifications[8]
Spec ID Parameter
Description
Min Typ
Max Units Details/conditions
Block current consumption at
100 Kbps
Block current consumption at
1000 Kbps
SID160 IUART1
–
–
–
–
55
µA
µA
–
–
SID161 IUART2
312
Table 23
UART AC Specifications[8]
Spec ID Parameter
Description
Min Typ
Max Units Details/conditions
SID162
FUART
Bit rate
–
–
1
Mbps
–
Note
8. Guaranteed by characterization.
Datasheet
35
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4.5
LCD direct drive
Table 24
Spec ID
LCD direct drive DC specifications[9]
Parameter
Description
Min Typ Max Units Details/conditions
Operating current in low
power mode
16 4 small segment
disp. at 50 Hz
SID154
ILCDLOW
5
–
µA
–
LCD capacitance per
SID155
SID156
SID157
CLCDCAP
LCDOFFSET
ILCDOP1
500 5000
pF
–
segment/common driver
–
–
Long-term segment offset
LCD system operating
current Vbias = 5 V
LCD system operating
current Vbias = 3.3 V
20
2
–
–
mV
–
32 4 segments at
50 Hz 25°C
32 4 segments at
50 Hz 25°C
–
–
mA
SID158
ILCDOP2
2
–
Table 25
Spec ID
SID159
LCD Direct Drive AC specifications[9]
Parameter Description
FLCD LCD frame rate
Min Typ Max Units Details/conditions
10 50 150 Hz
–
5.5
Memory
Table 26
Spec ID
SID173
Flash DC specifications
Parameter Description
VPE Erase and program voltage 1.71
Min Typ Max Units Details/conditions
5.5
–
V
–
Table 27
Spec ID
Flash AC specifications
Parameter
Description
Min Typ Max
Units Details/conditions
Row (block) write time
(erase and program)
Row erase time
Row program time after
erase
Bulk erase time (64 KB)
Total device program time
Flash endurance
Row (block) =
256 bytes
[10]
SID174
SID175
SID176
SID178
TROWWRITE
–
–
–
–
–
–
20
16
4
[10]
TROWERASE
TROWPROGRAM
–
ms
[10]
–
–
–
–
[10]
TBULKERASE
–
–
–
–
–
35
7
–
SID180[9] TDEVPROG
SID181[9] FEND
Seconds
Cycles
[10]
100 K
Flash retention. TA 55°C,
SID182[9] FRET
20
10
–
–
–
–
–
–
100 K P/E cycles
Years
Years
Flash retention. TA 85°C,
10 K P/E cycles
Flash retention. TA 105°C,
10K P/E cycles, three
years at TA ≥ 85°C
SID182A[9]
–
–
SID182B
10
–
20
–
Notes
9. Guaranteed by characterization.
10.It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations may be
interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and
privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
Datasheet
36
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 27
Spec ID
Flash AC specifications (continued)
Parameter
Description
Min Typ Max
Units Details/conditions
Number of Wait states at
48 MHz
Number of Wait states at
24 MHz
CPU execution from
Flash
CPU execution from
Flash
SID256
SID257
TWS48
2
1
–
–
–
–
TWS24
5.6
System resources
5.6.1
Power-on reset (POR)
Table 28
Power-on reset (PRES)
Spec ID
Parameter
Description
Min Typ Max
Units Details/conditions
SID.CLK#6 SR_POWER_UP Power supply slew rate
1
–
67
V/ms At power-up and
power-down
SID185[11] VRISEIPOR
SID186[11] VFALLIPOR
Rising trip voltage
Falling trip voltage
0.80
0.70
–
–
1.5
1.4
V
–
–
Table 29
Spec ID
Brown-out detect (BOD) for VCCD
Parameter Description
Min Typ Max
Units Details/conditions
SID190[11] VFALLPPOR
BOD trip voltage in active 1.48
and sleep modes
BOD trip voltage in Deep
Sleep
–
1.62
V
–
SID192[11] VFALLDPSLP
1.11
–
1.5
–
5.6.2
SWD interface
Table 30
SWD interface specifications
Spec ID
Parameter
Description
Min Typ Max
Units Details/conditions
SWDCLK ≤ 1/3 CPU
SID213
SID214
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
–
–
–
–
14
7
clock frequency
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
–
F_SWDCLK2
1.71 V VDD 3.3 V
0.25*
T
0.25*
T
SID215[12] T_SWDI_SETUP T = 1/f SWDCLK
SID216[12] T_SWDI_HOLD T = 1/f SWDCLK
–
–
–
ns
SID217[12] T_SWDO_VALID T = 1/f SWDCLK
SID217A[12] T_SWDO_HOLD T = 1/f SWDCLK
–
1
–
–
0.5*T
–
–
–
Notes
11.Guaranteed by characterization.
12.Guaranteed by design.
Datasheet
37
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6.3
Internal Main Oscillator
Table 31
IMO DC specifications
(Guaranteed by design)
Spec ID
SID218
Parameter
IIMO1
Description
IMO operating current at
48 MHz
Min Typ Max Units
Details/conditions
–
–
250
µA
–
SID219
IIMO2
IMO operating current at
24 MHz
–
–
180
µA
–
Table 32
IMO AC specifications
Parameter Description
Spec ID
Min Typ Max Units
Details/conditions
At –40°C to 85°C, for indus-
trial temperature range
and original extended
industrial range parts
At –40°C to 105°C, for all
extended industrial
temperature range parts
At –30°C to 105°C, for
enhanced IMO extended
industrial temperature
range parts
SID223[14]
–
–
–
–
–
–
±2.0
±2.5
±2.0
%
%
%
SID223A[13, 14]
Frequency variation at
24, 32, and 48 MHz
(trimmed)
SID223B[13, 14] FIMOTOL1
At –20°C to 105°C, for
enhanced IMO extended
industrial temperature
range parts
At 0°C to 85°C, for enhanced
IMO extended industrial
temperature range parts
SID223C[13, 14]
SID223D[13, 14]
–
–
–
–
±1.5
%
%
±1.25
SID226
SID228
TSTARTIMO
TJITRMSIMO2 RMS jitter at 24 MHz
IMO startup time
–
–
–
145
7
–
µs
ps
–
–
Notes
13.The enhanced IMO extended temperature range parts replace the original extended industrial temperature range parts. For details
on how to identify enhanced IMO extended temperature range parts, please refer to KBA235887.
14.Evaluated by characterization. Does not take into account soldering or board-level effects.
Datasheet
38
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6.4
Internal Low-Speed Oscillator
Table 33
ILO DC specifications
(Guaranteed by design)
Spec ID
SID231
Parameter
IILO1
Description
ILO operating current
Min Typ Max Units
0.3 1.05 µA
Details/conditions
–
–
Table 34
Spec ID
ILO AC specifications
Parameter Description
Min Typ Max Units
Details/conditions
SID234[15] TSTARTILO1 ILO startup time
–
40
20
–
50
40
2
60
80
ms
%
–
–
–
SID236[15] TILODUTY
SID237
ILO duty cycle
FILOTRIM1
ILO frequency range
kHz
5.6.5
Watch Crystal Oscillator (WCO)
Table 35
WCO specifications
Spec ID
SID398
Parameter
FWCO
Description
Crystal frequency
Min Typ
Max Units Details/conditions
kHz
–
32.76
8
–
SID399
SID400
SID401
SID402
SID403
SID404
SID405
FTOL
ESR
PD
TSTART
CL
C0
Frequency tolerance
Equivalent series resistance
Drive level
Startup time
Crystal load capacitance
Crystal shunt capacitance
–
–
–
–
6
–
–
50
50
–
–
–
250 ppm With 20-ppm crystal
–
1
500
12.5
–
kΩ
µW
ms
pF
1.35
–
pF
IWCO1
Operating current (high
power mode)
8
µA
5.6.6
External clock
Table 36
External clock specifications
Spec ID
Parameter
ExtClkFreq
Description
External clock input
frequency
Min Typ
Max Units Details/conditions
SID305[15]
0
–
48
MHz
–
–
SID306[15]
ExtClkDuty
Duty cycle; measured at VDD/2 45
–
55
%
5.6.7
External Crystal Oscillator and PLL
Table 37
Spec ID
SID316[16]
External Crystal Oscillator (ECO) specifications
Parameter
Description
Min Typ
Max Units Details/conditions
IECO1
External clock input
frequency
–
–
1.5
mA
–
–
SID317[16]
FECO
Crystal frequency range
4
–
33
MHz
Note
15.Guaranteed by design.
16.Guaranteed by characterization.
Datasheet
39
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 38
Spec ID
SID410
SID411
SID412
PLL specifications
Parameter
Description
Min Typ Max
Units Details/conditions
IDD_PLL_48 In = 3 MHz, Out = 48 MHz
IDD_PLL_24 In = 3 MHz, Out = 24 MHz
–
–
1
530
300
–
610
405
48
µA
µA
–
–
–
Fpllin
PLL input frequency
MHz
PLL intermediate frequency;
prescaler out
SID413
SID414
Fpllint
1
–
–
3
MHz
MHz
–
–
VCO output frequency
before post-divide
Fpllvco
Divvco
22.5
104
VCO Output post-divider
range; PLL output frequency
is Fpplvco/Divvco
SID415
1
–
8
–
–
SID416
SID417
Plllocktime Lock time at startup
–
–
–
–
250
150
µs
ps
Period jitter for VCO ≥ 67
Guaranteed by
design
Jperiod_1
MHz
Period jitter for VCO ≤ 67
Guaranteed by
design
SID416A
Jperiod_2
MHz
–
–
200
ps
5.6.8
System clock
Table 39
System clock specification
Spec ID
Parameter
Description
System clock source
switching time
Min Typ Max
Units Details/conditions
SID262[16] TCLKSWITCH
3
–
4
Periods
–
5.6.9
Smart I/Os
Table 40
Smart I/O pass-through time (Delay in bypass mode)
Parameter Description Min Typ Max
1.6
Spec ID
SID252
Units Details/conditions
PRG_BYPASS Max delay added by Smart
I/O in bypass mode
–
–
ns
–
5.6.10
Table 41
Spec ID
SID420
CAN
CAN specifications
Parameter
IDD_CAN
Description
Block current consumption
CAN Bit rate
Min Typ Max
Units Details/Conditions
–
–
–
–
200
1
µA
–
SID421
CAN_bits
Mbps Min 8-MHZ clock
Datasheet
40
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Ordering information
6
Ordering information
The marketing part numbers for the PSoC™ 4100S Plus devices are listed in the following table.
Table 42 Ordering information
Features
Packages
CY8C4126AXI-S443
24
24
24
24
24
48
48
48
48
48
48
48
48
48
48
48
24
24
24
24
24
24
24
24
24
24
48
48
48
48
48
48
48
48
48
48
48
48
64
64
8
8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
1 Msps
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
5
5
5
5
4
4
5
5
5
4
4
5
5
5
4
4
4
5
5
5
4
4
5
5
5
4
4
5
5
5
4
4
4
5
5
5
4
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
24 37
24 54
24 54
24 54
24 54
24 37
24 38
24 54
24 54
24 54
24 37
24 38
24 54
24 54
24 54
24 38
24 37
24 38
24 54
24 54
24 54
24 37
24 38
24 54
24 54
24 54
24 37
24 38
24 54
24 54
24 54
24 37
24 38
24 38
24 54
24 54
24 54
24 38
✔
–
–
–
–
✔
–
–
–
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 105
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 105
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 105
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 105
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 105
–40 to 85
–40 to 85
–40 to 85
–40 to 105
–40 to 85
–40 to 105
–40 to 85
–40 to 85
CY8C4126AZI-S445
CY8C4126AXI-S445
CY8C4126AZI-S455
CY8C4126AXI-S455
CY8C4146AXI-S443
CY8C4146AZI-S443
CY8C4146AZI-S445
CY8C4146AZQ-S445
CY8C4146AXI-S445
CY8C4146AXI-S453
CY8C4146AZI-S453
CY8C4146AZI-S455
CY8C4146AZQ-S455
CY8C4146AXI-S455
CY8C4146AZI-S463
CY8C4127AXI-S443
CY8C4127AZI-S443
CY8C4127AZI-S445
CY8C4127AZQ-S445
CY8C4127AXI-S445
CY8C4127AXI-S453
CY8C4127AZI-S453
CY8C4127AZI-S455
CY8C4127AZQ-S455
CY8C4127AXI-S455
CY8C4147AXI-S443
CY8C4147AZI-S443
CY8C4147AZI-S445
CY8C4147AZQ-S445
CY8C4147AXI-S445
CY8C4147AXI-S453
CY8C4147AZI-S453
CY8C4147AZQ-S453
CY8C4147AZI-S455
CY8C4147AZQ-S455
CY8C4147AXI-S455
CY8C4147AZI-S463
4126
64
8
–
–
✔
–
64
8
–
–
✔
–
64
8
–
–
✔
–
64
8
✔
–
–
–
64
8
1 Msps
✔
–
–
–
64
8
1 Msps
–
✔
✔
–
–
64
8
1 Msps
–
–
–
64
8
1 Msps
–
–
✔
–
4146
64
8
1 Msps
✔
–
–
–
64
8
1 Msps
✔
–
–
–
64
8
1 Msps
–
✔
✔
–
–
64
8
1 Msps
–
–
–
64
8
1 Msps
–
–
✔
–
64
8
1 Msps
–
✔
–
–
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
1 Msps
✔
–
–
–
✔
–
–
–
–
✔
✔
–
–
–
–
–
–
–
✔
–
4127
✔
–
–
–
✔
–
–
–
–
✔
✔
–
–
–
–
–
–
–
✔
–
✔
–
–
–
1 Msps
✔
–
–
–
1 Msps
–
✔
✔
–
–
1 Msps
–
–
–
1 Msps
–
–
✔
–
1 Msps
✔
–
–
–
4147
1 Msps
✔
✔
–
–
–
1 Msps
–
–
–
1 Msps
–
✔
✔
–
–
1 Msps
–
–
–
1 Msps
–
–
✔
–
1 Msps
–
✔
–
Datasheet
41
002-19966 Rev. *K
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Ordering information
Table 42
Ordering information (continued)
Features
Packages
CY8C4147AZI-S465
48
48
48
48
48
48
128
128
128
128
128
128
16
16
16
16
16
16
2
2
2
2
2
2
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
2
2
2
2
2
2
8
8
8
8
8
8
5
5
5
5
5
5
✔
✔
✔
✔
✔
✔
1
1
1
1
1
1
24 54
24 54
24 54
24 54
24 54
24 54
–
–
–
–
–
–
–
–
–
–
–
–
✔
✔
–
–
–
–40 to 85
–40 to 105
–40 to 85
–40 to 85
–40 to 105
-40 to 85
CY8C4147AZQ-S465
CY8C4147AXI-S465
CY8C4147AZI-S475
CY8C4147AZQ-S475
CY8C4147AXI-S475
✔
–
4147
✔
✔
–
–
✔
Datasheet
42
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Ordering information
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
CY8C
4
A
B
Description
Infineon prefix
Architecture
Family
Values
Meaning
4
1
2
PSoC™ 4 MCU
4100 family
CPU speed
24 MHz
4
48 MHz
C
Flash capacity
Package code
4
5
6
7
AX
AZ
LQ
16 KB
32 KB
64 KB
128 KB
DE
TQFP (0.8-mm pitch)
TQFP (0.5-mm pitch)
QFN
PV
SSOP
FN
CSP
I
Q
S
M
L
Industrial
F
S
Temperature range
Series designator
Extended Industrial
PSoC™ 4 S-series
PSoC™ 4 M-series
PSoC™ 4 L-series
PSoC™ 4 Bluetooth® LE-series
Code of feature set in the specific family
BL
000-999
XYZ
Attributes code
The following is an example of a part number:
CY 8 C 4 A B C DE F – S XYZ
Example
Infineon prefix
Architecture
Family within architecture
CPU speed
4 : PSoC™ 4 MCU
1 : 4100 family
4 : 48 MHz
5 : 32 KB
Flash capacity
Package code
:
AZ/AX TQFP
I : Industrial
Temperature range
Series designator
Attributes code
Datasheet
43
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
7
Packaging
The PSoC™ 4100S Plus is offered in 44-pin TQFP, 48-pin TQFP, 64-pin TQFP Normal pitch, and 64-pin TQFP fine
pitch packages.
Table 43 provides the package dimensions and Infineon drawing numbers.
Table 43
Spec ID#
Package list
Package
64-pin TQFP
64-pin TQFP
44-pin TQFP
48-pin TQFP
Description
Package dwg
51-85046
BID20
BID27
BID34A
BID70
14 × 14 × 1.4-mm height with 0.8-mm pitch
10 × 10 × 1.6-mm height with 0.5-mm pitch
10 × 10 × 1.4-mm height with 0.8-mm pitch
7 × 7 × 1.4-mm height with 0.5-mm pitch
51-85051
51-85064
51-85135
Table 44
Package thermal characteristics
Description
Parameter
Package
Min
–40
–40
–
Typ Max
Units
TA
Operating ambient temperature
Operating junction temperature
–
–
25
–
105
125
–
°C
TJ
°C
TJA
TJC
TJA
TJC
TJA
TJC
TJA
TJC
Package θJA
Package θJC
Package θJA
Package θJC
Package θJA
Package θJC
Package θJA
Package θJC
44-pin TQFP
44-pin TQFP
55.6
14.4
46
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
–
–
64-pin TQFP (0.5-mm pitch)
64-pin TQFP (0.5-mm pitch)
64-pin TQFP (0.8-mm pitch)
64-pin TQFP (0.8-mm pitch)
48-pin TQFP (0.5-mm pitch)
48-pin TQFP (0.5-mm pitch)
–
–
–
10
–
–
36.8
9.4
39.4
9.3
–
–
–
–
–
–
–
Table 45
Package
All
Solder reflow peak temperature
Maximum peak temperature
260°C
Maximum time at peak temperature
30 seconds
Table 46
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All
MSL 3
Datasheet
44
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
7.1
Package diagrams
ș 1
ș
ș 2
DIMENSIONS
MIN. NOM. MAX.
1.60
NOTE:
SYMBOL
A
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.05
0.15
A1
A2
D
1.35 1.40 1.45
15.75 16.00 16.25
13.95 14.00 14.05
15.75 16.00 16.25
13.95 14.00 14.05
D1
E
E1
0.08
0.08
0°
R
R
ș
0.20
0.20
7°
1
2
ș 1
ș 2
c
0°
11° 12° 13°
0.20
0.30 0.35 0.40
0.45 0.60 0.75
1.00 REF
b
L
L1
L 2
L 3
e
0.25 BSC
0.20
0.80 TYP
51-85046 *H
Figure 7
64-pin TQFP package (0.8-mm pitch) outline
Datasheet
45
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
51-85051 *D
Figure 8
64-pin TQFP package (0.5-mm pitch) outline
51-85064 *G
Figure 9
44-pin TQFP package outline
Datasheet
46
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
51-85135 *C
Figure 10
48-pin 7 × 7 × 1.4 mm TQFP package outline
Datasheet
47
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
8
Acronyms
Table 47
Acronym
abus
Acronyms used in this document
Description
analog local bus
ADC
AG
analog-to-digital converter
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data transfer
bus
ALU
arithmetic logic unit
AMUXBUS analog multiplexer bus
API
application programming interface
APSR
Arm®
ATM
BW
application program status register
advanced RISC machine, a CPU architecture
automatic thump mode
bandwidth
CAN
CMRR
CPU
CRC
DAC
DFB
DIO
DMIPS
DMA
DNL
DNU
DR
Controller Area Network, a communications protocol
common-mode rejection ratio
central processing unit
cyclic redundancy check, an error-checking protocol
digital-to-analog converter, see also IDAC, VDAC
digital filter block
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
Dhrystone million instructions per second
direct memory access, see also TD
differential nonlinearity, see also INL
do not use
port write data registers
DSI
digital system interconnect
DWT
ECC
data watchpoint and trace
error correcting code
ECO
EEPROM
EMI
EMIF
EOC
EOF
EPSR
ESD
ETM
FIR
external crystal oscillator
electrically erasable programmable read-only memory
electromagnetic interference
external memory interface
end of conversion
end of frame
execution program status register
electrostatic discharge
embedded trace macrocell
finite impulse response, see also IIR
flash patch and breakpoint
FPB
Datasheet
48
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 47
Acronym
FS
Acronyms used in this document (continued)
Description
full-speed
GPIO
HVI
IC
general-purpose input/output, applies to a PSoC™ pin
high-voltage interrupt, see also LVI, LVD
integrated circuit
IDAC
IDE
I2C, or IIC
IIR
ILO
IMO
INL
current DAC, see also DAC, VDAC
integrated development environment
Inter-Integrated Circuit, a communications protocol
infinite impulse response, see also FIR
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input/output, see also GPIO, DIO, SIO, USBIO
initial power-on reset
I/O
IPOR
IPSR
IRQ
interrupt program status register
interrupt request
ITM
LCD
LIN
instrumentation trace macrocell
liquid crystal display
Local Interconnect Network, a communications protocol.
link register
LR
LUT
lookup table
LVD
LVI
low-voltage detect, see also LVI
low-voltage interrupt, see also HVI
low-voltage transistor-transistor logic
multiply-accumulate
microcontroller unit
master-in slave-out
LVTTL
MAC
MCU
MISO
NC
no connect
NMI
nonmaskable interrupt
NRZ
NVIC
NVL
opamp
PAL
non-return-to-zero
nested vectored interrupt controller
nonvolatile latch, see also WOL
operational amplifier
programmable array logic, see also PLD
program counter
PC
PCB
PGA
PHUB
PHY
PICU
PLA
printed circuit board
programmable gain amplifier
peripheral hub
physical layer
port interrupt control unit
programmable logic array
Datasheet
49
002-19966 Rev. *K
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 47
Acronym
PLD
Acronyms used in this document (continued)
Description
programmable logic device, see also PAL
phase-locked loop
PLL
PMDD
POR
PRES
PRS
package material declaration data sheet
power-on reset
precise power-on reset
pseudo random sequence
port read data register
PS
PSoC™
PSRR
PWM
RAM
RISC
RMS
RTC
programmable system on chip
power supply rejection ratio
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
RTL
RTR
RX
register transfer language
remote transmission request
receive
SAR
SC/CT
SCL
successive approximation register
switched capacitor/continuous time
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
SIO
SOC
SOF
signal to noise and distortion ratio
special input/output, GPIO with advanced features. See GPIO.
start of conversion
start of frame
SPI
SR
Serial Peripheral Interface, a communications protocol
slew rate
SRAM
SRES
SWD
SWV
TD
static random access memory
software reset
serial wire debug, a test protocol
single-wire viewer
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
THD
TIA
TRM
TTL
technical reference manual
transistor-transistor logic
TX
transmit
UART
UDB
Universal Asynchronous Transmitter Receiver, a communications protocol
universal digital block
Datasheet
50
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 47
Acronym
USB
Acronyms used in this document (continued)
Description
Universal Serial Bus
USBIO
VDAC
WDT
USB input/output, PSoC™ pins used to connect to a USB port
voltage DAC, see also DAC, IDAC
watchdog timer
WOL
WRES
XRES
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
XTAL
crystal
Datasheet
51
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Document conventions
9
Document conventions
9.1
Units of measure
Table 48
Units of measure
Symbol
Unit of measure
°C
dB
degrees Celsius
decibel
fF
Hz
femto farad
hertz
KB
1024 bytes
kbps
Khr
kHz
k
ksps
LSB
Mbps
MHz
M
Msps
µA
kilobits per second
kilohour
kilohertz
kilo ohm
kilosamples per second
least significant bit
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
µF
µH
µs
µV
microhenry
microsecond
microvolt
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
nanovolt
ns
nV
ohm
pF
picofarad
ppm
ps
s
parts per million
picosecond
second
sps
sqrtHz
V
samples per second
square root of hertz
volt
Datasheet
52
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Revision history
Revision history
Document
Date of release Description of changes
version
*E
2017-12-15
2018-02-13
New release
Updated Pinouts and DC specifications.
*F
Updated Clock Diagram to show Watchdog details and clock divider infor-
mation.
*G
2018-05-09
2018-09-14
Removed preliminary statement in Pinouts.
Updated 32-bit MCU subsystem feature list.
Added 48-pin TQFP pin and package details.
Updated Watch Crystal Oscillator (WCO).
Corrected typos in CTBm opamp specifications.
Updated values for SID260.
*H
Updated Conditions for SID.CSD#15, SID.CSD#15A, and SID308A.
Updated min and max values for SID172A.
Added extended temperature range.
Updated the title for AN85951.
Updated Serial Communication Block (SCB).
Updated LCD segment drive.
*I
2019-06-28
2020-11-10
Updated description for SID55.
Added ModusToolbox™ in Features.
Updated Development ecosystem.
Added ModusToolbox™ software.
Updated Table 27: Updated SID182B.
Updated Table 32: Added SID223A.
Updated Ordering information.
*J
Migrated to Infineon template.
Updated Table 32: Updated spec SID223 and SID223A. Added specs SID223B
through SID223D.
*K
2023-01-24
Updated Ordering information.
Updated the footnotes in IMO AC specifications
Datasheet
53
002-19966 Rev. *K
2023-01-24
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
WARNINGS
The information given in this document shall in no Due to technical requirements products may contain
Edition 2023-01-24
Published by
event be regarded as a guarantee of conditions or dangerous substances. For information on the types
characteristics (“Beschaffenheitsgarantie”).
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Document reference
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