CY62148ELL-45ZSXIT [INFINEON]
Asynchronous SRAM;
| 型号： | CY62148ELL-45ZSXIT |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总20页 (文件大小：803K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY62148E MoBL
4-Mbit (512K × 8) Static RAM
4-Mbit (512K
× 8) Static RAM
advanced circuit design to provide ultra low standby current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications. The device also has an automatic power-down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The eight input and output pins (I/O0
through I/O7) are placed in a high impedance state when the
device is deselected (CE HIGH), Outputs are disabled (OE
HIGH), or during an active Write operation (CE LOW and WE
LOW).
Features
■ Very high speed: 45 ns
■ Voltage range: 4.5 V to 5.5 V
■ Pin compatible with CY62148B
■ Ultra low standby power
❐ Typical standby current: 2.5 µA
❐ Maximum standby current: 7 µA (Industrial)
■ Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A18).
■ Easy memory expansion with CE, and OE features
■ Automatic power-down when deselected
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 32-pin thin small outline package (TSOP) II
and 32-pin small-outline integrated circuit (SOIC)[1] packages
The CY62148E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
Functional Description
The CY62148E is a high performance CMOS static RAM
organized as 512K words by 8-bits. This device features
For a complete list of related documentation, click here.
Logic Block Diagram
A
I/O
I
0
0
INPUT BUFFER
A
1
A
2
I/O
I
1
2
3
4
5
6
7
A
3
A
4
I/O
I
A
5
A
I/O
I
6
512K x 8
A
7
A
I/O
I
8
ARRAY
A
9
A
I/O
I
10
A
11
A
I/O
I
12
I/O
CE
I
POWER
DOWN
COLUMN DECODER
WE
OE
Note
1. SOIC package is available only in 55 ns speed bin.
Cypress Semiconductor Corporation
Document Number: 38-05442 Rev. *S
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 26, 2020
CY62148E MoBL
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagrams ..........................................................12
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure .......................................................14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products ....................................................................19
PSoC® Solutions ......................................................19
Cypress Developer Community .................................19
Technical Support .....................................................19
Document Number: 38-05442 Rev. *S
Page 2 of 19
CY62148E MoBL
Pin Configurations
Figure 1. 32-pin SOIC/TSOP II pinout [2]
Top View
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
A17
A16
A14
A12
A7
1
2
32
31
30
29
28
27
26
25
24
23
22
3
4
5
A6
6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
7
8
9
10
11
12
13
14
15
16
CE
21
20
19
18
17
I/O7
I/O6
I/O5
I/O4
I/O3
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1 MHz f = fmax
Typ [3] Max Typ [3] Max
VCC Range (V)
Speed
(ns)
Product
Standby ISB2 (µA)
Range
CY62148ELL TSOP II Industrial
Min
4.5
4.5
Typ [3] Max
Typ [3]
2.5
Max
7
5.0
5.0
5.5
5.5
45
55
3.5
3.5
6
6
15
15
20
20
CY62148ELL SOIC
Industrial/
2.5
7
Automotive-A
Notes
2. SOIC package is available only in 55 ns speed bin.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document Number: 38-05442 Rev. *S
Page 3 of 19
CY62148E MoBL
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Latch-up current ....................................................> 200 mA
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Operating Range
Supply voltage
Ambient
Temperature
[6]
Device
Range
VCC
to ground potential .............–0.5 V to 6.0 V (VCCmax + 0.5 V)
DC voltage applied to outputs
CY62148E
Industrial/
Automotive-A
–40 °C to +85 °C 4.5 V to 5.5 V
in high Z state [4, 5] .............–0.5 V to 6.0 V (VCCmax + 0.5 V)
DC input voltage [4, 5] .........–0.5 V to 6.0 V (VCCmax + 0.5 V)
Electrical Characteristics
Over the operating range
45 ns
Min Typ [8] Max
55 ns [7]
Unit
Parameter
Description
Test Conditions
Min Typ [8] Max
[9]
VOH
Output HIGH voltage
VCC = 4.5 V, IOH = –1 mA
VCC = 5.5 V, IOH = –0.1 mA
IOL = 2.1 mA
2.4
–
–
–
–
–
–
–
2.4
–
–
–
–
–
–
–
3.4 [8]
0.4
V
V
V
V
V
3.4 [8]
VOL
VIH
VIL
Output LOW voltage
Input HIGH voltage
Input LOW voltage
–
0.4
–
VCC = 4.5 V to 5.5 V
2.2
–0.5
VCC + 0.5 2.2
VCC + 0.5
–
VCC = 4.5 V to 5.5 V For TSOPII
package
0.8
–
For SOIC
package
–
–
–
–0.5
–
0.6 [10]
IIX
Input leakage current
GND < VI < VCC
–1
–1
–
–
–
+1
+1
20
6
–1
–1
–
–
–
+1
+1
20
6
µA
µA
IOZ
ICC
Output leakage current GND < VO < VCC, output disabled
VCC operating supply
current
f = fmax = 1/tRC
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
,
15
3.5
15
3.5
mA
–
–
[11]
ISB2
Automatic CE
CE > VCC – 0.2 V,
–
2.5
7
–
2.5
7
µA
power-down current –
CMOS inputs
V
IN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
4.
5.
V
V
= –2.0 V for pulse durations less than 20 ns for I < 30 mA.
IL(min)
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
6. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
and 200 µs wait time after V stabilization.
CC
CC(min)
7. SOIC package is available only in 55 ns speed bin.
8. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
9. Please note that the maximum V limit for this device does not exceed minimum CMOS V of 3.5V. If you are interfacing this SRAM with 5 V legacy processors
OH
IH
that require a minimum V of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
IH
10. Under DC conditions the device meets a V of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6 V. This
IL
is applicable to SOIC package only.
11. Chip enable (CE) must be HIGH at CMOS level to meet the I
/ I
spec. Other inputs can be left floating.
SB2 CCDR
Document Number: 38-05442 Rev. *S
Page 4 of 19
CY62148E MoBL
Capacitance
Parameter [12]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)
COUT
10
pF
Thermal Resistance
32-pin SOIC 32-pin TSOP II
Parameter [12]
Description
Test Conditions
Unit
Package
Package
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
51.57
59.10
C/W
JC
Thermal resistance
(junction to case)
25.01
12.19
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
3.0 V
90%
10%
OUTPUT
90%
10%
R2
GND
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameter [12]
5.0 V
Unit
R1
R2
1800
990
RTH
VTH
639
1.77
V
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05442 Rev. *S
Page 5 of 19
CY62148E MoBL
Data Retention Characteristics
Over the operating range
Parameter
VDR
Description
VCC for data retention
Data retention current
Conditions
Min
2
Typ [13]
Max
–
Unit
V
–
3
[14]
ICCDR
VCC = VDR
,
Industrial/
Automotive-A
–
8.8
µA
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
tCDR
Chip deselect to data retention
time
0
–
–
–
–
ns
ns
[15]
tR
Operation recovery time
45/55
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 2.0 V
VCC
CE
t
t
CDR
R
Notes
13. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
14. Chip enable (CE) must be HIGH at CMOS level to meet the I
/ I
spec. Other inputs can be left floating.
SB2 CCDR
15. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V
> 100 µs.
CC(min)
CC
DR
CC(min)
Document Number: 38-05442 Rev. *S
Page 6 of 19
CY62148E MoBL
Switching Characteristics
Over the operating range
45 ns
55 ns [18]
Parameter [16, 17]
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
55
–
–
55
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
Data hold from address change
10
–
10
–
tACE
45
22
–
55
25
–
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z [19]
OE HIGH to high Z [19, 20]
CE LOW to low Z [19]
CE HIGH to high Z [19, 20]
CE LOW to power-up
CE HIGH to power-down
tDOE
–
–
tLZOE
5
5
tHZOE
–
18
–
–
20
–
tLZCE
10
–
10
–
tHZCE
18
–
20
–
tPU
0
0
tPD
–
45
–
55
Write Cycle [21, 22]
tWC
Write cycle time
45
35
35
0
–
–
55
40
40
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to write end
Address setup to write end
–
–
tHA
Address hold from write end
Address setup to write start
–
–
tSA
0
–
0
–
tPWE
tSD
35
25
0
–
40
25
0
–
WE pulse width
Data setup to write end
–
–
tHD
Data hold from write end
–
–
WE LOW to high Z [19, 20]
WE HIGH to low Z [19]
tHZWE
tLZWE
–
18
–
–
20
–
10
10
Notes
16. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the chip enable signal as described
in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Notes is no longer applicable. It is available
for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
17. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified I /I as shown in the Figure 2 on page 5.
OL OH
18. SOIC package is available only in 55 ns speed bin.
19. At any temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
LZWE
HZCE
LZCE HZOE
LZOE
HZWE
20. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
21. The internal wre.ite time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can terminate
IL
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
22. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 38-05442 Rev. *S
Page 7 of 19
CY62148E MoBL
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [23, 24]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [24, 25]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
t
V
CC
PU
50%
SUPPLY
CURRENT
50%
ISB
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [26, 27]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
28
DATA I/O
NOTE
DATA VALID
t
HZOE
Notes
23. Device is continuously selected. OE, CE = V .
IL
24. WE is HIGH for read cycles.
25. Address valid before or similar to CE transition LOW.
26. Data I/O is high impedance if OE = V
.
IH
27. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
28. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05442 Rev. *S
Page 8 of 19
CY62148E MoBL
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (CE Controlled) [29, 30]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [30, 31]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
32
NOTE
DATA VALID
DATA I/O
t
t
LZWE
HZWE
Notes
29. Data I/O is high impedance if OE = V
.
IH
30. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
31. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
32. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05442 Rev. *S
Page 9 of 19
CY62148E MoBL
Truth Table
CE
WE
X
OE
X
I/O
Mode
Deselect/power-down
Read
Power
H [33]
High Z
Data out
Data in
High Z
Standby (ISB)
L
L
L
H
L
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
X
Write
H
H
Selected, outputs disabled
Note
33. Chip enable (CE) must be HIGH at CMOS level to meet the I
/ I
spec. Other inputs can be left floating.
SB2 CCDR
Document Number: 38-05442 Rev. *S
Page 10 of 19
CY62148E MoBL
Ordering Information
Table 1 lists the CY62148E MoBL key package features and ordering codes. The table contains only the parts that are currently
available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress
website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Table 1. Key features and Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
55
CY62148ELL-45ZSXI
CY62148ELL-55SXI
51-85095 32-pin TSOP II (Pb-free)
51-85081 32-pin SOIC (Pb-free)
Industrial
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
X
E
- XX XX
LL
X
4
CY 621
8
Temperature Grade: X = I
I = Industrial
Pb-free
Package Type: XX = ZS or S
ZS = 32-pin TSOP II
S = 32-pin SOIC
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
Process Technology: E = 90 nm
Bus Width: 8 = × 8
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05442 Rev. *S
Page 11 of 19
CY62148E MoBL
Package Diagrams
Figure 9. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) Package Outline, 51-85095
51-85095 *D
Document Number: 38-05442 Rev. *S
Page 12 of 19
CY62148E MoBL
Package Diagrams (continued)
Figure 10. 32-pin SOIC (450 Mils) Package Outline, 51-85081
51-85081 *F
Document Number: 38-05442 Rev. *S
Page 13 of 19
CY62148E MoBL
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
Chip Enable
Symbol
°C
Unit of Measure
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
degree Celsius
megahertz
microampere
microsecond
milliampere
nanosecond
ohm
MHz
µA
µs
mA
ns
OE
Output Enable
MoBL
SOIC
SRAM
TSOP
WE
More Battery Life
Small Outline Integrated Circuit
Static Random Access Memory
Thin Small Outline Package
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 38-05442 Rev. *S
Page 14 of 19
CY62148E MoBL
Document History Page
Document Title: CY62148E MoBL, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05442
Submission
Revision
ECN
Description of Change
Date
**
201580
249276
01/08/2004 New data sheet.
*A
08/03/2004 Changed status from Advance Information to Preliminary.
Updated Features:
Added RTSOP II Package related information.
Removed FBGA Package related information.
Updated Functional Description:
Added RTSOP II package related information.
Removed FBGA Package related information.
Updated Pin Configurations:
Added RTSOP II package related information.
Removed FBGA Package related information.
Updated Operating Range:
Updated Note 6 (Changed VCC stabilization time from 100 s to 200 s).
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 2.0 A to 2.5 A.
Changed minimum value of tR parameter from 100 s to tRC ns.
Updated Switching Characteristics:
Changed minimum value of tOHA parameter from 6 ns to 10 ns corresponding to both 35 ns
and 45 ns speed bins.
Changed maximum value of tDOE parameter from 15 ns to 18 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZOE, tHZWE parameters from 12 ns to 15 ns corresponding
to 35 ns speed bin and 15 ns to 18 ns corresponding to 45 ns speed bin.
Changed minimum value of tSCE parameter from 25 ns to 30 ns corresponding to 35 ns
speed bin and 40 ns to 35 ns corresponding to 45 ns speed bin.
Changed maximum value of tHZCE parameter from 12 ns to18 ns corresponding to 35 ns
speed bin and 15 ns to 22 ns corresponding to 45 ns speed bin.
Changed minimum value of tSD parameter from 15 ns to 18 ns corresponding to 35 ns speed
bin and 20 ns to 22 ns corresponding to 45 ns speed bin.
Updated Ordering Information:
Corrected typo in Package Name column.
Updated part numbers.
*B
414820
12/16/2005 Changed status from Preliminary to Final.
Changed the address of Cypress Semiconductor Corporation on Page 1 from “3901 North
First Street” to “198 Champion Court”.
Updated Features:
Removed 35 ns speed bin.
Updated Pin Configurations:
Removed Note “DNU pins have to be left floating or tied to VSS to ensure proper application.”
and its reference.
Updated Product Portfolio:
Removed 35 ns speed bin.
Updated Maximum Ratings:
Updated Note 4 (to include current limit).
Document Number: 38-05442 Rev. *S
Page 15 of 19
CY62148E MoBL
Document History Page (continued)
Document Title: CY62148E MoBL, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05442
Submission
Revision
ECN
Description of Change
Date
*B (cont.)
414820
12/16/2005 Updated Electrical Characteristics:
Removed “L” version of CY62148E.
Changed typical value of ICC parameter from 1.5 mA to 2 mA corresponding to Test
Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2 mA to 2.5 mA corresponding to Test
Condition “f = 1 MHz”.
changed typical value of ICC parameter from 12 mA to 15 mA corresponding to Test
Condition “f = fmax”.
Removed ISB1 parameter and its corresponding details.
Changed typical value of ISB2 parameter from 0.7 A to 1 A.
Changed maximum value of ISB2 parameter from 2.5 A to 7 A.
Updated AC Test Loads and Waveforms:
Changed the AC test load capacitance from 100 pF to 30 pF in Figure 2.
Changed test load parameters R1, R2, RTH and VTH from 1838 , 994 , 645 and 1.75 V
to 1800 , 990 , 639 and 1.77 V.
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 2.5 A to 7 A.
Added typical value for ICCDR parameter.
Updated Switching Characteristics:
Removed 35 ns speed bin.
Changed minimum value of tLZOE parameter from 3 ns to 5 ns.
Changed minimum value of tLZCE and tLZWE parameters from 6 ns to 10 ns.
Changed maximum value of tHZCE parameter from 22 ns to 18 ns.
Changed minimum value of tPWE parameter from 30 ns to 35 ns.
Changed minimum value of tSD parameter from 22 ns to 25 ns.
Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
Updated to new template.
*C
464503
05/25/2006 Updated Product Portfolio (Included Automotive Range).
Updated Operating Range (Included Automotive Range).
Updated Electrical Characteristics (Included Automotive Range).
Updated Data Retention Characteristics (Included Automotive Range).
Updated Switching Characteristics (Included Automotive Range).
Updated Ordering Information:
Updated part numbers.
*D
*E
485639
833080
07/21/2006 Updated Operating Range:
Replaced “2.2 V to 3.6 V” with “4.5 V to 5.5 V” in “VCC” column.
03/09/2007 Updated Electrical Characteristics:
Added SOIC package in “Test Conditions” of VIL parameter and also added corresponding
values.
Added Note 10 and referred the same note in maximum value of VIL parameter
corresponding to SOIC package.
Document Number: 38-05442 Rev. *S
Page 16 of 19
CY62148E MoBL
Document History Page (continued)
Document Title: CY62148E MoBL, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05442
Submission
Revision
ECN
Description of Change
Date
*F
890962
03/09/2007 Updated Pin Configurations:
Added Note 2 and referred the same note in Figure 1.
Updated Product Portfolio:
Included Automotive-A range and removed Automotive-E range.
Updated Operating Range:
Included Automotive-A range and removed Automotive-E range.
Updated Electrical Characteristics:
Included Automotive-A range and removed Automotive-E range.
Added Note 11 (related to ISB2) and referred the same note in ISB2 parameter.
Updated Data Retention Characteristics:
Included Automotive-A range and removed Automotive-E range.
Updated Switching Characteristics:
Included Automotive-A range and removed Automotive-E range.
Updated Ordering Information:
Updated part numbers.
*G
2947039
06/10/2010 Updated Truth Table:
Added Note 33 and referred the same note in “CE” column.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85095 – Changed revision from ** to *A.
spec 51-85081 – Changed revision from *B to *C.
Updated to new template.
*H
3006318
3235744
08/23/2010 Updated Data Retention Characteristics:
Added Note 14 and referred the same note in ICCDR parameter.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated to new template.
*I
04/20/2011 Updated Functional Description:
Removed “For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines.” at the end.
Updated Package Diagrams:
spec 51-85095 – Changed revision from *A to *B.
Completing Sunset Review.
*J
3302815
3539544
07/14/2011 Updated to new template.
*K
03/01/2012 Updated Electrical Characteristics:
Updated Note 10.
Updated Package Diagrams:
spec 51-85081 – Changed revision from *C to *D.
Completing Sunset Review.
*L
3992135
05/06/2013 Updated Functional Description:
Updated description.
Updated Electrical Characteristics:
Added one more Test Condition “VCC = 5.5 V, IOH = –0.1 mA” for VOH parameter and also
added corresponding values.
Updated Package Diagrams:
spec 51-85081 – Changed revision from *D to *E.
Completing Sunset Review.
Document Number: 38-05442 Rev. *S
Page 17 of 19
CY62148E MoBL
Document History Page (continued)
Document Title: CY62148E MoBL, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05442
Submission
Revision
ECN
Description of Change
Date
*M
4099045
08/19/2013 Updated Switching Characteristics:
Added Note 16 and referred the same note in “Parameter” column.
Updated to new template.
*N
4576526
11/21/2014 Updated Features:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 22 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 31 and referred the same note in Figure 8.
*O
*P
4794169
5285890
06/11/2015 Updated Package Diagrams:
spec 51-85095 – Changed revision from *B to *D.
Updated to new template.
06/01/2016 Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated all values in “32-pin SOIC Package” and “32-pin TSOP II Package” columns.
Updated Data Retention Characteristics:
Removed details in “Conditions” column corresponding to tR parameter (To match the speed
grade).
Updated to new template.
Completing Sunset Review.
*Q
6072272
02/15/2018 Updated Ordering Information:
Updated part numbers.
Updated to new template.
*R
*S
6533264
6906316
04/04/2019 Updated to new template.
Completing Sunset Review.
06/26/2020 Updated Features:
Changed value of Typical standby current from 1 µA to 2.5 µA.
Changed value of Typical active current from 2 mA to 3.5 mA.
Updated Product Portfolio:
Changed typical value of Operating ICC from 2 mA to 3.5 mA corresponding to all packages
and “f = 1 MHz”.
Changed maximum value of Operating ICC from 2.5 mA to 6 mA corresponding to all
packages and “f = 1 MHz”.
Changed typical value of Standby, ISB2 from 1 µA to 2.5 µA corresponding to all packages.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 2 mA to 3.5 mA corresponding to all speed
bins and Test Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2.5 mA to 6 mA corresponding to all speed
bins and Test Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 1 µA to 2.5 µA corresponding to all speed bins.
Changed typical value of ISB2 parameter from 1 µA to 2.5 µA corresponding to all speed bins.
Updated Data Retention Characteristics:
Changed typical value of ICCDR parameter from 1 μA to 3 μA.
Changed maximum value of ICCDR parameter from 7 µA to 8.8 µA.
Updated Package Diagrams:
spec 51-85081 – Changed revision from *E to *F.
Updated to new template.
Document Number: 38-05442 Rev. *S
Page 18 of 19
CY62148E MoBL
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© Cypress Semiconductor Corporation, 2004–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05442 Rev. *S
Revised June 26, 2020
Page 19 of 19
More Battery Life is a trademark and MoBL is a registered trademark of Cypress Semiconductor Corporation.
相关型号：
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Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.450 INCH, ROHS COMPLIANT, SOIC-32
CYPRESS
CY62148ESL-55ZAXAT
Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, LEAD FREE, STSOP-32
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