CY22801KFXCT [INFINEON]
Universal Programmable Clock Generator;型号: | CY22801KFXCT |
厂家: | Infineon |
描述: | Universal Programmable Clock Generator 时钟 光电二极管 外围集成电路 晶体 |
文件: | 总26页 (文件大小:774K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY22801
Universal Programmable Clock Generator
(UPCG)
Universal Programmable Clock Generator (UPCG)
Features
Functional Description
■ Integrated phase-locked loop (PLL)
■ Field-Programmable
The CY22801 is a flash-programmable clock generator that
supports various applications in consumer and communications
markets. The device uses the Cypress-proprietary PLL along
with Spread Spectrum and VCXO technology to make it one of
the most versatile clock synthesizers in the market. The device
uses a Cypress-proprietary PLL to drive up to three configurable
outputs in an 8-pin SOIC.
■ Input frequency range:
❐ Crystal: 8 MHz to 30 MHz
❐ CLKIN: 1 MHz to 133 MHz
■ Low-voltage complementary metal oxide semiconductor
(LVCMOS) output frequency:
❐ Up to 200 MHz (commercial grade)
❐ Up to 166.6 MHz (industrial grade)
The CY22801 is programmed with an easy-to-use programmer
dongle, the CY36800, in conjunction with the CyClocksRT™
software. This enables fast sample generation of prototype
builds for user-defined frequencies. Cypress’s value-added
distribution partners and third-party programming systems from
BP Microsystems, HiLo Systems, and others, can also be
contacted for large production quantities. A JEDEC file needs to
be configured to program CY22801, which can be generated
using the CyClocksRT™ software.
■ Special Features:
❐ Spread Spectrum
❐ VCXO
❐ Inputs: PD or OE, FS
■ Low-jitter, high-accuracy outputs
For a complete list of related documentation, click here.
■ 3.3 V operation
■ Commercial and industrial temperature ranges
■ 8-pin small-outline integrated circuit (SOIC) package
■ Serial interface for device configuration
Logic Block Diagram
XIN/CLKIN
VCXO
REF
with Logic
Divider
PLL
XOUT
SDAT/FS0/
VCXO/OE
/PD#
CLKA
1
VCXO
CLKB/
FS1/
SCLK
Switch
Matrix
Serial I/F
with
Control
FS2
SCLK
/FS1
SDAT
/FS0
/PD#
Divider
CLKC
/FS2
2
Logic
OE
Cypress Semiconductor Corporation
Document Number: 001-15571 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 3, 2018
CY22801
Contents
Pin Configurations ...........................................................3
Pin Definitions ..................................................................3
External Reference Crystal/Clock Input .........................4
Output Clock Frequencies ...............................................4
VCXO .................................................................................4
VCXO Profile ...............................................................4
Spread Spectrum Clock Generation (SSCG) .................4
Spread Percentage .....................................................4
Modulation Frequency .................................................4
SSON Pin ....................................................................4
Multifunction Pins ............................................................5
Frequency Calculation and Register Definitions ...........5
Default Startup Condition for the CY22801 ....................6
Frequency Calculations and Register Definitions
using the Serial (I2C) Interface ........................................6
Reference Frequency ..................................................6
Programmable Crystal Input Oscillator
Gain Settings ......................................................................6
Using an External Clock as the Reference Input .........7
Input Load Capacitors .................................................8
PLL Frequency, Q Counter [42H(6..0)] .......................8
PLL Frequency, P Counter
[40H(1..0)], [41H(7..0)], [42H(7)] .........................................9
PLL Post Divider Options [0CH(7..0)], [47H(7..0)] .......9
Charge Pump Settings [40H(2..0)] ..............................9
Clock Output Settings: CLKSRC
CyClocksRT Software ....................................................12
Possible Configuration Examples ................................12
Informational Graphs .....................................................13
Absolute Maximum Conditions .....................................14
Recommended Operating Conditions ..........................14
Recommended Crystal Specifications
for non-VCXO Applications ...........................................14
Pullable Crystal Specifications
for VCXO Application only .............................................14
DC Electrical Specifications ..........................................15
AC Electrical Characteristics ........................................16
Test Circuit ......................................................................17
Timing Definitions ..........................................................17
2-wire Serial (I2C) Interface Timing ...............................18
Data Valid ..................................................................18
Data Frame ...............................................................18
Acknowledge Pulse ...................................................18
Ordering Information ......................................................20
Possible Configurations .............................................20
Ordering Code Definitions .........................................20
Package Diagram ............................................................21
Acronyms ........................................................................22
Document Conventions .................................................22
Units of Measure .......................................................22
Document History Page .................................................23
Sales, Solutions, and Legal Information ......................26
Worldwide Sales and Design Support .......................26
Products ....................................................................26
PSoC® Solutions ......................................................26
Cypress Developer Community .................................26
Technical Support .....................................................26
– Clock Output Crosspoint Switch Matrix
[44H(7..0)], [45H(7..0)], [46H(7..6)] ...................................10
Test, Reserved, and Blank Registers ........................10
Application Guideline .....................................................12
Best Practices for Best Jitter Performance ................12
Field Programming the CY22801 ..................................12
Document Number: 001-15571 Rev. *M
Page 2 of 26
CY22801
Pin Configurations
Figure 1. CY22801 8-pin SOIC pinout
XIN/CLKIN
XOUT
8
1
VDD
SDAT/FS0/
CLKC/FS2
CLKA
7
6
5
2
3
4
CY22801
VCXO/OE/PD#
CLKB/FS1/SCLK
VSS
Pin Definitions
Name
Pin Number
Description
CLKIN /
XIN
1
External reference crystal input / external reference clock input
VDD
2
3
3.3 V voltage supply
SDAT / FS0
/ VCXO /
Serial interface data line / frequency select 0 / VCXO analog control voltage / Output Enable /
Power-down
OE / PD#
VSS
4
5
Ground
CLKB/FS1
/ SCLK
Clock output B / frequency select 1 / serial interface clock line
CLKA
6
7
Clock output A
CLKC /
FS2
Clock output C / frequency select 3 / VSS
XOUT
8
External reference crystal output: Connect to external crystal. When the reference is an external clock
signal (applied to pin 1), this pin is not used and must be left floating.
Document Number: 001-15571 Rev. *M
Page 3 of 26
CY22801
VCXO is not compatible with Spread spectrum and Serial
Interface.
External Reference Crystal/Clock Input
CY22801 can accept external reference clock input as well as
crystal input. External reference clock input frequency range is
from 1 MHz to 133 MHz.
VCXO Profile
Figure 3 shows an example of a VCXO profile. The analog
voltage input is on the X-axis and the PPM range is on the Y-axis.
An increase in the VCXO input voltage results in a corresponding
increase in the output frequency. This moves the PPM from a
negative to positive offset.
The input crystal oscillator of the CY22801 is an important
feature because of the flexibility it provides in selecting a crystal
as a reference clock source. The oscillator inverter has
programmable gain, enabling maximum compatibility with a
reference crystal, based on manufacturer, process,
performance, and quality.
Figure 3. VCXO Profile
Input load capacitors are placed on the CY22801 die to reduce
external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency shift
that occurs when non-linear load capacitance is affected by load,
bias, supply, and temperature changes.
200
150
100
50
0
The value of the input load capacitors is determined by eight bits
in a programmable register. Total load capacitance is determined
by the formula:
0
0.5
1
1.5
2
2.5
3
3.5
-50
-100
-150
-200
CapLoad = (CL – CBRD – CCHIP) / 0.09375 pF
In CyClocksRT, enter the crystal capacitance (CL). The value of
CapLoad is determined automatically and programmed into the
CY22801.
VCXOinput [V]
Output Clock Frequencies
Spread Spectrum Clock Generation (SSCG)
The CY22801 is a very flexible clock generator with up to three
individual outputs, generated from an integrated PLL. See
Figure 2 for details.
Spread spectrum clock generation (SSCG) in CY22801 helps to
reduce EMI found in today’s high-speed digital electronic
systems.
The output of the PLL runs at high frequency and is divided down
to generate the output clocks. Two programmable dividers are
available for this purpose. Therefore, although the output clocks
may have different frequencies, they must be related, based on
the PLL frequency.
The device uses the proprietary spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the
input clock. By modulating the frequency of the clock, the
measured EMI at the fundamental and harmonic frequencies is
greatly reduced. This reduction in radiated energy can
significantly reduce the cost of complying with the regulatory
agency electromagnetic compatibility (EMC) requirements and
improve time to market without degrading system performance.
It is also possible to direct the reference clock input to any of the
outputs, thereby bypassing the PLL. Lastly, the reference clock
may be passed through either divider.
Figure 2. Basic PLL Block Diagram
Programmed spread spectrum modulation will appear same on
all three clock outputs as they come from same PLL even if
operating at different frequencies. Spread spectrum is not
compatible with VCXO feature.
Post
Divider
1N
REF
(XIN/CLKIN)
/Q
PFD
VCO
CLKA
CLKB
CLKC
Crosspoint
Switch
Matrix
/P
Post
Divider
2N
Spread Percentage
The percentage of spread can be programmed from ±0.25% to
±2.5% for center spread and from –0.5% to –5.0% for down
spread. The granularity is 0.25%.
Modulation Frequency
The default modulation frequency is 31.5 kHz. Other modulation
frequencies available through configuration software are
30.1 kHz and 32.9 kHz.
VCXO
One of the key components of the CY22801 device is the VCXO.
The VCXO is used to ‘pull’ the reference crystal higher or lower
to lock the system frequency to an external source. This is ideal
for applications where the output frequency needs to track along
with an external reference frequency that is constantly shifting.
SSON Pin
SSON pin functionality can be used to turn Spread ON and OFF
in clock output. Any one of the Multifunction pins can be
configured as SSON pin.
A special pullable crystal must be used to have adequate VCXO
pull range. Pullable crystal specifications are included in this
data sheet.
Document Number: 001-15571 Rev. *M
Page 4 of 26
CY22801
Multifunction Pins
Table 2. Possible Combinations for Multifunction Pins
There are three pins [1] with multiple functions either as control
pins or as output pins. The following are the acronyms used for
the different control function pins:
Possible Combinations
Pin#3
FS0
Pin#5
CLKB
CLKB
FS1
Pin#7
CLKC
FS2
A
B
C
D
E
F
■ Output enable (OE): If OE = 1, all outputs are enabled
FS0
■ Frequency select (FS0, 1, 2): These pins can be used to select
one of the programmed clock frequencies for clock output. All
of three multifunction pins support this functionality. Any of
these pins can also be configured as Spread spectrum ON
(SSON) pin. If SSON = 1, clock output has programmed
spread; if SSON = 0, clock output does not have spread.
FS0
FS2
OE / PD#
OE / PD#
OE / PD#
SDAT
CLKB
FS1
CLKC
CLKC
FS2
FS1
G
H
SCLK
CLKB
CLKC
CLKC
■ Power-down: active low (PD#): If PD# = 0, all outputs are
tristated and the device enters in the low-power state
VCXO
■ Voltage controlled crystal oscillator (VCXO): Analog voltage on
this pin controls the output frequency of oscillator
Frequency Calculation and Register
Definitions
■ Serial interface clock line (SCLK) and serial interface data line
(SDAT): These pins are for serial interface and are compatible
with I2C.
The CY22801 is an extremely flexible clock generator with four
basic variables that are used to determine the final output
frequency. They are the input reference frequency (REF), the
internally calculated P and Q dividers, and the post divider, which
can be a fixed or calculated value. There are three formulas to
determine the final output frequency of a CY22801 based
design:
Each of these three multi-function pins supports selected
functions mentioned in Table 1. One of the supported functions
can be programmed on the pin at a time.
Table 1. Multi Function Pin Options
CLK
■ CLK = ((REF × P) / Q) / Post divider
■ CLK = REF / Post divider
■ CLK = REF
Pin#
Pin Name
OE PD# VCXO FS
I2C
OUTPUT
3
SDAT / FS0 /
VCXO / OE /
PD#
Y
Y
Y[2] Y[3]
N[4]
SDAT[2]
The basic PLL block diagram is shown in Figure 4 on page 6.
Each of the three clock outputs on the CY22801 has a total of
seven output options available to it. There are six post divider
options available: /2 (two of these), /3, /4, /DIV1N and /DIV2N.
DIV1N and DIV2N are independently calculated and are applied
to individual output groups. The post divider options can be
applied to the calculated VCO frequency ((REF × P) / Q) or to
the REF directly.
5
7
CLKB / FS1 /
SCLK
N
N
N
N
N
N
Y
Y
Y
SCLK
N
CLKC / FS2
Y[5]
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the REF directly to the
crosspoint switch matrix.
Notes
1. There are Weak Pull up resistors (approximately 100 k) on all Multifunctional pins.
2. VCXO and SSON functions as well as VCXO and Serial Interface functions are not compatible.
3. ‘Y’ means pin supports this function.
4. ‘N’ means pin does not support this function.
5. Do not use this pin as Reference Clock Output.
Document Number: 001-15571 Rev. *M
Page 5 of 26
CY22801
Figure 4. Basic Block Diagram of CY22801 PLL
CLKSRC
Crosspoint
Switch Matrix
DIV1N[0CH]
DIV1SRC[0CH]
Qtotal
Divider Bank 1
/DIV1N
/2
REF
(Q+2)
PFD
VCO
[45H]
[44H, 45H]
[45H, 46H]
CLKA
[42H]
/3
Ptotal
(2(PB+4)+PO)
Divider Bank 2
/DIV2N
CLKB
CLKC
[40H, 41H, 42H]
/4
/2
DIV2SRC[47H]
DIV1N[47H]
CLKOE[09H]
All programmable registers in the CY22801 are addressed with
eight bits and contain eight bits of data. The CY22801 is a slave
device with an address of 1101001 (69H).
Table 3 on page 7 lists the I2C registers and their definitions.
Specific register definitions and their allowable values are listed
as follows.
Default Startup Condition for the CY22801
The default (programmed) condition of the device is generally set
by the distributor who programs the device using a customer
specific JEDEC file produced by CyClocksRT. Parts shipped
from the factory are blank and unprogrammed. In this condition,
all bits are set to 0, all outputs are three-stated, and the crystal
oscillator circuit is active.
Reference Frequency
While you can develop your own subroutine to program any or
all of the individual registers described in the following pages, it
may be easier to use CyClocksRT to produce the required
The REF can be a crystal or a driven frequency (CLKIN). For
crystals, the frequency range must be between 8 MHz and
30 MHz. For a driven frequency, the frequency range must be
between 1 MHz and 133 MHz.
register setting file [6]
.
The serial interface address of the CY22801 is 69H. If there is a
conflict with any other devices in your system, then this can also
Programmable Crystal Input Oscillator Gain Settings
be changed [7, 8]
.
The Input crystal oscillator gain (XDRV) is controlled by two bits
in register 12H and are set according to Table 4 on page 8. The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
manufacturer), and the CapLoad setting during crystal startup.
Frequency Calculations and Register
2
Definitions using the Serial (I C) Interface
The CY22801 provides an industry standard serial interface for
volatile, in-system programming of unique frequencies and
options. Serial programming and re-programming allows for
quick design changes and product enhancements, eliminates
inventory of old design parts, and simplifies manufacturing.
Bits 3 and 4 of register 12H control the input crystal oscillator gain
setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The
setting is programmed according to Table 4 on page 8. All other
bits in the register are reserved and should be programmed as
shown in Table 5 on page 8.
The I2C Interface provides volatile programming. This means
when the target system is powered down, the CY22801 reverts
to its pre-I2C state, as defined above (programmed or
unprogrammed). When the system is powered back up again,
the I2C registers must be reconfigured again.
FTAAddrSrc[1:0] bits set Frequency tuning array address
source. This will be set by CyClockRT software based on
selected configuration.
Notes
6. Advanced features like VCXO, SCL, SDA, FS, OE, SSON are not supported by CyClocksRT. Contact your local Cypress field application engineer for functional
feasibility and custom configuration with these advanced features.
7. Please Contact your local Cypress FAE, if you need serial interface address other than 69H.
8. while configuring Jedec through CyClocksRT software, if Pin3 (SDAT) and Pin5 (SCLK) is not configured for any functionality, the jedec file automatically gets configured
with I2C Enable Functionality with default I2C address as 69 H.
Document Number: 001-15571 Rev. *M
Page 6 of 26
CY22801
Using an External Clock as the Reference Input
The CY22801 also accepts an external clock as reference, with speeds up to 133 MHz. With an external clock, the XDRV (register 12H) bits must be set according to Table
6 on page 8.
Table 3. Summary Table – CY22801 Programmable Registers
Register
09H
Description
CLKOE control
D7
0
D6
0
D5
D4
D3
0
D2
D1
0
D0
0
CLKC
CLKA
CLKB
OCH
DIV1SRC mux and DIV1N
divider
DIV1SRC
DIV1N (6)
DIV1N (5)
DIV1N (4)
DIV1N (3)
DIV1N (2)
DIV1N (1)
DIV1N (0)
12H
Inputcrystaloscillatordrive FTAAddrSrc[1] FTAAddrSrc[0]
control
XCapSrc
XDRV (1)
XDRV (0)
0
0
0
13H
40H
41H
42H
44H
Input load capacitor control CapLoad (7)
CapLoad (6)
CapLoad (5)
CapLoad (4)
Pump (2)
PB (4)
Q (4)
CapLoad (3)
Pump (1)
PB (3)
Q (3)
CapLoad (2)
Pump (0)
PB (2)
Q (2)
CapLoad (1)
PB (9)
CapLoad (0)
PB (8)
Charge pump and PB
counter
1
PB (7)
PO
1
PB (6)
Q (6)
1
0
PB (5)
Q (5)
1
PB (1)
PB (0)
PO counter, Q counter
Q (1)
Q (0)
Crosspoint switch matrix
control
1
1
1
1
CLKSRC2 for CLKSRC1 for
CLKB CLKB
45H
46H
47H
CLKSRC0 for
CLKB
1
1
1
1
1
CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for
CLKA
CLKA
CLKA
CLKC
CLKSRC1 for CLKSRC0 for
1
1
1
1
CLKC
CLKC
DIV2SRC mux and DIV2N
divider
DIV2SRC
DIV2N(6)
DIV2N(5)
DIV2N(4)
DIV2N(3)
DIV2N(2)
DIV2N(1)
DIV2N(0)
Document Number: 001-15571 Rev. *M
Page 7 of 26
CY22801
Table 4. Programmable Crystal Input Oscillator Gain Settings
Cap Register Settings
00H–80H
80H–C0H
C0H–FFH
18 pF to 30 pF
Effective Load Capacitance
(CapLoad)
6 pF to 12 pF
12 pF to 18 pF
Crystal ESR
8 to 15 MHz
15 to 20 MHz
20 to 25 MHz
25 to 30 MHz
30
00
60
01
30
01
60
10
30
01
60
10
Crystal input
frequency
01
01
10
10
10
10
01
10
10
10
10
10
10
11
10
11
11
N/A
Table 5. Crystal Oscillator Gain Bit Locations and Values
Address
D7
D6
D5
D4
D3
XDRV(0)
D2
D1
D0
12H
0
0
1
XDRV(1)
0
0
0
Table 6. Programmable External Reference Input Oscillator Drive Settings
Reference Frequency
Drive Setting
1 to 25 MHz
00
25 to 50 MHz
01
50 to 90 MHz
10
90 to 133 MHz
11
In CyClocksRT, enter the crystal capacitance (C ). The value of
Input Load Capacitors
L
CapLoad is determined automatically and programmed into the
CY22801. Through the SDAT and SCLK pins, the value can be
adjusted up or down if your board capacitance is greater or less
than 2 pF. For an external clock source, CapLoad defaults to 0.
See Table 7 on page 9 for CapLoad bit locations and values.
XCapSrc bit in 12H register selects the source of Input load
capacitance. This will be set by CyClockRT software based on
selected configuration.
Input load capacitors allow you to set the load capacitance of the
CY22801 to match the input load capacitance from a crystal. The
value of the input load capacitors is determined by 8 bits in a
programmable register [13H]. Total load capacitance is
determined by the formula:
The input load capacitors are placed on the CY22801 die to
reduce external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency shift
that occurs when nonlinear load capacitance is affected by load,
bias, supply, and temperature changes.
CapLoad = (C – C
– C
) / 0.09375 pF
L
BRD
CHIP
where:
PLL Frequency, Q Counter [42H(6..0)]
■ C = specified load capacitance of your crystal.
L
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7 bit divider with a
maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2 is
added to this register value to achieve the total Q, or Q . Q
■ C
BRD
= the total board capacitance, due to external capacitors
and board trace capacitance. In CyClocksRT, this value
defaults to 2 pF.
■ C
CHIP
= 6 pF.
total
total
is defined by the formula:
■ 0.09375 pF = the step resolution available due to the 8-bit
register.
Q
= Q + 2
total
The minimum value of Q
is 2. The maximum value of Q
is
In CyclocksRT, only the crystal capacitance (C ) is specified.
total
total
L
129. Register 42H is defined in the table.
Stable operation of the CY22801 cannot be guaranteed if
REF/Q falls below 250 kHz. Q bit locations and values are
C
is set to 6 pF and C
defaults to 2 pF. If your board
CHIP
BRD
capacitance is higher or lower than 2 pF, the formula given earlier
is used to calculate a new CapLoad value and programmed into
register 13H.
total
total
defined in Table 8 on page 9.
Document Number: 001-15571 Rev. *M
Page 8 of 26
CY22801
output frequency. The mux determines if the clock signal feeding
into the divider banks is the calculated VCO frequency or REF.
There are two select muxes (DIV1SRC and DIV2SRC) and two
divider banks (Divider Bank 1 and Divider Bank 2) used to
determine this clock signal. The clock signal passing through
DIV1SRC and DIV2SRC is referred to as DIV1CLK and
DIV2CLK, respectively.
PLL Frequency, P Counter [40H(1..0)], [41H(7..0)],
[42H(7)]
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Q
VCO frequency. The product counter, defined as P
) value to achieve the
total
, is made
total
up of two internal variables, PB and PO. The formula for
calculating P is:
total
The divider banks have four unique divider options available: /2,
/3, /4, and /DIVxN. DIVxN is a variable that can be independently
programmed (DIV1N and DIV2N) for each of the two divider
banks. The minimum value of DIVxN is 4. The maximum value
of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to
work properly.
P
= (2(PB + 4) + PO)
total
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings. The three MSBs of register 40H are
preset and reserved and cannot be changed. PO is a single bit
variable, defined in register 42H(7). This allows for odd numbers
DIV1SRC is a single bit variable, controlled by register 0CH. The
remaining seven bits of register 0CH determine the value of post
divider DIV1N.
in P
.
total
The remaining seven bits of 42H are used to define the
Q counter, as shown in Table 8.
DIV2SRC is a single bit variable, controlled by register 47H. The
remaining seven bits of register 47H determine the value of post
divider DIV2N.
The minimum value of P
is 8. The maximum value of P
is
total
total
2055. To achieve the minimum value of P
, PB and PO should
total
Register 0CH and 47H are defined in Table 9.
both be programmed to 0. To achieve the maximum value of
, PB should be programmed to 1023, and PO should be
Charge Pump Settings [40H(2..0)]
P
total
programmed to 1.
The correct pump setting is important for PLL stability. Charge
pump settings are controlled by bits (4..2) of register 40H, and
are dependent on internal variable PB (see “PLL Frequency, P
Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 10 on page 10
summarizes the proper charge pump settings, based on Ptotal.
Stable operation of the CY22801 cannot be guaranteed if the
value of (P
× (REF/Q )) is above 400 MHz or below
total
total
100 MHz.
PLL Post Divider Options [0CH(7..0)], [47H(7..0)]
See Table 11 on page 10 for register 40H bit locations and
values.
The output of the VCO is routed through two independent
muxes, then to two divider banks to determine the final clock
Table 7. Input Load Capacitor Register Bit Settings
Address
D7
D6
D5
D4
D3
D2
D1
D0
13H
CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0)
Table 8. P Counter and Q Counter Register Definition
Address
40H
D7
1
D6
1
D5
0
D4
Pump(2)
PB(4)
Q(4)
D3
Pump(1)
PB(3)
Q(3)
D2
Pump(0)
PB(2)
Q(2)
D1
D0
PB(9)
PB(1)
Q(1)
PB(8)
PB(0)
Q(0)
41H
PB(7)
PO
PB(6)
Q(6)
PB(5)
Q(5)
42H
Table 9. PLL Post Divider Options
Address
0CH
D7
D6
D5
D4
D3
D2
D1
D0
DIV1SRC
DIV2SRC
DIV1N(6)
DIV2N(6)
DIV1N(5)
DIV2N(5)
DIV1N(4)
DIV2N(4)
DIV1N(3)
DIV2N(3)
DIV1N(2)
DIV2N(2)
DIV1N(1)
DIV2N(1)
DIV1N(0)
DIV2N(0)
47H
Document Number: 001-15571 Rev. *M
Page 9 of 26
CY22801
Table 10. Charge Pump Settings
Charge Pump Setting – Pump(2..0)
Calculated Ptotal
000
001
16–44
45–479
480–639
010
011
640–799
100
800–1023
101, 110, 111
Do not use – device will be unstable
Table 11. Register 40H Change Pump Bit Settings
Address
D7
D6
D5
D4
D3
D2
D1
D0
40H
1
1
0
Pump(2)
Pump(1)
Pump(0)
PB(9)
PB(8)
Although using the above table guarantees stability, it is
recommended to use the Print preview function in CyClocksRT
to determine the correct charge pump settings for optimal jitter
performance.
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1).
When DIV2N is divisible by four, then CLKSRC(1,0,1) is
guaranteed to be rising edge phase-aligned with
CLKSRC(1,0,0). When DIV2N is divisible by eight, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
PLL stability cannot be guaranteed for values below 16 and
above 1023. If values above 1023 are needed, use CyClocksRT
to determine the best charge pump setting. To configure device
using serial interface, please refer CyClocksRT.
CLKOE – Clock Output Enable Control [09H(5..0)]
Clock Output Settings: CLKSRC – Clock Output
Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)],
[46H(7..6)]
Each clock output has its own output enable, controlled by
register 09H(5..0). To enable an output, set the corresponding
CLKOE bit to 1. CLKOE settings are in Table 14 on page 11.
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint switch
matrix defines which source is attached to each individual clock
output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H.
The remainder of register 46H(5:0) must be written with the
values stated in the register table when writing register values
46H(7:6).
Test, Reserved, and Blank Registers
Writing to any of the following registers causes the part to exhibit
abnormal behavior, as follows.
[00H to 08H]
[0AH to 0BH]
[0DH to 11H]
[14H to 3FH]
[43H]
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved.
When DIV1N is divisible by four, then CLKSRC(0,1,0) is
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is
[48H to FFH]
Table 12. Clock Output Setting
CLKSRC2 CLKSRC1 CLKSRC0
Definition and Notes
0
0
0
0
0
1
Reference input.
DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4
to 127. If Divider Bank 1 is not being used, set DIV1N to 8.
0
0
1
1
1
0
0
1
0
DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.
DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.
DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4
to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
1
1
1
0
1
1
1
0
1
DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.
DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.
Reserved – do not use.
Document Number: 001-15571 Rev. *M
Page 10 of 26
CY22801
Table 13. Clock Output Register Setting
Address
D7
D6
D5
D4
D3
D2
D1
D0
44H
1
1
1
1
1
1
CLKSRC2
for CLKB
CLKSRC1
for CLKB
45H
46H
CLKSRC0
for CLKB
1
1
1
1
1
CLKSRC2
for CLKA
CLKSRC1
for CLKA
CLKSRC0
for CLKA
CLKSRC2
for CLKC
CLKSRC1
for CLKC
CLKSRC0
for CLKC
1
1
1
1
Table 14. CLKOE Bit Setting
Address
D7
D6
D5
D4
D3
D2
D1
D0
09H
0
0
CLKC
CLKA
0
CLKB
0
0
Document Number: 001-15571 Rev. *M
Page 11 of 26
CY22801
Application Guideline
Field Programming the CY22801
The CY22801 is programmed using the CY36800 USB
programmer dongle. The CY22801 is flash-technology based, so
the parts are reprogrammed up to 100 times. This enables fast
and easy design changes and product updates, and eliminates
any issues with old and out-of-date inventory.
Best Practices for Best Jitter Performance
Jitter can be specified in different terminologies:
Time Domain:
■ Cycle-to-cycle jitter
■ Period jitter
Samples and small prototype quantities are programmed using
the CY36800 programmer. Cypress’s value-added distribution
partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others, can also be contacted
for large production quantities. Third-Party Programmer List can
be found at below link http://www.cypress.com/?rID=14364.
■ Long-term jitter
Frequency domain:
■ Deterministic jitter
■ Random jitter
■ Phase noise
CyClocksRT Software
CyClocksRT is an easy-to-use software application that enables
the user to custom-configure the CY22801. Users can specify
the XIN/CLKIN frequency, crystal load capacitance, and output
These jitter terms are usually given in terms of root mean square
(RMS), peak-to-peak, or in the case of phase noise, dBC/Hz with
respect to fundamental frequency. Cycle-to-cycle and period
jitter are generally used terminologies. Jitter depends on many
factors and few of the them can be controlled in application:
frequencies. CyClocksRT then creates an industry-standard
[6]
JEDEC file that is used to program the CY22801
.
When needed, an advanced mode is available that enables
users to override the automatically generated voltage controlled
oscillator (VCO) frequency and output divider values.
■ Input reference jitter
■ Number of active clock outputs
■ Operating temperature
■ Clock output load
CyClocksRT is a component of the CyberClocks™ software that
you can download free of charge from the Cypress website at
http://www.cypress.com.
CY36800 InstaClock™ Kit
■ PLL frequencies
The Cypress CY36800 InstaClock kit comes with everything
needed to design the CY22801 and program samples and small
prototype quantities. The CyClocksRT software is used to
quickly create a JEDEC programming file, which is then
downloaded directly to the portable programmer that is included
in the CY36800 InstaClock kit. The JEDEC file can also be saved
for use in a production programming system for larger volumes.
■ Termination and layout
■ Supply voltage accuracy
Jitter is directly proportional to the input reference jitter, number
of active clock outputs, operating temperature and clock output
load, but inversely proportional to the PLL frequency. Best
practices for termination, layout and supply voltage filtering are
discussed in application note “Layout and Termination
Techniques For Cypress Clock Generators – AN1111”.
The CY36800 also comes with five samples of the CY22801,
which are programmed with preconfigured JEDEC files using the
InstaClock software.
Possible Configuration Examples
Table 15. Possible Configuration
Possible Configurations
Pin#1
Pin#3
Pin#5
Pin#6
Pin#7
Pin#8
A
CLKIN: 33 MHz
OE
CLKB: 33 MHz
CLKA:
100 MHz with
+/-1% Spread
SSON
NC
B
C
XIN: 27 MHz
crystal
VCXO
OE
PD#
FS1
CLKA: 74.25 /
74.175824 MHz
FS2
FS2
XOUT: 27 MHz
crystal
CLKIN: 10 MHz
CLKA: 25 / 40 /
33.3333 /
NC
50 MHz
D
CLKIN: 10 MHz
SDAT
SCLK
CLKA
CLKB
NC
Contact your local Cypress field application engineer for functional feasibility and custom configuration with these advanced features.
Document Number: 001-15571 Rev. *M
Page 12 of 26
CY22801
Informational Graphs
The informational graphs are meant to convey the typical performance levels. No performance specifications is implied or guaranteed.
172.5
171.5
68.5
68
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= -4%
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= -4%
170.5
169.5
67.5
67
168.5
167.5
166.5
66.5
66
Fnominal
Fnominal
165.5
164.5
163.5
162.5
65.5
65
64.5
64
161.5
160.5
159.5
63.5
0
20
40
60
80
100
120
140 160
180
200
Time (us)
0
20
40
60
80
100
120
140 160 180
200
Time (us)
169.5
169
168.5
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= +/-1%
67.5
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= +/-1%
67
66.5
66
168
167.5
167
166.5
Fnominal
Fnominal
166
165.5
65.5
165
164.5
164
65
163.5
163
64.5
162.5
0
20
40
60 80
100 120 140 160 180 200
Time (us)
0
20
40
60
80
100 120 140
Time (us)
160 180 200
Document Number: 001-15571 Rev. *M
Page 13 of 26
CY22801
Absolute Maximum Conditions
Parameter
Description
Min
–0.5
–65
–
Max
4.6
Unit
V
V
Supply voltage
DD
S
T
T
Storage temperature
Junction temperature
Input and output voltage
150
125
°C
°C
V
J
V
V
– 0.5
V
+ 0.5
IO
SS
DD
ESD
Electrostatic discharge voltage per MIL-STD-833, Method 3015
2000
–
V
Recommended Operating Conditions
Parameter
Description
Min
3.14
0
Typ
3.3
–
Max
3.47
70
Unit
V
V
Operating voltage
DD
T
Ambient temperature, commercial grade
Ambient temperature, industrial grade
Maximum load capacitance on the CLK output
°C
°C
pF
ms
A
–40
–
--
85
C
–
15
LOAD
t
Power-up time for V to reach the minimum specified voltage (power
0.05
–
500
PU
DD
ramps must be monotonic)
Recommended Crystal Specifications for non-VCXO Applications
Parameter
Name
Description
Min
Typ
Max
Unit
F
Nominal crystal frequency
Parallel resonance, fundamental mode,
and AT cut
8
–
30
MHz
NOM
C
R
Nominal load capacitance
6
–
–
30
50
pF
LNOM
Equivalent series resistance Fundamental mode
(ESR)
35
1
DL
Crystal drive level
No external series resistor assumed
–
0.5
2
mW
Pullable Crystal Specifications for VCXO Application only
[9]
Parameter
Name
Min
Typ
14
–
Max
–
Unit
pF
C
Crystal load capacitance
–
–
3
LNOM
1
R
Equivalent series resistance
25
–
R /R
Ratio of third overtone mode ESR to fundamental mode ESR. Ratio is
–
–
3
1
used because typical R values are much less than the maximum spec.
1
DL
Crystal drive level. No external series resistor assumed
–
300
–
0.5
–
2
–
mW
ppm
ppm
pF
F
F
Third overtone separation from 3 × F
Third overtone separation from 3 × F
Crystal shunt capacitance
(high side)
(low side)
3SEPHI
3SEPLO
NOM
NOM
–
–150
7
C0
C0/C1
Ratio of shunt to motional capacitance
Crystal motional capacitance
180
–
250
21.6
C
14.4
18
fF
1
Note
9. Crystals that meet this specification include Ecliptek ECX-5788-13.500M, Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL, and PDI HA13500XFSA14XC.
Document Number: 001-15571 Rev. *M
Page 14 of 26
CY22801
DC Electrical Specifications
[10]
Parameter
Name
Output high current
Output low current
Input capacitance
Input capacitance
Description
= V – 0.5, V = 3.3 V (source)
Min
12
12
–
Typ
24
24
–
Max
Unit
mA
mA
pF
I
V
V
–
–
7
–
OH
OL
OH
OL
DD
DD
I
= 0.5, V = 3.3 V (sink)
DD
C
All input pins except XIN and XOUT
IN1
IN2
C
XIN and XOUT pins for non-VCXO
applications
–
24
pF
I
Input high current
Input low current
VCXO pullability range
VCXO input range
Input high voltage
Input low voltage
V
V
= V
DD
–
–
5
–
10
50
A
A
ppm
V
IH
IH
IL
I
= 0 V
IL
fXO
Using crystal in this data sheet
±150
0
–
V
V
V
–
V
DD
VCXO
IH
CMOS levels, 70% of V
CMOS levels, 30% of V
0.7 × V
–
–
0.3 × V
–
V
DD
DD
DD
–
–
–
V
IL
DD
[11]
V
supply current
All three clock outputs are at 100 MHz
30
mA
I
DD
DD
Notes
10. Not 100% tested, guaranteed by design.
11. Power supply current is configuration dependent. Use CyClocksRT to calculate actual I for specific output frequency configurations.
DD
Document Number: 001-15571 Rev. *M
Page 15 of 26
CY22801
AC Electrical Characteristics
[12]
Parameter
Name
Description
Min
8
Typ
–
Max
30
Unit
MHz
MHz
MHz
f
Reference frequency - crystal
Reference frequency - driven
REFC
REFD
OUT
f
f
1
–
133
200
Output frequency, commercial
grade
–
–
Output frequency, industrial
grade
–
–
166.6
MHz
DC
Output duty cycle
50% of V
see Figure 6
45
50
55
–
%
DD,
t
Rising edge slew rate
Output clock rise time, 20%–80% of
see Figure 7
0.8
1.4
V/ns
3
V
DD,
t
Falling edge slew rate
Skew
Output clock fall time, 80%–20% of
see Figure 7
0.8
–
1.4
–
–
V/ns
ps
4
V
DD,
[13]
[14]
Output-output
skew
between
250
–
t
t
5
related outputs, see Figure 9
Clock jitter
Peak-to-peak period jitter, see
Figure 8
–
250
–
ps
6
[14]
tCCJ
Cycle-to-cycle jitter CLKA/B/C
XIN = CLKA/B/C = 166 MHz,
±2% spread and No REFOUT,
–
110
ps
V
DD = 3.3 V, see Figure 10
XIN = CLKA/B/C = 66.66 MHz,
±2% spread and No REFOUT,
–
–
–
–
–
–
–
–
170
140
290
300
300
300
ps
ps
ps
ns
ns
ns
V
DD = 3.3 V, see Figure 10
XIN = CLKA/B/C = 33.33 MHz,
±2% spread and No REFOUT,
V
DD = 3.3 V, see Figure 10
XIN = CLKA/B/C = 14.318 MHz,
±2% spread and No REFOUT,
–
V
DD = 3.3 V, see Figure 10
tPD
Power-down time
Output disable time
Output enable time
Time from falling edge on PD# pin to
tristated outputs (asynchronous),
see Figure 11
150
150
150
tOE1
Time from falling edge on OE pin to
tristated outputs (asynchronous),
see Figure 12
tOE2
Time from rising edge on OE pin to
valid clock outputs (asynchronous),
see Figure 12
FMOD
Spread spectrum modulation
frequency
30.1
–
31.5
–
32.9
3
kHz
ms
t
PLL lock time
10
Notes
12. Not 100% tested, guaranteed by design.
13. Skew value guaranteed when outputs are generated from the same divider bank.
14. Jitter measurement may vary. Actual jitter is dependent on input jitter and edge rate, number of active outputs, input and output frequencies, supply voltage,
temperature, and output load.
Document Number: 001-15571 Rev. *M
Page 16 of 26
CY22801
Test Circuit
Figure 5. Test Circuit Diagram
V
CLKout
DD
C
0.1F
LOAD
Output
GND
Timing Definitions
Figure 6. Duty Cycle Definition; DC = t2/t1
Figure 7. Rise and Fall Time Definitions
t3 t4
t1
t2
80%
50%
CLK
CLK
50%
20%
Figure 8. Period Jitter Definition
Figure 9. Skew Definition
t5
t6
50%
CLKx
CLK
50%
CLKy
50%
Figure 10. Cycle to Cycle Jitter Definition (CCJ)
Figure 11. Power-Down and Power-Up Timing
TCycle_i
TCycle_i+1
VIH
POWER
DOWN
tPU
VIL
50%
High
CLK
Impedance
CLK
tPD
t
CCJ = TCycle_i - TCycle_i+1 (over 1000 Cycles)
Figure 12. Output Enable and Disable Timing
VIH
OUTPUT
ENABLE
tOE2
VIL
High
CLK
Impedance
tOE1
Document Number: 001-15571 Rev. *M
Page 17 of 26
CY22801
2
Start Sequence – Start frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a Start signal is given, the next
eight-bit data must be the device address (seven bits) and a R/W
bit, followed by the register address (eight bits) and register data
(eight bits).
2-wire Serial (I C) Interface Timing
2
When using I C interface, the CY22801 should be programmed
as I C-capable prior to using this interface.
2
The CY22801 uses a 2-wire serial-interface SDAT and SCLK
that operates up to 400 kbits/second in read or write mode. The
basic write serial format is as follows.
Stop Sequence – Stop frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); eight-bit Memory Address (MA); ACK;
eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK;
eight-bit data in MA+2; ACK; and so on, until STOP bit. The basic
serial format is illustrated in Figure 14.
Acknowledge Pulse
During Write mode, the CY22801 responds with an ACK pulse
after every eight bits. This is accomplished by pulling the SDAT
th
line LOW during the N × 9 clock cycle, as illustrated in
Data Valid
Figure 16. (N = the number of eight-bit segments transmitted.)
During Read mode, the ACK pulse, after the data packet is sent,
is generated by the master.
Data is valid when the Clock is HIGH, and may only be
transitional when the clock is LOW, as illustrated in Figure 13.
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 15.
Figure 13. Data Valid and Data Transition Periods
Transition to next bit
Data valid
SDAT
V
V
IH
SCLK
IL
Figure 14. Data Frame Architecture
1-bit
Slave
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
Slave
ACK ACK
1-bit
1-bit
Slave
ACK
Slave
ACK
Slave
ACK
Slave
ACK
Slave
ACK
Slave
ACK
SDAT Write
Multiple
Contiguous
Registers
R/W = 0
7-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
Device Register Register Register
Register
Register
Data
Register
Data
Address Address Data
(XXH) (XXH)
Data
(XXH+1) (XXH+2)
Data
(FFH)
(00H)
Stop Signal
Start Signal
1-bit
Slave
1-bit
Master
R/W = 1 ACK
1-bit
Master Master Master
ACK ACK ACK
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
Slave
Master
NACK
SDAT Read
Multiple
Contiguous
Registers
ACK ACK
8-bit
R/W = 0
7-bit
8-bit
Register
8-bit
8-bit
8-bit
Device Register 7-Bit
Register
Register
Data
Register
Data
Address Address Device Data
(XXH) Address
Data
(FFH)
(XXH)
(XXH+1)
(00H)
Stop Signal
Start Signal
Document Number: 001-15571 Rev. *M
Page 18 of 26
CY22801
Figure 15. Start and Stop Frame
SDAT
SCLK
Transition
to next bit
START
STOP
Figure 16. Frame Format (Device Address, R/W, Register Address, Register Data
SDAT
+
+
+
START
D7 D6 D1
D0
DA6 DA5DA0 R/W ACK
RA7 RA6RA1 RA0 ACK
ACK
STOP
+
+
+
SCLK
Figure 17. Definition for Timing on the Serial BUS
SDAT
SCLK
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
tr
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tHIGH
P
S
S
Sr
Table 16. Serial Programming Interface Timing Specifications
Parameter Description
Min
Max
400
–
Unit
kHz
s
f
Frequency of SCLK
–
SCLK
t
Hold time START condition
0.6
HD:STA
t
t
t
t
t
t
t
t
t
Low period of the SCLK clock
High period of the SCLK clock
1.3
0.6
0.6
100
100
–
–
–
s
s
s
ns
ns
ns
ns
s
s
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
Setup time for a repeated START condition
Data hold time
–
–
Data setup time
–
Rise time
300
300
–
Fall time
–
F
Setup time for STOP condition
Bus-free time between STOP and START conditions
0.6
1.3
SU:STO
BUF
–
Document Number: 001-15571 Rev. *M
Page 19 of 26
CY22801
Ordering Information
Ordering Code
CY22801KFXC
Package Type
8-pin SOIC
Operating Range
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Operating Voltage
3.3 V
3.3 V
3.3 V
3.3 V
CY22801KFXCT
CY22801KFXI
8-pin SOIC – Tape and Reel
8-pin SOIC
CY22801KFXIT
8-pin SOIC – Tape and Reel
Some product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales
representative for more information.
Possible Configurations
Ordering Code
Package Type
8-pin SOIC
Operating Range
Operating Voltage
[15]
Commercial, 0 °C to 70 °C
3.3 V
CY22801SXC-xxx
[15]
8-pin SOIC – Tape and Reel
8-pin SOIC
Commercial, 0 °C to 70 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
CY22801SXC-xxxT
[15]
CY22801SXI-xxx
CY22801SXI-xxxT
CY22801KSXC-xxx
[15]
[15]
[15]
8-pin SOIC – Tape and Reel
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin SOIC
CY22801KSXC-xxxT
[15]
CY22801KSXI-xxx
CY22801KSXI-xxxT
[15]
8-pin SOIC – Tape and Reel
Ordering Code Definitions
xxx
X
CY 22801X
X
X
X
-
X = blank or T
blank = Tube; T = Tape and Reel
Custom Configuration Code (Only for Factory Programmable Devices)
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Programming Option: X = F or blank
F = Field Programmable; blank = Factory Programmable
Device part number: 22801X = 22801K or 22801
X in Device part number: X = K or none
K = Foundry Manufacturing
Company ID: CY = Cypress
Note
15. Ordering codes with “xxx” are factory-programmed configurations. Factory programming is available for high volume orders. For more details, contact your local
Cypress field application engineer or Cypress sales representative.
Document Number: 001-15571 Rev. *M
Page 20 of 26
CY22801
Package Diagram
Figure 18. 8-pin SOIC (150 Mils) S08.15/SZ08.15 Package Outline, 51-85066
51-85066 *I
Document Number: 001-15571 Rev. *M
Page 21 of 26
CY22801
Acronyms
Document Conventions
Table 17. Acronyms Used in this Document
Units of Measure
Acronym
ACK
Description
Table 18. Units of Measure
Acknowledge
Clock Input
Symbol
°C
Unit of Measure
CLKIN
CMOS
EMI
degree Celsius
Complementary Metal-Oxide Semiconductor
Electromagnetic Interference
Electrostatic Discharge
dBc/Hz
fF
decibels relative to the carrier per Hertz
femtofarad
hertz
ESD
Hz
EMC
Electromagnetic Compatibility
Equivalent Series Resistance
Frequency Select
kbit
kHz
MHz
µA
1024 bits
ESR
kilohertz
FS
megahertz
microampere
microfarad
microsecond
milliampere
millisecond
milliwatt
2
I C
Inter Integrated Circuit
JEDEC
LSB
Joint Electron Device Engineering Council
Least Significant Bit
µF
µs
LVCMOS Low-Voltage Complementary Metal Oxide
Semiconductor
mA
ms
mW
ns
MSB
OE
Most Significant Bit
Output Enable
nanosecond
ohm
PD
Power Down
PFD
Phase Frequency Detector
Phase Locked Loop
%
percent
PLL
pF
picofarad
SSON
SCLK
SDAT
SOIC
SSC
Spread Spectrum ON
ppm
ps
parts per million
picosecond
volt
Serial Interface Clock
Serial Interface Data
V
Small-Outline Integrated Circuit
Spread Spectrum Clock
Spread Spectrum Clock Generation
Universal Programmable Clock Generator
Voltage Controlled Oscillator
Voltage Controlled Crystal Oscillator
SSCG
UPCG
VCO
VCXO
Document Number: 001-15571 Rev. *M
Page 22 of 26
CY22801
Document History Page
Document Title: CY22801, Universal Programmable Clock Generator (UPCG)
Document Number: 001-15571
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
1058080
KVM /
KKVTMP
05/10/07
New data sheet.
*A
*B
2440787
2724806
AESA
05/16/08
Updated Ordering Information (Added existing part numbers CY22801FXCT,
CY22801FXI, CY22801FXIT, CY22801SXC-xxx and CY22801SXC-xxxT and
added new part numbers CY22801KFXC, CY22801KFXCT, CY22801KFXI,
CY22801KFXIT, CY22801KSXC-xxx and CY22801KSXC-xxxT, added Note
“Not recommended for new designs.” and referred the same note for some
ordering codes, Added Note 15 and referred the same note for some ordering
codes).
Updated to new template.
KVM /
AESA
6/26/09
Updated Recommended Operating Conditions (Added T parameter
A
(Industrial Grade Ambient Temperature) and details).
Updated AC Electrical Characteristics (Added f
parameter (Industrial
OUT
Grade Output Frequency) and details).
Updated Ordering Information (Removed CY22801FXCT and CY22801FXIT,
added CY22801KSXI-xxx and CY22801KSXI-xxxT, added temperature
ranges in the Operating Range column in the Ordering Information Table).
Updated Package Diagram (Corrected package reference from S8 to SZ08 for
the spec 51-85066).
*C
*D
2897775
2981862
KVM
03/23/10
Updated Ordering Information:
Updated part numbers (Removed inactive parts).
Added Possible Configurations and moved xxx parts under the same.
Updated Package Diagram:
spec 51-85066 – Changed revision from *C to *D.
BASH
07/15/2010 Updated Features (Added Special Features).
Removed the section Benefits.
Updated Logic Block Diagram.
Updated Pin Configurations.
Updated Pin Definitions.
Added VCXO.
Added Spread Spectrum Clock Generation (SSCG).
Added Multifunction Pins.
Added Frequency Calculation and Register Definitions
Added Default Startup Condition for the CY22801.
Added Frequency Calculations and Register Definitions using the Serial (I2C)
Interface.
Added Application Guideline.
Added Possible Configuration Examples.
Added Informational Graphs.
Added Pullable Crystal Specifications for VCXO Application only.
Updated DC Electrical Specifications (Added I , I , fXO, V
parameters
IH IL
VCXO
and their details).
Updated AC Electrical Characteristics (Added tCCJ, tPD, t
, t
, F
OE1 OE2 MOD
parameters and their details).
Updated Timing Definitions (Added Figure 8, Figure 9, Figure 10, Figure 11,
Figure 12).
Added 2-wire Serial (I2C) Interface Timing.
Updated Ordering Information:
Updated Possible Configurations:
Updated details in “Ordering Code” column.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Document Number: 001-15571 Rev. *M
Page 23 of 26
CY22801
Document History Page (continued)
Document Title: CY22801, Universal Programmable Clock Generator (UPCG)
Document Number: 001-15571
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*E
3207656
CXQ
03/28/2011 Updated 2-wire Serial (I2C) Interface Timing:
Updated Table 16 (Changed minimum value of t parameter from 0 ns to
DH
100 ns).
*F
3455237
3580417
BASH /
PURU
12/05/2011 Updated Multifunction Pins (Added Note 1 and referred the same note in the
first paragraph in the section).
Updated Package Diagram:
spec 51-85066 – Changed revision from *D to *E.
Updated to new template.
*G
PURU
04/12/2012 Updated Features (Removed Field-programmable).
Updated Functional Description (Replaced “programming using CY36800”
with “programmed using Factory Specific Configurations”).
Updated Default Startup Condition for the CY22801 (Added Note 6 and
referred the same note at the end of 2nd paragraph in the section, added
Note 7 and referred the same note at the end of 3rd paragraph in the section).
Updated Frequency Calculations and Register Definitions using the Serial
(I2C) Interface (Updated PLL Frequency, P Counter [40H(1..0)], [41H(7..0)],
[42H(7)] (“Replaced CY22150 with CY22801”)).
Updated Field Programming the CY22801 (Replaced “programming using
CY36800” with “programmed using Factory Specific Configurations”).
Removed the section “CY36800 InstaClock™ Kit”.
*H
3686409
PURU
07/20/2012 Updated Features (Added Field-programmable).
Updated Functional Description (Replaced “programmed using Factory
Specific Configurations” with “programming using CY36800”).
Updated Field Programming the CY22801 (Replaced “programmed using
Factory Specific Configurations” with “programming using CY36800”).
Added the section “CY36800 InstaClock™ Kit”.
Updated Default Startup Condition for the CY22801 (Added Note 8 and
referred the same note at the end of 3nd paragraph in the section)
Updated to new template.
*I
4576237
AJU
11/21/2014 Updated Features:
Updated details under “Low-voltage complementary metal oxide
semiconductor (LVCMOS) output frequency”.
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated AC Electrical Characteristics:
Removed minimum values corresponding to f
Updated 2-wire Serial (I2C) Interface Timing:
and f
parameters.
REFD
OUT
Updated Figure 14 (Updated the last ACK in SDAT Read (Multiple Contiguous
Registers) to “NACK”.
Updated Package Diagram:
spec 51-85066 – Changed revision from *E to *F.
*J
4632360
4643649
TAVA
TAVA
01/20/2015 Updated Ordering Information:
Updated Possible Configurations:
Updated details in “Ordering Code” column.
Updated to new template.
*K
01/28/2015 Updated Ordering Information:
Updated Possible Configurations:
Updated details in “Ordering Code” column.
Updated Package Diagram:
spec 51-85066 – Changed revision from *F to *G.
Document Number: 001-15571 Rev. *M
Page 24 of 26
CY22801
Document History Page (continued)
Document Title: CY22801, Universal Programmable Clock Generator (UPCG)
Document Number: 001-15571
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*L
4805790
TAVA
06/26/2015 Updated 2-wire Serial (I2C) Interface Timing:
Updated Figure 13.
Added Figure 17.
Updated Table 16:
Updated entire table.
Updated to new template.
Completing Sunset Review.
*M
6012075
PAWK
01/03/2018 Updated Package Diagram:
spec 51-85066 – Changed revision from *G to *I.
Updated to new template.
Document Number: 001-15571 Rev. *M
Page 25 of 26
CY22801
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
®
®
Arm Cortex Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Clocks & Buffers
Interface
Community | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Memory
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2007-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-15571 Rev. *M
Revised January 3, 2018
Page 26 of 26
CyClocksRT, CyberClocks, and InstaClock are trademarks of Cypress Semiconductor Corporation.
相关型号:
©2020 ICPDF网 联系我们和版权申明