CY14B256LA-SP25XI [INFINEON]
nvSRAM (non-volatile SRAM);
| 型号： | CY14B256LA-SP25XI |
| 厂家： | 
Infineon |
| 描述： | nvSRAM (non-volatile SRAM) 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总23页 (文件大小：889K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY14B256LA
256-Kbit (32 K × 8) nvSRAM
CY14B256LA, 256-Kbit (32
K × 8) nvSRAM
Features
Functional Description
■ 25 ns and 45 ns access times
The Cypress CY14B256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 K bytes of 8 bits each. The embedded
nonvolatile elements incorporate QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
■ Internally organized as 32 K × 8 (CY14B256LA)
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20-year data retention
For a complete list of related documentation, click here.
■ Single 3 V +20% to –10% operation
■ Industrial temperature
■ 44-pin thin small outline package (TSOP)Type II, 48-pin shrunk
small outline package (SSOP), and 32-pin small-outline
integrated circuit (SOIC) packages
■ Pb-free and restriction of hazardous substances (RoHS)
compliance
Logic Block Diagram
V
CC
V
CAP
Quantum Trap
512 X 512
POWER
CONTROL
A5
STORE
A6
A7
A8
RECALL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
512 X 512
HSB
A9
A11
A12
A13
A14
SOFTWARE
DETECT
A13
-
A0
COLUMN I/O
DQ0
DQ1
DQ2
DQ3
COLUMN DEC
DQ4
DQ5
DQ6
DQ7
A0
A4
A10
A1
A3
A2
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-54707 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 25, 2020
CY14B256LA
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................4
Device Operation ..............................................................5
SRAM Read ................................................................5
SRAM Write .................................................................5
AutoStore Operation ....................................................5
Hardware STORE Operation .......................................5
Hardware RECALL (Power-Up) ..................................6
Software STORE .........................................................6
Software RECALL .......................................................6
Preventing AutoStore ..................................................7
Data Protection ............................................................7
Maximum Ratings .............................................................8
Operating Range ...............................................................8
DC Electrical Characteristics ..........................................8
Data Retention and Endurance .......................................9
Capacitance ......................................................................9
Thermal Resistance ..........................................................9
AC Test Loads ................................................................10
AC Test Conditions ........................................................10
AC Switching Characteristics .......................................11
Switching Waveforms ....................................................11
AutoStore/Power-Up RECALL .......................................13
Switching Waveforms ....................................................13
Software Controlled STORE/RECALL Cycle ................14
Switching Waveforms ....................................................14
Hardware STORE Cycle .................................................15
Switching Waveforms ....................................................15
Truth Table For SRAM Operations ................................16
Ordering Information ......................................................16
Ordering Code Definitions .........................................16
Package Diagrams ..........................................................17
Acronyms ........................................................................20
Document Conventions .................................................20
Units of Measure .......................................................20
Document History Page .................................................21
Sales, Solutions, and Legal Information ......................22
Worldwide Sales and Design Support .......................22
Products ....................................................................22
PSoC® Solutions .......................................................22
Cypress Developer Community .................................22
Technical Support .....................................................22
Document Number: 001-54707 Rev. *L
Page 2 of 22
CY14B256LA
Pinouts
Figure 1. 44-pin TSOP II / 48-pin SSOP pinout
V
NC
NC
1
2
3
CAP
44
43
42
41
HSB
NC
48
47
V
CC
1
2
3
[5]
NC
A
NC
[4]
14
A
NC
46
45
44
43
42
0
HSB
WE
[3]
A
12
A
1
4
5
4
NC
A
7
[2]
A
2
A
13
5
NC
NC
NC
40
39
A
6
[1]
[1]
6
7
8
9
10
11
12
13
14
A
8
A
9
A
3
6
A
5
A
4
7
8
38
37
36
35
NC
A
41
40
NC
A
CE
OE
DQ
4
11
DQ
44-pin TSOP II
9
0
1
7
48-pin SSOP
NC
NC
NC
39
NC
NC
NC
DQ
10
11
12
DQ
V
6
38
37
36
(x 8)
(x 8)
V
CC
34
33
32
31
SS
Top View
not to scale)
Top View
not to scale)
V
V
V
SS
SS
CC
V
SS
(
(
DQ
13
14
15
16
17
18
DQ
NC
2
5
NC
NC
35
DQ
3
DQ
V
NC
DQ0
15
16
17
18
19
20
21
4
34
33
32
31
WE
A
5
30
29
28
27
26
25
24
23
DQ6
OE
CAP
A
3
A
2
A
14
A
6
A
10
A
13
12
A
1
A
7
30
29
28
27
26
25
CE
DQ7
A
A
0
A
19
20
21
22
8
A
11
DQ1
DQ2
NC
A
9
DQ5
DQ4
DQ3
A
10
22
23
24
NC
NC
NC
NC
NC
V
CC
Figure 2. 32-pin SOIC pinout
V
CAP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
HSB
WE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A
14
A
12
A
A
13
7
A
A
A
8
6
5
A
9
A
11
A
4
A
3
(x8)
OE
NC
Top View
NC
(
not to scale)
A
A
10
2
A
1
CE
A
0
DQ
7
DQ
DQ
DQ
DQ
0
6
1
DQ
5
4
DQ
2
18
17
V
SS
DQ
3
Notes
1. Address expansion for 1-Mbit. NC pin not connected to die.
2. Address expansion for 2-Mbit. NC pin not connected to die.
3. Address expansion for 4-Mbit. NC pin not connected to die.
4. Address expansion for 8-Mbit. NC pin not connected to die.
5. Address expansion for 16-Mbit. NC pin not connected to die.
Document Number: 001-54707 Rev. *L
Page 3 of 22
CY14B256LA
Pin Definitions
Pin Name
I/O Type
Input
Description
A0–A14
Address inputs. Used to select one of the 32,768 bytes of the nvSRAM.
DQ0–DQ7 Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation.
WE
Input
Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Input
Input
Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tristated on deasserting OE HIGH.
VSS
VCC
Ground
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device. 3.0 V +20%, –10%
Input/Output Hardware STORE busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection
optional).
HSB
VCAP
NC
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No connect No connect. This pin is not connected to the die.
Document Number: 001-54707 Rev. *L
Page 4 of 22
CY14B256LA
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 8 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. Place a
pull-up on WE to hold it inactive during power-up. This pull-up is
only effective if the WE signal is tristate during power-up. Many
MPUs tristate their controls on power-up. This must be verified
when using the pull-up. When the nvSRAM comes out of
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
Device Operation
The CY14B256LA nvSRAM is made up of two functional
components paired in the same physical cell. They are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B256LA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer to the Truth Table For SRAM Operations on page 16 for a
complete description of read and write modes.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software-initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
SRAM Read
Figure 3. AutoStore Mode
The CY14B256LA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A0-14 determines which of the 32,768 data bytes each are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of tAA (read cycle 1). If the read
VCC
0.1 uF
is initiated by CE or OE, the outputs are valid at tACE or at tDOE
,
whichever is later (read cycle 2). The data output repeatedly
responds to address changes within the tAA access time without
the need for transitions on any control input pins. This remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
VCC
WE
VCAP
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if the data is valid tSD before the end of
a WE-controlled write or before the end of a CE-controlled write.
Keep OE HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
VCAP
VSS
Hardware STORE Operation
The CY14B256LA provides the HSB pin to control and
acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B256LA conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle only begins if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 kΩ weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
AutoStore Operation
The CY14B256LA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by HSB; Software STORE activated by an address sequence;
AutoStore on device power-down. The AutoStore operation is a
unique feature of QuantumTrap technology and is enabled by
default on the CY14B256LA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 kΩ pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B256LA. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other
external source.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 7. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
will corrupt the data stored in nvSRAM.
Document Number: 001-54707 Rev. *L
Page 5 of 22
CY14B256LA
During any STORE operation, regardless of how it is initiated,
the CY14B256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
tLZHSB time after HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power-Up)
Software RECALL
During power-up or after any low-power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven low by the HSB driver.
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
Software STORE
1. Read address 0x0E38 valid READ
2. Read address 0x31C7 valid READ
3. Read address 0x03E0 valid READ
4. Read address 0x3C1F valid READ
5. Read address 0x303F valid READ
6. Read address 0x0C63 initiate RECALL cycle
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14B256LA Software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Internally, RECALLis a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x0E38 valid READ
2. Read address 0x31C7 valid READ
3. Read address 0x03E0 valid READ
4. Read address 0x3C1F valid READ
5. Read address 0x303F valid READ
6. Read address 0x0FC0 initiate STORE cycle
Table 1. Mode Selection
[6]
A14–A0
Mode
I/O
Power
Standby
Active
CE
WE
OE
H
X
X
X
X
X
Not selected
Read SRAM
Write SRAM
Output high Z
Output data
Input data
L
L
L
H
L
L
X
L
Active
Active[7]
H
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Disable
Notes
6. While there are 15 address lines on the CY14B256LA, only the lower 14 are used to control software modes.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-54707 Rev. *L
Page 6 of 22
CY14B256LA
Table 1. Mode Selection (continued)
[6]
A14–A0
Mode
I/O
Power
CE
WE
OE
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Active[8]
Enable
[8]
L
L
H
H
L
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output data
Output data
Output data
Output data
Output data
Active ICC2
Output high Z
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output data
Output data
Output data
Output data
Output data
Output high Z
Active[8]
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x0E38 valid READ
2. Read address 0x31C7 valid READ
3. Read address 0x03E0 valid READ
4. Read address 0x3C1F valid READ
5. Read address 0x303F valid READ
6. Read address 0x0B46 AutoStore enable
1. Read address 0x0E38 valid READ
2. Read address 0x31C7 valid READ
3. Read address 0x03E0 valid READ
4. Read address 0x3C1F valid READ
5. Read address 0x303F valid READ
6. Read address 0x0B45 AutoStore disable
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power-down
cycles. The part comes from the factory with AutoStore enabled
and 0x00 written in all cells.
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
Data Protection
The CY14B256LA protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and write operations. The low voltage condition is detected when
VCC is less than VSWITCH. If the CY14B256LA is in a write mode
(both CE and WE are LOW) at power-up, after a RECALL or
STORE, the write is inhibited until the SRAM is enabled after
t
LZHSB (HSB to output active). This protects against inadvertent
writes during power-up or brown out conditions.
Note
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-54707 Rev. *L
Page 7 of 22
CY14B256LA
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Storage temperature ................................ –65 °C to +150 °C
Maximum accumulated storage time:
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 °C
DC output current (1 output at a time, 1s duration) .... 15 mA
At 150 °C ambient temperature ...................... 1000 h
At 85 °C ambient temperature ..................... 20 years
Maximum junction temperature ................................. 150 °C
Supply voltage on VCC relative to Vss ............–0.5 V to 4.1 V
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Latch-up current ................................................... > 200 mA
Voltage applied to outputs
in high Z state ..................................... –0.5 V to VCC + 0.5 V
Operating Range
Range
Industrial
Ambient Temperature
VCC
Input voltage .......................................–0.5 V to VCC + 0.5 V
–40 °C to +85 °C
2.7 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
Description
Power supply
Average VCC current
Test Conditions
Min
2.7
–
Typ [9]
Max
Unit
3.0
–
3.6
V
ICC1
tRC = 25 ns
RC = 45 ns
70
52
mA
mA
t
Values obtained without output loads
(IOUT = 0 mA)
ICC2
ICC3
Average VCC current during STORE All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
–
10
–
mA
mA
Average VCC current at
RC= 200 ns, VCC(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
35
t
ICC4
ISB
Average VCAP current during
AutoStore cycle
All inputs don’t Care. Average current for
duration tSTORE
–
–
–
–
5
5
mA
mA
VCC standby current
CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after nonvolatile
cycle is complete.
Inputs are static. f = 0 MHz.
[10]
IIX
Input leakage current (except HSB) VCC = Max, VSS < VIN < VCC
–1
–100
–1
–
–
–
+1
+1
+1
μA
μA
μA
Input leakage current (for HSB)
Off-state output leakage current
VCC = Max, VSS < VIN < VCC
IOZ
VCC = Max, VSS < VOUT < VCC
CE or OE > VIH or WE < VIL
,
VIH
VIL
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output LOW voltage
2.0
Vss – 0.5
2.4
–
–
–
–
VCC + 0.5
0.8
V
V
V
V
VOH
VOL
IOUT = –2 mA
IOUT = 4 mA
–
0.4
Notes
9. Typical values are at 25 °C, V = V
. Not 100% tested.
CC(Typ)
CC
10. The HSB pin has I
= –2 µA for V of 2.4 V when both active high and low drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
Document Number: 001-54707 Rev. *L
Page 8 of 22
CY14B256LA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Storage capacitor
Test Conditions
Min
61
–
Typ [9]
Max
180
VCC
Unit
μF
V
[11]
VCAP
Between VCAP pin and VSS
68
–
[12, 13]
VVCAP
Maximum voltage driven on VCAP pin VCC = Max
by the device
Data Retention and Endurance
Over the Operating Range
Parameter
Description
Min
Unit
Years
K
DATAR
NVC
Data retention
20
Nonvolatile STORE operations
1,000
Capacitance
Parameter[13]
Description
Test Conditions
Max
Unit
pF
CIN
Input capacitance (except HSB) TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)
Input capacitance (for HSB)
7
8
7
8
pF
COUT
Output capacitance (except HSB)
pF
Output capacitance (for HSB)
pF
Thermal Resistance
48-pin
SSOP
44-pin
TSOP II
32-pin
SOIC
Parameter[13]
Description
Test Conditions
Unit
ΘJA
Thermal resistance
(Junction to ambient)
Test conditions follow standard test 37.47
methods and procedures for measuring
41.74
11.9
41.55
°C/W
thermal impedance, in accordance with
ΘJC
Thermal resistance
(Junction to case)
24.71
24.43
°C/W
EIA/JESD51.
Notes
11. Min V
value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor on
CAP
CAP
V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
CAP
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V
options.
CAP
12. Maximum voltage on V
pin (V
) is provided for guidance when choosing the V
capacitor. The voltage rating of the V capacitor across the operating
CAP
VCAP
CAP
CAP
temperature range should be higher than the V
voltage.
VCAP
13. These parameters are guaranteed by design and are not tested.
Document Number: 001-54707 Rev. *L
Page 9 of 22
CY14B256LA
AC Test Loads
Figure 4. AC Test Loads
577 Ω
For tristate specs
577 Ω
3.0 V
3.0 V
R1
R1
OUTPUT
OUTPUT
R2
789 Ω
R2
789 Ω
5 pF
30 pF
AC Test Conditions
Input Pulse Levels .................................................0 V to 3 V
Input Rise and Fall Times (10%–90%) ....................... < 3 ns
Input and Output Timing Reference Levels .................. 1.5 V
Document Number: 001-54707 Rev. *L
Page 10 of 22
CY14B256LA
AC Switching Characteristics
Over the Operating Range
Parameters [14]
25 ns
45 ns
Description
Unit
Max
Cypress
Parameters
Alt
Min
Max
Min
Parameters
SRAM Read Cycle
tACE tACS
Chip enable access time
Read cycle time
–
25
25
–
–
45
45
–
ns
ns
[15]
tRC
tAA
tOE
tOH
tLZ
tRC
[16]
Address access time
–
–
3
3
–
0
–
0
–
25
12
–
–
–
3
3
–
0
–
0
–
45
20
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
tDOE
[16]
tOHA
[17, 18]
–
–
tLZCE
tHZCE
tLZOE
[17, 18]
[17, 18]
[17, 18]
tHZ
tOLZ
tOHZ
tPA
10
–
15
–
10
–
15
–
tHZOE
[17]
tPU
[17]
tPS
25
45
tPD
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tWC
tWP
tCW
tDW
tDH
tAW
tAS
Write cycle time
Write pulse width
25
20
20
10
0
20
0
0
–
–
–
–
–
–
–
–
10
45
30
30
15
0
30
0
0
–
–
–
–
–
–
–
–
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
tHA
tWR
tWZ
[17, 18, 19]
–
–
tHZWE
[17, 18]
tOW
Output active after end of write
3
–
3
–
ns
tLZWE
Switching Waveforms
Figure 5. SRAM Read Cycle #1 (Address Controlled) [15, 16, 20]
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Notes
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V
, and output loading of the specified
CC(typ)
CC
I
/I and load capacitance shown in Figure .
OL OH
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE and OE LOW.
17. These parameters are guaranteed by design and are not tested.
18. Measured ±200 mV from steady state output voltage.
19. If WE is low when CE goes low, the outputs remain in the high impedance state.
20. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-54707 Rev. *L
Page 11 of 22
CY14B256LA
Switching Waveforms (continued)
Figure 6. SRAM Read Cycle #2 (CE and OE Controlled) [21, 22]
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tLZOE
High Impedance
Standby
Data Output
Output Data Valid
tPU
tPD
Active
ICC
Figure 7. SRAM Write Cycle #1 (WE Controlled) [22, 23, 24]
tWC
Address
CE
Address Valid
tSCE
tHA
tAW
tPWE
WE
Data Input
Data Output
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Previous Data
Figure 8. SRAM Write Cycle #2 (CE Controlled) [22, 23, 24]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Notes
21. WE must be HIGH during SRAM read cycles.
22. HSB must remain HIGH during READ and WRITE cycles.
23. If WE is low when CE goes low, the outputs remain in the high impedance state.
24. CE or WE must be > V during address transitions.
IH
Document Number: 001-54707 Rev. *L
Page 12 of 22
CY14B256LA
AutoStore/Power-Up RECALL
Over the Operating Range
CY14B256LA
Parameters
Description
Unit
Min
Max
[25]
Power-up RECALL duration
STORE cycle duration
–
20
ms
ms
ns
V
tHRECALL
[26]
–
–
8
25
tSTORE
[27]
Time allowed to complete SRAM write cycle
Low voltage trigger level
tDELAY
VSWITCH
–
2.65
–
[28]
VCC rise time
150
–
µs
V
tVCCRISE
[28]
HSB output disable voltage
1.9
VHDIS
[28]
tLZHSB
HSB to output active time
HSB high active time
–
–
5
µs
ns
[28]
tHHHD
500
Switching Waveforms
Figure 9. AutoStore or Power-Up RECALL [29]
VCC
VSWITCH
VHDIS
26
26
tVCCRISE
tSTORE
tSTORE
Note
Note
tHHHD
tHHHD
30
30
Note
Note
HSB OUT
AutoStore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
AutoStore
POWER
DOWN
AutoStore
POWER-UP
RECALL
Notes
25. t
starts from the time V rises above V .
SWITCH
HRECALL
CC
26. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
27. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time t
28. These parameters are guaranteed by design and are not tested.
.
DELAY
29. Read and Write cycles are ignored during STORE, RECALL, and while V is below V
.
CC
SWITCH
30. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-54707 Rev. *L
Page 13 of 22
CY14B256LA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
25 ns
45 ns
Unit
Parameters [31, 32]
Description
Min
Max
Min
Max
tRC
STORE/RECALL initiation cycle time
Address setup time
25
–
45
–
ns
ns
ns
ns
µs
tSA
0
20
0
–
–
0
30
0
–
tCW
Clock pulse width
–
tHA
Address hold time
–
–
tRECALL
RECALL duration
–
200
–
200
Switching Waveforms
Figure 10. CE and OE Controlled Software STORE/RECALL Cycle [32]
tRC
tRC
Address
CE
Address #1
tCW
Address #6
tCW
tSA
tHA
tHA
tHA
tSA
tHA
OE
tHHHD
tHZCE
HSB (STORE only)
DQ (DATA)
33
Note
tDELAY
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 11. Autostore Enable / Disable Cycle[32]
tRC
tRC
Address
Address #1
Address #6
tCW
tSA
tCW
CE
OE
tHA
tHA
tHA
tSA
tHA
tSS
tHZCE
33
tLZCE
tDELAY
Note
DQ (DATA)
RWI
Notes
31. The software sequence is clocked with CE controlled or OE controlled reads.
32. The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE must be HIGH during all six consecutive cycles.
33. DQ output data at the sixth read may be invalid since the output is disabled at t
time.
DELAY
Document Number: 001-54707 Rev. *L
Page 14 of 22
CY14B256LA
Hardware STORE Cycle
Over the Operating Range
CY14B256LA
Parameters
Description
Unit
Min
–
Max
25
tDHSB
tPHSB
HSB to output active time when write latch is not set
Hardware STORE pulse width
ns
ns
μs
15
–
–
[34, 35]
tSS
Soft sequence processing time
100
Switching Waveforms
Figure 12. Hardware STORE Cycle [36]
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
DQ (Data Out)
RWI
tLZHSB
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100 kOhm resistor,
HSB (IN)
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDELAY
tDHSB
tDHSB
HSB (OUT)
RWI
Figure 13. Soft Sequence Processing [34, 35]
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
34. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
35. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
36. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-54707 Rev. *L
Page 15 of 22
CY14B256LA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 2. Truth Table
CE
H
L
WE
X
OE
X
Inputs/Outputs
High Z
Mode
Deselect/power-down
Read
Power
Standby
Active
H
L
Data out (DQ0–DQ7);
High Z
L
H
H
Output disabled
Write
Active
L
L
X
Data in (DQ0–DQ7);
Active
Ordering Information
Speed
(ns)
Ordering Code
Package Diagram
Package Type
Operating Range
25
CY14B256LA-ZS25XIT
CY14B256LA-ZS25XI
CY14B256LA-SP25XIT
CY14B256LA-SP25XI
CY14B256LA-SZ25XIT
CY14B256LA-SZ25XI
CY14B256LA-SP45XIT
CY14B256LA-SP45XI
CY14B256LA-SZ45XIT
CY14B256LA-SZ45XI
51-85087
51-85087
51-85061
51-85061
51-85127
51-85127
51-85061
51-85061
51-85127
51-85127
44-pin TSOP II
Industrial
44-pin TSOP II
48-pin SSOP
48-pin SSOP
32-pin SOIC
32-pin SOIC
48-pin SSOP
48-pin SSOP
32-pin SOIC
32-pin SOIC
45
All the above parts are Pb-free.
Ordering Code Definitions
CY 14 B 256 L A - ZS 25 X I T
Option:
T - Tape and Reel
Blank – Std.
Temperature:
I - Industrial (–40 to 85 °C)
Pb-free
Speed:
25 – 25 ns
45 – 45 ns
Package:
ZS - 44-pin TSOP II
SP - 48-pin SSOP
SZ - 32-pin SOIC
Die revision:
Blank – No Rev
A – 1st Rev
Data Bus:
L – × 8
Density:
256 – 256 Kb
Voltage:
B – 3.0 V
14 – nvSRAM
Cypress
Document Number: 001-54707 Rev. *L
Page 16 of 22
CY14B256LA
Package Diagrams
Figure 14. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-54707 Rev. *L
Page 17 of 22
CY14B256LA
Package Diagrams (continued)
Figure 15. 48-pin SSOP (300 Mils) Package Outline, 51-85061
51-85061 *F
Document Number: 001-54707 Rev. *L
Page 18 of 22
CY14B256LA
Package Diagrams (continued)
Figure 16. 32-pin SOIC (300 Mil) Package Outline, 51-85127
51-85127 *D
Document Number: 001-54707 Rev. *L
Page 19 of 22
CY14B256LA
Acronyms
Document Conventions
Units of Measure
Acronym
Description
chip enable
CE
Symbol
°C
Unit of Measure
CMOS
complementary metal oxide semiconductor
electronic industries alliance
hardware store busy
degree Celsius
kilohm
EIA
kΩ
MHz
μA
μF
μs
mA
ms
ns
HSB
I/O
megahertz
microampere
microfarad
microsecond
milliampere
millisecond
nanosecond
ohm
input/output
nvSRAM
non-volatile static random access memory
output enable
OE
RoHS
restriction of hazardous substances
read and write inhibited
RWI
SRAM
SSOP
SOIC
TSOP
WE
static random access memory
shrink small outline package
small outline integrated circuit
thin small outline package
write enable
Ω
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-54707 Rev. *L
Page 20 of 22
CY14B256LA
Document History Page
Document Title: CY14B256LA, 256-Kbit (32 K × 8) nvSRAM
Document Number: 001-54707
Submission
Revision
ECN
Description of Change
Date
**
2746918
2772059
2829117
07/31/2009 New data sheet.
*A
*B
09/30/2009 Updated Software STORE, RECALL and Autostore Enable, Disable soft sequence
12/16/09
Updated STORE cycles to QuantumTrap from 200K to 1 Million
Updated 48-pin SSOP package diagram
Added Contents. Moved to external web
*C
2894560
03/18/10
Added more clarity on HSB pin operation
Updated HSB pin operation in Figure 9 and updated footnote 21
Removed from ordering information table.
CY14B256LA-ZS25XIT, CY14B256LA-ZS25XI, CY14B256LA-ZS45XIT, CY14B256-
LA-ZS45XI
Updated Package Diagrams for spec 51-85061 and 51-85087.
Updated copyright section.
Updated links under section sales, solutions, and legal information.
*D
*E
2995066
3074570
07/28/2010 Added CY14B256LA-ZS25XI part to ordering information table.
10/29/10
Added CY14B256LA-ZS25XIT part to ordering information table.
Added Units of Measure table
*F
3143330
3315247
01/17/2011 Fixed typo in Figure 9.
*G
07/15/2011 Updated DC Electrical Characteristics (Added Note 11 and referred the same note in VCAP
parameter).
Updated Capacitance (Included Input capacitance (for HSB) and Output capacitance (for
HSB)).
Updated Thermal Resistance (ΘJA and ΘJC values for 44-pin TSOP II packages).
Updated AC Switching Characteristics (Added Note 14 and referred the same note in Pa-
rameters).
*H
*I
3430452
3660776
11/04/2011 Corrected alignment of footnote 24.
Updated Package Diagrams.
06/29/2012 Updated DC Electrical Characteristics (Added VVCAP parameter and its details, added Note
12 and referred the same note in VVCAP parameter, also referred Note 13 in VVCAP
parameter).
*J
3759425
09/28/2012 Updated Maximum Ratings (Removed “Ambient temperature with power applied” and
included “Maximum junction temperature”).
Updated Package Diagrams (spec 51-85087 (Changed revision from *D to *E), spec
51-85061 (Changed revision from *E to *F)).
*K
*L
4568935
6868237
11/14/2014 Added documentation related hyperlink in page 1
04/25/2020 Updated to template.
Updated Spec 51-85127 *C to *D in Package Diagrams.
Document Number: 001-54707 Rev. *L
Page 21 of 22
CY14B256LA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
© Cypress Semiconductor Corporation, 2009-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves
all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If
the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document.Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility
of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any
device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices.
“Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect
its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product
as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims,
costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical
Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published
data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a
Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-54707 Rev. *L
Revised April 25, 2020
Page 22 of 22
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