CY14B101Q2-LHXIT [INFINEON]
nvSRAM (non-volatile SRAM);
| 型号： | CY14B101Q2-LHXIT |
| 厂家： | 
Infineon |
| 描述： | nvSRAM (non-volatile SRAM) 静态存储器 内存集成电路 |
| 文件： | 总30页 (文件大小：1210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
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The fact that Infineon offers the following product as part of the Infineon product
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Infineon continues to support existing part numbers. Please continue to use the
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CY14B101Q1
CY14B101Q2
CY14B101Q3
1-Mbit (128K × 8) Serial SPI nvSRAM
1-Mbit (128K
× 8) Serial SPI nvSRAM
❐ CY14B101Q1 has identical pin configuration to industry
standard 8-pin NV memory
Features
❐ 8-pin dual flat no-lead (DFN) package and 16-pin small
■ 1-Mbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 128K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
(except for CY14B101Q1)
outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Functional Description
The
Cypress
CY14B101Q1/CY14B101Q2/CY14B101Q3
combines a 1-Mbit nvSRAM with a nonvolatile element in each
memory cell with serial SPI interface. The memory is organized
as 128 K words of 8 bits each. The embedded nonvolatile
elements incorporate the QuantumTrap technology, creating the
world’s most reliable nonvolatile memory. The SRAM provides
infinite read and write cycles, while the QuantumTrap cell
provides highly reliable nonvolatile storage of data. Data
transfers from SRAM to the nonvolatile elements (STORE
operation) takes place automatically at power-down (except for
CY14B101Q1). On power-up, data is restored to the SRAM from
the nonvolatile memory (RECALL operation). Both STORE and
RECALL operations can also be initiated by the user through SPI
instruction.
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years
■ High speed serial peripheral interface (SPI)
❐ 40 MHz clock rate
❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
■ Write protection
For a complete list of related documentation, click here.
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4,1/2, or entire array
Configuration
Feature
CY14B101Q1
CY14B101Q2
CY14B101Q3
■ Low power consumption
❐ Single 3 V +20%, –10% operation
❐ Average active current of 10 mA at 40 MHz operation
AutoStore
No
Yes
Yes
Yes
Yes
Software
STORE
Yes
■ Industry standard configurations
❐ Industrial temperature
Hardware
STORE
No
No
Yes
Logic Block Diagram
VCC
VCAP
QuantumTrap
128 K X 8
Power Control
CS
WP
SCK
Instruction decode
Write protect
Control logic
STORE/RECALL
Control
STORE
HSB
SRAM Array
128 K X 8
HOLD
RECALL
Instruction
register
D0-D7
A0-A16
Address
Decoder
Data I/O register
Status Register
SO
SI
Cypress Semiconductor Corporation
Document Number: 001-50091 Rev. *P
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 12, 2018
CY14B101Q1
CY14B101Q2
CY14B101Q3
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................4
Device Operation ..............................................................5
SRAM Write .................................................................5
SRAM Read ................................................................5
STORE Operation .......................................................5
AutoStore Operation ....................................................6
Software STORE Operation ........................................6
Hardware STORE and HSB Pin Operation .................6
RECALL Operation ......................................................6
Hardware RECALL (Power-Up) ..................................6
Software RECALL .......................................................6
Disabling and Enabling AutoStore ...............................7
Serial Peripheral Interface ...............................................7
SPI Overview ...............................................................7
SPI Modes ...................................................................8
SPI Operating Features ....................................................9
Power-Up ....................................................................9
Power-On Reset ..........................................................9
Power-Down ................................................................9
Active Power and Standby Power Modes ...................9
SPI Functional Description ..............................................9
Status Register ...............................................................10
Read Status Register (RDSR) Instruction .................10
Write Status Register (WRSR) Instruction ................10
Write Protection and Block Protection .........................11
Write Enable (WREN) Instruction ..............................11
Write Disable (WRDI) Instruction ..............................11
Block Protection ........................................................11
Write Protect (WP) Pin ..............................................12
Memory Access ..............................................................12
Read Sequence (READ) instruction ..........................12
Write Sequence (WRITE) instruction ........................12
Software STORE (STORE) instruction ......................14
Software RECALL (RECALL) instruction ..................14
AutoStore Enable (ASENB) instruction .....................14
AutoStore Disable (ASDISB) instruction ...................14
HOLD Pin Operation .................................................14
Maximum Ratings ...........................................................15
Operating Range .............................................................15
DC Electrical Characteristics ........................................15
Data Retention and Endurance .....................................16
Capacitance ....................................................................16
Thermal Resistance ........................................................16
AC Test Loads and Waveforms .....................................16
AC Test Conditions ........................................................16
AC Switching Characteristics .......................................17
Switching Waveforms ....................................................18
AutoStore or Power-Up RECALL ..................................19
Switching Waveforms ....................................................19
Software Controlled STORE and RECALL Cycles ......20
Switching Waveforms ....................................................20
Hardware STORE Cycle .................................................21
Switching Waveforms ....................................................21
Ordering Information ......................................................22
Ordering Code Definitions .........................................22
Package Diagrams ..........................................................23
Acronyms ........................................................................25
Document Conventions .................................................25
Units of Measure .......................................................25
Document History Page .................................................26
Sales, Solutions, and Legal Information ......................29
Worldwide Sales and Design Support .......................29
Products ....................................................................29
PSoC® Solutions ......................................................29
Cypress Developer Community .................................29
Technical Support .....................................................29
Document Number: 001-50091 Rev. *P
Page 2 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Pinouts
Figure 1. 8-pin DFN pinout [1, 2, 3]
CY14B101Q1
CY14B101Q2
O1
2
8
7
6
5
O1
2
V
CS
SO
WP
V
CC
CS
8
7
CC
HOLD
SCK
SI
SO
HOLD
SCK
SI
EXPOSED
PAD
EXPOSED
PAD
V
3
3
4
6
5
CAP
V
V
4
SS
SS
Top View
Top View
(not to scale)
(not to scale)
Figure 2. 16-pin SOIC pinout
V
16
NC
1
2
3
CC
NC
NC
NC
WP
NC
V
15
14
13
12
11
CAP
CY14B101Q3
Top View
4
5
6
SO
SI
not to scale
SCK
HOLD
NC
7
8
10
9
CS
V
SS
HSB
Notes
1. HSB pin is not available in 8-pin DFN packages.
2. CY14B101Q1 part does not have V pin and does not support AutoStore.
CAP
3. CY14B101Q2 part does not have WP pin.
Document Number: 001-50091 Rev. *P
Page 3 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Pin Definitions
Pin Name
I/O Type
Description
CS
Input
Chip select. Activates the device when pulled LOW. Driving this pin high puts the device in low power
standby mode.
SCK
Input
Serial clock. Runs at speeds up to maximum of fSCK. Serial input is latched at the rising edge of this
clock. Serial output is driven at the falling edge of the clock.
SI
SO
Input
Output
Input
Serial input. Pin for input of all SPI instructions and data.
Serial output. Pin for output of data through SPI.
Write protect. Implements hardware write protection in SPI.
HOLD pin. suspends serial operation.
WP
HOLD
HSB
Input
Input/Output Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak
internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM
to nonvolatile elements. If AutoStore is not needed, this pin must be left as No connect. It must never
be connected to VSS
.
NC
VSS
VCC
No connect No connect: This pin is not connected to the die.
Power supply Ground
Power supply Power supply (2.7 V to 3.6 V)
EXPOSED No connect The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. It is recommended
PAD to connect the EXPOSED PAD to VSS. Thermal vias can be used to increase thermal conductivity.
Document Number: 001-50091 Rev. *P
Page 4 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
SRAM Write
Device Operation
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables the user to perform infinite write operations. A write cycle
is performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, three bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
CY14B101Q1/CY14B101Q2/CY14B101Q3 is a 1-Mbit nvSRAM
memory with a nonvolatile element in each memory cell. All the
reads and writes to nvSRAM happen to the SRAM, which gives
nvSRAM the unique capability to handle infinite writes to the
memory. The data in SRAM is secured by a STORE sequence,
which transfers the data in parallel to the nonvolatile
QuantumTrap cells. A small capacitor (VCAP) is used to
AutoStore the SRAM data in nonvolatile cells when power goes
down providing power-down data security. The QuantumTrap
nonvolatile elements built in the reliable SONOS technology
make nvSRAM the ideal choice for secure data storage.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The 1 Mbit memory array is organized as 128K words × 8 bits.
The memory is accessed through a standard SPI interface that
enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The SPI write cycle sequence is defined in the memory access
section of SPI Protocol Description.
The device is enabled using the Chip Select ( ) pin and
accessed through Serial Input (SI), Serial Output (SO), and
Serial Clock (SCK) pins.
SRAM Read
CS
A read cycle is performed at the SPI bus speed and the data is
read out with zero cycle delay after the READ instruction is
executed. The READ instruction is issued through the SI pin of
the nvSRAM and consists of the READ opcode and 3 bytes of
address. The data is read out on the SO pin.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the status register. Further, the
HOLD pin can be used to suspend any serial communication
without resetting the serial sequence.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard
SPI opcodes for memory access. In addition to the general SPI
instructions for read and write, it provides four special
instructions which enable access to four nvSRAM specific
functions: STORE, RECALL, AutoStore Disable (ASDISB), and
AutoStore Enable (ASENB).
The SPI read cycle sequence is defined in the memory access
section of SPI Protocol Description.
STORE Operation
The major benefit of serial (SPI) nvSRAM over serial EEPROMs
is that all reads and writes to nvSRAM are performed at the
speed of SPI bus with zero cycle delay. Therefore, no wait time
is required after any of the memory accesses. The STORE and
RECALL operations need finite time to complete and all memory
accesses are inhibited during this time. While a STORE or
RECALL operation is in progress, the busy status of the device
is indicated by the Hardware STORE Busy (HSB) pin and also
reflected on the RDY bit of the Status Register.
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device stores data to the
nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, read/write to CY14B101Q1/CY14B101Q2/
The device is available in three different pin configurations that
enable the user to choose a part which fits in best in their
application. The feature summary is given in Table 1.
CY14B101Q3 is inhibited until the cycle is completed.
The HSB signal or the RDY bit in the Status register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
Table 1. Feature Summary
Feature
WP
CY14B101Q1
CY14B101Q2
CY14B101Q3
Yes
No
No
Yes
No
Yes
Yes
Yes
Yes
Yes
V
CAP
HSB
No
AutoStore
No
Yes
Yes
Power Up
RECALL
Yes
Hardware
STORE
No
No
Yes
Yes
Software
STORE
Yes
Yes
Document Number: 001-50091 Rev. *P
Page 5 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
AutoStore Operation
Hardware STORE and HSB Pin Operation
The AutoStore operation is a unique feature of nvSRAM, which
automatically stores the SRAM data to QuantumTrap during
power-down. This STORE makes use of an external capacitor
(VCAP) and enables the device to safely STORE the data in the
nonvolatile memory when power goes down.
The HSB pin in CY14B101Q3 is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after tDELAY duration. An actual
STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
writes to the memory are inhibited for tSTORE duration or as long
as HSB pin is LOW.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
RECALL.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in AutoStore Disable (ASDISB) instruction on page 14.
If AutoStore is enabled without a capacitor on the VCAP pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This corrupts the data stored in the
nvSRAM and Status register. To resume normal functionality, the
WRSR instruction must be issued to update the nonvolatile bits
BP0, BP1 and WPEN in the Status Register.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100 k pull-up
resistor.
Note For successful last data byte STORE, a hardware store
should be initiated atleast one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
Figure 3 shows the proper connection of the storage capacitor
(VCAP
)
for AutoStore operation. See DC Electrical
Characteristics on page 15 for the size of the VCAP
.
Note CY14B101Q1/CY14B101Q2 do not have HSB pin. RDY bit
of the SPI status register may be probed to determine the Ready
or Busy status of nvSRAM.
Note CY14B101Q1 does not support AutoStore operation. The
user must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
RECALL Operation
Figure 3. AutoStore Mode
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up;
and Software RECALL, initiated by a SPI RECALL instruction.
VCC
0.1 uF
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared. Next, the nonvolatile information is transferred
into the SRAM cells. All memory accesses are inhibited while a
RECALL cycle is in progress. The RECALL operation does not
alter the data in the nonvolatile elements.
VCC
CS
VCAP
Hardware RECALL (Power-Up)
VCAP
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
VSS
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
Software RECALL
Software RECALL enables the user to initiate a RECALL
operation to restore the content of nonvolatile memory on to the
SRAM. A Software RECALL is issued by using the SPI
instruction for RECALL.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status register or the HSB pin may be polled to find the
Ready or Busy status of the nvSRAM. After the tSTORE cycle time
is completed, the SRAM is activated again for read and write
operations.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Document Number: 001-50091 Rev. *P
Page 6 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
SPI Slave
Disabling and Enabling AutoStore
The SPI slave device is activated by the master through the chip
select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power-down.
AutoStore can be re-enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if the user
need this setting to survive the power cycle, a STORE operation
must be performed following AutoStore Disable or Enable
operation.
CY14B101Q1/CY14B101Q2/CY14B101Q3 operates as a SPI
slave and may share the SPI bus with other SPI slave devices.
Chip Select (CS)
Note CY14B101Q2/CY14B101Q3 has AutoStore Enabled from
the factory and CY14B101Q1/CY14B101Q2/CY14B101Q3
comes from the factory with 0x00 written in all cells. In
CY14B101Q1, VCAP pin is not present and AutoStore option is
not available. The AutoStore Enable and Disable instructions to
CY14B101Q1 are ignored.
For selecting any slave device, the master needs to pull-down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW. When the device is
not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high-impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active chip
select cycle.
Note If AutoStore is disabled and VCAP is not required, then the
V
CAP pin must be left open. VCAP pin must never be connected
to ground. Power-Up RECALL operation cannot be disabled in
any case.
Serial Clock (SCK)
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
Serial Peripheral Interface
SPI Overview
CY14B101Q1/CY14B101Q2/CY14B101Q3 enables SPI modes
0 and 3 for data communication. In both these modes, the inputs
are latched by the slave device on the rising edge of SCK and
outputs are issued on the falling edge. Therefore, the first rising
edge of SCK signifies the arrival of the first bit (MSB) of SPI
instruction on the SI pin. Further, all data inputs and outputs are
synchronized with SCK.
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
CY14B101Q1/CY14B101Q2/CY14B101Q3 provides serial
access to nvSRAM through SPI interface. The SPI bus on this
device can run at speeds up to 40 MHz.
The SPI is a synchronous serial interface, which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using a CS pin.
Data Transmission - SI and SO
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are as follows:
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
most significant bit (MSB). This is valid for both address and data
transmission.
The 1 Mbit serial nvSRAM requires a 3-byte address for any read
or write operation. However, since the actual address is only
17 bits, it implies that the first seven bits which are fed in are
ignored by the device. Although these seven bits are ‘don’t care’,
Cypress recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard
opcodes for memory accesses. In addition to the memory
accesses, it provides additional opcodes for the nvSRAM
specific functions: STORE, RECALL, AutoStore Enable, and
AutoStore Disable. See Table 2 on page 9 for details.
Document Number: 001-50091 Rev. *P
Page 7 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Invalid Opcode
Status Register
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tristated.
CY14B101Q1/CY14B101Q2/CY14B101Q3 has an 8-bit status
register. The bits in the status register are used to configure the
SPI bus. These bits are described in the Table 4 on page 10.
Figure 4. System Configuration Using SPI nvSRAM
S C K
M O SI
M IS O
SC K
S I
S O
SC K
SI
S O
uC ontroller
C Y 14B 101Q x
C Y 14B 101Q x
C S
H O LD
C S
H O LD
C S 1
H O LD 1
C S 2
H O LD 2
SPI Modes
CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a
microcontroller with its SPI peripheral running in either of the
following two modes:
Figure 5. SPI Mode 0
CS
SCK
SI
■ SPI Mode 0 (CPOL = 0, CPHA = 0)
■ SPI Mode 3 (CPOL = 1, CPHA = 1)
0
1
2
3
4
5
6
7
For both these modes, the input data is latched-in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge, after the clock toggles, is considered. The output
data is available on the falling edge of SCK.
7
6
5
4
3
2
1
0
MSB
LSB
The two SPI modes are shown in Figure 5 and Figure 6. The
status of clock when the bus master is in standby mode and not
transferring data is:
Figure 6. SPI Mode 3
■ SCK remains at 0 for Mode 0
■ SCK remains at 1 for Mode 3
CS
0
1
2
3
4
5
6
7
CPOL and CPHA bits must be set in the SPI controller for the
either Mode 0 or Mode 3. The device detects the SPI mode from
the status of SCK pin when the device is selected by bringing the
CS pin LOW. If SCK pin is LOW when the device is selected, SPI
Mode 0 is assumed and if SCK pin is HIGH, it works in SPI
Mode 3.
SCK
SI
7
6
5
4
3
2
1
0
MSB
LSB
Document Number: 001-50091 Rev. *P
Page 8 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Active Power and Standby Power Modes
SPI Operating Features
When CS is LOW, the device is selected, and is in the active
power mode. The device consumes ICC current, as specified in
DC Electrical Characteristics on page 15. When CS is HIGH, the
device is deselected and the device goes into the standby power
mode if a STORE or RECALL cycle is not in progress. If a
STORE or RECALL cycle is in progress, the device goes into the
standby power mode after the STORE or RECALL cycle is
completed. In the standby power mode, the current drawn by the
Power-Up
Power-up is defined as the condition when the power supply is
turned on and VCC crosses VSWITCH voltage. During this time,
the CS must be allowed to follow the VCC voltage. Therefore, CS
must be connected to VCC through a suitable pull-up resistor. As
a built-in safety feature, CS is both edge sensitive and level
sensitive. After power-up, the device is not selected until a falling
edge is detected on CS. This ensures that CS is HIGH, before
going LOW to start the first operation.
device drops to ISB
.
SPI Functional Description
As described earlier, nvSRAM performs a Power-Up RECALL
operation after power-up and therefore, all memory accesses are
disabled for tFA duration after power-up. The HSB pin can be
probed to check the ready or busy status of nvSRAM after
power-up.
The CY14B101Q1/CY14B101Q2/CY14B101Q3 uses an 8-bit
instruction register. Instructions and their operation codes are
listed in Table 2. All instructions, addresses, and data are
transferred with the MSB first and start with a HIGH to LOW CS
transition. There are, in all, 10 SPI instructions which provide
access to most of the functions in nvSRAM. Further, the WP,
HOLD and HSB pins provide additional functionality driven
through hardware.
Power-On Reset
A power-on reset (POR) circuit is included to prevent inadvertent
writes. At power-up, the device does not respond to any
instruction until the VCC reaches the POR threshold voltage
(VSWITCH). After VCC transitions the POR threshold, the device
is internally reset and performs an Power-Up RECALL operation.
During Power-Up RECALL all device accesses are inhibited.
The device is in the following state after POR:
Table 2. Instruction Set
Instruction
Category
Instruction
Name
Opcode
Operation
■ Deselected (after power-up, a falling edge is required on CS
before any instructions are started).
WREN
0000 0110 Set write enable
latch
WRDI
0000 0100
0000 0101
0000 0001
Reset write
enable latch
■ Standby power mode
Status Register
Control Instruc-
tions
■ Not in the HOLD condition
RDSR
WRSR
READ
WRITE
Read Status
Register
■ Status register state:
❐ Write Enable (WEN) bit is reset to 0.
❐ WPEN, BP1, BP0 unchanged from previous STORE
operation
Write Status
Register
0000 0011 Read data from
memory array
❐ Don’t care bits 4–6 are reset to 0.
SRAM
Read/Write
Instructions
The WPEN, BP1, and BP0 bits of the Status Register are
nonvolatile bits and remain unchanged from the previous
STORE operation.
0000 0010
Write data to
memory array
STORE
0011 1100 Software STORE
Before selecting and issuing instructions to the memory, a valid
and stable VCC voltage must be applied. This voltage must
remain valid until the end of the instruction transmission.
RECALL
0110 0000
Software
RECALL
Special NV
Instructions
ASENB
ASDISB
0101 1001 AutoStore Enable
Power-Down
0001 1001
AutoStore
Disable
At power-down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
received when the power goes down, it is allowed tDELAY time to
complete the write. After which all memory accesses are
inhibited and a conditional AutoStore operation is performed
(AutoStore is not performed if no writes have happened since
last RECALL cycle). This feature prevents inadvertent writes to
nvSRAM from happening during power-down.
Reserved
- Reserved - 0001 1110
The SPI instructions are divided based on their functionality in
the following types:
❐ Status Register access: RDSR and WRSR instructions
❐ Write protection functions: WREN and WRDI instructions
along with WP pin and WEN, BP0, and BP1 bits
❐ SRAM memory access: READ and WRITE instructions
However, to completely avoid the possibility of inadvertent writes
during power-down, ensure that the device is deselected and is
in standby power mode, and the CS follows the voltage applied
❐ nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
on VCC
.
Document Number: 001-50091 Rev. *P
Page 9 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Status Register
The status register bits are listed in Table 4. The status register consists of a Ready bit (RDY) and data protection bits BP1, BP0,
WEN, and WPEN. The RDY bit can be polled to check the Ready or Busy status while a nvSRAM STORE or Software RECALL cycle
is in progress. The status register can be modified by WRSR instruction and read by RDSR instruction. However, only the WPEN,
BP1, and BP0 bits of the Status Register can be modified by using WRSR instruction. The WRSR instruction has no effect on WEN
and RDY bits. The default value shipped from the factory for WEN, BP0, BP1, bits 4–6 and WPEN bits is ‘0’.
Table 3. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN (0)
X (0)
X (0)
X (0)
BP1 (0)
BP0 (0)
WEN (0)
RDY
Table 4. Status Register Bit Definition
Bit
Definition
Description
Bit 0 (RDY)
Ready
Read only bit indicates the ready status of device to perform a memory access. This bit is
set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.
Bit 1 (WEN)
Write Enable
WEN indicates if the device is Write Enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEN = ‘1’ --> Write Enabled
WEN = ‘0’ --> Write Disabled
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4-6
Block protect bit ‘0’ Used for block protection. For details see Table 5 on page 11.
Block protect bit ‘1’ Used for block protection. For details see Table 5 on page 11.
Don’t care
Bits are writable and volatile. On power-up, bits are written with ‘0’.
Bit 7 (WPEN)
Write protect enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 6 on page 12.
WRSR instruction is a write instruction and needs writes to be
enabled (WEN bit set to ‘1’) using the WREN instruction before
it is issued. The instruction is issued after the falling edge of CS
using the opcode for WRSR followed by 8 bits of data to be
stored in the Status Register. Since only bits 2, 3, and 7 can be
modified by WRSR instruction; therefore, it is recommended to
leave the bits 4-6 as ‘0’ while writing to the Status Register
Read Status Register (RDSR) Instruction
The RDSR instruction provides access to the status register.
This instruction is used to probe the Write Enable Status of the
device or the Ready status of the device. RDY bit is set by the
device to ‘1’ whenever a STORE or Software RECALL cycle is
in progress. The block protection and WPEN bits indicate the
extent of protection employed.
Note In CY14B101Q1/CY14B101Q2/CY14B101Q3, the values
written to Status Register are saved to nonvolatile memory only
after a STORE operation. If AutoStore is disabled (or while using
CY14B101Q1), any modifications to the Status Register must be
secured by performing a Software STORE operation.
This instruction is issued after the falling edge of CS using the
opcode for RDSR.
Write Status Register (WRSR) Instruction
The WRSR instruction enables the user to write to the Status
register. However, this instruction cannot be used to modify bit 0
and bit 1 (RDY and WEN). The BP0 and BP1 bits can be used
to select one of four levels of block protection. Further, WPEN bit
must be set to ‘1’ to enable the use of write protect (WP) pin.
Note CY14B101Q2 does not have WP pin. Any modification to
bit 7 of the Status register has no effect on the functionality of
CY14B101Q2.
Figure 7. Read Status Register (RDSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
1
MSB
LSB
HI-Z
SO
D4
D2
D7 D6 D5
MSB
D3
D1 D0
LSB
Data
Document Number: 001-50091 Rev. *P
Page 10 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Figure 8. Write Status Register (WRSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data in
Opcode
D2
D3
X
SI
1
D7
X
X
0
0
0
0
0
0
0
X
X
MSB
LSB
HI-Z
SO
Write Disable (WRDI) Instruction
Write Protection and Block Protection
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following the falling edge of CS followed
by opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
CY14B101Q1/CY14B101Q2/CY14B101Q3 provides features
for both software and hardware write protection using WRDI
instruction and WP. Additionally, this device also provides block
protection mechanism through BP0 and BP1 pins of the Status
Register.
The write enable and disable status of the device is indicated by
WEN bit of the status register. The write instructions (WRSR and
WRITE) and nvSRAM special instruction (STORE, RECALL,
ASENB, and ASDISB) need the write to be enabled (WEN
bit = 1) before they can be issued.
Figure 10. WRDI Instruction
CS
0
1
2
3
4
5
6
7
Write Enable (WREN) Instruction
SCK
SI
On power-up, the device is always in the write disable state. The
following WRITE, WRSR, or nvSRAM special instruction must
therefore be preceded by a Write Enable instruction. If the device
is not write enabled (WEN = ‘0’), it ignores the write instructions
and returns to the standby state when CS is brought HIGH. A
new CS falling edge is required to re-initiate serial communi-
cation. The instruction is issued following the falling edge of CS.
When this instruction is used, the WEN bit of status register is
set to ‘1’. WEN bit defaults to ‘0’ on power-up.
0
0
0
0
0
1
0
0
HI-Z
SO
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 5 shows the function of
block protect bits.
Note After completion of a write instruction (WRSR or WRITE)
or nvSRAM special instruction (STORE, RECALL, ASENB, and
ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to
provide protection from any inadvertent writes. Therefore,
WREN instruction must be used before a new write instruction is
issued.
Table 5. Block Write Protect Bits
StatusRegister
Figure 9. WREN Instruction
Bits
Level
Array Addresses Protected
CS
BP1
BP0
0
1
2
3
4
5
6
7
0
0
0
1
1
0
1
0
1
None
SCK
SI
1 (1/4)
2 (1/2)
3 (All)
0x18000–0x1FFFF
0x10000–0x1FFFF
0x00000–0x1FFFF
0
0
0
0
0
1
1
0
HI-Z
SO
Document Number: 001-50091 Rev. *P
Page 11 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
address. The Most Significant address byte contains A16 in bit 0
and other bits as ‘don’t cares’. Address bits A15 to A0 are sent
in the following two address bytes. After the last address bit is
transmitted on the SI pin, the data (D7-D0) at the specific
address is shifted out on the SO line on the falling edge of SCK
starting with D7. Any other data on SI line after the last address
bit is ignored.
Write Protect (WP) Pin
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the status register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This enables the user to install the device in a
system with the WP pin tied to ground, and still write to the status
register.
CY14B101Q1/CY14B101Q2/CY14B101Q3 allows reads to be
performed in bursts through SPI, which can be used to read
consecutive addresses without issuing a new READ instruction.
If only one byte is to be read, the CS line must be driven HIGH
after one byte of data comes out. However, the read sequence
may be continued by holding the CS line LOW and the address
is automatically incremented and data continues to shift out on
SO pin. When the last data memory address (0x1FFFF) is
reached, the address rolls over to 0x0000 and the device
continues to read.
WP pin can be used along with WPEN and block protect bits
(BP1 and BP0) of the status register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to status register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the status register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the status register.
Write Sequence (WRITE) instruction
The write operations on this device are performed through the SI
pin. To perform a write operation, if the device is write disabled,
then the device must first be write enabled through the WREN
instruction. When the writes are enabled (WEN = ‘1’), WRITE
instruction is issued after the falling edge of CS. A WRITE
instruction constitutes transmitting the WRITE opcode on SI line
followed by 3 bytes of address and the data (D7-D0) which is to
be written. The Most Significant address byte contains A16 in bit
0 with other bits being ‘don’t cares’. Address bits A15 to A0 are
sent in the following two address bytes.
Note CY14B101Q2 does not have WP pin and therefore does
not provide hardware write protection.
Table 6 summarizes all the protection features of this device.
Table 6. Write Protection Operation
Protected Unprotected
Status
WPEN WP WEN
Blocks
Blocks
Protected
Writable
Writable
Writable
Register
X
0
1
1
X
0
1
1
1
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
X
CY14B101Q1/CY14B101Q2/CY14B101Q3 enables writes to be
performed in bursts through SPI, which can be used to write
consecutive addresses without issuing a new WRITE instruction.
If only one byte is to be written, the CS line must be driven HIGH
after the D0 (LSB of data) is transmitted. However, if more bytes
are to be written, CS line must be held LOW and address is
incremented automatically. The following bytes on the SI line are
treated as data bytes and written in the successive addresses.
When the last data memory address (0x1FFFF) is reached, the
address rolls over to 0x0000 and the device continues to write.
The WEN bit is reset to ‘0’ on completion of a WRITE sequence.
LOW
HIGH
Memory Access
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the status register and the HSB pin.
Read Sequence (READ) instruction
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
The read operations on this device are performed by giving the
instruction on SI and reading the output on SO pin. The following
sequence needs to be followed for a read operation: After the CS
line is pulled LOW to select a device, the read opcode is
transmitted through the SI line followed by three bytes of
Figure 11. Read Instruction Timing
CS
0
1
0
1
2
3
4
5
6
7
2
3
4
5
6
7
20 21 22 23
0
1
2
3
4
5
6
7
SCK
Op-Code
17-bit Address
0 A16
SI
0
0
0
0
0
0
0
0
1
1
A3
A2 A1 A0
0
0
0
0
MSB
LSB
SO
D7 D6 D5 D4 D3
D2
D1
D0
MSB
LSB
Data
Document Number: 001-50091 Rev. *P
Page 12 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Figure 12. Burst Mode Read Instruction Timing
CS
20 21 22 23
0
1
0
1
2
3
4
5
6
7
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
2
3
4
5
6
7
7
SCK
Op-Code
17-bit Address
A16
1
1
0
0
0
0
0
0
0
A3 A2 A1 A0
SI
0
0
0
0
0
0
MSB
LSB
Data Byte N
Data Byte 1
SO
D7 D6 D5 D4
D0
D3 D2
D7 D0 D7 D6 D5 D4
D1
D3 D2 D1 D0
MSB
MSB
LSB
LSB
Figure 13. Write Instruction Timing
CS
0
1
0
1
2
3
4
5
7
2
3
4
5
6
7
20 21 22 23
0
1
2
3
4
5
6
7
6
SCK
Op-Code
17-bit Address
D4
D2
D1 D0
SI
0
0
D7 D6 D5
LSB
MSB
D3
0
0
0
0
0
0
1
0
A16
A3
A2 A1 A0
0
0
0
0
0
MSB
LSB
Data
HI-Z
SO
Figure 14. Burst Mode Write Instruction Timing
CS
22 23
20 21
0
1
0
1
2
3
4
5
6
7
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
2
3
4
5
6
7
7
SCK
Data Byte N
Data Byte 1
Op-Code
17-bit Address
A16
D7 D6 D5 D4
MSB
D7 D0 D7 D6 D5 D4
D3 D2
D3 D2
1
0
0
0
0
0
0
0
0
A3 A2 A1 A0
LSB
D1 D0
D1 D0
0
0
0
0
0
0
SI
MSB
LSB
HI-Z
SO
Table 7. nvSRAM Special Instructions
nvSRAM Special Instructions
Function Name
STORE
Opcode
0011 1100
0110 0000
Operation
Software STORE
Software RECALL
CY14B101Q1/CY14B101Q2/CY14B101Q3
provides
four
special instructions, which enables access to the nvSRAM
specific functions: STORE, RECALL, ASDISB, and ASENB.
Table 7 lists these instructions.
RECALL
ASENB
0101 1001 AutoStore Enable
0001 1001 AutoStore Disable
ASDISB
Document Number: 001-50091 Rev. *P
Page 13 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Software STORE (STORE) instruction
When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is performed
irrespective of whether a write has taken place since the last
STORE or RECALL operation.
Figure 17. AutoStore Enable Operation
CS
0
1
2
3
4
5
6
7
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the STORE
instruction.
SCK
SI
0
1
0
1
1
0
0
1
HI-Z
SO
Figure 15. Software STORE Operation
AutoStore Disable (ASDISB) instruction
AutoStore is enabled by default in CY14B101Q2/CY14B101Q3.
The ASDISB instruction disables the AutoStore. This setting is
not nonvolatile and needs to be followed by a STORE sequence
if this is desired to survive the power cycle.
CS
0
1
2
3
4
5
6
7
SCK
SI
To issue this instruction, the device must be write enabled
(WEN = ‘1’). The instruction is performed by transmitting the
ASDISB opcode on the SI pin following the falling edge of CS.
The WEN bit is cleared on the positive edge of CS following the
ASDISB instruction.
0
0
1
1
1
1
0
0
HI-Z
SO
Software RECALL (RECALL) instruction
Figure 18. AutoStore Disable Operation
When a RECALL instruction is executed, nvSRAM performs a
Software RECALL operation. To issue this instruction, the device
must be write enabled (WEN = ‘1’).
CS
0
1
2
3
4
5
6
7
The instruction is performed by transmitting the RECALL opcode
on the SI pin following the falling edge of CS. The WEN bit is
cleared on the positive edge of CS following the RECALL
instruction.
SCK
SI
0
0
0
1
1
0
0
1
HI-Z
Figure 16. Software RECALL Operation
SO
HOLD Pin Operation
CS
0
1
2
3
4
5
6
7
The HOLD pin is used to pause the serial communication. When
the device is selected and a serial sequence is underway, HOLD
is used to pause the serial communication with the master device
without resetting the ongoing serial sequence. To pause, the
HOLD pin must be brought LOW when the SCK pin is LOW. CS
pin must remain LOW along with HOLD pin to pause serial
communication. While the device serial communication is
paused, inputs to the SI pin are ignored and the SO pin is in the
high impedance state. To resume serial communication, the
HOLD pin must be brought HIGH when the SCK pin is LOW
(SCK may toggle during HOLD).
SCK
SI
0
1
1
0
0
0
0
0
HI-Z
SO
AutoStore Enable (ASENB) instruction
The AutoStore Enable instruction enables the AutoStore on
CY14B101Q1. This setting is not nonvolatile and needs to be
followed by a STORE sequence if this is desired to survive the
power cycle.
Figure 19. HOLD Operation
To issue this instruction, the device must be write enabled
(WEN = ‘1’). The instruction is performed by transmitting the
ASENB opcode on the SI pin following the falling edge of CS.
The WEN bit is cleared on the positive edge of CS following the
ASENB instruction.
CS
SCK
HOLD
SO
Note If ASDISB and ASENB instructions are executed in
CY14B101Q1, the device is busy for the duration of software
sequence processing time (tSS). However, ASDISB and ASENB
instructions have no effect on CY14B101Q1 as AutoStore is
internally disabled.
Document Number: 001-50091 Rev. *P
Page 14 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Transient voltage (<20 ns)
on any pin to ground potential ............ –2.0 V to VCC + 2.0 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Package power dissipation capability (TA = 25 °C) ..... 1.0 W
Surface mount lead soldering temperature
(3 Seconds) ............................................................. +260C
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
DC output current (1 output at a time, 1s duration) .... 15 mA
At 150 C ambient temperature ...................... 1000 h
At 85 C ambient temperature .................... 20 Years
Maximum junction temperature ................................. 150 C
Supply voltage on VCC relative to VSS .........–0.5 V to +4.1 V
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Operating Range
DC voltage applied to outputs
in High Z state ....................................–0.5 V to VCC + 0.5 V
Range
Industrial
Ambient Temperature
VCC
–40 C to +85 C
2.7 V to 3.6 V
Input voltage .......................................–0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
Description
Power supply voltage
Average Vcc current
Test Conditions
Min
2.7
–
Typ[4]
3.0
–
Max
3.6
10
Unit
V
ICC1
At fSCK = 40 MHz.
mA
Values obtained without output loads
(IOUT = 0 mA)
ICC2
ICC4
ISB
Average VCC current during
STORE
All inputs don’t care, VCC = Max.
Average current for duration tSTORE
–
–
–
–
–
–
10
5
mA
mA
mA
Average VCAP current during All inputs don’t care. Average current
AutoStore cycle
for duration tSTORE
VCC standby current
CS > (VCC – 0.2 V).
5
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after nonvolatile
cycle is complete.
Inputs are static. f = 0 MHz.
[5]
Input leakage current (except VCC = Max, VSS < VIN < VCC
HSB)
–1
–
+1
µA
IIX
Input leakage current (for HSB) VCC = Max, VSS < VIN < VCC
–100
–1
–
–
+1
+1
µA
µA
IOZ
Off state output leakage
current
VCC = Max, VSS < VOUT < VCC
VIH
VIL
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output LOW voltage
Storage capacitor
2.0
–
–
VCC + 0.5
V
V
VSS – 0.5
0.8
–
VOH
VOL
IOUT = –2 mA
2.4
–
–
V
IOUT = 4 mA
–
0.4
180
V
[6]
Between VCAP pin and VSS
61
68
µF
VCAP
[7, 8]
VVCAP
Maximum voltage driven on
VCC = Max
–
–
VCC
V
VCAP pin by the device
Notes
4. Typical values are at 25 °C, V = V (Typ). Not 100% tested.
CC
CC
5. The HSB pin has I
= -2 µA for V of 2.4 V when both active high and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
6. Min V value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor on
CAP
CAP
V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
CAP
is always recommended to use a capacitor within the specified min and max limits. See application note AN43593 for more details on V
options.
CAP
7. Maximum voltage on V
pin (V
) is provided for guidance when choosing the V
capacitor. The voltage rating of the V capacitor across the operating
CAP
VCAP
CAP
CAP
temperature range should be higher than the V
voltage.
VCAP
8. These parameters are guaranteed by design and are not tested.
Document Number: 001-50091 Rev. *P
Page 15 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Data Retention and Endurance
Over the Operating Range
Parameter
Description
Min
20
Unit
Years
K
DATAR
NVC
Data retention
Nonvolatile STORE operations
1,000
Capacitance
Parameter [9]
CIN
Description
Input capacitance
Test Conditions
Max
6
Unit
pF
TA = 25 C, f = 1 MHz, VCC = VCC(Typ)
COUT
Output pin capacitance
8
pF
Thermal Resistance
Parameter [9]
Description
Test Conditions
16-pin SOIC
8-pin DFN
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
55.17
17.7
C/W
JC
Thermal resistance
(junction to case)
2.64
18.8
C/W
AC Test Loads and Waveforms
Figure 20. AC Test Loads and Waveforms
577
R1
577
3.0 V
OUTPUT
3.0 V
OUTPUT
R1
R2
789
R2
789
5 pF
30 pF
AC Test Conditions
Input pulse levels ...................................................0 V to 3 V
Input rise and fall times (10%–90%) ............................ <3 ns
Input and output timing reference levels ....................... 1.5 V
Note
9. These parameters are guaranteed by design and are not tested.
Document Number: 001-50091 Rev. *P
Page 16 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
AC Switching Characteristics
Over the Operating Range
Parameters [10]
40 MHz
Description
Unit
Max
Cypress
Alt.
Min
Parameter Parameter
fSCK
tCL
fSCK
tWL
tWH
tCE
tCES
tCEH
tSU
tH
Clock frequency, SCK
Clock pulse width LOW
Clock pulse width HIGH
CS HIGH time
–
11
11
20
10
10
5
40
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCH
–
tCS
–
tCSS
tCSH
tSD
CS setup time
–
CS hold time
–
Data in setup time
Data in hold time
HOLD hold time
–
tHD
5
–
tHH
tHD
tCD
tV
5
–
tSH
HOLD setup time
Output valid
5
–
tCO
–
9
[11]
tHHZ
tHZ
tLZ
tHO
tDIS
HOLD to output High Z
HOLD to output Low Z
Output hold time
Output disable time
–
15
15
–
[11]
tHLZ
tOH
–
0
tHZCS
–
25
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V (Typ), and output loading of the specified
CC
CC
I
/I and load capacitance shown in Figure 20.
OL OH
11. These parameters are guaranteed by design and are not tested.
Document Number: 001-50091 Rev. *P
Page 17 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Switching Waveforms
Figure 21. Synchronous Data Timing (Mode 0)
t
CS
CS
t
t
t
CSS
CH
CL
t
CSH
SCK
t
t
SD
HD
SI
VALID IN
VALID IN
VALID IN
t
t
t
OH
HZCS
CO
HI-Z
HI-Z
SO
Figure 22. HOLD Timing
CS
SCK
t
t
HH
HH
t
t
SH
SH
HOLD
SO
t
t
HLZ
HHZ
Document Number: 001-50091 Rev. *P
Page 18 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
AutoStore or Power-Up RECALL
Over the Operating Range
CY14B101Q1/
CY14B101Q2/
CY14B101Q3
Parameter
Description
Unit
Min
Max
[12]
Power-Up RECALL duration
STORE cycle duration
–
20
8
ms
ms
ns
tFA
[13]
[14]
–
–
tSTORE
tDELAY
Time allowed to complete SRAM cycle
25
VSWITCH
Low voltage trigger level
VCC rise time
–
2.65
–
V
[15]
150
s
tVCCRISE
[15]
HSB output disable voltage
HSB high to nvSRAM active time
HSB high active time
–
–
–
1.9
5
V
VHDIS
[15]
s
ns
tLZHSB
[15]
500
tHHHD
Switching Waveforms
Figure 23. AutoStore or Power-Up RECALL[16]
VCC
VSWITCH
VHDIS
13
13
tVCCRISE
tSTORE
tSTORE
Note
Note
tHHHD
tHHHD
17
17
Note
Note
HSB OUT
AutoStore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tFA
tFA
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
AutoStore
POWER
DOWN
AutoStore
POWER-UP
RECALL
Notes
12. t starts from the time V rises above V
SWITCH.
FA
CC
13. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.
14. On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
15. These parameters are guaranteed by design and are not tested.
.
DELAY
16. Read and Write cycles are ignored during STORE, RECALL, and while V is below V
CC
SWITCH.
17. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-50091 Rev. *P
Page 19 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Software Controlled STORE and RECALL Cycles
Over the Operating Range
CY14B101Q1/
CY14B101Q2/
CY14B101Q3
Parameter
Description
Unit
Min
–
Max
tRECALL
RECALL duration
200
100
s
s
[18, 19]
tSS
Soft sequence processing time
–
Switching Waveforms
Figure 24. Software STORE Cycle[19]
Figure 25. Software RECALL Cycle[19]
CS
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
SCK
SI
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
t
t
RECALL
STORE
HI-Z
HI-Z
RWI
RDY
RWI
RDY
Figure 26. AutoStore Enable Cycle
Figure 27. AutoStore Disable Cycle
CS
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
SCK
SI
0
0
0
1
1
0
0
1
0
1
0
1
1
0
0
1
t
SS
t
SS
HI-Z
HI-Z
RWI
RDY
RWI
RDY
Notes
18. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
19. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document Number: 001-50091 Rev. *P
Page 20 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Hardware STORE Cycle
Over the Operating Range
CY14B101Q3
Parameter
Description
Unit
Min
Max
tPHSB
Hardware STORE pulse width
15
–
ns
Switching Waveforms
Figure 28. Hardware STORE Cycle [20]
Write Latch set
t
PHSB
HSB (IN)
t
STORE
t
t
HHHD
DELAY
HSB (OUT)
RWI
t
LZHSB
Write Latch not set
t
PHSB
HSB (IN)
HSB pin is driven HIGH to V
only by Internal
CC
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
HSB (OUT)
RWI
t
DELAY
Note
20. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-50091 Rev. *P
Page 21 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Ordering Information
Ordering Code
CY14B101Q2-LHXI
Package Diagram
Package Type
Operating Range
001-50671
8-pin DFN (With VCAP
)
Industrial
All the above parts are Pb-free.
Ordering Code Definitions
CY 14 B 101 Q 2-SF X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (–40 to 85 °C)
Pb-free
Package:
SF - 16 SOIC
LH - 8 DFN
1 - With WP
2 - With VCAP
3 - With VCAP, WP and HSB
Q - Serial SPI nvSRAM
Density:
101 - 1 Mb
Voltage:
B - 3.0 V
14 - nvSRAM
Cypress
Document Number: 001-50091 Rev. *P
Page 22 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Package Diagrams
Figure 29. 8-pin DFN (5 × 6 × 0.85 mm) Package Outline, 001-50671
001-50671 *E
Document Number: 001-50091 Rev. *P
Page 23 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Package Diagrams (continued)
Figure 30. 16-pin SOIC (0.413 × 0.299 × 0.0932 inches) Package Outline, 51-85022
51-85022 *E
Document Number: 001-50091 Rev. *P
Page 24 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CPHA
CPOL
DFN
Clock Phase
Symbol
°C
Unit of Measure
Clock Polarity
degree Celsius
hertz
Hz
kHz
K
Mbit
MHz
A
F
s
Dual Flat No-lead
kilohertz
kilohm
EEPROM Electrically Erasable Programmable Read-Only
Memory
EIA
Electronic Industries Alliance
Input/Output
megabit
I/O
megahertz
microampere
microfarad
microsecond
milliampere
millisecond
nanosecond
ohm
JEDEC
LSB
Joint Electron Devices Engineering Council
Least Significant Bit
MSB
Most Significant Bit
mA
ms
ns
nvSRAM
RWI
non-volatile Static Random Access Memory
Read and Write Inhibit
RoHS
SPI
Restriction of Hazardous Substances
Serial Peripheral Interface
%
percent
SONOS
SOIC
SRAM
Silicon-Oxide-Nitride-Oxide Semiconductor
Small Outline Integrated Circuit
Static Random Access Memory
pF
V
picofarad
volt
W
watt
Document Number: 001-50091 Rev. *P
Page 25 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Document History Page
Document Title: CY14B101Q1/CY14B101Q2/CY14B101Q3, 1-Mbit (128K × 8) Serial SPI nvSRAM
Document Number: 001-50091
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
**
2607408
GSIN /
GVCH /
AESA
12/19/2008 New data sheet.
*A
2654487
GVCH /
PYRS
02/04/2009 Changed status from Advance information to Preliminary.
Updated Document Title to read as
“CY14B101Q1/CY14B101Q2/CY14B101Q3, 1-MBit (128K x 8) Serial SPI
nvSRAM”.
Changed part number from CY14B101QxA to CY14B101Qx in all instances
across the document.
Updated Pin Definitions:
Updated details in “Description” column corresponding to VCAP pin.
Updated Device Operation:
Updated description.
Updated Serial Peripheral Interface:
Updated description.
Updated Status Register:
Updated description.
Updated Table 3.
Updated DC Electrical Characteristics:
Changed maximum value of ICC2 parameter from 5 mA to 10 mA.
Updated Ordering Information:
Updated part numbers.
*B
2733293
GVCH /
AESA
07/08/2009 Corrected typo error in the Document History Page (Description of change)
Updated Pinouts:
Updated Note 2 and Note 3 (Fixed typo error)
Updated Device Operation:
Updated AutoStore Operation:
Updated description.
Updated DC Electrical Characteristics:
Updated details in “Test Conditions” column corresponding to ICC1 and ISB
parameters.
Updated AutoStore or Power-Up RECALL:
Updated details in “Description” column corresponding to VHDIS parameter.
*C
*D
2757348
2839453
GVCH
08/28/2009 Changed status from Preliminary to Final.
Removed Commercial Temperature Range related information in all instances
across the document.
Updated Memory Access:
Updated Write Sequence (WRITE) instruction:
Updated description (Added Note at the end).
Updated Thermal Resistance:
Added values 16-pin SOIC and 8-pin DFN packages.
GVCH /
PYRS
01/06/2010 Updated Features:
Replaced “200,000 STORE cycles to QuantumTrap” with “1 Million STORE
cycles to QuantumTrap”.
Updated Device Operation:
Updated AutoStore Operation:
Updated Figure 3.
Document Number: 001-50091 Rev. *P
Page 26 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Document History Page (continued)
Document Title: CY14B101Q1/CY14B101Q2/CY14B101Q3, 1-Mbit (128K × 8) Serial SPI nvSRAM
Document Number: 001-50091
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
*E
2894833
GVCH
03/17/2010 Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 001-50671 – Changed revision from *A to *B.
spec 51-85022 – Changed revision from *B to *C.
Updated to new template.
*F
*G
*H
2910569
3037045
3134300
BTK /
GVCH
04/12/2010 Updated Pinouts:
Updated Figure 1 (to show the pad in the pin diagrams).
Updated Pin Definitions:
Added “EXPOSED PAD” and its corresponding details.
Updated SPI Operating Features:
Updated Power-On Reset:
Updated description (Added status of bits 4–6).
Updated Power-Down:
Updated description.
Updated Status Register:
Updated Table 4:
Added “Bits 4–6” and its details.
Updated Switching Waveforms:
Updated Figure 21.
Updated Figure 22.
Updated Switching Waveforms:
Updated Figure 23
Updated Note 17.
Updated Hardware STORE Cycle:
Removed tDHSB parameter and its details.
Updated Switching Waveforms:
Updated Figure 28.
GVCH
10/09/2010 Changed ground naming convention from GND to VSS in all instances across
the document.
Updated SPI Operating Features:
Updated Power-On Reset:
Updated description.
Updated Power-Down:
Updated description.
Updated Status Register:
Updated Write Status Register (WRSR) Instruction:
Updated Figure 8.
Updated Memory Access:
Updated HOLD Pin Operation:
Updated description.
Updated Figure 19 (to indicate that CS pin must remain LOW along with HOLD
pin to pause serial communication).
Updated Switching Waveforms:
Updated Figure 22 (to indicate that CS pin must remain LOW along with HOLD
pin to pause serial communication).
Updated Switching Waveforms:
Added Figure 26.
Added Figure 27.
Added Acronyms and Units of Measure.
GVCH
01/11/2011 Updated Device Operation:
Updated Hardware STORE and HSB Pin Operation:
Updated description (Added more clarity on HSB pin operation).
Updated AutoStore or Power-Up RECALL:
Updated details in “Description” column of tLZHSB parameter.
Document Number: 001-50091 Rev. *P
Page 27 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Document History Page (continued)
Document Title: CY14B101Q1/CY14B101Q2/CY14B101Q3, 1-Mbit (128K × 8) Serial SPI nvSRAM
Document Number: 001-50091
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
*I
3320877
GVCH
GVCH
GVCH
07/19/2011 Updated DC Electrical Characteristics:
Added Note 6 and referred the same note in VCAP parameter.
Updated AC Switching Characteristics:
Added Note 10 and referred the same note in “Parameters” column.
*J
3493427
3665165
01/13/2012 Updated Package Diagrams:
spec 001-50671 – Changed revision from *B to *C.
spec 51-85022 – Changed revision from *C to *D.
Completing Sunset Review.
*K
08/03/2012 Updated Maximum Ratings (Changed “Ambient temperature with power
applied” to “Maximum junction temperature”).
Updated DC Electrical Characteristics (Added VVCAP parameter and its details,
added Note 7 and referred the same note in VVCAP parameter, also referred
Note 8 in VVCAP parameter).
*L
4010138
GVCH
05/24/2013 Added watermark “Not Recommended for New Designs” across the document.
Updated Package Diagrams:
spec 51-85022 – Changed revision from *D to *E.
*M
*N
*O
*P
4445267
4563189
4617542
6028188
GVCH
GVCH
GVCH
GVCH
07/17/2014 Removed watermark “Not Recommended for New Designs” across the
document.
11/06/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
01/08/2015 No technical updates.
Completing Sunset Review.
01/12/2018 Updated Package Diagrams:
spec 001-50671 – Changed revision from *C to *E.
Updated to new template.
Completing Sunset Review.
Document Number: 001-50091 Rev. *P
Page 28 of 29
CY14B101Q1
CY14B101Q2
CY14B101Q3
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2008-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-50091 Rev. *P
Revised January 12, 2018
Page 29 of 29
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