CHL8228G-00CRTY [INFINEON]
Digital Multi-Phase Buck Controller; 数字多相降压控制器型号: | CHL8228G-00CRTY |
厂家: | Infineon |
描述: | Digital Multi-Phase Buck Controller |
文件: | 总3页 (文件大小:346K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Digital Multi-Phase Buck Controller
CHL8225G/8G
FEATURES
DESCRIPTION
5-phase & 8-phase dual output PWM Controller
The CHL8225G/8G are dual-loop, digital multi-phase buck
controllers. The CHL8225G drives up to 5 phases and the
CHL8228G drives up to 8 phases. They feature Input
Voltage Management allowing up to 3 input voltages to be
monitored to ensure adequate power is delivered to the
load. Dynamic voltage control is provided by 4 registers
which are programmed through I2C/SMBus/PMBus and
then selected using a 2-bit parallel bus for fast access.
with phases flexibly assigned between Loops 1 & 2
Dynamic voltage control by 2-bit parallel interface
with Gamer Mode override and Vmax setting
Input Voltage Management for up to 3 Input
Voltages
ICRITICAL Monitor and Phase Current Capture Mode
Phase Switching frequency from 200kHz to 1.2MHz
The CHL8225G/8G includes the IR Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. IR Variable Gate Drive
optimizes the MOSFET gate drive voltage as a function of
real-time load current. IR Dynamic Phase Control adds and
drops phases based upon load current. The CHL8225G/8G
can be configured to enter 1-phase operation and active
diode emulation based upon load current or by command.
IR Efficiency Shaping Features including Variable
Gate Drive, Dynamic Phase Control
Programmable 1-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
IR Adaptive Transient Algorithm (ATA) minimizes
output bulk capacitors and system cost
Per-Loop Fault Protection: OVP, UVP, OCP, OTP
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors.
I2C/SMBus/PMBus system interface for telemetry of
Temperature, Voltage, Current & Power for both
loops
The I2C/PMBus interface can communicate with up to 16
CHL8225G/8G-based VR loops. Device configuration and
fault parameters are defined using the IR Digital Power
Design Center (DPDC) GUI and stored in on-chip NVM.
Non-Volatile Memory (NVM) for custom
configuration
Compatible with IR ATL and 3.3V tri-state Drivers
+3.3V supply voltage; 0ºC to 85ºC ambient
operation
The CHL8225G/8G provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based
temperature sensing with VRHOT signal. The CHL8225G/8G
includes numerous features like register diagnostics for
fast design cycles and platform differentiation, simplifying
VRD design and enabling fastest time-to-market with its
“set-and-forget” methodology.
Pb-Free, RoHS, 6x6 40-pin & 8x8 56-pin QFN, MSL2
package
APPLICATIONS
Multiphase GPU systems
PIN DIAGRAM
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
2
42
41
40
39
38
37
ISEN7
ISEN8
RCSP
RCSP_L2
RCSM_L2
VCC
40
39
38
37
36
35
34
33
32
31
3
RCSM
1
2
30
29
28
27
26
25
24
23
22
21
RCSP_L2
RCSM_L2
VCC
RCSP
RCSM
4
VCC
5
VRHOT2
VSEN
VSEN_L2
VRTN_L2
3
VCC
6
4
VSEN_L2
VRTN_L2
PWM5
VSEN
CHL8228G
7
36 PWM8
VRTN
56 Pin 8x8 QFN
Top View
CHL8225G
5
8
35
VRTN
RRES
PWM7
40 Pin 6x6 QFN
Top View
9
34
33
32
31
30
29
TSEN
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
6
RRES
10
11
V18A
7
PWM4
TSEN
VR_READY_L1
8
PWM3
V18A
VR_READY_L2 12
PWM2
9
VR_READY_L1
VR_READY_L2
41 GND
13
14
EN_L2
PWM1
57 GND
10
VINSEN
11
12
13
14
15
16
17
18
19
20
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Figure 1: CHL8225G Package Top View
Figure 2: CHL8228G Package Top View
1
June 21, 2013 | FINAL | V1.12
Digital Multi-Phase Buck Controller
CHL8225G/8G
ORDERING INFORMATION
CHL822 G ―
Package
QFN
Packing Qty
Part Number
CHL8225G-00CRT
CHL8225G-00CRTY
CHL8225G-xxCRT1
T=3000
TY=4900
T – Tape & Reel / TY - Tray
QFN
T=3000
R – Package Type (QFN)
CHL8228G-00CRT
CHL8228G-00CRTY
CHL8228G-xxCRT1
T=3000
TY=2600
QFN
C – Operating Temperature
(Commercial Standard)
QFN
T=3000
xx – Configuration File
Notes:
1. “xx” indicates customer specific configuration file.
Part Number
5: CHL8225G
8: CHL8228G
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
2
42
41
40
39
38
37
ISEN7
ISEN8
RCSP
40
39
38
37
36
35
34
33
32
31
RCSP_L2
RCSM_L2
VCC
1
2
30
29
28
27
26
25
24
23
22
21
RCSP_L2
RCSM_L2
VCC
RCSP
RCSM
3
RCSM
4
VCC
5
VRHOT2
VSEN
VSEN_L2
VRTN_L2
3
VCC
6
4
VSEN_L2
VRTN_L2
PWM5
VSEN
CHL8228G
56 Pin 8x8 QFN
Top View
7
36 PWM8
VRTN
CHL8225G
5
VRTN
8
35
RRES
PWM7
40 Pin 6x6 QFN
Top View
6
RRES
9
34
33
32
31
30
29
TSEN
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
10
11
12
13
14
V18A
7
PWM4
TSEN
VR_READY_L1
VR_READY_L2
EN_L2
PWM3
8
V18A
PWM2
9
VR_READY_L1
VR_READY_L2
41 GND
57 GND
PWM1
10
VINSEN
11
12
13
14
15
16
17
18
19
20
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Figure 4: CHL8228G Top View Enlarged
Figure 3: CHL8225G Top View Enlarged
2
June 21, 2013 | FINAL | V1.12
Digital Multi-Phase Buck Controller
CHL8225G/8G
FUNCTIONAL BLOCK DIAGRAM
V18A
VCC
LDO
RCSP_L2
VID_2
RSCM_L2
1.8V
AFE_2
VSEN_L2
VRTN_L2
ITOT_2
Vout1_Error
Voltage
ADC
PWM1
PWM2
PWM3
PWM4
RCSP
RSCM
Vout2_Error
AFE_1
VSEN
VRTN
VID_1
ISEN1
Mode Control
PWM Generator
IP1
IRTN1
.
.
.
.
.
.
PWM5
PWM6
.
.
.
Phase_
Period_1
Control
and
Monitoring
ISENx
IRTNx
IPx
Phase_
Period_2
Only for
CHL8228G
ITOT_1
Σ
PWM7
PWM8
CHL8225G CHL8228G
x
y
z
3
4
5
4
5
8
Iout
Vin
ISENy
VAR_GATE
IPy
IRTNy
.
.
.
.
.
.
.
.
.
ITOT_2
Vout
ISENz
IRTNz
Temp
IPz
Current ADC
Σ
Fault Bus
System Clock
IP1
.
.
.
IP5
System Clock
ADC Clocks
IP6
.
.
.
Only for
CHL8228G
IP8
MUX Clocks
Phase_Period_1
TSEN2
(CHL8228G only)
Phase_Period_2
VID_1
TSEN
VID_2
VINSEN
Monitor ADC
Iout
Vin
Reference,
Oscillator,
State Control,
Interfaces,
Registers and
NVM
VINSEN_AUX1
VINSEN_AUX2
(CHL8228G only)
Temp
Fault Bus
V3_3
EN
VIDSEL1
VIDSEL0
SMB_DIO
SMB_CLK
VRHOT_ICRIT#
VR_READY_L1
VR_READY_L2
VIDSEL0_L2
VIDSEL1_L2
Only for
CHL8228G
VRHOT2
EN_L2
VMAX RRES
VBOOT
Only for CHL8228G
Figure 5: CHL8225G & CHL8228G Functional Block Diagram
June 21, 2013 | FINAL | V1.12
3
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